| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1459464713 | Feb 08 08:27:19 AM UTC 25 | Feb 08 08:28:47 AM UTC 25 | 3692631415 ps | ||
| T252 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1773261268 | Feb 08 08:27:45 AM UTC 25 | Feb 08 08:28:56 AM UTC 25 | 2966560863 ps | ||
| T253 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3485307320 | Feb 08 08:27:30 AM UTC 25 | Feb 08 08:28:57 AM UTC 25 | 3668745474 ps | ||
| T254 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.2318876358 | Feb 08 08:28:08 AM UTC 25 | Feb 08 08:29:00 AM UTC 25 | 2146667567 ps | ||
| T255 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2472984113 | Feb 08 08:28:31 AM UTC 25 | Feb 08 08:29:02 AM UTC 25 | 1270927903 ps | ||
| T256 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3764033774 | Feb 08 08:28:00 AM UTC 25 | Feb 08 08:29:07 AM UTC 25 | 2798902190 ps | ||
| T257 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3298598833 | Feb 08 08:28:19 AM UTC 25 | Feb 08 08:29:08 AM UTC 25 | 2026656998 ps | ||
| T258 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.778061472 | Feb 08 08:28:06 AM UTC 25 | Feb 08 08:29:19 AM UTC 25 | 3036228222 ps | ||
| T259 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2665413582 | Feb 08 08:28:11 AM UTC 25 | Feb 08 08:29:19 AM UTC 25 | 2826195820 ps | ||
| T260 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.490202467 | Feb 08 08:28:48 AM UTC 25 | Feb 08 08:29:24 AM UTC 25 | 1450668620 ps | ||
| T261 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.4230139650 | Feb 08 08:28:58 AM UTC 25 | Feb 08 08:29:24 AM UTC 25 | 1023308781 ps | ||
| T262 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3537241614 | Feb 08 08:29:01 AM UTC 25 | Feb 08 08:29:25 AM UTC 25 | 958908075 ps | ||
| T263 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.225877911 | Feb 08 08:28:43 AM UTC 25 | Feb 08 08:29:27 AM UTC 25 | 1825391127 ps | ||
| T264 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2790074947 | Feb 08 08:28:43 AM UTC 25 | Feb 08 08:29:33 AM UTC 25 | 2058637662 ps | ||
| T265 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1528851252 | Feb 08 08:29:08 AM UTC 25 | Feb 08 08:29:34 AM UTC 25 | 1048961695 ps | ||
| T266 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.838873210 | Feb 08 08:28:30 AM UTC 25 | Feb 08 08:29:36 AM UTC 25 | 2771612568 ps | ||
| T267 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.3018484030 | Feb 08 08:28:20 AM UTC 25 | Feb 08 08:29:38 AM UTC 25 | 3247858729 ps | ||
| T268 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.27081882 | Feb 08 08:29:09 AM UTC 25 | Feb 08 08:29:51 AM UTC 25 | 1728247606 ps | ||
| T269 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.2183754014 | Feb 08 08:28:48 AM UTC 25 | Feb 08 08:29:58 AM UTC 25 | 2945695796 ps | ||
| T270 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1262510263 | Feb 08 08:29:39 AM UTC 25 | Feb 08 08:30:02 AM UTC 25 | 911569125 ps | ||
| T271 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2077734921 | Feb 08 08:29:29 AM UTC 25 | Feb 08 08:30:04 AM UTC 25 | 1429181171 ps | ||
| T272 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.2905769166 | Feb 08 08:29:24 AM UTC 25 | Feb 08 08:30:04 AM UTC 25 | 1624815102 ps | ||
| T273 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1001490805 | Feb 08 08:29:20 AM UTC 25 | Feb 08 08:30:04 AM UTC 25 | 1813195848 ps | ||
| T274 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2937765354 | Feb 08 08:29:52 AM UTC 25 | Feb 08 08:30:19 AM UTC 25 | 1068478405 ps | ||
| T275 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.566854661 | Feb 08 08:29:03 AM UTC 25 | Feb 08 08:30:20 AM UTC 25 | 3256467081 ps | ||
| T276 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2473489731 | Feb 08 08:28:57 AM UTC 25 | Feb 08 08:30:24 AM UTC 25 | 3656627717 ps | ||
| T277 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3239259143 | Feb 08 08:29:20 AM UTC 25 | Feb 08 08:30:26 AM UTC 25 | 2739591821 ps | ||
| T278 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.4115133957 | Feb 08 08:29:34 AM UTC 25 | Feb 08 08:30:29 AM UTC 25 | 2296175576 ps | ||
| T279 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2838065172 | Feb 08 08:29:25 AM UTC 25 | Feb 08 08:30:44 AM UTC 25 | 3286369965 ps | ||
| T280 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.4034143570 | Feb 08 08:30:05 AM UTC 25 | Feb 08 08:30:45 AM UTC 25 | 1638295060 ps | ||
| T281 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1807328197 | Feb 08 08:29:25 AM UTC 25 | Feb 08 08:30:47 AM UTC 25 | 3430590684 ps | ||
| T282 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1373401719 | Feb 08 08:30:03 AM UTC 25 | Feb 08 08:30:47 AM UTC 25 | 1812992549 ps | ||
| T283 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.204830797 | Feb 08 08:29:37 AM UTC 25 | Feb 08 08:30:51 AM UTC 25 | 3094237736 ps | ||
| T284 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4180241505 | Feb 08 08:30:26 AM UTC 25 | Feb 08 08:30:56 AM UTC 25 | 1160506856 ps | ||
| T285 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1412312519 | Feb 08 08:29:35 AM UTC 25 | Feb 08 08:30:58 AM UTC 25 | 3501940033 ps | ||
| T286 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3774791973 | Feb 08 08:30:05 AM UTC 25 | Feb 08 08:31:01 AM UTC 25 | 2280034045 ps | ||
| T287 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1969690762 | Feb 08 08:30:30 AM UTC 25 | Feb 08 08:31:08 AM UTC 25 | 1537559790 ps | ||
| T288 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.4175985872 | Feb 08 08:29:59 AM UTC 25 | Feb 08 08:31:15 AM UTC 25 | 3178768814 ps | ||
| T289 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1162827727 | Feb 08 08:30:20 AM UTC 25 | Feb 08 08:31:18 AM UTC 25 | 2422007411 ps | ||
| T290 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.154040016 | Feb 08 08:30:48 AM UTC 25 | Feb 08 08:31:19 AM UTC 25 | 1193243421 ps | ||
| T291 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.308635068 | Feb 08 08:30:21 AM UTC 25 | Feb 08 08:31:22 AM UTC 25 | 2537391688 ps | ||
| T292 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.976804321 | Feb 08 08:30:48 AM UTC 25 | Feb 08 08:31:27 AM UTC 25 | 1532533387 ps | ||
| T293 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3447897075 | Feb 08 08:30:57 AM UTC 25 | Feb 08 08:31:32 AM UTC 25 | 1371785447 ps | ||
| T294 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3015898844 | Feb 08 08:30:05 AM UTC 25 | Feb 08 08:31:32 AM UTC 25 | 3670075355 ps | ||
| T295 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2532768569 | Feb 08 08:31:02 AM UTC 25 | Feb 08 08:31:34 AM UTC 25 | 1280764314 ps | ||
| T296 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1246408944 | Feb 08 08:30:25 AM UTC 25 | Feb 08 08:31:39 AM UTC 25 | 3065818568 ps | ||
| T297 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3955683509 | Feb 08 08:31:19 AM UTC 25 | Feb 08 08:31:39 AM UTC 25 | 772330829 ps | ||
| T298 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.1732301126 | Feb 08 08:30:46 AM UTC 25 | Feb 08 08:31:49 AM UTC 25 | 2589010559 ps | ||
| T299 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1086026146 | Feb 08 08:30:45 AM UTC 25 | Feb 08 08:31:56 AM UTC 25 | 2936257583 ps | ||
| T300 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1987687793 | Feb 08 08:30:51 AM UTC 25 | Feb 08 08:32:01 AM UTC 25 | 2899512545 ps | ||
| T301 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.267419391 | Feb 08 08:31:27 AM UTC 25 | Feb 08 08:32:03 AM UTC 25 | 1428883398 ps | ||
| T302 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2403358774 | Feb 08 08:31:35 AM UTC 25 | Feb 08 08:32:15 AM UTC 25 | 1647944349 ps | ||
| T303 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4289256227 | Feb 08 08:31:09 AM UTC 25 | Feb 08 08:32:19 AM UTC 25 | 2916847599 ps | ||
| T304 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.880452021 | Feb 08 08:31:33 AM UTC 25 | Feb 08 08:32:20 AM UTC 25 | 1919765281 ps | ||
| T305 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3502036856 | Feb 08 08:30:58 AM UTC 25 | Feb 08 08:32:24 AM UTC 25 | 3576528295 ps | ||
| T306 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.4070731778 | Feb 08 08:31:56 AM UTC 25 | Feb 08 08:32:28 AM UTC 25 | 1273501925 ps | ||
| T307 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2680916341 | Feb 08 08:31:40 AM UTC 25 | Feb 08 08:32:31 AM UTC 25 | 2108986043 ps | ||
| T308 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1779956324 | Feb 08 08:31:17 AM UTC 25 | Feb 08 08:32:32 AM UTC 25 | 3141323565 ps | ||
| T309 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.2227231028 | Feb 08 08:31:23 AM UTC 25 | Feb 08 08:32:33 AM UTC 25 | 2912978688 ps | ||
| T310 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3609252211 | Feb 08 08:31:20 AM UTC 25 | Feb 08 08:32:33 AM UTC 25 | 3059101127 ps | ||
| T311 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.3575623306 | Feb 08 08:32:02 AM UTC 25 | Feb 08 08:32:39 AM UTC 25 | 1487705185 ps | ||
| T312 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2638905833 | Feb 08 08:32:32 AM UTC 25 | Feb 08 08:32:54 AM UTC 25 | 828088350 ps | ||
| T313 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.503766339 | Feb 08 08:32:33 AM UTC 25 | Feb 08 08:32:54 AM UTC 25 | 839100670 ps | ||
| T314 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2572587827 | Feb 08 08:32:21 AM UTC 25 | Feb 08 08:32:54 AM UTC 25 | 1327817508 ps | ||
| T315 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1625956677 | Feb 08 08:32:29 AM UTC 25 | Feb 08 08:32:54 AM UTC 25 | 990196671 ps | ||
| T316 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4275353142 | Feb 08 08:31:33 AM UTC 25 | Feb 08 08:32:57 AM UTC 25 | 3502673558 ps | ||
| T317 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.2005960122 | Feb 08 08:31:49 AM UTC 25 | Feb 08 08:32:59 AM UTC 25 | 2913341986 ps | ||
| T318 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1954546985 | Feb 08 08:31:40 AM UTC 25 | Feb 08 08:33:03 AM UTC 25 | 3466069140 ps | ||
| T319 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1530601093 | Feb 08 08:32:16 AM UTC 25 | Feb 08 08:33:04 AM UTC 25 | 1983655891 ps | ||
| T320 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2131779191 | Feb 08 08:32:40 AM UTC 25 | Feb 08 08:33:05 AM UTC 25 | 1009115481 ps | ||
| T321 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2402262777 | Feb 08 08:32:35 AM UTC 25 | Feb 08 08:33:05 AM UTC 25 | 1236461044 ps | ||
| T322 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.283931961 | Feb 08 08:32:25 AM UTC 25 | Feb 08 08:33:16 AM UTC 25 | 2124630617 ps | ||
| T323 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2475320052 | Feb 08 08:32:55 AM UTC 25 | Feb 08 08:33:28 AM UTC 25 | 1317440833 ps | ||
| T324 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2720388121 | Feb 08 08:32:04 AM UTC 25 | Feb 08 08:33:31 AM UTC 25 | 3709710977 ps | ||
| T325 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.725455740 | Feb 08 08:32:55 AM UTC 25 | Feb 08 08:33:36 AM UTC 25 | 1676034826 ps | ||
| T326 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.93994237 | Feb 08 08:32:20 AM UTC 25 | Feb 08 08:33:37 AM UTC 25 | 3216493564 ps | ||
| T327 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1908677418 | Feb 08 08:33:17 AM UTC 25 | Feb 08 08:33:44 AM UTC 25 | 1042278584 ps | ||
| T328 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.785012427 | Feb 08 08:32:54 AM UTC 25 | Feb 08 08:33:50 AM UTC 25 | 2319214048 ps | ||
| T329 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3267465792 | Feb 08 08:33:04 AM UTC 25 | Feb 08 08:33:54 AM UTC 25 | 2050016169 ps | ||
| T330 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.341079304 | Feb 08 08:32:34 AM UTC 25 | Feb 08 08:33:55 AM UTC 25 | 3401737602 ps | ||
| T331 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1005766787 | Feb 08 08:32:58 AM UTC 25 | Feb 08 08:34:05 AM UTC 25 | 2822770380 ps | ||
| T332 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.218123997 | Feb 08 08:33:06 AM UTC 25 | Feb 08 08:34:08 AM UTC 25 | 2550898428 ps | ||
| T333 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.183709449 | Feb 08 08:33:50 AM UTC 25 | Feb 08 08:34:12 AM UTC 25 | 819404463 ps | ||
| T334 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1262782359 | Feb 08 08:32:55 AM UTC 25 | Feb 08 08:34:17 AM UTC 25 | 3440819962 ps | ||
| T335 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1054079547 | Feb 08 08:33:05 AM UTC 25 | Feb 08 08:34:21 AM UTC 25 | 3169221457 ps | ||
| T336 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3595754267 | Feb 08 08:33:06 AM UTC 25 | Feb 08 08:34:24 AM UTC 25 | 3240741786 ps | ||
| T337 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1820554750 | Feb 08 08:33:00 AM UTC 25 | Feb 08 08:34:29 AM UTC 25 | 3737241555 ps | ||
| T338 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.291844856 | Feb 08 08:33:54 AM UTC 25 | Feb 08 08:34:42 AM UTC 25 | 1893137534 ps | ||
| T339 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3670199588 | Feb 08 08:33:37 AM UTC 25 | Feb 08 08:34:43 AM UTC 25 | 2739556639 ps | ||
| T340 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.942095202 | Feb 08 08:34:25 AM UTC 25 | Feb 08 08:34:45 AM UTC 25 | 768869181 ps | ||
| T341 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3469671378 | Feb 08 08:33:33 AM UTC 25 | Feb 08 08:34:46 AM UTC 25 | 3043238126 ps | ||
| T342 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.4163524662 | Feb 08 08:34:13 AM UTC 25 | Feb 08 08:34:51 AM UTC 25 | 1547657543 ps | ||
| T343 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.796052973 | Feb 08 08:34:30 AM UTC 25 | Feb 08 08:34:55 AM UTC 25 | 975990166 ps | ||
| T344 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1195589398 | Feb 08 08:33:29 AM UTC 25 | Feb 08 08:34:55 AM UTC 25 | 3621797551 ps | ||
| T345 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3695814225 | Feb 08 08:33:38 AM UTC 25 | Feb 08 08:34:57 AM UTC 25 | 3238258488 ps | ||
| T346 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4045004967 | Feb 08 08:33:56 AM UTC 25 | Feb 08 08:34:57 AM UTC 25 | 2460239873 ps | ||
| T347 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2132760049 | Feb 08 08:34:22 AM UTC 25 | Feb 08 08:35:02 AM UTC 25 | 1599952959 ps | ||
| T348 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.1992145503 | Feb 08 08:33:45 AM UTC 25 | Feb 08 08:35:03 AM UTC 25 | 3245816263 ps | ||
| T349 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.1770115992 | Feb 08 08:34:09 AM UTC 25 | Feb 08 08:35:19 AM UTC 25 | 2944062907 ps | ||
| T350 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3329291550 | Feb 08 08:34:06 AM UTC 25 | Feb 08 08:35:26 AM UTC 25 | 3340361145 ps | ||
| T351 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1621580087 | Feb 08 08:34:18 AM UTC 25 | Feb 08 08:35:28 AM UTC 25 | 2916074132 ps | ||
| T352 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3894910144 | Feb 08 08:35:03 AM UTC 25 | Feb 08 08:35:31 AM UTC 25 | 1124715380 ps | ||
| T353 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.572061905 | Feb 08 08:34:56 AM UTC 25 | Feb 08 08:35:35 AM UTC 25 | 1622481106 ps | ||
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| T454 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.710334829 | Feb 08 08:41:40 AM UTC 25 | Feb 08 08:42:03 AM UTC 25 | 861374290 ps | ||
| T455 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2070141515 | Feb 08 08:41:37 AM UTC 25 | Feb 08 08:42:03 AM UTC 25 | 1042985556 ps | ||
| T456 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.797092440 | Feb 08 08:41:41 AM UTC 25 | Feb 08 08:42:03 AM UTC 25 | 890997319 ps | ||
| T457 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2242149620 | Feb 08 08:41:13 AM UTC 25 | Feb 08 08:42:04 AM UTC 25 | 2102379876 ps | ||
| T458 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1235680627 | Feb 08 08:41:34 AM UTC 25 | Feb 08 08:42:06 AM UTC 25 | 1334645827 ps | ||
| T459 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1885973091 | Feb 08 08:41:33 AM UTC 25 | Feb 08 08:42:06 AM UTC 25 | 1365024688 ps | ||
| T460 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.695666261 | Feb 08 08:41:03 AM UTC 25 | Feb 08 08:42:06 AM UTC 25 | 2708082982 ps | ||
| T461 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3545560886 | Feb 08 08:41:39 AM UTC 25 | Feb 08 08:42:06 AM UTC 25 | 1076341393 ps | ||
| T462 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2991985033 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:42:07 AM UTC 25 | 974968122 ps | ||
| T463 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2850560606 | Feb 08 08:41:44 AM UTC 25 | Feb 08 08:42:08 AM UTC 25 | 918391484 ps | ||
| T464 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.154548857 | Feb 08 08:41:38 AM UTC 25 | Feb 08 08:42:09 AM UTC 25 | 1238631568 ps | ||
| T465 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.3161800732 | Feb 08 08:41:41 AM UTC 25 | Feb 08 08:42:10 AM UTC 25 | 1210564275 ps | ||
| T466 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.2993094451 | Feb 08 08:41:37 AM UTC 25 | Feb 08 08:42:12 AM UTC 25 | 1431952841 ps | ||
| T467 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2767542597 | Feb 08 08:40:54 AM UTC 25 | Feb 08 08:42:13 AM UTC 25 | 3378341404 ps | ||
| T468 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1321077732 | Feb 08 08:41:28 AM UTC 25 | Feb 08 08:42:14 AM UTC 25 | 1909843457 ps | ||
| T469 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4209516135 | Feb 08 08:41:38 AM UTC 25 | Feb 08 08:42:14 AM UTC 25 | 1492172793 ps | ||
| T470 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2205061249 | Feb 08 08:41:06 AM UTC 25 | Feb 08 08:42:15 AM UTC 25 | 2913097904 ps | ||
| T471 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3498696173 | Feb 08 08:41:26 AM UTC 25 | Feb 08 08:42:20 AM UTC 25 | 2258518800 ps | ||
| T472 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3413586476 | Feb 08 08:41:39 AM UTC 25 | Feb 08 08:42:20 AM UTC 25 | 1712038821 ps | ||
| T473 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.205584562 | Feb 08 08:41:10 AM UTC 25 | Feb 08 08:42:25 AM UTC 25 | 3207627547 ps | ||
| T474 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3180287385 | Feb 08 08:41:36 AM UTC 25 | Feb 08 08:42:26 AM UTC 25 | 2076351779 ps | ||
| T475 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2033168510 | Feb 08 08:41:39 AM UTC 25 | Feb 08 08:42:26 AM UTC 25 | 1961933634 ps | ||
| T476 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.130427684 | Feb 08 08:41:35 AM UTC 25 | Feb 08 08:42:28 AM UTC 25 | 2256075038 ps | ||
| T477 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2522088112 | Feb 08 08:41:34 AM UTC 25 | Feb 08 08:42:28 AM UTC 25 | 2306352603 ps | ||
| T478 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.355006047 | Feb 08 08:41:43 AM UTC 25 | Feb 08 08:42:29 AM UTC 25 | 1897507301 ps | ||
| T479 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3022440477 | Feb 08 08:41:32 AM UTC 25 | Feb 08 08:42:31 AM UTC 25 | 2523385939 ps | ||
| T480 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.2633248179 | Feb 08 08:41:38 AM UTC 25 | Feb 08 08:42:33 AM UTC 25 | 2310989005 ps | ||
| T481 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3678354883 | Feb 08 08:41:20 AM UTC 25 | Feb 08 08:42:34 AM UTC 25 | 3146317467 ps | ||
| T482 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.1035891574 | Feb 08 08:41:36 AM UTC 25 | Feb 08 08:42:34 AM UTC 25 | 2462618974 ps | ||
| T483 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2162098694 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:42:36 AM UTC 25 | 2211129487 ps | ||
| T484 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2880996374 | Feb 08 08:41:35 AM UTC 25 | Feb 08 08:42:36 AM UTC 25 | 2597591131 ps | ||
| T485 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1220023747 | Feb 08 08:41:11 AM UTC 25 | Feb 08 08:42:37 AM UTC 25 | 3637476042 ps | ||
| T486 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2069180611 | Feb 08 08:41:35 AM UTC 25 | Feb 08 08:42:38 AM UTC 25 | 2659388426 ps | ||
| T487 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3384143171 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:42:41 AM UTC 25 | 2463252071 ps | ||
| T488 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.310131041 | Feb 08 08:41:27 AM UTC 25 | Feb 08 08:42:42 AM UTC 25 | 3172597374 ps | ||
| T489 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3934298588 | Feb 08 08:41:39 AM UTC 25 | Feb 08 08:42:43 AM UTC 25 | 2694623667 ps | ||
| T490 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3533849077 | Feb 08 08:41:37 AM UTC 25 | Feb 08 08:42:49 AM UTC 25 | 3018664119 ps | ||
| T491 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.22306638 | Feb 08 08:41:34 AM UTC 25 | Feb 08 08:42:52 AM UTC 25 | 3250217241 ps | ||
| T492 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.771431944 | Feb 08 08:41:36 AM UTC 25 | Feb 08 08:42:53 AM UTC 25 | 3203972674 ps | ||
| T493 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1843119953 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:42:53 AM UTC 25 | 2938671960 ps | ||
| T494 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4211409302 | Feb 08 08:41:44 AM UTC 25 | Feb 08 08:42:58 AM UTC 25 | 3000618440 ps | ||
| T495 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.3568607096 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:43:01 AM UTC 25 | 3223550658 ps | ||
| T496 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4135627402 | Feb 08 08:41:45 AM UTC 25 | Feb 08 08:43:02 AM UTC 25 | 3079988078 ps | ||
| T497 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3326996775 | Feb 08 08:41:39 AM UTC 25 | Feb 08 08:43:05 AM UTC 25 | 3480521862 ps | ||
| T498 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.559841660 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:43:08 AM UTC 25 | 3463921701 ps | ||
| T499 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.72006951 | Feb 08 08:41:42 AM UTC 25 | Feb 08 08:43:13 AM UTC 25 | 3608451749 ps | ||
| T500 | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.951893590 | Feb 08 08:41:43 AM UTC 25 | Feb 08 08:43:15 AM UTC 25 | 3612901570 ps |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.1215615036 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3260507617 ps |
| CPU time | 60.35 seconds |
| Started | Feb 08 08:11:28 AM UTC 25 |
| Finished | Feb 08 08:12:45 AM UTC 25 |
| Peak memory | 154460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215615036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pr im_prince_test.1215615036 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/0.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.3475206807 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1796587900 ps |
| CPU time | 33.41 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:18 AM UTC 25 |
| Peak memory | 154412 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475206807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pr im_prince_test.3475206807 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/1.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.1478250656 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 797515082 ps |
| CPU time | 15.3 seconds |
| Started | Feb 08 08:11:46 AM UTC 25 |
| Finished | Feb 08 08:12:06 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478250656 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.p rim_prince_test.1478250656 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/10.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.1410609922 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3040057247 ps |
| CPU time | 55.47 seconds |
| Started | Feb 08 08:17:56 AM UTC 25 |
| Finished | Feb 08 08:19:09 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410609922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100. prim_prince_test.1410609922 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/100.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.3875899947 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3065841641 ps |
| CPU time | 56.27 seconds |
| Started | Feb 08 08:18:07 AM UTC 25 |
| Finished | Feb 08 08:19:20 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875899947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101. prim_prince_test.3875899947 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/101.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.2897194083 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 3652162217 ps |
| CPU time | 66.74 seconds |
| Started | Feb 08 08:18:08 AM UTC 25 |
| Finished | Feb 08 08:19:36 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897194083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102. prim_prince_test.2897194083 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/102.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.3615341891 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2108647891 ps |
| CPU time | 38.64 seconds |
| Started | Feb 08 08:18:09 AM UTC 25 |
| Finished | Feb 08 08:19:00 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615341891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103. prim_prince_test.3615341891 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/103.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.2398085294 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3635954246 ps |
| CPU time | 66.42 seconds |
| Started | Feb 08 08:18:10 AM UTC 25 |
| Finished | Feb 08 08:19:36 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398085294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104. prim_prince_test.2398085294 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/104.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.3360474541 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 773114880 ps |
| CPU time | 14.59 seconds |
| Started | Feb 08 08:18:12 AM UTC 25 |
| Finished | Feb 08 08:18:32 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360474541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105. prim_prince_test.3360474541 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/105.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3218483338 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2564329142 ps |
| CPU time | 46.93 seconds |
| Started | Feb 08 08:18:14 AM UTC 25 |
| Finished | Feb 08 08:19:15 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218483338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106. prim_prince_test.3218483338 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/106.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.120708314 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3257749753 ps |
| CPU time | 60.09 seconds |
| Started | Feb 08 08:18:19 AM UTC 25 |
| Finished | Feb 08 08:19:37 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120708314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.p rim_prince_test.120708314 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/107.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.3232835407 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1798582535 ps |
| CPU time | 32.9 seconds |
| Started | Feb 08 08:18:22 AM UTC 25 |
| Finished | Feb 08 08:19:05 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232835407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108. prim_prince_test.3232835407 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/108.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.3034798757 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2244402937 ps |
| CPU time | 41.27 seconds |
| Started | Feb 08 08:18:25 AM UTC 25 |
| Finished | Feb 08 08:19:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034798757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109. prim_prince_test.3034798757 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/109.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.3475518046 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3567500120 ps |
| CPU time | 65.67 seconds |
| Started | Feb 08 08:12:03 AM UTC 25 |
| Finished | Feb 08 08:13:29 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475518046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.p rim_prince_test.3475518046 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/11.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.3924824980 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1644803053 ps |
| CPU time | 30.5 seconds |
| Started | Feb 08 08:18:32 AM UTC 25 |
| Finished | Feb 08 08:19:12 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924824980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110. prim_prince_test.3924824980 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/110.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.2766622493 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3709863862 ps |
| CPU time | 67.49 seconds |
| Started | Feb 08 08:18:34 AM UTC 25 |
| Finished | Feb 08 08:20:02 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766622493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111. prim_prince_test.2766622493 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/111.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.3601479145 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 1516910073 ps |
| CPU time | 27.85 seconds |
| Started | Feb 08 08:18:42 AM UTC 25 |
| Finished | Feb 08 08:19:19 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601479145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112. prim_prince_test.3601479145 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/112.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.1894199696 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3692184481 ps |
| CPU time | 67.96 seconds |
| Started | Feb 08 08:18:49 AM UTC 25 |
| Finished | Feb 08 08:20:17 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894199696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113. prim_prince_test.1894199696 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/113.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.1241700853 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 804240378 ps |
| CPU time | 15.09 seconds |
| Started | Feb 08 08:19:00 AM UTC 25 |
| Finished | Feb 08 08:19:21 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241700853 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114. prim_prince_test.1241700853 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/114.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.4180700559 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2470904499 ps |
| CPU time | 45.32 seconds |
| Started | Feb 08 08:19:06 AM UTC 25 |
| Finished | Feb 08 08:20:06 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180700559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115. prim_prince_test.4180700559 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/115.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.2720763313 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2192337438 ps |
| CPU time | 40.25 seconds |
| Started | Feb 08 08:19:07 AM UTC 25 |
| Finished | Feb 08 08:19:59 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720763313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116. prim_prince_test.2720763313 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/116.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.3137435626 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3662416693 ps |
| CPU time | 66.86 seconds |
| Started | Feb 08 08:19:10 AM UTC 25 |
| Finished | Feb 08 08:20:37 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137435626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117. prim_prince_test.3137435626 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/117.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.1404009408 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3203346275 ps |
| CPU time | 58.71 seconds |
| Started | Feb 08 08:19:13 AM UTC 25 |
| Finished | Feb 08 08:20:29 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404009408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118. prim_prince_test.1404009408 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/118.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.1319163635 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 1949818523 ps |
| CPU time | 36.11 seconds |
| Started | Feb 08 08:19:16 AM UTC 25 |
| Finished | Feb 08 08:20:03 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319163635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119. prim_prince_test.1319163635 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/119.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.2870976366 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1741471141 ps |
| CPU time | 32.49 seconds |
| Started | Feb 08 08:12:09 AM UTC 25 |
| Finished | Feb 08 08:12:52 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870976366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.p rim_prince_test.2870976366 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/12.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.4117463600 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2690098753 ps |
| CPU time | 49.44 seconds |
| Started | Feb 08 08:19:20 AM UTC 25 |
| Finished | Feb 08 08:20:24 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117463600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120. prim_prince_test.4117463600 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/120.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.2779928308 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3563163009 ps |
| CPU time | 64.92 seconds |
| Started | Feb 08 08:19:20 AM UTC 25 |
| Finished | Feb 08 08:20:44 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779928308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121. prim_prince_test.2779928308 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/121.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.228185784 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2215593919 ps |
| CPU time | 40.57 seconds |
| Started | Feb 08 08:19:21 AM UTC 25 |
| Finished | Feb 08 08:20:14 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228185784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.p rim_prince_test.228185784 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/122.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.3976699163 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3407689821 ps |
| CPU time | 62.68 seconds |
| Started | Feb 08 08:19:22 AM UTC 25 |
| Finished | Feb 08 08:20:43 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976699163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123. prim_prince_test.3976699163 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/123.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.3557110859 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2300106834 ps |
| CPU time | 42.02 seconds |
| Started | Feb 08 08:19:36 AM UTC 25 |
| Finished | Feb 08 08:20:31 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557110859 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124. prim_prince_test.3557110859 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/124.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.2560566183 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2575063370 ps |
| CPU time | 46.94 seconds |
| Started | Feb 08 08:19:37 AM UTC 25 |
| Finished | Feb 08 08:20:39 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560566183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125. prim_prince_test.2560566183 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/125.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.686467395 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1223053824 ps |
| CPU time | 22.83 seconds |
| Started | Feb 08 08:19:37 AM UTC 25 |
| Finished | Feb 08 08:20:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686467395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.p rim_prince_test.686467395 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/126.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.2453077825 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 1644664963 ps |
| CPU time | 30.08 seconds |
| Started | Feb 08 08:20:00 AM UTC 25 |
| Finished | Feb 08 08:20:40 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453077825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127. prim_prince_test.2453077825 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/127.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.2333210439 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1443959568 ps |
| CPU time | 26.54 seconds |
| Started | Feb 08 08:20:02 AM UTC 25 |
| Finished | Feb 08 08:20:38 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333210439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128. prim_prince_test.2333210439 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/128.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.1587680554 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 3524016774 ps |
| CPU time | 64.14 seconds |
| Started | Feb 08 08:20:04 AM UTC 25 |
| Finished | Feb 08 08:21:28 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587680554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129. prim_prince_test.1587680554 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/129.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.874729140 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3149383133 ps |
| CPU time | 58.2 seconds |
| Started | Feb 08 08:12:10 AM UTC 25 |
| Finished | Feb 08 08:13:25 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874729140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pr im_prince_test.874729140 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/13.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.1241313239 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 3316312643 ps |
| CPU time | 60.38 seconds |
| Started | Feb 08 08:20:07 AM UTC 25 |
| Finished | Feb 08 08:21:27 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241313239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130. prim_prince_test.1241313239 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/130.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.1691251603 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2228825823 ps |
| CPU time | 40.78 seconds |
| Started | Feb 08 08:20:09 AM UTC 25 |
| Finished | Feb 08 08:21:03 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691251603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131. prim_prince_test.1691251603 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/131.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.2197166046 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2961993484 ps |
| CPU time | 54.1 seconds |
| Started | Feb 08 08:20:15 AM UTC 25 |
| Finished | Feb 08 08:21:25 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197166046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132. prim_prince_test.2197166046 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/132.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.1424908266 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2483467739 ps |
| CPU time | 45.21 seconds |
| Started | Feb 08 08:20:18 AM UTC 25 |
| Finished | Feb 08 08:21:17 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424908266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133. prim_prince_test.1424908266 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/133.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.839072341 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 952311913 ps |
| CPU time | 17.7 seconds |
| Started | Feb 08 08:20:25 AM UTC 25 |
| Finished | Feb 08 08:20:49 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839072341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.p rim_prince_test.839072341 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/134.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.1251434981 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2486268361 ps |
| CPU time | 45.27 seconds |
| Started | Feb 08 08:20:30 AM UTC 25 |
| Finished | Feb 08 08:21:30 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251434981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135. prim_prince_test.1251434981 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/135.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.123941555 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2829857952 ps |
| CPU time | 51.69 seconds |
| Started | Feb 08 08:20:32 AM UTC 25 |
| Finished | Feb 08 08:21:40 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123941555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.p rim_prince_test.123941555 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/136.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.3630349757 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2362147550 ps |
| CPU time | 43.22 seconds |
| Started | Feb 08 08:20:37 AM UTC 25 |
| Finished | Feb 08 08:21:34 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630349757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137. prim_prince_test.3630349757 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/137.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.2746200292 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1436143308 ps |
| CPU time | 26.45 seconds |
| Started | Feb 08 08:20:39 AM UTC 25 |
| Finished | Feb 08 08:21:15 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746200292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138. prim_prince_test.2746200292 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/138.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.4132792959 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3471934306 ps |
| CPU time | 63.24 seconds |
| Started | Feb 08 08:20:39 AM UTC 25 |
| Finished | Feb 08 08:22:02 AM UTC 25 |
| Peak memory | 154640 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132792959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139. prim_prince_test.4132792959 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/139.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.1017999631 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2223851556 ps |
| CPU time | 41.4 seconds |
| Started | Feb 08 08:12:20 AM UTC 25 |
| Finished | Feb 08 08:13:14 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017999631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.p rim_prince_test.1017999631 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/14.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.3659145961 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2776371253 ps |
| CPU time | 50.22 seconds |
| Started | Feb 08 08:20:41 AM UTC 25 |
| Finished | Feb 08 08:21:48 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659145961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140. prim_prince_test.3659145961 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/140.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.3669568819 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2878894873 ps |
| CPU time | 52.49 seconds |
| Started | Feb 08 08:20:45 AM UTC 25 |
| Finished | Feb 08 08:21:54 AM UTC 25 |
| Peak memory | 154552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669568819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141. prim_prince_test.3669568819 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/141.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.1160476807 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 2206240836 ps |
| CPU time | 40.11 seconds |
| Started | Feb 08 08:20:45 AM UTC 25 |
| Finished | Feb 08 08:21:38 AM UTC 25 |
| Peak memory | 154544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160476807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142. prim_prince_test.1160476807 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/142.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3910490778 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 1389388623 ps |
| CPU time | 25.64 seconds |
| Started | Feb 08 08:20:50 AM UTC 25 |
| Finished | Feb 08 08:21:24 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910490778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143. prim_prince_test.3910490778 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/143.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.662883429 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2942130481 ps |
| CPU time | 53.89 seconds |
| Started | Feb 08 08:21:04 AM UTC 25 |
| Finished | Feb 08 08:22:14 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662883429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.p rim_prince_test.662883429 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/144.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.1170682131 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 807190579 ps |
| CPU time | 15.02 seconds |
| Started | Feb 08 08:21:16 AM UTC 25 |
| Finished | Feb 08 08:21:37 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170682131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145. prim_prince_test.1170682131 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/145.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.2946958132 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2913371425 ps |
| CPU time | 52.98 seconds |
| Started | Feb 08 08:21:18 AM UTC 25 |
| Finished | Feb 08 08:22:27 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946958132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146. prim_prince_test.2946958132 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/146.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1884186174 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1745572474 ps |
| CPU time | 31.94 seconds |
| Started | Feb 08 08:21:24 AM UTC 25 |
| Finished | Feb 08 08:22:07 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884186174 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147. prim_prince_test.1884186174 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/147.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.2911331442 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2258247773 ps |
| CPU time | 41.19 seconds |
| Started | Feb 08 08:21:26 AM UTC 25 |
| Finished | Feb 08 08:22:21 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911331442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148. prim_prince_test.2911331442 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/148.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.1090655570 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2014003954 ps |
| CPU time | 36.81 seconds |
| Started | Feb 08 08:21:27 AM UTC 25 |
| Finished | Feb 08 08:22:16 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090655570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149. prim_prince_test.1090655570 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/149.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.1080717072 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2499729231 ps |
| CPU time | 45.92 seconds |
| Started | Feb 08 08:12:22 AM UTC 25 |
| Finished | Feb 08 08:13:22 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080717072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.p rim_prince_test.1080717072 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/15.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.3842378223 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1846725297 ps |
| CPU time | 33.76 seconds |
| Started | Feb 08 08:21:28 AM UTC 25 |
| Finished | Feb 08 08:22:13 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842378223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150. prim_prince_test.3842378223 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/150.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.4056341763 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2263797589 ps |
| CPU time | 41.29 seconds |
| Started | Feb 08 08:21:30 AM UTC 25 |
| Finished | Feb 08 08:22:24 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056341763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151. prim_prince_test.4056341763 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/151.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.2513860302 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2238702759 ps |
| CPU time | 40.88 seconds |
| Started | Feb 08 08:21:35 AM UTC 25 |
| Finished | Feb 08 08:22:29 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513860302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152. prim_prince_test.2513860302 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/152.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.3360110987 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1182580670 ps |
| CPU time | 21.91 seconds |
| Started | Feb 08 08:21:38 AM UTC 25 |
| Finished | Feb 08 08:22:07 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360110987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153. prim_prince_test.3360110987 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/153.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.1645332119 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2290194862 ps |
| CPU time | 41.99 seconds |
| Started | Feb 08 08:21:39 AM UTC 25 |
| Finished | Feb 08 08:22:34 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645332119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154. prim_prince_test.1645332119 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/154.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.3526040808 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2828204178 ps |
| CPU time | 51.39 seconds |
| Started | Feb 08 08:21:41 AM UTC 25 |
| Finished | Feb 08 08:22:48 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526040808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155. prim_prince_test.3526040808 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/155.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.2229895277 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 3552076274 ps |
| CPU time | 64.6 seconds |
| Started | Feb 08 08:21:49 AM UTC 25 |
| Finished | Feb 08 08:23:13 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229895277 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156. prim_prince_test.2229895277 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/156.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.1311024156 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1383942748 ps |
| CPU time | 25.54 seconds |
| Started | Feb 08 08:21:54 AM UTC 25 |
| Finished | Feb 08 08:22:28 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311024156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157. prim_prince_test.1311024156 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/157.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.3262253227 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2688680242 ps |
| CPU time | 48.8 seconds |
| Started | Feb 08 08:22:03 AM UTC 25 |
| Finished | Feb 08 08:23:07 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262253227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158. prim_prince_test.3262253227 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/158.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.3938728504 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 809227627 ps |
| CPU time | 15.13 seconds |
| Started | Feb 08 08:22:07 AM UTC 25 |
| Finished | Feb 08 08:22:28 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938728504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159. prim_prince_test.3938728504 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/159.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.3566250333 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2644796422 ps |
| CPU time | 48.73 seconds |
| Started | Feb 08 08:12:32 AM UTC 25 |
| Finished | Feb 08 08:13:36 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566250333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.p rim_prince_test.3566250333 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/16.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.2419145843 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 839206247 ps |
| CPU time | 15.59 seconds |
| Started | Feb 08 08:22:08 AM UTC 25 |
| Finished | Feb 08 08:22:30 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419145843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160. prim_prince_test.2419145843 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/160.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3188993060 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2428126770 ps |
| CPU time | 44.14 seconds |
| Started | Feb 08 08:22:13 AM UTC 25 |
| Finished | Feb 08 08:23:11 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188993060 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161. prim_prince_test.3188993060 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/161.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.615272712 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3168989549 ps |
| CPU time | 57.67 seconds |
| Started | Feb 08 08:22:14 AM UTC 25 |
| Finished | Feb 08 08:23:30 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615272712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.p rim_prince_test.615272712 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/162.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.120275901 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1698904256 ps |
| CPU time | 30.98 seconds |
| Started | Feb 08 08:22:16 AM UTC 25 |
| Finished | Feb 08 08:22:58 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120275901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.p rim_prince_test.120275901 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/163.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.279287663 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 2828709768 ps |
| CPU time | 51.48 seconds |
| Started | Feb 08 08:22:22 AM UTC 25 |
| Finished | Feb 08 08:23:29 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279287663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.p rim_prince_test.279287663 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/164.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.190885242 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3327449524 ps |
| CPU time | 60.49 seconds |
| Started | Feb 08 08:22:26 AM UTC 25 |
| Finished | Feb 08 08:23:45 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190885242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.p rim_prince_test.190885242 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/165.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.2280628603 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 797070690 ps |
| CPU time | 14.78 seconds |
| Started | Feb 08 08:22:28 AM UTC 25 |
| Finished | Feb 08 08:22:48 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280628603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166. prim_prince_test.2280628603 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/166.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.1210464936 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 866548528 ps |
| CPU time | 16.03 seconds |
| Started | Feb 08 08:22:29 AM UTC 25 |
| Finished | Feb 08 08:22:51 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210464936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167. prim_prince_test.1210464936 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/167.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.1016483186 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2311355668 ps |
| CPU time | 42.22 seconds |
| Started | Feb 08 08:22:29 AM UTC 25 |
| Finished | Feb 08 08:23:25 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016483186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168. prim_prince_test.1016483186 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/168.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.4013280923 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 860275777 ps |
| CPU time | 15.89 seconds |
| Started | Feb 08 08:22:30 AM UTC 25 |
| Finished | Feb 08 08:22:53 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013280923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169. prim_prince_test.4013280923 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/169.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.2896215213 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2892802932 ps |
| CPU time | 53.13 seconds |
| Started | Feb 08 08:12:35 AM UTC 25 |
| Finished | Feb 08 08:13:45 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896215213 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.p rim_prince_test.2896215213 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/17.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.3451432603 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2715250343 ps |
| CPU time | 49.6 seconds |
| Started | Feb 08 08:22:31 AM UTC 25 |
| Finished | Feb 08 08:23:37 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451432603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170. prim_prince_test.3451432603 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/170.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.3176651253 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2499639925 ps |
| CPU time | 45.62 seconds |
| Started | Feb 08 08:22:35 AM UTC 25 |
| Finished | Feb 08 08:23:35 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176651253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171. prim_prince_test.3176651253 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/171.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.2459345220 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 1252771573 ps |
| CPU time | 23.08 seconds |
| Started | Feb 08 08:22:49 AM UTC 25 |
| Finished | Feb 08 08:23:20 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459345220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172. prim_prince_test.2459345220 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/172.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.2401559904 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3489608966 ps |
| CPU time | 63.54 seconds |
| Started | Feb 08 08:22:49 AM UTC 25 |
| Finished | Feb 08 08:24:12 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401559904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173. prim_prince_test.2401559904 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/173.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.188568780 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1311979337 ps |
| CPU time | 24.28 seconds |
| Started | Feb 08 08:22:52 AM UTC 25 |
| Finished | Feb 08 08:23:25 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188568780 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.p rim_prince_test.188568780 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/174.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.1110259403 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 863685094 ps |
| CPU time | 16.03 seconds |
| Started | Feb 08 08:22:54 AM UTC 25 |
| Finished | Feb 08 08:23:15 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110259403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175. prim_prince_test.1110259403 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/175.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.864996278 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3561332732 ps |
| CPU time | 65.16 seconds |
| Started | Feb 08 08:22:59 AM UTC 25 |
| Finished | Feb 08 08:24:23 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864996278 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.p rim_prince_test.864996278 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/176.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.3465856478 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1174050305 ps |
| CPU time | 21.75 seconds |
| Started | Feb 08 08:23:08 AM UTC 25 |
| Finished | Feb 08 08:23:37 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465856478 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177. prim_prince_test.3465856478 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/177.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.2540760076 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2235042218 ps |
| CPU time | 40.77 seconds |
| Started | Feb 08 08:23:12 AM UTC 25 |
| Finished | Feb 08 08:24:06 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540760076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178. prim_prince_test.2540760076 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/178.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.3420381591 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2738829568 ps |
| CPU time | 50.28 seconds |
| Started | Feb 08 08:23:14 AM UTC 25 |
| Finished | Feb 08 08:24:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420381591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179. prim_prince_test.3420381591 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/179.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.2633223421 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2737063413 ps |
| CPU time | 50.22 seconds |
| Started | Feb 08 08:12:45 AM UTC 25 |
| Finished | Feb 08 08:13:51 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633223421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.p rim_prince_test.2633223421 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/18.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.935061376 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3079166787 ps |
| CPU time | 56.16 seconds |
| Started | Feb 08 08:23:16 AM UTC 25 |
| Finished | Feb 08 08:24:29 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935061376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.p rim_prince_test.935061376 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/180.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.1093237423 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1729162597 ps |
| CPU time | 31.9 seconds |
| Started | Feb 08 08:23:21 AM UTC 25 |
| Finished | Feb 08 08:24:03 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093237423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181. prim_prince_test.1093237423 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/181.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.751317989 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3625002659 ps |
| CPU time | 66.63 seconds |
| Started | Feb 08 08:23:25 AM UTC 25 |
| Finished | Feb 08 08:24:52 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751317989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.p rim_prince_test.751317989 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/182.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.900991569 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1252525265 ps |
| CPU time | 23.08 seconds |
| Started | Feb 08 08:23:26 AM UTC 25 |
| Finished | Feb 08 08:23:57 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900991569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.p rim_prince_test.900991569 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/183.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.3166116772 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3244678781 ps |
| CPU time | 59.6 seconds |
| Started | Feb 08 08:23:29 AM UTC 25 |
| Finished | Feb 08 08:24:47 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166116772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184. prim_prince_test.3166116772 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/184.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.832030191 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2730852161 ps |
| CPU time | 50.17 seconds |
| Started | Feb 08 08:23:30 AM UTC 25 |
| Finished | Feb 08 08:24:36 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832030191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.p rim_prince_test.832030191 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/185.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.3442109182 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3335393085 ps |
| CPU time | 61.09 seconds |
| Started | Feb 08 08:23:36 AM UTC 25 |
| Finished | Feb 08 08:24:55 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442109182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186. prim_prince_test.3442109182 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/186.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.1419479930 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2285133787 ps |
| CPU time | 41.8 seconds |
| Started | Feb 08 08:23:38 AM UTC 25 |
| Finished | Feb 08 08:24:32 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419479930 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187. prim_prince_test.1419479930 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/187.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.2913093420 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3613483561 ps |
| CPU time | 65.96 seconds |
| Started | Feb 08 08:23:38 AM UTC 25 |
| Finished | Feb 08 08:25:04 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913093420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188. prim_prince_test.2913093420 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/188.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.2108611902 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3109016283 ps |
| CPU time | 57 seconds |
| Started | Feb 08 08:23:46 AM UTC 25 |
| Finished | Feb 08 08:25:00 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108611902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189. prim_prince_test.2108611902 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/189.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.3783102956 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3607706649 ps |
| CPU time | 66.58 seconds |
| Started | Feb 08 08:12:47 AM UTC 25 |
| Finished | Feb 08 08:14:13 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783102956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.p rim_prince_test.3783102956 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/19.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.548457734 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1419291202 ps |
| CPU time | 26.4 seconds |
| Started | Feb 08 08:23:58 AM UTC 25 |
| Finished | Feb 08 08:24:33 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548457734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.p rim_prince_test.548457734 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/190.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.3405879960 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3003584689 ps |
| CPU time | 55.57 seconds |
| Started | Feb 08 08:24:04 AM UTC 25 |
| Finished | Feb 08 08:25:17 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405879960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191. prim_prince_test.3405879960 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/191.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.2704835716 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3111651483 ps |
| CPU time | 57.68 seconds |
| Started | Feb 08 08:24:06 AM UTC 25 |
| Finished | Feb 08 08:25:21 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704835716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192. prim_prince_test.2704835716 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/192.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.2872681437 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3208046043 ps |
| CPU time | 59.3 seconds |
| Started | Feb 08 08:24:13 AM UTC 25 |
| Finished | Feb 08 08:25:30 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872681437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193. prim_prince_test.2872681437 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/193.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.1563889249 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1958015464 ps |
| CPU time | 36.02 seconds |
| Started | Feb 08 08:24:20 AM UTC 25 |
| Finished | Feb 08 08:25:09 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563889249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194. prim_prince_test.1563889249 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/194.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.874661343 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3546305002 ps |
| CPU time | 65.18 seconds |
| Started | Feb 08 08:24:24 AM UTC 25 |
| Finished | Feb 08 08:25:49 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874661343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.p rim_prince_test.874661343 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/195.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.3996611444 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 1499180884 ps |
| CPU time | 27.78 seconds |
| Started | Feb 08 08:24:31 AM UTC 25 |
| Finished | Feb 08 08:25:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996611444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196. prim_prince_test.3996611444 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/196.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.3804068140 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2684360834 ps |
| CPU time | 49.28 seconds |
| Started | Feb 08 08:24:34 AM UTC 25 |
| Finished | Feb 08 08:25:38 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804068140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197. prim_prince_test.3804068140 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/197.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.1301232409 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 1063939068 ps |
| CPU time | 19.75 seconds |
| Started | Feb 08 08:24:34 AM UTC 25 |
| Finished | Feb 08 08:25:00 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301232409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198. prim_prince_test.1301232409 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/198.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.3306636849 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1658141339 ps |
| CPU time | 30.69 seconds |
| Started | Feb 08 08:24:37 AM UTC 25 |
| Finished | Feb 08 08:25:18 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306636849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199. prim_prince_test.3306636849 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/199.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.434930571 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2384893880 ps |
| CPU time | 44.75 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:32 AM UTC 25 |
| Peak memory | 154576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434930571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pri m_prince_test.434930571 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/2.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.3833414881 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 887657693 ps |
| CPU time | 16.7 seconds |
| Started | Feb 08 08:12:50 AM UTC 25 |
| Finished | Feb 08 08:13:12 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833414881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.p rim_prince_test.3833414881 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/20.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.4047933760 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2006030001 ps |
| CPU time | 36.8 seconds |
| Started | Feb 08 08:24:48 AM UTC 25 |
| Finished | Feb 08 08:25:37 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047933760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200. prim_prince_test.4047933760 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/200.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.2242065683 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 1440214522 ps |
| CPU time | 26.87 seconds |
| Started | Feb 08 08:24:52 AM UTC 25 |
| Finished | Feb 08 08:25:28 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242065683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201. prim_prince_test.2242065683 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/201.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.1818085068 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2433081576 ps |
| CPU time | 44.6 seconds |
| Started | Feb 08 08:24:55 AM UTC 25 |
| Finished | Feb 08 08:25:54 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818085068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202. prim_prince_test.1818085068 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/202.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.2416800433 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 847148689 ps |
| CPU time | 15.71 seconds |
| Started | Feb 08 08:25:01 AM UTC 25 |
| Finished | Feb 08 08:25:23 AM UTC 25 |
| Peak memory | 154564 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416800433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203. prim_prince_test.2416800433 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/203.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.3257939125 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2194369621 ps |
| CPU time | 40.53 seconds |
| Started | Feb 08 08:25:01 AM UTC 25 |
| Finished | Feb 08 08:25:55 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257939125 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204. prim_prince_test.3257939125 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/204.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.1471838397 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 818465194 ps |
| CPU time | 15.23 seconds |
| Started | Feb 08 08:25:05 AM UTC 25 |
| Finished | Feb 08 08:25:25 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471838397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205. prim_prince_test.1471838397 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/205.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.3362818969 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3697952326 ps |
| CPU time | 67.21 seconds |
| Started | Feb 08 08:25:09 AM UTC 25 |
| Finished | Feb 08 08:26:36 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362818969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206. prim_prince_test.3362818969 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/206.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.569179987 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 790713077 ps |
| CPU time | 14.78 seconds |
| Started | Feb 08 08:25:10 AM UTC 25 |
| Finished | Feb 08 08:25:30 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569179987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.p rim_prince_test.569179987 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/207.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.2722719904 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3563266840 ps |
| CPU time | 64.75 seconds |
| Started | Feb 08 08:25:18 AM UTC 25 |
| Finished | Feb 08 08:26:42 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722719904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208. prim_prince_test.2722719904 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/208.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.2856594332 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 1907294688 ps |
| CPU time | 34.96 seconds |
| Started | Feb 08 08:25:18 AM UTC 25 |
| Finished | Feb 08 08:26:04 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856594332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209. prim_prince_test.2856594332 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/209.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.2685756199 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2643262664 ps |
| CPU time | 49.08 seconds |
| Started | Feb 08 08:12:52 AM UTC 25 |
| Finished | Feb 08 08:13:55 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685756199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.p rim_prince_test.2685756199 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/21.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.2902081921 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1984883806 ps |
| CPU time | 36.46 seconds |
| Started | Feb 08 08:25:22 AM UTC 25 |
| Finished | Feb 08 08:26:10 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902081921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210. prim_prince_test.2902081921 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/210.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.3159772087 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2239850166 ps |
| CPU time | 40.93 seconds |
| Started | Feb 08 08:25:24 AM UTC 25 |
| Finished | Feb 08 08:26:18 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159772087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211. prim_prince_test.3159772087 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/211.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.1097130417 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1308643189 ps |
| CPU time | 24.18 seconds |
| Started | Feb 08 08:25:26 AM UTC 25 |
| Finished | Feb 08 08:25:59 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097130417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212. prim_prince_test.1097130417 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/212.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.132415549 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2547459168 ps |
| CPU time | 46.41 seconds |
| Started | Feb 08 08:25:28 AM UTC 25 |
| Finished | Feb 08 08:26:29 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132415549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.p rim_prince_test.132415549 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/213.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.2696863488 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2041215039 ps |
| CPU time | 37.19 seconds |
| Started | Feb 08 08:25:32 AM UTC 25 |
| Finished | Feb 08 08:26:20 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696863488 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214. prim_prince_test.2696863488 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/214.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.429502798 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1198309837 ps |
| CPU time | 22.18 seconds |
| Started | Feb 08 08:25:32 AM UTC 25 |
| Finished | Feb 08 08:26:01 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429502798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.p rim_prince_test.429502798 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/215.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.2369805716 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1459288622 ps |
| CPU time | 26.83 seconds |
| Started | Feb 08 08:25:38 AM UTC 25 |
| Finished | Feb 08 08:26:13 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369805716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216. prim_prince_test.2369805716 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/216.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.2131794534 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3143739272 ps |
| CPU time | 57.43 seconds |
| Started | Feb 08 08:25:39 AM UTC 25 |
| Finished | Feb 08 08:26:54 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131794534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217. prim_prince_test.2131794534 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/217.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.459698554 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1723082297 ps |
| CPU time | 31.58 seconds |
| Started | Feb 08 08:25:50 AM UTC 25 |
| Finished | Feb 08 08:26:32 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459698554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.p rim_prince_test.459698554 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/218.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.3268416568 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3235958542 ps |
| CPU time | 59.29 seconds |
| Started | Feb 08 08:25:55 AM UTC 25 |
| Finished | Feb 08 08:27:12 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268416568 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219. prim_prince_test.3268416568 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/219.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.3489630334 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2383421341 ps |
| CPU time | 43.56 seconds |
| Started | Feb 08 08:12:54 AM UTC 25 |
| Finished | Feb 08 08:13:51 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489630334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.p rim_prince_test.3489630334 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/22.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.2705677099 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1933184675 ps |
| CPU time | 35.73 seconds |
| Started | Feb 08 08:25:55 AM UTC 25 |
| Finished | Feb 08 08:26:42 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705677099 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220. prim_prince_test.2705677099 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/220.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.3078661957 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1296747492 ps |
| CPU time | 23.99 seconds |
| Started | Feb 08 08:25:59 AM UTC 25 |
| Finished | Feb 08 08:26:31 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078661957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221. prim_prince_test.3078661957 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/221.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.10093575 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2218666585 ps |
| CPU time | 40.6 seconds |
| Started | Feb 08 08:26:02 AM UTC 25 |
| Finished | Feb 08 08:26:56 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10093575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.pr im_prince_test.10093575 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/222.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.956466223 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2451053402 ps |
| CPU time | 44.91 seconds |
| Started | Feb 08 08:26:04 AM UTC 25 |
| Finished | Feb 08 08:27:04 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956466223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.p rim_prince_test.956466223 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/223.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.4062951358 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 994187769 ps |
| CPU time | 18.56 seconds |
| Started | Feb 08 08:26:11 AM UTC 25 |
| Finished | Feb 08 08:26:36 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062951358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224. prim_prince_test.4062951358 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/224.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1613663315 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2675974269 ps |
| CPU time | 49.16 seconds |
| Started | Feb 08 08:26:14 AM UTC 25 |
| Finished | Feb 08 08:27:18 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613663315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225. prim_prince_test.1613663315 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/225.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.987132536 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 3601691020 ps |
| CPU time | 65.54 seconds |
| Started | Feb 08 08:26:19 AM UTC 25 |
| Finished | Feb 08 08:27:44 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987132536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.p rim_prince_test.987132536 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/226.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3830622440 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2727073298 ps |
| CPU time | 49.77 seconds |
| Started | Feb 08 08:26:21 AM UTC 25 |
| Finished | Feb 08 08:27:26 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830622440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227. prim_prince_test.3830622440 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/227.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.2446562792 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 958492910 ps |
| CPU time | 17.85 seconds |
| Started | Feb 08 08:26:30 AM UTC 25 |
| Finished | Feb 08 08:26:54 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446562792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228. prim_prince_test.2446562792 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/228.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.3555297504 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2586859237 ps |
| CPU time | 47.3 seconds |
| Started | Feb 08 08:26:32 AM UTC 25 |
| Finished | Feb 08 08:27:34 AM UTC 25 |
| Peak memory | 154552 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555297504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229. prim_prince_test.3555297504 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/229.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.246362388 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2294837860 ps |
| CPU time | 42.07 seconds |
| Started | Feb 08 08:12:55 AM UTC 25 |
| Finished | Feb 08 08:13:50 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246362388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pr im_prince_test.246362388 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/23.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.1259911285 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3122835876 ps |
| CPU time | 57.5 seconds |
| Started | Feb 08 08:26:32 AM UTC 25 |
| Finished | Feb 08 08:27:47 AM UTC 25 |
| Peak memory | 154492 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259911285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230. prim_prince_test.1259911285 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/230.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.636087516 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1020663487 ps |
| CPU time | 19.04 seconds |
| Started | Feb 08 08:26:37 AM UTC 25 |
| Finished | Feb 08 08:27:03 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636087516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.p rim_prince_test.636087516 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/231.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.309705971 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1549082299 ps |
| CPU time | 28.76 seconds |
| Started | Feb 08 08:26:37 AM UTC 25 |
| Finished | Feb 08 08:27:15 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309705971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.p rim_prince_test.309705971 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/232.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.1770503945 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3223188090 ps |
| CPU time | 58.68 seconds |
| Started | Feb 08 08:26:42 AM UTC 25 |
| Finished | Feb 08 08:27:59 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770503945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233. prim_prince_test.1770503945 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/233.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.967909244 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 960831200 ps |
| CPU time | 17.96 seconds |
| Started | Feb 08 08:26:44 AM UTC 25 |
| Finished | Feb 08 08:27:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967909244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.p rim_prince_test.967909244 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/234.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.986117829 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1446390618 ps |
| CPU time | 26.83 seconds |
| Started | Feb 08 08:26:55 AM UTC 25 |
| Finished | Feb 08 08:27:30 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986117829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.p rim_prince_test.986117829 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/235.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.2574621601 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 1400453437 ps |
| CPU time | 25.74 seconds |
| Started | Feb 08 08:26:55 AM UTC 25 |
| Finished | Feb 08 08:27:29 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574621601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236. prim_prince_test.2574621601 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/236.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.189253988 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 798489192 ps |
| CPU time | 14.92 seconds |
| Started | Feb 08 08:26:57 AM UTC 25 |
| Finished | Feb 08 08:27:17 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189253988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.p rim_prince_test.189253988 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/237.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.3548363298 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 1999393744 ps |
| CPU time | 36.62 seconds |
| Started | Feb 08 08:27:04 AM UTC 25 |
| Finished | Feb 08 08:27:53 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548363298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238. prim_prince_test.3548363298 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/238.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.1567580220 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3069229413 ps |
| CPU time | 56.22 seconds |
| Started | Feb 08 08:27:05 AM UTC 25 |
| Finished | Feb 08 08:28:18 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567580220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239. prim_prince_test.1567580220 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/239.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.2411974551 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2969979808 ps |
| CPU time | 55.02 seconds |
| Started | Feb 08 08:13:03 AM UTC 25 |
| Finished | Feb 08 08:14:13 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411974551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.p rim_prince_test.2411974551 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/24.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.3699665364 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2980655051 ps |
| CPU time | 54.24 seconds |
| Started | Feb 08 08:27:08 AM UTC 25 |
| Finished | Feb 08 08:28:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699665364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240. prim_prince_test.3699665364 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/240.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.3780376581 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2131809773 ps |
| CPU time | 38.97 seconds |
| Started | Feb 08 08:27:13 AM UTC 25 |
| Finished | Feb 08 08:28:05 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780376581 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241. prim_prince_test.3780376581 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/241.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.2651590665 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2143237034 ps |
| CPU time | 38.92 seconds |
| Started | Feb 08 08:27:17 AM UTC 25 |
| Finished | Feb 08 08:28:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651590665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242. prim_prince_test.2651590665 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/242.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2774281122 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3506260641 ps |
| CPU time | 64.11 seconds |
| Started | Feb 08 08:27:19 AM UTC 25 |
| Finished | Feb 08 08:28:42 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774281122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243. prim_prince_test.2774281122 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/243.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.1459464713 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 3692631415 ps |
| CPU time | 68.15 seconds |
| Started | Feb 08 08:27:19 AM UTC 25 |
| Finished | Feb 08 08:28:47 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459464713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244. prim_prince_test.1459464713 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/244.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2780450954 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1185116976 ps |
| CPU time | 21.91 seconds |
| Started | Feb 08 08:27:27 AM UTC 25 |
| Finished | Feb 08 08:27:57 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780450954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245. prim_prince_test.2780450954 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/245.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.3485307320 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3668745474 ps |
| CPU time | 66.82 seconds |
| Started | Feb 08 08:27:30 AM UTC 25 |
| Finished | Feb 08 08:28:57 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485307320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246. prim_prince_test.3485307320 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/246.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.444253580 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2399316458 ps |
| CPU time | 43.84 seconds |
| Started | Feb 08 08:27:31 AM UTC 25 |
| Finished | Feb 08 08:28:29 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444253580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.p rim_prince_test.444253580 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/247.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.2277368112 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1423957207 ps |
| CPU time | 26.35 seconds |
| Started | Feb 08 08:27:35 AM UTC 25 |
| Finished | Feb 08 08:28:10 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277368112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248. prim_prince_test.2277368112 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/248.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1773261268 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2966560863 ps |
| CPU time | 54.39 seconds |
| Started | Feb 08 08:27:45 AM UTC 25 |
| Finished | Feb 08 08:28:56 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773261268 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249. prim_prince_test.1773261268 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/249.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.3465065594 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3221823563 ps |
| CPU time | 59.16 seconds |
| Started | Feb 08 08:13:06 AM UTC 25 |
| Finished | Feb 08 08:14:22 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465065594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.p rim_prince_test.3465065594 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/25.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.2490376133 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2211995919 ps |
| CPU time | 41.1 seconds |
| Started | Feb 08 08:27:47 AM UTC 25 |
| Finished | Feb 08 08:28:42 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490376133 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250. prim_prince_test.2490376133 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/250.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.642815365 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1491407674 ps |
| CPU time | 27.67 seconds |
| Started | Feb 08 08:27:54 AM UTC 25 |
| Finished | Feb 08 08:28:30 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642815365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.p rim_prince_test.642815365 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/251.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.243683529 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2053461481 ps |
| CPU time | 38.04 seconds |
| Started | Feb 08 08:27:58 AM UTC 25 |
| Finished | Feb 08 08:28:48 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243683529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.p rim_prince_test.243683529 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/252.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.3764033774 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2798902190 ps |
| CPU time | 51.26 seconds |
| Started | Feb 08 08:28:00 AM UTC 25 |
| Finished | Feb 08 08:29:07 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764033774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253. prim_prince_test.3764033774 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/253.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.778061472 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3036228222 ps |
| CPU time | 55.56 seconds |
| Started | Feb 08 08:28:06 AM UTC 25 |
| Finished | Feb 08 08:29:19 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778061472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.p rim_prince_test.778061472 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/254.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.2318876358 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2146667567 ps |
| CPU time | 39.31 seconds |
| Started | Feb 08 08:28:08 AM UTC 25 |
| Finished | Feb 08 08:29:00 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318876358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255. prim_prince_test.2318876358 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/255.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2665413582 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2826195820 ps |
| CPU time | 52.24 seconds |
| Started | Feb 08 08:28:11 AM UTC 25 |
| Finished | Feb 08 08:29:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665413582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256. prim_prince_test.2665413582 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/256.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.3298598833 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2026656998 ps |
| CPU time | 37.15 seconds |
| Started | Feb 08 08:28:19 AM UTC 25 |
| Finished | Feb 08 08:29:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298598833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257. prim_prince_test.3298598833 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/257.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.3018484030 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3247858729 ps |
| CPU time | 59.26 seconds |
| Started | Feb 08 08:28:20 AM UTC 25 |
| Finished | Feb 08 08:29:38 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018484030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258. prim_prince_test.3018484030 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/258.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.838873210 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2771612568 ps |
| CPU time | 51.11 seconds |
| Started | Feb 08 08:28:30 AM UTC 25 |
| Finished | Feb 08 08:29:36 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838873210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.p rim_prince_test.838873210 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/259.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.3981408932 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2151391460 ps |
| CPU time | 39.82 seconds |
| Started | Feb 08 08:13:13 AM UTC 25 |
| Finished | Feb 08 08:14:05 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981408932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.p rim_prince_test.3981408932 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/26.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.2472984113 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1270927903 ps |
| CPU time | 23.51 seconds |
| Started | Feb 08 08:28:31 AM UTC 25 |
| Finished | Feb 08 08:29:02 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472984113 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260. prim_prince_test.2472984113 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/260.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2790074947 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2058637662 ps |
| CPU time | 37.88 seconds |
| Started | Feb 08 08:28:43 AM UTC 25 |
| Finished | Feb 08 08:29:33 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790074947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261. prim_prince_test.2790074947 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/261.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.225877911 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 1825391127 ps |
| CPU time | 33.78 seconds |
| Started | Feb 08 08:28:43 AM UTC 25 |
| Finished | Feb 08 08:29:27 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225877911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.p rim_prince_test.225877911 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/262.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.490202467 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1450668620 ps |
| CPU time | 26.74 seconds |
| Started | Feb 08 08:28:48 AM UTC 25 |
| Finished | Feb 08 08:29:24 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490202467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.p rim_prince_test.490202467 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/263.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.2183754014 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2945695796 ps |
| CPU time | 53.78 seconds |
| Started | Feb 08 08:28:48 AM UTC 25 |
| Finished | Feb 08 08:29:58 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183754014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264. prim_prince_test.2183754014 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/264.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.2473489731 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3656627717 ps |
| CPU time | 66.83 seconds |
| Started | Feb 08 08:28:57 AM UTC 25 |
| Finished | Feb 08 08:30:24 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473489731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265. prim_prince_test.2473489731 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/265.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.4230139650 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1023308781 ps |
| CPU time | 19.08 seconds |
| Started | Feb 08 08:28:58 AM UTC 25 |
| Finished | Feb 08 08:29:24 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230139650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266. prim_prince_test.4230139650 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/266.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3537241614 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 958908075 ps |
| CPU time | 18.03 seconds |
| Started | Feb 08 08:29:01 AM UTC 25 |
| Finished | Feb 08 08:29:25 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537241614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267. prim_prince_test.3537241614 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/267.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.566854661 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3256467081 ps |
| CPU time | 59.4 seconds |
| Started | Feb 08 08:29:03 AM UTC 25 |
| Finished | Feb 08 08:30:20 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566854661 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.p rim_prince_test.566854661 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/268.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.1528851252 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1048961695 ps |
| CPU time | 19.8 seconds |
| Started | Feb 08 08:29:08 AM UTC 25 |
| Finished | Feb 08 08:29:34 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528851252 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269. prim_prince_test.1528851252 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/269.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.2521439309 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2664130082 ps |
| CPU time | 48.91 seconds |
| Started | Feb 08 08:13:15 AM UTC 25 |
| Finished | Feb 08 08:14:19 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521439309 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.p rim_prince_test.2521439309 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/27.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.27081882 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 1728247606 ps |
| CPU time | 31.65 seconds |
| Started | Feb 08 08:29:09 AM UTC 25 |
| Finished | Feb 08 08:29:51 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27081882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.pr im_prince_test.27081882 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/270.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.1001490805 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1813195848 ps |
| CPU time | 33.15 seconds |
| Started | Feb 08 08:29:20 AM UTC 25 |
| Finished | Feb 08 08:30:04 AM UTC 25 |
| Peak memory | 154544 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001490805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271. prim_prince_test.1001490805 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/271.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.3239259143 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2739591821 ps |
| CPU time | 50.07 seconds |
| Started | Feb 08 08:29:20 AM UTC 25 |
| Finished | Feb 08 08:30:26 AM UTC 25 |
| Peak memory | 154612 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239259143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272. prim_prince_test.3239259143 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/272.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.2905769166 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1624815102 ps |
| CPU time | 29.74 seconds |
| Started | Feb 08 08:29:24 AM UTC 25 |
| Finished | Feb 08 08:30:04 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905769166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273. prim_prince_test.2905769166 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/273.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.2838065172 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 3286369965 ps |
| CPU time | 60.09 seconds |
| Started | Feb 08 08:29:25 AM UTC 25 |
| Finished | Feb 08 08:30:44 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838065172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274. prim_prince_test.2838065172 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/274.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.1807328197 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3430590684 ps |
| CPU time | 62.47 seconds |
| Started | Feb 08 08:29:25 AM UTC 25 |
| Finished | Feb 08 08:30:47 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807328197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275. prim_prince_test.1807328197 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/275.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.2077734921 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1429181171 ps |
| CPU time | 26.37 seconds |
| Started | Feb 08 08:29:29 AM UTC 25 |
| Finished | Feb 08 08:30:04 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077734921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276. prim_prince_test.2077734921 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/276.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.4115133957 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2296175576 ps |
| CPU time | 42.29 seconds |
| Started | Feb 08 08:29:34 AM UTC 25 |
| Finished | Feb 08 08:30:29 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115133957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277. prim_prince_test.4115133957 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/277.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.1412312519 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3501940033 ps |
| CPU time | 63.62 seconds |
| Started | Feb 08 08:29:35 AM UTC 25 |
| Finished | Feb 08 08:30:58 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412312519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278. prim_prince_test.1412312519 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/278.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.204830797 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3094237736 ps |
| CPU time | 56.32 seconds |
| Started | Feb 08 08:29:37 AM UTC 25 |
| Finished | Feb 08 08:30:51 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204830797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.p rim_prince_test.204830797 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/279.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.615194628 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3250301068 ps |
| CPU time | 59.56 seconds |
| Started | Feb 08 08:13:23 AM UTC 25 |
| Finished | Feb 08 08:14:41 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615194628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pr im_prince_test.615194628 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/28.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.1262510263 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 911569125 ps |
| CPU time | 16.79 seconds |
| Started | Feb 08 08:29:39 AM UTC 25 |
| Finished | Feb 08 08:30:02 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262510263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280. prim_prince_test.1262510263 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/280.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2937765354 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1068478405 ps |
| CPU time | 19.77 seconds |
| Started | Feb 08 08:29:52 AM UTC 25 |
| Finished | Feb 08 08:30:19 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937765354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281. prim_prince_test.2937765354 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/281.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.4175985872 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3178768814 ps |
| CPU time | 58.5 seconds |
| Started | Feb 08 08:29:59 AM UTC 25 |
| Finished | Feb 08 08:31:15 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175985872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282. prim_prince_test.4175985872 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/282.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.1373401719 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1812992549 ps |
| CPU time | 33.62 seconds |
| Started | Feb 08 08:30:03 AM UTC 25 |
| Finished | Feb 08 08:30:47 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373401719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283. prim_prince_test.1373401719 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/283.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3015898844 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3670075355 ps |
| CPU time | 66.84 seconds |
| Started | Feb 08 08:30:05 AM UTC 25 |
| Finished | Feb 08 08:31:32 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015898844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284. prim_prince_test.3015898844 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/284.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.4034143570 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1638295060 ps |
| CPU time | 30.07 seconds |
| Started | Feb 08 08:30:05 AM UTC 25 |
| Finished | Feb 08 08:30:45 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034143570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285. prim_prince_test.4034143570 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/285.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3774791973 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2280034045 ps |
| CPU time | 42.21 seconds |
| Started | Feb 08 08:30:05 AM UTC 25 |
| Finished | Feb 08 08:31:01 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774791973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286. prim_prince_test.3774791973 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/286.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.1162827727 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2422007411 ps |
| CPU time | 44.39 seconds |
| Started | Feb 08 08:30:20 AM UTC 25 |
| Finished | Feb 08 08:31:18 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162827727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287. prim_prince_test.1162827727 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/287.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.308635068 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2537391688 ps |
| CPU time | 46.58 seconds |
| Started | Feb 08 08:30:21 AM UTC 25 |
| Finished | Feb 08 08:31:22 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308635068 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.p rim_prince_test.308635068 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/288.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.1246408944 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3065818568 ps |
| CPU time | 56.13 seconds |
| Started | Feb 08 08:30:25 AM UTC 25 |
| Finished | Feb 08 08:31:39 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246408944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289. prim_prince_test.1246408944 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/289.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.56050804 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2998802355 ps |
| CPU time | 55.31 seconds |
| Started | Feb 08 08:13:26 AM UTC 25 |
| Finished | Feb 08 08:14:38 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56050804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pri m_prince_test.56050804 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/29.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.4180241505 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1160506856 ps |
| CPU time | 21.82 seconds |
| Started | Feb 08 08:30:26 AM UTC 25 |
| Finished | Feb 08 08:30:56 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180241505 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290. prim_prince_test.4180241505 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/290.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.1969690762 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1537559790 ps |
| CPU time | 28.57 seconds |
| Started | Feb 08 08:30:30 AM UTC 25 |
| Finished | Feb 08 08:31:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969690762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291. prim_prince_test.1969690762 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/291.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.1086026146 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2936257583 ps |
| CPU time | 53.92 seconds |
| Started | Feb 08 08:30:45 AM UTC 25 |
| Finished | Feb 08 08:31:56 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086026146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292. prim_prince_test.1086026146 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/292.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.1732301126 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2589010559 ps |
| CPU time | 47.36 seconds |
| Started | Feb 08 08:30:46 AM UTC 25 |
| Finished | Feb 08 08:31:49 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732301126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293. prim_prince_test.1732301126 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/293.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.154040016 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1193243421 ps |
| CPU time | 22.19 seconds |
| Started | Feb 08 08:30:48 AM UTC 25 |
| Finished | Feb 08 08:31:19 AM UTC 25 |
| Peak memory | 154488 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154040016 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.p rim_prince_test.154040016 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/294.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.976804321 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1532533387 ps |
| CPU time | 28.57 seconds |
| Started | Feb 08 08:30:48 AM UTC 25 |
| Finished | Feb 08 08:31:27 AM UTC 25 |
| Peak memory | 154540 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976804321 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.p rim_prince_test.976804321 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/295.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.1987687793 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2899512545 ps |
| CPU time | 53.03 seconds |
| Started | Feb 08 08:30:51 AM UTC 25 |
| Finished | Feb 08 08:32:01 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987687793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296. prim_prince_test.1987687793 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/296.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.3447897075 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1371785447 ps |
| CPU time | 25.21 seconds |
| Started | Feb 08 08:30:57 AM UTC 25 |
| Finished | Feb 08 08:31:32 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447897075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297. prim_prince_test.3447897075 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/297.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.3502036856 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3576528295 ps |
| CPU time | 64.97 seconds |
| Started | Feb 08 08:30:58 AM UTC 25 |
| Finished | Feb 08 08:32:24 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502036856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298. prim_prince_test.3502036856 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/298.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.2532768569 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1280764314 ps |
| CPU time | 23.71 seconds |
| Started | Feb 08 08:31:02 AM UTC 25 |
| Finished | Feb 08 08:31:34 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532768569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299. prim_prince_test.2532768569 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/299.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.646678326 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3137622987 ps |
| CPU time | 58.59 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:50 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646678326 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pri m_prince_test.646678326 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/3.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.3670332260 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1731102459 ps |
| CPU time | 31.94 seconds |
| Started | Feb 08 08:13:30 AM UTC 25 |
| Finished | Feb 08 08:14:12 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670332260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.p rim_prince_test.3670332260 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/30.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.4289256227 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2916847599 ps |
| CPU time | 53.31 seconds |
| Started | Feb 08 08:31:09 AM UTC 25 |
| Finished | Feb 08 08:32:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289256227 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 300. prim_prince_test.4289256227 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/300.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.1779956324 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3141323565 ps |
| CPU time | 57.51 seconds |
| Started | Feb 08 08:31:17 AM UTC 25 |
| Finished | Feb 08 08:32:32 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779956324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 301. prim_prince_test.1779956324 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/301.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.3955683509 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 772330829 ps |
| CPU time | 14.54 seconds |
| Started | Feb 08 08:31:19 AM UTC 25 |
| Finished | Feb 08 08:31:39 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955683509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 302. prim_prince_test.3955683509 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/302.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.3609252211 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3059101127 ps |
| CPU time | 55.93 seconds |
| Started | Feb 08 08:31:20 AM UTC 25 |
| Finished | Feb 08 08:32:33 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609252211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 303. prim_prince_test.3609252211 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/303.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.2227231028 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2912978688 ps |
| CPU time | 53.08 seconds |
| Started | Feb 08 08:31:23 AM UTC 25 |
| Finished | Feb 08 08:32:33 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227231028 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 304. prim_prince_test.2227231028 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/304.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.267419391 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1428883398 ps |
| CPU time | 26.55 seconds |
| Started | Feb 08 08:31:27 AM UTC 25 |
| Finished | Feb 08 08:32:03 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267419391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 305.p rim_prince_test.267419391 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/305.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.880452021 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1919765281 ps |
| CPU time | 35.13 seconds |
| Started | Feb 08 08:31:33 AM UTC 25 |
| Finished | Feb 08 08:32:20 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880452021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 306.p rim_prince_test.880452021 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/306.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.4275353142 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3502673558 ps |
| CPU time | 64.4 seconds |
| Started | Feb 08 08:31:33 AM UTC 25 |
| Finished | Feb 08 08:32:57 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275353142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 307. prim_prince_test.4275353142 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/307.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2403358774 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1647944349 ps |
| CPU time | 30.13 seconds |
| Started | Feb 08 08:31:35 AM UTC 25 |
| Finished | Feb 08 08:32:15 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403358774 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 308. prim_prince_test.2403358774 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/308.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.1954546985 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3466069140 ps |
| CPU time | 63.17 seconds |
| Started | Feb 08 08:31:40 AM UTC 25 |
| Finished | Feb 08 08:33:03 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954546985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 309. prim_prince_test.1954546985 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/309.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.1317457958 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3527892219 ps |
| CPU time | 64.58 seconds |
| Started | Feb 08 08:13:37 AM UTC 25 |
| Finished | Feb 08 08:15:01 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317457958 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.p rim_prince_test.1317457958 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/31.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.2680916341 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2108986043 ps |
| CPU time | 38.85 seconds |
| Started | Feb 08 08:31:40 AM UTC 25 |
| Finished | Feb 08 08:32:31 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680916341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 310. prim_prince_test.2680916341 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/310.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.2005960122 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2913341986 ps |
| CPU time | 53.22 seconds |
| Started | Feb 08 08:31:49 AM UTC 25 |
| Finished | Feb 08 08:32:59 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005960122 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 311. prim_prince_test.2005960122 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/311.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.4070731778 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1273501925 ps |
| CPU time | 23.49 seconds |
| Started | Feb 08 08:31:56 AM UTC 25 |
| Finished | Feb 08 08:32:28 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070731778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 312. prim_prince_test.4070731778 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/312.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.3575623306 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1487705185 ps |
| CPU time | 27.28 seconds |
| Started | Feb 08 08:32:02 AM UTC 25 |
| Finished | Feb 08 08:32:39 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575623306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 313. prim_prince_test.3575623306 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/313.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.2720388121 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3709710977 ps |
| CPU time | 67.35 seconds |
| Started | Feb 08 08:32:04 AM UTC 25 |
| Finished | Feb 08 08:33:31 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720388121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 314. prim_prince_test.2720388121 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/314.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.1530601093 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1983655891 ps |
| CPU time | 36.4 seconds |
| Started | Feb 08 08:32:16 AM UTC 25 |
| Finished | Feb 08 08:33:04 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530601093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 315. prim_prince_test.1530601093 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/315.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.93994237 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3216493564 ps |
| CPU time | 58.75 seconds |
| Started | Feb 08 08:32:20 AM UTC 25 |
| Finished | Feb 08 08:33:37 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93994237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 316.pr im_prince_test.93994237 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/316.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2572587827 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1327817508 ps |
| CPU time | 24.52 seconds |
| Started | Feb 08 08:32:21 AM UTC 25 |
| Finished | Feb 08 08:32:54 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572587827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 317. prim_prince_test.2572587827 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/317.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.283931961 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2124630617 ps |
| CPU time | 38.63 seconds |
| Started | Feb 08 08:32:25 AM UTC 25 |
| Finished | Feb 08 08:33:16 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283931961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 318.p rim_prince_test.283931961 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/318.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1625956677 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 990196671 ps |
| CPU time | 18.45 seconds |
| Started | Feb 08 08:32:29 AM UTC 25 |
| Finished | Feb 08 08:32:54 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625956677 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 319. prim_prince_test.1625956677 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/319.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.2456635846 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1128779070 ps |
| CPU time | 20.91 seconds |
| Started | Feb 08 08:13:45 AM UTC 25 |
| Finished | Feb 08 08:14:13 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456635846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.p rim_prince_test.2456635846 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/32.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.2638905833 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 828088350 ps |
| CPU time | 15.43 seconds |
| Started | Feb 08 08:32:32 AM UTC 25 |
| Finished | Feb 08 08:32:54 AM UTC 25 |
| Peak memory | 154580 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638905833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 320. prim_prince_test.2638905833 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/320.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.503766339 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 839100670 ps |
| CPU time | 15.73 seconds |
| Started | Feb 08 08:32:33 AM UTC 25 |
| Finished | Feb 08 08:32:54 AM UTC 25 |
| Peak memory | 154584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503766339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 321.p rim_prince_test.503766339 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/321.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.341079304 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 3401737602 ps |
| CPU time | 62.17 seconds |
| Started | Feb 08 08:32:34 AM UTC 25 |
| Finished | Feb 08 08:33:55 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341079304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 322.p rim_prince_test.341079304 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/322.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.2402262777 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1236461044 ps |
| CPU time | 22.97 seconds |
| Started | Feb 08 08:32:35 AM UTC 25 |
| Finished | Feb 08 08:33:05 AM UTC 25 |
| Peak memory | 154572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402262777 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 323. prim_prince_test.2402262777 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/323.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.2131779191 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1009115481 ps |
| CPU time | 18.72 seconds |
| Started | Feb 08 08:32:40 AM UTC 25 |
| Finished | Feb 08 08:33:05 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131779191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 324. prim_prince_test.2131779191 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/324.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.785012427 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2319214048 ps |
| CPU time | 42.63 seconds |
| Started | Feb 08 08:32:54 AM UTC 25 |
| Finished | Feb 08 08:33:50 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785012427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 325.p rim_prince_test.785012427 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/325.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.2475320052 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1317440833 ps |
| CPU time | 24.39 seconds |
| Started | Feb 08 08:32:55 AM UTC 25 |
| Finished | Feb 08 08:33:28 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475320052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 326. prim_prince_test.2475320052 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/326.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.725455740 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1676034826 ps |
| CPU time | 30.82 seconds |
| Started | Feb 08 08:32:55 AM UTC 25 |
| Finished | Feb 08 08:33:36 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725455740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 327.p rim_prince_test.725455740 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/327.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.1262782359 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 3440819962 ps |
| CPU time | 62.86 seconds |
| Started | Feb 08 08:32:55 AM UTC 25 |
| Finished | Feb 08 08:34:17 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262782359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 328. prim_prince_test.1262782359 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/328.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.1005766787 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2822770380 ps |
| CPU time | 51.68 seconds |
| Started | Feb 08 08:32:58 AM UTC 25 |
| Finished | Feb 08 08:34:05 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005766787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 329. prim_prince_test.1005766787 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/329.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.1399382518 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1856622488 ps |
| CPU time | 34.37 seconds |
| Started | Feb 08 08:13:50 AM UTC 25 |
| Finished | Feb 08 08:14:36 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399382518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.p rim_prince_test.1399382518 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/33.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1820554750 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3737241555 ps |
| CPU time | 68.22 seconds |
| Started | Feb 08 08:33:00 AM UTC 25 |
| Finished | Feb 08 08:34:29 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820554750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 330. prim_prince_test.1820554750 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/330.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.3267465792 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2050016169 ps |
| CPU time | 37.93 seconds |
| Started | Feb 08 08:33:04 AM UTC 25 |
| Finished | Feb 08 08:33:54 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267465792 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 331. prim_prince_test.3267465792 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/331.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.1054079547 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 3169221457 ps |
| CPU time | 58.15 seconds |
| Started | Feb 08 08:33:05 AM UTC 25 |
| Finished | Feb 08 08:34:21 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054079547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 332. prim_prince_test.1054079547 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/332.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.3595754267 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3240741786 ps |
| CPU time | 59.43 seconds |
| Started | Feb 08 08:33:06 AM UTC 25 |
| Finished | Feb 08 08:34:24 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595754267 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 333. prim_prince_test.3595754267 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/333.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.218123997 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 2550898428 ps |
| CPU time | 46.86 seconds |
| Started | Feb 08 08:33:06 AM UTC 25 |
| Finished | Feb 08 08:34:08 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218123997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 334.p rim_prince_test.218123997 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/334.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.1908677418 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1042278584 ps |
| CPU time | 19.28 seconds |
| Started | Feb 08 08:33:17 AM UTC 25 |
| Finished | Feb 08 08:33:44 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908677418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 335. prim_prince_test.1908677418 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/335.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.1195589398 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 3621797551 ps |
| CPU time | 66.06 seconds |
| Started | Feb 08 08:33:29 AM UTC 25 |
| Finished | Feb 08 08:34:55 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195589398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 336. prim_prince_test.1195589398 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/336.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.3469671378 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3043238126 ps |
| CPU time | 55.97 seconds |
| Started | Feb 08 08:33:33 AM UTC 25 |
| Finished | Feb 08 08:34:46 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469671378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 337. prim_prince_test.3469671378 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/337.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.3670199588 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2739556639 ps |
| CPU time | 49.87 seconds |
| Started | Feb 08 08:33:37 AM UTC 25 |
| Finished | Feb 08 08:34:43 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670199588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 338. prim_prince_test.3670199588 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/338.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3695814225 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3238258488 ps |
| CPU time | 59.13 seconds |
| Started | Feb 08 08:33:38 AM UTC 25 |
| Finished | Feb 08 08:34:57 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695814225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 339. prim_prince_test.3695814225 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/339.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.2548748918 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1157924366 ps |
| CPU time | 21.58 seconds |
| Started | Feb 08 08:13:51 AM UTC 25 |
| Finished | Feb 08 08:14:20 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548748918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.p rim_prince_test.2548748918 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/34.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.1992145503 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3245816263 ps |
| CPU time | 59.38 seconds |
| Started | Feb 08 08:33:45 AM UTC 25 |
| Finished | Feb 08 08:35:03 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992145503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 340. prim_prince_test.1992145503 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/340.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.183709449 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 819404463 ps |
| CPU time | 15.18 seconds |
| Started | Feb 08 08:33:50 AM UTC 25 |
| Finished | Feb 08 08:34:12 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183709449 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 341.p rim_prince_test.183709449 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/341.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.291844856 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1893137534 ps |
| CPU time | 34.81 seconds |
| Started | Feb 08 08:33:54 AM UTC 25 |
| Finished | Feb 08 08:34:42 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291844856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 342.p rim_prince_test.291844856 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/342.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.4045004967 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2460239873 ps |
| CPU time | 45.25 seconds |
| Started | Feb 08 08:33:56 AM UTC 25 |
| Finished | Feb 08 08:34:57 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045004967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 343. prim_prince_test.4045004967 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/343.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.3329291550 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3340361145 ps |
| CPU time | 61.39 seconds |
| Started | Feb 08 08:34:06 AM UTC 25 |
| Finished | Feb 08 08:35:26 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329291550 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 344. prim_prince_test.3329291550 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/344.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.1770115992 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 2944062907 ps |
| CPU time | 53.35 seconds |
| Started | Feb 08 08:34:09 AM UTC 25 |
| Finished | Feb 08 08:35:19 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770115992 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 345. prim_prince_test.1770115992 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/345.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.4163524662 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1547657543 ps |
| CPU time | 28.41 seconds |
| Started | Feb 08 08:34:13 AM UTC 25 |
| Finished | Feb 08 08:34:51 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163524662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 346. prim_prince_test.4163524662 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/346.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.1621580087 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2916074132 ps |
| CPU time | 53.33 seconds |
| Started | Feb 08 08:34:18 AM UTC 25 |
| Finished | Feb 08 08:35:28 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621580087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 347. prim_prince_test.1621580087 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/347.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.2132760049 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1599952959 ps |
| CPU time | 29.28 seconds |
| Started | Feb 08 08:34:22 AM UTC 25 |
| Finished | Feb 08 08:35:02 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132760049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 348. prim_prince_test.2132760049 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/348.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.942095202 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 768869181 ps |
| CPU time | 14.36 seconds |
| Started | Feb 08 08:34:25 AM UTC 25 |
| Finished | Feb 08 08:34:45 AM UTC 25 |
| Peak memory | 154584 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942095202 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 349.p rim_prince_test.942095202 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/349.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.1889361342 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3576847085 ps |
| CPU time | 65.37 seconds |
| Started | Feb 08 08:13:51 AM UTC 25 |
| Finished | Feb 08 08:15:16 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889361342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.p rim_prince_test.1889361342 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/35.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.796052973 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 975990166 ps |
| CPU time | 18.15 seconds |
| Started | Feb 08 08:34:30 AM UTC 25 |
| Finished | Feb 08 08:34:55 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796052973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 350.p rim_prince_test.796052973 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/350.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.472680191 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2357500327 ps |
| CPU time | 42.96 seconds |
| Started | Feb 08 08:34:43 AM UTC 25 |
| Finished | Feb 08 08:35:40 AM UTC 25 |
| Peak memory | 156532 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472680191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 351.p rim_prince_test.472680191 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/351.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.1767624890 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3661194087 ps |
| CPU time | 66.7 seconds |
| Started | Feb 08 08:34:44 AM UTC 25 |
| Finished | Feb 08 08:36:11 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767624890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 352. prim_prince_test.1767624890 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/352.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.2753933493 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 3120555108 ps |
| CPU time | 56.8 seconds |
| Started | Feb 08 08:34:46 AM UTC 25 |
| Finished | Feb 08 08:36:00 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753933493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 353. prim_prince_test.2753933493 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/353.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.2649066094 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1998322501 ps |
| CPU time | 36.31 seconds |
| Started | Feb 08 08:34:47 AM UTC 25 |
| Finished | Feb 08 08:35:36 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649066094 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 354. prim_prince_test.2649066094 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/354.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.38350029 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2939965233 ps |
| CPU time | 53.54 seconds |
| Started | Feb 08 08:34:52 AM UTC 25 |
| Finished | Feb 08 08:36:03 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38350029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 355.pr im_prince_test.38350029 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/355.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.3529664071 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3519177125 ps |
| CPU time | 64.34 seconds |
| Started | Feb 08 08:34:56 AM UTC 25 |
| Finished | Feb 08 08:36:20 AM UTC 25 |
| Peak memory | 154608 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529664071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 356. prim_prince_test.3529664071 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/356.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.572061905 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 1622481106 ps |
| CPU time | 29.67 seconds |
| Started | Feb 08 08:34:56 AM UTC 25 |
| Finished | Feb 08 08:35:35 AM UTC 25 |
| Peak memory | 154576 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572061905 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 357.p rim_prince_test.572061905 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/357.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2345176120 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3376295156 ps |
| CPU time | 61.26 seconds |
| Started | Feb 08 08:34:58 AM UTC 25 |
| Finished | Feb 08 08:36:18 AM UTC 25 |
| Peak memory | 156112 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345176120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 358. prim_prince_test.2345176120 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/358.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.2501569143 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2163524370 ps |
| CPU time | 39.84 seconds |
| Started | Feb 08 08:34:58 AM UTC 25 |
| Finished | Feb 08 08:35:51 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501569143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 359. prim_prince_test.2501569143 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/359.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.586805876 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3018260071 ps |
| CPU time | 55.23 seconds |
| Started | Feb 08 08:13:56 AM UTC 25 |
| Finished | Feb 08 08:15:08 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586805876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pr im_prince_test.586805876 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/36.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.3894910144 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 1124715380 ps |
| CPU time | 20.78 seconds |
| Started | Feb 08 08:35:03 AM UTC 25 |
| Finished | Feb 08 08:35:31 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894910144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 360. prim_prince_test.3894910144 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/360.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.3559365673 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3588988550 ps |
| CPU time | 65.46 seconds |
| Started | Feb 08 08:35:04 AM UTC 25 |
| Finished | Feb 08 08:36:30 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559365673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 361. prim_prince_test.3559365673 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/361.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.456481304 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2201574335 ps |
| CPU time | 39.98 seconds |
| Started | Feb 08 08:35:20 AM UTC 25 |
| Finished | Feb 08 08:36:13 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456481304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 362.p rim_prince_test.456481304 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/362.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.929856338 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3251483734 ps |
| CPU time | 59.03 seconds |
| Started | Feb 08 08:35:28 AM UTC 25 |
| Finished | Feb 08 08:36:45 AM UTC 25 |
| Peak memory | 156568 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929856338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 363.p rim_prince_test.929856338 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/363.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.472107370 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1005971782 ps |
| CPU time | 18.52 seconds |
| Started | Feb 08 08:35:29 AM UTC 25 |
| Finished | Feb 08 08:35:54 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472107370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 364.p rim_prince_test.472107370 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/364.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.4157365525 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3536518007 ps |
| CPU time | 64.47 seconds |
| Started | Feb 08 08:35:32 AM UTC 25 |
| Finished | Feb 08 08:36:56 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157365525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 365. prim_prince_test.4157365525 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/365.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.2806276349 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1240618076 ps |
| CPU time | 22.87 seconds |
| Started | Feb 08 08:35:36 AM UTC 25 |
| Finished | Feb 08 08:36:07 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806276349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 366. prim_prince_test.2806276349 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/366.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.1383268725 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3071962370 ps |
| CPU time | 56.1 seconds |
| Started | Feb 08 08:35:37 AM UTC 25 |
| Finished | Feb 08 08:36:51 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383268725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 367. prim_prince_test.1383268725 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/367.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.253298991 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 1179825655 ps |
| CPU time | 21.72 seconds |
| Started | Feb 08 08:35:41 AM UTC 25 |
| Finished | Feb 08 08:36:11 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253298991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 368.p rim_prince_test.253298991 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/368.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.3634851826 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1337518130 ps |
| CPU time | 24.63 seconds |
| Started | Feb 08 08:35:52 AM UTC 25 |
| Finished | Feb 08 08:36:24 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634851826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 369. prim_prince_test.3634851826 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/369.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.1498789439 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2977701579 ps |
| CPU time | 54.67 seconds |
| Started | Feb 08 08:14:05 AM UTC 25 |
| Finished | Feb 08 08:15:16 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498789439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.p rim_prince_test.1498789439 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/37.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.97155387 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2939596264 ps |
| CPU time | 54.24 seconds |
| Started | Feb 08 08:35:55 AM UTC 25 |
| Finished | Feb 08 08:37:05 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97155387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 370.pr im_prince_test.97155387 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/370.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.3616530452 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3510621829 ps |
| CPU time | 64 seconds |
| Started | Feb 08 08:36:01 AM UTC 25 |
| Finished | Feb 08 08:37:24 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616530452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 371. prim_prince_test.3616530452 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/371.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.130932360 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2533862444 ps |
| CPU time | 46.64 seconds |
| Started | Feb 08 08:36:04 AM UTC 25 |
| Finished | Feb 08 08:37:05 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130932360 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 372.p rim_prince_test.130932360 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/372.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2961106045 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2127823373 ps |
| CPU time | 39.29 seconds |
| Started | Feb 08 08:36:08 AM UTC 25 |
| Finished | Feb 08 08:37:00 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961106045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 373. prim_prince_test.2961106045 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/373.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.3336460395 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3499571759 ps |
| CPU time | 63.98 seconds |
| Started | Feb 08 08:36:11 AM UTC 25 |
| Finished | Feb 08 08:37:34 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336460395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 374. prim_prince_test.3336460395 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/374.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.3583188514 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2049346815 ps |
| CPU time | 37.99 seconds |
| Started | Feb 08 08:36:12 AM UTC 25 |
| Finished | Feb 08 08:37:03 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583188514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 375. prim_prince_test.3583188514 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/375.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2603033533 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1296110891 ps |
| CPU time | 24.12 seconds |
| Started | Feb 08 08:36:15 AM UTC 25 |
| Finished | Feb 08 08:36:47 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603033533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 376. prim_prince_test.2603033533 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/376.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1260904229 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3395346984 ps |
| CPU time | 61.99 seconds |
| Started | Feb 08 08:36:19 AM UTC 25 |
| Finished | Feb 08 08:37:40 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260904229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 377. prim_prince_test.1260904229 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/377.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.967761466 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3169933333 ps |
| CPU time | 58.07 seconds |
| Started | Feb 08 08:36:20 AM UTC 25 |
| Finished | Feb 08 08:37:36 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967761466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 378.p rim_prince_test.967761466 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/378.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.446634889 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 997733278 ps |
| CPU time | 18.63 seconds |
| Started | Feb 08 08:36:25 AM UTC 25 |
| Finished | Feb 08 08:36:51 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446634889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 379.p rim_prince_test.446634889 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/379.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.4030238819 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2312108128 ps |
| CPU time | 42.48 seconds |
| Started | Feb 08 08:14:12 AM UTC 25 |
| Finished | Feb 08 08:15:08 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030238819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.p rim_prince_test.4030238819 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/38.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.1780686883 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 1833620183 ps |
| CPU time | 33.75 seconds |
| Started | Feb 08 08:36:30 AM UTC 25 |
| Finished | Feb 08 08:37:15 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780686883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 380. prim_prince_test.1780686883 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/380.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.2653440442 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2174796009 ps |
| CPU time | 39.78 seconds |
| Started | Feb 08 08:36:46 AM UTC 25 |
| Finished | Feb 08 08:37:40 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653440442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 381. prim_prince_test.2653440442 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/381.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.2323037815 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2763087829 ps |
| CPU time | 50.1 seconds |
| Started | Feb 08 08:36:48 AM UTC 25 |
| Finished | Feb 08 08:37:54 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323037815 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 382. prim_prince_test.2323037815 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/382.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2377922703 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3063688543 ps |
| CPU time | 55.95 seconds |
| Started | Feb 08 08:36:52 AM UTC 25 |
| Finished | Feb 08 08:38:05 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377922703 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 383. prim_prince_test.2377922703 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/383.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.852706382 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2209392739 ps |
| CPU time | 40.69 seconds |
| Started | Feb 08 08:36:52 AM UTC 25 |
| Finished | Feb 08 08:37:46 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852706382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 384.p rim_prince_test.852706382 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/384.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.3500869798 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2055181956 ps |
| CPU time | 37.58 seconds |
| Started | Feb 08 08:36:57 AM UTC 25 |
| Finished | Feb 08 08:37:47 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500869798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 385. prim_prince_test.3500869798 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/385.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.1990200359 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2576666554 ps |
| CPU time | 47.32 seconds |
| Started | Feb 08 08:37:00 AM UTC 25 |
| Finished | Feb 08 08:38:02 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990200359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 386. prim_prince_test.1990200359 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/386.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.2419002315 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2596722408 ps |
| CPU time | 47.92 seconds |
| Started | Feb 08 08:37:03 AM UTC 25 |
| Finished | Feb 08 08:38:06 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419002315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 387. prim_prince_test.2419002315 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/387.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.1462548203 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1160494361 ps |
| CPU time | 21.47 seconds |
| Started | Feb 08 08:37:07 AM UTC 25 |
| Finished | Feb 08 08:37:36 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462548203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 388. prim_prince_test.1462548203 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/388.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.762922494 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 1022950371 ps |
| CPU time | 19.08 seconds |
| Started | Feb 08 08:37:07 AM UTC 25 |
| Finished | Feb 08 08:37:32 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762922494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 389.p rim_prince_test.762922494 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/389.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.2425972599 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3375211859 ps |
| CPU time | 61.62 seconds |
| Started | Feb 08 08:14:14 AM UTC 25 |
| Finished | Feb 08 08:15:34 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425972599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.p rim_prince_test.2425972599 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/39.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.333410641 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2457207104 ps |
| CPU time | 45.11 seconds |
| Started | Feb 08 08:37:16 AM UTC 25 |
| Finished | Feb 08 08:38:15 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333410641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 390.p rim_prince_test.333410641 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/390.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1795950663 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2310834300 ps |
| CPU time | 42.5 seconds |
| Started | Feb 08 08:37:25 AM UTC 25 |
| Finished | Feb 08 08:38:21 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795950663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 391. prim_prince_test.1795950663 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/391.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.592686927 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1931575616 ps |
| CPU time | 35.39 seconds |
| Started | Feb 08 08:37:33 AM UTC 25 |
| Finished | Feb 08 08:38:20 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592686927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 392.p rim_prince_test.592686927 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/392.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.1636237870 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1247196063 ps |
| CPU time | 23.17 seconds |
| Started | Feb 08 08:37:35 AM UTC 25 |
| Finished | Feb 08 08:38:06 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636237870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 393. prim_prince_test.1636237870 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/393.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.158928110 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 1926578455 ps |
| CPU time | 35.23 seconds |
| Started | Feb 08 08:37:37 AM UTC 25 |
| Finished | Feb 08 08:38:23 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158928110 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 394.p rim_prince_test.158928110 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/394.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3544273290 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1522381195 ps |
| CPU time | 27.89 seconds |
| Started | Feb 08 08:37:37 AM UTC 25 |
| Finished | Feb 08 08:38:14 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544273290 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 395. prim_prince_test.3544273290 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/395.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.3192491452 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1867338154 ps |
| CPU time | 34.76 seconds |
| Started | Feb 08 08:37:41 AM UTC 25 |
| Finished | Feb 08 08:38:27 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192491452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 396. prim_prince_test.3192491452 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/396.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.11687850 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3101741426 ps |
| CPU time | 57.09 seconds |
| Started | Feb 08 08:37:41 AM UTC 25 |
| Finished | Feb 08 08:38:55 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11687850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 397.pr im_prince_test.11687850 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/397.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.951447582 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 1396394000 ps |
| CPU time | 25.71 seconds |
| Started | Feb 08 08:37:47 AM UTC 25 |
| Finished | Feb 08 08:38:22 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951447582 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 398.p rim_prince_test.951447582 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/398.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.1152216722 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2930231757 ps |
| CPU time | 53.83 seconds |
| Started | Feb 08 08:37:47 AM UTC 25 |
| Finished | Feb 08 08:38:58 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152216722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 399. prim_prince_test.1152216722 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/399.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.2734027389 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2471522470 ps |
| CPU time | 46.44 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:34 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734027389 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pr im_prince_test.2734027389 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/4.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.1677212988 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2734915080 ps |
| CPU time | 50.02 seconds |
| Started | Feb 08 08:14:15 AM UTC 25 |
| Finished | Feb 08 08:15:20 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677212988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.p rim_prince_test.1677212988 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/40.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.717837883 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1260093051 ps |
| CPU time | 23.42 seconds |
| Started | Feb 08 08:37:54 AM UTC 25 |
| Finished | Feb 08 08:38:26 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717837883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 400.p rim_prince_test.717837883 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/400.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.298303744 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3237471861 ps |
| CPU time | 58.93 seconds |
| Started | Feb 08 08:38:04 AM UTC 25 |
| Finished | Feb 08 08:39:21 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298303744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 401.p rim_prince_test.298303744 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/401.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2573469678 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2425300270 ps |
| CPU time | 44.38 seconds |
| Started | Feb 08 08:38:07 AM UTC 25 |
| Finished | Feb 08 08:39:05 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573469678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 402. prim_prince_test.2573469678 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/402.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.1636133246 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2889039571 ps |
| CPU time | 52.63 seconds |
| Started | Feb 08 08:38:07 AM UTC 25 |
| Finished | Feb 08 08:39:16 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636133246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 403. prim_prince_test.1636133246 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/403.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3850273500 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2543318585 ps |
| CPU time | 46.54 seconds |
| Started | Feb 08 08:38:07 AM UTC 25 |
| Finished | Feb 08 08:39:08 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850273500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 404. prim_prince_test.3850273500 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/404.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.4280027348 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1452989707 ps |
| CPU time | 26.78 seconds |
| Started | Feb 08 08:38:14 AM UTC 25 |
| Finished | Feb 08 08:38:50 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280027348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 405. prim_prince_test.4280027348 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/405.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.222042439 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1236420285 ps |
| CPU time | 23.13 seconds |
| Started | Feb 08 08:38:16 AM UTC 25 |
| Finished | Feb 08 08:38:47 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222042439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 406.p rim_prince_test.222042439 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/406.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.1058517606 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1825026993 ps |
| CPU time | 33.41 seconds |
| Started | Feb 08 08:38:21 AM UTC 25 |
| Finished | Feb 08 08:39:05 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058517606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 407. prim_prince_test.1058517606 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/407.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.32146830 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1254359767 ps |
| CPU time | 23.18 seconds |
| Started | Feb 08 08:38:22 AM UTC 25 |
| Finished | Feb 08 08:38:53 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32146830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 408.pr im_prince_test.32146830 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/408.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.1957470027 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3649857452 ps |
| CPU time | 66.68 seconds |
| Started | Feb 08 08:38:23 AM UTC 25 |
| Finished | Feb 08 08:39:50 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957470027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 409. prim_prince_test.1957470027 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/409.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.1468458015 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2329252338 ps |
| CPU time | 42.73 seconds |
| Started | Feb 08 08:14:15 AM UTC 25 |
| Finished | Feb 08 08:15:10 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468458015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.p rim_prince_test.1468458015 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/41.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.2023619632 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1287903896 ps |
| CPU time | 23.77 seconds |
| Started | Feb 08 08:38:24 AM UTC 25 |
| Finished | Feb 08 08:38:56 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023619632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 410. prim_prince_test.2023619632 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/410.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.1773373624 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2669076385 ps |
| CPU time | 48.91 seconds |
| Started | Feb 08 08:38:26 AM UTC 25 |
| Finished | Feb 08 08:39:30 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773373624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 411. prim_prince_test.1773373624 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/411.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.2386344120 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3162294605 ps |
| CPU time | 57.43 seconds |
| Started | Feb 08 08:38:27 AM UTC 25 |
| Finished | Feb 08 08:39:42 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386344120 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 412. prim_prince_test.2386344120 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/412.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.4042307299 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2616763641 ps |
| CPU time | 47.62 seconds |
| Started | Feb 08 08:38:49 AM UTC 25 |
| Finished | Feb 08 08:39:51 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042307299 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 413. prim_prince_test.4042307299 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/413.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.1746557080 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2453395106 ps |
| CPU time | 44.76 seconds |
| Started | Feb 08 08:38:51 AM UTC 25 |
| Finished | Feb 08 08:39:49 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746557080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 414. prim_prince_test.1746557080 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/414.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.1787622849 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2989628392 ps |
| CPU time | 54.81 seconds |
| Started | Feb 08 08:38:54 AM UTC 25 |
| Finished | Feb 08 08:40:05 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787622849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 415. prim_prince_test.1787622849 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/415.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2565099887 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2803507115 ps |
| CPU time | 51.85 seconds |
| Started | Feb 08 08:38:56 AM UTC 25 |
| Finished | Feb 08 08:40:04 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565099887 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 416. prim_prince_test.2565099887 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/416.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.2930726804 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1777860715 ps |
| CPU time | 32.59 seconds |
| Started | Feb 08 08:38:57 AM UTC 25 |
| Finished | Feb 08 08:39:40 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930726804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 417. prim_prince_test.2930726804 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/417.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1656484330 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1895908421 ps |
| CPU time | 34.81 seconds |
| Started | Feb 08 08:38:58 AM UTC 25 |
| Finished | Feb 08 08:39:44 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656484330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 418. prim_prince_test.1656484330 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/418.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.1758706216 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 869500062 ps |
| CPU time | 16.23 seconds |
| Started | Feb 08 08:39:06 AM UTC 25 |
| Finished | Feb 08 08:39:28 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758706216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 419. prim_prince_test.1758706216 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/419.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.3871507036 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2422651089 ps |
| CPU time | 44.45 seconds |
| Started | Feb 08 08:14:20 AM UTC 25 |
| Finished | Feb 08 08:15:18 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871507036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.p rim_prince_test.3871507036 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/42.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.2415332005 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3320620129 ps |
| CPU time | 61.1 seconds |
| Started | Feb 08 08:39:07 AM UTC 25 |
| Finished | Feb 08 08:40:26 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415332005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 420. prim_prince_test.2415332005 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/420.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.580378770 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2518322402 ps |
| CPU time | 46.01 seconds |
| Started | Feb 08 08:39:09 AM UTC 25 |
| Finished | Feb 08 08:40:09 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580378770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 421.p rim_prince_test.580378770 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/421.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.3844657233 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 3710717786 ps |
| CPU time | 67.62 seconds |
| Started | Feb 08 08:39:17 AM UTC 25 |
| Finished | Feb 08 08:40:45 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844657233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 422. prim_prince_test.3844657233 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/422.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.1589668140 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1073847560 ps |
| CPU time | 19.95 seconds |
| Started | Feb 08 08:39:21 AM UTC 25 |
| Finished | Feb 08 08:39:48 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589668140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 423. prim_prince_test.1589668140 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/423.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.1179368700 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2845404488 ps |
| CPU time | 51.78 seconds |
| Started | Feb 08 08:39:28 AM UTC 25 |
| Finished | Feb 08 08:40:36 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179368700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 424. prim_prince_test.1179368700 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/424.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1944112442 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3416629964 ps |
| CPU time | 62.32 seconds |
| Started | Feb 08 08:39:32 AM UTC 25 |
| Finished | Feb 08 08:40:53 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944112442 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 425. prim_prince_test.1944112442 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/425.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.3867793985 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2231064094 ps |
| CPU time | 40.93 seconds |
| Started | Feb 08 08:39:42 AM UTC 25 |
| Finished | Feb 08 08:40:36 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867793985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 426. prim_prince_test.3867793985 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/426.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.3381708860 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3316689766 ps |
| CPU time | 60.75 seconds |
| Started | Feb 08 08:39:43 AM UTC 25 |
| Finished | Feb 08 08:41:02 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381708860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 427. prim_prince_test.3381708860 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/427.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2647107877 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3323034088 ps |
| CPU time | 60.63 seconds |
| Started | Feb 08 08:39:45 AM UTC 25 |
| Finished | Feb 08 08:41:04 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647107877 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 428. prim_prince_test.2647107877 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/428.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.4146684946 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2957373688 ps |
| CPU time | 53.99 seconds |
| Started | Feb 08 08:39:49 AM UTC 25 |
| Finished | Feb 08 08:41:00 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146684946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 429. prim_prince_test.4146684946 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/429.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.1481022996 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2124946557 ps |
| CPU time | 38.9 seconds |
| Started | Feb 08 08:14:21 AM UTC 25 |
| Finished | Feb 08 08:15:12 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481022996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.p rim_prince_test.1481022996 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/43.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.983245991 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 870125429 ps |
| CPU time | 16.08 seconds |
| Started | Feb 08 08:39:51 AM UTC 25 |
| Finished | Feb 08 08:40:13 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983245991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 430.p rim_prince_test.983245991 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/430.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.857370143 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2284451166 ps |
| CPU time | 41.84 seconds |
| Started | Feb 08 08:39:51 AM UTC 25 |
| Finished | Feb 08 08:40:46 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857370143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 431.p rim_prince_test.857370143 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/431.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1044895540 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 2761937207 ps |
| CPU time | 50.43 seconds |
| Started | Feb 08 08:39:52 AM UTC 25 |
| Finished | Feb 08 08:40:58 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044895540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 432. prim_prince_test.1044895540 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/432.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.1638313953 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1052615290 ps |
| CPU time | 19.65 seconds |
| Started | Feb 08 08:40:04 AM UTC 25 |
| Finished | Feb 08 08:40:31 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638313953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 433. prim_prince_test.1638313953 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/433.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.1330977956 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 1397501490 ps |
| CPU time | 25.76 seconds |
| Started | Feb 08 08:40:06 AM UTC 25 |
| Finished | Feb 08 08:40:41 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330977956 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 434. prim_prince_test.1330977956 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/434.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.268311692 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 3237429674 ps |
| CPU time | 59.18 seconds |
| Started | Feb 08 08:40:10 AM UTC 25 |
| Finished | Feb 08 08:41:28 AM UTC 25 |
| Peak memory | 156528 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268311692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 435.p rim_prince_test.268311692 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/435.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.2700218234 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1739247558 ps |
| CPU time | 31.94 seconds |
| Started | Feb 08 08:40:14 AM UTC 25 |
| Finished | Feb 08 08:40:56 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700218234 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 436. prim_prince_test.2700218234 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/436.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.3214412520 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2492680027 ps |
| CPU time | 45.4 seconds |
| Started | Feb 08 08:40:27 AM UTC 25 |
| Finished | Feb 08 08:41:26 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214412520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 437. prim_prince_test.3214412520 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/437.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.3882228387 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3425262137 ps |
| CPU time | 62.09 seconds |
| Started | Feb 08 08:40:32 AM UTC 25 |
| Finished | Feb 08 08:41:52 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882228387 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 438. prim_prince_test.3882228387 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/438.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.3609443840 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1320636152 ps |
| CPU time | 24.41 seconds |
| Started | Feb 08 08:40:37 AM UTC 25 |
| Finished | Feb 08 08:41:10 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609443840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 439. prim_prince_test.3609443840 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/439.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.332497869 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1797491255 ps |
| CPU time | 33.11 seconds |
| Started | Feb 08 08:14:23 AM UTC 25 |
| Finished | Feb 08 08:15:07 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332497869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pr im_prince_test.332497869 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/44.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.3461633084 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1418131255 ps |
| CPU time | 25.97 seconds |
| Started | Feb 08 08:40:37 AM UTC 25 |
| Finished | Feb 08 08:41:12 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461633084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 440. prim_prince_test.3461633084 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/440.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.503467429 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2628692563 ps |
| CPU time | 48.18 seconds |
| Started | Feb 08 08:40:42 AM UTC 25 |
| Finished | Feb 08 08:41:45 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503467429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 441.p rim_prince_test.503467429 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/441.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3912463188 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 800845856 ps |
| CPU time | 14.93 seconds |
| Started | Feb 08 08:40:47 AM UTC 25 |
| Finished | Feb 08 08:41:07 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912463188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 442. prim_prince_test.3912463188 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/442.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3490545578 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 882088894 ps |
| CPU time | 16.49 seconds |
| Started | Feb 08 08:40:47 AM UTC 25 |
| Finished | Feb 08 08:41:09 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490545578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 443. prim_prince_test.3490545578 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/443.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.2767542597 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3378341404 ps |
| CPU time | 61.92 seconds |
| Started | Feb 08 08:40:54 AM UTC 25 |
| Finished | Feb 08 08:42:13 AM UTC 25 |
| Peak memory | 156572 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767542597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 444. prim_prince_test.2767542597 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/444.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.942003990 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 839346488 ps |
| CPU time | 15.74 seconds |
| Started | Feb 08 08:40:57 AM UTC 25 |
| Finished | Feb 08 08:41:18 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942003990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 445.p rim_prince_test.942003990 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/445.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.1705349249 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2038863546 ps |
| CPU time | 37.48 seconds |
| Started | Feb 08 08:40:58 AM UTC 25 |
| Finished | Feb 08 08:41:47 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705349249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 446. prim_prince_test.1705349249 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/446.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.3968372243 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 983961161 ps |
| CPU time | 18.38 seconds |
| Started | Feb 08 08:41:00 AM UTC 25 |
| Finished | Feb 08 08:41:25 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968372243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 447. prim_prince_test.3968372243 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/447.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.695666261 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2708082982 ps |
| CPU time | 49.4 seconds |
| Started | Feb 08 08:41:03 AM UTC 25 |
| Finished | Feb 08 08:42:06 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695666261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 448.p rim_prince_test.695666261 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/448.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.2205061249 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2913097904 ps |
| CPU time | 53.53 seconds |
| Started | Feb 08 08:41:06 AM UTC 25 |
| Finished | Feb 08 08:42:15 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205061249 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 449. prim_prince_test.2205061249 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/449.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.109884322 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2711247507 ps |
| CPU time | 49.75 seconds |
| Started | Feb 08 08:14:36 AM UTC 25 |
| Finished | Feb 08 08:15:40 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109884322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pr im_prince_test.109884322 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/45.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2201356719 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 982843654 ps |
| CPU time | 18.24 seconds |
| Started | Feb 08 08:41:08 AM UTC 25 |
| Finished | Feb 08 08:41:33 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201356719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 450. prim_prince_test.2201356719 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/450.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.205584562 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 3207627547 ps |
| CPU time | 58.73 seconds |
| Started | Feb 08 08:41:10 AM UTC 25 |
| Finished | Feb 08 08:42:25 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205584562 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 451.p rim_prince_test.205584562 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/451.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.1220023747 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3637476042 ps |
| CPU time | 67.06 seconds |
| Started | Feb 08 08:41:11 AM UTC 25 |
| Finished | Feb 08 08:42:37 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220023747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 452. prim_prince_test.1220023747 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/452.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.2242149620 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2102379876 ps |
| CPU time | 38.97 seconds |
| Started | Feb 08 08:41:13 AM UTC 25 |
| Finished | Feb 08 08:42:04 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242149620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 453. prim_prince_test.2242149620 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/453.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.3678354883 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3146317467 ps |
| CPU time | 58.04 seconds |
| Started | Feb 08 08:41:20 AM UTC 25 |
| Finished | Feb 08 08:42:34 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678354883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 454. prim_prince_test.3678354883 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/454.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3498696173 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2258518800 ps |
| CPU time | 42.28 seconds |
| Started | Feb 08 08:41:26 AM UTC 25 |
| Finished | Feb 08 08:42:20 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498696173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 455. prim_prince_test.3498696173 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/455.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.310131041 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3172597374 ps |
| CPU time | 58.52 seconds |
| Started | Feb 08 08:41:27 AM UTC 25 |
| Finished | Feb 08 08:42:42 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310131041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 456.p rim_prince_test.310131041 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/456.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1321077732 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 1909843457 ps |
| CPU time | 35.34 seconds |
| Started | Feb 08 08:41:28 AM UTC 25 |
| Finished | Feb 08 08:42:14 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321077732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 457. prim_prince_test.1321077732 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/457.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.4048556830 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 988468690 ps |
| CPU time | 18.53 seconds |
| Started | Feb 08 08:41:31 AM UTC 25 |
| Finished | Feb 08 08:41:56 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048556830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 458. prim_prince_test.4048556830 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/458.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.3022440477 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 2523385939 ps |
| CPU time | 46.45 seconds |
| Started | Feb 08 08:41:32 AM UTC 25 |
| Finished | Feb 08 08:42:31 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022440477 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 459. prim_prince_test.3022440477 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/459.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.2507607140 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2503530497 ps |
| CPU time | 46.09 seconds |
| Started | Feb 08 08:14:39 AM UTC 25 |
| Finished | Feb 08 08:15:39 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507607140 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.p rim_prince_test.2507607140 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/46.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1885973091 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 1365024688 ps |
| CPU time | 25.12 seconds |
| Started | Feb 08 08:41:33 AM UTC 25 |
| Finished | Feb 08 08:42:06 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885973091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 460. prim_prince_test.1885973091 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/460.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.1090985698 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 893974073 ps |
| CPU time | 16.73 seconds |
| Started | Feb 08 08:41:34 AM UTC 25 |
| Finished | Feb 08 08:41:56 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090985698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 461. prim_prince_test.1090985698 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/461.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2522088112 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2306352603 ps |
| CPU time | 42.71 seconds |
| Started | Feb 08 08:41:34 AM UTC 25 |
| Finished | Feb 08 08:42:28 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522088112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 462. prim_prince_test.2522088112 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/462.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.1235680627 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1334645827 ps |
| CPU time | 24.88 seconds |
| Started | Feb 08 08:41:34 AM UTC 25 |
| Finished | Feb 08 08:42:06 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235680627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 463. prim_prince_test.1235680627 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/463.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.22306638 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 3250217241 ps |
| CPU time | 61.53 seconds |
| Started | Feb 08 08:41:34 AM UTC 25 |
| Finished | Feb 08 08:42:52 AM UTC 25 |
| Peak memory | 154672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22306638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 464.pr im_prince_test.22306638 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/464.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.130427684 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2256075038 ps |
| CPU time | 42 seconds |
| Started | Feb 08 08:41:35 AM UTC 25 |
| Finished | Feb 08 08:42:28 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130427684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 465.p rim_prince_test.130427684 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/465.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.2880996374 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2597591131 ps |
| CPU time | 48.06 seconds |
| Started | Feb 08 08:41:35 AM UTC 25 |
| Finished | Feb 08 08:42:36 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880996374 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 466. prim_prince_test.2880996374 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/466.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.2069180611 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2659388426 ps |
| CPU time | 49.61 seconds |
| Started | Feb 08 08:41:35 AM UTC 25 |
| Finished | Feb 08 08:42:38 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069180611 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 467. prim_prince_test.2069180611 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/467.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.771431944 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3203972674 ps |
| CPU time | 61.05 seconds |
| Started | Feb 08 08:41:36 AM UTC 25 |
| Finished | Feb 08 08:42:53 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771431944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 468.p rim_prince_test.771431944 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/468.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3180287385 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2076351779 ps |
| CPU time | 39.22 seconds |
| Started | Feb 08 08:41:36 AM UTC 25 |
| Finished | Feb 08 08:42:26 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180287385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 469. prim_prince_test.3180287385 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/469.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.3186260487 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 2924757800 ps |
| CPU time | 53.22 seconds |
| Started | Feb 08 08:14:41 AM UTC 25 |
| Finished | Feb 08 08:15:50 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186260487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.p rim_prince_test.3186260487 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/47.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.1035891574 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2462618974 ps |
| CPU time | 45.85 seconds |
| Started | Feb 08 08:41:36 AM UTC 25 |
| Finished | Feb 08 08:42:34 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035891574 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 470. prim_prince_test.1035891574 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/470.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.2993094451 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1431952841 ps |
| CPU time | 26.72 seconds |
| Started | Feb 08 08:41:37 AM UTC 25 |
| Finished | Feb 08 08:42:12 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993094451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 471. prim_prince_test.2993094451 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/471.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.4191366163 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 906853683 ps |
| CPU time | 17.01 seconds |
| Started | Feb 08 08:41:37 AM UTC 25 |
| Finished | Feb 08 08:42:00 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191366163 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 472. prim_prince_test.4191366163 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/472.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3533849077 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3018664119 ps |
| CPU time | 56.31 seconds |
| Started | Feb 08 08:41:37 AM UTC 25 |
| Finished | Feb 08 08:42:49 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533849077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 473. prim_prince_test.3533849077 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/473.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.2070141515 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1042985556 ps |
| CPU time | 19.53 seconds |
| Started | Feb 08 08:41:37 AM UTC 25 |
| Finished | Feb 08 08:42:03 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070141515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 474. prim_prince_test.2070141515 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/474.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.957726865 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 969851693 ps |
| CPU time | 18.44 seconds |
| Started | Feb 08 08:41:37 AM UTC 25 |
| Finished | Feb 08 08:42:02 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957726865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 475.p rim_prince_test.957726865 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/475.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4209516135 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1492172793 ps |
| CPU time | 27.66 seconds |
| Started | Feb 08 08:41:38 AM UTC 25 |
| Finished | Feb 08 08:42:14 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209516135 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 476. prim_prince_test.4209516135 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/476.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.154548857 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1238631568 ps |
| CPU time | 23.38 seconds |
| Started | Feb 08 08:41:38 AM UTC 25 |
| Finished | Feb 08 08:42:09 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154548857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 477.p rim_prince_test.154548857 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/477.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.2633248179 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2310989005 ps |
| CPU time | 42.99 seconds |
| Started | Feb 08 08:41:38 AM UTC 25 |
| Finished | Feb 08 08:42:33 AM UTC 25 |
| Peak memory | 154648 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633248179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 478. prim_prince_test.2633248179 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/478.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.2033168510 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1961933634 ps |
| CPU time | 36.69 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:42:26 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033168510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 479. prim_prince_test.2033168510 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/479.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.3501839706 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 936666681 ps |
| CPU time | 17.63 seconds |
| Started | Feb 08 08:15:02 AM UTC 25 |
| Finished | Feb 08 08:15:26 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501839706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.p rim_prince_test.3501839706 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/48.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.3934298588 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2694623667 ps |
| CPU time | 50.36 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:42:43 AM UTC 25 |
| Peak memory | 154496 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934298588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 480. prim_prince_test.3934298588 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/480.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.3326996775 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3480521862 ps |
| CPU time | 67.22 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:43:05 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326996775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 481. prim_prince_test.3326996775 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/481.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.4243614459 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 766320464 ps |
| CPU time | 14.65 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:41:59 AM UTC 25 |
| Peak memory | 154548 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243614459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 482. prim_prince_test.4243614459 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/482.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.3413586476 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1712038821 ps |
| CPU time | 31.69 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:42:20 AM UTC 25 |
| Peak memory | 154560 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413586476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 483. prim_prince_test.3413586476 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/483.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3545560886 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1076341393 ps |
| CPU time | 20.4 seconds |
| Started | Feb 08 08:41:39 AM UTC 25 |
| Finished | Feb 08 08:42:06 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545560886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 484. prim_prince_test.3545560886 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/484.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.710334829 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 861374290 ps |
| CPU time | 16.37 seconds |
| Started | Feb 08 08:41:40 AM UTC 25 |
| Finished | Feb 08 08:42:03 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710334829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 485.p rim_prince_test.710334829 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/485.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.3161800732 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1210564275 ps |
| CPU time | 22.47 seconds |
| Started | Feb 08 08:41:41 AM UTC 25 |
| Finished | Feb 08 08:42:10 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161800732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 486. prim_prince_test.3161800732 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/486.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.797092440 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 890997319 ps |
| CPU time | 16.94 seconds |
| Started | Feb 08 08:41:41 AM UTC 25 |
| Finished | Feb 08 08:42:03 AM UTC 25 |
| Peak memory | 154588 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797092440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 487.p rim_prince_test.797092440 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/487.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.3568607096 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3223550658 ps |
| CPU time | 62.35 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:43:01 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568607096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 488. prim_prince_test.3568607096 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/488.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.72006951 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3608451749 ps |
| CPU time | 70.94 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:43:13 AM UTC 25 |
| Peak memory | 154672 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72006951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 489.pr im_prince_test.72006951 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/489.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.716240406 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2176222100 ps |
| CPU time | 39.9 seconds |
| Started | Feb 08 08:15:08 AM UTC 25 |
| Finished | Feb 08 08:16:00 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716240406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pr im_prince_test.716240406 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/49.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.1843119953 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2938671960 ps |
| CPU time | 55.98 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:42:53 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843119953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 490. prim_prince_test.1843119953 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/490.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.2162098694 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2211129487 ps |
| CPU time | 41.32 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:42:36 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162098694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 491. prim_prince_test.2162098694 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/491.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.3384143171 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2463252071 ps |
| CPU time | 46.21 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:42:41 AM UTC 25 |
| Peak memory | 154652 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384143171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 492. prim_prince_test.3384143171 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/492.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.2991985033 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 974968122 ps |
| CPU time | 18.34 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:42:07 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991985033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 493. prim_prince_test.2991985033 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/493.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.559841660 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3463921701 ps |
| CPU time | 66.89 seconds |
| Started | Feb 08 08:41:42 AM UTC 25 |
| Finished | Feb 08 08:43:08 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559841660 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 494.p rim_prince_test.559841660 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/494.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.355006047 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1897507301 ps |
| CPU time | 35.7 seconds |
| Started | Feb 08 08:41:43 AM UTC 25 |
| Finished | Feb 08 08:42:29 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355006047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 495.p rim_prince_test.355006047 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/495.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.951893590 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3612901570 ps |
| CPU time | 71.98 seconds |
| Started | Feb 08 08:41:43 AM UTC 25 |
| Finished | Feb 08 08:43:15 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951893590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 496.p rim_prince_test.951893590 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/496.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.4211409302 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3000618440 ps |
| CPU time | 57.4 seconds |
| Started | Feb 08 08:41:44 AM UTC 25 |
| Finished | Feb 08 08:42:58 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211409302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 497. prim_prince_test.4211409302 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/497.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.2850560606 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 918391484 ps |
| CPU time | 17.55 seconds |
| Started | Feb 08 08:41:44 AM UTC 25 |
| Finished | Feb 08 08:42:08 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850560606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 498. prim_prince_test.2850560606 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/498.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.4135627402 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3079988078 ps |
| CPU time | 59.07 seconds |
| Started | Feb 08 08:41:45 AM UTC 25 |
| Finished | Feb 08 08:43:02 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135627402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 499. prim_prince_test.4135627402 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/499.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.2095866169 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 1907946862 ps |
| CPU time | 35.59 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:21 AM UTC 25 |
| Peak memory | 154604 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095866169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pr im_prince_test.2095866169 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/5.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.2622667026 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2724633391 ps |
| CPU time | 49.94 seconds |
| Started | Feb 08 08:15:09 AM UTC 25 |
| Finished | Feb 08 08:16:14 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622667026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.p rim_prince_test.2622667026 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/50.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.3164377414 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2016406334 ps |
| CPU time | 37.12 seconds |
| Started | Feb 08 08:15:09 AM UTC 25 |
| Finished | Feb 08 08:15:58 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164377414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.p rim_prince_test.3164377414 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/51.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.258617195 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2302538454 ps |
| CPU time | 42.14 seconds |
| Started | Feb 08 08:15:11 AM UTC 25 |
| Finished | Feb 08 08:16:06 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258617195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.pr im_prince_test.258617195 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/52.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.305788003 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 1852758850 ps |
| CPU time | 34.14 seconds |
| Started | Feb 08 08:15:13 AM UTC 25 |
| Finished | Feb 08 08:15:58 AM UTC 25 |
| Peak memory | 156048 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305788003 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.pr im_prince_test.305788003 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/53.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.677771524 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3117584432 ps |
| CPU time | 56.82 seconds |
| Started | Feb 08 08:15:16 AM UTC 25 |
| Finished | Feb 08 08:16:31 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677771524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.pr im_prince_test.677771524 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/54.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.1773517250 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 1783125619 ps |
| CPU time | 32.74 seconds |
| Started | Feb 08 08:15:17 AM UTC 25 |
| Finished | Feb 08 08:16:01 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773517250 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.p rim_prince_test.1773517250 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/55.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.2987236771 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2852399865 ps |
| CPU time | 51.98 seconds |
| Started | Feb 08 08:15:18 AM UTC 25 |
| Finished | Feb 08 08:16:26 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987236771 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.p rim_prince_test.2987236771 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/56.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.3924537784 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 841458195 ps |
| CPU time | 15.76 seconds |
| Started | Feb 08 08:15:21 AM UTC 25 |
| Finished | Feb 08 08:15:42 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924537784 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.p rim_prince_test.3924537784 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/57.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.3038548282 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3116925251 ps |
| CPU time | 56.74 seconds |
| Started | Feb 08 08:15:27 AM UTC 25 |
| Finished | Feb 08 08:16:40 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038548282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.p rim_prince_test.3038548282 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/58.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.1522539881 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3187211822 ps |
| CPU time | 58.16 seconds |
| Started | Feb 08 08:15:35 AM UTC 25 |
| Finished | Feb 08 08:16:50 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522539881 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.p rim_prince_test.1522539881 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/59.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.228686072 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2985038627 ps |
| CPU time | 56.1 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:46 AM UTC 25 |
| Peak memory | 154556 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228686072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pri m_prince_test.228686072 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/6.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.3767283802 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 937722342 ps |
| CPU time | 17.46 seconds |
| Started | Feb 08 08:15:40 AM UTC 25 |
| Finished | Feb 08 08:16:03 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767283802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.p rim_prince_test.3767283802 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/60.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.1650936563 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1823685995 ps |
| CPU time | 33.31 seconds |
| Started | Feb 08 08:15:41 AM UTC 25 |
| Finished | Feb 08 08:16:25 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650936563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.p rim_prince_test.1650936563 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/61.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.2900507336 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2533574116 ps |
| CPU time | 46.31 seconds |
| Started | Feb 08 08:15:43 AM UTC 25 |
| Finished | Feb 08 08:16:43 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900507336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.p rim_prince_test.2900507336 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/62.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.2545976843 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2212206729 ps |
| CPU time | 40.42 seconds |
| Started | Feb 08 08:15:51 AM UTC 25 |
| Finished | Feb 08 08:16:44 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545976843 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.p rim_prince_test.2545976843 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/63.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.79098999 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 790370661 ps |
| CPU time | 14.85 seconds |
| Started | Feb 08 08:15:59 AM UTC 25 |
| Finished | Feb 08 08:16:19 AM UTC 25 |
| Peak memory | 154460 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79098999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.pri m_prince_test.79098999 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/64.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.2186525513 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2166199776 ps |
| CPU time | 39.74 seconds |
| Started | Feb 08 08:15:59 AM UTC 25 |
| Finished | Feb 08 08:16:51 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186525513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.p rim_prince_test.2186525513 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/65.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.700069455 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2211698493 ps |
| CPU time | 40.31 seconds |
| Started | Feb 08 08:16:01 AM UTC 25 |
| Finished | Feb 08 08:16:54 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700069455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.pr im_prince_test.700069455 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/66.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.14565683 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2860221720 ps |
| CPU time | 52.05 seconds |
| Started | Feb 08 08:16:02 AM UTC 25 |
| Finished | Feb 08 08:17:10 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14565683 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.pri m_prince_test.14565683 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/67.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.3347032232 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 3408924720 ps |
| CPU time | 61.91 seconds |
| Started | Feb 08 08:16:04 AM UTC 25 |
| Finished | Feb 08 08:17:24 AM UTC 25 |
| Peak memory | 154656 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347032232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.p rim_prince_test.3347032232 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/68.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.1134932337 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 985623268 ps |
| CPU time | 18.42 seconds |
| Started | Feb 08 08:16:07 AM UTC 25 |
| Finished | Feb 08 08:16:32 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134932337 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.p rim_prince_test.1134932337 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/69.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.504413716 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3060443503 ps |
| CPU time | 57.39 seconds |
| Started | Feb 08 08:11:35 AM UTC 25 |
| Finished | Feb 08 08:12:48 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504413716 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pri m_prince_test.504413716 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/7.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.287386312 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 2453701983 ps |
| CPU time | 44.75 seconds |
| Started | Feb 08 08:16:14 AM UTC 25 |
| Finished | Feb 08 08:17:13 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287386312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.pr im_prince_test.287386312 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/70.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.3079265730 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2794335034 ps |
| CPU time | 50.8 seconds |
| Started | Feb 08 08:16:20 AM UTC 25 |
| Finished | Feb 08 08:17:26 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079265730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.p rim_prince_test.3079265730 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/71.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.916734538 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2644311833 ps |
| CPU time | 48.31 seconds |
| Started | Feb 08 08:16:25 AM UTC 25 |
| Finished | Feb 08 08:17:28 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916734538 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.pr im_prince_test.916734538 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/72.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.61030987 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1530127965 ps |
| CPU time | 28.18 seconds |
| Started | Feb 08 08:16:28 AM UTC 25 |
| Finished | Feb 08 08:17:05 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61030987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.pri m_prince_test.61030987 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/73.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.4080872708 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2629064139 ps |
| CPU time | 47.85 seconds |
| Started | Feb 08 08:16:32 AM UTC 25 |
| Finished | Feb 08 08:17:34 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080872708 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.p rim_prince_test.4080872708 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/74.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.2890963195 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 969153703 ps |
| CPU time | 18.09 seconds |
| Started | Feb 08 08:16:33 AM UTC 25 |
| Finished | Feb 08 08:16:57 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890963195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.p rim_prince_test.2890963195 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/75.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.2556955294 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 782394919 ps |
| CPU time | 14.68 seconds |
| Started | Feb 08 08:16:41 AM UTC 25 |
| Finished | Feb 08 08:17:01 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556955294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.p rim_prince_test.2556955294 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/76.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.1297937936 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1345474569 ps |
| CPU time | 24.68 seconds |
| Started | Feb 08 08:16:44 AM UTC 25 |
| Finished | Feb 08 08:17:16 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297937936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.p rim_prince_test.1297937936 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/77.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3722244084 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2619637289 ps |
| CPU time | 47.84 seconds |
| Started | Feb 08 08:16:45 AM UTC 25 |
| Finished | Feb 08 08:17:47 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722244084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.p rim_prince_test.3722244084 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/78.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.295786687 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2485039587 ps |
| CPU time | 45.17 seconds |
| Started | Feb 08 08:16:51 AM UTC 25 |
| Finished | Feb 08 08:17:50 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295786687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.pr im_prince_test.295786687 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/79.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.1226399801 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3587515129 ps |
| CPU time | 65.99 seconds |
| Started | Feb 08 08:11:37 AM UTC 25 |
| Finished | Feb 08 08:13:02 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226399801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pr im_prince_test.1226399801 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/8.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3737779712 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 880473903 ps |
| CPU time | 16.36 seconds |
| Started | Feb 08 08:16:52 AM UTC 25 |
| Finished | Feb 08 08:17:14 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737779712 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.p rim_prince_test.3737779712 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/80.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.2611293571 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1985441623 ps |
| CPU time | 36.07 seconds |
| Started | Feb 08 08:16:54 AM UTC 25 |
| Finished | Feb 08 08:17:41 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611293571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.p rim_prince_test.2611293571 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/81.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.503709761 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1625995397 ps |
| CPU time | 30 seconds |
| Started | Feb 08 08:16:58 AM UTC 25 |
| Finished | Feb 08 08:17:38 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503709761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.pr im_prince_test.503709761 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/82.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.3795929980 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 796747402 ps |
| CPU time | 14.8 seconds |
| Started | Feb 08 08:17:02 AM UTC 25 |
| Finished | Feb 08 08:17:23 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795929980 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.p rim_prince_test.3795929980 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/83.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.459152004 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2502411595 ps |
| CPU time | 45.79 seconds |
| Started | Feb 08 08:17:06 AM UTC 25 |
| Finished | Feb 08 08:18:06 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459152004 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.pr im_prince_test.459152004 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/84.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2380592960 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2957287750 ps |
| CPU time | 53.91 seconds |
| Started | Feb 08 08:17:10 AM UTC 25 |
| Finished | Feb 08 08:18:21 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380592960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.p rim_prince_test.2380592960 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/85.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.779480240 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3339255338 ps |
| CPU time | 61.04 seconds |
| Started | Feb 08 08:17:13 AM UTC 25 |
| Finished | Feb 08 08:18:33 AM UTC 25 |
| Peak memory | 154660 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779480240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.pr im_prince_test.779480240 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/86.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.3758527282 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1621134399 ps |
| CPU time | 29.99 seconds |
| Started | Feb 08 08:17:15 AM UTC 25 |
| Finished | Feb 08 08:17:55 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758527282 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.p rim_prince_test.3758527282 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/87.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.2503691807 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 919818971 ps |
| CPU time | 17.08 seconds |
| Started | Feb 08 08:17:17 AM UTC 25 |
| Finished | Feb 08 08:17:41 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503691807 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.p rim_prince_test.2503691807 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/88.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.2322366242 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 933337288 ps |
| CPU time | 17.43 seconds |
| Started | Feb 08 08:17:24 AM UTC 25 |
| Finished | Feb 08 08:17:48 AM UTC 25 |
| Peak memory | 154592 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322366242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.p rim_prince_test.2322366242 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/89.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.1867251808 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3671429264 ps |
| CPU time | 68.6 seconds |
| Started | Feb 08 08:11:38 AM UTC 25 |
| Finished | Feb 08 08:13:05 AM UTC 25 |
| Peak memory | 154668 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867251808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pr im_prince_test.1867251808 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/9.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.1901510612 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1759947898 ps |
| CPU time | 32.56 seconds |
| Started | Feb 08 08:17:26 AM UTC 25 |
| Finished | Feb 08 08:18:09 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901510612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.p rim_prince_test.1901510612 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/90.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.3302773392 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1590242031 ps |
| CPU time | 29.64 seconds |
| Started | Feb 08 08:17:28 AM UTC 25 |
| Finished | Feb 08 08:18:07 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302773392 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.p rim_prince_test.3302773392 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/91.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2857401541 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1666896611 ps |
| CPU time | 30.69 seconds |
| Started | Feb 08 08:17:30 AM UTC 25 |
| Finished | Feb 08 08:18:11 AM UTC 25 |
| Peak memory | 154596 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857401541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.p rim_prince_test.2857401541 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/92.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.1143402593 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2785654339 ps |
| CPU time | 51.21 seconds |
| Started | Feb 08 08:17:35 AM UTC 25 |
| Finished | Feb 08 08:18:41 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143402593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.p rim_prince_test.1143402593 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/93.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.2577890543 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1875747229 ps |
| CPU time | 34.48 seconds |
| Started | Feb 08 08:17:39 AM UTC 25 |
| Finished | Feb 08 08:18:24 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577890543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.p rim_prince_test.2577890543 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/94.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.3508553837 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1028102305 ps |
| CPU time | 19.33 seconds |
| Started | Feb 08 08:17:42 AM UTC 25 |
| Finished | Feb 08 08:18:08 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508553837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.p rim_prince_test.3508553837 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/95.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.3379369657 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1466821551 ps |
| CPU time | 27.05 seconds |
| Started | Feb 08 08:17:42 AM UTC 25 |
| Finished | Feb 08 08:18:18 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379369657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.p rim_prince_test.3379369657 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/96.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.2924842618 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1005271983 ps |
| CPU time | 18.77 seconds |
| Started | Feb 08 08:17:48 AM UTC 25 |
| Finished | Feb 08 08:18:13 AM UTC 25 |
| Peak memory | 154600 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924842618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.p rim_prince_test.2924842618 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/97.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.2980195873 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 3256482262 ps |
| CPU time | 59.38 seconds |
| Started | Feb 08 08:17:48 AM UTC 25 |
| Finished | Feb 08 08:19:05 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980195873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.p rim_prince_test.2980195873 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/98.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.4112293158 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2416257281 ps |
| CPU time | 44.19 seconds |
| Started | Feb 08 08:17:50 AM UTC 25 |
| Finished | Feb 08 08:18:48 AM UTC 25 |
| Peak memory | 154664 kb |
| Host | ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112293158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.p rim_prince_test.4112293158 |
| Directory | /workspaces/repo/scratch/os_regression/prim_prince-sim-vcs/99.prim_prince_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |