| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | 100.00 |
| T251 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2731496960 | Oct 14 08:20:54 PM UTC 24 | Oct 14 08:21:56 PM UTC 24 | 2680983426 ps | ||
| T252 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1420861679 | Oct 14 08:21:26 PM UTC 24 | Oct 14 08:21:56 PM UTC 24 | 1266271566 ps | ||
| T253 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3720614689 | Oct 14 08:20:52 PM UTC 24 | Oct 14 08:21:57 PM UTC 24 | 2818406290 ps | ||
| T254 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2937323419 | Oct 14 08:21:37 PM UTC 24 | Oct 14 08:21:58 PM UTC 24 | 854052994 ps | ||
| T255 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.48243107 | Oct 14 08:21:32 PM UTC 24 | Oct 14 08:21:59 PM UTC 24 | 1100681810 ps | ||
| T256 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.959661006 | Oct 14 08:20:32 PM UTC 24 | Oct 14 08:21:59 PM UTC 24 | 3677333854 ps | ||
| T257 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1597828230 | Oct 14 08:21:13 PM UTC 24 | Oct 14 08:22:01 PM UTC 24 | 2062961460 ps | ||
| T258 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3850557963 | Oct 14 08:20:57 PM UTC 24 | Oct 14 08:22:01 PM UTC 24 | 2712468632 ps | ||
| T259 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3824748776 | Oct 14 08:21:20 PM UTC 24 | Oct 14 08:22:03 PM UTC 24 | 1809673064 ps | ||
| T260 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3886193927 | Oct 14 08:21:25 PM UTC 24 | Oct 14 08:22:03 PM UTC 24 | 1598433793 ps | ||
| T261 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2609365254 | Oct 14 08:21:36 PM UTC 24 | Oct 14 08:22:03 PM UTC 24 | 1107264724 ps | ||
| T262 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3434545572 | Oct 14 08:21:43 PM UTC 24 | Oct 14 08:22:05 PM UTC 24 | 893585539 ps | ||
| T263 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3688793302 | Oct 14 08:21:09 PM UTC 24 | Oct 14 08:22:07 PM UTC 24 | 2434954693 ps | ||
| T264 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2084308404 | Oct 14 08:20:57 PM UTC 24 | Oct 14 08:22:07 PM UTC 24 | 3039041473 ps | ||
| T265 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3901940245 | Oct 14 08:21:17 PM UTC 24 | Oct 14 08:22:11 PM UTC 24 | 2263309140 ps | ||
| T266 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.3015377269 | Oct 14 08:20:45 PM UTC 24 | Oct 14 08:22:12 PM UTC 24 | 3716170055 ps | ||
| T267 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3705705090 | Oct 14 08:21:22 PM UTC 24 | Oct 14 08:22:14 PM UTC 24 | 2183941451 ps | ||
| T268 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.3697436064 | Oct 14 08:21:22 PM UTC 24 | Oct 14 08:22:14 PM UTC 24 | 2192455536 ps | ||
| T269 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3540607497 | Oct 14 08:21:08 PM UTC 24 | Oct 14 08:22:14 PM UTC 24 | 2808184829 ps | ||
| T270 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.4178752015 | Oct 14 08:21:35 PM UTC 24 | Oct 14 08:22:16 PM UTC 24 | 1690440004 ps | ||
| T271 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.900700731 | Oct 14 08:21:04 PM UTC 24 | Oct 14 08:22:17 PM UTC 24 | 3094894275 ps | ||
| T272 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3478555472 | Oct 14 08:21:39 PM UTC 24 | Oct 14 08:22:18 PM UTC 24 | 1667059759 ps | ||
| T273 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1755558240 | Oct 14 08:21:50 PM UTC 24 | Oct 14 08:22:19 PM UTC 24 | 1178292362 ps | ||
| T274 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3096718393 | Oct 14 08:21:35 PM UTC 24 | Oct 14 08:22:19 PM UTC 24 | 1877670921 ps | ||
| T275 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.1191615825 | Oct 14 08:21:15 PM UTC 24 | Oct 14 08:22:19 PM UTC 24 | 2786988920 ps | ||
| T276 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3547793754 | Oct 14 08:21:41 PM UTC 24 | Oct 14 08:22:19 PM UTC 24 | 1605126233 ps | ||
| T277 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.361127179 | Oct 14 08:21:06 PM UTC 24 | Oct 14 08:22:23 PM UTC 24 | 3305791689 ps | ||
| T278 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.657137241 | Oct 14 08:22:04 PM UTC 24 | Oct 14 08:22:23 PM UTC 24 | 758029286 ps | ||
| T279 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3519738306 | Oct 14 08:21:47 PM UTC 24 | Oct 14 08:22:26 PM UTC 24 | 1625846174 ps | ||
| T280 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.2201494362 | Oct 14 08:21:07 PM UTC 24 | Oct 14 08:22:26 PM UTC 24 | 3378521372 ps | ||
| T281 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1615136797 | Oct 14 08:21:04 PM UTC 24 | Oct 14 08:22:27 PM UTC 24 | 3511315783 ps | ||
| T282 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1433877380 | Oct 14 08:21:47 PM UTC 24 | Oct 14 08:22:27 PM UTC 24 | 1713116624 ps | ||
| T283 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1452551353 | Oct 14 08:21:14 PM UTC 24 | Oct 14 08:22:27 PM UTC 24 | 3207907861 ps | ||
| T284 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.562133096 | Oct 14 08:21:53 PM UTC 24 | Oct 14 08:22:28 PM UTC 24 | 1459783478 ps | ||
| T285 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2808694190 | Oct 14 08:22:09 PM UTC 24 | Oct 14 08:22:29 PM UTC 24 | 842255178 ps | ||
| T286 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1298697817 | Oct 14 08:21:57 PM UTC 24 | Oct 14 08:22:30 PM UTC 24 | 1321464766 ps | ||
| T287 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1052953759 | Oct 14 08:22:01 PM UTC 24 | Oct 14 08:22:32 PM UTC 24 | 1296733816 ps | ||
| T288 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2360580822 | Oct 14 08:21:55 PM UTC 24 | Oct 14 08:22:33 PM UTC 24 | 1566052355 ps | ||
| T289 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.2930223246 | Oct 14 08:21:23 PM UTC 24 | Oct 14 08:22:34 PM UTC 24 | 3032937642 ps | ||
| T290 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2496862536 | Oct 14 08:21:59 PM UTC 24 | Oct 14 08:22:35 PM UTC 24 | 1482195820 ps | ||
| T291 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3456890532 | Oct 14 08:21:19 PM UTC 24 | Oct 14 08:22:36 PM UTC 24 | 3255457796 ps | ||
| T292 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1962013329 | Oct 14 08:21:33 PM UTC 24 | Oct 14 08:22:37 PM UTC 24 | 2684829578 ps | ||
| T293 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2393159516 | Oct 14 08:21:16 PM UTC 24 | Oct 14 08:22:40 PM UTC 24 | 3538902096 ps | ||
| T294 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.89443422 | Oct 14 08:22:18 PM UTC 24 | Oct 14 08:22:41 PM UTC 24 | 926966330 ps | ||
| T295 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2059739238 | Oct 14 08:21:40 PM UTC 24 | Oct 14 08:22:42 PM UTC 24 | 2626228557 ps | ||
| T296 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.1344221108 | Oct 14 08:21:27 PM UTC 24 | Oct 14 08:22:43 PM UTC 24 | 3259488402 ps | ||
| T297 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1639650171 | Oct 14 08:21:50 PM UTC 24 | Oct 14 08:22:44 PM UTC 24 | 2239322744 ps | ||
| T298 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3856619648 | Oct 14 08:22:04 PM UTC 24 | Oct 14 08:22:45 PM UTC 24 | 1703450124 ps | ||
| T299 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.496811763 | Oct 14 08:21:54 PM UTC 24 | Oct 14 08:22:45 PM UTC 24 | 2142684012 ps | ||
| T300 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1654418381 | Oct 14 08:21:58 PM UTC 24 | Oct 14 08:22:45 PM UTC 24 | 1930025461 ps | ||
| T301 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.679239787 | Oct 14 08:21:34 PM UTC 24 | Oct 14 08:22:45 PM UTC 24 | 3022191534 ps | ||
| T302 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3602417048 | Oct 14 08:22:12 PM UTC 24 | Oct 14 08:22:46 PM UTC 24 | 1428227200 ps | ||
| T303 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1846790591 | Oct 14 08:22:15 PM UTC 24 | Oct 14 08:22:47 PM UTC 24 | 1324422072 ps | ||
| T304 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1771354441 | Oct 14 08:22:02 PM UTC 24 | Oct 14 08:22:47 PM UTC 24 | 1891872864 ps | ||
| T305 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.89673287 | Oct 14 08:22:04 PM UTC 24 | Oct 14 08:22:49 PM UTC 24 | 1870065307 ps | ||
| T306 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3225180372 | Oct 14 08:21:39 PM UTC 24 | Oct 14 08:22:52 PM UTC 24 | 3122433641 ps | ||
| T307 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1367049954 | Oct 14 08:22:23 PM UTC 24 | Oct 14 08:22:52 PM UTC 24 | 1169475558 ps | ||
| T308 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.519311667 | Oct 14 08:21:27 PM UTC 24 | Oct 14 08:22:52 PM UTC 24 | 3609918640 ps | ||
| T309 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.310951787 | Oct 14 08:22:03 PM UTC 24 | Oct 14 08:22:53 PM UTC 24 | 2113712996 ps | ||
| T310 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.510358355 | Oct 14 08:21:49 PM UTC 24 | Oct 14 08:22:54 PM UTC 24 | 2796781974 ps | ||
| T311 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.3250220357 | Oct 14 08:21:44 PM UTC 24 | Oct 14 08:22:54 PM UTC 24 | 2966310760 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3615707104 | Oct 14 08:21:53 PM UTC 24 | Oct 14 08:22:55 PM UTC 24 | 2688370756 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.473876953 | Oct 14 08:21:57 PM UTC 24 | Oct 14 08:22:56 PM UTC 24 | 2437102529 ps | ||
| T314 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.3769976734 | Oct 14 08:21:45 PM UTC 24 | Oct 14 08:22:56 PM UTC 24 | 3059626848 ps | ||
| T315 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2994105511 | Oct 14 08:21:59 PM UTC 24 | Oct 14 08:22:56 PM UTC 24 | 2457799221 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1988722254 | Oct 14 08:21:57 PM UTC 24 | Oct 14 08:22:56 PM UTC 24 | 2522515034 ps | ||
| T317 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.1642719266 | Oct 14 08:21:37 PM UTC 24 | Oct 14 08:22:59 PM UTC 24 | 3540857136 ps | ||
| T318 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3192497058 | Oct 14 08:21:40 PM UTC 24 | Oct 14 08:22:59 PM UTC 24 | 3440694849 ps | ||
| T319 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3438011711 | Oct 14 08:22:16 PM UTC 24 | Oct 14 08:23:00 PM UTC 24 | 1815733669 ps | ||
| T320 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.407417434 | Oct 14 08:22:42 PM UTC 24 | Oct 14 08:23:02 PM UTC 24 | 816452526 ps | ||
| T321 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2719336893 | Oct 14 08:22:28 PM UTC 24 | Oct 14 08:23:02 PM UTC 24 | 1424202606 ps | ||
| T322 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.826507901 | Oct 14 08:22:14 PM UTC 24 | Oct 14 08:23:04 PM UTC 24 | 2105305864 ps | ||
| T323 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.3778747231 | Oct 14 08:22:15 PM UTC 24 | Oct 14 08:23:05 PM UTC 24 | 2110096767 ps | ||
| T324 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.257716866 | Oct 14 08:21:47 PM UTC 24 | Oct 14 08:23:05 PM UTC 24 | 3319137124 ps | ||
| T325 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1159505804 | Oct 14 08:21:42 PM UTC 24 | Oct 14 08:23:05 PM UTC 24 | 3534893411 ps | ||
| T326 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1843748990 | Oct 14 08:22:13 PM UTC 24 | Oct 14 08:23:06 PM UTC 24 | 2217794488 ps | ||
| T327 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3250927302 | Oct 14 08:21:44 PM UTC 24 | Oct 14 08:23:09 PM UTC 24 | 3649641788 ps | ||
| T328 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2531572413 | Oct 14 08:21:48 PM UTC 24 | Oct 14 08:23:10 PM UTC 24 | 3485327574 ps | ||
| T329 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1816724376 | Oct 14 08:22:37 PM UTC 24 | Oct 14 08:23:12 PM UTC 24 | 1485048694 ps | ||
| T330 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.659743997 | Oct 14 08:22:29 PM UTC 24 | Oct 14 08:23:13 PM UTC 24 | 1848667816 ps | ||
| T331 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1386093266 | Oct 14 08:22:09 PM UTC 24 | Oct 14 08:23:13 PM UTC 24 | 2799074692 ps | ||
| T332 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1238871035 | Oct 14 08:22:48 PM UTC 24 | Oct 14 08:23:16 PM UTC 24 | 1174193529 ps | ||
| T333 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2437148274 | Oct 14 08:22:20 PM UTC 24 | Oct 14 08:23:17 PM UTC 24 | 2402594925 ps | ||
| T334 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2888086261 | Oct 14 08:22:31 PM UTC 24 | Oct 14 08:23:17 PM UTC 24 | 1978401037 ps | ||
| T335 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.4224880228 | Oct 14 08:22:50 PM UTC 24 | Oct 14 08:23:18 PM UTC 24 | 1153636548 ps | ||
| T336 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.59944573 | Oct 14 08:22:54 PM UTC 24 | Oct 14 08:23:19 PM UTC 24 | 1050640342 ps | ||
| T337 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3347144586 | Oct 14 08:22:20 PM UTC 24 | Oct 14 08:23:19 PM UTC 24 | 2502548556 ps | ||
| T338 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.4020254420 | Oct 14 08:22:53 PM UTC 24 | Oct 14 08:23:20 PM UTC 24 | 1161593548 ps | ||
| T339 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2338944846 | Oct 14 08:22:58 PM UTC 24 | Oct 14 08:23:20 PM UTC 24 | 939969695 ps | ||
| T340 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2922150395 | Oct 14 08:24:00 PM UTC 24 | Oct 14 08:24:32 PM UTC 24 | 1301076082 ps | ||
| T341 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3652533804 | Oct 14 08:22:52 PM UTC 24 | Oct 14 08:23:21 PM UTC 24 | 1165428958 ps | ||
| T342 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2530819470 | Oct 14 08:22:46 PM UTC 24 | Oct 14 08:23:21 PM UTC 24 | 1459954924 ps | ||
| T343 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.864954010 | Oct 14 08:22:56 PM UTC 24 | Oct 14 08:23:21 PM UTC 24 | 1030471004 ps | ||
| T344 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1996695400 | Oct 14 08:22:34 PM UTC 24 | Oct 14 08:23:22 PM UTC 24 | 2012473116 ps | ||
| T345 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.190068895 | Oct 14 08:23:14 PM UTC 24 | Oct 14 08:24:32 PM UTC 24 | 3362877445 ps | ||
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| T437 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3378147261 | Oct 14 08:23:59 PM UTC 24 | Oct 14 08:24:49 PM UTC 24 | 2105809365 ps | ||
| T438 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3888162238 | Oct 14 08:23:40 PM UTC 24 | Oct 14 08:24:49 PM UTC 24 | 2961593683 ps | ||
| T439 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2233114271 | Oct 14 08:23:36 PM UTC 24 | Oct 14 08:24:50 PM UTC 24 | 3142568985 ps | ||
| T440 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3046934773 | Oct 14 08:24:00 PM UTC 24 | Oct 14 08:24:50 PM UTC 24 | 2137234505 ps | ||
| T441 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1000718281 | Oct 14 08:23:32 PM UTC 24 | Oct 14 08:24:50 PM UTC 24 | 3333719192 ps | ||
| T442 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1136041667 | Oct 14 08:24:30 PM UTC 24 | Oct 14 08:24:51 PM UTC 24 | 872871657 ps | ||
| T443 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3792756324 | Oct 14 08:24:32 PM UTC 24 | Oct 14 08:24:52 PM UTC 24 | 765478690 ps | ||
| T444 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2987511014 | Oct 14 08:23:48 PM UTC 24 | Oct 14 08:24:52 PM UTC 24 | 2756520114 ps | ||
| T445 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1742302623 | Oct 14 08:23:51 PM UTC 24 | Oct 14 08:24:52 PM UTC 24 | 2606487506 ps | ||
| T446 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3289975377 | Oct 14 08:24:30 PM UTC 24 | Oct 14 08:24:53 PM UTC 24 | 930337933 ps | ||
| T447 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1630051856 | Oct 14 08:24:12 PM UTC 24 | Oct 14 08:24:53 PM UTC 24 | 1740667165 ps | ||
| T448 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.109168814 | Oct 14 08:23:30 PM UTC 24 | Oct 14 08:24:54 PM UTC 24 | 3607793324 ps | ||
| T449 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.832915172 | Oct 14 08:23:45 PM UTC 24 | Oct 14 08:24:55 PM UTC 24 | 3012814930 ps | ||
| T450 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.2235750131 | Oct 14 08:24:13 PM UTC 24 | Oct 14 08:24:55 PM UTC 24 | 1768904147 ps | ||
| T451 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3013446663 | Oct 14 08:24:13 PM UTC 24 | Oct 14 08:24:56 PM UTC 24 | 1802402898 ps | ||
| T452 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.3105031352 | Oct 14 08:24:02 PM UTC 24 | Oct 14 08:24:56 PM UTC 24 | 2328168160 ps | ||
| T453 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4184332366 | Oct 14 08:24:36 PM UTC 24 | Oct 14 08:24:58 PM UTC 24 | 891975853 ps | ||
| T454 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1816452642 | Oct 14 08:23:46 PM UTC 24 | Oct 14 08:24:59 PM UTC 24 | 3098086462 ps | ||
| T455 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.577237834 | Oct 14 08:23:50 PM UTC 24 | Oct 14 08:25:01 PM UTC 24 | 3063835352 ps | ||
| T456 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.1027040265 | Oct 14 08:23:36 PM UTC 24 | Oct 14 08:25:01 PM UTC 24 | 3648755749 ps | ||
| T457 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1091150218 | Oct 14 08:23:54 PM UTC 24 | Oct 14 08:25:01 PM UTC 24 | 2878790979 ps | ||
| T458 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1954520982 | Oct 14 08:24:12 PM UTC 24 | Oct 14 08:25:04 PM UTC 24 | 2204258132 ps | ||
| T459 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.980546684 | Oct 14 08:24:44 PM UTC 24 | Oct 14 08:25:04 PM UTC 24 | 844147597 ps | ||
| T460 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3479688990 | Oct 14 08:24:41 PM UTC 24 | Oct 14 08:25:05 PM UTC 24 | 974147906 ps | ||
| T461 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1118922112 | Oct 14 08:24:07 PM UTC 24 | Oct 14 08:25:08 PM UTC 24 | 2596551539 ps | ||
| T462 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2003640301 | Oct 14 08:24:14 PM UTC 24 | Oct 14 08:25:09 PM UTC 24 | 2365964100 ps | ||
| T463 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1920114996 | Oct 14 08:23:48 PM UTC 24 | Oct 14 08:25:09 PM UTC 24 | 3492683610 ps | ||
| T464 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2302613102 | Oct 14 08:24:22 PM UTC 24 | Oct 14 08:25:09 PM UTC 24 | 1986119067 ps | ||
| T465 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.941337205 | Oct 14 08:24:23 PM UTC 24 | Oct 14 08:25:09 PM UTC 24 | 1927562719 ps | ||
| T466 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.467083556 | Oct 14 08:24:39 PM UTC 24 | Oct 14 08:25:10 PM UTC 24 | 1321755251 ps | ||
| T467 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4172271509 | Oct 14 08:23:51 PM UTC 24 | Oct 14 08:25:10 PM UTC 24 | 3435746035 ps | ||
| T468 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3292999750 | Oct 14 08:24:15 PM UTC 24 | Oct 14 08:25:11 PM UTC 24 | 2412081700 ps | ||
| T469 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1583966328 | Oct 14 08:23:53 PM UTC 24 | Oct 14 08:25:12 PM UTC 24 | 3417445722 ps | ||
| T470 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.26903147 | Oct 14 08:24:30 PM UTC 24 | Oct 14 08:25:13 PM UTC 24 | 1868855301 ps | ||
| T471 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.916741500 | Oct 14 08:24:48 PM UTC 24 | Oct 14 08:25:13 PM UTC 24 | 1071497443 ps | ||
| T472 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3656093500 | Oct 14 08:24:39 PM UTC 24 | Oct 14 08:25:15 PM UTC 24 | 1590928380 ps | ||
| T473 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1821459964 | Oct 14 08:23:55 PM UTC 24 | Oct 14 08:25:16 PM UTC 24 | 3513205164 ps | ||
| T474 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4252465011 | Oct 14 08:24:32 PM UTC 24 | Oct 14 08:25:16 PM UTC 24 | 1873484759 ps | ||
| T475 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2105109870 | Oct 14 08:24:31 PM UTC 24 | Oct 14 08:25:17 PM UTC 24 | 1988395615 ps | ||
| T476 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.4122533865 | Oct 14 08:24:23 PM UTC 24 | Oct 14 08:25:20 PM UTC 24 | 2404557805 ps | ||
| T477 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4167423781 | Oct 14 08:24:31 PM UTC 24 | Oct 14 08:25:21 PM UTC 24 | 2149523098 ps | ||
| T478 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.2238099254 | Oct 14 08:24:39 PM UTC 24 | Oct 14 08:25:23 PM UTC 24 | 1948221235 ps | ||
| T479 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3515306775 | Oct 14 08:24:47 PM UTC 24 | Oct 14 08:25:23 PM UTC 24 | 1520773136 ps | ||
| T480 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.1666308605 | Oct 14 08:24:04 PM UTC 24 | Oct 14 08:25:26 PM UTC 24 | 3544435322 ps | ||
| T481 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1992977197 | Oct 14 08:24:18 PM UTC 24 | Oct 14 08:25:26 PM UTC 24 | 3005524419 ps | ||
| T482 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2874538952 | Oct 14 08:24:40 PM UTC 24 | Oct 14 08:25:26 PM UTC 24 | 1956072536 ps | ||
| T483 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.1502226200 | Oct 14 08:24:08 PM UTC 24 | Oct 14 08:25:27 PM UTC 24 | 3449799526 ps | ||
| T484 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2340779224 | Oct 14 08:24:50 PM UTC 24 | Oct 14 08:25:27 PM UTC 24 | 1643188691 ps | ||
| T485 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.730753641 | Oct 14 08:24:51 PM UTC 24 | Oct 14 08:25:28 PM UTC 24 | 1526495313 ps | ||
| T486 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3431670247 | Oct 14 08:24:25 PM UTC 24 | Oct 14 08:25:30 PM UTC 24 | 2770146994 ps | ||
| T487 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2415777370 | Oct 14 08:24:29 PM UTC 24 | Oct 14 08:25:30 PM UTC 24 | 2556548431 ps | ||
| T488 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3021868925 | Oct 14 08:24:30 PM UTC 24 | Oct 14 08:25:31 PM UTC 24 | 2599434219 ps | ||
| T489 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1643800405 | Oct 14 08:24:48 PM UTC 24 | Oct 14 08:25:32 PM UTC 24 | 1786869871 ps | ||
| T490 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3038024599 | Oct 14 08:24:10 PM UTC 24 | Oct 14 08:25:32 PM UTC 24 | 3637228620 ps | ||
| T491 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.867081922 | Oct 14 08:24:36 PM UTC 24 | Oct 14 08:25:32 PM UTC 24 | 2470426240 ps | ||
| T492 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.329527415 | Oct 14 08:24:35 PM UTC 24 | Oct 14 08:25:39 PM UTC 24 | 2834193905 ps | ||
| T493 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.994714346 | Oct 14 08:24:14 PM UTC 24 | Oct 14 08:25:40 PM UTC 24 | 3588878951 ps | ||
| T494 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.117325955 | Oct 14 08:24:25 PM UTC 24 | Oct 14 08:25:45 PM UTC 24 | 3458640750 ps | ||
| T495 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2551315707 | Oct 14 08:24:36 PM UTC 24 | Oct 14 08:25:58 PM UTC 24 | 3240635700 ps | ||
| T496 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2656114417 | Oct 14 08:24:42 PM UTC 24 | Oct 14 08:26:01 PM UTC 24 | 3398125171 ps | ||
| T497 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3343442059 | Oct 14 08:24:39 PM UTC 24 | Oct 14 08:26:01 PM UTC 24 | 3277963361 ps | ||
| T498 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3000447007 | Oct 14 08:24:33 PM UTC 24 | Oct 14 08:26:03 PM UTC 24 | 3546173322 ps | ||
| T499 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1659620241 | Oct 14 08:24:47 PM UTC 24 | Oct 14 08:26:04 PM UTC 24 | 3233287100 ps | ||
| T500 | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3533998045 | Oct 14 08:24:50 PM UTC 24 | Oct 14 08:26:14 PM UTC 24 | 3543665518 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/1.prim_prince_test.1447268317 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 865361830 ps |
| CPU time | 16.15 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:00 PM UTC 24 |
| Peak memory | 154964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447268317 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 1.prim_prince_test.1447268317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/1.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/0.prim_prince_test.3600001907 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2801496353 ps |
| CPU time | 53.82 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:47 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600001907 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.prim_prince_test.3600001907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/0.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/10.prim_prince_test.382052437 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1119707145 ps |
| CPU time | 20.76 seconds |
| Started | Oct 14 08:16:39 PM UTC 24 |
| Finished | Oct 14 08:17:07 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382052437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 10.prim_prince_test.382052437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/10.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/100.prim_prince_test.1474351000 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 2992090048 ps |
| CPU time | 54.78 seconds |
| Started | Oct 14 08:18:24 PM UTC 24 |
| Finished | Oct 14 08:19:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474351000 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 100.prim_prince_test.1474351000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/100.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/101.prim_prince_test.264056057 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2932592707 ps |
| CPU time | 54.24 seconds |
| Started | Oct 14 08:18:24 PM UTC 24 |
| Finished | Oct 14 08:19:33 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264056057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 101.prim_prince_test.264056057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/101.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/102.prim_prince_test.382968336 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2596495754 ps |
| CPU time | 49.68 seconds |
| Started | Oct 14 08:18:25 PM UTC 24 |
| Finished | Oct 14 08:19:28 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382968336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 102.prim_prince_test.382968336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/102.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/103.prim_prince_test.1500616304 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2760903600 ps |
| CPU time | 52.28 seconds |
| Started | Oct 14 08:18:26 PM UTC 24 |
| Finished | Oct 14 08:19:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500616304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 103.prim_prince_test.1500616304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/103.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/104.prim_prince_test.1235800873 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2263629078 ps |
| CPU time | 43.41 seconds |
| Started | Oct 14 08:18:27 PM UTC 24 |
| Finished | Oct 14 08:19:22 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235800873 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 104.prim_prince_test.1235800873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/104.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/105.prim_prince_test.916075553 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 2397614138 ps |
| CPU time | 45.19 seconds |
| Started | Oct 14 08:18:27 PM UTC 24 |
| Finished | Oct 14 08:19:25 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916075553 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 105.prim_prince_test.916075553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/105.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/106.prim_prince_test.3497959643 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2918403022 ps |
| CPU time | 53.85 seconds |
| Started | Oct 14 08:18:27 PM UTC 24 |
| Finished | Oct 14 08:19:36 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497959643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 106.prim_prince_test.3497959643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/106.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/107.prim_prince_test.640047417 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1120697731 ps |
| CPU time | 21.3 seconds |
| Started | Oct 14 08:18:28 PM UTC 24 |
| Finished | Oct 14 08:18:56 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640047417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 107.prim_prince_test.640047417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/107.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/108.prim_prince_test.2200244142 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1849624674 ps |
| CPU time | 34.53 seconds |
| Started | Oct 14 08:18:29 PM UTC 24 |
| Finished | Oct 14 08:19:14 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200244142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 108.prim_prince_test.2200244142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/108.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/109.prim_prince_test.3419586993 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 2404103282 ps |
| CPU time | 45.89 seconds |
| Started | Oct 14 08:18:32 PM UTC 24 |
| Finished | Oct 14 08:19:30 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419586993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 109.prim_prince_test.3419586993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/109.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/11.prim_prince_test.2112025950 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1755333768 ps |
| CPU time | 33.85 seconds |
| Started | Oct 14 08:16:39 PM UTC 24 |
| Finished | Oct 14 08:17:23 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112025950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 11.prim_prince_test.2112025950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/11.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/110.prim_prince_test.543344563 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1573317670 ps |
| CPU time | 29.14 seconds |
| Started | Oct 14 08:18:32 PM UTC 24 |
| Finished | Oct 14 08:19:10 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543344563 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 110.prim_prince_test.543344563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/110.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/111.prim_prince_test.1951322433 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 988347492 ps |
| CPU time | 19.04 seconds |
| Started | Oct 14 08:18:32 PM UTC 24 |
| Finished | Oct 14 08:18:57 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951322433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 111.prim_prince_test.1951322433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/111.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/112.prim_prince_test.2438578126 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2055993804 ps |
| CPU time | 39.28 seconds |
| Started | Oct 14 08:18:34 PM UTC 24 |
| Finished | Oct 14 08:19:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2438578126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 112.prim_prince_test.2438578126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/112.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/113.prim_prince_test.2055694808 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3271207506 ps |
| CPU time | 62.5 seconds |
| Started | Oct 14 08:18:37 PM UTC 24 |
| Finished | Oct 14 08:19:55 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055694808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 113.prim_prince_test.2055694808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/113.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/114.prim_prince_test.3723583757 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2382969223 ps |
| CPU time | 44.59 seconds |
| Started | Oct 14 08:18:37 PM UTC 24 |
| Finished | Oct 14 08:19:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723583757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 114.prim_prince_test.3723583757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/114.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/115.prim_prince_test.513209460 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 2914714237 ps |
| CPU time | 54.13 seconds |
| Started | Oct 14 08:18:39 PM UTC 24 |
| Finished | Oct 14 08:19:48 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513209460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 115.prim_prince_test.513209460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/115.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/116.prim_prince_test.624987104 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 2367914162 ps |
| CPU time | 44.5 seconds |
| Started | Oct 14 08:18:40 PM UTC 24 |
| Finished | Oct 14 08:19:37 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624987104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 116.prim_prince_test.624987104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/116.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/117.prim_prince_test.605069338 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 2889559903 ps |
| CPU time | 53.03 seconds |
| Started | Oct 14 08:18:40 PM UTC 24 |
| Finished | Oct 14 08:19:48 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605069338 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 117.prim_prince_test.605069338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/117.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/118.prim_prince_test.2826452542 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2032099026 ps |
| CPU time | 38.11 seconds |
| Started | Oct 14 08:18:40 PM UTC 24 |
| Finished | Oct 14 08:19:29 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826452542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 118.prim_prince_test.2826452542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/118.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/119.prim_prince_test.3705148508 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2061402318 ps |
| CPU time | 38.37 seconds |
| Started | Oct 14 08:18:42 PM UTC 24 |
| Finished | Oct 14 08:19:31 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705148508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 119.prim_prince_test.3705148508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/119.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/12.prim_prince_test.269269809 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 809758216 ps |
| CPU time | 16.1 seconds |
| Started | Oct 14 08:16:40 PM UTC 24 |
| Finished | Oct 14 08:17:01 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269269809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 12.prim_prince_test.269269809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/12.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/120.prim_prince_test.2188816189 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1573674577 ps |
| CPU time | 30.29 seconds |
| Started | Oct 14 08:18:44 PM UTC 24 |
| Finished | Oct 14 08:19:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188816189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 120.prim_prince_test.2188816189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/120.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/121.prim_prince_test.3046622536 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 3594079619 ps |
| CPU time | 68.44 seconds |
| Started | Oct 14 08:18:45 PM UTC 24 |
| Finished | Oct 14 08:20:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046622536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 121.prim_prince_test.3046622536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/121.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/122.prim_prince_test.3807762132 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 1592002915 ps |
| CPU time | 29.92 seconds |
| Started | Oct 14 08:18:45 PM UTC 24 |
| Finished | Oct 14 08:19:24 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807762132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 122.prim_prince_test.3807762132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/122.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/123.prim_prince_test.1401870503 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3228397885 ps |
| CPU time | 61.69 seconds |
| Started | Oct 14 08:18:46 PM UTC 24 |
| Finished | Oct 14 08:20:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401870503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 123.prim_prince_test.1401870503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/123.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/124.prim_prince_test.1069827787 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2680626799 ps |
| CPU time | 51.08 seconds |
| Started | Oct 14 08:18:48 PM UTC 24 |
| Finished | Oct 14 08:19:53 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069827787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 124.prim_prince_test.1069827787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/124.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/125.prim_prince_test.1868863490 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1891742860 ps |
| CPU time | 36.05 seconds |
| Started | Oct 14 08:18:50 PM UTC 24 |
| Finished | Oct 14 08:19:36 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868863490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 125.prim_prince_test.1868863490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/125.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/126.prim_prince_test.550824180 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 3333837933 ps |
| CPU time | 63.29 seconds |
| Started | Oct 14 08:18:52 PM UTC 24 |
| Finished | Oct 14 08:20:11 PM UTC 24 |
| Peak memory | 155024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550824180 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 126.prim_prince_test.550824180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/126.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/127.prim_prince_test.1140637167 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2846212698 ps |
| CPU time | 54.22 seconds |
| Started | Oct 14 08:18:52 PM UTC 24 |
| Finished | Oct 14 08:20:00 PM UTC 24 |
| Peak memory | 155032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140637167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 127.prim_prince_test.1140637167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/127.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/128.prim_prince_test.4073785458 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2321838486 ps |
| CPU time | 43.56 seconds |
| Started | Oct 14 08:18:52 PM UTC 24 |
| Finished | Oct 14 08:19:47 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073785458 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 128.prim_prince_test.4073785458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/128.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/129.prim_prince_test.2692950469 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1071879688 ps |
| CPU time | 20.37 seconds |
| Started | Oct 14 08:18:53 PM UTC 24 |
| Finished | Oct 14 08:19:19 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692950469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 129.prim_prince_test.2692950469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/129.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/13.prim_prince_test.689760177 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3302665528 ps |
| CPU time | 61 seconds |
| Started | Oct 14 08:16:40 PM UTC 24 |
| Finished | Oct 14 08:17:59 PM UTC 24 |
| Peak memory | 155000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689760177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 13.prim_prince_test.689760177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/13.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/130.prim_prince_test.2393260205 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2842843274 ps |
| CPU time | 52.49 seconds |
| Started | Oct 14 08:18:54 PM UTC 24 |
| Finished | Oct 14 08:20:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393260205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 130.prim_prince_test.2393260205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/130.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/131.prim_prince_test.2122250710 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3626870354 ps |
| CPU time | 69.07 seconds |
| Started | Oct 14 08:18:54 PM UTC 24 |
| Finished | Oct 14 08:20:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122250710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 131.prim_prince_test.2122250710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/131.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/132.prim_prince_test.290208195 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2326202784 ps |
| CPU time | 42.61 seconds |
| Started | Oct 14 08:18:55 PM UTC 24 |
| Finished | Oct 14 08:19:50 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290208195 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 132.prim_prince_test.290208195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/132.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/133.prim_prince_test.1657831921 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3203588570 ps |
| CPU time | 59.11 seconds |
| Started | Oct 14 08:18:57 PM UTC 24 |
| Finished | Oct 14 08:20:13 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657831921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 133.prim_prince_test.1657831921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/133.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/134.prim_prince_test.3030099077 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3504078347 ps |
| CPU time | 65.74 seconds |
| Started | Oct 14 08:18:57 PM UTC 24 |
| Finished | Oct 14 08:20:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030099077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 134.prim_prince_test.3030099077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/134.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/135.prim_prince_test.2138975245 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 2820938634 ps |
| CPU time | 54.1 seconds |
| Started | Oct 14 08:18:58 PM UTC 24 |
| Finished | Oct 14 08:20:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138975245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 135.prim_prince_test.2138975245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/135.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/136.prim_prince_test.3599148334 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1624186754 ps |
| CPU time | 31.54 seconds |
| Started | Oct 14 08:19:01 PM UTC 24 |
| Finished | Oct 14 08:19:41 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599148334 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 136.prim_prince_test.3599148334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/136.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/137.prim_prince_test.59165758 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2911347291 ps |
| CPU time | 53.86 seconds |
| Started | Oct 14 08:19:03 PM UTC 24 |
| Finished | Oct 14 08:20:12 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59165758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 137.prim_prince_test.59165758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/137.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/138.prim_prince_test.1281527551 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3691073599 ps |
| CPU time | 69.75 seconds |
| Started | Oct 14 08:19:05 PM UTC 24 |
| Finished | Oct 14 08:20:33 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281527551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 138.prim_prince_test.1281527551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/138.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/139.prim_prince_test.1557302623 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2366026149 ps |
| CPU time | 44.81 seconds |
| Started | Oct 14 08:19:07 PM UTC 24 |
| Finished | Oct 14 08:20:03 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557302623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 139.prim_prince_test.1557302623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/139.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/14.prim_prince_test.1306080190 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 1092903772 ps |
| CPU time | 20.13 seconds |
| Started | Oct 14 08:16:44 PM UTC 24 |
| Finished | Oct 14 08:17:11 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306080190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 14.prim_prince_test.1306080190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/14.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/140.prim_prince_test.971079382 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1082654384 ps |
| CPU time | 20.77 seconds |
| Started | Oct 14 08:19:07 PM UTC 24 |
| Finished | Oct 14 08:19:33 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971079382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 140.prim_prince_test.971079382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/140.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/141.prim_prince_test.4074438523 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3268854553 ps |
| CPU time | 62.39 seconds |
| Started | Oct 14 08:19:08 PM UTC 24 |
| Finished | Oct 14 08:20:26 PM UTC 24 |
| Peak memory | 156400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074438523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 141.prim_prince_test.4074438523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/141.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/142.prim_prince_test.1346472954 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3259635699 ps |
| CPU time | 61.56 seconds |
| Started | Oct 14 08:19:10 PM UTC 24 |
| Finished | Oct 14 08:20:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346472954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 142.prim_prince_test.1346472954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/142.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/143.prim_prince_test.3484104072 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1798007586 ps |
| CPU time | 34.16 seconds |
| Started | Oct 14 08:19:11 PM UTC 24 |
| Finished | Oct 14 08:19:54 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484104072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 143.prim_prince_test.3484104072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/143.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/144.prim_prince_test.731820362 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1058535393 ps |
| CPU time | 20.5 seconds |
| Started | Oct 14 08:19:12 PM UTC 24 |
| Finished | Oct 14 08:19:39 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731820362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 144.prim_prince_test.731820362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/144.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/145.prim_prince_test.3330569812 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3472286394 ps |
| CPU time | 65.83 seconds |
| Started | Oct 14 08:19:14 PM UTC 24 |
| Finished | Oct 14 08:20:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330569812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 145.prim_prince_test.3330569812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/145.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/146.prim_prince_test.2377609185 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3224976390 ps |
| CPU time | 60.32 seconds |
| Started | Oct 14 08:19:20 PM UTC 24 |
| Finished | Oct 14 08:20:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377609185 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 146.prim_prince_test.2377609185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/146.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/147.prim_prince_test.1584274029 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 1007237928 ps |
| CPU time | 19.71 seconds |
| Started | Oct 14 08:19:22 PM UTC 24 |
| Finished | Oct 14 08:19:48 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584274029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 147.prim_prince_test.1584274029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/147.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/148.prim_prince_test.3166158999 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3012129980 ps |
| CPU time | 57.32 seconds |
| Started | Oct 14 08:19:22 PM UTC 24 |
| Finished | Oct 14 08:20:35 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166158999 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 148.prim_prince_test.3166158999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/148.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/149.prim_prince_test.2658288615 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3132266160 ps |
| CPU time | 57.65 seconds |
| Started | Oct 14 08:19:23 PM UTC 24 |
| Finished | Oct 14 08:20:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658288615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 149.prim_prince_test.2658288615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/149.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/15.prim_prince_test.3842986532 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2845363559 ps |
| CPU time | 54.72 seconds |
| Started | Oct 14 08:16:45 PM UTC 24 |
| Finished | Oct 14 08:17:55 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842986532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 15.prim_prince_test.3842986532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/15.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/150.prim_prince_test.73179490 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1281627573 ps |
| CPU time | 24.68 seconds |
| Started | Oct 14 08:19:25 PM UTC 24 |
| Finished | Oct 14 08:19:56 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73179490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 150.prim_prince_test.73179490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/150.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/151.prim_prince_test.4074838606 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 812308865 ps |
| CPU time | 15.65 seconds |
| Started | Oct 14 08:19:25 PM UTC 24 |
| Finished | Oct 14 08:19:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074838606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 151.prim_prince_test.4074838606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/151.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/152.prim_prince_test.1229375840 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2773350494 ps |
| CPU time | 51.15 seconds |
| Started | Oct 14 08:19:26 PM UTC 24 |
| Finished | Oct 14 08:20:31 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229375840 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 152.prim_prince_test.1229375840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/152.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/153.prim_prince_test.310759258 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3123355522 ps |
| CPU time | 57.09 seconds |
| Started | Oct 14 08:19:26 PM UTC 24 |
| Finished | Oct 14 08:20:39 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310759258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 153.prim_prince_test.310759258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/153.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/154.prim_prince_test.834625702 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 2952637275 ps |
| CPU time | 54.62 seconds |
| Started | Oct 14 08:19:27 PM UTC 24 |
| Finished | Oct 14 08:20:37 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834625702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 154.prim_prince_test.834625702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/154.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/155.prim_prince_test.2462407471 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2764016984 ps |
| CPU time | 52.62 seconds |
| Started | Oct 14 08:19:28 PM UTC 24 |
| Finished | Oct 14 08:20:34 PM UTC 24 |
| Peak memory | 156464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462407471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 155.prim_prince_test.2462407471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/155.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/156.prim_prince_test.2463111198 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3114732337 ps |
| CPU time | 59.03 seconds |
| Started | Oct 14 08:19:30 PM UTC 24 |
| Finished | Oct 14 08:20:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463111198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 156.prim_prince_test.2463111198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/156.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/157.prim_prince_test.140934671 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2403359124 ps |
| CPU time | 45.73 seconds |
| Started | Oct 14 08:19:31 PM UTC 24 |
| Finished | Oct 14 08:20:29 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140934671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 157.prim_prince_test.140934671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/157.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/158.prim_prince_test.4087103520 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1661933344 ps |
| CPU time | 30.49 seconds |
| Started | Oct 14 08:19:32 PM UTC 24 |
| Finished | Oct 14 08:20:11 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087103520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 158.prim_prince_test.4087103520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/158.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/159.prim_prince_test.2959878888 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2559207416 ps |
| CPU time | 47.35 seconds |
| Started | Oct 14 08:19:32 PM UTC 24 |
| Finished | Oct 14 08:20:32 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959878888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 159.prim_prince_test.2959878888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/159.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/16.prim_prince_test.1821597349 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3047047401 ps |
| CPU time | 57.03 seconds |
| Started | Oct 14 08:16:45 PM UTC 24 |
| Finished | Oct 14 08:17:59 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821597349 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 16.prim_prince_test.1821597349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/16.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/160.prim_prince_test.1871425384 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3432157336 ps |
| CPU time | 63.22 seconds |
| Started | Oct 14 08:19:33 PM UTC 24 |
| Finished | Oct 14 08:20:53 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871425384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 160.prim_prince_test.1871425384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/160.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/161.prim_prince_test.3388321906 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1870932371 ps |
| CPU time | 35.4 seconds |
| Started | Oct 14 08:19:33 PM UTC 24 |
| Finished | Oct 14 08:20:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388321906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 161.prim_prince_test.3388321906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/161.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/162.prim_prince_test.29469396 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2436592692 ps |
| CPU time | 45.01 seconds |
| Started | Oct 14 08:19:35 PM UTC 24 |
| Finished | Oct 14 08:20:32 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29469396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 162.prim_prince_test.29469396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/162.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/163.prim_prince_test.283545629 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3610320703 ps |
| CPU time | 66.8 seconds |
| Started | Oct 14 08:19:35 PM UTC 24 |
| Finished | Oct 14 08:20:59 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283545629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 163.prim_prince_test.283545629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/163.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/164.prim_prince_test.3430381455 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3303184915 ps |
| CPU time | 60.08 seconds |
| Started | Oct 14 08:19:35 PM UTC 24 |
| Finished | Oct 14 08:20:51 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430381455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 164.prim_prince_test.3430381455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/164.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/165.prim_prince_test.1981661978 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1111250021 ps |
| CPU time | 21.38 seconds |
| Started | Oct 14 08:19:36 PM UTC 24 |
| Finished | Oct 14 08:20:03 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981661978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 165.prim_prince_test.1981661978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/165.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/166.prim_prince_test.1226217682 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1094097540 ps |
| CPU time | 20.44 seconds |
| Started | Oct 14 08:19:37 PM UTC 24 |
| Finished | Oct 14 08:20:03 PM UTC 24 |
| Peak memory | 154916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226217682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 166.prim_prince_test.1226217682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/166.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/167.prim_prince_test.2272211876 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1502627644 ps |
| CPU time | 27.95 seconds |
| Started | Oct 14 08:19:37 PM UTC 24 |
| Finished | Oct 14 08:20:13 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272211876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 167.prim_prince_test.2272211876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/167.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/168.prim_prince_test.2361741091 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2253551409 ps |
| CPU time | 42.63 seconds |
| Started | Oct 14 08:19:37 PM UTC 24 |
| Finished | Oct 14 08:20:31 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361741091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 168.prim_prince_test.2361741091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/168.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/169.prim_prince_test.2983568545 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 1382926006 ps |
| CPU time | 26.12 seconds |
| Started | Oct 14 08:19:38 PM UTC 24 |
| Finished | Oct 14 08:20:11 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983568545 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 169.prim_prince_test.2983568545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/169.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/17.prim_prince_test.870761493 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 871291379 ps |
| CPU time | 16.51 seconds |
| Started | Oct 14 08:16:48 PM UTC 24 |
| Finished | Oct 14 08:17:10 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870761493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 17.prim_prince_test.870761493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/17.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/170.prim_prince_test.66722176 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3237964381 ps |
| CPU time | 61.48 seconds |
| Started | Oct 14 08:19:39 PM UTC 24 |
| Finished | Oct 14 08:20:56 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66722176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 170.prim_prince_test.66722176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/170.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/171.prim_prince_test.27704761 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1411269351 ps |
| CPU time | 25.96 seconds |
| Started | Oct 14 08:19:39 PM UTC 24 |
| Finished | Oct 14 08:20:13 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27704761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 171.prim_prince_test.27704761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/171.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/172.prim_prince_test.1056577426 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2490830585 ps |
| CPU time | 47.14 seconds |
| Started | Oct 14 08:19:42 PM UTC 24 |
| Finished | Oct 14 08:20:42 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056577426 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 172.prim_prince_test.1056577426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/172.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/173.prim_prince_test.3451099386 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1304964992 ps |
| CPU time | 24.92 seconds |
| Started | Oct 14 08:19:42 PM UTC 24 |
| Finished | Oct 14 08:20:14 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451099386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 173.prim_prince_test.3451099386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/173.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/174.prim_prince_test.1074026417 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2508440506 ps |
| CPU time | 46.27 seconds |
| Started | Oct 14 08:19:46 PM UTC 24 |
| Finished | Oct 14 08:20:46 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074026417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 174.prim_prince_test.1074026417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/174.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/175.prim_prince_test.2648030244 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1334340701 ps |
| CPU time | 25.51 seconds |
| Started | Oct 14 08:19:48 PM UTC 24 |
| Finished | Oct 14 08:20:20 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648030244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 175.prim_prince_test.2648030244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/175.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/176.prim_prince_test.178632245 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 898819949 ps |
| CPU time | 17.17 seconds |
| Started | Oct 14 08:19:49 PM UTC 24 |
| Finished | Oct 14 08:20:11 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178632245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 176.prim_prince_test.178632245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/176.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/177.prim_prince_test.1192730137 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2839840671 ps |
| CPU time | 52.73 seconds |
| Started | Oct 14 08:19:49 PM UTC 24 |
| Finished | Oct 14 08:20:55 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192730137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 177.prim_prince_test.1192730137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/177.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/178.prim_prince_test.3124418114 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1582773355 ps |
| CPU time | 29.4 seconds |
| Started | Oct 14 08:19:49 PM UTC 24 |
| Finished | Oct 14 08:20:27 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124418114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 178.prim_prince_test.3124418114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/178.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/179.prim_prince_test.4278861220 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3190269050 ps |
| CPU time | 60.27 seconds |
| Started | Oct 14 08:19:50 PM UTC 24 |
| Finished | Oct 14 08:21:06 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278861220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 179.prim_prince_test.4278861220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/179.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/18.prim_prince_test.2069401490 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1447156486 ps |
| CPU time | 28.55 seconds |
| Started | Oct 14 08:16:49 PM UTC 24 |
| Finished | Oct 14 08:17:25 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069401490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 18.prim_prince_test.2069401490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/18.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/180.prim_prince_test.187474739 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1698452735 ps |
| CPU time | 32.49 seconds |
| Started | Oct 14 08:19:51 PM UTC 24 |
| Finished | Oct 14 08:20:32 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187474739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 180.prim_prince_test.187474739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/180.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/181.prim_prince_test.4121243776 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3181657110 ps |
| CPU time | 58.66 seconds |
| Started | Oct 14 08:19:54 PM UTC 24 |
| Finished | Oct 14 08:21:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121243776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 181.prim_prince_test.4121243776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/181.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/182.prim_prince_test.3443506198 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 1151950098 ps |
| CPU time | 21.34 seconds |
| Started | Oct 14 08:19:55 PM UTC 24 |
| Finished | Oct 14 08:20:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443506198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 182.prim_prince_test.3443506198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/182.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/183.prim_prince_test.2503510862 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1186299313 ps |
| CPU time | 22.77 seconds |
| Started | Oct 14 08:19:56 PM UTC 24 |
| Finished | Oct 14 08:20:25 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503510862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 183.prim_prince_test.2503510862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/183.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/184.prim_prince_test.1062300946 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2181927386 ps |
| CPU time | 41.37 seconds |
| Started | Oct 14 08:19:57 PM UTC 24 |
| Finished | Oct 14 08:20:50 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062300946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 184.prim_prince_test.1062300946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/184.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/185.prim_prince_test.835219918 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1562664658 ps |
| CPU time | 29.81 seconds |
| Started | Oct 14 08:20:00 PM UTC 24 |
| Finished | Oct 14 08:20:38 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835219918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 185.prim_prince_test.835219918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/185.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/186.prim_prince_test.2588639754 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3207528428 ps |
| CPU time | 58.5 seconds |
| Started | Oct 14 08:20:02 PM UTC 24 |
| Finished | Oct 14 08:21:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588639754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 186.prim_prince_test.2588639754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/186.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/187.prim_prince_test.2894254799 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2263392248 ps |
| CPU time | 41.33 seconds |
| Started | Oct 14 08:20:04 PM UTC 24 |
| Finished | Oct 14 08:20:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894254799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 187.prim_prince_test.2894254799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/187.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/188.prim_prince_test.1669419011 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 3585773127 ps |
| CPU time | 65.21 seconds |
| Started | Oct 14 08:20:04 PM UTC 24 |
| Finished | Oct 14 08:21:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669419011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 188.prim_prince_test.1669419011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/188.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/189.prim_prince_test.941437448 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1633912536 ps |
| CPU time | 30.93 seconds |
| Started | Oct 14 08:20:05 PM UTC 24 |
| Finished | Oct 14 08:20:44 PM UTC 24 |
| Peak memory | 154828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941437448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 189.prim_prince_test.941437448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/189.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/19.prim_prince_test.2623898945 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 949263046 ps |
| CPU time | 18.76 seconds |
| Started | Oct 14 08:16:49 PM UTC 24 |
| Finished | Oct 14 08:17:13 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623898945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 19.prim_prince_test.2623898945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/19.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/190.prim_prince_test.1552847423 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1625624734 ps |
| CPU time | 30.41 seconds |
| Started | Oct 14 08:20:05 PM UTC 24 |
| Finished | Oct 14 08:20:44 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552847423 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 190.prim_prince_test.1552847423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/190.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/191.prim_prince_test.4161122524 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1829152510 ps |
| CPU time | 34.54 seconds |
| Started | Oct 14 08:20:05 PM UTC 24 |
| Finished | Oct 14 08:20:49 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161122524 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 191.prim_prince_test.4161122524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/191.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/192.prim_prince_test.4123709153 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2542274349 ps |
| CPU time | 47.7 seconds |
| Started | Oct 14 08:20:07 PM UTC 24 |
| Finished | Oct 14 08:21:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123709153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 192.prim_prince_test.4123709153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/192.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/193.prim_prince_test.3860465841 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 946762642 ps |
| CPU time | 17.93 seconds |
| Started | Oct 14 08:20:12 PM UTC 24 |
| Finished | Oct 14 08:20:36 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860465841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 193.prim_prince_test.3860465841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/193.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/194.prim_prince_test.3138959447 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3503284060 ps |
| CPU time | 66.16 seconds |
| Started | Oct 14 08:20:12 PM UTC 24 |
| Finished | Oct 14 08:21:35 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138959447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 194.prim_prince_test.3138959447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/194.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/195.prim_prince_test.1852951552 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2872095833 ps |
| CPU time | 52.18 seconds |
| Started | Oct 14 08:20:12 PM UTC 24 |
| Finished | Oct 14 08:21:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852951552 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 195.prim_prince_test.1852951552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/195.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/196.prim_prince_test.2209311920 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3301875811 ps |
| CPU time | 62.28 seconds |
| Started | Oct 14 08:20:12 PM UTC 24 |
| Finished | Oct 14 08:21:31 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209311920 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 196.prim_prince_test.2209311920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/196.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/197.prim_prince_test.386362370 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2110974266 ps |
| CPU time | 39.93 seconds |
| Started | Oct 14 08:20:13 PM UTC 24 |
| Finished | Oct 14 08:21:03 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386362370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 197.prim_prince_test.386362370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/197.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/198.prim_prince_test.184780748 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 2827575020 ps |
| CPU time | 51.22 seconds |
| Started | Oct 14 08:20:13 PM UTC 24 |
| Finished | Oct 14 08:21:18 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184780748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 198.prim_prince_test.184780748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/198.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/199.prim_prince_test.4084622929 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2280927173 ps |
| CPU time | 42 seconds |
| Started | Oct 14 08:20:14 PM UTC 24 |
| Finished | Oct 14 08:21:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084622929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 199.prim_prince_test.4084622929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/199.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/2.prim_prince_test.1765364979 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 899104391 ps |
| CPU time | 18.43 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:02 PM UTC 24 |
| Peak memory | 154888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765364979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.prim_prince_test.1765364979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/2.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/20.prim_prince_test.2726966126 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3743412311 ps |
| CPU time | 72.24 seconds |
| Started | Oct 14 08:16:50 PM UTC 24 |
| Finished | Oct 14 08:18:21 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726966126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 20.prim_prince_test.2726966126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/20.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/200.prim_prince_test.2836420408 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 3725830466 ps |
| CPU time | 67.75 seconds |
| Started | Oct 14 08:20:14 PM UTC 24 |
| Finished | Oct 14 08:21:40 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836420408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 200.prim_prince_test.2836420408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/200.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/201.prim_prince_test.1393063816 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1557915842 ps |
| CPU time | 28.36 seconds |
| Started | Oct 14 08:20:14 PM UTC 24 |
| Finished | Oct 14 08:20:51 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393063816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 201.prim_prince_test.1393063816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/201.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/202.prim_prince_test.3270534500 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2948252882 ps |
| CPU time | 55.5 seconds |
| Started | Oct 14 08:20:15 PM UTC 24 |
| Finished | Oct 14 08:21:25 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270534500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 202.prim_prince_test.3270534500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/202.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/203.prim_prince_test.922604263 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3511787661 ps |
| CPU time | 66.46 seconds |
| Started | Oct 14 08:20:16 PM UTC 24 |
| Finished | Oct 14 08:21:39 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922604263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 203.prim_prince_test.922604263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/203.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/204.prim_prince_test.4055679142 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1130275099 ps |
| CPU time | 21.4 seconds |
| Started | Oct 14 08:20:19 PM UTC 24 |
| Finished | Oct 14 08:20:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055679142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 204.prim_prince_test.4055679142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/204.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/205.prim_prince_test.3506297839 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3522722343 ps |
| CPU time | 65.28 seconds |
| Started | Oct 14 08:20:21 PM UTC 24 |
| Finished | Oct 14 08:21:44 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506297839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 205.prim_prince_test.3506297839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/205.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/206.prim_prince_test.1058488069 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3153897587 ps |
| CPU time | 59.61 seconds |
| Started | Oct 14 08:20:21 PM UTC 24 |
| Finished | Oct 14 08:21:36 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058488069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 206.prim_prince_test.1058488069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/206.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/207.prim_prince_test.3687303903 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 3642298380 ps |
| CPU time | 68.71 seconds |
| Started | Oct 14 08:20:22 PM UTC 24 |
| Finished | Oct 14 08:21:49 PM UTC 24 |
| Peak memory | 155028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687303903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 207.prim_prince_test.3687303903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/207.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/208.prim_prince_test.3195819376 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 1432513533 ps |
| CPU time | 26.4 seconds |
| Started | Oct 14 08:20:22 PM UTC 24 |
| Finished | Oct 14 08:20:57 PM UTC 24 |
| Peak memory | 154968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195819376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 208.prim_prince_test.3195819376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/208.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/209.prim_prince_test.265185849 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2529779704 ps |
| CPU time | 47.98 seconds |
| Started | Oct 14 08:20:24 PM UTC 24 |
| Finished | Oct 14 08:21:24 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265185849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 209.prim_prince_test.265185849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/209.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/21.prim_prince_test.2273724629 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1910105248 ps |
| CPU time | 37.82 seconds |
| Started | Oct 14 08:16:50 PM UTC 24 |
| Finished | Oct 14 08:17:38 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273724629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 21.prim_prince_test.2273724629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/21.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/210.prim_prince_test.3933493414 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2306475577 ps |
| CPU time | 43.85 seconds |
| Started | Oct 14 08:20:27 PM UTC 24 |
| Finished | Oct 14 08:21:22 PM UTC 24 |
| Peak memory | 154864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933493414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 210.prim_prince_test.3933493414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/210.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/211.prim_prince_test.884882676 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1876358737 ps |
| CPU time | 35.38 seconds |
| Started | Oct 14 08:20:27 PM UTC 24 |
| Finished | Oct 14 08:21:12 PM UTC 24 |
| Peak memory | 154664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884882676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 211.prim_prince_test.884882676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/211.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/212.prim_prince_test.2567108382 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3572734260 ps |
| CPU time | 67.22 seconds |
| Started | Oct 14 08:20:28 PM UTC 24 |
| Finished | Oct 14 08:21:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567108382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 212.prim_prince_test.2567108382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/212.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/213.prim_prince_test.2601644407 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 3043979101 ps |
| CPU time | 55.74 seconds |
| Started | Oct 14 08:20:28 PM UTC 24 |
| Finished | Oct 14 08:21:39 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601644407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 213.prim_prince_test.2601644407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/213.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/214.prim_prince_test.1149033797 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1024655491 ps |
| CPU time | 19.07 seconds |
| Started | Oct 14 08:20:29 PM UTC 24 |
| Finished | Oct 14 08:20:54 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149033797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 214.prim_prince_test.1149033797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/214.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/215.prim_prince_test.1525116295 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2852850748 ps |
| CPU time | 53.02 seconds |
| Started | Oct 14 08:20:31 PM UTC 24 |
| Finished | Oct 14 08:21:38 PM UTC 24 |
| Peak memory | 156460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525116295 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 215.prim_prince_test.1525116295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/215.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/216.prim_prince_test.1185021372 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2592623115 ps |
| CPU time | 48.36 seconds |
| Started | Oct 14 08:20:32 PM UTC 24 |
| Finished | Oct 14 08:21:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185021372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 216.prim_prince_test.1185021372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/216.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/217.prim_prince_test.959661006 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3677333854 ps |
| CPU time | 69.15 seconds |
| Started | Oct 14 08:20:32 PM UTC 24 |
| Finished | Oct 14 08:21:59 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959661006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 217.prim_prince_test.959661006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/217.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/218.prim_prince_test.3704627391 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1666661693 ps |
| CPU time | 31.96 seconds |
| Started | Oct 14 08:20:34 PM UTC 24 |
| Finished | Oct 14 08:21:14 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704627391 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 218.prim_prince_test.3704627391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/218.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/219.prim_prince_test.1137038092 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1301725295 ps |
| CPU time | 24.23 seconds |
| Started | Oct 14 08:20:34 PM UTC 24 |
| Finished | Oct 14 08:21:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137038092 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 219.prim_prince_test.1137038092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/219.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/22.prim_prince_test.738075351 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 1705275288 ps |
| CPU time | 32.76 seconds |
| Started | Oct 14 08:16:50 PM UTC 24 |
| Finished | Oct 14 08:17:32 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738075351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 22.prim_prince_test.738075351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/22.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/220.prim_prince_test.1812857467 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 1884368263 ps |
| CPU time | 34.67 seconds |
| Started | Oct 14 08:20:34 PM UTC 24 |
| Finished | Oct 14 08:21:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812857467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 220.prim_prince_test.1812857467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/220.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/221.prim_prince_test.4168153134 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 1432871064 ps |
| CPU time | 26.83 seconds |
| Started | Oct 14 08:20:36 PM UTC 24 |
| Finished | Oct 14 08:21:10 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168153134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 221.prim_prince_test.4168153134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/221.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/222.prim_prince_test.3751632263 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2419144187 ps |
| CPU time | 45.31 seconds |
| Started | Oct 14 08:20:36 PM UTC 24 |
| Finished | Oct 14 08:21:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751632263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 222.prim_prince_test.3751632263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/222.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/223.prim_prince_test.4168809141 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1824371912 ps |
| CPU time | 34.99 seconds |
| Started | Oct 14 08:20:37 PM UTC 24 |
| Finished | Oct 14 08:21:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168809141 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 223.prim_prince_test.4168809141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/223.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/224.prim_prince_test.1012782402 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 2203626903 ps |
| CPU time | 42.06 seconds |
| Started | Oct 14 08:20:38 PM UTC 24 |
| Finished | Oct 14 08:21:31 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012782402 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 224.prim_prince_test.1012782402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/224.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/225.prim_prince_test.1611376388 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 965658475 ps |
| CPU time | 18.51 seconds |
| Started | Oct 14 08:20:38 PM UTC 24 |
| Finished | Oct 14 08:21:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611376388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 225.prim_prince_test.1611376388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/225.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/226.prim_prince_test.3925803243 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3138633920 ps |
| CPU time | 57.92 seconds |
| Started | Oct 14 08:20:38 PM UTC 24 |
| Finished | Oct 14 08:21:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925803243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 226.prim_prince_test.3925803243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/226.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/227.prim_prince_test.3534727301 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2895006018 ps |
| CPU time | 52.61 seconds |
| Started | Oct 14 08:20:38 PM UTC 24 |
| Finished | Oct 14 08:21:46 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534727301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 227.prim_prince_test.3534727301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/227.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/228.prim_prince_test.1171760318 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3214246286 ps |
| CPU time | 58.67 seconds |
| Started | Oct 14 08:20:40 PM UTC 24 |
| Finished | Oct 14 08:21:54 PM UTC 24 |
| Peak memory | 155008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171760318 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 228.prim_prince_test.1171760318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/228.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/229.prim_prince_test.3424417606 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 1605898998 ps |
| CPU time | 30.39 seconds |
| Started | Oct 14 08:20:40 PM UTC 24 |
| Finished | Oct 14 08:21:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424417606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 229.prim_prince_test.3424417606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/229.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/23.prim_prince_test.4098081617 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2938740204 ps |
| CPU time | 56.43 seconds |
| Started | Oct 14 08:16:51 PM UTC 24 |
| Finished | Oct 14 08:18:03 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098081617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 23.prim_prince_test.4098081617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/23.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/230.prim_prince_test.1729038242 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1268630554 ps |
| CPU time | 23.51 seconds |
| Started | Oct 14 08:20:43 PM UTC 24 |
| Finished | Oct 14 08:21:13 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729038242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 230.prim_prince_test.1729038242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/230.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/231.prim_prince_test.117016259 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2692726743 ps |
| CPU time | 50.98 seconds |
| Started | Oct 14 08:20:45 PM UTC 24 |
| Finished | Oct 14 08:21:49 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117016259 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 231.prim_prince_test.117016259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/231.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/232.prim_prince_test.1535648192 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 787912776 ps |
| CPU time | 15.32 seconds |
| Started | Oct 14 08:20:45 PM UTC 24 |
| Finished | Oct 14 08:21:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535648192 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 232.prim_prince_test.1535648192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/232.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/233.prim_prince_test.3015377269 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3716170055 ps |
| CPU time | 68.59 seconds |
| Started | Oct 14 08:20:45 PM UTC 24 |
| Finished | Oct 14 08:22:12 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015377269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 233.prim_prince_test.3015377269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/233.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/234.prim_prince_test.955774752 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 1447207509 ps |
| CPU time | 27.78 seconds |
| Started | Oct 14 08:20:46 PM UTC 24 |
| Finished | Oct 14 08:21:21 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955774752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 234.prim_prince_test.955774752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/234.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/235.prim_prince_test.2415288037 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 1912210226 ps |
| CPU time | 35.87 seconds |
| Started | Oct 14 08:20:48 PM UTC 24 |
| Finished | Oct 14 08:21:34 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415288037 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 235.prim_prince_test.2415288037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/235.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/236.prim_prince_test.2047166868 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1074843647 ps |
| CPU time | 20.16 seconds |
| Started | Oct 14 08:20:49 PM UTC 24 |
| Finished | Oct 14 08:21:15 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047166868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 236.prim_prince_test.2047166868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/236.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/237.prim_prince_test.967020990 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 1004887959 ps |
| CPU time | 19.36 seconds |
| Started | Oct 14 08:20:50 PM UTC 24 |
| Finished | Oct 14 08:21:15 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967020990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 237.prim_prince_test.967020990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/237.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/238.prim_prince_test.4066922736 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1263744363 ps |
| CPU time | 24.24 seconds |
| Started | Oct 14 08:20:52 PM UTC 24 |
| Finished | Oct 14 08:21:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066922736 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 238.prim_prince_test.4066922736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/238.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/239.prim_prince_test.3720614689 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2818406290 ps |
| CPU time | 51.92 seconds |
| Started | Oct 14 08:20:52 PM UTC 24 |
| Finished | Oct 14 08:21:57 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720614689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 239.prim_prince_test.3720614689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/239.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/24.prim_prince_test.2903623008 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2917951870 ps |
| CPU time | 55.13 seconds |
| Started | Oct 14 08:16:52 PM UTC 24 |
| Finished | Oct 14 08:18:03 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903623008 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.prim_prince_test.2903623008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/24.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/240.prim_prince_test.2731496960 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2680983426 ps |
| CPU time | 48.78 seconds |
| Started | Oct 14 08:20:54 PM UTC 24 |
| Finished | Oct 14 08:21:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731496960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 240.prim_prince_test.2731496960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/240.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/241.prim_prince_test.2824024042 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2614400716 ps |
| CPU time | 47.99 seconds |
| Started | Oct 14 08:20:55 PM UTC 24 |
| Finished | Oct 14 08:21:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824024042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 241.prim_prince_test.2824024042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/241.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/242.prim_prince_test.2306571471 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2151228154 ps |
| CPU time | 39.29 seconds |
| Started | Oct 14 08:20:56 PM UTC 24 |
| Finished | Oct 14 08:21:46 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306571471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 242.prim_prince_test.2306571471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/242.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/243.prim_prince_test.2084308404 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 3039041473 ps |
| CPU time | 54.98 seconds |
| Started | Oct 14 08:20:57 PM UTC 24 |
| Finished | Oct 14 08:22:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084308404 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 243.prim_prince_test.2084308404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/243.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/244.prim_prince_test.3850557963 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2712468632 ps |
| CPU time | 51.18 seconds |
| Started | Oct 14 08:20:57 PM UTC 24 |
| Finished | Oct 14 08:22:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850557963 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 244.prim_prince_test.3850557963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/244.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/245.prim_prince_test.2847697588 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 2233260520 ps |
| CPU time | 41.02 seconds |
| Started | Oct 14 08:20:57 PM UTC 24 |
| Finished | Oct 14 08:21:49 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847697588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 245.prim_prince_test.2847697588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/245.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/246.prim_prince_test.2201722055 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 1038386750 ps |
| CPU time | 20.04 seconds |
| Started | Oct 14 08:21:00 PM UTC 24 |
| Finished | Oct 14 08:21:26 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201722055 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 246.prim_prince_test.2201722055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/246.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/247.prim_prince_test.900700731 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3094894275 ps |
| CPU time | 58.35 seconds |
| Started | Oct 14 08:21:04 PM UTC 24 |
| Finished | Oct 14 08:22:17 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900700731 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 247.prim_prince_test.900700731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/247.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/248.prim_prince_test.3452776287 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1581080980 ps |
| CPU time | 29.73 seconds |
| Started | Oct 14 08:21:04 PM UTC 24 |
| Finished | Oct 14 08:21:42 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452776287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 248.prim_prince_test.3452776287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/248.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/249.prim_prince_test.1615136797 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3511315783 ps |
| CPU time | 66.22 seconds |
| Started | Oct 14 08:21:04 PM UTC 24 |
| Finished | Oct 14 08:22:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615136797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 249.prim_prince_test.1615136797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/249.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/25.prim_prince_test.2130703316 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 1888575276 ps |
| CPU time | 37.02 seconds |
| Started | Oct 14 08:16:53 PM UTC 24 |
| Finished | Oct 14 08:17:40 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130703316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 25.prim_prince_test.2130703316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/25.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/250.prim_prince_test.361127179 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3305791689 ps |
| CPU time | 61.07 seconds |
| Started | Oct 14 08:21:06 PM UTC 24 |
| Finished | Oct 14 08:22:23 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361127179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 250.prim_prince_test.361127179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/250.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/251.prim_prince_test.3328337333 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1918363876 ps |
| CPU time | 36.45 seconds |
| Started | Oct 14 08:21:06 PM UTC 24 |
| Finished | Oct 14 08:21:52 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328337333 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 251.prim_prince_test.3328337333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/251.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/252.prim_prince_test.2201494362 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3378521372 ps |
| CPU time | 62.63 seconds |
| Started | Oct 14 08:21:07 PM UTC 24 |
| Finished | Oct 14 08:22:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201494362 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 252.prim_prince_test.2201494362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/252.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/253.prim_prince_test.2574212211 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1168033487 ps |
| CPU time | 22.29 seconds |
| Started | Oct 14 08:21:08 PM UTC 24 |
| Finished | Oct 14 08:21:37 PM UTC 24 |
| Peak memory | 154888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574212211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 253.prim_prince_test.2574212211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/253.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/254.prim_prince_test.3540607497 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2808184829 ps |
| CPU time | 52.23 seconds |
| Started | Oct 14 08:21:08 PM UTC 24 |
| Finished | Oct 14 08:22:14 PM UTC 24 |
| Peak memory | 154800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540607497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 254.prim_prince_test.3540607497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/254.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/255.prim_prince_test.3688793302 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2434954693 ps |
| CPU time | 45.81 seconds |
| Started | Oct 14 08:21:09 PM UTC 24 |
| Finished | Oct 14 08:22:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688793302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 255.prim_prince_test.3688793302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/255.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/256.prim_prince_test.2932529969 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 1296836784 ps |
| CPU time | 24.65 seconds |
| Started | Oct 14 08:21:11 PM UTC 24 |
| Finished | Oct 14 08:21:43 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932529969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 256.prim_prince_test.2932529969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/256.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/257.prim_prince_test.1597828230 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2062961460 ps |
| CPU time | 37.59 seconds |
| Started | Oct 14 08:21:13 PM UTC 24 |
| Finished | Oct 14 08:22:01 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597828230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 257.prim_prince_test.1597828230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/257.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/258.prim_prince_test.1452551353 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3207907861 ps |
| CPU time | 57.99 seconds |
| Started | Oct 14 08:21:14 PM UTC 24 |
| Finished | Oct 14 08:22:27 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452551353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 258.prim_prince_test.1452551353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/258.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/259.prim_prince_test.1191615825 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2786988920 ps |
| CPU time | 50.77 seconds |
| Started | Oct 14 08:21:15 PM UTC 24 |
| Finished | Oct 14 08:22:19 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191615825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 259.prim_prince_test.1191615825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/259.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/26.prim_prince_test.421336946 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1992631558 ps |
| CPU time | 39.69 seconds |
| Started | Oct 14 08:16:53 PM UTC 24 |
| Finished | Oct 14 08:17:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421336946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 26.prim_prince_test.421336946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/26.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/260.prim_prince_test.3647374219 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 897687447 ps |
| CPU time | 17 seconds |
| Started | Oct 14 08:21:16 PM UTC 24 |
| Finished | Oct 14 08:21:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647374219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 260.prim_prince_test.3647374219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/260.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/261.prim_prince_test.2393159516 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3538902096 ps |
| CPU time | 66.82 seconds |
| Started | Oct 14 08:21:16 PM UTC 24 |
| Finished | Oct 14 08:22:40 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393159516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 261.prim_prince_test.2393159516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/261.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/262.prim_prince_test.3901940245 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2263309140 ps |
| CPU time | 42.61 seconds |
| Started | Oct 14 08:21:17 PM UTC 24 |
| Finished | Oct 14 08:22:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901940245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 262.prim_prince_test.3901940245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/262.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/263.prim_prince_test.2815031355 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 992576607 ps |
| CPU time | 19 seconds |
| Started | Oct 14 08:21:18 PM UTC 24 |
| Finished | Oct 14 08:21:43 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815031355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 263.prim_prince_test.2815031355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/263.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/264.prim_prince_test.3456890532 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 3255457796 ps |
| CPU time | 60.78 seconds |
| Started | Oct 14 08:21:19 PM UTC 24 |
| Finished | Oct 14 08:22:36 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456890532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 264.prim_prince_test.3456890532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/264.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/265.prim_prince_test.3744539883 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1161350393 ps |
| CPU time | 21.52 seconds |
| Started | Oct 14 08:21:20 PM UTC 24 |
| Finished | Oct 14 08:21:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744539883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 265.prim_prince_test.3744539883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/265.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/266.prim_prince_test.3824748776 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1809673064 ps |
| CPU time | 34.25 seconds |
| Started | Oct 14 08:21:20 PM UTC 24 |
| Finished | Oct 14 08:22:03 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824748776 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 266.prim_prince_test.3824748776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/266.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/267.prim_prince_test.3705705090 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2183941451 ps |
| CPU time | 41.01 seconds |
| Started | Oct 14 08:21:22 PM UTC 24 |
| Finished | Oct 14 08:22:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705705090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 267.prim_prince_test.3705705090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/267.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/268.prim_prince_test.3697436064 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2192455536 ps |
| CPU time | 41.39 seconds |
| Started | Oct 14 08:21:22 PM UTC 24 |
| Finished | Oct 14 08:22:14 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697436064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 268.prim_prince_test.3697436064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/268.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/269.prim_prince_test.4118994116 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 924662195 ps |
| CPU time | 17.27 seconds |
| Started | Oct 14 08:21:23 PM UTC 24 |
| Finished | Oct 14 08:21:46 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118994116 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 269.prim_prince_test.4118994116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/269.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/27.prim_prince_test.3928765308 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 847902125 ps |
| CPU time | 17.25 seconds |
| Started | Oct 14 08:16:53 PM UTC 24 |
| Finished | Oct 14 08:17:16 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928765308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 27.prim_prince_test.3928765308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/27.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/270.prim_prince_test.2930223246 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3032937642 ps |
| CPU time | 56.41 seconds |
| Started | Oct 14 08:21:23 PM UTC 24 |
| Finished | Oct 14 08:22:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930223246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 270.prim_prince_test.2930223246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/270.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/271.prim_prince_test.3886193927 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1598433793 ps |
| CPU time | 29.48 seconds |
| Started | Oct 14 08:21:25 PM UTC 24 |
| Finished | Oct 14 08:22:03 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886193927 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 271.prim_prince_test.3886193927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/271.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/272.prim_prince_test.1420861679 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1266271566 ps |
| CPU time | 23.31 seconds |
| Started | Oct 14 08:21:26 PM UTC 24 |
| Finished | Oct 14 08:21:56 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420861679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 272.prim_prince_test.1420861679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/272.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/273.prim_prince_test.1344221108 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3259488402 ps |
| CPU time | 59.25 seconds |
| Started | Oct 14 08:21:27 PM UTC 24 |
| Finished | Oct 14 08:22:43 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344221108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 273.prim_prince_test.1344221108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/273.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/274.prim_prince_test.519311667 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3609918640 ps |
| CPU time | 67.61 seconds |
| Started | Oct 14 08:21:27 PM UTC 24 |
| Finished | Oct 14 08:22:52 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519311667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 274.prim_prince_test.519311667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/274.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/275.prim_prince_test.48243107 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1100681810 ps |
| CPU time | 20.96 seconds |
| Started | Oct 14 08:21:32 PM UTC 24 |
| Finished | Oct 14 08:21:59 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48243107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 275.prim_prince_test.48243107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/275.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/276.prim_prince_test.1962013329 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2684829578 ps |
| CPU time | 50.96 seconds |
| Started | Oct 14 08:21:33 PM UTC 24 |
| Finished | Oct 14 08:22:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962013329 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 276.prim_prince_test.1962013329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/276.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/277.prim_prince_test.679239787 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3022191534 ps |
| CPU time | 56.8 seconds |
| Started | Oct 14 08:21:34 PM UTC 24 |
| Finished | Oct 14 08:22:45 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679239787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 277.prim_prince_test.679239787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/277.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/278.prim_prince_test.4178752015 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 1690440004 ps |
| CPU time | 32.09 seconds |
| Started | Oct 14 08:21:35 PM UTC 24 |
| Finished | Oct 14 08:22:16 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178752015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 278.prim_prince_test.4178752015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/278.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/279.prim_prince_test.3096718393 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1877670921 ps |
| CPU time | 34.54 seconds |
| Started | Oct 14 08:21:35 PM UTC 24 |
| Finished | Oct 14 08:22:19 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096718393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 279.prim_prince_test.3096718393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/279.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/28.prim_prince_test.984439678 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 3088995829 ps |
| CPU time | 57.59 seconds |
| Started | Oct 14 08:16:53 PM UTC 24 |
| Finished | Oct 14 08:18:07 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984439678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.prim_prince_test.984439678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/28.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/280.prim_prince_test.2609365254 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1107264724 ps |
| CPU time | 21.15 seconds |
| Started | Oct 14 08:21:36 PM UTC 24 |
| Finished | Oct 14 08:22:03 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609365254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 280.prim_prince_test.2609365254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/280.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/281.prim_prince_test.2937323419 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 854052994 ps |
| CPU time | 15.9 seconds |
| Started | Oct 14 08:21:37 PM UTC 24 |
| Finished | Oct 14 08:21:58 PM UTC 24 |
| Peak memory | 154940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937323419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 281.prim_prince_test.2937323419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/281.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/282.prim_prince_test.1642719266 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3540857136 ps |
| CPU time | 64.28 seconds |
| Started | Oct 14 08:21:37 PM UTC 24 |
| Finished | Oct 14 08:22:59 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642719266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 282.prim_prince_test.1642719266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/282.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/283.prim_prince_test.3225180372 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3122433641 ps |
| CPU time | 58.02 seconds |
| Started | Oct 14 08:21:39 PM UTC 24 |
| Finished | Oct 14 08:22:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225180372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 283.prim_prince_test.3225180372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/283.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/284.prim_prince_test.3478555472 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1667059759 ps |
| CPU time | 30.45 seconds |
| Started | Oct 14 08:21:39 PM UTC 24 |
| Finished | Oct 14 08:22:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478555472 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 284.prim_prince_test.3478555472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/284.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/285.prim_prince_test.2059739238 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2626228557 ps |
| CPU time | 49.32 seconds |
| Started | Oct 14 08:21:40 PM UTC 24 |
| Finished | Oct 14 08:22:42 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059739238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 285.prim_prince_test.2059739238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/285.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/286.prim_prince_test.3192497058 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3440694849 ps |
| CPU time | 62.35 seconds |
| Started | Oct 14 08:21:40 PM UTC 24 |
| Finished | Oct 14 08:22:59 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192497058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 286.prim_prince_test.3192497058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/286.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/287.prim_prince_test.3547793754 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1605126233 ps |
| CPU time | 30.3 seconds |
| Started | Oct 14 08:21:41 PM UTC 24 |
| Finished | Oct 14 08:22:19 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547793754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 287.prim_prince_test.3547793754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/287.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/288.prim_prince_test.1159505804 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3534893411 ps |
| CPU time | 66.2 seconds |
| Started | Oct 14 08:21:42 PM UTC 24 |
| Finished | Oct 14 08:23:05 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159505804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 288.prim_prince_test.1159505804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/288.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/289.prim_prince_test.3434545572 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 893585539 ps |
| CPU time | 17.1 seconds |
| Started | Oct 14 08:21:43 PM UTC 24 |
| Finished | Oct 14 08:22:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434545572 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 289.prim_prince_test.3434545572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/289.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/29.prim_prince_test.3578834126 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1069877799 ps |
| CPU time | 20.39 seconds |
| Started | Oct 14 08:16:53 PM UTC 24 |
| Finished | Oct 14 08:17:20 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578834126 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 29.prim_prince_test.3578834126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/29.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/290.prim_prince_test.3250220357 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2966310760 ps |
| CPU time | 55.72 seconds |
| Started | Oct 14 08:21:44 PM UTC 24 |
| Finished | Oct 14 08:22:54 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250220357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 290.prim_prince_test.3250220357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/290.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/291.prim_prince_test.3250927302 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 3649641788 ps |
| CPU time | 66.58 seconds |
| Started | Oct 14 08:21:44 PM UTC 24 |
| Finished | Oct 14 08:23:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250927302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 291.prim_prince_test.3250927302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/291.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/292.prim_prince_test.3769976734 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3059626848 ps |
| CPU time | 56.89 seconds |
| Started | Oct 14 08:21:45 PM UTC 24 |
| Finished | Oct 14 08:22:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769976734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 292.prim_prince_test.3769976734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/292.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/293.prim_prince_test.257716866 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3319137124 ps |
| CPU time | 62.16 seconds |
| Started | Oct 14 08:21:47 PM UTC 24 |
| Finished | Oct 14 08:23:05 PM UTC 24 |
| Peak memory | 154944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257716866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 293.prim_prince_test.257716866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/293.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/294.prim_prince_test.3519738306 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 1625846174 ps |
| CPU time | 30.68 seconds |
| Started | Oct 14 08:21:47 PM UTC 24 |
| Finished | Oct 14 08:22:26 PM UTC 24 |
| Peak memory | 154872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519738306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 294.prim_prince_test.3519738306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/294.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/295.prim_prince_test.1433877380 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1713116624 ps |
| CPU time | 31.38 seconds |
| Started | Oct 14 08:21:47 PM UTC 24 |
| Finished | Oct 14 08:22:27 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433877380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 295.prim_prince_test.1433877380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/295.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/296.prim_prince_test.2531572413 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3485327574 ps |
| CPU time | 64.88 seconds |
| Started | Oct 14 08:21:48 PM UTC 24 |
| Finished | Oct 14 08:23:10 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531572413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 296.prim_prince_test.2531572413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/296.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/297.prim_prince_test.510358355 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2796781974 ps |
| CPU time | 50.91 seconds |
| Started | Oct 14 08:21:49 PM UTC 24 |
| Finished | Oct 14 08:22:54 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510358355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 297.prim_prince_test.510358355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/297.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/298.prim_prince_test.1755558240 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1178292362 ps |
| CPU time | 21.72 seconds |
| Started | Oct 14 08:21:50 PM UTC 24 |
| Finished | Oct 14 08:22:19 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755558240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 298.prim_prince_test.1755558240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/298.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/299.prim_prince_test.1639650171 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2239322744 ps |
| CPU time | 42.19 seconds |
| Started | Oct 14 08:21:50 PM UTC 24 |
| Finished | Oct 14 08:22:44 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639650171 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 299.prim_prince_test.1639650171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/299.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/3.prim_prince_test.2101364707 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1195398914 ps |
| CPU time | 23.44 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:09 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101364707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 3.prim_prince_test.2101364707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/3.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/30.prim_prince_test.1355690785 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3591031100 ps |
| CPU time | 68.48 seconds |
| Started | Oct 14 08:16:54 PM UTC 24 |
| Finished | Oct 14 08:18:21 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355690785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 30.prim_prince_test.1355690785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/30.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/300.prim_prince_test.562133096 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1459783478 ps |
| CPU time | 27.87 seconds |
| Started | Oct 14 08:21:53 PM UTC 24 |
| Finished | Oct 14 08:22:28 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562133096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 300.prim_prince_test.562133096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/300.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/301.prim_prince_test.3615707104 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2688370756 ps |
| CPU time | 48.91 seconds |
| Started | Oct 14 08:21:53 PM UTC 24 |
| Finished | Oct 14 08:22:55 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615707104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 301.prim_prince_test.3615707104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/301.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/302.prim_prince_test.496811763 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2142684012 ps |
| CPU time | 40.38 seconds |
| Started | Oct 14 08:21:54 PM UTC 24 |
| Finished | Oct 14 08:22:45 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496811763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 302.prim_prince_test.496811763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/302.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/303.prim_prince_test.2360580822 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1566052355 ps |
| CPU time | 29.63 seconds |
| Started | Oct 14 08:21:55 PM UTC 24 |
| Finished | Oct 14 08:22:33 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360580822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 303.prim_prince_test.2360580822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/303.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/304.prim_prince_test.1988722254 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2522515034 ps |
| CPU time | 46.06 seconds |
| Started | Oct 14 08:21:57 PM UTC 24 |
| Finished | Oct 14 08:22:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988722254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 304.prim_prince_test.1988722254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/304.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/305.prim_prince_test.473876953 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 2437102529 ps |
| CPU time | 45.69 seconds |
| Started | Oct 14 08:21:57 PM UTC 24 |
| Finished | Oct 14 08:22:56 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473876953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 305.prim_prince_test.473876953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/305.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/306.prim_prince_test.1298697817 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 1321464766 ps |
| CPU time | 25.09 seconds |
| Started | Oct 14 08:21:57 PM UTC 24 |
| Finished | Oct 14 08:22:30 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298697817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 306.prim_prince_test.1298697817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/306.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/307.prim_prince_test.1654418381 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1930025461 ps |
| CPU time | 36.48 seconds |
| Started | Oct 14 08:21:58 PM UTC 24 |
| Finished | Oct 14 08:22:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654418381 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 307.prim_prince_test.1654418381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/307.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/308.prim_prince_test.2496862536 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1482195820 ps |
| CPU time | 27.63 seconds |
| Started | Oct 14 08:21:59 PM UTC 24 |
| Finished | Oct 14 08:22:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496862536 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 308.prim_prince_test.2496862536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/308.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/309.prim_prince_test.2994105511 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2457799221 ps |
| CPU time | 44.54 seconds |
| Started | Oct 14 08:21:59 PM UTC 24 |
| Finished | Oct 14 08:22:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994105511 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 309.prim_prince_test.2994105511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/309.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/31.prim_prince_test.3507005330 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3313469698 ps |
| CPU time | 64.01 seconds |
| Started | Oct 14 08:16:55 PM UTC 24 |
| Finished | Oct 14 08:18:16 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507005330 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 31.prim_prince_test.3507005330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/31.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/310.prim_prince_test.1052953759 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1296733816 ps |
| CPU time | 24.37 seconds |
| Started | Oct 14 08:22:01 PM UTC 24 |
| Finished | Oct 14 08:22:32 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052953759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 310.prim_prince_test.1052953759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/310.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/311.prim_prince_test.1771354441 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1891872864 ps |
| CPU time | 35.85 seconds |
| Started | Oct 14 08:22:02 PM UTC 24 |
| Finished | Oct 14 08:22:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771354441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 311.prim_prince_test.1771354441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/311.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/312.prim_prince_test.310951787 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2113712996 ps |
| CPU time | 39.95 seconds |
| Started | Oct 14 08:22:03 PM UTC 24 |
| Finished | Oct 14 08:22:53 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310951787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 312.prim_prince_test.310951787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/312.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/313.prim_prince_test.657137241 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 758029286 ps |
| CPU time | 14.7 seconds |
| Started | Oct 14 08:22:04 PM UTC 24 |
| Finished | Oct 14 08:22:23 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657137241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 313.prim_prince_test.657137241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/313.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/314.prim_prince_test.3856619648 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 1703450124 ps |
| CPU time | 31.53 seconds |
| Started | Oct 14 08:22:04 PM UTC 24 |
| Finished | Oct 14 08:22:45 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856619648 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 314.prim_prince_test.3856619648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/314.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/315.prim_prince_test.89673287 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1870065307 ps |
| CPU time | 35.34 seconds |
| Started | Oct 14 08:22:04 PM UTC 24 |
| Finished | Oct 14 08:22:49 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89673287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 315.prim_prince_test.89673287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/315.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/316.prim_prince_test.4153455612 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3377128888 ps |
| CPU time | 61.35 seconds |
| Started | Oct 14 08:22:06 PM UTC 24 |
| Finished | Oct 14 08:23:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153455612 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 316.prim_prince_test.4153455612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/316.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/317.prim_prince_test.2808694190 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 842255178 ps |
| CPU time | 15.65 seconds |
| Started | Oct 14 08:22:09 PM UTC 24 |
| Finished | Oct 14 08:22:29 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808694190 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 317.prim_prince_test.2808694190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/317.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/318.prim_prince_test.1386093266 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2799074692 ps |
| CPU time | 50.85 seconds |
| Started | Oct 14 08:22:09 PM UTC 24 |
| Finished | Oct 14 08:23:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386093266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 318.prim_prince_test.1386093266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/318.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/319.prim_prince_test.1823873279 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3163911664 ps |
| CPU time | 57.98 seconds |
| Started | Oct 14 08:22:10 PM UTC 24 |
| Finished | Oct 14 08:23:23 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823873279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 319.prim_prince_test.1823873279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/319.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/32.prim_prince_test.2035027882 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1511677427 ps |
| CPU time | 29.85 seconds |
| Started | Oct 14 08:16:58 PM UTC 24 |
| Finished | Oct 14 08:17:37 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035027882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 32.prim_prince_test.2035027882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/32.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/320.prim_prince_test.3602417048 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1428227200 ps |
| CPU time | 27.03 seconds |
| Started | Oct 14 08:22:12 PM UTC 24 |
| Finished | Oct 14 08:22:46 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602417048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 320.prim_prince_test.3602417048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/320.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/321.prim_prince_test.1843748990 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2217794488 ps |
| CPU time | 41.67 seconds |
| Started | Oct 14 08:22:13 PM UTC 24 |
| Finished | Oct 14 08:23:06 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843748990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 321.prim_prince_test.1843748990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/321.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/322.prim_prince_test.826507901 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 2105305864 ps |
| CPU time | 39.02 seconds |
| Started | Oct 14 08:22:14 PM UTC 24 |
| Finished | Oct 14 08:23:04 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826507901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 322.prim_prince_test.826507901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/322.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/323.prim_prince_test.1846790591 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1324422072 ps |
| CPU time | 24.54 seconds |
| Started | Oct 14 08:22:15 PM UTC 24 |
| Finished | Oct 14 08:22:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846790591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 323.prim_prince_test.1846790591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/323.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/324.prim_prince_test.3778747231 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2110096767 ps |
| CPU time | 38.48 seconds |
| Started | Oct 14 08:22:15 PM UTC 24 |
| Finished | Oct 14 08:23:05 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778747231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 324.prim_prince_test.3778747231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/324.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/325.prim_prince_test.3438011711 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1815733669 ps |
| CPU time | 34.18 seconds |
| Started | Oct 14 08:22:16 PM UTC 24 |
| Finished | Oct 14 08:23:00 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438011711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 325.prim_prince_test.3438011711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/325.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/326.prim_prince_test.89443422 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 926966330 ps |
| CPU time | 17.94 seconds |
| Started | Oct 14 08:22:18 PM UTC 24 |
| Finished | Oct 14 08:22:41 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89443422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 326.prim_prince_test.89443422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/326.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/327.prim_prince_test.1790161179 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3603711078 ps |
| CPU time | 66.99 seconds |
| Started | Oct 14 08:22:19 PM UTC 24 |
| Finished | Oct 14 08:23:43 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790161179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 327.prim_prince_test.1790161179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/327.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/328.prim_prince_test.3347144586 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2502548556 ps |
| CPU time | 47.05 seconds |
| Started | Oct 14 08:22:20 PM UTC 24 |
| Finished | Oct 14 08:23:19 PM UTC 24 |
| Peak memory | 154948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347144586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 328.prim_prince_test.3347144586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/328.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/329.prim_prince_test.2437148274 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 2402594925 ps |
| CPU time | 45.07 seconds |
| Started | Oct 14 08:22:20 PM UTC 24 |
| Finished | Oct 14 08:23:17 PM UTC 24 |
| Peak memory | 154856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437148274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 329.prim_prince_test.2437148274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/329.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/33.prim_prince_test.1106393459 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1750755025 ps |
| CPU time | 34.13 seconds |
| Started | Oct 14 08:17:00 PM UTC 24 |
| Finished | Oct 14 08:17:45 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106393459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 33.prim_prince_test.1106393459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/33.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/330.prim_prince_test.1247340222 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3703229656 ps |
| CPU time | 69.23 seconds |
| Started | Oct 14 08:22:20 PM UTC 24 |
| Finished | Oct 14 08:23:47 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247340222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 330.prim_prince_test.1247340222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/330.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/331.prim_prince_test.1037776287 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3285169029 ps |
| CPU time | 61.22 seconds |
| Started | Oct 14 08:22:20 PM UTC 24 |
| Finished | Oct 14 08:23:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037776287 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 331.prim_prince_test.1037776287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/331.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/332.prim_prince_test.3638984664 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3499204585 ps |
| CPU time | 65.07 seconds |
| Started | Oct 14 08:22:22 PM UTC 24 |
| Finished | Oct 14 08:23:44 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638984664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 332.prim_prince_test.3638984664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/332.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/333.prim_prince_test.1367049954 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1169475558 ps |
| CPU time | 22.06 seconds |
| Started | Oct 14 08:22:23 PM UTC 24 |
| Finished | Oct 14 08:22:52 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367049954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 333.prim_prince_test.1367049954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/333.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/334.prim_prince_test.917824846 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 2616491021 ps |
| CPU time | 47.55 seconds |
| Started | Oct 14 08:22:25 PM UTC 24 |
| Finished | Oct 14 08:23:25 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917824846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 334.prim_prince_test.917824846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/334.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/335.prim_prince_test.3552378084 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2590592515 ps |
| CPU time | 48.2 seconds |
| Started | Oct 14 08:22:27 PM UTC 24 |
| Finished | Oct 14 08:23:28 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552378084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 335.prim_prince_test.3552378084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/335.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/336.prim_prince_test.4154981194 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3559668611 ps |
| CPU time | 66.02 seconds |
| Started | Oct 14 08:22:27 PM UTC 24 |
| Finished | Oct 14 08:23:50 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154981194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 336.prim_prince_test.4154981194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/336.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/337.prim_prince_test.2719336893 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1424202606 ps |
| CPU time | 26.38 seconds |
| Started | Oct 14 08:22:28 PM UTC 24 |
| Finished | Oct 14 08:23:02 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719336893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 337.prim_prince_test.2719336893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/337.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/338.prim_prince_test.1897394710 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3004478627 ps |
| CPU time | 56.17 seconds |
| Started | Oct 14 08:22:28 PM UTC 24 |
| Finished | Oct 14 08:23:39 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897394710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 338.prim_prince_test.1897394710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/338.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/339.prim_prince_test.3171763372 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2782288771 ps |
| CPU time | 52.32 seconds |
| Started | Oct 14 08:22:28 PM UTC 24 |
| Finished | Oct 14 08:23:34 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171763372 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 339.prim_prince_test.3171763372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/339.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/34.prim_prince_test.1041525626 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3235098630 ps |
| CPU time | 62.44 seconds |
| Started | Oct 14 08:17:03 PM UTC 24 |
| Finished | Oct 14 08:18:22 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041525626 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 34.prim_prince_test.1041525626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/34.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/340.prim_prince_test.659743997 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 1848667816 ps |
| CPU time | 34.8 seconds |
| Started | Oct 14 08:22:29 PM UTC 24 |
| Finished | Oct 14 08:23:13 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659743997 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 340.prim_prince_test.659743997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/340.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/341.prim_prince_test.598231879 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2763247783 ps |
| CPU time | 50.55 seconds |
| Started | Oct 14 08:22:31 PM UTC 24 |
| Finished | Oct 14 08:23:35 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598231879 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 341.prim_prince_test.598231879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/341.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/342.prim_prince_test.2888086261 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1978401037 ps |
| CPU time | 37.12 seconds |
| Started | Oct 14 08:22:31 PM UTC 24 |
| Finished | Oct 14 08:23:17 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888086261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 342.prim_prince_test.2888086261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/342.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/343.prim_prince_test.833185031 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3276324154 ps |
| CPU time | 59.51 seconds |
| Started | Oct 14 08:22:33 PM UTC 24 |
| Finished | Oct 14 08:23:48 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833185031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 343.prim_prince_test.833185031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/343.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/344.prim_prince_test.1996695400 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2012473116 ps |
| CPU time | 37.77 seconds |
| Started | Oct 14 08:22:34 PM UTC 24 |
| Finished | Oct 14 08:23:22 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996695400 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 344.prim_prince_test.1996695400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/344.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/345.prim_prince_test.2766888385 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3584238211 ps |
| CPU time | 64.95 seconds |
| Started | Oct 14 08:22:35 PM UTC 24 |
| Finished | Oct 14 08:23:57 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766888385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 345.prim_prince_test.2766888385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/345.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/346.prim_prince_test.745627635 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2226823473 ps |
| CPU time | 40.8 seconds |
| Started | Oct 14 08:22:36 PM UTC 24 |
| Finished | Oct 14 08:23:28 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745627635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 346.prim_prince_test.745627635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/346.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/347.prim_prince_test.2138161114 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2362189339 ps |
| CPU time | 43.88 seconds |
| Started | Oct 14 08:22:37 PM UTC 24 |
| Finished | Oct 14 08:23:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138161114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 347.prim_prince_test.2138161114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/347.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/348.prim_prince_test.1816724376 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 1485048694 ps |
| CPU time | 27.2 seconds |
| Started | Oct 14 08:22:37 PM UTC 24 |
| Finished | Oct 14 08:23:12 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816724376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 348.prim_prince_test.1816724376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/348.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/349.prim_prince_test.2559096973 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1915149474 ps |
| CPU time | 35.98 seconds |
| Started | Oct 14 08:22:37 PM UTC 24 |
| Finished | Oct 14 08:23:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559096973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 349.prim_prince_test.2559096973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/349.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/35.prim_prince_test.1107443972 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2508716400 ps |
| CPU time | 47.66 seconds |
| Started | Oct 14 08:17:03 PM UTC 24 |
| Finished | Oct 14 08:18:04 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107443972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 35.prim_prince_test.1107443972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/35.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/350.prim_prince_test.3659467168 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2060931863 ps |
| CPU time | 38.82 seconds |
| Started | Oct 14 08:22:39 PM UTC 24 |
| Finished | Oct 14 08:23:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659467168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 350.prim_prince_test.3659467168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/350.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/351.prim_prince_test.2677831200 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2015691181 ps |
| CPU time | 37.85 seconds |
| Started | Oct 14 08:22:41 PM UTC 24 |
| Finished | Oct 14 08:23:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677831200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 351.prim_prince_test.2677831200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/351.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/352.prim_prince_test.407417434 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 816452526 ps |
| CPU time | 15.55 seconds |
| Started | Oct 14 08:22:42 PM UTC 24 |
| Finished | Oct 14 08:23:02 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407417434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 352.prim_prince_test.407417434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/352.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/353.prim_prince_test.4018642144 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 3059853949 ps |
| CPU time | 55.27 seconds |
| Started | Oct 14 08:22:43 PM UTC 24 |
| Finished | Oct 14 08:23:53 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018642144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 353.prim_prince_test.4018642144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/353.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/354.prim_prince_test.3005921429 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 2168449417 ps |
| CPU time | 40.29 seconds |
| Started | Oct 14 08:22:44 PM UTC 24 |
| Finished | Oct 14 08:23:35 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005921429 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 354.prim_prince_test.3005921429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/354.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/355.prim_prince_test.2985129421 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2966966063 ps |
| CPU time | 53.67 seconds |
| Started | Oct 14 08:22:45 PM UTC 24 |
| Finished | Oct 14 08:23:54 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985129421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 355.prim_prince_test.2985129421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/355.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/356.prim_prince_test.18807686 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2707641985 ps |
| CPU time | 49.27 seconds |
| Started | Oct 14 08:22:45 PM UTC 24 |
| Finished | Oct 14 08:23:48 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18807686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 356.prim_prince_test.18807686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/356.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/357.prim_prince_test.1004112523 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2389481220 ps |
| CPU time | 44.73 seconds |
| Started | Oct 14 08:22:46 PM UTC 24 |
| Finished | Oct 14 08:23:42 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004112523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 357.prim_prince_test.1004112523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/357.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/358.prim_prince_test.2530819470 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1459954924 ps |
| CPU time | 27.58 seconds |
| Started | Oct 14 08:22:46 PM UTC 24 |
| Finished | Oct 14 08:23:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530819470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 358.prim_prince_test.2530819470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/358.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/359.prim_prince_test.3778739889 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2536610536 ps |
| CPU time | 46.25 seconds |
| Started | Oct 14 08:22:47 PM UTC 24 |
| Finished | Oct 14 08:23:46 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778739889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 359.prim_prince_test.3778739889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/359.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/36.prim_prince_test.2063060851 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1966062784 ps |
| CPU time | 36.66 seconds |
| Started | Oct 14 08:17:03 PM UTC 24 |
| Finished | Oct 14 08:17:51 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063060851 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 36.prim_prince_test.2063060851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/36.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/360.prim_prince_test.4187690151 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3402562880 ps |
| CPU time | 63.3 seconds |
| Started | Oct 14 08:22:48 PM UTC 24 |
| Finished | Oct 14 08:24:07 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187690151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 360.prim_prince_test.4187690151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/360.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/361.prim_prince_test.772835301 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3630901895 ps |
| CPU time | 67.02 seconds |
| Started | Oct 14 08:22:48 PM UTC 24 |
| Finished | Oct 14 08:24:12 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772835301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 361.prim_prince_test.772835301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/361.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/362.prim_prince_test.1238871035 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 1174193529 ps |
| CPU time | 21.74 seconds |
| Started | Oct 14 08:22:48 PM UTC 24 |
| Finished | Oct 14 08:23:16 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238871035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 362.prim_prince_test.1238871035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/362.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/363.prim_prince_test.1136985240 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1513829213 ps |
| CPU time | 28.51 seconds |
| Started | Oct 14 08:22:49 PM UTC 24 |
| Finished | Oct 14 08:23:25 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136985240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 363.prim_prince_test.1136985240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/363.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/364.prim_prince_test.4224880228 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1153636548 ps |
| CPU time | 22.03 seconds |
| Started | Oct 14 08:22:50 PM UTC 24 |
| Finished | Oct 14 08:23:18 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224880228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 364.prim_prince_test.4224880228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/364.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/365.prim_prince_test.3652533804 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1165428958 ps |
| CPU time | 21.99 seconds |
| Started | Oct 14 08:22:52 PM UTC 24 |
| Finished | Oct 14 08:23:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652533804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 365.prim_prince_test.3652533804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/365.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/366.prim_prince_test.4020254420 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1161593548 ps |
| CPU time | 21.27 seconds |
| Started | Oct 14 08:22:53 PM UTC 24 |
| Finished | Oct 14 08:23:20 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020254420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 366.prim_prince_test.4020254420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/366.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/367.prim_prince_test.59944573 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1050640342 ps |
| CPU time | 19.64 seconds |
| Started | Oct 14 08:22:54 PM UTC 24 |
| Finished | Oct 14 08:23:19 PM UTC 24 |
| Peak memory | 154712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59944573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 367.prim_prince_test.59944573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/367.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/368.prim_prince_test.4144559523 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2557694427 ps |
| CPU time | 47.45 seconds |
| Started | Oct 14 08:22:54 PM UTC 24 |
| Finished | Oct 14 08:23:54 PM UTC 24 |
| Peak memory | 154816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144559523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 368.prim_prince_test.4144559523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/368.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/369.prim_prince_test.2546064595 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2350058934 ps |
| CPU time | 43.76 seconds |
| Started | Oct 14 08:22:55 PM UTC 24 |
| Finished | Oct 14 08:23:50 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546064595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 369.prim_prince_test.2546064595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/369.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/37.prim_prince_test.354823487 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2660448503 ps |
| CPU time | 51.38 seconds |
| Started | Oct 14 08:17:04 PM UTC 24 |
| Finished | Oct 14 08:18:09 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354823487 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 37.prim_prince_test.354823487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/37.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/370.prim_prince_test.152497351 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1512677887 ps |
| CPU time | 28.18 seconds |
| Started | Oct 14 08:22:55 PM UTC 24 |
| Finished | Oct 14 08:23:31 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152497351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 370.prim_prince_test.152497351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/370.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/371.prim_prince_test.4254274935 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2733637294 ps |
| CPU time | 50.89 seconds |
| Started | Oct 14 08:22:55 PM UTC 24 |
| Finished | Oct 14 08:23:59 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254274935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 371.prim_prince_test.4254274935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/371.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/372.prim_prince_test.864954010 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1030471004 ps |
| CPU time | 19.07 seconds |
| Started | Oct 14 08:22:56 PM UTC 24 |
| Finished | Oct 14 08:23:21 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864954010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 372.prim_prince_test.864954010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/372.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/373.prim_prince_test.2338944846 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 939969695 ps |
| CPU time | 17.3 seconds |
| Started | Oct 14 08:22:58 PM UTC 24 |
| Finished | Oct 14 08:23:20 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338944846 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 373.prim_prince_test.2338944846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/373.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/374.prim_prince_test.1204471471 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2225916367 ps |
| CPU time | 40.72 seconds |
| Started | Oct 14 08:22:58 PM UTC 24 |
| Finished | Oct 14 08:23:50 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204471471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 374.prim_prince_test.1204471471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/374.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/375.prim_prince_test.2166696738 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1755808298 ps |
| CPU time | 32.85 seconds |
| Started | Oct 14 08:22:58 PM UTC 24 |
| Finished | Oct 14 08:23:40 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166696738 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 375.prim_prince_test.2166696738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/375.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/376.prim_prince_test.2957108241 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2731097846 ps |
| CPU time | 50.92 seconds |
| Started | Oct 14 08:23:00 PM UTC 24 |
| Finished | Oct 14 08:24:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957108241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 376.prim_prince_test.2957108241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/376.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/377.prim_prince_test.1298265917 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2229241737 ps |
| CPU time | 40.74 seconds |
| Started | Oct 14 08:23:00 PM UTC 24 |
| Finished | Oct 14 08:23:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298265917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 377.prim_prince_test.1298265917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/377.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/378.prim_prince_test.410103823 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2260596883 ps |
| CPU time | 41.28 seconds |
| Started | Oct 14 08:23:00 PM UTC 24 |
| Finished | Oct 14 08:23:53 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410103823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 378.prim_prince_test.410103823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/378.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/379.prim_prince_test.3826065726 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3729304093 ps |
| CPU time | 67.51 seconds |
| Started | Oct 14 08:23:02 PM UTC 24 |
| Finished | Oct 14 08:24:28 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826065726 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 379.prim_prince_test.3826065726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/379.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/38.prim_prince_test.2270121323 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2891233198 ps |
| CPU time | 56.22 seconds |
| Started | Oct 14 08:17:04 PM UTC 24 |
| Finished | Oct 14 08:18:15 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270121323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 38.prim_prince_test.2270121323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/38.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/380.prim_prince_test.633986034 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2697736588 ps |
| CPU time | 50.07 seconds |
| Started | Oct 14 08:23:03 PM UTC 24 |
| Finished | Oct 14 08:24:07 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633986034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 380.prim_prince_test.633986034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/380.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/381.prim_prince_test.443995718 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1665951571 ps |
| CPU time | 30.79 seconds |
| Started | Oct 14 08:23:05 PM UTC 24 |
| Finished | Oct 14 08:23:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443995718 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 381.prim_prince_test.443995718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/381.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/382.prim_prince_test.4035527929 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2178956142 ps |
| CPU time | 40.65 seconds |
| Started | Oct 14 08:23:06 PM UTC 24 |
| Finished | Oct 14 08:23:57 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035527929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 382.prim_prince_test.4035527929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/382.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/383.prim_prince_test.2090945972 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2073912377 ps |
| CPU time | 38.96 seconds |
| Started | Oct 14 08:23:06 PM UTC 24 |
| Finished | Oct 14 08:23:55 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090945972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 383.prim_prince_test.2090945972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/383.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/384.prim_prince_test.3309846694 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3735834380 ps |
| CPU time | 69.61 seconds |
| Started | Oct 14 08:23:06 PM UTC 24 |
| Finished | Oct 14 08:24:33 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309846694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 384.prim_prince_test.3309846694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/384.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/385.prim_prince_test.2076937303 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2256168147 ps |
| CPU time | 40.8 seconds |
| Started | Oct 14 08:23:07 PM UTC 24 |
| Finished | Oct 14 08:23:59 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076937303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 385.prim_prince_test.2076937303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/385.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/386.prim_prince_test.1915407258 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2267727000 ps |
| CPU time | 42.22 seconds |
| Started | Oct 14 08:23:09 PM UTC 24 |
| Finished | Oct 14 08:24:03 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915407258 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 386.prim_prince_test.1915407258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/386.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/387.prim_prince_test.925952542 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3535347977 ps |
| CPU time | 63.84 seconds |
| Started | Oct 14 08:23:11 PM UTC 24 |
| Finished | Oct 14 08:24:32 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925952542 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 387.prim_prince_test.925952542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/387.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/388.prim_prince_test.2226647655 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1551715344 ps |
| CPU time | 28.95 seconds |
| Started | Oct 14 08:23:13 PM UTC 24 |
| Finished | Oct 14 08:23:50 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226647655 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 388.prim_prince_test.2226647655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/388.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/389.prim_prince_test.190068895 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3362877445 ps |
| CPU time | 61.2 seconds |
| Started | Oct 14 08:23:14 PM UTC 24 |
| Finished | Oct 14 08:24:32 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190068895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 389.prim_prince_test.190068895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/389.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/39.prim_prince_test.2100912606 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 861829512 ps |
| CPU time | 16.88 seconds |
| Started | Oct 14 08:17:08 PM UTC 24 |
| Finished | Oct 14 08:17:30 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100912606 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 39.prim_prince_test.2100912606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/39.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/390.prim_prince_test.755629042 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2364033312 ps |
| CPU time | 42.68 seconds |
| Started | Oct 14 08:23:14 PM UTC 24 |
| Finished | Oct 14 08:24:09 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755629042 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 390.prim_prince_test.755629042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/390.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/391.prim_prince_test.1474258264 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2331612845 ps |
| CPU time | 43.75 seconds |
| Started | Oct 14 08:23:17 PM UTC 24 |
| Finished | Oct 14 08:24:13 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474258264 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 391.prim_prince_test.1474258264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/391.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/392.prim_prince_test.2788546561 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3706403784 ps |
| CPU time | 68.84 seconds |
| Started | Oct 14 08:23:18 PM UTC 24 |
| Finished | Oct 14 08:24:46 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788546561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 392.prim_prince_test.2788546561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/392.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/393.prim_prince_test.2443682826 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1728179617 ps |
| CPU time | 31.49 seconds |
| Started | Oct 14 08:23:18 PM UTC 24 |
| Finished | Oct 14 08:24:00 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443682826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 393.prim_prince_test.2443682826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/393.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/394.prim_prince_test.1775462906 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2711350490 ps |
| CPU time | 50.85 seconds |
| Started | Oct 14 08:23:20 PM UTC 24 |
| Finished | Oct 14 08:24:24 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775462906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 394.prim_prince_test.1775462906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/394.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/395.prim_prince_test.3615999205 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 3355791645 ps |
| CPU time | 61 seconds |
| Started | Oct 14 08:23:20 PM UTC 24 |
| Finished | Oct 14 08:24:38 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615999205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 395.prim_prince_test.3615999205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/395.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/396.prim_prince_test.4289087902 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1554318364 ps |
| CPU time | 28.51 seconds |
| Started | Oct 14 08:23:21 PM UTC 24 |
| Finished | Oct 14 08:23:58 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289087902 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 396.prim_prince_test.4289087902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/396.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/397.prim_prince_test.1574510991 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2594515521 ps |
| CPU time | 48.21 seconds |
| Started | Oct 14 08:23:21 PM UTC 24 |
| Finished | Oct 14 08:24:22 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574510991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 397.prim_prince_test.1574510991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/397.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/398.prim_prince_test.2635287819 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1090063702 ps |
| CPU time | 20.09 seconds |
| Started | Oct 14 08:23:21 PM UTC 24 |
| Finished | Oct 14 08:23:48 PM UTC 24 |
| Peak memory | 154940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635287819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 398.prim_prince_test.2635287819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/398.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/399.prim_prince_test.182512922 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 908863799 ps |
| CPU time | 17.36 seconds |
| Started | Oct 14 08:23:21 PM UTC 24 |
| Finished | Oct 14 08:23:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182512922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 399.prim_prince_test.182512922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/399.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/4.prim_prince_test.1850529373 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 3488239278 ps |
| CPU time | 66.56 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:18:03 PM UTC 24 |
| Peak memory | 153480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850529373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.prim_prince_test.1850529373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/4.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/40.prim_prince_test.2203108285 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 930381795 ps |
| CPU time | 18.43 seconds |
| Started | Oct 14 08:17:08 PM UTC 24 |
| Finished | Oct 14 08:17:32 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203108285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 40.prim_prince_test.2203108285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/40.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/400.prim_prince_test.3665720033 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1087364803 ps |
| CPU time | 20.41 seconds |
| Started | Oct 14 08:23:23 PM UTC 24 |
| Finished | Oct 14 08:23:49 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665720033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 400.prim_prince_test.3665720033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/400.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/401.prim_prince_test.432261548 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2181439785 ps |
| CPU time | 40.86 seconds |
| Started | Oct 14 08:23:23 PM UTC 24 |
| Finished | Oct 14 08:24:14 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432261548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 401.prim_prince_test.432261548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/401.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/402.prim_prince_test.2708565768 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2819833245 ps |
| CPU time | 52.24 seconds |
| Started | Oct 14 08:23:23 PM UTC 24 |
| Finished | Oct 14 08:24:29 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708565768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 402.prim_prince_test.2708565768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/402.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/403.prim_prince_test.306376403 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2052115193 ps |
| CPU time | 38.42 seconds |
| Started | Oct 14 08:23:24 PM UTC 24 |
| Finished | Oct 14 08:24:13 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306376403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 403.prim_prince_test.306376403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/403.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/404.prim_prince_test.3357159498 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2268044782 ps |
| CPU time | 42.29 seconds |
| Started | Oct 14 08:23:24 PM UTC 24 |
| Finished | Oct 14 08:24:18 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357159498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 404.prim_prince_test.3357159498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/404.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/405.prim_prince_test.3156449145 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1531006475 ps |
| CPU time | 27.99 seconds |
| Started | Oct 14 08:23:25 PM UTC 24 |
| Finished | Oct 14 08:24:01 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156449145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 405.prim_prince_test.3156449145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/405.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/406.prim_prince_test.2787717335 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1852763299 ps |
| CPU time | 34.86 seconds |
| Started | Oct 14 08:23:26 PM UTC 24 |
| Finished | Oct 14 08:24:10 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787717335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 406.prim_prince_test.2787717335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/406.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/407.prim_prince_test.223362451 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1318698991 ps |
| CPU time | 24.94 seconds |
| Started | Oct 14 08:23:26 PM UTC 24 |
| Finished | Oct 14 08:23:58 PM UTC 24 |
| Peak memory | 156336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223362451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 407.prim_prince_test.223362451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/407.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/408.prim_prince_test.1526145629 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3380659529 ps |
| CPU time | 61.91 seconds |
| Started | Oct 14 08:23:29 PM UTC 24 |
| Finished | Oct 14 08:24:47 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526145629 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 408.prim_prince_test.1526145629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/408.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/409.prim_prince_test.3969178885 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3016983308 ps |
| CPU time | 54.78 seconds |
| Started | Oct 14 08:23:29 PM UTC 24 |
| Finished | Oct 14 08:24:38 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969178885 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 409.prim_prince_test.3969178885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/409.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/41.prim_prince_test.2572278468 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3174286821 ps |
| CPU time | 59.75 seconds |
| Started | Oct 14 08:17:09 PM UTC 24 |
| Finished | Oct 14 08:18:25 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572278468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 41.prim_prince_test.2572278468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/41.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/410.prim_prince_test.1148758628 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2947665993 ps |
| CPU time | 53.63 seconds |
| Started | Oct 14 08:23:29 PM UTC 24 |
| Finished | Oct 14 08:24:37 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148758628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 410.prim_prince_test.1148758628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/410.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/411.prim_prince_test.109168814 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3607793324 ps |
| CPU time | 66.99 seconds |
| Started | Oct 14 08:23:30 PM UTC 24 |
| Finished | Oct 14 08:24:54 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109168814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 411.prim_prince_test.109168814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/411.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/412.prim_prince_test.1000718281 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3333719192 ps |
| CPU time | 61.96 seconds |
| Started | Oct 14 08:23:32 PM UTC 24 |
| Finished | Oct 14 08:24:50 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000718281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 412.prim_prince_test.1000718281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/412.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/413.prim_prince_test.462302130 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2956862653 ps |
| CPU time | 53.88 seconds |
| Started | Oct 14 08:23:32 PM UTC 24 |
| Finished | Oct 14 08:24:41 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462302130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 413.prim_prince_test.462302130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/413.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/414.prim_prince_test.3056463380 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2834663982 ps |
| CPU time | 51.45 seconds |
| Started | Oct 14 08:23:34 PM UTC 24 |
| Finished | Oct 14 08:24:40 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056463380 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 414.prim_prince_test.3056463380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/414.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/415.prim_prince_test.1027040265 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3648755749 ps |
| CPU time | 67.76 seconds |
| Started | Oct 14 08:23:36 PM UTC 24 |
| Finished | Oct 14 08:25:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027040265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 415.prim_prince_test.1027040265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/415.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/416.prim_prince_test.2233114271 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3142568985 ps |
| CPU time | 58.37 seconds |
| Started | Oct 14 08:23:36 PM UTC 24 |
| Finished | Oct 14 08:24:50 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233114271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 416.prim_prince_test.2233114271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/416.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/417.prim_prince_test.3788393269 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1074294445 ps |
| CPU time | 20.07 seconds |
| Started | Oct 14 08:23:36 PM UTC 24 |
| Finished | Oct 14 08:24:02 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788393269 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 417.prim_prince_test.3788393269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/417.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/418.prim_prince_test.1648635863 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2434484617 ps |
| CPU time | 44.65 seconds |
| Started | Oct 14 08:23:38 PM UTC 24 |
| Finished | Oct 14 08:24:35 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648635863 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 418.prim_prince_test.1648635863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/418.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/419.prim_prince_test.3888162238 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2961593683 ps |
| CPU time | 54.49 seconds |
| Started | Oct 14 08:23:40 PM UTC 24 |
| Finished | Oct 14 08:24:49 PM UTC 24 |
| Peak memory | 154704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888162238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 419.prim_prince_test.3888162238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/419.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/42.prim_prince_test.2827808283 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1601627472 ps |
| CPU time | 30.52 seconds |
| Started | Oct 14 08:17:10 PM UTC 24 |
| Finished | Oct 14 08:17:50 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827808283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 42.prim_prince_test.2827808283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/42.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/420.prim_prince_test.3018584494 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2073554733 ps |
| CPU time | 38.83 seconds |
| Started | Oct 14 08:23:40 PM UTC 24 |
| Finished | Oct 14 08:24:29 PM UTC 24 |
| Peak memory | 154660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018584494 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 420.prim_prince_test.3018584494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/420.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/421.prim_prince_test.1187216506 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1226407038 ps |
| CPU time | 22.4 seconds |
| Started | Oct 14 08:23:42 PM UTC 24 |
| Finished | Oct 14 08:24:11 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187216506 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 421.prim_prince_test.1187216506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/421.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/422.prim_prince_test.674717694 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1923843413 ps |
| CPU time | 36.11 seconds |
| Started | Oct 14 08:23:43 PM UTC 24 |
| Finished | Oct 14 08:24:29 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674717694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 422.prim_prince_test.674717694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/422.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/423.prim_prince_test.2414673643 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 1805451422 ps |
| CPU time | 34.04 seconds |
| Started | Oct 14 08:23:45 PM UTC 24 |
| Finished | Oct 14 08:24:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414673643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 423.prim_prince_test.2414673643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/423.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/424.prim_prince_test.832915172 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3012814930 ps |
| CPU time | 55.57 seconds |
| Started | Oct 14 08:23:45 PM UTC 24 |
| Finished | Oct 14 08:24:55 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832915172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 424.prim_prince_test.832915172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/424.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/425.prim_prince_test.1989093367 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 1071370848 ps |
| CPU time | 20.47 seconds |
| Started | Oct 14 08:23:46 PM UTC 24 |
| Finished | Oct 14 08:24:12 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989093367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 425.prim_prince_test.1989093367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/425.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/426.prim_prince_test.1816452642 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 3098086462 ps |
| CPU time | 57.7 seconds |
| Started | Oct 14 08:23:46 PM UTC 24 |
| Finished | Oct 14 08:24:59 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816452642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 426.prim_prince_test.1816452642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/426.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/427.prim_prince_test.1920114996 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3492683610 ps |
| CPU time | 63.76 seconds |
| Started | Oct 14 08:23:48 PM UTC 24 |
| Finished | Oct 14 08:25:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920114996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 427.prim_prince_test.1920114996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/427.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/428.prim_prince_test.2987511014 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2756520114 ps |
| CPU time | 50.08 seconds |
| Started | Oct 14 08:23:48 PM UTC 24 |
| Finished | Oct 14 08:24:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987511014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 428.prim_prince_test.2987511014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/428.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/429.prim_prince_test.2835727036 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1639387166 ps |
| CPU time | 30.19 seconds |
| Started | Oct 14 08:23:50 PM UTC 24 |
| Finished | Oct 14 08:24:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835727036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 429.prim_prince_test.2835727036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/429.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/43.prim_prince_test.4100858224 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3012144445 ps |
| CPU time | 56.18 seconds |
| Started | Oct 14 08:17:12 PM UTC 24 |
| Finished | Oct 14 08:18:24 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100858224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 43.prim_prince_test.4100858224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/43.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/430.prim_prince_test.3887927191 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 1361268809 ps |
| CPU time | 25.76 seconds |
| Started | Oct 14 08:23:50 PM UTC 24 |
| Finished | Oct 14 08:24:23 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887927191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 430.prim_prince_test.3887927191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/430.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/431.prim_prince_test.577237834 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3063835352 ps |
| CPU time | 56.45 seconds |
| Started | Oct 14 08:23:50 PM UTC 24 |
| Finished | Oct 14 08:25:01 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577237834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 431.prim_prince_test.577237834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/431.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/432.prim_prince_test.1742302623 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2606487506 ps |
| CPU time | 47.91 seconds |
| Started | Oct 14 08:23:51 PM UTC 24 |
| Finished | Oct 14 08:24:52 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742302623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 432.prim_prince_test.1742302623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/432.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/433.prim_prince_test.2734146291 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2244884395 ps |
| CPU time | 42.13 seconds |
| Started | Oct 14 08:23:51 PM UTC 24 |
| Finished | Oct 14 08:24:45 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734146291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 433.prim_prince_test.2734146291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/433.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/434.prim_prince_test.4172271509 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3435746035 ps |
| CPU time | 62.25 seconds |
| Started | Oct 14 08:23:51 PM UTC 24 |
| Finished | Oct 14 08:25:10 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172271509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 434.prim_prince_test.4172271509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/434.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/435.prim_prince_test.3013253709 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 829434209 ps |
| CPU time | 15.51 seconds |
| Started | Oct 14 08:23:51 PM UTC 24 |
| Finished | Oct 14 08:24:12 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013253709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 435.prim_prince_test.3013253709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/435.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/436.prim_prince_test.1583966328 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3417445722 ps |
| CPU time | 62.89 seconds |
| Started | Oct 14 08:23:53 PM UTC 24 |
| Finished | Oct 14 08:25:12 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583966328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 436.prim_prince_test.1583966328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/436.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/437.prim_prince_test.1091150218 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2878790979 ps |
| CPU time | 53.75 seconds |
| Started | Oct 14 08:23:54 PM UTC 24 |
| Finished | Oct 14 08:25:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091150218 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 437.prim_prince_test.1091150218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/437.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/438.prim_prince_test.1424595502 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 1255022492 ps |
| CPU time | 23.17 seconds |
| Started | Oct 14 08:23:54 PM UTC 24 |
| Finished | Oct 14 08:24:24 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424595502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 438.prim_prince_test.1424595502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/438.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/439.prim_prince_test.1401919592 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1078298721 ps |
| CPU time | 20.11 seconds |
| Started | Oct 14 08:23:55 PM UTC 24 |
| Finished | Oct 14 08:24:21 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401919592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 439.prim_prince_test.1401919592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/439.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/44.prim_prince_test.576541119 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2178221874 ps |
| CPU time | 40.97 seconds |
| Started | Oct 14 08:17:14 PM UTC 24 |
| Finished | Oct 14 08:18:07 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576541119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 44.prim_prince_test.576541119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/44.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/440.prim_prince_test.1821459964 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 3513205164 ps |
| CPU time | 63.83 seconds |
| Started | Oct 14 08:23:55 PM UTC 24 |
| Finished | Oct 14 08:25:16 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821459964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 440.prim_prince_test.1821459964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/440.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/441.prim_prince_test.2264422466 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1318061575 ps |
| CPU time | 24.91 seconds |
| Started | Oct 14 08:23:56 PM UTC 24 |
| Finished | Oct 14 08:24:28 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264422466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 441.prim_prince_test.2264422466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/441.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/442.prim_prince_test.3171616732 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1618276295 ps |
| CPU time | 30.49 seconds |
| Started | Oct 14 08:23:59 PM UTC 24 |
| Finished | Oct 14 08:24:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171616732 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 442.prim_prince_test.3171616732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/442.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/443.prim_prince_test.3378147261 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2105809365 ps |
| CPU time | 39.41 seconds |
| Started | Oct 14 08:23:59 PM UTC 24 |
| Finished | Oct 14 08:24:49 PM UTC 24 |
| Peak memory | 154864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378147261 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 443.prim_prince_test.3378147261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/443.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/444.prim_prince_test.3251678203 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1639894499 ps |
| CPU time | 30.82 seconds |
| Started | Oct 14 08:23:59 PM UTC 24 |
| Finished | Oct 14 08:24:38 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251678203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 444.prim_prince_test.3251678203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/444.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/445.prim_prince_test.3541436292 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2061571373 ps |
| CPU time | 37.68 seconds |
| Started | Oct 14 08:23:59 PM UTC 24 |
| Finished | Oct 14 08:24:47 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541436292 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 445.prim_prince_test.3541436292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/445.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/446.prim_prince_test.2922150395 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1301076082 ps |
| CPU time | 24.5 seconds |
| Started | Oct 14 08:24:00 PM UTC 24 |
| Finished | Oct 14 08:24:32 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922150395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 446.prim_prince_test.2922150395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/446.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/447.prim_prince_test.1532180432 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 1925713283 ps |
| CPU time | 35.54 seconds |
| Started | Oct 14 08:24:00 PM UTC 24 |
| Finished | Oct 14 08:24:46 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532180432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 447.prim_prince_test.1532180432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/447.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/448.prim_prince_test.3046934773 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2137234505 ps |
| CPU time | 38.87 seconds |
| Started | Oct 14 08:24:00 PM UTC 24 |
| Finished | Oct 14 08:24:50 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046934773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 448.prim_prince_test.3046934773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/448.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/449.prim_prince_test.3105031352 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2328168160 ps |
| CPU time | 43.37 seconds |
| Started | Oct 14 08:24:02 PM UTC 24 |
| Finished | Oct 14 08:24:56 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105031352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 449.prim_prince_test.3105031352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/449.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/45.prim_prince_test.3409369914 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 887149483 ps |
| CPU time | 17.14 seconds |
| Started | Oct 14 08:17:14 PM UTC 24 |
| Finished | Oct 14 08:17:37 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409369914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 45.prim_prince_test.3409369914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/45.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/450.prim_prince_test.2899228103 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1699654131 ps |
| CPU time | 31.38 seconds |
| Started | Oct 14 08:24:03 PM UTC 24 |
| Finished | Oct 14 08:24:43 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899228103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 450.prim_prince_test.2899228103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/450.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/451.prim_prince_test.1666308605 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 3544435322 ps |
| CPU time | 64.72 seconds |
| Started | Oct 14 08:24:04 PM UTC 24 |
| Finished | Oct 14 08:25:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666308605 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 451.prim_prince_test.1666308605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/451.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/452.prim_prince_test.3916623939 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1243758023 ps |
| CPU time | 23.66 seconds |
| Started | Oct 14 08:24:05 PM UTC 24 |
| Finished | Oct 14 08:24:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916623939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 452.prim_prince_test.3916623939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/452.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/453.prim_prince_test.1118922112 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2596551539 ps |
| CPU time | 47.83 seconds |
| Started | Oct 14 08:24:07 PM UTC 24 |
| Finished | Oct 14 08:25:08 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118922112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 453.prim_prince_test.1118922112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/453.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/454.prim_prince_test.1502226200 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3449799526 ps |
| CPU time | 61.62 seconds |
| Started | Oct 14 08:24:08 PM UTC 24 |
| Finished | Oct 14 08:25:27 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502226200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 454.prim_prince_test.1502226200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/454.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/455.prim_prince_test.3038024599 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3637228620 ps |
| CPU time | 64.56 seconds |
| Started | Oct 14 08:24:10 PM UTC 24 |
| Finished | Oct 14 08:25:32 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038024599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 455.prim_prince_test.3038024599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/455.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/456.prim_prince_test.1630051856 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1740667165 ps |
| CPU time | 32.13 seconds |
| Started | Oct 14 08:24:12 PM UTC 24 |
| Finished | Oct 14 08:24:53 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630051856 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 456.prim_prince_test.1630051856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/456.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/457.prim_prince_test.1954520982 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2204258132 ps |
| CPU time | 40.47 seconds |
| Started | Oct 14 08:24:12 PM UTC 24 |
| Finished | Oct 14 08:25:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954520982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 457.prim_prince_test.1954520982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/457.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/458.prim_prince_test.3013446663 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1802402898 ps |
| CPU time | 33.56 seconds |
| Started | Oct 14 08:24:13 PM UTC 24 |
| Finished | Oct 14 08:24:56 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013446663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 458.prim_prince_test.3013446663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/458.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/459.prim_prince_test.2235750131 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1768904147 ps |
| CPU time | 32.4 seconds |
| Started | Oct 14 08:24:13 PM UTC 24 |
| Finished | Oct 14 08:24:55 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235750131 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 459.prim_prince_test.2235750131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/459.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/46.prim_prince_test.781666662 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1086252612 ps |
| CPU time | 21.28 seconds |
| Started | Oct 14 08:17:16 PM UTC 24 |
| Finished | Oct 14 08:17:44 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781666662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 46.prim_prince_test.781666662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/46.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/460.prim_prince_test.1393224514 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 886763829 ps |
| CPU time | 16.7 seconds |
| Started | Oct 14 08:24:14 PM UTC 24 |
| Finished | Oct 14 08:24:35 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393224514 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 460.prim_prince_test.1393224514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/460.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/461.prim_prince_test.994714346 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3588878951 ps |
| CPU time | 68.07 seconds |
| Started | Oct 14 08:24:14 PM UTC 24 |
| Finished | Oct 14 08:25:40 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994714346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 461.prim_prince_test.994714346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/461.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/462.prim_prince_test.2003640301 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2365964100 ps |
| CPU time | 43.27 seconds |
| Started | Oct 14 08:24:14 PM UTC 24 |
| Finished | Oct 14 08:25:09 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003640301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 462.prim_prince_test.2003640301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/462.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/463.prim_prince_test.3292999750 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2412081700 ps |
| CPU time | 44.5 seconds |
| Started | Oct 14 08:24:15 PM UTC 24 |
| Finished | Oct 14 08:25:11 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292999750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 463.prim_prince_test.3292999750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/463.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/464.prim_prince_test.1992977197 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3005524419 ps |
| CPU time | 53.46 seconds |
| Started | Oct 14 08:24:18 PM UTC 24 |
| Finished | Oct 14 08:25:26 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992977197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 464.prim_prince_test.1992977197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/464.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/465.prim_prince_test.2302613102 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1986119067 ps |
| CPU time | 37.02 seconds |
| Started | Oct 14 08:24:22 PM UTC 24 |
| Finished | Oct 14 08:25:09 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302613102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 465.prim_prince_test.2302613102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/465.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/466.prim_prince_test.4122533865 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2404557805 ps |
| CPU time | 44.3 seconds |
| Started | Oct 14 08:24:23 PM UTC 24 |
| Finished | Oct 14 08:25:20 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122533865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 466.prim_prince_test.4122533865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/466.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/467.prim_prince_test.941337205 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1927562719 ps |
| CPU time | 35.94 seconds |
| Started | Oct 14 08:24:23 PM UTC 24 |
| Finished | Oct 14 08:25:09 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941337205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 467.prim_prince_test.941337205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/467.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/468.prim_prince_test.117325955 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 3458640750 ps |
| CPU time | 62.21 seconds |
| Started | Oct 14 08:24:25 PM UTC 24 |
| Finished | Oct 14 08:25:45 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117325955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 468.prim_prince_test.117325955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/468.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/469.prim_prince_test.3431670247 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2770146994 ps |
| CPU time | 51.24 seconds |
| Started | Oct 14 08:24:25 PM UTC 24 |
| Finished | Oct 14 08:25:30 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431670247 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 469.prim_prince_test.3431670247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/469.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/47.prim_prince_test.749005913 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1676270845 ps |
| CPU time | 32.27 seconds |
| Started | Oct 14 08:17:19 PM UTC 24 |
| Finished | Oct 14 08:18:01 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749005913 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.prim_prince_test.749005913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/47.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/470.prim_prince_test.2415777370 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2556548431 ps |
| CPU time | 47.26 seconds |
| Started | Oct 14 08:24:29 PM UTC 24 |
| Finished | Oct 14 08:25:30 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415777370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 470.prim_prince_test.2415777370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/470.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/471.prim_prince_test.26903147 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 1868855301 ps |
| CPU time | 34.43 seconds |
| Started | Oct 14 08:24:30 PM UTC 24 |
| Finished | Oct 14 08:25:13 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26903147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 471.prim_prince_test.26903147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/471.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/472.prim_prince_test.3289975377 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 930337933 ps |
| CPU time | 17.56 seconds |
| Started | Oct 14 08:24:30 PM UTC 24 |
| Finished | Oct 14 08:24:53 PM UTC 24 |
| Peak memory | 154904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289975377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 472.prim_prince_test.3289975377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/472.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/473.prim_prince_test.3021868925 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2599434219 ps |
| CPU time | 48.31 seconds |
| Started | Oct 14 08:24:30 PM UTC 24 |
| Finished | Oct 14 08:25:31 PM UTC 24 |
| Peak memory | 154960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021868925 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 473.prim_prince_test.3021868925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/473.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/474.prim_prince_test.1136041667 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 872871657 ps |
| CPU time | 16.5 seconds |
| Started | Oct 14 08:24:30 PM UTC 24 |
| Finished | Oct 14 08:24:51 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136041667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 474.prim_prince_test.1136041667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/474.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/475.prim_prince_test.2105109870 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1988395615 ps |
| CPU time | 35.84 seconds |
| Started | Oct 14 08:24:31 PM UTC 24 |
| Finished | Oct 14 08:25:17 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105109870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 475.prim_prince_test.2105109870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/475.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/476.prim_prince_test.4167423781 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2149523098 ps |
| CPU time | 39.4 seconds |
| Started | Oct 14 08:24:31 PM UTC 24 |
| Finished | Oct 14 08:25:21 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167423781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 476.prim_prince_test.4167423781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/476.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/477.prim_prince_test.3792756324 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 765478690 ps |
| CPU time | 14.56 seconds |
| Started | Oct 14 08:24:32 PM UTC 24 |
| Finished | Oct 14 08:24:52 PM UTC 24 |
| Peak memory | 154732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792756324 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 477.prim_prince_test.3792756324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/477.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/478.prim_prince_test.4252465011 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 1873484759 ps |
| CPU time | 34.44 seconds |
| Started | Oct 14 08:24:32 PM UTC 24 |
| Finished | Oct 14 08:25:16 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252465011 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 478.prim_prince_test.4252465011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/478.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/479.prim_prince_test.3000447007 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3546173322 ps |
| CPU time | 69.7 seconds |
| Started | Oct 14 08:24:33 PM UTC 24 |
| Finished | Oct 14 08:26:03 PM UTC 24 |
| Peak memory | 156916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000447007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 479.prim_prince_test.3000447007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/479.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/48.prim_prince_test.2509517357 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3321488330 ps |
| CPU time | 63.4 seconds |
| Started | Oct 14 08:17:20 PM UTC 24 |
| Finished | Oct 14 08:18:41 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509517357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 48.prim_prince_test.2509517357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/48.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/480.prim_prince_test.329527415 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 2834193905 ps |
| CPU time | 49.51 seconds |
| Started | Oct 14 08:24:35 PM UTC 24 |
| Finished | Oct 14 08:25:39 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329527415 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 480.prim_prince_test.329527415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/480.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/481.prim_prince_test.4184332366 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 891975853 ps |
| CPU time | 16.83 seconds |
| Started | Oct 14 08:24:36 PM UTC 24 |
| Finished | Oct 14 08:24:58 PM UTC 24 |
| Peak memory | 154700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184332366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 481.prim_prince_test.4184332366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/481.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/482.prim_prince_test.867081922 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2470426240 ps |
| CPU time | 43.47 seconds |
| Started | Oct 14 08:24:36 PM UTC 24 |
| Finished | Oct 14 08:25:32 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867081922 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 482.prim_prince_test.867081922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/482.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/483.prim_prince_test.2551315707 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 3240635700 ps |
| CPU time | 64.44 seconds |
| Started | Oct 14 08:24:36 PM UTC 24 |
| Finished | Oct 14 08:25:58 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551315707 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 483.prim_prince_test.2551315707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/483.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/484.prim_prince_test.3343442059 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3277963361 ps |
| CPU time | 64.39 seconds |
| Started | Oct 14 08:24:39 PM UTC 24 |
| Finished | Oct 14 08:26:01 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343442059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 484.prim_prince_test.3343442059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/484.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/485.prim_prince_test.3656093500 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 1590928380 ps |
| CPU time | 28.6 seconds |
| Started | Oct 14 08:24:39 PM UTC 24 |
| Finished | Oct 14 08:25:15 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656093500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 485.prim_prince_test.3656093500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/485.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/486.prim_prince_test.467083556 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1321755251 ps |
| CPU time | 24.31 seconds |
| Started | Oct 14 08:24:39 PM UTC 24 |
| Finished | Oct 14 08:25:10 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467083556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 486.prim_prince_test.467083556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/486.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/487.prim_prince_test.2238099254 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1948221235 ps |
| CPU time | 34.48 seconds |
| Started | Oct 14 08:24:39 PM UTC 24 |
| Finished | Oct 14 08:25:23 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238099254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 487.prim_prince_test.2238099254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/487.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/488.prim_prince_test.2874538952 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1956072536 ps |
| CPU time | 36.69 seconds |
| Started | Oct 14 08:24:40 PM UTC 24 |
| Finished | Oct 14 08:25:26 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874538952 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 488.prim_prince_test.2874538952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/488.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/489.prim_prince_test.3479688990 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 974147906 ps |
| CPU time | 18.27 seconds |
| Started | Oct 14 08:24:41 PM UTC 24 |
| Finished | Oct 14 08:25:05 PM UTC 24 |
| Peak memory | 154736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479688990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 489.prim_prince_test.3479688990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/489.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/49.prim_prince_test.1781757052 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 2240865068 ps |
| CPU time | 41.97 seconds |
| Started | Oct 14 08:17:24 PM UTC 24 |
| Finished | Oct 14 08:18:17 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781757052 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 49.prim_prince_test.1781757052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/49.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/490.prim_prince_test.2656114417 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3398125171 ps |
| CPU time | 60.25 seconds |
| Started | Oct 14 08:24:42 PM UTC 24 |
| Finished | Oct 14 08:26:01 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656114417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 490.prim_prince_test.2656114417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/490.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/491.prim_prince_test.980546684 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 844147597 ps |
| CPU time | 15.88 seconds |
| Started | Oct 14 08:24:44 PM UTC 24 |
| Finished | Oct 14 08:25:04 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980546684 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 491.prim_prince_test.980546684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/491.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/492.prim_prince_test.7402128 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2325331169 ps |
| CPU time | 40.36 seconds |
| Started | Oct 14 08:24:46 PM UTC 24 |
| Finished | Oct 14 08:25:38 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7402128 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 492.prim_prince_test.7402128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/492.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/493.prim_prince_test.1659620241 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 3233287100 ps |
| CPU time | 58.55 seconds |
| Started | Oct 14 08:24:47 PM UTC 24 |
| Finished | Oct 14 08:26:04 PM UTC 24 |
| Peak memory | 155040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659620241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 493.prim_prince_test.1659620241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/493.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/494.prim_prince_test.3515306775 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1520773136 ps |
| CPU time | 28.33 seconds |
| Started | Oct 14 08:24:47 PM UTC 24 |
| Finished | Oct 14 08:25:23 PM UTC 24 |
| Peak memory | 156332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515306775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 494.prim_prince_test.3515306775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/494.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/495.prim_prince_test.1643800405 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1786869871 ps |
| CPU time | 33.9 seconds |
| Started | Oct 14 08:24:48 PM UTC 24 |
| Finished | Oct 14 08:25:32 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643800405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 495.prim_prince_test.1643800405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/495.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/496.prim_prince_test.916741500 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1071497443 ps |
| CPU time | 19.31 seconds |
| Started | Oct 14 08:24:48 PM UTC 24 |
| Finished | Oct 14 08:25:13 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916741500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 496.prim_prince_test.916741500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/496.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/497.prim_prince_test.2340779224 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 1643188691 ps |
| CPU time | 28.83 seconds |
| Started | Oct 14 08:24:50 PM UTC 24 |
| Finished | Oct 14 08:25:27 PM UTC 24 |
| Peak memory | 154776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340779224 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 497.prim_prince_test.2340779224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/497.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/498.prim_prince_test.3533998045 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 3543665518 ps |
| CPU time | 63.57 seconds |
| Started | Oct 14 08:24:50 PM UTC 24 |
| Finished | Oct 14 08:26:14 PM UTC 24 |
| Peak memory | 154912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533998045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 498.prim_prince_test.3533998045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/498.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/499.prim_prince_test.730753641 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1526495313 ps |
| CPU time | 28.2 seconds |
| Started | Oct 14 08:24:51 PM UTC 24 |
| Finished | Oct 14 08:25:28 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730753641 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 499.prim_prince_test.730753641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/499.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/5.prim_prince_test.2168672554 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2208027600 ps |
| CPU time | 44.36 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:35 PM UTC 24 |
| Peak memory | 153220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168672554 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 5.prim_prince_test.2168672554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/5.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/50.prim_prince_test.2713863058 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2532801426 ps |
| CPU time | 47.81 seconds |
| Started | Oct 14 08:17:25 PM UTC 24 |
| Finished | Oct 14 08:18:26 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713863058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 50.prim_prince_test.2713863058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/50.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/51.prim_prince_test.534258822 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1328555180 ps |
| CPU time | 25.9 seconds |
| Started | Oct 14 08:17:27 PM UTC 24 |
| Finished | Oct 14 08:18:00 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534258822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 51.prim_prince_test.534258822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/51.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/52.prim_prince_test.4039143397 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 848960835 ps |
| CPU time | 16.67 seconds |
| Started | Oct 14 08:17:31 PM UTC 24 |
| Finished | Oct 14 08:17:52 PM UTC 24 |
| Peak memory | 154880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039143397 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 52.prim_prince_test.4039143397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/52.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/53.prim_prince_test.1370112013 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2340772060 ps |
| CPU time | 43.88 seconds |
| Started | Oct 14 08:17:31 PM UTC 24 |
| Finished | Oct 14 08:18:27 PM UTC 24 |
| Peak memory | 154964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370112013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 53.prim_prince_test.1370112013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/53.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/54.prim_prince_test.4067691457 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1317842560 ps |
| CPU time | 25.51 seconds |
| Started | Oct 14 08:17:33 PM UTC 24 |
| Finished | Oct 14 08:18:06 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067691457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 54.prim_prince_test.4067691457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/54.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/55.prim_prince_test.96148888 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 766919370 ps |
| CPU time | 15.17 seconds |
| Started | Oct 14 08:17:33 PM UTC 24 |
| Finished | Oct 14 08:17:53 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96148888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 55.prim_prince_test.96148888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/55.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/56.prim_prince_test.3158431520 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1208766981 ps |
| CPU time | 23.02 seconds |
| Started | Oct 14 08:17:34 PM UTC 24 |
| Finished | Oct 14 08:18:04 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158431520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 56.prim_prince_test.3158431520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/56.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/57.prim_prince_test.2108174057 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1782484672 ps |
| CPU time | 33.15 seconds |
| Started | Oct 14 08:17:34 PM UTC 24 |
| Finished | Oct 14 08:18:17 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108174057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 57.prim_prince_test.2108174057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/57.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/58.prim_prince_test.2652099273 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 909065071 ps |
| CPU time | 17.85 seconds |
| Started | Oct 14 08:17:35 PM UTC 24 |
| Finished | Oct 14 08:17:58 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652099273 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 58.prim_prince_test.2652099273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/58.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/59.prim_prince_test.3285205544 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3120555358 ps |
| CPU time | 59.74 seconds |
| Started | Oct 14 08:17:36 PM UTC 24 |
| Finished | Oct 14 08:18:51 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285205544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 59.prim_prince_test.3285205544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/59.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/6.prim_prince_test.801921435 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2325937658 ps |
| CPU time | 44.19 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:35 PM UTC 24 |
| Peak memory | 155048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801921435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 6.prim_prince_test.801921435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/6.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/60.prim_prince_test.2375220271 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2639839655 ps |
| CPU time | 49.74 seconds |
| Started | Oct 14 08:17:36 PM UTC 24 |
| Finished | Oct 14 08:18:39 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375220271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 60.prim_prince_test.2375220271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/60.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/61.prim_prince_test.2566600830 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1324099077 ps |
| CPU time | 25.31 seconds |
| Started | Oct 14 08:17:37 PM UTC 24 |
| Finished | Oct 14 08:18:10 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566600830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 61.prim_prince_test.2566600830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/61.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/62.prim_prince_test.283060516 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2106726789 ps |
| CPU time | 40.62 seconds |
| Started | Oct 14 08:17:37 PM UTC 24 |
| Finished | Oct 14 08:18:29 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283060516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 62.prim_prince_test.283060516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/62.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/63.prim_prince_test.1891704904 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2746209539 ps |
| CPU time | 51.14 seconds |
| Started | Oct 14 08:17:38 PM UTC 24 |
| Finished | Oct 14 08:18:44 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891704904 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 63.prim_prince_test.1891704904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/63.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/64.prim_prince_test.2053245293 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2852060220 ps |
| CPU time | 54.83 seconds |
| Started | Oct 14 08:17:41 PM UTC 24 |
| Finished | Oct 14 08:18:51 PM UTC 24 |
| Peak memory | 155032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053245293 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 64.prim_prince_test.2053245293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/64.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/65.prim_prince_test.3102580323 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2898404627 ps |
| CPU time | 53.55 seconds |
| Started | Oct 14 08:17:42 PM UTC 24 |
| Finished | Oct 14 08:18:51 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102580323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 65.prim_prince_test.3102580323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/65.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/66.prim_prince_test.3126171967 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1961328518 ps |
| CPU time | 37.08 seconds |
| Started | Oct 14 08:17:45 PM UTC 24 |
| Finished | Oct 14 08:18:32 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126171967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 66.prim_prince_test.3126171967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/66.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/67.prim_prince_test.3888319146 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3432662174 ps |
| CPU time | 64.33 seconds |
| Started | Oct 14 08:17:45 PM UTC 24 |
| Finished | Oct 14 08:19:06 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888319146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 67.prim_prince_test.3888319146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/67.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/68.prim_prince_test.1433310241 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2191299390 ps |
| CPU time | 41.92 seconds |
| Started | Oct 14 08:17:46 PM UTC 24 |
| Finished | Oct 14 08:18:39 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433310241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 68.prim_prince_test.1433310241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/68.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/69.prim_prince_test.320010741 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1784808990 ps |
| CPU time | 34.57 seconds |
| Started | Oct 14 08:17:48 PM UTC 24 |
| Finished | Oct 14 08:18:32 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320010741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 69.prim_prince_test.320010741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/69.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/7.prim_prince_test.2522417403 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2083062100 ps |
| CPU time | 40 seconds |
| Started | Oct 14 08:16:38 PM UTC 24 |
| Finished | Oct 14 08:17:30 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522417403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.prim_prince_test.2522417403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/7.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/70.prim_prince_test.985586799 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 1737276609 ps |
| CPU time | 33.52 seconds |
| Started | Oct 14 08:17:49 PM UTC 24 |
| Finished | Oct 14 08:18:31 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985586799 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 70.prim_prince_test.985586799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/70.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/71.prim_prince_test.2373803555 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1443358915 ps |
| CPU time | 27.93 seconds |
| Started | Oct 14 08:17:51 PM UTC 24 |
| Finished | Oct 14 08:18:26 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373803555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 71.prim_prince_test.2373803555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/71.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/72.prim_prince_test.3022764617 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2851951321 ps |
| CPU time | 54.15 seconds |
| Started | Oct 14 08:17:52 PM UTC 24 |
| Finished | Oct 14 08:19:00 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022764617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 72.prim_prince_test.3022764617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/72.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/73.prim_prince_test.1382400214 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2910119508 ps |
| CPU time | 55.71 seconds |
| Started | Oct 14 08:17:53 PM UTC 24 |
| Finished | Oct 14 08:19:03 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382400214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 73.prim_prince_test.1382400214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/73.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/74.prim_prince_test.2862696924 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1238122587 ps |
| CPU time | 23.45 seconds |
| Started | Oct 14 08:17:53 PM UTC 24 |
| Finished | Oct 14 08:18:23 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862696924 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 74.prim_prince_test.2862696924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/74.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/75.prim_prince_test.1256647837 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2244426626 ps |
| CPU time | 43 seconds |
| Started | Oct 14 08:17:56 PM UTC 24 |
| Finished | Oct 14 08:18:51 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256647837 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 75.prim_prince_test.1256647837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/75.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/76.prim_prince_test.79950929 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 894503137 ps |
| CPU time | 17.38 seconds |
| Started | Oct 14 08:17:59 PM UTC 24 |
| Finished | Oct 14 08:18:22 PM UTC 24 |
| Peak memory | 154984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79950929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 76.prim_prince_test.79950929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/76.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/77.prim_prince_test.436740026 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1590159410 ps |
| CPU time | 30.73 seconds |
| Started | Oct 14 08:18:00 PM UTC 24 |
| Finished | Oct 14 08:18:39 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436740026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 77.prim_prince_test.436740026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/77.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/78.prim_prince_test.3068701833 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1959238196 ps |
| CPU time | 37.32 seconds |
| Started | Oct 14 08:18:00 PM UTC 24 |
| Finished | Oct 14 08:18:48 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068701833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 78.prim_prince_test.3068701833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/78.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/79.prim_prince_test.3352310628 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 1431137050 ps |
| CPU time | 27.61 seconds |
| Started | Oct 14 08:18:00 PM UTC 24 |
| Finished | Oct 14 08:18:36 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352310628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 79.prim_prince_test.3352310628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/79.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/8.prim_prince_test.2572528685 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3663479758 ps |
| CPU time | 68.46 seconds |
| Started | Oct 14 08:16:39 PM UTC 24 |
| Finished | Oct 14 08:18:07 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572528685 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.prim_prince_test.2572528685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/8.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/80.prim_prince_test.3424198622 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1001310494 ps |
| CPU time | 19.16 seconds |
| Started | Oct 14 08:18:01 PM UTC 24 |
| Finished | Oct 14 08:18:26 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424198622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 80.prim_prince_test.3424198622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/80.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/81.prim_prince_test.3790792210 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2545229692 ps |
| CPU time | 48.72 seconds |
| Started | Oct 14 08:18:03 PM UTC 24 |
| Finished | Oct 14 08:19:05 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790792210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 81.prim_prince_test.3790792210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/81.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/82.prim_prince_test.443771036 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3427889530 ps |
| CPU time | 65.26 seconds |
| Started | Oct 14 08:18:04 PM UTC 24 |
| Finished | Oct 14 08:19:25 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443771036 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 82.prim_prince_test.443771036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/82.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/83.prim_prince_test.4067167281 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1657095689 ps |
| CPU time | 31.56 seconds |
| Started | Oct 14 08:18:04 PM UTC 24 |
| Finished | Oct 14 08:18:44 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067167281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 83.prim_prince_test.4067167281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/83.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/84.prim_prince_test.1426841739 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1673071954 ps |
| CPU time | 31.83 seconds |
| Started | Oct 14 08:18:05 PM UTC 24 |
| Finished | Oct 14 08:18:45 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426841739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 84.prim_prince_test.1426841739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/84.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/85.prim_prince_test.2518414906 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2006449278 ps |
| CPU time | 38.5 seconds |
| Started | Oct 14 08:18:05 PM UTC 24 |
| Finished | Oct 14 08:18:53 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518414906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 85.prim_prince_test.2518414906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/85.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/86.prim_prince_test.2561436089 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2486439229 ps |
| CPU time | 45.86 seconds |
| Started | Oct 14 08:18:07 PM UTC 24 |
| Finished | Oct 14 08:19:05 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561436089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 86.prim_prince_test.2561436089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/86.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/87.prim_prince_test.209743170 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3736256369 ps |
| CPU time | 67.99 seconds |
| Started | Oct 14 08:18:08 PM UTC 24 |
| Finished | Oct 14 08:19:35 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209743170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 87.prim_prince_test.209743170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/87.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/88.prim_prince_test.2372011698 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 986664502 ps |
| CPU time | 18.88 seconds |
| Started | Oct 14 08:18:08 PM UTC 24 |
| Finished | Oct 14 08:18:32 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372011698 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 88.prim_prince_test.2372011698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/88.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/89.prim_prince_test.589091978 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2518974735 ps |
| CPU time | 48.02 seconds |
| Started | Oct 14 08:18:08 PM UTC 24 |
| Finished | Oct 14 08:19:09 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589091978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 89.prim_prince_test.589091978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/89.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/9.prim_prince_test.2850815619 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 847155452 ps |
| CPU time | 16.9 seconds |
| Started | Oct 14 08:16:39 PM UTC 24 |
| Finished | Oct 14 08:17:01 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850815619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 9.prim_prince_test.2850815619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/9.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/90.prim_prince_test.3380195533 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2392507659 ps |
| CPU time | 44.47 seconds |
| Started | Oct 14 08:18:10 PM UTC 24 |
| Finished | Oct 14 08:19:07 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380195533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 90.prim_prince_test.3380195533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/90.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/91.prim_prince_test.588420033 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 3696633445 ps |
| CPU time | 68.09 seconds |
| Started | Oct 14 08:18:11 PM UTC 24 |
| Finished | Oct 14 08:19:38 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588420033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 91.prim_prince_test.588420033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/91.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/92.prim_prince_test.2859866921 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 2751141585 ps |
| CPU time | 51.12 seconds |
| Started | Oct 14 08:18:16 PM UTC 24 |
| Finished | Oct 14 08:19:21 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859866921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 92.prim_prince_test.2859866921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/92.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/93.prim_prince_test.3157863469 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 805750347 ps |
| CPU time | 15.67 seconds |
| Started | Oct 14 08:18:17 PM UTC 24 |
| Finished | Oct 14 08:18:38 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157863469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 93.prim_prince_test.3157863469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/93.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/94.prim_prince_test.509598861 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2230767282 ps |
| CPU time | 41.99 seconds |
| Started | Oct 14 08:18:17 PM UTC 24 |
| Finished | Oct 14 08:19:11 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509598861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 94.prim_prince_test.509598861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/94.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/95.prim_prince_test.1328527950 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3118988418 ps |
| CPU time | 56.95 seconds |
| Started | Oct 14 08:18:18 PM UTC 24 |
| Finished | Oct 14 08:19:31 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328527950 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 95.prim_prince_test.1328527950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/95.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/96.prim_prince_test.885144147 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3419374378 ps |
| CPU time | 62.56 seconds |
| Started | Oct 14 08:18:21 PM UTC 24 |
| Finished | Oct 14 08:19:41 PM UTC 24 |
| Peak memory | 155044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885144147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 96.prim_prince_test.885144147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/96.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/97.prim_prince_test.641620971 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1103927186 ps |
| CPU time | 20.7 seconds |
| Started | Oct 14 08:18:23 PM UTC 24 |
| Finished | Oct 14 08:18:49 PM UTC 24 |
| Peak memory | 154980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641620971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 97.prim_prince_test.641620971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/97.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/98.prim_prince_test.1167801043 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 846381042 ps |
| CPU time | 16.48 seconds |
| Started | Oct 14 08:18:23 PM UTC 24 |
| Finished | Oct 14 08:18:44 PM UTC 24 |
| Peak memory | 154972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167801043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 98.prim_prince_test.1167801043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/98.prim_prince_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default/99.prim_prince_test.3285233412 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3726613052 ps |
| CPU time | 68.25 seconds |
| Started | Oct 14 08:18:23 PM UTC 24 |
| Finished | Oct 14 08:19:49 PM UTC 24 |
| Peak memory | 155036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285233412 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 99.prim_prince_test.3285233412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/prim_prince-sim-vcs/99.prim_prince_test/latest |
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