PWM Simulation Results

Friday May 06 2022 08:04:28 UTC

GitHub Revision: `7cddd1c0e`
Foundry Revision: `7cddd1c0e`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 4082396206

Test Results

Milestone	Name	Tests	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	5	5	100.00
V1	csr_rw	pwm_csr_rw	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	20	20	100.00
		pwm_csr_aliasing	5	5	100.00
V1		TOTAL	105	105	100.00
V2	dutycycle	pwm_rand_output	36	50	72.00
V2	pulse	pwm_rand_output	36	50	72.00
V2	blink	pwm_rand_output	36	50	72.00
V2	heartbeat	pwm_rand_output	36	50	72.00
V2	resolution	pwm_rand_output	36	50	72.00
V2	multi_channel	pwm_rand_output	36	50	72.00
V2	polarity	pwm_rand_output	36	50	72.00
V2	phase	pwm_rand_output	36	50	72.00
V2	lowpower	pwm_rand_output	36	50	72.00
V2	perf	pwm_stress_perf	0	0	--
V2	stress_all	pwm_stress_perf	0	0	--
V2	alert_test	pwm_alert_test	50	50	100.00
V2	intr_test	pwm_intr_test	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	5	5	100.00
		pwm_csr_rw	20	20	100.00
		pwm_csr_aliasing	5	5	100.00
		pwm_same_csr_outstanding	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	5	5	100.00
		pwm_csr_rw	20	20	100.00
		pwm_csr_aliasing	5	5	100.00
		pwm_same_csr_outstanding	20	20	100.00
V2		TOTAL	176	190	92.63
V2S	tl_intg_err	pwm_tl_intg_err	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity	0	0	--
V2S		TOTAL	20	20	100.00
V3		TOTAL	0	0	--
	Unmapped tests	pwm_mem_walk	5	5	100.00
		pwm_mem_partial_access	5	5	100.00
		TOTAL	311	325	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	6	6	6	100.00
V2	6	5	4	66.67
V2S	2	1	1	50.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.65	76.52	68.98	80.31	74.11	72.73	100.00	81.28	93.77

Failure Buckets

Exit reason: Error: User command failed UVM_FATAL (pwm_scoreboard.sv:201) scoreboard [scoreboard] has 9 failures:
- Test pwm_rand_output has 9 failures.
  - 1.pwm_rand_output.626693540
    Line 178, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_rand_output/out/run.log
```
  UVM_FATAL @ 158796030 ps: (pwm_scoreboard.sv:201) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM pulse on Channel           3 did not match
  .......| Exp Item |.......
  
  ------| PWM ITEM |------
```
  - 7.pwm_rand_output.4188609456
    Line 204, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_rand_output/out/run.log
```
  UVM_FATAL @ 373790798 ps: (pwm_scoreboard.sv:201) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM pulse on Channel           3 did not match
  .......| Exp Item |.......
  
  ------| PWM ITEM |------
```
  - ... and 7 more failures.

UVM_ERROR (pwm_scoreboard.sv:371) [scoreboard] exp_item_q[i] item uncompared: has 5 failures:

Test pwm_rand_output has 5 failures.

9.pwm_rand_output.1204537588
Line 147, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_rand_output/out/run.log

  UVM_ERROR @ 298390353 ps: (pwm_scoreboard.sv:371) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -----------------------------------------
  Name            Type      Size  Value
  -----------------------------------------
  exp_item        pwm_item  -     @11949

11.pwm_rand_output.2381045028
Line 223, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/11.pwm_rand_output/out/run.log

  UVM_ERROR @ 660395596 ps: (pwm_scoreboard.sv:371) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  --------------------------------------
  Name            Type      Size  Value
  --------------------------------------
  exp_item        pwm_item  -     @12573

... and 3 more failures.