83db9403d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 7.000s | 2.039ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 32.003us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 3.000s | 14.829us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 472.472us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 411.284us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 5.000s | 27.456us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 14.829us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 5.000s | 411.284us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.133m | 10.829ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 52.000s | 10.505ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.317m | 223.691ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 23.437us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 14.913us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 506.275us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 506.275us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 32.003us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 14.829us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 411.284us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 86.047us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 32.003us | 5 | 5 | 100.00 |
pwm_csr_rw | 3.000s | 14.829us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 411.284us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 4.000s | 86.047us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 117.242us | 20 | 20 | 100.00 |
pwm_sec_cm | 5.000s | 110.890us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 117.242us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.62 | 99.59 | 99.26 | 99.88 | 95.34 | 94.92 | -- | 100.00 | 99.34 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
15.pwm_stress_all.1208989645
Line 500, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_stress_all/latest/run.log
UVM_ERROR @ 74136152387 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 74136152387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.pwm_stress_all.3727284851
Line 6814537, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/25.pwm_stress_all/latest/run.log
UVM_ERROR @ 29205695856 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 29205695856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.