c06cc3921
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 6.000s | 2.126ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 47.949us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 4.000s | 23.877us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 232.538us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 357.501us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 5.000s | 22.107us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 23.877us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 5.000s | 357.501us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 1.717m | 87.491ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 51.000s | 10.720ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.433m | 88.565ms | 48 | 50 | 96.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 54.984us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 3.000s | 24.251us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 9.000s | 169.700us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 9.000s | 169.700us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 47.949us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 23.877us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 357.501us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 103.316us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 47.949us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 23.877us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 357.501us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 103.316us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 7.000s | 606.229us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 50.771us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 7.000s | 606.229us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.45 | 99.49 | 99.08 | 99.80 | 94.86 | 94.92 | -- | 100.00 | 99.34 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 2 failures:
9.pwm_stress_all.3383454235
Line 3837, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_stress_all/latest/run.log
UVM_ERROR @ 19483362983 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 19483362983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.pwm_stress_all.1582895308
Line 137549, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_stress_all/latest/run.log
UVM_ERROR @ 179930960777 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 179930960777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 1 failures:
42.pwm_rand_output.3222145107
Line 306, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/42.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---