PWM Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 88555427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 7.000s 512.889us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 52.466us 5 5 100.00
V1 csr_rw pwm_csr_rw 4.000s 50.380us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 12.000s 629.784us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 376.308us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 6.000s 120.345us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 4.000s 50.380us 20 20 100.00
pwm_csr_aliasing 5.000s 376.308us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 pulse pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 blink pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 heartbeat pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 resolution pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 multi_channel pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 polarity pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 phase pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 lowpower pwm_rand_output 1.533m 10.718ms 49 50 98.00
V2 perf pwm_perf 54.000s 10.828ms 49 50 98.00
V2 stress_all pwm_stress_all 4.567m 69.029ms 46 50 92.00
V2 alert_test pwm_alert_test 3.000s 34.889us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 16.877us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 8.000s 180.502us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 8.000s 180.502us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 52.466us 5 5 100.00
pwm_csr_rw 4.000s 50.380us 20 20 100.00
pwm_csr_aliasing 5.000s 376.308us 5 5 100.00
pwm_same_csr_outstanding 5.000s 60.575us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 52.466us 5 5 100.00
pwm_csr_rw 4.000s 50.380us 20 20 100.00
pwm_csr_aliasing 5.000s 376.308us 5 5 100.00
pwm_same_csr_outstanding 5.000s 60.575us 20 20 100.00
V2 TOTAL 284 290 97.93
V2S tl_intg_err pwm_tl_intg_err 6.000s 1.938ms 20 20 100.00
pwm_sec_cm 3.000s 1.115ms 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 1.938ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 414 420 98.57

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 4 57.14
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.62 99.59 99.26 99.92 95.27 94.92 -- 100.00 99.34

Failure Buckets

Past Results