PWRMGR Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: 83db9403d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	29.332us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.710s	35.400us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.660s	139.767us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.990s	44.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.530s	59.182us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	44.137us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.470s	211.292us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.470s	211.292us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	67.795us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	43.260us	49	50	98.00
V2	reset	pwrmgr_reset	1.250s	65.080us	50	50	100.00
		pwrmgr_reset_invalid	1.080s	114.065us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.250s	65.080us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.750s	331.800us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.600s	244.480us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.970s	64.937us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	8.050s	2.362ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	47.445us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.480s	119.864us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.480s	119.864us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.710s	35.400us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	44.137us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.870s	252.155us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.710s	35.400us	5	5	100.00
		pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
		pwrmgr_csr_aliasing	0.990s	44.137us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.870s	252.155us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.720s	193.537us	20	20	100.00
		pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.720s	193.537us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.140s	811.236us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.260s	839.248us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.020s	69.445us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.660s	30.636us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.420s	360.479us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.700s	40.141us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.670s	54.947us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.510s	217.207us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	20.634us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	50.390s	12.164ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1068	1070	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.91	98.21	96.58	99.44	96.00	96.27	100.00	98.85

Failure Buckets

• UVM_ERROR (pwrmgr_base_vseq.sv:264) [pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.577171103
      Line 6314, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8570430754 ps: (pwrmgr_base_vseq.sv:264) [uvm_test_top.env.virtual_sequencer.pwrmgr_aborted_low_power_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 8570430754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 31.pwrmgr_lowpower_invalid.3663689318
      Line 217, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  30763347 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  30763347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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