26b0ee226
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwrmgr_smoke | 0.720s | 32.538us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.680s | 60.702us | 5 | 5 | 100.00 |
V1 | csr_rw | pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.490s | 336.470us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwrmgr_csr_aliasing | 0.990s | 42.562us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.490s | 119.706us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 |
pwrmgr_csr_aliasing | 0.990s | 42.562us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | wakeup | pwrmgr_wakeup | 1.260s | 185.579us | 50 | 50 | 100.00 |
V2 | control_clks | pwrmgr_wakeup | 1.260s | 185.579us | 50 | 50 | 100.00 |
V2 | aborted_low_power | pwrmgr_aborted_low_power | 0.810s | 32.356us | 50 | 50 | 100.00 |
pwrmgr_lowpower_invalid | 0.780s | 45.185us | 50 | 50 | 100.00 | ||
V2 | reset | pwrmgr_reset | 1.280s | 80.409us | 50 | 50 | 100.00 |
pwrmgr_reset_invalid | 1.100s | 111.112us | 50 | 50 | 100.00 | ||
V2 | main_power_glitch_reset | pwrmgr_reset | 1.280s | 80.409us | 50 | 50 | 100.00 |
V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 1.820s | 315.225us | 50 | 50 | 100.00 |
V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 1.340s | 276.973us | 50 | 50 | 100.00 |
V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.950s | 49.705us | 50 | 50 | 100.00 |
V2 | stress_all | pwrmgr_stress_all | 7.850s | 1.649ms | 50 | 50 | 100.00 |
V2 | intr_test | pwrmgr_intr_test | 0.680s | 22.402us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 3.160s | 1.620ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwrmgr_tl_errors | 3.160s | 1.620ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.680s | 60.702us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.990s | 42.562us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.940s | 46.947us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.680s | 60.702us | 5 | 5 | 100.00 |
pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 | ||
pwrmgr_csr_aliasing | 0.990s | 42.562us | 5 | 5 | 100.00 | ||
pwrmgr_same_csr_outstanding | 0.940s | 46.947us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 540 | 540 | 100.00 | |||
V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.680s | 196.917us | 20 | 20 | 100.00 |
pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 | ||
V2S | prim_count_check | pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.680s | 196.917us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 4.070s | 836.224us | 50 | 50 | 100.00 |
V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 4.030s | 868.395us | 50 | 50 | 100.00 |
V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.960s | 70.856us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.670s | 29.566us | 50 | 50 | 100.00 |
V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 |
V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.710s | 705.153us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.680s | 51.758us | 50 | 50 | 100.00 |
V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.710s | 63.653us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 1.670s | 257.518us | 50 | 50 | 100.00 |
V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 |
V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.690s | 63.850us | 20 | 20 | 100.00 |
V2S | TOTAL | 375 | 375 | 100.00 | |||
V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 42.050s | 8.899ms | 47 | 50 | 94.00 |
V3 | TOTAL | 47 | 50 | 94.00 | |||
TOTAL | 1067 | 1070 | 99.72 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 12 | 12 | 12 | 100.00 |
V2S | 9 | 9 | 9 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.91 | 98.21 | 96.44 | 99.44 | 96.00 | 96.27 | 100.00 | 99.02 |
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
has 2 failures:
16.pwrmgr_stress_all_with_rand_reset.1672400409
Line 1448, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest/run.log
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
UVM_ERROR @ 4587216661 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
UVM_INFO @ 4587216661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pwrmgr_stress_all_with_rand_reset.3069872919
Line 2616, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log
Offending 'pwrmgr.u_fsm.reset_reqs_i[pwrmgr_reg_pkg::ResetEscIdx]'
UVM_ERROR @ 13084676818 ps: (pwrmgr.sv:159) [ASSERT FAILED] PwrmgrSecCmFsmEscToResetReq_A
UVM_INFO @ 13084676818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:99) [pwrmgr_common_vseq] wait timeout occurred!
has 1 failures:
27.pwrmgr_stress_all_with_rand_reset.4181242904
Line 4246, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14339178655 ps: (cip_base_vseq.sv:99) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] wait timeout occurred!
UVM_INFO @ 14339178655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---