PWRMGR Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.730s 27.616us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 35.053us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.690s 274.529us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.010s 95.391us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.060s 56.487us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 95.391us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.640s 298.116us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.640s 298.116us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.790s 93.148us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 43.294us 50 50 100.00
V2 reset pwrmgr_reset 1.360s 80.130us 50 50 100.00
pwrmgr_reset_invalid 1.070s 99.561us 49 50 98.00
V2 main_power_glitch_reset pwrmgr_reset 1.360s 80.130us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.610s 366.824us 49 50 98.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.580s 293.822us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.970s 56.756us 50 50 100.00
V2 stress_all pwrmgr_stress_all 9.810s 2.141ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.700s 20.568us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.600s 272.231us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.600s 272.231us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 35.053us 5 5 100.00
pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 95.391us 5 5 100.00
pwrmgr_same_csr_outstanding 0.910s 47.344us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 35.053us 5 5 100.00
pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 95.391us 5 5 100.00
pwrmgr_same_csr_outstanding 0.910s 47.344us 20 20 100.00
V2 TOTAL 538 540 99.63
V2S tl_intg_err pwrmgr_tl_intg_err 2.020s 1.293ms 20 20 100.00
pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 2.020s 1.293ms 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.820s 792.119us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 4.060s 906.424us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.930s 53.344us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.680s 29.873us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.170s 686.617us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 47.814us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.730s 56.655us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.370s 273.541us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.700s 25.348us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 49.420s 12.326ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1068 1070 99.81

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 10 83.33
V2S 9 9 9 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.93 98.21 96.58 99.44 96.00 96.27 100.00 99.02

Failure Buckets

Past Results