PWRMGR Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: c06cc3921

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.770s	30.839us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.670s	50.102us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.500s	281.232us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.050s	191.034us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.350s	112.653us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	191.034us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.330s	258.413us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.330s	258.413us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.810s	38.336us	50	50	100.00
		pwrmgr_lowpower_invalid	0.800s	46.830us	50	50	100.00
V2	reset	pwrmgr_reset	1.410s	88.667us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	105.999us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.410s	88.667us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.620s	321.915us	49	50	98.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.650s	263.452us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.960s	66.460us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.100s	1.507ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.670s	22.323us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.940s	736.594us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.940s	736.594us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.670s	50.102us	5	5	100.00
		pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	191.034us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	43.285us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.670s	50.102us	5	5	100.00
		pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
		pwrmgr_csr_aliasing	1.050s	191.034us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.910s	43.285us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.690s	205.618us	20	20	100.00
		pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.690s	205.618us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.110s	866.584us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.110s	826.570us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.010s	75.322us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	30.256us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.830s	710.323us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.680s	73.844us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.770s	53.898us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.670s	249.529us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.710s	30.057us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	38.750s	9.412ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1069	1070	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.93	98.21	96.58	99.44	96.00	96.27	100.00	99.02

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test pwrmgr_wakeup_reset has 1 failures.

    • 44.pwrmgr_wakeup_reset.1901739209
      Line 337, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.26_19.05.15
• 2023.05.25_18.17.53
• 2023.05.24_17.37.59
• 2023.05.23_17.57.06
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