PWRMGR Simulation Results

Monday May 29 2023 07:02:33 UTC

GitHub Revision: 877a77116

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88555427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.720s	31.550us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.740s	31.258us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.750s	72.021us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	133.622us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.380s	103.736us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	133.622us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.570s	249.293us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.570s	249.293us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.820s	34.437us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	43.686us	50	50	100.00
V2	reset	pwrmgr_reset	1.380s	77.014us	50	50	100.00
		pwrmgr_reset_invalid	1.090s	100.422us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.380s	77.014us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.680s	352.244us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.320s	285.135us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.000s	63.053us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	7.120s	1.924ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.680s	85.616us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.910s	209.518us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.910s	209.518us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.740s	31.258us	5	5	100.00
		pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	133.622us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	158.778us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.740s	31.258us	5	5	100.00
		pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	133.622us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	158.778us	20	20	100.00
V2		TOTAL			540	540	100.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.740s	190.708us	20	20	100.00
		pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.740s	190.708us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	3.980s	780.751us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.340s	869.202us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.950s	73.482us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.650s	47.569us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.610s	966.935us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.690s	56.813us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.690s	52.268us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.710s	292.909us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.720s	66.268us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	47.720s	10.592ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1069	1070	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	12	100.00
V2S	9	9	9	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.91	98.21	96.58	99.44	96.00	96.27	100.00	98.85

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: pwrmgr_reg_block.wake_status reset value: * wake_status has 1 failures:
  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 40.pwrmgr_stress_all_with_rand_reset.4272569991
      Line 812, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2379137912 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 17 [0x11]) Regname: pwrmgr_reg_block.wake_status reset value: 0x0 wake_status
        UVM_INFO @ 2379137912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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