PWRMGR Simulation Results

Sunday October 17 2021 19:37:32 UTC

GitHub Revision: 4ac735964

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke pwrmgr_smoke 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 20 20 100.00
V1 TOTAL 105 105 100.00
V2 wakeup wakeup 0 0 --
V2 control_clks control_clks 0 0 --
V2 aborted_lowpower aborted_lowpower 0 0 --
V2 reset reset 0 0 --
V2 main_power_glitch_reset main_power_glitch_reset 0 0 --
V2 reset_wakeup_race reset_wakeup_race 0 0 --
V2 lowpower_wakeup_race lowpower_wakeup_race 0 0 --
V2 intr_test pwrmgr_intr_test 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 5 5 100.00
pwrmgr_csr_rw 20 20 100.00
pwrmgr_csr_aliasing 5 5 100.00
pwrmgr_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 5 5 100.00
pwrmgr_csr_rw 20 20 100.00
pwrmgr_csr_aliasing 5 5 100.00
pwrmgr_same_csr_outstanding 20 20 100.00
V2 TOTAL 90 90 100.00
V2S TOTAL 0 0 --
V3 stress stress 0 0 --
V3 tl_intg_err pwrmgr_tl_intg_err 20 20 100.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 0 0 --
V3 TOTAL 20 20 100.00
Unmapped tests pwrmgr_wakeup 50 50 100.00
pwrmgr_mem_walk 5 5 100.00
pwrmgr_mem_partial_access 5 5 100.00
TOTAL 275 275 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 3 3 3 100.00
V1 6 6 6 100.00
V2 10 3 3 30.00
V3 3 1 1 33.33

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
87.98 98.40 84.33 92.14 -- 96.38 95.20 61.44

Past Results