ROM_CTRL Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	35.150s	7.184ms	46	50	92.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.530s	1.448ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.300s	2.350ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.620s	4.226ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	13.820s	8.194ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.210s	1.822ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.300s	2.350ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.820s	8.194ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	11.510s	5.923ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.830s	12.723ms	5	5	100.00
V1		TOTAL			111	115	96.52
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	14.980s	2.020ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.315m	50.654ms	50	50	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.020s	8.527ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.850s	2.118ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.730s	10.299ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.730s	10.299ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.530s	1.448ms	5	5	100.00
		rom_ctrl_csr_rw	14.300s	2.350ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.820s	8.194ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.630s	4.266ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.530s	1.448ms	5	5	100.00
		rom_ctrl_csr_rw	14.300s	2.350ms	20	20	100.00
		rom_ctrl_csr_aliasing	13.820s	8.194ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.630s	4.266ms	20	20	100.00
V2		TOTAL			240	240	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.626m	45.199ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.705m	9.115ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.220m	4.571ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.705m	9.115ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.705m	9.115ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.705m	9.115ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	35.150s	7.184ms	46	50	92.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	35.150s	7.184ms	46	50	92.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	35.150s	7.184ms	46	50	92.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.220m	4.571ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
		rom_ctrl_kmac_err_chk	30.020s	8.527ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.352m	30.778ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.626m	45.199ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.705m	9.115ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.968h	71.218ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			476	500	95.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.73	97.16	92.68	97.88	86.67	98.36	98.04	99.30

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 15 failures.
  - 4.rom_ctrl_stress_all_with_rand_reset.594970287
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:abb9574d-8ab1-430b-b7e8-11a14facbf01
```
  - 5.rom_ctrl_stress_all_with_rand_reset.3761796094
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d5da47cd-5aa0-4020-8ec9-b261de77aebd
```
  - ... and 13 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 8 failures:

Test rom_ctrl_stress_all_with_rand_reset has 4 failures.

0.rom_ctrl_stress_all_with_rand_reset.3437510445
Line 239, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 15672437799 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xde56f81
  UVM_INFO @ 15672437799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rom_ctrl_stress_all_with_rand_reset.2033495351
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10011574859 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xd7d193a8
  UVM_INFO @ 10011574859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test rom_ctrl_smoke has 4 failures.

1.rom_ctrl_smoke.666154493
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010447138 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb013c925
  UVM_INFO @ 10010447138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.rom_ctrl_smoke.2711659385
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010076200 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xba31eac5
  UVM_INFO @ 10010076200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 36.rom_ctrl_corrupt_sig_fatal_chk.2239639126
    Line 234, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/36.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```