ROM_CTRL Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	35.740s	4.171ms	48	50	96.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	15.360s	2.594ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.660s	2.130ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	13.920s	8.755ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	12.100s	2.268ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	15.100s	9.715ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.660s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.100s	2.268ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.480s	1.035ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	13.860s	2.097ms	5	5	100.00
V1		TOTAL			113	115	98.26
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.740s	2.212ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	1.729m	15.363ms	48	50	96.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	28.890s	16.043ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.840s	2.025ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.960s	1.980ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.960s	1.980ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	15.360s	2.594ms	5	5	100.00
		rom_ctrl_csr_rw	14.660s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.100s	2.268ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.390s	2.167ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	15.360s	2.594ms	5	5	100.00
		rom_ctrl_csr_rw	14.660s	2.130ms	20	20	100.00
		rom_ctrl_csr_aliasing	12.100s	2.268ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.390s	2.167ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	5.464m	82.466ms	17	20	85.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.693m	8.619ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.195m	7.677ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.693m	8.619ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.693m	8.619ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.693m	8.619ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	35.740s	4.171ms	48	50	96.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	35.740s	4.171ms	48	50	96.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	35.740s	4.171ms	48	50	96.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.195m	7.677ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
		rom_ctrl_kmac_err_chk	28.890s	16.043ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.502m	157.203ms	48	50	96.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	5.464m	82.466ms	17	20	85.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.693m	8.619ms	5	5	100.00
V2S		TOTAL			90	95	94.74
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.519h	101.805ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			469	500	93.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	5	83.33
V2S	4	4	2	50.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.68	97.16	92.68	97.88	86.67	98.36	98.19	98.84

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 17 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 17 failures.
  - 5.rom_ctrl_stress_all_with_rand_reset.2361384864
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/5.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:dc898d82-2afc-41b4-a3d7-630168d53869
```
  - 7.rom_ctrl_stress_all_with_rand_reset.4249592910
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/7.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:15abccb4-0cec-4bf3-af81-a7276b645406
```
  - ... and 15 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 9 failures:

Test rom_ctrl_stress_all has 2 failures.

2.rom_ctrl_stress_all.2935212746
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10012486558 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x1dc16cd1
  UVM_INFO @ 10012486558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.rom_ctrl_stress_all.333275592
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/35.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10009306079 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x26b3924c
  UVM_INFO @ 10009306079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_stress_all_with_rand_reset has 5 failures.

6.rom_ctrl_stress_all_with_rand_reset.1100565461
Line 228, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/6.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10147277260 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x642e5db2
  UVM_INFO @ 10147277260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.rom_ctrl_stress_all_with_rand_reset.339851795
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/14.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10005641842 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xd10ecbea
  UVM_INFO @ 10005641842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test rom_ctrl_smoke has 2 failures.

16.rom_ctrl_smoke.647342946
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/16.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10010535857 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x523cb820
  UVM_INFO @ 10010535857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.rom_ctrl_smoke.855351865
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10021884622 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x96d96eff
  UVM_INFO @ 10021884622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 3 failures:

Test rom_ctrl_passthru_mem_tl_intg_err has 3 failures.

2.rom_ctrl_passthru_mem_tl_intg_err.1958244890
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10010737775 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x77f98004
  UVM_INFO @ 10010737775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rom_ctrl_passthru_mem_tl_intg_err.3173884914
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @ 10011343726 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_common_vseq] Timeout waiting tl_access : addr=0x91568004
  UVM_INFO @ 10011343726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:595) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 2 failures:

Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

3.rom_ctrl_corrupt_sig_fatal_chk.2343277390
Line 253, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 3851852967 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 3851852967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.rom_ctrl_corrupt_sig_fatal_chk.2084835237
Line 231, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/28.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

  UVM_ERROR @ 644889339 ps: (cip_base_vseq.sv:595) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
  UVM_INFO @ 644889339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---