ROM_CTRL Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	38.380s	17.799ms	47	50	94.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	14.100s	1.771ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	14.390s	8.674ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	14.740s	4.276ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	14.250s	2.023ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	13.810s	1.792ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	14.390s	8.674ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	2.023ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	12.380s	1.648ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	11.950s	1.600ms	5	5	100.00
V1		TOTAL			112	115	97.39
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	15.730s	2.108ms	50	50	100.00
V2	stress_all	rom_ctrl_stress_all	2.066m	30.700ms	43	50	86.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	30.430s	8.226ms	50	50	100.00
V2	alert_test	rom_ctrl_alert_test	14.070s	2.112ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.340s	3.763ms	19	20	95.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.340s	3.763ms	19	20	95.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	14.100s	1.771ms	5	5	100.00
		rom_ctrl_csr_rw	14.390s	8.674ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	2.023ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.530s	4.285ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	14.100s	1.771ms	5	5	100.00
		rom_ctrl_csr_rw	14.390s	8.674ms	20	20	100.00
		rom_ctrl_csr_aliasing	14.250s	2.023ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.530s	4.285ms	20	20	100.00
V2		TOTAL			232	240	96.67
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	4.154m	115.097ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.692m	5.123ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.191m	26.488ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.692m	5.123ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.692m	5.123ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.692m	5.123ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	38.380s	17.799ms	47	50	94.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	38.380s	17.799ms	47	50	94.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	38.380s	17.799ms	47	50	94.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.191m	26.488ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
		rom_ctrl_kmac_err_chk	30.430s	8.226ms	50	50	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.496m	155.120ms	49	50	98.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	4.154m	115.097ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.692m	5.123ms	5	5	100.00
V2S		TOTAL			94	95	98.95
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.875h	76.604ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			473	500	94.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	6	6	4	66.67
V2S	4	4	3	75.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.83	97.16	93.12	97.88	86.67	98.68	98.19	99.07

Failure Buckets

Job rom_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
- Test rom_ctrl_stress_all_with_rand_reset has 14 failures.
  - 1.rom_ctrl_stress_all_with_rand_reset.680904373
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/1.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:3644e9a6-28b1-4c8e-a0b0-abd8f79a8b80
```
  - 9.rom_ctrl_stress_all_with_rand_reset.3093177193
    Log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/9.rom_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ccb69656-2953-4e55-ae06-d3f742767103
```
  - ... and 12 more failures.

UVM_FATAL (cip_base_vseq.sv:245) [rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=* has 11 failures:

Test rom_ctrl_stress_all has 7 failures.

0.rom_ctrl_stress_all.2582199114
Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/0.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10016983104 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x420c7088
  UVM_INFO @ 10016983104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rom_ctrl_stress_all.636209265
Line 221, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/4.rom_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10110557046 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xe44428fb
  UVM_INFO @ 10110557046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

12.rom_ctrl_stress_all_with_rand_reset.4086729884
Line 222, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/12.rom_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 10082847969 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0x207282b7
  UVM_INFO @ 10082847969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_ctrl_smoke has 3 failures.

19.rom_ctrl_smoke.1073965541
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/19.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10007752908 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xb58d0cf0
  UVM_INFO @ 10007752908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.rom_ctrl_smoke.784613995
Line 218, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/26.rom_ctrl_smoke/latest/run.log

  UVM_FATAL @ 10011991020 ps: (cip_base_vseq.sv:245) [uvm_test_top.env.virtual_sequencer.rom_ctrl_smoke_vseq] Timeout waiting tl_access : addr=0xa5275356
  UVM_INFO @ 10011991020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (rom_ctrl_scoreboard.sv:253) [scoreboard] Check failed pwrmgr_complete == *'b* (* [*] vs * [*]) pwrmgr signals never checked has 1 failures:
- Test rom_ctrl_tl_errors has 1 failures.
  - 2.rom_ctrl_tl_errors.2734996914
    Line 219, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/2.rom_ctrl_tl_errors/latest/run.log
```
  UVM_ERROR @ 1651488967 ps: (rom_ctrl_scoreboard.sv:253) [uvm_test_top.env.scoreboard] Check failed pwrmgr_complete == 1'b1 (0 [0x0] vs 1 [0x1]) pwrmgr signals never checked
  UVM_INFO @ 1651488967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 25.rom_ctrl_corrupt_sig_fatal_chk.3328402101
    Line 245, in log /container/opentitan-public/scratch/os_regression/rom_ctrl-sim-vcs/25.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```