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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.49 97.11 92.68 97.88 100.00 98.37 98.04 98.38


Total test records in report: 485
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T264 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1486447349 Oct 04 03:11:26 PM PDT 23 Oct 04 03:11:37 PM PDT 23 755046193 ps
T265 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3827885954 Oct 04 03:09:47 PM PDT 23 Oct 04 03:12:40 PM PDT 23 13543626833 ps
T266 /workspace/coverage/default/9.rom_ctrl_alert_test.3230284453 Oct 04 03:09:26 PM PDT 23 Oct 04 03:09:38 PM PDT 23 1152878710 ps
T267 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3296087882 Oct 04 03:08:55 PM PDT 23 Oct 04 03:16:24 PM PDT 23 143084797654 ps
T268 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.801525565 Oct 04 03:10:03 PM PDT 23 Oct 04 03:10:09 PM PDT 23 97398142 ps
T269 /workspace/coverage/default/2.rom_ctrl_alert_test.2234192653 Oct 04 03:09:52 PM PDT 23 Oct 04 03:10:08 PM PDT 23 3677780437 ps
T270 /workspace/coverage/default/8.rom_ctrl_alert_test.1218241641 Oct 04 03:09:57 PM PDT 23 Oct 04 03:10:10 PM PDT 23 8403285347 ps
T271 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1757766617 Oct 04 03:08:52 PM PDT 23 Oct 04 03:12:40 PM PDT 23 47841430133 ps
T272 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3884336535 Oct 04 03:09:48 PM PDT 23 Oct 04 03:10:00 PM PDT 23 1016092466 ps
T273 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2243082363 Oct 04 03:08:32 PM PDT 23 Oct 04 03:08:47 PM PDT 23 1576971308 ps
T274 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.364146673 Oct 04 03:09:11 PM PDT 23 Oct 04 03:09:17 PM PDT 23 340508038 ps
T275 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1446726507 Oct 04 03:08:33 PM PDT 23 Oct 04 03:08:43 PM PDT 23 693346593 ps
T276 /workspace/coverage/default/37.rom_ctrl_alert_test.3015783356 Oct 04 03:11:31 PM PDT 23 Oct 04 03:11:47 PM PDT 23 1953279878 ps
T277 /workspace/coverage/default/13.rom_ctrl_smoke.4171784453 Oct 04 03:10:45 PM PDT 23 Oct 04 03:10:56 PM PDT 23 194101604 ps
T278 /workspace/coverage/default/22.rom_ctrl_stress_all.3679777968 Oct 04 03:09:15 PM PDT 23 Oct 04 03:09:36 PM PDT 23 7790627582 ps
T279 /workspace/coverage/default/43.rom_ctrl_stress_all.2504326456 Oct 04 03:08:39 PM PDT 23 Oct 04 03:10:28 PM PDT 23 13007297141 ps
T280 /workspace/coverage/default/47.rom_ctrl_smoke.410275776 Oct 04 03:12:09 PM PDT 23 Oct 04 03:12:32 PM PDT 23 2460512612 ps
T281 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.39709784 Oct 04 03:20:21 PM PDT 23 Oct 04 03:23:37 PM PDT 23 38515016627 ps
T282 /workspace/coverage/default/0.rom_ctrl_stress_all.2290557676 Oct 04 03:08:42 PM PDT 23 Oct 04 03:09:19 PM PDT 23 22369481311 ps
T283 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1055349097 Oct 04 03:09:11 PM PDT 23 Oct 04 03:14:17 PM PDT 23 50969239614 ps
T284 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.65111899 Oct 04 03:08:33 PM PDT 23 Oct 04 04:09:25 PM PDT 23 170801032106 ps
T285 /workspace/coverage/default/21.rom_ctrl_alert_test.1414001544 Oct 04 03:09:01 PM PDT 23 Oct 04 03:09:06 PM PDT 23 347723114 ps
T286 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.684664121 Oct 04 03:09:28 PM PDT 23 Oct 04 03:09:44 PM PDT 23 1802976946 ps
T287 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1485979277 Oct 04 03:08:58 PM PDT 23 Oct 04 03:09:16 PM PDT 23 4335037957 ps
T288 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3725299702 Oct 04 03:08:39 PM PDT 23 Oct 04 03:08:50 PM PDT 23 993817763 ps
T289 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2906312111 Oct 04 03:08:51 PM PDT 23 Oct 04 03:09:07 PM PDT 23 6169890140 ps
T290 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3508715611 Oct 04 03:15:35 PM PDT 23 Oct 04 03:17:07 PM PDT 23 2868989951 ps
T291 /workspace/coverage/default/13.rom_ctrl_alert_test.2946766998 Oct 04 03:08:56 PM PDT 23 Oct 04 03:09:00 PM PDT 23 85637862 ps
T292 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.57052068 Oct 04 03:09:16 PM PDT 23 Oct 04 03:21:55 PM PDT 23 19963682468 ps
T293 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1793269187 Oct 04 03:09:19 PM PDT 23 Oct 04 03:20:57 PM PDT 23 49055546659 ps
T294 /workspace/coverage/default/5.rom_ctrl_smoke.2852157138 Oct 04 03:08:12 PM PDT 23 Oct 04 03:08:51 PM PDT 23 7889342734 ps
T295 /workspace/coverage/default/16.rom_ctrl_alert_test.3364727909 Oct 04 03:09:25 PM PDT 23 Oct 04 03:09:31 PM PDT 23 174851494 ps
T296 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3331510827 Oct 04 03:08:52 PM PDT 23 Oct 04 03:08:59 PM PDT 23 543841330 ps
T297 /workspace/coverage/default/32.rom_ctrl_alert_test.3274744075 Oct 04 03:09:01 PM PDT 23 Oct 04 03:09:08 PM PDT 23 1379250693 ps
T298 /workspace/coverage/default/9.rom_ctrl_stress_all.3545626695 Oct 04 03:10:21 PM PDT 23 Oct 04 03:11:50 PM PDT 23 34303983709 ps
T36 /workspace/coverage/default/3.rom_ctrl_sec_cm.1518350187 Oct 04 03:10:32 PM PDT 23 Oct 04 03:12:32 PM PDT 23 1443428767 ps
T47 /workspace/coverage/default/37.rom_ctrl_stress_all.2969063054 Oct 04 03:09:04 PM PDT 23 Oct 04 03:09:37 PM PDT 23 11828284591 ps
T48 /workspace/coverage/default/24.rom_ctrl_alert_test.4010511389 Oct 04 03:15:22 PM PDT 23 Oct 04 03:15:39 PM PDT 23 11477846558 ps
T299 /workspace/coverage/default/44.rom_ctrl_stress_all.4247528583 Oct 04 03:14:37 PM PDT 23 Oct 04 03:15:09 PM PDT 23 2883986674 ps
T300 /workspace/coverage/default/31.rom_ctrl_alert_test.2301059750 Oct 04 03:11:51 PM PDT 23 Oct 04 03:12:04 PM PDT 23 5828381650 ps
T301 /workspace/coverage/default/9.rom_ctrl_smoke.1770414265 Oct 04 03:08:31 PM PDT 23 Oct 04 03:08:49 PM PDT 23 9863649580 ps
T100 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3445512065 Oct 04 03:09:30 PM PDT 23 Oct 04 03:09:40 PM PDT 23 807177194 ps
T302 /workspace/coverage/default/27.rom_ctrl_alert_test.3915297667 Oct 04 03:09:06 PM PDT 23 Oct 04 03:09:13 PM PDT 23 323063414 ps
T303 /workspace/coverage/default/38.rom_ctrl_stress_all.3721232686 Oct 04 03:08:36 PM PDT 23 Oct 04 03:09:09 PM PDT 23 2262157001 ps
T304 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3319287599 Oct 04 03:09:08 PM PDT 23 Oct 04 03:09:28 PM PDT 23 2422793095 ps
T305 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1032029379 Oct 04 03:12:19 PM PDT 23 Oct 04 03:12:26 PM PDT 23 151145588 ps
T306 /workspace/coverage/default/40.rom_ctrl_stress_all.3014509027 Oct 04 03:08:39 PM PDT 23 Oct 04 03:09:09 PM PDT 23 2754812566 ps
T307 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.535461538 Oct 04 03:08:40 PM PDT 23 Oct 04 03:15:06 PM PDT 23 85393060693 ps
T308 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3826380654 Oct 04 03:08:53 PM PDT 23 Oct 04 03:09:03 PM PDT 23 691143074 ps
T309 /workspace/coverage/default/41.rom_ctrl_alert_test.1250194136 Oct 04 03:08:55 PM PDT 23 Oct 04 03:09:00 PM PDT 23 161742741 ps
T310 /workspace/coverage/default/1.rom_ctrl_stress_all.361520855 Oct 04 03:10:11 PM PDT 23 Oct 04 03:11:36 PM PDT 23 14173992919 ps
T311 /workspace/coverage/default/6.rom_ctrl_smoke.3721173078 Oct 04 03:08:34 PM PDT 23 Oct 04 03:08:45 PM PDT 23 190130913 ps
T312 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.786610862 Oct 04 03:09:12 PM PDT 23 Oct 04 03:09:28 PM PDT 23 2056743127 ps
T313 /workspace/coverage/default/31.rom_ctrl_smoke.1344859092 Oct 04 03:11:08 PM PDT 23 Oct 04 03:11:26 PM PDT 23 9300483556 ps
T314 /workspace/coverage/default/45.rom_ctrl_stress_all.4189144455 Oct 04 03:08:59 PM PDT 23 Oct 04 03:09:23 PM PDT 23 820345176 ps
T315 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1603036471 Oct 04 03:09:20 PM PDT 23 Oct 04 03:11:52 PM PDT 23 26553059022 ps
T316 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3986225894 Oct 04 03:11:18 PM PDT 23 Oct 04 03:13:35 PM PDT 23 26363721597 ps
T317 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.57820792 Oct 04 03:09:54 PM PDT 23 Oct 04 03:25:16 PM PDT 23 17655206853 ps
T318 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3257922278 Oct 04 03:08:36 PM PDT 23 Oct 04 03:08:41 PM PDT 23 128999038 ps
T319 /workspace/coverage/default/13.rom_ctrl_stress_all.4096591242 Oct 04 03:09:45 PM PDT 23 Oct 04 03:10:12 PM PDT 23 10795990076 ps
T320 /workspace/coverage/default/14.rom_ctrl_alert_test.2311867835 Oct 04 03:09:21 PM PDT 23 Oct 04 03:09:34 PM PDT 23 1197316643 ps
T321 /workspace/coverage/default/14.rom_ctrl_stress_all.1364830589 Oct 04 03:08:37 PM PDT 23 Oct 04 03:09:19 PM PDT 23 6621786461 ps
T322 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3465133158 Oct 04 03:10:42 PM PDT 23 Oct 04 03:11:02 PM PDT 23 1467932935 ps
T323 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1553616570 Oct 04 03:08:30 PM PDT 23 Oct 04 03:08:51 PM PDT 23 17251550286 ps
T324 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2802172244 Oct 04 03:14:09 PM PDT 23 Oct 04 03:19:50 PM PDT 23 31872262770 ps
T325 /workspace/coverage/default/3.rom_ctrl_smoke.3638390977 Oct 04 03:09:22 PM PDT 23 Oct 04 03:09:39 PM PDT 23 3254265527 ps
T14 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2636222529 Oct 04 03:12:12 PM PDT 23 Oct 04 03:27:24 PM PDT 23 159528467674 ps
T326 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1993427297 Oct 04 03:08:53 PM PDT 23 Oct 04 03:09:09 PM PDT 23 6729075608 ps
T327 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.813783421 Oct 04 03:08:44 PM PDT 23 Oct 04 03:09:01 PM PDT 23 6766713500 ps
T328 /workspace/coverage/default/1.rom_ctrl_alert_test.2750627295 Oct 04 03:10:05 PM PDT 23 Oct 04 03:10:10 PM PDT 23 89070008 ps
T329 /workspace/coverage/default/35.rom_ctrl_alert_test.2446011124 Oct 04 03:08:52 PM PDT 23 Oct 04 03:09:07 PM PDT 23 1629454797 ps
T330 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2921757402 Oct 04 03:08:34 PM PDT 23 Oct 04 03:32:32 PM PDT 23 151312834072 ps
T331 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1292648235 Oct 04 03:09:30 PM PDT 23 Oct 04 03:09:44 PM PDT 23 2781778992 ps
T332 /workspace/coverage/default/20.rom_ctrl_alert_test.3874601888 Oct 04 03:08:58 PM PDT 23 Oct 04 03:09:09 PM PDT 23 3740900037 ps
T333 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.647369777 Oct 04 03:09:15 PM PDT 23 Oct 04 03:12:38 PM PDT 23 19682851790 ps
T334 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1687927660 Oct 04 03:09:16 PM PDT 23 Oct 04 03:28:03 PM PDT 23 268669975207 ps
T335 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.915812126 Oct 04 03:09:24 PM PDT 23 Oct 04 03:09:59 PM PDT 23 15662107568 ps
T336 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3158380974 Oct 04 03:09:46 PM PDT 23 Oct 04 03:10:20 PM PDT 23 24536703393 ps
T337 /workspace/coverage/default/11.rom_ctrl_alert_test.4209828557 Oct 04 03:10:04 PM PDT 23 Oct 04 03:10:11 PM PDT 23 908085820 ps
T338 /workspace/coverage/default/3.rom_ctrl_alert_test.3219776540 Oct 04 03:09:56 PM PDT 23 Oct 04 03:10:09 PM PDT 23 2728294278 ps
T339 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1098765065 Oct 04 03:08:55 PM PDT 23 Oct 04 03:09:09 PM PDT 23 1686826558 ps
T340 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4095422919 Oct 04 03:09:03 PM PDT 23 Oct 04 03:09:22 PM PDT 23 5059888191 ps
T341 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3225688552 Oct 04 03:09:19 PM PDT 23 Oct 04 03:48:00 PM PDT 23 48640084384 ps
T342 /workspace/coverage/default/49.rom_ctrl_smoke.938468594 Oct 04 03:09:01 PM PDT 23 Oct 04 03:09:26 PM PDT 23 2762291588 ps
T41 /workspace/coverage/default/0.rom_ctrl_sec_cm.2726033671 Oct 04 03:10:47 PM PDT 23 Oct 04 03:11:46 PM PDT 23 695460433 ps
T343 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1318604066 Oct 04 03:10:06 PM PDT 23 Oct 04 03:10:18 PM PDT 23 2801609761 ps
T344 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1604851772 Oct 04 03:09:09 PM PDT 23 Oct 04 03:09:21 PM PDT 23 1056771490 ps
T345 /workspace/coverage/default/49.rom_ctrl_alert_test.1500553806 Oct 04 03:10:25 PM PDT 23 Oct 04 03:10:40 PM PDT 23 6809517139 ps
T346 /workspace/coverage/default/34.rom_ctrl_alert_test.599547908 Oct 04 03:12:16 PM PDT 23 Oct 04 03:12:21 PM PDT 23 85635636 ps
T347 /workspace/coverage/default/6.rom_ctrl_alert_test.841627404 Oct 04 03:08:37 PM PDT 23 Oct 04 03:08:45 PM PDT 23 596092548 ps
T348 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3865012498 Oct 04 03:10:07 PM PDT 23 Oct 04 03:10:24 PM PDT 23 1903783271 ps
T349 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3754274346 Oct 04 03:09:04 PM PDT 23 Oct 04 03:09:14 PM PDT 23 691139386 ps
T350 /workspace/coverage/default/34.rom_ctrl_smoke.3543264503 Oct 04 03:09:30 PM PDT 23 Oct 04 03:10:02 PM PDT 23 11812007034 ps
T351 /workspace/coverage/default/26.rom_ctrl_alert_test.3308155488 Oct 04 03:08:49 PM PDT 23 Oct 04 03:09:05 PM PDT 23 1452617447 ps
T352 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1889603798 Oct 04 03:09:16 PM PDT 23 Oct 04 03:09:23 PM PDT 23 142735708 ps
T353 /workspace/coverage/default/23.rom_ctrl_alert_test.3147606450 Oct 04 03:10:10 PM PDT 23 Oct 04 03:10:15 PM PDT 23 346585309 ps
T354 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3738323489 Oct 04 03:09:20 PM PDT 23 Oct 04 04:14:59 PM PDT 23 41743109364 ps
T355 /workspace/coverage/default/19.rom_ctrl_stress_all.3192424008 Oct 04 03:08:29 PM PDT 23 Oct 04 03:10:04 PM PDT 23 17259244123 ps
T356 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3330223001 Oct 04 03:09:04 PM PDT 23 Oct 04 03:13:29 PM PDT 23 65029639152 ps
T357 /workspace/coverage/default/4.rom_ctrl_alert_test.3203576930 Oct 04 03:09:19 PM PDT 23 Oct 04 03:09:25 PM PDT 23 140477459 ps
T358 /workspace/coverage/default/44.rom_ctrl_alert_test.945111009 Oct 04 03:09:26 PM PDT 23 Oct 04 03:09:33 PM PDT 23 2241343792 ps
T359 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3826970216 Oct 04 03:14:01 PM PDT 23 Oct 04 03:14:19 PM PDT 23 4396307727 ps
T360 /workspace/coverage/default/36.rom_ctrl_stress_all.4221416432 Oct 04 03:10:43 PM PDT 23 Oct 04 03:11:23 PM PDT 23 13910070169 ps
T361 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.151631042 Oct 04 03:09:12 PM PDT 23 Oct 04 03:11:00 PM PDT 23 6722424228 ps
T362 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3323471037 Oct 04 03:14:13 PM PDT 23 Oct 04 03:15:52 PM PDT 23 7168270176 ps
T363 /workspace/coverage/default/40.rom_ctrl_smoke.426933822 Oct 04 03:08:37 PM PDT 23 Oct 04 03:08:48 PM PDT 23 193419520 ps
T364 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.54441399 Oct 04 03:09:53 PM PDT 23 Oct 04 03:10:06 PM PDT 23 10530528563 ps
T365 /workspace/coverage/default/47.rom_ctrl_stress_all.2075576654 Oct 04 03:15:12 PM PDT 23 Oct 04 03:16:07 PM PDT 23 6495529950 ps
T366 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.133596125 Oct 04 03:09:33 PM PDT 23 Oct 04 03:10:08 PM PDT 23 8716258817 ps
T367 /workspace/coverage/default/25.rom_ctrl_stress_all.1868460121 Oct 04 03:11:58 PM PDT 23 Oct 04 03:12:57 PM PDT 23 5651958230 ps
T368 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3446473235 Oct 04 03:09:43 PM PDT 23 Oct 04 03:09:59 PM PDT 23 4591052473 ps
T369 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2717917855 Oct 04 03:09:05 PM PDT 23 Oct 04 03:09:32 PM PDT 23 2890539573 ps
T370 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3797514916 Oct 04 03:09:16 PM PDT 23 Oct 04 03:14:22 PM PDT 23 52657595852 ps
T371 /workspace/coverage/default/18.rom_ctrl_stress_all.3169749903 Oct 04 03:12:07 PM PDT 23 Oct 04 03:12:45 PM PDT 23 16595986258 ps
T372 /workspace/coverage/default/12.rom_ctrl_alert_test.3580214280 Oct 04 03:09:09 PM PDT 23 Oct 04 03:09:26 PM PDT 23 4029624434 ps
T373 /workspace/coverage/default/15.rom_ctrl_smoke.753016400 Oct 04 03:10:47 PM PDT 23 Oct 04 03:11:08 PM PDT 23 1576563444 ps
T374 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1390016823 Oct 04 03:10:01 PM PDT 23 Oct 04 03:10:16 PM PDT 23 3346681335 ps
T375 /workspace/coverage/default/10.rom_ctrl_stress_all.3211687787 Oct 04 03:10:54 PM PDT 23 Oct 04 03:11:29 PM PDT 23 6289567273 ps
T376 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4017475220 Oct 04 03:08:35 PM PDT 23 Oct 04 05:09:30 PM PDT 23 120087505667 ps
T377 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1696693308 Oct 04 03:08:57 PM PDT 23 Oct 04 03:09:16 PM PDT 23 1368367132 ps
T378 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.177063214 Oct 04 03:08:58 PM PDT 23 Oct 04 03:09:11 PM PDT 23 15839619496 ps
T379 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3356993884 Oct 04 03:09:02 PM PDT 23 Oct 04 03:10:44 PM PDT 23 8326887430 ps
T380 /workspace/coverage/default/7.rom_ctrl_alert_test.2292466208 Oct 04 03:10:41 PM PDT 23 Oct 04 03:10:48 PM PDT 23 1873892142 ps
T381 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1786819785 Oct 04 03:09:34 PM PDT 23 Oct 04 04:01:17 PM PDT 23 99970408249 ps
T382 /workspace/coverage/default/1.rom_ctrl_smoke.1683655818 Oct 04 03:08:49 PM PDT 23 Oct 04 03:09:23 PM PDT 23 25894053967 ps
T383 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3033446587 Oct 04 03:09:19 PM PDT 23 Oct 04 03:16:57 PM PDT 23 72578576143 ps
T384 /workspace/coverage/default/38.rom_ctrl_alert_test.1457184175 Oct 04 03:08:33 PM PDT 23 Oct 04 03:08:50 PM PDT 23 7571165174 ps
T385 /workspace/coverage/default/31.rom_ctrl_stress_all.3673495398 Oct 04 03:10:00 PM PDT 23 Oct 04 03:10:32 PM PDT 23 686287335 ps
T386 /workspace/coverage/default/15.rom_ctrl_alert_test.59811144 Oct 04 03:11:01 PM PDT 23 Oct 04 03:11:07 PM PDT 23 499105794 ps
T387 /workspace/coverage/default/27.rom_ctrl_stress_all.2890873861 Oct 04 03:09:15 PM PDT 23 Oct 04 03:09:29 PM PDT 23 800370602 ps
T388 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1942268118 Oct 04 03:11:26 PM PDT 23 Oct 04 03:13:57 PM PDT 23 4642925310 ps
T389 /workspace/coverage/default/15.rom_ctrl_stress_all.531216406 Oct 04 03:08:34 PM PDT 23 Oct 04 03:08:57 PM PDT 23 19620514744 ps
T390 /workspace/coverage/default/34.rom_ctrl_stress_all.201169367 Oct 04 03:10:52 PM PDT 23 Oct 04 03:12:04 PM PDT 23 7122850063 ps
T391 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1955193551 Oct 04 03:09:25 PM PDT 23 Oct 04 03:11:15 PM PDT 23 7378509009 ps
T392 /workspace/coverage/default/4.rom_ctrl_smoke.1707316172 Oct 04 03:09:29 PM PDT 23 Oct 04 03:09:53 PM PDT 23 21376116078 ps
T393 /workspace/coverage/default/45.rom_ctrl_smoke.423598377 Oct 04 03:10:14 PM PDT 23 Oct 04 03:10:43 PM PDT 23 13606585185 ps
T394 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3101667955 Oct 04 03:12:12 PM PDT 23 Oct 04 03:12:19 PM PDT 23 177360770 ps
T395 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1376768759 Oct 04 03:09:21 PM PDT 23 Oct 04 03:09:35 PM PDT 23 582150531 ps
T396 /workspace/coverage/default/20.rom_ctrl_smoke.3908762989 Oct 04 03:08:53 PM PDT 23 Oct 04 03:09:15 PM PDT 23 16476080677 ps
T397 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3301967176 Oct 04 03:09:17 PM PDT 23 Oct 04 03:09:27 PM PDT 23 169160696 ps
T398 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4283546811 Oct 04 03:08:57 PM PDT 23 Oct 04 03:19:40 PM PDT 23 100664912654 ps
T399 /workspace/coverage/default/24.rom_ctrl_stress_all.3656794304 Oct 04 03:09:54 PM PDT 23 Oct 04 03:10:26 PM PDT 23 16522193842 ps
T400 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2750208747 Oct 04 03:13:12 PM PDT 23 Oct 04 03:13:26 PM PDT 23 6251111469 ps
T401 /workspace/coverage/default/28.rom_ctrl_smoke.3952445073 Oct 04 03:08:47 PM PDT 23 Oct 04 03:09:36 PM PDT 23 8397531337 ps
T402 /workspace/coverage/default/4.rom_ctrl_stress_all.4251056329 Oct 04 03:09:42 PM PDT 23 Oct 04 03:10:23 PM PDT 23 7163130572 ps
T403 /workspace/coverage/default/14.rom_ctrl_smoke.888061447 Oct 04 03:08:56 PM PDT 23 Oct 04 03:09:26 PM PDT 23 3506516604 ps
T404 /workspace/coverage/default/46.rom_ctrl_stress_all.2810013963 Oct 04 03:14:13 PM PDT 23 Oct 04 03:14:30 PM PDT 23 2401472649 ps
T405 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.650001941 Oct 04 03:13:48 PM PDT 23 Oct 04 03:16:53 PM PDT 23 40324488651 ps
T406 /workspace/coverage/default/36.rom_ctrl_smoke.3994531307 Oct 04 03:12:50 PM PDT 23 Oct 04 03:13:01 PM PDT 23 189495555 ps
T407 /workspace/coverage/default/49.rom_ctrl_stress_all.1001938636 Oct 04 03:08:57 PM PDT 23 Oct 04 03:09:43 PM PDT 23 40874440638 ps
T408 /workspace/coverage/default/28.rom_ctrl_stress_all.3719531284 Oct 04 03:08:53 PM PDT 23 Oct 04 03:09:37 PM PDT 23 4873562748 ps
T409 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1984017416 Oct 04 03:08:14 PM PDT 23 Oct 04 03:08:47 PM PDT 23 16137182236 ps
T410 /workspace/coverage/default/0.rom_ctrl_smoke.2536763742 Oct 04 03:07:57 PM PDT 23 Oct 04 03:08:35 PM PDT 23 7752690641 ps
T411 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4260347742 Oct 04 03:23:57 PM PDT 23 Oct 04 03:24:19 PM PDT 23 7881003017 ps
T412 /workspace/coverage/default/18.rom_ctrl_alert_test.1327724881 Oct 04 03:08:56 PM PDT 23 Oct 04 03:09:05 PM PDT 23 2895583584 ps
T413 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2590014975 Oct 04 03:13:04 PM PDT 23 Oct 04 03:13:15 PM PDT 23 197647901 ps
T414 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3608127045 Oct 04 03:14:14 PM PDT 23 Oct 04 03:16:26 PM PDT 23 6965925271 ps
T415 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3690668101 Oct 04 03:08:37 PM PDT 23 Oct 04 03:09:10 PM PDT 23 3961938119 ps
T416 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1396683874 Oct 04 03:15:01 PM PDT 23 Oct 04 03:18:21 PM PDT 23 152129518182 ps
T417 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3372834017 Oct 04 03:09:30 PM PDT 23 Oct 04 03:15:24 PM PDT 23 52368281829 ps
T418 /workspace/coverage/default/11.rom_ctrl_stress_all.3736687987 Oct 04 03:12:11 PM PDT 23 Oct 04 03:13:27 PM PDT 23 8752807697 ps
T419 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.861772554 Oct 04 03:08:45 PM PDT 23 Oct 04 03:09:12 PM PDT 23 11743296269 ps
T420 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1812645665 Oct 04 03:08:56 PM PDT 23 Oct 04 03:09:10 PM PDT 23 17778231282 ps
T421 /workspace/coverage/default/37.rom_ctrl_smoke.3099359095 Oct 04 03:09:10 PM PDT 23 Oct 04 03:09:41 PM PDT 23 5743637423 ps
T422 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3898555530 Oct 04 03:08:51 PM PDT 23 Oct 04 03:10:54 PM PDT 23 2348587790 ps
T423 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2833754634 Oct 04 03:10:29 PM PDT 23 Oct 04 03:10:45 PM PDT 23 6368344658 ps
T424 /workspace/coverage/default/42.rom_ctrl_smoke.787552092 Oct 04 03:08:41 PM PDT 23 Oct 04 03:09:10 PM PDT 23 3437419560 ps
T425 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2302054231 Oct 04 03:09:28 PM PDT 23 Oct 04 04:00:28 PM PDT 23 109017377114 ps
T426 /workspace/coverage/default/33.rom_ctrl_smoke.1228108491 Oct 04 03:12:13 PM PDT 23 Oct 04 03:12:24 PM PDT 23 374680353 ps
T112 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3636542610 Oct 04 03:08:44 PM PDT 23 Oct 04 03:58:49 PM PDT 23 296348238865 ps
T42 /workspace/coverage/default/1.rom_ctrl_sec_cm.4237417357 Oct 04 03:08:13 PM PDT 23 Oct 04 03:09:22 PM PDT 23 2041483778 ps
T427 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3724122105 Oct 04 03:09:01 PM PDT 23 Oct 04 03:09:19 PM PDT 23 1044985820 ps
T428 /workspace/coverage/default/12.rom_ctrl_stress_all.2282929720 Oct 04 03:09:03 PM PDT 23 Oct 04 03:10:02 PM PDT 23 23999728131 ps
T429 /workspace/coverage/default/27.rom_ctrl_smoke.2127502949 Oct 04 03:09:01 PM PDT 23 Oct 04 03:09:20 PM PDT 23 1118647706 ps
T430 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2739781382 Oct 04 03:10:04 PM PDT 23 Oct 04 03:17:52 PM PDT 23 14318573182 ps
T431 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.981689061 Oct 04 03:09:27 PM PDT 23 Oct 04 03:09:42 PM PDT 23 31834788825 ps
T432 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2630334846 Oct 04 01:19:41 PM PDT 23 Oct 04 01:21:23 PM PDT 23 1872853614 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.803854952 Oct 04 01:20:15 PM PDT 23 Oct 04 01:20:20 PM PDT 23 308533682 ps
T116 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2037193628 Oct 04 01:30:04 PM PDT 23 Oct 04 01:30:48 PM PDT 23 689450990 ps
T434 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1974165336 Oct 04 01:20:28 PM PDT 23 Oct 04 01:20:43 PM PDT 23 6146649451 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.591968673 Oct 04 01:30:39 PM PDT 23 Oct 04 01:30:44 PM PDT 23 88911797 ps
T436 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1312062465 Oct 04 01:17:57 PM PDT 23 Oct 04 01:18:10 PM PDT 23 5725760273 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4283459185 Oct 04 01:19:50 PM PDT 23 Oct 04 01:20:03 PM PDT 23 2409422109 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1293335803 Oct 04 01:22:54 PM PDT 23 Oct 04 01:23:08 PM PDT 23 5692984159 ps
T439 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1649831811 Oct 04 01:33:05 PM PDT 23 Oct 04 01:33:12 PM PDT 23 853426941 ps
T440 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.314257550 Oct 04 01:28:33 PM PDT 23 Oct 04 01:29:14 PM PDT 23 595326428 ps
T118 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.775998263 Oct 04 01:21:23 PM PDT 23 Oct 04 01:22:17 PM PDT 23 34622140485 ps
T441 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2570569519 Oct 04 01:28:35 PM PDT 23 Oct 04 01:29:22 PM PDT 23 1788246408 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3952725083 Oct 04 01:27:07 PM PDT 23 Oct 04 01:27:12 PM PDT 23 187824705 ps
T443 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.746761812 Oct 04 01:25:44 PM PDT 23 Oct 04 01:26:01 PM PDT 23 8484860598 ps
T444 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2398131976 Oct 04 01:19:48 PM PDT 23 Oct 04 01:20:05 PM PDT 23 7498385997 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1380091145 Oct 04 01:17:50 PM PDT 23 Oct 04 01:18:09 PM PDT 23 9176419756 ps
T446 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3976510164 Oct 04 01:22:46 PM PDT 23 Oct 04 01:23:04 PM PDT 23 7875691675 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2283678775 Oct 04 01:25:06 PM PDT 23 Oct 04 01:25:22 PM PDT 23 1195707826 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4030139167 Oct 04 01:20:07 PM PDT 23 Oct 04 01:20:28 PM PDT 23 2180456672 ps
T120 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2758425317 Oct 04 01:21:54 PM PDT 23 Oct 04 01:22:41 PM PDT 23 1433934622 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.75595337 Oct 04 01:26:08 PM PDT 23 Oct 04 01:29:01 PM PDT 23 45184912631 ps
T450 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2877859590 Oct 04 01:22:49 PM PDT 23 Oct 04 01:22:54 PM PDT 23 542060778 ps
T451 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3181909446 Oct 04 01:28:26 PM PDT 23 Oct 04 01:28:37 PM PDT 23 4827465696 ps
T452 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.990377150 Oct 04 01:17:51 PM PDT 23 Oct 04 01:18:05 PM PDT 23 5797565770 ps
T453 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1494341731 Oct 04 01:17:51 PM PDT 23 Oct 04 01:18:04 PM PDT 23 2753008477 ps
T454 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.288869006 Oct 04 01:17:45 PM PDT 23 Oct 04 01:18:03 PM PDT 23 1566324252 ps
T455 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2347914219 Oct 04 01:20:14 PM PDT 23 Oct 04 01:20:19 PM PDT 23 346722369 ps
T456 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.737995257 Oct 04 01:22:27 PM PDT 23 Oct 04 01:22:36 PM PDT 23 415707662 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3597198068 Oct 04 01:21:59 PM PDT 23 Oct 04 01:22:05 PM PDT 23 4138333946 ps
T458 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2632614691 Oct 04 01:33:56 PM PDT 23 Oct 04 01:34:02 PM PDT 23 88851148 ps
T459 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1887900219 Oct 04 01:20:05 PM PDT 23 Oct 04 01:20:17 PM PDT 23 12638953247 ps
T119 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3573458835 Oct 04 01:21:36 PM PDT 23 Oct 04 01:22:52 PM PDT 23 967777532 ps
T460 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3460807178 Oct 04 01:21:41 PM PDT 23 Oct 04 01:21:56 PM PDT 23 6650092013 ps
T461 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2091501005 Oct 04 01:25:25 PM PDT 23 Oct 04 01:30:16 PM PDT 23 32802106410 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1825557719 Oct 04 01:20:32 PM PDT 23 Oct 04 01:21:58 PM PDT 23 2001229929 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3851785657 Oct 04 01:18:05 PM PDT 23 Oct 04 01:18:11 PM PDT 23 346141285 ps
T464 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.412575526 Oct 04 01:19:12 PM PDT 23 Oct 04 01:19:30 PM PDT 23 7946526847 ps
T465 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2075769123 Oct 04 01:21:09 PM PDT 23 Oct 04 01:21:26 PM PDT 23 4020302859 ps
T466 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1971586681 Oct 04 01:18:12 PM PDT 23 Oct 04 01:19:05 PM PDT 23 3904838682 ps
T467 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1180379777 Oct 04 01:29:14 PM PDT 23 Oct 04 01:29:23 PM PDT 23 3402051754 ps
T468 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.476769645 Oct 04 01:29:16 PM PDT 23 Oct 04 01:29:33 PM PDT 23 17308445520 ps
T469 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3451441772 Oct 04 01:25:51 PM PDT 23 Oct 04 01:25:57 PM PDT 23 220417523 ps
T470 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2805810699 Oct 04 01:19:45 PM PDT 23 Oct 04 01:20:03 PM PDT 23 2212475376 ps
T471 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2542216159 Oct 04 01:19:58 PM PDT 23 Oct 04 01:20:11 PM PDT 23 17985849685 ps
T472 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3099653743 Oct 04 01:22:54 PM PDT 23 Oct 04 01:23:05 PM PDT 23 5716438290 ps
T473 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2327218472 Oct 04 01:23:03 PM PDT 23 Oct 04 01:23:10 PM PDT 23 314043270 ps
T474 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3056503482 Oct 04 01:31:51 PM PDT 23 Oct 04 01:31:59 PM PDT 23 1964749785 ps
T475 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1208970525 Oct 04 01:20:18 PM PDT 23 Oct 04 01:20:31 PM PDT 23 743346422 ps
T476 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1219045906 Oct 04 01:20:20 PM PDT 23 Oct 04 01:20:26 PM PDT 23 92252731 ps
T477 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1622240450 Oct 04 01:18:42 PM PDT 23 Oct 04 01:18:57 PM PDT 23 2747856359 ps
T478 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.963330315 Oct 04 01:22:46 PM PDT 23 Oct 04 01:23:03 PM PDT 23 7375508800 ps
T479 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3996462955 Oct 04 01:30:59 PM PDT 23 Oct 04 01:31:18 PM PDT 23 2237844357 ps
T480 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.100757596 Oct 04 01:18:42 PM PDT 23 Oct 04 01:19:02 PM PDT 23 2042681398 ps
T481 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3957036408 Oct 04 01:24:24 PM PDT 23 Oct 04 01:24:42 PM PDT 23 5189148289 ps
T117 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.676624303 Oct 04 01:20:52 PM PDT 23 Oct 04 01:22:06 PM PDT 23 627968145 ps
T482 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1931187008 Oct 04 01:18:10 PM PDT 23 Oct 04 01:19:34 PM PDT 23 4812122152 ps
T483 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1659317779 Oct 04 01:24:33 PM PDT 23 Oct 04 01:24:49 PM PDT 23 9923986575 ps
T484 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.260592541 Oct 04 01:25:39 PM PDT 23 Oct 04 01:26:58 PM PDT 23 11301327396 ps
T485 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1064623922 Oct 04 01:26:57 PM PDT 23 Oct 04 01:27:10 PM PDT 23 2558899683 ps

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.224683756
Short name T24
Test name
Test status
Simulation time 1364819074 ps
CPU time 10.13 seconds
Started Oct 04 01:22:13 PM PDT 23
Finished Oct 04 01:22:24 PM PDT 23
Peak memory 218872 kb
Host smart-7e820e93-e5f7-4aea-8058-d9d7e22150b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224683756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.224683756
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2933719512
Short name T6
Test name
Test status
Simulation time 61059581360 ps
CPU time 2570.07 seconds
Started Oct 04 03:09:18 PM PDT 23
Finished Oct 04 03:52:09 PM PDT 23
Peak memory 235808 kb
Host smart-04f446f1-1f1e-4143-bd6d-b5dd7bc858d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933719512 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2933719512
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.654649735
Short name T29
Test name
Test status
Simulation time 54366552812 ps
CPU time 193.65 seconds
Started Oct 04 01:17:57 PM PDT 23
Finished Oct 04 01:21:11 PM PDT 23
Peak memory 218884 kb
Host smart-60638724-1078-45ea-911d-2e45ecd6b669
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654649735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.654649735
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3759752840
Short name T58
Test name
Test status
Simulation time 7991368649 ps
CPU time 86.34 seconds
Started Oct 04 01:23:24 PM PDT 23
Finished Oct 04 01:24:56 PM PDT 23
Peak memory 218980 kb
Host smart-9a5c7110-e00f-4397-83ed-22a9e214de0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759752840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3759752840
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2187244749
Short name T20
Test name
Test status
Simulation time 5614391209 ps
CPU time 135.71 seconds
Started Oct 04 03:09:18 PM PDT 23
Finished Oct 04 03:11:34 PM PDT 23
Peak memory 237928 kb
Host smart-1bee974e-f2d3-4b99-b378-8d53af744ab7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187244749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2187244749
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4262032258
Short name T59
Test name
Test status
Simulation time 609468923 ps
CPU time 10.84 seconds
Started Oct 04 01:20:02 PM PDT 23
Finished Oct 04 01:20:13 PM PDT 23
Peak memory 219052 kb
Host smart-f3a0c962-b2a0-44c4-a7ae-ae1e1a11adb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262032258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4262032258
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1421375255
Short name T15
Test name
Test status
Simulation time 14121496596 ps
CPU time 46.95 seconds
Started Oct 04 03:08:49 PM PDT 23
Finished Oct 04 03:09:38 PM PDT 23
Peak memory 213388 kb
Host smart-32afce3c-2434-403a-aa83-25bfa9b521ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421375255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1421375255
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2758425317
Short name T120
Test name
Test status
Simulation time 1433934622 ps
CPU time 46.49 seconds
Started Oct 04 01:21:54 PM PDT 23
Finished Oct 04 01:22:41 PM PDT 23
Peak memory 211768 kb
Host smart-29b18291-cb15-4e7a-a683-36717f3b1cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758425317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2758425317
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.4237417357
Short name T42
Test name
Test status
Simulation time 2041483778 ps
CPU time 67.83 seconds
Started Oct 04 03:08:13 PM PDT 23
Finished Oct 04 03:09:22 PM PDT 23
Peak memory 235952 kb
Host smart-477ed1a3-e075-4465-b646-c6f3855184e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237417357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.4237417357
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1623853201
Short name T33
Test name
Test status
Simulation time 9159803333 ps
CPU time 87.05 seconds
Started Oct 04 01:27:03 PM PDT 23
Finished Oct 04 01:28:31 PM PDT 23
Peak memory 211360 kb
Host smart-1a508f94-5974-490c-b9e3-0fc9758635fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623853201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1623853201
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.572194019
Short name T57
Test name
Test status
Simulation time 940051107 ps
CPU time 13.7 seconds
Started Oct 04 01:20:23 PM PDT 23
Finished Oct 04 01:20:37 PM PDT 23
Peak memory 218896 kb
Host smart-2aa4fd55-e47a-49dc-80ed-ed8401d7d053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572194019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.572194019
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4100852338
Short name T2
Test name
Test status
Simulation time 8356260891 ps
CPU time 106.93 seconds
Started Oct 04 03:09:18 PM PDT 23
Finished Oct 04 03:11:06 PM PDT 23
Peak memory 237580 kb
Host smart-98b2bbee-9bb2-41f0-a59d-7d60cf80bdc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100852338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4100852338
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.676624303
Short name T117
Test name
Test status
Simulation time 627968145 ps
CPU time 74.03 seconds
Started Oct 04 01:20:52 PM PDT 23
Finished Oct 04 01:22:06 PM PDT 23
Peak memory 212908 kb
Host smart-c0c24c87-798e-49f1-be56-32b943b9832b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676624303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.676624303
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.235495013
Short name T181
Test name
Test status
Simulation time 7840498571 ps
CPU time 21.41 seconds
Started Oct 04 03:08:34 PM PDT 23
Finished Oct 04 03:08:56 PM PDT 23
Peak memory 212052 kb
Host smart-6a8b1dc7-29d1-4e7c-8490-18e1825c88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235495013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.235495013
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2269927410
Short name T199
Test name
Test status
Simulation time 340590746 ps
CPU time 9.89 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 211224 kb
Host smart-ff5e2f3e-0642-4eca-bc90-87b368d8ad86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269927410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2269927410
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.975915972
Short name T81
Test name
Test status
Simulation time 8752153290 ps
CPU time 11.76 seconds
Started Oct 04 01:27:27 PM PDT 23
Finished Oct 04 01:27:39 PM PDT 23
Peak memory 210736 kb
Host smart-95c3d06b-0789-46fe-b02f-b6a3b2916eba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975915972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.975915972
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2340409736
Short name T68
Test name
Test status
Simulation time 110466914683 ps
CPU time 382.97 seconds
Started Oct 04 01:19:49 PM PDT 23
Finished Oct 04 01:26:13 PM PDT 23
Peak memory 210712 kb
Host smart-99259fc9-4bea-4235-85b3-39bb26a5d0e8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340409736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2340409736
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2654787580
Short name T169
Test name
Test status
Simulation time 3219721903 ps
CPU time 13.57 seconds
Started Oct 04 03:10:07 PM PDT 23
Finished Oct 04 03:10:21 PM PDT 23
Peak memory 211088 kb
Host smart-6a79052f-9163-49d3-b7eb-28660b0bf548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654787580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2654787580
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.298443376
Short name T75
Test name
Test status
Simulation time 328995584 ps
CPU time 78.76 seconds
Started Oct 04 01:25:41 PM PDT 23
Finished Oct 04 01:27:01 PM PDT 23
Peak memory 212128 kb
Host smart-aaf0a571-10bc-45f4-a679-355132810a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298443376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.298443376
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.3636542610
Short name T112
Test name
Test status
Simulation time 296348238865 ps
CPU time 3003.43 seconds
Started Oct 04 03:08:44 PM PDT 23
Finished Oct 04 03:58:49 PM PDT 23
Peak memory 251700 kb
Host smart-2bd1d9e8-f60f-4823-a604-50e3b118ac52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636542610 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.3636542610
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2882617701
Short name T90
Test name
Test status
Simulation time 309794915 ps
CPU time 5.78 seconds
Started Oct 04 03:08:54 PM PDT 23
Finished Oct 04 03:09:00 PM PDT 23
Peak memory 210976 kb
Host smart-21ad06a8-3120-4b75-a4e6-3e536b1d3da1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2882617701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2882617701
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2190443194
Short name T12
Test name
Test status
Simulation time 405739946977 ps
CPU time 8223.82 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 05:26:04 PM PDT 23
Peak memory 236628 kb
Host smart-373bd565-71bc-448a-afa3-40f8c9fac46b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190443194 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2190443194
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.718892113
Short name T104
Test name
Test status
Simulation time 1280734648 ps
CPU time 11.85 seconds
Started Oct 04 01:17:36 PM PDT 23
Finished Oct 04 01:17:49 PM PDT 23
Peak memory 216900 kb
Host smart-beb7af38-4c41-431e-8b4f-006ccea3ec13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718892113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.718892113
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.42482395
Short name T85
Test name
Test status
Simulation time 1489860145 ps
CPU time 7.38 seconds
Started Oct 04 01:18:32 PM PDT 23
Finished Oct 04 01:18:40 PM PDT 23
Peak memory 210632 kb
Host smart-a8a831d1-03d7-457a-bc05-d5d2329adbfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42482395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_res
et.42482395
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3361894574
Short name T122
Test name
Test status
Simulation time 1890608080 ps
CPU time 15.66 seconds
Started Oct 04 01:20:57 PM PDT 23
Finished Oct 04 01:21:13 PM PDT 23
Peak memory 218896 kb
Host smart-98103c5b-c2e6-4b90-a5c8-80e770b7ec68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361894574 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3361894574
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3056503482
Short name T474
Test name
Test status
Simulation time 1964749785 ps
CPU time 7.13 seconds
Started Oct 04 01:31:51 PM PDT 23
Finished Oct 04 01:31:59 PM PDT 23
Peak memory 210728 kb
Host smart-96601241-0061-4130-ab1d-c02821b52406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056503482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3056503482
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2480838236
Short name T133
Test name
Test status
Simulation time 261710504 ps
CPU time 5.28 seconds
Started Oct 04 01:22:40 PM PDT 23
Finished Oct 04 01:22:45 PM PDT 23
Peak memory 210696 kb
Host smart-02d48923-8b1d-496a-a2b3-f0f65dab6245
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480838236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.2480838236
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3099653743
Short name T472
Test name
Test status
Simulation time 5716438290 ps
CPU time 11.15 seconds
Started Oct 04 01:22:54 PM PDT 23
Finished Oct 04 01:23:05 PM PDT 23
Peak memory 210760 kb
Host smart-52ffcd86-bff7-43e0-be4b-e1b858ea665c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099653743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.3099653743
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1661234826
Short name T82
Test name
Test status
Simulation time 44803222217 ps
CPU time 402.66 seconds
Started Oct 04 01:25:01 PM PDT 23
Finished Oct 04 01:31:46 PM PDT 23
Peak memory 219112 kb
Host smart-6f7186a6-a5ab-446b-952d-80e7d8db50a5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661234826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1661234826
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.671001328
Short name T142
Test name
Test status
Simulation time 1032543611 ps
CPU time 10.48 seconds
Started Oct 04 01:19:41 PM PDT 23
Finished Oct 04 01:19:52 PM PDT 23
Peak memory 217340 kb
Host smart-41386f7c-c4e3-4d93-bfd0-484dc2ce63aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671001328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.671001328
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1208970525
Short name T475
Test name
Test status
Simulation time 743346422 ps
CPU time 11.52 seconds
Started Oct 04 01:20:18 PM PDT 23
Finished Oct 04 01:20:31 PM PDT 23
Peak memory 219128 kb
Host smart-005d4cd8-0273-43e9-b54b-07f2b53691d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208970525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1208970525
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2944269575
Short name T134
Test name
Test status
Simulation time 5138107520 ps
CPU time 10.44 seconds
Started Oct 04 01:21:58 PM PDT 23
Finished Oct 04 01:22:09 PM PDT 23
Peak memory 210816 kb
Host smart-b52d3ea3-0811-4989-894c-c4d2b2e23d27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944269575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2944269575
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2327218472
Short name T473
Test name
Test status
Simulation time 314043270 ps
CPU time 6.54 seconds
Started Oct 04 01:23:03 PM PDT 23
Finished Oct 04 01:23:10 PM PDT 23
Peak memory 215896 kb
Host smart-5ba5a00f-2d8b-43bc-acd5-f486411830a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327218472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2327218472
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2680572353
Short name T67
Test name
Test status
Simulation time 8048985509 ps
CPU time 16.92 seconds
Started Oct 04 01:18:16 PM PDT 23
Finished Oct 04 01:18:34 PM PDT 23
Peak memory 210748 kb
Host smart-366096ee-f04f-427a-81a6-cc9c1f52f48d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680572353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2680572353
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1064623922
Short name T485
Test name
Test status
Simulation time 2558899683 ps
CPU time 12.43 seconds
Started Oct 04 01:26:57 PM PDT 23
Finished Oct 04 01:27:10 PM PDT 23
Peak memory 218996 kb
Host smart-73fb68f4-c528-4bc6-ba9c-68afadac5a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064623922 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1064623922
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1791929563
Short name T89
Test name
Test status
Simulation time 3503693035 ps
CPU time 11.84 seconds
Started Oct 04 01:22:56 PM PDT 23
Finished Oct 04 01:23:08 PM PDT 23
Peak memory 210724 kb
Host smart-d8082c70-5896-48ab-a808-23460362f959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791929563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1791929563
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.539614609
Short name T149
Test name
Test status
Simulation time 168665335 ps
CPU time 4.59 seconds
Started Oct 04 01:17:46 PM PDT 23
Finished Oct 04 01:17:51 PM PDT 23
Peak memory 210668 kb
Host smart-8afb00ce-be4c-4254-9dbb-34be7795a9ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539614609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.539614609
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1208468961
Short name T138
Test name
Test status
Simulation time 8437296013 ps
CPU time 15.2 seconds
Started Oct 04 01:25:09 PM PDT 23
Finished Oct 04 01:25:25 PM PDT 23
Peak memory 210732 kb
Host smart-5bcc969f-3670-4509-9ecd-ab6aaf4cc879
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208468961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1208468961
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1831866486
Short name T83
Test name
Test status
Simulation time 7780494554 ps
CPU time 100.45 seconds
Started Oct 04 01:18:44 PM PDT 23
Finished Oct 04 01:20:25 PM PDT 23
Peak memory 218972 kb
Host smart-c66a65f6-1c36-4827-a6fc-0ba2dcd059f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831866486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1831866486
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1659317779
Short name T483
Test name
Test status
Simulation time 9923986575 ps
CPU time 16.14 seconds
Started Oct 04 01:24:33 PM PDT 23
Finished Oct 04 01:24:49 PM PDT 23
Peak memory 217696 kb
Host smart-6ca51c0d-d909-435a-a4b0-9aa954403842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659317779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1659317779
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2009194572
Short name T63
Test name
Test status
Simulation time 309645342 ps
CPU time 6.71 seconds
Started Oct 04 01:21:08 PM PDT 23
Finished Oct 04 01:21:15 PM PDT 23
Peak memory 218908 kb
Host smart-5e85b0b3-0c52-46f0-aeb6-2cee7bfce8b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009194572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2009194572
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.775998263
Short name T118
Test name
Test status
Simulation time 34622140485 ps
CPU time 51.6 seconds
Started Oct 04 01:21:23 PM PDT 23
Finished Oct 04 01:22:17 PM PDT 23
Peak memory 219116 kb
Host smart-9040389e-87c9-4be1-8de9-eb1a9f534a24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775998263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.775998263
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.746761812
Short name T443
Test name
Test status
Simulation time 8484860598 ps
CPU time 17.07 seconds
Started Oct 04 01:25:44 PM PDT 23
Finished Oct 04 01:26:01 PM PDT 23
Peak memory 218868 kb
Host smart-5e960df8-c9a6-40a6-ba2a-fb74c988842b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746761812 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.746761812
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2877859590
Short name T450
Test name
Test status
Simulation time 542060778 ps
CPU time 4.99 seconds
Started Oct 04 01:22:49 PM PDT 23
Finished Oct 04 01:22:54 PM PDT 23
Peak memory 210624 kb
Host smart-b43e3042-5774-4908-b1bc-939e912c7031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877859590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2877859590
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1253072270
Short name T26
Test name
Test status
Simulation time 4224650437 ps
CPU time 16.78 seconds
Started Oct 04 01:17:55 PM PDT 23
Finished Oct 04 01:18:13 PM PDT 23
Peak memory 210704 kb
Host smart-06b708c8-5e67-47b8-ade3-f7cf78ca4834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253072270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1253072270
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3267523739
Short name T61
Test name
Test status
Simulation time 3376164986 ps
CPU time 13.25 seconds
Started Oct 04 01:20:18 PM PDT 23
Finished Oct 04 01:20:32 PM PDT 23
Peak memory 219012 kb
Host smart-8a3cae2a-8f6a-4938-8ba5-c290436af466
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267523739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3267523739
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2037193628
Short name T116
Test name
Test status
Simulation time 689450990 ps
CPU time 43.1 seconds
Started Oct 04 01:30:04 PM PDT 23
Finished Oct 04 01:30:48 PM PDT 23
Peak memory 211748 kb
Host smart-b6dadfc9-1e26-4ddd-b736-e9deefa3e4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037193628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2037193628
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.4237137471
Short name T113
Test name
Test status
Simulation time 2284842034 ps
CPU time 12 seconds
Started Oct 04 01:21:31 PM PDT 23
Finished Oct 04 01:21:43 PM PDT 23
Peak memory 218928 kb
Host smart-872881f0-e537-4550-83a5-2cf5ddb1eb13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237137471 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.4237137471
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1312062465
Short name T436
Test name
Test status
Simulation time 5725760273 ps
CPU time 12.48 seconds
Started Oct 04 01:17:57 PM PDT 23
Finished Oct 04 01:18:10 PM PDT 23
Peak memory 210684 kb
Host smart-1cac3725-aa13-4a62-b8e8-56d946d42187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312062465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1312062465
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.4129620506
Short name T40
Test name
Test status
Simulation time 107237118102 ps
CPU time 258.41 seconds
Started Oct 04 01:19:38 PM PDT 23
Finished Oct 04 01:23:57 PM PDT 23
Peak memory 210800 kb
Host smart-307e62e3-e57b-4a72-8d58-c6b1b7805d2a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129620506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.4129620506
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1974165336
Short name T434
Test name
Test status
Simulation time 6146649451 ps
CPU time 14.06 seconds
Started Oct 04 01:20:28 PM PDT 23
Finished Oct 04 01:20:43 PM PDT 23
Peak memory 210684 kb
Host smart-14ba5aad-46bf-4813-9974-bfd163dee1f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974165336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1974165336
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.593883561
Short name T131
Test name
Test status
Simulation time 2192439764 ps
CPU time 19.52 seconds
Started Oct 04 01:26:11 PM PDT 23
Finished Oct 04 01:26:31 PM PDT 23
Peak memory 218964 kb
Host smart-87d090f5-09a0-4b4f-8890-43f831ce3ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593883561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.593883561
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3462344562
Short name T114
Test name
Test status
Simulation time 1730085277 ps
CPU time 83.2 seconds
Started Oct 04 01:20:01 PM PDT 23
Finished Oct 04 01:21:25 PM PDT 23
Peak memory 219012 kb
Host smart-30ff78df-349c-417b-97c5-323c9d3a05be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462344562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3462344562
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4106783099
Short name T125
Test name
Test status
Simulation time 681074149 ps
CPU time 7.89 seconds
Started Oct 04 01:19:58 PM PDT 23
Finished Oct 04 01:20:06 PM PDT 23
Peak memory 210712 kb
Host smart-d324ae87-3297-4d11-900e-c06ce40735ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106783099 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4106783099
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1243433635
Short name T128
Test name
Test status
Simulation time 29623179076 ps
CPU time 16.09 seconds
Started Oct 04 01:18:10 PM PDT 23
Finished Oct 04 01:18:27 PM PDT 23
Peak memory 210680 kb
Host smart-5984f0ec-5c64-4a9b-8336-3072351d7df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243433635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1243433635
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2264683659
Short name T69
Test name
Test status
Simulation time 19633171878 ps
CPU time 241.49 seconds
Started Oct 04 01:25:26 PM PDT 23
Finished Oct 04 01:29:28 PM PDT 23
Peak memory 218880 kb
Host smart-a008b18f-ede4-4b65-bb42-53448f18bbf0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264683659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2264683659
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3851785657
Short name T463
Test name
Test status
Simulation time 346141285 ps
CPU time 5.55 seconds
Started Oct 04 01:18:05 PM PDT 23
Finished Oct 04 01:18:11 PM PDT 23
Peak memory 210708 kb
Host smart-7dd20fe4-8a4b-4e24-8c0e-b207e6eb5216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851785657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3851785657
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.3406114547
Short name T145
Test name
Test status
Simulation time 86481380 ps
CPU time 7.62 seconds
Started Oct 04 01:25:16 PM PDT 23
Finished Oct 04 01:25:24 PM PDT 23
Peak memory 218832 kb
Host smart-91208220-7a6c-4a61-8293-616979feabdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406114547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.3406114547
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1931187008
Short name T482
Test name
Test status
Simulation time 4812122152 ps
CPU time 83.6 seconds
Started Oct 04 01:18:10 PM PDT 23
Finished Oct 04 01:19:34 PM PDT 23
Peak memory 218968 kb
Host smart-3157a782-d013-41c5-b2d8-cb79c9eb9a13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931187008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1931187008
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2398131976
Short name T444
Test name
Test status
Simulation time 7498385997 ps
CPU time 17 seconds
Started Oct 04 01:19:48 PM PDT 23
Finished Oct 04 01:20:05 PM PDT 23
Peak memory 219148 kb
Host smart-6ae91db0-f62c-4a2e-a2c1-6f9ba6a02ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398131976 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2398131976
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3181909446
Short name T451
Test name
Test status
Simulation time 4827465696 ps
CPU time 10.96 seconds
Started Oct 04 01:28:26 PM PDT 23
Finished Oct 04 01:28:37 PM PDT 23
Peak memory 217484 kb
Host smart-7f954be1-d16f-4e0e-a2a6-3d81f75f0bb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181909446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3181909446
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2091501005
Short name T461
Test name
Test status
Simulation time 32802106410 ps
CPU time 290.47 seconds
Started Oct 04 01:25:25 PM PDT 23
Finished Oct 04 01:30:16 PM PDT 23
Peak memory 218976 kb
Host smart-c53b5223-2df8-444e-849a-5eb40fc516fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091501005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2091501005
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4059266397
Short name T146
Test name
Test status
Simulation time 18958360689 ps
CPU time 15.42 seconds
Started Oct 04 01:29:15 PM PDT 23
Finished Oct 04 01:29:31 PM PDT 23
Peak memory 210784 kb
Host smart-d98c9893-4a61-4360-97db-f5c16f256c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059266397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4059266397
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2283678775
Short name T447
Test name
Test status
Simulation time 1195707826 ps
CPU time 14.5 seconds
Started Oct 04 01:25:06 PM PDT 23
Finished Oct 04 01:25:22 PM PDT 23
Peak memory 218872 kb
Host smart-e7556212-809f-4584-8286-00524726f6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283678775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2283678775
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.618570583
Short name T55
Test name
Test status
Simulation time 297652654 ps
CPU time 39.64 seconds
Started Oct 04 01:26:08 PM PDT 23
Finished Oct 04 01:26:48 PM PDT 23
Peak memory 211916 kb
Host smart-fbaad0a1-8013-4779-ad32-ec2c4277da34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618570583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.618570583
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1293335803
Short name T438
Test name
Test status
Simulation time 5692984159 ps
CPU time 13.29 seconds
Started Oct 04 01:22:54 PM PDT 23
Finished Oct 04 01:23:08 PM PDT 23
Peak memory 219072 kb
Host smart-d1872c87-4964-43ed-a34b-79d95e9a2616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293335803 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1293335803
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.4219133197
Short name T66
Test name
Test status
Simulation time 1896486598 ps
CPU time 15.45 seconds
Started Oct 04 01:18:12 PM PDT 23
Finished Oct 04 01:18:28 PM PDT 23
Peak memory 217084 kb
Host smart-e1945c66-d2d7-46e4-bba0-703e8ac92e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219133197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.4219133197
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1971586681
Short name T466
Test name
Test status
Simulation time 3904838682 ps
CPU time 52.52 seconds
Started Oct 04 01:18:12 PM PDT 23
Finished Oct 04 01:19:05 PM PDT 23
Peak memory 210708 kb
Host smart-78c977d8-e7db-45d7-8cc0-fac4e15cab8d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971586681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1971586681
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2632614691
Short name T458
Test name
Test status
Simulation time 88851148 ps
CPU time 4.51 seconds
Started Oct 04 01:33:56 PM PDT 23
Finished Oct 04 01:34:02 PM PDT 23
Peak memory 210732 kb
Host smart-e481519b-bfb0-4bc1-bb56-b1f2e72cc657
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632614691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2632614691
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2669749735
Short name T137
Test name
Test status
Simulation time 584518241 ps
CPU time 8.06 seconds
Started Oct 04 01:20:51 PM PDT 23
Finished Oct 04 01:20:59 PM PDT 23
Peak memory 218876 kb
Host smart-c3f2fb6b-cc60-4eb4-924b-0033506a96a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669749735 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2669749735
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3460807178
Short name T460
Test name
Test status
Simulation time 6650092013 ps
CPU time 14.23 seconds
Started Oct 04 01:21:41 PM PDT 23
Finished Oct 04 01:21:56 PM PDT 23
Peak memory 217636 kb
Host smart-e3a1e5db-29a7-431e-b2bd-850de874abb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460807178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3460807178
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.694278866
Short name T73
Test name
Test status
Simulation time 189464315923 ps
CPU time 261.27 seconds
Started Oct 04 01:18:08 PM PDT 23
Finished Oct 04 01:22:30 PM PDT 23
Peak memory 210752 kb
Host smart-8e78f3a5-a9ca-40b6-bc25-095e7a5ff045
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694278866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.694278866
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2884159393
Short name T144
Test name
Test status
Simulation time 455077833 ps
CPU time 7.21 seconds
Started Oct 04 01:22:02 PM PDT 23
Finished Oct 04 01:22:10 PM PDT 23
Peak memory 210672 kb
Host smart-cd342433-7886-48dc-9259-82c5dceae049
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884159393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2884159393
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3573458835
Short name T119
Test name
Test status
Simulation time 967777532 ps
CPU time 76.34 seconds
Started Oct 04 01:21:36 PM PDT 23
Finished Oct 04 01:22:52 PM PDT 23
Peak memory 213220 kb
Host smart-bbbac131-a2d8-4429-9b4e-5ddb732619ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573458835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3573458835
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1180379777
Short name T467
Test name
Test status
Simulation time 3402051754 ps
CPU time 8.5 seconds
Started Oct 04 01:29:14 PM PDT 23
Finished Oct 04 01:29:23 PM PDT 23
Peak memory 210808 kb
Host smart-f2144fcc-b32b-4ab2-a217-1874e6a3284d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180379777 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1180379777
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1649831811
Short name T439
Test name
Test status
Simulation time 853426941 ps
CPU time 6.98 seconds
Started Oct 04 01:33:05 PM PDT 23
Finished Oct 04 01:33:12 PM PDT 23
Peak memory 210880 kb
Host smart-72b6c484-1e91-4ee8-9c9e-5d5384e3a8bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649831811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1649831811
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2485562382
Short name T70
Test name
Test status
Simulation time 24440261691 ps
CPU time 201.42 seconds
Started Oct 04 01:18:13 PM PDT 23
Finished Oct 04 01:21:35 PM PDT 23
Peak memory 218540 kb
Host smart-de6d9f92-39e1-45a1-949e-09155af7cd2f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485562382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2485562382
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.4045185573
Short name T60
Test name
Test status
Simulation time 3556092690 ps
CPU time 6.24 seconds
Started Oct 04 01:18:12 PM PDT 23
Finished Oct 04 01:18:19 PM PDT 23
Peak memory 210664 kb
Host smart-eede11a4-bb8b-498f-9c30-8c1c317449f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045185573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.4045185573
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1487613147
Short name T140
Test name
Test status
Simulation time 31370518459 ps
CPU time 17.9 seconds
Started Oct 04 01:22:42 PM PDT 23
Finished Oct 04 01:23:00 PM PDT 23
Peak memory 214892 kb
Host smart-3a9b672f-a348-480e-bc1a-a114846a45eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487613147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1487613147
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2254294043
Short name T62
Test name
Test status
Simulation time 304000387 ps
CPU time 40.05 seconds
Started Oct 04 01:18:13 PM PDT 23
Finished Oct 04 01:18:53 PM PDT 23
Peak memory 218804 kb
Host smart-0943a2f0-4b23-42ec-ac29-52b5097d33f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254294043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.2254294043
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.2805810699
Short name T470
Test name
Test status
Simulation time 2212475376 ps
CPU time 17.15 seconds
Started Oct 04 01:19:45 PM PDT 23
Finished Oct 04 01:20:03 PM PDT 23
Peak memory 218948 kb
Host smart-35ff353a-f034-4603-a288-81f04157f134
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805810699 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.2805810699
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1392608486
Short name T79
Test name
Test status
Simulation time 5576565173 ps
CPU time 9.6 seconds
Started Oct 04 01:24:23 PM PDT 23
Finished Oct 04 01:24:33 PM PDT 23
Peak memory 216268 kb
Host smart-16913a16-8a30-44fd-8133-d6eaebf02d4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392608486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1392608486
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1068842538
Short name T80
Test name
Test status
Simulation time 1721691337 ps
CPU time 6.01 seconds
Started Oct 04 01:18:15 PM PDT 23
Finished Oct 04 01:18:22 PM PDT 23
Peak memory 216576 kb
Host smart-f234ea5b-942d-4ee3-a16a-d1221c196654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068842538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1068842538
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3551811478
Short name T141
Test name
Test status
Simulation time 2286711671 ps
CPU time 13.19 seconds
Started Oct 04 01:38:12 PM PDT 23
Finished Oct 04 01:38:25 PM PDT 23
Peak memory 219020 kb
Host smart-5b7918e0-112e-496f-8043-3d7073fed81c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551811478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3551811478
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1709286836
Short name T76
Test name
Test status
Simulation time 2997513985 ps
CPU time 46.34 seconds
Started Oct 04 01:18:22 PM PDT 23
Finished Oct 04 01:19:09 PM PDT 23
Peak memory 211500 kb
Host smart-132961f8-849b-460f-91e7-33de6a3d2421
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709286836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1709286836
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1795201819
Short name T77
Test name
Test status
Simulation time 7398451503 ps
CPU time 16.23 seconds
Started Oct 04 01:18:27 PM PDT 23
Finished Oct 04 01:18:43 PM PDT 23
Peak memory 213844 kb
Host smart-50277bdb-fb40-4da6-98a6-1a3711b7b4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795201819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1795201819
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2310702262
Short name T132
Test name
Test status
Simulation time 347057281 ps
CPU time 4.18 seconds
Started Oct 04 01:21:36 PM PDT 23
Finished Oct 04 01:21:41 PM PDT 23
Peak memory 210640 kb
Host smart-da731096-13b2-4ad9-942d-daea5eafea15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310702262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2310702262
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3192570995
Short name T74
Test name
Test status
Simulation time 33651582384 ps
CPU time 161.01 seconds
Started Oct 04 01:24:49 PM PDT 23
Finished Oct 04 01:27:31 PM PDT 23
Peak memory 210780 kb
Host smart-e29352b1-cfec-4d00-ab4d-3dee583da36e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192570995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3192570995
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2028207487
Short name T143
Test name
Test status
Simulation time 1835022832 ps
CPU time 5.86 seconds
Started Oct 04 01:19:30 PM PDT 23
Finished Oct 04 01:19:36 PM PDT 23
Peak memory 210632 kb
Host smart-e3cdff70-ea69-49d0-8fc8-7c10fdcac233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028207487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2028207487
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4283459185
Short name T437
Test name
Test status
Simulation time 2409422109 ps
CPU time 12.29 seconds
Started Oct 04 01:19:50 PM PDT 23
Finished Oct 04 01:20:03 PM PDT 23
Peak memory 218956 kb
Host smart-4f6668ab-b410-4867-b77b-1cbb6d23e176
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283459185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4283459185
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.314257550
Short name T440
Test name
Test status
Simulation time 595326428 ps
CPU time 40.17 seconds
Started Oct 04 01:28:33 PM PDT 23
Finished Oct 04 01:29:14 PM PDT 23
Peak memory 212004 kb
Host smart-281b538a-f9af-4d07-baa3-eca9de05118b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314257550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.314257550
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3288265050
Short name T124
Test name
Test status
Simulation time 3980075317 ps
CPU time 11.55 seconds
Started Oct 04 01:22:27 PM PDT 23
Finished Oct 04 01:22:39 PM PDT 23
Peak memory 219088 kb
Host smart-400fced2-c3dc-4753-9601-8b8888eebb76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288265050 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3288265050
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3658186057
Short name T25
Test name
Test status
Simulation time 1237352273 ps
CPU time 11.74 seconds
Started Oct 04 01:18:34 PM PDT 23
Finished Oct 04 01:18:46 PM PDT 23
Peak memory 216976 kb
Host smart-e6f75999-510d-4577-99b9-df112343bd12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658186057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3658186057
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1789142270
Short name T72
Test name
Test status
Simulation time 1868608037 ps
CPU time 104.43 seconds
Started Oct 04 01:19:31 PM PDT 23
Finished Oct 04 01:21:16 PM PDT 23
Peak memory 210792 kb
Host smart-c0253271-ed4a-4d10-81e6-b34cc8a8c1c7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789142270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1789142270
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.50732563
Short name T136
Test name
Test status
Simulation time 5631091399 ps
CPU time 12.16 seconds
Started Oct 04 01:18:31 PM PDT 23
Finished Oct 04 01:18:44 PM PDT 23
Peak memory 210784 kb
Host smart-64123a40-96b9-4ad4-9c3f-ae92e40286cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50732563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ct
rl_same_csr_outstanding.50732563
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.591968673
Short name T435
Test name
Test status
Simulation time 88911797 ps
CPU time 4.52 seconds
Started Oct 04 01:30:39 PM PDT 23
Finished Oct 04 01:30:44 PM PDT 23
Peak memory 210760 kb
Host smart-8a198243-eb1f-4020-a621-9dfbb7fc8562
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591968673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.591968673
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2318673632
Short name T148
Test name
Test status
Simulation time 1202406377 ps
CPU time 6.82 seconds
Started Oct 04 01:18:11 PM PDT 23
Finished Oct 04 01:18:19 PM PDT 23
Peak memory 210636 kb
Host smart-3508a670-5711-434b-b3ee-f949d59c7df9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318673632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2318673632
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1525022665
Short name T129
Test name
Test status
Simulation time 8142961749 ps
CPU time 18.01 seconds
Started Oct 04 01:24:10 PM PDT 23
Finished Oct 04 01:24:28 PM PDT 23
Peak memory 218608 kb
Host smart-2b1eb387-44b5-4e0e-b75f-00f690bef082
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525022665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1525022665
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.556827678
Short name T123
Test name
Test status
Simulation time 3884557582 ps
CPU time 8.51 seconds
Started Oct 04 01:18:44 PM PDT 23
Finished Oct 04 01:18:53 PM PDT 23
Peak memory 213888 kb
Host smart-8960a37d-855e-492c-acff-73648e604011
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556827678 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.556827678
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2827699889
Short name T86
Test name
Test status
Simulation time 11036429041 ps
CPU time 10.79 seconds
Started Oct 04 01:18:50 PM PDT 23
Finished Oct 04 01:19:01 PM PDT 23
Peak memory 210764 kb
Host smart-dd4f2b42-4469-432e-ad9f-350f1d5b74e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827699889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2827699889
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3612688046
Short name T28
Test name
Test status
Simulation time 10872797694 ps
CPU time 13.24 seconds
Started Oct 04 01:25:24 PM PDT 23
Finished Oct 04 01:25:38 PM PDT 23
Peak memory 210692 kb
Host smart-be738962-c640-4baa-87df-bc5cc05470c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612688046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3612688046
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1865980628
Short name T135
Test name
Test status
Simulation time 1426549006 ps
CPU time 12.6 seconds
Started Oct 04 01:21:58 PM PDT 23
Finished Oct 04 01:22:11 PM PDT 23
Peak memory 210652 kb
Host smart-348cbade-2336-4e52-a887-14de8831b1b1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865980628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1865980628
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.75595337
Short name T449
Test name
Test status
Simulation time 45184912631 ps
CPU time 173.1 seconds
Started Oct 04 01:26:08 PM PDT 23
Finished Oct 04 01:29:01 PM PDT 23
Peak memory 210776 kb
Host smart-27a70055-e83f-4974-93be-6558c9f7a722
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75595337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.75595337
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1622240450
Short name T477
Test name
Test status
Simulation time 2747856359 ps
CPU time 13.85 seconds
Started Oct 04 01:18:42 PM PDT 23
Finished Oct 04 01:18:57 PM PDT 23
Peak memory 218724 kb
Host smart-d19a03a4-e5be-4293-a85a-84964574c0ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622240450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1622240450
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.288869006
Short name T454
Test name
Test status
Simulation time 1566324252 ps
CPU time 17.55 seconds
Started Oct 04 01:17:45 PM PDT 23
Finished Oct 04 01:18:03 PM PDT 23
Peak memory 218856 kb
Host smart-43a4dad6-044e-45d0-8824-510c1e6b7e52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288869006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.288869006
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.687478089
Short name T78
Test name
Test status
Simulation time 5501978222 ps
CPU time 47.3 seconds
Started Oct 04 01:21:29 PM PDT 23
Finished Oct 04 01:22:17 PM PDT 23
Peak memory 218940 kb
Host smart-d3ba5c09-762c-408b-8260-1143395ffa7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687478089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.687478089
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1380091145
Short name T445
Test name
Test status
Simulation time 9176419756 ps
CPU time 16.9 seconds
Started Oct 04 01:17:50 PM PDT 23
Finished Oct 04 01:18:09 PM PDT 23
Peak memory 210804 kb
Host smart-a1dd7f24-f578-4547-9da5-58aae1a627e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380091145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1380091145
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2347914219
Short name T455
Test name
Test status
Simulation time 346722369 ps
CPU time 4.7 seconds
Started Oct 04 01:20:14 PM PDT 23
Finished Oct 04 01:20:19 PM PDT 23
Peak memory 210800 kb
Host smart-8610169e-b455-4c3d-98ee-d2e6acc990c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347914219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2347914219
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3996462955
Short name T479
Test name
Test status
Simulation time 2237844357 ps
CPU time 18.89 seconds
Started Oct 04 01:30:59 PM PDT 23
Finished Oct 04 01:31:18 PM PDT 23
Peak memory 210756 kb
Host smart-b04e96a3-2a3f-41e8-9d1d-c0b2a513f951
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996462955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3996462955
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1080993999
Short name T121
Test name
Test status
Simulation time 3087436877 ps
CPU time 13.9 seconds
Started Oct 04 01:31:53 PM PDT 23
Finished Oct 04 01:32:10 PM PDT 23
Peak memory 218980 kb
Host smart-c6d35224-c93d-4c20-9d4c-87409e3b7cea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080993999 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1080993999
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1494341731
Short name T453
Test name
Test status
Simulation time 2753008477 ps
CPU time 12.45 seconds
Started Oct 04 01:17:51 PM PDT 23
Finished Oct 04 01:18:04 PM PDT 23
Peak memory 217076 kb
Host smart-6edc4749-ab39-4402-9818-6dba35cfb37d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494341731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1494341731
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3597198068
Short name T457
Test name
Test status
Simulation time 4138333946 ps
CPU time 6.25 seconds
Started Oct 04 01:21:59 PM PDT 23
Finished Oct 04 01:22:05 PM PDT 23
Peak memory 210716 kb
Host smart-17605bdf-65b5-4573-9343-c1477c9e9184
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597198068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3597198068
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.412575526
Short name T464
Test name
Test status
Simulation time 7946526847 ps
CPU time 15.5 seconds
Started Oct 04 01:19:12 PM PDT 23
Finished Oct 04 01:19:30 PM PDT 23
Peak memory 210688 kb
Host smart-6597e89a-675f-43fc-a47b-5d4f243eecd5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412575526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
412575526
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2686530866
Short name T64
Test name
Test status
Simulation time 3641583419 ps
CPU time 10.31 seconds
Started Oct 04 01:23:43 PM PDT 23
Finished Oct 04 01:23:55 PM PDT 23
Peak memory 210676 kb
Host smart-98d59822-d193-41a1-82cd-bbd476f8179f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686530866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2686530866
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.998247694
Short name T126
Test name
Test status
Simulation time 4548898932 ps
CPU time 17 seconds
Started Oct 04 01:23:01 PM PDT 23
Finished Oct 04 01:23:19 PM PDT 23
Peak memory 219180 kb
Host smart-8b4d1e48-da2d-47db-beec-33612795adf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998247694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.998247694
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1825557719
Short name T462
Test name
Test status
Simulation time 2001229929 ps
CPU time 84.9 seconds
Started Oct 04 01:20:32 PM PDT 23
Finished Oct 04 01:21:58 PM PDT 23
Peak memory 218900 kb
Host smart-63740e9f-8bee-4a31-840d-f2b4c73a1e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825557719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1825557719
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2075769123
Short name T465
Test name
Test status
Simulation time 4020302859 ps
CPU time 15.77 seconds
Started Oct 04 01:21:09 PM PDT 23
Finished Oct 04 01:21:26 PM PDT 23
Peak memory 217316 kb
Host smart-d91e4393-430b-4459-b7d3-a7e0f9cef58a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075769123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2075769123
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.803854952
Short name T433
Test name
Test status
Simulation time 308533682 ps
CPU time 4.79 seconds
Started Oct 04 01:20:15 PM PDT 23
Finished Oct 04 01:20:20 PM PDT 23
Peak memory 216456 kb
Host smart-b905bf18-92a2-4248-b1eb-895dbcfb02ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803854952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.803854952
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4030139167
Short name T448
Test name
Test status
Simulation time 2180456672 ps
CPU time 20.67 seconds
Started Oct 04 01:20:07 PM PDT 23
Finished Oct 04 01:20:28 PM PDT 23
Peak memory 210808 kb
Host smart-339ae4d7-e93c-4575-a929-533fe8e546da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030139167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4030139167
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3926920647
Short name T32
Test name
Test status
Simulation time 340553596 ps
CPU time 4.42 seconds
Started Oct 04 01:25:49 PM PDT 23
Finished Oct 04 01:25:54 PM PDT 23
Peak memory 211332 kb
Host smart-73174c14-0b76-4a52-9c59-7f7c43e5fb3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926920647 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3926920647
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2199678464
Short name T65
Test name
Test status
Simulation time 2250146015 ps
CPU time 10.86 seconds
Started Oct 04 01:18:40 PM PDT 23
Finished Oct 04 01:18:52 PM PDT 23
Peak memory 210724 kb
Host smart-44994911-1a96-4089-a56c-d861c7ca3d76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199678464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2199678464
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3927280250
Short name T31
Test name
Test status
Simulation time 645711567 ps
CPU time 8.46 seconds
Started Oct 04 01:20:06 PM PDT 23
Finished Oct 04 01:20:15 PM PDT 23
Peak memory 210728 kb
Host smart-8c77c856-626f-4599-804b-8e75e0127ab5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927280250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3927280250
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1555105808
Short name T130
Test name
Test status
Simulation time 1402537660 ps
CPU time 8.36 seconds
Started Oct 04 01:28:13 PM PDT 23
Finished Oct 04 01:28:22 PM PDT 23
Peak memory 210624 kb
Host smart-3ba33b64-d0cd-41f9-9223-374cd652afb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555105808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1555105808
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1529098449
Short name T30
Test name
Test status
Simulation time 7442289156 ps
CPU time 100.92 seconds
Started Oct 04 01:17:51 PM PDT 23
Finished Oct 04 01:19:33 PM PDT 23
Peak memory 219112 kb
Host smart-9b68f82e-1618-4590-8b5c-df7af73bc3a1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529098449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1529098449
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1784002954
Short name T105
Test name
Test status
Simulation time 2076558091 ps
CPU time 16.52 seconds
Started Oct 04 01:23:42 PM PDT 23
Finished Oct 04 01:23:59 PM PDT 23
Peak memory 217408 kb
Host smart-2cbde009-9517-4875-8b2f-2380f8e4adf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784002954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1784002954
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.100757596
Short name T480
Test name
Test status
Simulation time 2042681398 ps
CPU time 19.21 seconds
Started Oct 04 01:18:42 PM PDT 23
Finished Oct 04 01:19:02 PM PDT 23
Peak memory 218848 kb
Host smart-db782d21-5ef6-4b7f-9dd3-213434812104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100757596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.100757596
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.838331839
Short name T115
Test name
Test status
Simulation time 847276302 ps
CPU time 39.75 seconds
Started Oct 04 01:26:24 PM PDT 23
Finished Oct 04 01:27:04 PM PDT 23
Peak memory 211860 kb
Host smart-c6774260-0ccd-41f4-9742-0546b49ab757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838331839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.838331839
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3952725083
Short name T442
Test name
Test status
Simulation time 187824705 ps
CPU time 5.15 seconds
Started Oct 04 01:27:07 PM PDT 23
Finished Oct 04 01:27:12 PM PDT 23
Peak memory 219000 kb
Host smart-35d54067-e0ea-4459-9681-d9311a778b5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952725083 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3952725083
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2493749348
Short name T106
Test name
Test status
Simulation time 8169742268 ps
CPU time 15.09 seconds
Started Oct 04 01:25:40 PM PDT 23
Finished Oct 04 01:25:56 PM PDT 23
Peak memory 217420 kb
Host smart-29e8831c-1b8b-487f-8f59-289e24ddc869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493749348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2493749348
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.896187649
Short name T84
Test name
Test status
Simulation time 26277634654 ps
CPU time 140.79 seconds
Started Oct 04 01:25:30 PM PDT 23
Finished Oct 04 01:27:51 PM PDT 23
Peak memory 210708 kb
Host smart-5f1b2824-35b3-4660-bf89-6b124919e0d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896187649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.896187649
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.476769645
Short name T468
Test name
Test status
Simulation time 17308445520 ps
CPU time 15.93 seconds
Started Oct 04 01:29:16 PM PDT 23
Finished Oct 04 01:29:33 PM PDT 23
Peak memory 210884 kb
Host smart-7ad95dd1-dabd-4761-b623-15fa3764d133
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476769645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.476769645
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.963330315
Short name T478
Test name
Test status
Simulation time 7375508800 ps
CPU time 16.68 seconds
Started Oct 04 01:22:46 PM PDT 23
Finished Oct 04 01:23:03 PM PDT 23
Peak memory 218912 kb
Host smart-35470637-4474-4c74-a83e-3d4e24fc999d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963330315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.963330315
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.260592541
Short name T484
Test name
Test status
Simulation time 11301327396 ps
CPU time 78.67 seconds
Started Oct 04 01:25:39 PM PDT 23
Finished Oct 04 01:26:58 PM PDT 23
Peak memory 211308 kb
Host smart-4c48e18a-7d8c-4f2c-8901-d7cf14a782f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260592541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.260592541
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2381460541
Short name T147
Test name
Test status
Simulation time 334551888 ps
CPU time 4.86 seconds
Started Oct 04 01:21:29 PM PDT 23
Finished Oct 04 01:21:35 PM PDT 23
Peak memory 212804 kb
Host smart-ea351ecb-b183-4639-a85a-4cda3ea0b76b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381460541 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2381460541
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2005096488
Short name T108
Test name
Test status
Simulation time 2882339090 ps
CPU time 15.01 seconds
Started Oct 04 01:24:23 PM PDT 23
Finished Oct 04 01:24:38 PM PDT 23
Peak memory 217044 kb
Host smart-f9ec8003-ca59-4b3e-bbdb-42cbc3c61e5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005096488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2005096488
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.350843529
Short name T71
Test name
Test status
Simulation time 122761229849 ps
CPU time 305.32 seconds
Started Oct 04 01:25:31 PM PDT 23
Finished Oct 04 01:30:37 PM PDT 23
Peak memory 210712 kb
Host smart-6a5958e0-9ea6-4f35-a9ba-e3fffb9c41de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350843529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.350843529
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1821586701
Short name T150
Test name
Test status
Simulation time 298216348 ps
CPU time 6.44 seconds
Started Oct 04 01:25:51 PM PDT 23
Finished Oct 04 01:25:57 PM PDT 23
Peak memory 210636 kb
Host smart-cecf93ca-3b95-4efd-8624-560ba76c3c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821586701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1821586701
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3714945947
Short name T54
Test name
Test status
Simulation time 4649551812 ps
CPU time 12.07 seconds
Started Oct 04 01:23:56 PM PDT 23
Finished Oct 04 01:24:09 PM PDT 23
Peak memory 219020 kb
Host smart-bfae699e-14f9-4227-b08e-65fb47d3faf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714945947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.3714945947
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1219045906
Short name T476
Test name
Test status
Simulation time 92252731 ps
CPU time 4.98 seconds
Started Oct 04 01:20:20 PM PDT 23
Finished Oct 04 01:20:26 PM PDT 23
Peak memory 213872 kb
Host smart-8d0d57be-6191-46e0-a2f2-8fd55536a0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219045906 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1219045906
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3451441772
Short name T469
Test name
Test status
Simulation time 220417523 ps
CPU time 5.8 seconds
Started Oct 04 01:25:51 PM PDT 23
Finished Oct 04 01:25:57 PM PDT 23
Peak memory 215628 kb
Host smart-eab725b3-8414-40f3-92ba-59e1e7fa39e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451441772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3451441772
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3075351484
Short name T88
Test name
Test status
Simulation time 96911129586 ps
CPU time 201.68 seconds
Started Oct 04 01:20:56 PM PDT 23
Finished Oct 04 01:24:18 PM PDT 23
Peak memory 218868 kb
Host smart-36054300-c1e1-4dbc-b277-a3140a9eeb43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075351484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3075351484
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.533848835
Short name T107
Test name
Test status
Simulation time 390367899 ps
CPU time 5.11 seconds
Started Oct 04 01:25:11 PM PDT 23
Finished Oct 04 01:25:17 PM PDT 23
Peak memory 210592 kb
Host smart-c59bd365-ecae-49cc-acb5-e6220239ee47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533848835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.533848835
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.737995257
Short name T456
Test name
Test status
Simulation time 415707662 ps
CPU time 8.77 seconds
Started Oct 04 01:22:27 PM PDT 23
Finished Oct 04 01:22:36 PM PDT 23
Peak memory 218972 kb
Host smart-c6c20cf8-b8d3-426c-8697-6d83ed9f18cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737995257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.737995257
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2126011352
Short name T27
Test name
Test status
Simulation time 1152050697 ps
CPU time 44.79 seconds
Started Oct 04 01:22:08 PM PDT 23
Finished Oct 04 01:22:54 PM PDT 23
Peak memory 211564 kb
Host smart-bbf7e2cc-48e2-4196-a531-9f8744768b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126011352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2126011352
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.990377150
Short name T452
Test name
Test status
Simulation time 5797565770 ps
CPU time 13.08 seconds
Started Oct 04 01:17:51 PM PDT 23
Finished Oct 04 01:18:05 PM PDT 23
Peak memory 219156 kb
Host smart-60a26697-341a-4f10-9a04-27502c251ee0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990377150 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.990377150
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3957036408
Short name T481
Test name
Test status
Simulation time 5189148289 ps
CPU time 16.57 seconds
Started Oct 04 01:24:24 PM PDT 23
Finished Oct 04 01:24:42 PM PDT 23
Peak memory 210804 kb
Host smart-a7d18890-ff53-4aa3-938d-cf5e51769dda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957036408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3957036408
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2630334846
Short name T432
Test name
Test status
Simulation time 1872853614 ps
CPU time 101.74 seconds
Started Oct 04 01:19:41 PM PDT 23
Finished Oct 04 01:21:23 PM PDT 23
Peak memory 210652 kb
Host smart-fd012d9e-8439-4dfc-93a2-c18c6e5fc315
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630334846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2630334846
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2542216159
Short name T471
Test name
Test status
Simulation time 17985849685 ps
CPU time 13.36 seconds
Started Oct 04 01:19:58 PM PDT 23
Finished Oct 04 01:20:11 PM PDT 23
Peak memory 217988 kb
Host smart-652b917f-24d5-4021-afd5-3d27a774440b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542216159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2542216159
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.250313021
Short name T127
Test name
Test status
Simulation time 11658997520 ps
CPU time 17.52 seconds
Started Oct 04 01:21:57 PM PDT 23
Finished Oct 04 01:22:15 PM PDT 23
Peak memory 218956 kb
Host smart-9e5fd536-f0ad-4e83-b03e-7ccf61bfe5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250313021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.250313021
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3976510164
Short name T446
Test name
Test status
Simulation time 7875691675 ps
CPU time 16.9 seconds
Started Oct 04 01:22:46 PM PDT 23
Finished Oct 04 01:23:04 PM PDT 23
Peak memory 213572 kb
Host smart-9e15c491-8f53-4e3f-9ed4-fabfe8c6311c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976510164 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3976510164
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2426386773
Short name T139
Test name
Test status
Simulation time 1505126649 ps
CPU time 13.45 seconds
Started Oct 04 01:19:36 PM PDT 23
Finished Oct 04 01:19:50 PM PDT 23
Peak memory 216996 kb
Host smart-1aee6c78-8277-49ea-8136-15b01c702be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426386773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2426386773
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3833792182
Short name T87
Test name
Test status
Simulation time 19936584471 ps
CPU time 185.79 seconds
Started Oct 04 01:19:20 PM PDT 23
Finished Oct 04 01:22:28 PM PDT 23
Peak memory 218876 kb
Host smart-00cdb0c4-391c-483c-91a5-f840ca0cb661
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833792182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3833792182
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1887900219
Short name T459
Test name
Test status
Simulation time 12638953247 ps
CPU time 11.44 seconds
Started Oct 04 01:20:05 PM PDT 23
Finished Oct 04 01:20:17 PM PDT 23
Peak memory 217480 kb
Host smart-30ef586b-db78-4995-af87-94c6702541d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887900219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1887900219
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.926591916
Short name T56
Test name
Test status
Simulation time 2085158112 ps
CPU time 18.22 seconds
Started Oct 04 01:23:53 PM PDT 23
Finished Oct 04 01:24:12 PM PDT 23
Peak memory 218920 kb
Host smart-6725e3d7-c424-44a0-a072-23dcef5ee650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926591916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.926591916
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2570569519
Short name T441
Test name
Test status
Simulation time 1788246408 ps
CPU time 46.22 seconds
Started Oct 04 01:28:35 PM PDT 23
Finished Oct 04 01:29:22 PM PDT 23
Peak memory 211928 kb
Host smart-5dd57658-ebad-4fe0-a783-7633b6408e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570569519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2570569519
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.185853648
Short name T193
Test name
Test status
Simulation time 10624125865 ps
CPU time 11.16 seconds
Started Oct 04 03:07:48 PM PDT 23
Finished Oct 04 03:08:00 PM PDT 23
Peak memory 211136 kb
Host smart-d7330bfe-ebb4-452c-9339-3cb3c525d05a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185853648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.185853648
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1603036471
Short name T315
Test name
Test status
Simulation time 26553059022 ps
CPU time 150.87 seconds
Started Oct 04 03:09:20 PM PDT 23
Finished Oct 04 03:11:52 PM PDT 23
Peak memory 237264 kb
Host smart-cdad6708-2b26-4b07-9a9f-9062205cffde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603036471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1603036471
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3619874424
Short name T232
Test name
Test status
Simulation time 4568773112 ps
CPU time 21.65 seconds
Started Oct 04 03:10:06 PM PDT 23
Finished Oct 04 03:10:28 PM PDT 23
Peak memory 213560 kb
Host smart-136b32ad-0ef6-4bbc-b274-71c67f9cc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619874424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3619874424
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1604851772
Short name T344
Test name
Test status
Simulation time 1056771490 ps
CPU time 11.47 seconds
Started Oct 04 03:09:09 PM PDT 23
Finished Oct 04 03:09:21 PM PDT 23
Peak memory 211096 kb
Host smart-d416faea-3b00-4127-9cce-b81d2983ed75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604851772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1604851772
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2726033671
Short name T41
Test name
Test status
Simulation time 695460433 ps
CPU time 58.15 seconds
Started Oct 04 03:10:47 PM PDT 23
Finished Oct 04 03:11:46 PM PDT 23
Peak memory 237012 kb
Host smart-1afdaa2d-d808-4a0a-b947-3c8a66be4279
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726033671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2726033671
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2536763742
Short name T410
Test name
Test status
Simulation time 7752690641 ps
CPU time 37.68 seconds
Started Oct 04 03:07:57 PM PDT 23
Finished Oct 04 03:08:35 PM PDT 23
Peak memory 212724 kb
Host smart-62bfa8c0-609d-49f4-9427-80c640f7686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536763742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2536763742
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2290557676
Short name T282
Test name
Test status
Simulation time 22369481311 ps
CPU time 36.87 seconds
Started Oct 04 03:08:42 PM PDT 23
Finished Oct 04 03:09:19 PM PDT 23
Peak memory 215528 kb
Host smart-1926551c-5f68-473a-a645-8cef1733bdb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290557676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2290557676
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2921757402
Short name T330
Test name
Test status
Simulation time 151312834072 ps
CPU time 1437.14 seconds
Started Oct 04 03:08:34 PM PDT 23
Finished Oct 04 03:32:32 PM PDT 23
Peak memory 235920 kb
Host smart-bff9426f-820d-4081-bf29-48b549e7dd94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921757402 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2921757402
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2750627295
Short name T328
Test name
Test status
Simulation time 89070008 ps
CPU time 4.33 seconds
Started Oct 04 03:10:05 PM PDT 23
Finished Oct 04 03:10:10 PM PDT 23
Peak memory 211000 kb
Host smart-9ef0457f-c5d2-4aac-abb4-0ed003bfb402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750627295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2750627295
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2325882401
Short name T165
Test name
Test status
Simulation time 6267534883 ps
CPU time 127.78 seconds
Started Oct 04 03:14:54 PM PDT 23
Finished Oct 04 03:17:02 PM PDT 23
Peak memory 237696 kb
Host smart-3bb8e74a-0164-4684-bee6-0727aedd4d04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325882401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2325882401
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4095422919
Short name T340
Test name
Test status
Simulation time 5059888191 ps
CPU time 17.94 seconds
Started Oct 04 03:09:03 PM PDT 23
Finished Oct 04 03:09:22 PM PDT 23
Peak memory 213944 kb
Host smart-674dde52-7a7b-43ef-aca9-87a110c9b51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095422919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4095422919
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3986063682
Short name T168
Test name
Test status
Simulation time 372849140 ps
CPU time 5.58 seconds
Started Oct 04 03:09:51 PM PDT 23
Finished Oct 04 03:09:57 PM PDT 23
Peak memory 211052 kb
Host smart-f986b48f-ce0b-4374-a390-1006a7e6a217
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3986063682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3986063682
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1683655818
Short name T382
Test name
Test status
Simulation time 25894053967 ps
CPU time 31.84 seconds
Started Oct 04 03:08:49 PM PDT 23
Finished Oct 04 03:09:23 PM PDT 23
Peak memory 213480 kb
Host smart-532bf964-bd49-47e9-9929-65966113ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683655818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1683655818
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.361520855
Short name T310
Test name
Test status
Simulation time 14173992919 ps
CPU time 85.08 seconds
Started Oct 04 03:10:11 PM PDT 23
Finished Oct 04 03:11:36 PM PDT 23
Peak memory 216652 kb
Host smart-0e1cedfd-4a4c-4c51-b3f0-4b2831015cad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361520855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.361520855
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.879561530
Short name T209
Test name
Test status
Simulation time 85673864 ps
CPU time 4.38 seconds
Started Oct 04 03:09:18 PM PDT 23
Finished Oct 04 03:09:23 PM PDT 23
Peak memory 211068 kb
Host smart-2393d6c8-d8c7-4565-bc89-757d1d0f2122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879561530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.879561530
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3356307502
Short name T53
Test name
Test status
Simulation time 5339598179 ps
CPU time 166.49 seconds
Started Oct 04 03:08:12 PM PDT 23
Finished Oct 04 03:10:59 PM PDT 23
Peak memory 237640 kb
Host smart-5f999e47-8469-45d4-82d4-a5b7b9b41fb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356307502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3356307502
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2906312111
Short name T289
Test name
Test status
Simulation time 6169890140 ps
CPU time 15.26 seconds
Started Oct 04 03:08:51 PM PDT 23
Finished Oct 04 03:09:07 PM PDT 23
Peak memory 211188 kb
Host smart-32ecedb9-e233-45f1-9220-c86e90a1ab3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906312111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2906312111
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.4065952005
Short name T198
Test name
Test status
Simulation time 184536374 ps
CPU time 10.19 seconds
Started Oct 04 03:09:45 PM PDT 23
Finished Oct 04 03:09:56 PM PDT 23
Peak memory 212320 kb
Host smart-a2eb8567-c02b-465c-a011-42e8cb0ad687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065952005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.4065952005
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3211687787
Short name T375
Test name
Test status
Simulation time 6289567273 ps
CPU time 34.84 seconds
Started Oct 04 03:10:54 PM PDT 23
Finished Oct 04 03:11:29 PM PDT 23
Peak memory 216748 kb
Host smart-60d9759a-29ba-4237-a3b5-4530ace6954d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211687787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3211687787
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.449439083
Short name T189
Test name
Test status
Simulation time 156917121545 ps
CPU time 1567.93 seconds
Started Oct 04 03:08:29 PM PDT 23
Finished Oct 04 03:34:38 PM PDT 23
Peak memory 235772 kb
Host smart-469a3c34-9b80-4190-8148-0ff24ae99e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449439083 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.449439083
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4209828557
Short name T337
Test name
Test status
Simulation time 908085820 ps
CPU time 6.14 seconds
Started Oct 04 03:10:04 PM PDT 23
Finished Oct 04 03:10:11 PM PDT 23
Peak memory 211068 kb
Host smart-ff5fb8e7-a3e9-4a8a-a62b-704326b0c847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209828557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4209828557
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3797514916
Short name T370
Test name
Test status
Simulation time 52657595852 ps
CPU time 304.94 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:14:22 PM PDT 23
Peak memory 237592 kb
Host smart-d5c256f2-e51f-4d14-a1b0-c329d5efe502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797514916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3797514916
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3319287599
Short name T304
Test name
Test status
Simulation time 2422793095 ps
CPU time 19.57 seconds
Started Oct 04 03:09:08 PM PDT 23
Finished Oct 04 03:09:28 PM PDT 23
Peak memory 211388 kb
Host smart-6624dfff-107f-4abb-8e01-8bbcbd5d8d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319287599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3319287599
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.801525565
Short name T268
Test name
Test status
Simulation time 97398142 ps
CPU time 5.93 seconds
Started Oct 04 03:10:03 PM PDT 23
Finished Oct 04 03:10:09 PM PDT 23
Peak memory 211084 kb
Host smart-04c69217-925d-4d46-8898-027d779302ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801525565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.801525565
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1528859610
Short name T254
Test name
Test status
Simulation time 2912124493 ps
CPU time 15.82 seconds
Started Oct 04 03:08:09 PM PDT 23
Finished Oct 04 03:08:25 PM PDT 23
Peak memory 212868 kb
Host smart-0a514564-bfc6-4808-819a-992a76c5d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528859610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1528859610
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3736687987
Short name T418
Test name
Test status
Simulation time 8752807697 ps
CPU time 75.11 seconds
Started Oct 04 03:12:11 PM PDT 23
Finished Oct 04 03:13:27 PM PDT 23
Peak memory 215624 kb
Host smart-feefadf2-b77d-42d0-a9a2-969c6b58ca71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736687987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3736687987
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1857493558
Short name T247
Test name
Test status
Simulation time 106584122143 ps
CPU time 1186.07 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:29:03 PM PDT 23
Peak memory 235748 kb
Host smart-cccfc43e-6fc0-48db-a71a-a27d95984b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857493558 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1857493558
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3580214280
Short name T372
Test name
Test status
Simulation time 4029624434 ps
CPU time 16.67 seconds
Started Oct 04 03:09:09 PM PDT 23
Finished Oct 04 03:09:26 PM PDT 23
Peak memory 211196 kb
Host smart-1e9f9edb-372a-4fd7-82ac-ca3b083121bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580214280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3580214280
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.552314929
Short name T10
Test name
Test status
Simulation time 53745209419 ps
CPU time 306.14 seconds
Started Oct 04 03:11:00 PM PDT 23
Finished Oct 04 03:16:07 PM PDT 23
Peak memory 211516 kb
Host smart-a3266761-b1b3-41e4-b08c-d976b1f22f5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552314929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.552314929
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3465133158
Short name T322
Test name
Test status
Simulation time 1467932935 ps
CPU time 18.99 seconds
Started Oct 04 03:10:42 PM PDT 23
Finished Oct 04 03:11:02 PM PDT 23
Peak memory 211128 kb
Host smart-db5a12df-cec3-485d-bad7-ece7b0fe0912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465133158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3465133158
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1657510379
Short name T263
Test name
Test status
Simulation time 384299542 ps
CPU time 5.7 seconds
Started Oct 04 03:10:43 PM PDT 23
Finished Oct 04 03:10:49 PM PDT 23
Peak memory 210960 kb
Host smart-bc8b9284-caca-4d2a-a302-64322079bbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657510379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1657510379
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1145722549
Short name T7
Test name
Test status
Simulation time 2709129249 ps
CPU time 31.11 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:32 PM PDT 23
Peak memory 212968 kb
Host smart-8ac3c6e1-d52d-4e31-a814-a36f2782e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145722549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1145722549
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2282929720
Short name T428
Test name
Test status
Simulation time 23999728131 ps
CPU time 57.75 seconds
Started Oct 04 03:09:03 PM PDT 23
Finished Oct 04 03:10:02 PM PDT 23
Peak memory 218116 kb
Host smart-75d2423e-3f5f-4906-bd2d-e1748db49ead
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282929720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2282929720
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2946766998
Short name T291
Test name
Test status
Simulation time 85637862 ps
CPU time 4.28 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:09:00 PM PDT 23
Peak memory 210996 kb
Host smart-8261340e-27af-4f53-ae86-3fe705335700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946766998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2946766998
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1955193551
Short name T391
Test name
Test status
Simulation time 7378509009 ps
CPU time 108.05 seconds
Started Oct 04 03:09:25 PM PDT 23
Finished Oct 04 03:11:15 PM PDT 23
Peak memory 237732 kb
Host smart-435e35f2-8eb8-4634-8d25-a55e418e4453
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955193551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1955193551
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2717917855
Short name T369
Test name
Test status
Simulation time 2890539573 ps
CPU time 26.4 seconds
Started Oct 04 03:09:05 PM PDT 23
Finished Oct 04 03:09:32 PM PDT 23
Peak memory 211648 kb
Host smart-506d927d-3939-438b-a64e-9c49e0d58a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717917855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2717917855
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1954577754
Short name T213
Test name
Test status
Simulation time 7677739773 ps
CPU time 15.86 seconds
Started Oct 04 03:09:23 PM PDT 23
Finished Oct 04 03:09:39 PM PDT 23
Peak memory 211332 kb
Host smart-2060e734-d548-4969-9e9d-d324f358b72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954577754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1954577754
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.4171784453
Short name T277
Test name
Test status
Simulation time 194101604 ps
CPU time 10.35 seconds
Started Oct 04 03:10:45 PM PDT 23
Finished Oct 04 03:10:56 PM PDT 23
Peak memory 213232 kb
Host smart-f8f29f22-f4d9-4b06-a093-e16657f123e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171784453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.4171784453
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.4096591242
Short name T319
Test name
Test status
Simulation time 10795990076 ps
CPU time 26.84 seconds
Started Oct 04 03:09:45 PM PDT 23
Finished Oct 04 03:10:12 PM PDT 23
Peak memory 214564 kb
Host smart-441c6a24-0abb-4cb5-a025-204b7e4ac5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096591242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.4096591242
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.57820792
Short name T317
Test name
Test status
Simulation time 17655206853 ps
CPU time 921.67 seconds
Started Oct 04 03:09:54 PM PDT 23
Finished Oct 04 03:25:16 PM PDT 23
Peak memory 233120 kb
Host smart-76423c9a-1028-4233-a1f2-2075ab4060ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57820792 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.57820792
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2311867835
Short name T320
Test name
Test status
Simulation time 1197316643 ps
CPU time 12.03 seconds
Started Oct 04 03:09:21 PM PDT 23
Finished Oct 04 03:09:34 PM PDT 23
Peak memory 210904 kb
Host smart-9d28d820-57f0-44a0-b9e2-0647e1a79d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311867835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2311867835
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2268322757
Short name T178
Test name
Test status
Simulation time 1676994488 ps
CPU time 112.44 seconds
Started Oct 04 03:13:24 PM PDT 23
Finished Oct 04 03:15:17 PM PDT 23
Peak memory 238556 kb
Host smart-3a65c734-bc6b-47a8-91ca-ffb7e7a1e634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268322757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2268322757
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.915812126
Short name T335
Test name
Test status
Simulation time 15662107568 ps
CPU time 32.66 seconds
Started Oct 04 03:09:24 PM PDT 23
Finished Oct 04 03:09:59 PM PDT 23
Peak memory 211500 kb
Host smart-34c3ec04-e38d-4d9d-8a18-6a74006ae44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915812126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.915812126
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1279410705
Short name T164
Test name
Test status
Simulation time 302888126 ps
CPU time 7.88 seconds
Started Oct 04 03:08:35 PM PDT 23
Finished Oct 04 03:08:43 PM PDT 23
Peak memory 210980 kb
Host smart-030590ad-31d1-4de6-9f18-c6ac39f0f841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1279410705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1279410705
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.888061447
Short name T403
Test name
Test status
Simulation time 3506516604 ps
CPU time 30.46 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:09:26 PM PDT 23
Peak memory 212404 kb
Host smart-64bdc28e-777a-4ec8-8446-54a55c325c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888061447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.888061447
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1364830589
Short name T321
Test name
Test status
Simulation time 6621786461 ps
CPU time 41.12 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:09:19 PM PDT 23
Peak memory 216536 kb
Host smart-e0b747c8-e97b-4849-bc65-023e9321109f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364830589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1364830589
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.57052068
Short name T292
Test name
Test status
Simulation time 19963682468 ps
CPU time 758.73 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:21:55 PM PDT 23
Peak memory 235816 kb
Host smart-0f436ae0-20e6-440f-840f-fdaf86a7f1df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57052068 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.57052068
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.59811144
Short name T386
Test name
Test status
Simulation time 499105794 ps
CPU time 6.03 seconds
Started Oct 04 03:11:01 PM PDT 23
Finished Oct 04 03:11:07 PM PDT 23
Peak memory 211012 kb
Host smart-d28cdbec-10fd-4cd5-a330-e6a14dad45bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59811144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.59811144
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2600936285
Short name T175
Test name
Test status
Simulation time 197001438444 ps
CPU time 348.81 seconds
Started Oct 04 03:09:14 PM PDT 23
Finished Oct 04 03:15:04 PM PDT 23
Peak memory 237716 kb
Host smart-e9611054-2b7d-446b-b3d1-ce9bfd66b84c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600936285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2600936285
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3724122105
Short name T427
Test name
Test status
Simulation time 1044985820 ps
CPU time 16.23 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:19 PM PDT 23
Peak memory 211620 kb
Host smart-c1a45f00-120b-4d37-94f6-d9ce5ef82415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724122105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3724122105
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.753016400
Short name T373
Test name
Test status
Simulation time 1576563444 ps
CPU time 20.67 seconds
Started Oct 04 03:10:47 PM PDT 23
Finished Oct 04 03:11:08 PM PDT 23
Peak memory 213208 kb
Host smart-79753c74-1566-412f-92b5-cdff6705bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753016400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.753016400
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.531216406
Short name T389
Test name
Test status
Simulation time 19620514744 ps
CPU time 22.56 seconds
Started Oct 04 03:08:34 PM PDT 23
Finished Oct 04 03:08:57 PM PDT 23
Peak memory 219476 kb
Host smart-ecae7d0a-5eb0-4243-b250-0670991eadfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531216406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.531216406
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3738323489
Short name T354
Test name
Test status
Simulation time 41743109364 ps
CPU time 3937.52 seconds
Started Oct 04 03:09:20 PM PDT 23
Finished Oct 04 04:14:59 PM PDT 23
Peak memory 235908 kb
Host smart-a9c7d38d-275b-4c2f-abf1-bd4d8a8f9ad9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738323489 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3738323489
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.3364727909
Short name T295
Test name
Test status
Simulation time 174851494 ps
CPU time 4.33 seconds
Started Oct 04 03:09:25 PM PDT 23
Finished Oct 04 03:09:31 PM PDT 23
Peak memory 210992 kb
Host smart-00e466c3-58c7-450a-9a5e-9c48c51342cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364727909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.3364727909
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.175666417
Short name T50
Test name
Test status
Simulation time 170673214055 ps
CPU time 417.01 seconds
Started Oct 04 03:08:55 PM PDT 23
Finished Oct 04 03:15:53 PM PDT 23
Peak memory 237800 kb
Host smart-5b1a53e2-640c-425f-a620-517282bc1d22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175666417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.175666417
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4087959054
Short name T258
Test name
Test status
Simulation time 1965381089 ps
CPU time 21.8 seconds
Started Oct 04 03:11:14 PM PDT 23
Finished Oct 04 03:11:37 PM PDT 23
Peak memory 211108 kb
Host smart-c81bc521-d096-41eb-9e1b-e203074fbe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087959054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4087959054
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1098765065
Short name T339
Test name
Test status
Simulation time 1686826558 ps
CPU time 14.16 seconds
Started Oct 04 03:08:55 PM PDT 23
Finished Oct 04 03:09:09 PM PDT 23
Peak memory 210980 kb
Host smart-63f19d57-4c4e-44c1-b395-f2883615a3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098765065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1098765065
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1106724203
Short name T154
Test name
Test status
Simulation time 6457533182 ps
CPU time 29.36 seconds
Started Oct 04 03:10:22 PM PDT 23
Finished Oct 04 03:10:52 PM PDT 23
Peak memory 213932 kb
Host smart-8c74002d-a21d-4c28-b369-bc3517795c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106724203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1106724203
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3097550047
Short name T206
Test name
Test status
Simulation time 6860797415 ps
CPU time 39.99 seconds
Started Oct 04 03:10:05 PM PDT 23
Finished Oct 04 03:10:45 PM PDT 23
Peak memory 215964 kb
Host smart-86945e92-ca88-4b9f-84e5-7892b9b3ea2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097550047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3097550047
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4142180804
Short name T221
Test name
Test status
Simulation time 2145669509 ps
CPU time 11.37 seconds
Started Oct 04 03:10:03 PM PDT 23
Finished Oct 04 03:10:15 PM PDT 23
Peak memory 210972 kb
Host smart-7cebabe7-8071-4f0b-aeb1-ac361b716825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142180804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4142180804
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2619170053
Short name T8
Test name
Test status
Simulation time 10994832359 ps
CPU time 173.11 seconds
Started Oct 04 03:23:38 PM PDT 23
Finished Oct 04 03:26:31 PM PDT 23
Peak memory 238008 kb
Host smart-f0b145c5-96cb-49c2-8c53-40775141b18e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619170053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2619170053
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4173940821
Short name T211
Test name
Test status
Simulation time 3444772218 ps
CPU time 20.83 seconds
Started Oct 04 03:09:42 PM PDT 23
Finished Oct 04 03:10:03 PM PDT 23
Peak memory 211164 kb
Host smart-9c60e2cf-369b-494d-98b9-f8b12fb1b2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173940821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4173940821
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.54441399
Short name T364
Test name
Test status
Simulation time 10530528563 ps
CPU time 12.63 seconds
Started Oct 04 03:09:53 PM PDT 23
Finished Oct 04 03:10:06 PM PDT 23
Peak memory 211144 kb
Host smart-f70774e7-6dd3-4e11-bbe9-23435992d2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54441399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.54441399
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1756478913
Short name T219
Test name
Test status
Simulation time 1481935608 ps
CPU time 10.24 seconds
Started Oct 04 03:10:22 PM PDT 23
Finished Oct 04 03:10:33 PM PDT 23
Peak memory 212116 kb
Host smart-4752eb48-c4d4-438d-bbfc-b5af26234028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756478913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1756478913
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.764447656
Short name T245
Test name
Test status
Simulation time 1594465210 ps
CPU time 14.41 seconds
Started Oct 04 03:09:51 PM PDT 23
Finished Oct 04 03:10:05 PM PDT 23
Peak memory 214276 kb
Host smart-aa71bb77-3327-4f1b-99c9-e721afdebe7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764447656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.764447656
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2302054231
Short name T425
Test name
Test status
Simulation time 109017377114 ps
CPU time 3059.56 seconds
Started Oct 04 03:09:28 PM PDT 23
Finished Oct 04 04:00:28 PM PDT 23
Peak memory 237320 kb
Host smart-21e571b4-bc56-4555-a13f-d13bce337137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302054231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2302054231
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1327724881
Short name T412
Test name
Test status
Simulation time 2895583584 ps
CPU time 8.58 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:09:05 PM PDT 23
Peak memory 211032 kb
Host smart-f5d17cee-9ae5-413b-8d6c-2250e3f93635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327724881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1327724881
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2342015960
Short name T21
Test name
Test status
Simulation time 76240665494 ps
CPU time 376.4 seconds
Started Oct 04 03:09:34 PM PDT 23
Finished Oct 04 03:15:51 PM PDT 23
Peak memory 211480 kb
Host smart-0c423b23-e1a1-432c-b7ab-d46a78e4723b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342015960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2342015960
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2545697701
Short name T184
Test name
Test status
Simulation time 3537391862 ps
CPU time 29.78 seconds
Started Oct 04 03:09:47 PM PDT 23
Finished Oct 04 03:10:17 PM PDT 23
Peak memory 211252 kb
Host smart-dbc31b22-d8cd-427f-8342-3cc9f7f5f0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545697701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2545697701
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.105727443
Short name T248
Test name
Test status
Simulation time 101509950 ps
CPU time 5.76 seconds
Started Oct 04 03:10:02 PM PDT 23
Finished Oct 04 03:10:08 PM PDT 23
Peak memory 211096 kb
Host smart-fd2ee526-b24d-4008-b4c9-797900f5242b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105727443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.105727443
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2242123561
Short name T241
Test name
Test status
Simulation time 4344045316 ps
CPU time 38.84 seconds
Started Oct 04 03:10:55 PM PDT 23
Finished Oct 04 03:11:35 PM PDT 23
Peak memory 212804 kb
Host smart-7bb471f4-b79b-41e9-bbd0-bfda730bbfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242123561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2242123561
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3169749903
Short name T371
Test name
Test status
Simulation time 16595986258 ps
CPU time 37.18 seconds
Started Oct 04 03:12:07 PM PDT 23
Finished Oct 04 03:12:45 PM PDT 23
Peak memory 213336 kb
Host smart-2dcfac9a-4d2f-42dc-a592-e36863852df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169749903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3169749903
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2693095659
Short name T202
Test name
Test status
Simulation time 57271439386 ps
CPU time 6971.29 seconds
Started Oct 04 03:08:16 PM PDT 23
Finished Oct 04 05:04:29 PM PDT 23
Peak memory 236028 kb
Host smart-6fdacd34-0cd5-42e5-8d38-c1a80747a403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693095659 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2693095659
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1333578674
Short name T226
Test name
Test status
Simulation time 40566526039 ps
CPU time 456.37 seconds
Started Oct 04 03:09:33 PM PDT 23
Finished Oct 04 03:17:11 PM PDT 23
Peak memory 237752 kb
Host smart-97a738db-9322-49fd-99eb-59ec6711ab6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333578674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1333578674
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.861772554
Short name T419
Test name
Test status
Simulation time 11743296269 ps
CPU time 26.58 seconds
Started Oct 04 03:08:45 PM PDT 23
Finished Oct 04 03:09:12 PM PDT 23
Peak memory 211624 kb
Host smart-0dbec8c0-5a31-4d56-989e-748c9e49f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861772554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.861772554
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1889603798
Short name T352
Test name
Test status
Simulation time 142735708 ps
CPU time 7.13 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:09:23 PM PDT 23
Peak memory 211052 kb
Host smart-b5fe24ef-956c-4526-a7d7-2b1c56dafdc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889603798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1889603798
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3569127870
Short name T16
Test name
Test status
Simulation time 5932250826 ps
CPU time 34.04 seconds
Started Oct 04 03:14:18 PM PDT 23
Finished Oct 04 03:14:52 PM PDT 23
Peak memory 212780 kb
Host smart-b768ead6-78f0-4710-abd1-6049217643e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569127870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3569127870
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3192424008
Short name T355
Test name
Test status
Simulation time 17259244123 ps
CPU time 94.47 seconds
Started Oct 04 03:08:29 PM PDT 23
Finished Oct 04 03:10:04 PM PDT 23
Peak memory 219384 kb
Host smart-cab0a8ad-a914-4055-ae88-efe8ec4e1669
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192424008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3192424008
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1687927660
Short name T334
Test name
Test status
Simulation time 268669975207 ps
CPU time 1125.93 seconds
Started Oct 04 03:09:16 PM PDT 23
Finished Oct 04 03:28:03 PM PDT 23
Peak memory 236132 kb
Host smart-a9dad430-1364-46f8-b6c2-630a3b176e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687927660 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1687927660
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2234192653
Short name T269
Test name
Test status
Simulation time 3677780437 ps
CPU time 15.11 seconds
Started Oct 04 03:09:52 PM PDT 23
Finished Oct 04 03:10:08 PM PDT 23
Peak memory 211012 kb
Host smart-177f98fd-c0d3-4fff-858b-df4f941f8e27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234192653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2234192653
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2802172244
Short name T324
Test name
Test status
Simulation time 31872262770 ps
CPU time 340.36 seconds
Started Oct 04 03:14:09 PM PDT 23
Finished Oct 04 03:19:50 PM PDT 23
Peak memory 228484 kb
Host smart-2477f8c9-c447-43bd-9757-5026eb42da4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802172244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2802172244
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4260347742
Short name T411
Test name
Test status
Simulation time 7881003017 ps
CPU time 21.45 seconds
Started Oct 04 03:23:57 PM PDT 23
Finished Oct 04 03:24:19 PM PDT 23
Peak memory 211736 kb
Host smart-133fb61f-ee49-4850-97c3-b8abeb530b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260347742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4260347742
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1032029379
Short name T305
Test name
Test status
Simulation time 151145588 ps
CPU time 5.82 seconds
Started Oct 04 03:12:19 PM PDT 23
Finished Oct 04 03:12:26 PM PDT 23
Peak memory 211060 kb
Host smart-9b2f1301-c2d0-473e-ba19-18058cca5444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032029379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1032029379
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3766261675
Short name T34
Test name
Test status
Simulation time 147518359 ps
CPU time 56.58 seconds
Started Oct 04 03:09:31 PM PDT 23
Finished Oct 04 03:10:28 PM PDT 23
Peak memory 235092 kb
Host smart-934bebee-3f6a-4261-8bc5-249c504d61c0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766261675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3766261675
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1656615061
Short name T155
Test name
Test status
Simulation time 1755904238 ps
CPU time 20.8 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:09:17 PM PDT 23
Peak memory 212440 kb
Host smart-18559a5a-dca4-4511-a4e2-d5fc62dca60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656615061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1656615061
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2457757052
Short name T191
Test name
Test status
Simulation time 1113718835 ps
CPU time 11.85 seconds
Started Oct 04 03:08:36 PM PDT 23
Finished Oct 04 03:08:48 PM PDT 23
Peak memory 213408 kb
Host smart-c07d6d9a-0d0f-4c00-a958-a1f333f1bd3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457757052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2457757052
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4283546811
Short name T398
Test name
Test status
Simulation time 100664912654 ps
CPU time 642.42 seconds
Started Oct 04 03:08:57 PM PDT 23
Finished Oct 04 03:19:40 PM PDT 23
Peak memory 233888 kb
Host smart-0bed2442-3baa-4e0e-a5a2-12a3266aaf6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283546811 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4283546811
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3874601888
Short name T332
Test name
Test status
Simulation time 3740900037 ps
CPU time 10.09 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 03:09:09 PM PDT 23
Peak memory 211032 kb
Host smart-4667a4e9-1aa4-4d00-9071-daf091d5ead5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874601888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3874601888
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3033446587
Short name T383
Test name
Test status
Simulation time 72578576143 ps
CPU time 458 seconds
Started Oct 04 03:09:19 PM PDT 23
Finished Oct 04 03:16:57 PM PDT 23
Peak memory 233784 kb
Host smart-fcd184ee-395a-4d78-b9ac-67e306bf89ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033446587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3033446587
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1696693308
Short name T377
Test name
Test status
Simulation time 1368367132 ps
CPU time 17.99 seconds
Started Oct 04 03:08:57 PM PDT 23
Finished Oct 04 03:09:16 PM PDT 23
Peak memory 211368 kb
Host smart-92ff2f12-7492-4dbe-97b2-192371fad57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696693308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1696693308
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.487502098
Short name T238
Test name
Test status
Simulation time 575104860 ps
CPU time 5.21 seconds
Started Oct 04 03:14:15 PM PDT 23
Finished Oct 04 03:14:20 PM PDT 23
Peak memory 210668 kb
Host smart-cefda0f9-be66-46db-bcad-4cd12b34977c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487502098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.487502098
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3908762989
Short name T396
Test name
Test status
Simulation time 16476080677 ps
CPU time 22.1 seconds
Started Oct 04 03:08:53 PM PDT 23
Finished Oct 04 03:09:15 PM PDT 23
Peak memory 213392 kb
Host smart-ed67588f-ef0f-4ea1-a7bf-a0ae6e8e1dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908762989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3908762989
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1945601650
Short name T109
Test name
Test status
Simulation time 51690817164 ps
CPU time 86.57 seconds
Started Oct 04 03:09:51 PM PDT 23
Finished Oct 04 03:11:18 PM PDT 23
Peak memory 216456 kb
Host smart-86f5cb47-37c5-48a7-ac71-af8d7bbcfc5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945601650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1945601650
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1414001544
Short name T285
Test name
Test status
Simulation time 347723114 ps
CPU time 4.43 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:06 PM PDT 23
Peak memory 211128 kb
Host smart-b4846695-4622-4070-b6f0-26b789ad7276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414001544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1414001544
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.39709784
Short name T281
Test name
Test status
Simulation time 38515016627 ps
CPU time 196.16 seconds
Started Oct 04 03:20:21 PM PDT 23
Finished Oct 04 03:23:37 PM PDT 23
Peak memory 233648 kb
Host smart-378bc91a-c279-4e00-98be-2680f1e441d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39709784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.39709784
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.786610862
Short name T312
Test name
Test status
Simulation time 2056743127 ps
CPU time 16.38 seconds
Started Oct 04 03:09:12 PM PDT 23
Finished Oct 04 03:09:28 PM PDT 23
Peak memory 211936 kb
Host smart-ac78acbd-d178-4d19-b28b-1db20e98d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786610862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.786610862
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1485979277
Short name T287
Test name
Test status
Simulation time 4335037957 ps
CPU time 17.79 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 03:09:16 PM PDT 23
Peak memory 211092 kb
Host smart-45ee365c-b640-4fc9-951f-093166c711ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485979277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1485979277
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.553601330
Short name T233
Test name
Test status
Simulation time 9203314419 ps
CPU time 28.28 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 213612 kb
Host smart-b5b3b679-696f-4665-b394-c8017e18ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553601330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.553601330
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2113840242
Short name T102
Test name
Test status
Simulation time 5500410980 ps
CPU time 27.98 seconds
Started Oct 04 03:09:45 PM PDT 23
Finished Oct 04 03:10:13 PM PDT 23
Peak memory 217272 kb
Host smart-7e3b2486-82a2-478b-9cb1-10a2eb671373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113840242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2113840242
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2571069849
Short name T251
Test name
Test status
Simulation time 81871492467 ps
CPU time 7021.64 seconds
Started Oct 04 03:11:24 PM PDT 23
Finished Oct 04 05:08:27 PM PDT 23
Peak memory 235760 kb
Host smart-3e259bfa-4fda-4fc4-8594-97745a633b77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571069849 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2571069849
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.544070883
Short name T172
Test name
Test status
Simulation time 85492820 ps
CPU time 4.4 seconds
Started Oct 04 03:09:51 PM PDT 23
Finished Oct 04 03:09:56 PM PDT 23
Peak memory 211020 kb
Host smart-b84865ac-76f0-49eb-a5f0-c250074ee000
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544070883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.544070883
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2174687812
Short name T200
Test name
Test status
Simulation time 10493857136 ps
CPU time 191.29 seconds
Started Oct 04 03:09:17 PM PDT 23
Finished Oct 04 03:12:29 PM PDT 23
Peak memory 240540 kb
Host smart-3e9758b4-5ee9-416f-8671-8f014f24daec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174687812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2174687812
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3826970216
Short name T359
Test name
Test status
Simulation time 4396307727 ps
CPU time 17.42 seconds
Started Oct 04 03:14:01 PM PDT 23
Finished Oct 04 03:14:19 PM PDT 23
Peak memory 211600 kb
Host smart-3d1de392-21f8-4470-bc04-caaa9eb4af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826970216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3826970216
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3278020527
Short name T240
Test name
Test status
Simulation time 2099115082 ps
CPU time 17.55 seconds
Started Oct 04 03:10:30 PM PDT 23
Finished Oct 04 03:10:48 PM PDT 23
Peak memory 210936 kb
Host smart-6d758521-362e-4eac-ad13-995c32a44e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278020527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3278020527
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.854977179
Short name T192
Test name
Test status
Simulation time 32999308421 ps
CPU time 36.67 seconds
Started Oct 04 03:08:57 PM PDT 23
Finished Oct 04 03:09:34 PM PDT 23
Peak memory 213580 kb
Host smart-3ed9dd6b-ef69-41e7-83e2-40fa42c07dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854977179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.854977179
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3679777968
Short name T278
Test name
Test status
Simulation time 7790627582 ps
CPU time 20.25 seconds
Started Oct 04 03:09:15 PM PDT 23
Finished Oct 04 03:09:36 PM PDT 23
Peak memory 211960 kb
Host smart-dc81f883-c3a7-46dd-98f0-e9c1d0276a1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679777968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3679777968
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.2662263277
Short name T171
Test name
Test status
Simulation time 119554094197 ps
CPU time 1243.4 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:29:40 PM PDT 23
Peak memory 236624 kb
Host smart-6c217042-7b81-411f-8877-5b0a5c2ebcd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662263277 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.2662263277
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3147606450
Short name T353
Test name
Test status
Simulation time 346585309 ps
CPU time 4.35 seconds
Started Oct 04 03:10:10 PM PDT 23
Finished Oct 04 03:10:15 PM PDT 23
Peak memory 211100 kb
Host smart-e5c69a76-307a-423e-b49d-4dd936e506be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147606450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3147606450
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1843928173
Short name T51
Test name
Test status
Simulation time 302304979360 ps
CPU time 481.35 seconds
Started Oct 04 03:08:50 PM PDT 23
Finished Oct 04 03:16:53 PM PDT 23
Peak memory 236476 kb
Host smart-aa4ca986-3f43-4477-a317-2932668a18c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843928173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1843928173
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2722649889
Short name T201
Test name
Test status
Simulation time 2377722892 ps
CPU time 23.07 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 03:09:21 PM PDT 23
Peak memory 211372 kb
Host smart-45e82a06-3948-413a-a782-1cefbdf4966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722649889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2722649889
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.49101859
Short name T224
Test name
Test status
Simulation time 6457498773 ps
CPU time 15.33 seconds
Started Oct 04 03:08:10 PM PDT 23
Finished Oct 04 03:08:26 PM PDT 23
Peak memory 211112 kb
Host smart-684b560f-2bf3-4b56-889c-894191b7f0cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49101859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.49101859
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1343821609
Short name T261
Test name
Test status
Simulation time 15394480968 ps
CPU time 37.08 seconds
Started Oct 04 03:09:02 PM PDT 23
Finished Oct 04 03:09:41 PM PDT 23
Peak memory 213476 kb
Host smart-9ba0646b-fff8-4fbe-8a4b-c648feace5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343821609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1343821609
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.4010511389
Short name T48
Test name
Test status
Simulation time 11477846558 ps
CPU time 15.93 seconds
Started Oct 04 03:15:22 PM PDT 23
Finished Oct 04 03:15:39 PM PDT 23
Peak memory 211072 kb
Host smart-49a8cc88-06e1-43d4-ba21-61113964313d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010511389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.4010511389
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3356993884
Short name T379
Test name
Test status
Simulation time 8326887430 ps
CPU time 100.84 seconds
Started Oct 04 03:09:02 PM PDT 23
Finished Oct 04 03:10:44 PM PDT 23
Peak memory 237600 kb
Host smart-dbcbcd56-494a-40f0-95ce-f5e38c15d089
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356993884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3356993884
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3696791817
Short name T222
Test name
Test status
Simulation time 2918120971 ps
CPU time 18.94 seconds
Started Oct 04 03:09:30 PM PDT 23
Finished Oct 04 03:09:49 PM PDT 23
Peak memory 211296 kb
Host smart-8eae4622-7c9b-4cd7-a780-9500b8c22e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696791817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3696791817
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2833754634
Short name T423
Test name
Test status
Simulation time 6368344658 ps
CPU time 15.4 seconds
Started Oct 04 03:10:29 PM PDT 23
Finished Oct 04 03:10:45 PM PDT 23
Peak memory 211220 kb
Host smart-f7e5a19b-597b-40b3-957d-4f103e6d6a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2833754634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2833754634
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.564251681
Short name T95
Test name
Test status
Simulation time 5231424780 ps
CPU time 19.44 seconds
Started Oct 04 03:09:32 PM PDT 23
Finished Oct 04 03:09:52 PM PDT 23
Peak memory 213164 kb
Host smart-b36f9c9e-a31a-4711-abfd-9df7974ad27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564251681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.564251681
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3656794304
Short name T399
Test name
Test status
Simulation time 16522193842 ps
CPU time 31.83 seconds
Started Oct 04 03:09:54 PM PDT 23
Finished Oct 04 03:10:26 PM PDT 23
Peak memory 213828 kb
Host smart-49646dee-9897-480d-8299-4d97f7b7f99c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656794304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3656794304
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1119155492
Short name T227
Test name
Test status
Simulation time 1272102942 ps
CPU time 11.14 seconds
Started Oct 04 03:11:00 PM PDT 23
Finished Oct 04 03:11:12 PM PDT 23
Peak memory 211000 kb
Host smart-372a984e-3a08-43a5-ba19-9a6d484c0422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119155492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1119155492
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1364791921
Short name T180
Test name
Test status
Simulation time 33298544213 ps
CPU time 140.03 seconds
Started Oct 04 03:12:39 PM PDT 23
Finished Oct 04 03:15:00 PM PDT 23
Peak memory 236700 kb
Host smart-faf9301f-2028-42a3-abf7-5c72956e441b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364791921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1364791921
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2590014975
Short name T413
Test name
Test status
Simulation time 197647901 ps
CPU time 9.48 seconds
Started Oct 04 03:13:04 PM PDT 23
Finished Oct 04 03:13:15 PM PDT 23
Peak memory 209472 kb
Host smart-86468285-bc4f-4b79-b7b4-ce7b3aac467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590014975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2590014975
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.684664121
Short name T286
Test name
Test status
Simulation time 1802976946 ps
CPU time 15.1 seconds
Started Oct 04 03:09:28 PM PDT 23
Finished Oct 04 03:09:44 PM PDT 23
Peak memory 211040 kb
Host smart-e94ebd66-0e39-4d13-b42e-877b6876d49e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684664121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.684664121
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3176804846
Short name T97
Test name
Test status
Simulation time 13831757744 ps
CPU time 33.24 seconds
Started Oct 04 03:11:56 PM PDT 23
Finished Oct 04 03:12:30 PM PDT 23
Peak memory 213088 kb
Host smart-8b814563-1eb9-48e8-bec7-11f41652b0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176804846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3176804846
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1868460121
Short name T367
Test name
Test status
Simulation time 5651958230 ps
CPU time 58.83 seconds
Started Oct 04 03:11:58 PM PDT 23
Finished Oct 04 03:12:57 PM PDT 23
Peak memory 216292 kb
Host smart-d3825797-dc75-4b30-a050-34e017e1a59e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868460121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1868460121
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3308155488
Short name T351
Test name
Test status
Simulation time 1452617447 ps
CPU time 13.66 seconds
Started Oct 04 03:08:49 PM PDT 23
Finished Oct 04 03:09:05 PM PDT 23
Peak memory 211044 kb
Host smart-8fa72acb-bddc-4e37-a128-3ea211928b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308155488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3308155488
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1777197796
Short name T195
Test name
Test status
Simulation time 403580752366 ps
CPU time 204.91 seconds
Started Oct 04 03:09:32 PM PDT 23
Finished Oct 04 03:12:57 PM PDT 23
Peak memory 237992 kb
Host smart-6e7903ae-7f60-4e88-b20c-095608a8c72b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777197796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1777197796
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2457133947
Short name T185
Test name
Test status
Simulation time 3285851976 ps
CPU time 28.95 seconds
Started Oct 04 03:13:16 PM PDT 23
Finished Oct 04 03:13:45 PM PDT 23
Peak memory 211780 kb
Host smart-1f75585c-d02c-40f7-84e9-f7eaad060d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457133947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2457133947
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1092344877
Short name T92
Test name
Test status
Simulation time 330391152 ps
CPU time 5.72 seconds
Started Oct 04 03:09:34 PM PDT 23
Finished Oct 04 03:09:40 PM PDT 23
Peak memory 211048 kb
Host smart-28e2717c-6fd0-4556-9e0c-8f8f0c58a563
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1092344877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1092344877
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3092304083
Short name T94
Test name
Test status
Simulation time 8604987619 ps
CPU time 26.64 seconds
Started Oct 04 03:13:32 PM PDT 23
Finished Oct 04 03:13:59 PM PDT 23
Peak memory 213160 kb
Host smart-ef143227-2509-4c92-9a90-aa699e06fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092304083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3092304083
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.109076552
Short name T196
Test name
Test status
Simulation time 7586346257 ps
CPU time 37.38 seconds
Started Oct 04 03:14:11 PM PDT 23
Finished Oct 04 03:14:48 PM PDT 23
Peak memory 214292 kb
Host smart-8407636e-b0c1-42df-9495-380f0b1cc786
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109076552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.109076552
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.257884433
Short name T246
Test name
Test status
Simulation time 52314504252 ps
CPU time 1950.33 seconds
Started Oct 04 03:10:14 PM PDT 23
Finished Oct 04 03:42:45 PM PDT 23
Peak memory 235896 kb
Host smart-32b0546f-fb1e-45bf-bec3-84d3090370c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257884433 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.257884433
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3915297667
Short name T302
Test name
Test status
Simulation time 323063414 ps
CPU time 6.58 seconds
Started Oct 04 03:09:06 PM PDT 23
Finished Oct 04 03:09:13 PM PDT 23
Peak memory 211024 kb
Host smart-78d76acc-b91f-4fbe-9a4b-dc6a1a46d750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915297667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3915297667
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1553616570
Short name T323
Test name
Test status
Simulation time 17251550286 ps
CPU time 20.67 seconds
Started Oct 04 03:08:30 PM PDT 23
Finished Oct 04 03:08:51 PM PDT 23
Peak memory 211460 kb
Host smart-73f6c5f3-01bf-4305-ae41-c73d655ff5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553616570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1553616570
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3331510827
Short name T296
Test name
Test status
Simulation time 543841330 ps
CPU time 6.62 seconds
Started Oct 04 03:08:52 PM PDT 23
Finished Oct 04 03:08:59 PM PDT 23
Peak memory 210984 kb
Host smart-d73e6e79-6c4f-4803-bca3-14dfcd14bb07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331510827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3331510827
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2127502949
Short name T429
Test name
Test status
Simulation time 1118647706 ps
CPU time 18.61 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:20 PM PDT 23
Peak memory 212580 kb
Host smart-dd57fb65-55a9-402a-aefc-380a9907fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127502949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2127502949
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2890873861
Short name T387
Test name
Test status
Simulation time 800370602 ps
CPU time 14.2 seconds
Started Oct 04 03:09:15 PM PDT 23
Finished Oct 04 03:09:29 PM PDT 23
Peak memory 212740 kb
Host smart-e2574bd3-87aa-4325-be6e-020cad6ced28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890873861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2890873861
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2620649801
Short name T152
Test name
Test status
Simulation time 68824111321 ps
CPU time 4027.88 seconds
Started Oct 04 03:11:05 PM PDT 23
Finished Oct 04 04:18:14 PM PDT 23
Peak memory 235772 kb
Host smart-2744cf4d-33ac-475e-b248-36615e605f06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620649801 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2620649801
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2121995482
Short name T37
Test name
Test status
Simulation time 1638476787 ps
CPU time 13.67 seconds
Started Oct 04 03:09:14 PM PDT 23
Finished Oct 04 03:09:28 PM PDT 23
Peak memory 211052 kb
Host smart-4540b255-0b61-4c06-aad3-9673ce290bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121995482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2121995482
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3986225894
Short name T316
Test name
Test status
Simulation time 26363721597 ps
CPU time 135.2 seconds
Started Oct 04 03:11:18 PM PDT 23
Finished Oct 04 03:13:35 PM PDT 23
Peak memory 227940 kb
Host smart-fc1fbae8-b901-4de6-b084-1c3acd7fbe49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986225894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3986225894
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.711281198
Short name T187
Test name
Test status
Simulation time 5920543810 ps
CPU time 19.58 seconds
Started Oct 04 03:10:01 PM PDT 23
Finished Oct 04 03:10:21 PM PDT 23
Peak memory 211988 kb
Host smart-b632fa41-3dd6-4bf0-bb62-33bf037836cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711281198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.711281198
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.813783421
Short name T327
Test name
Test status
Simulation time 6766713500 ps
CPU time 15.47 seconds
Started Oct 04 03:08:44 PM PDT 23
Finished Oct 04 03:09:01 PM PDT 23
Peak memory 211088 kb
Host smart-b7e16dd6-5df7-447e-ad12-b56212ea1c0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813783421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.813783421
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3952445073
Short name T401
Test name
Test status
Simulation time 8397531337 ps
CPU time 44.68 seconds
Started Oct 04 03:08:47 PM PDT 23
Finished Oct 04 03:09:36 PM PDT 23
Peak memory 214304 kb
Host smart-c8b86793-171a-40a8-8390-22ffe0329d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952445073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3952445073
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3719531284
Short name T408
Test name
Test status
Simulation time 4873562748 ps
CPU time 42.86 seconds
Started Oct 04 03:08:53 PM PDT 23
Finished Oct 04 03:09:37 PM PDT 23
Peak memory 216376 kb
Host smart-e6760042-f0c4-4817-9adf-b5f08a3bb136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719531284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3719531284
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2739781382
Short name T430
Test name
Test status
Simulation time 14318573182 ps
CPU time 467.53 seconds
Started Oct 04 03:10:04 PM PDT 23
Finished Oct 04 03:17:52 PM PDT 23
Peak memory 223236 kb
Host smart-5a3453c1-2438-46ca-8490-cc0dda1044a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739781382 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2739781382
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.818053227
Short name T253
Test name
Test status
Simulation time 4481733956 ps
CPU time 12.49 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:08:50 PM PDT 23
Peak memory 211152 kb
Host smart-473eb2ab-622e-4932-b7c1-6d64ae5b5c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818053227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.818053227
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.647369777
Short name T333
Test name
Test status
Simulation time 19682851790 ps
CPU time 201.61 seconds
Started Oct 04 03:09:15 PM PDT 23
Finished Oct 04 03:12:38 PM PDT 23
Peak memory 213332 kb
Host smart-24dcde75-1da8-45fd-811a-858e3ec5b39b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647369777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.647369777
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3725299702
Short name T288
Test name
Test status
Simulation time 993817763 ps
CPU time 11.34 seconds
Started Oct 04 03:08:39 PM PDT 23
Finished Oct 04 03:08:50 PM PDT 23
Peak memory 211084 kb
Host smart-e7bb2c8f-bd5c-486b-851f-9c25c3624fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725299702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3725299702
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3257922278
Short name T318
Test name
Test status
Simulation time 128999038 ps
CPU time 5.42 seconds
Started Oct 04 03:08:36 PM PDT 23
Finished Oct 04 03:08:41 PM PDT 23
Peak memory 210992 kb
Host smart-53f39564-10e2-49af-8adc-10f848a71b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257922278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3257922278
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2017123443
Short name T44
Test name
Test status
Simulation time 6190258986 ps
CPU time 27.85 seconds
Started Oct 04 03:08:53 PM PDT 23
Finished Oct 04 03:09:21 PM PDT 23
Peak memory 213644 kb
Host smart-a3a10d94-32ae-4418-8bb3-b70d7c607f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017123443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2017123443
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.459726034
Short name T19
Test name
Test status
Simulation time 1214784394 ps
CPU time 17.93 seconds
Started Oct 04 03:10:23 PM PDT 23
Finished Oct 04 03:10:41 PM PDT 23
Peak memory 213356 kb
Host smart-4187509b-bb19-414f-87c4-d6902eac14a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459726034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.459726034
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.4017475220
Short name T376
Test name
Test status
Simulation time 120087505667 ps
CPU time 7254.06 seconds
Started Oct 04 03:08:35 PM PDT 23
Finished Oct 04 05:09:30 PM PDT 23
Peak memory 238520 kb
Host smart-07813d0d-3ac9-4d71-9d98-d6ec78937839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017475220 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.4017475220
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.3219776540
Short name T338
Test name
Test status
Simulation time 2728294278 ps
CPU time 12.66 seconds
Started Oct 04 03:09:56 PM PDT 23
Finished Oct 04 03:10:09 PM PDT 23
Peak memory 211272 kb
Host smart-ad6d3cb5-77b8-46da-9381-2874caf383fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219776540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.3219776540
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3372834017
Short name T417
Test name
Test status
Simulation time 52368281829 ps
CPU time 354.17 seconds
Started Oct 04 03:09:30 PM PDT 23
Finished Oct 04 03:15:24 PM PDT 23
Peak memory 227900 kb
Host smart-266892ee-456f-4e03-947b-db57bc5673c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372834017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3372834017
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2500649667
Short name T259
Test name
Test status
Simulation time 450505177 ps
CPU time 9.38 seconds
Started Oct 04 03:10:43 PM PDT 23
Finished Oct 04 03:10:53 PM PDT 23
Peak memory 211216 kb
Host smart-23cff434-03c6-49ab-a431-7956c7ed0ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500649667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2500649667
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1292648235
Short name T331
Test name
Test status
Simulation time 2781778992 ps
CPU time 13.36 seconds
Started Oct 04 03:09:30 PM PDT 23
Finished Oct 04 03:09:44 PM PDT 23
Peak memory 211124 kb
Host smart-8227bcf6-6623-4621-bc99-73b290f80844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292648235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1292648235
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1518350187
Short name T36
Test name
Test status
Simulation time 1443428767 ps
CPU time 119.85 seconds
Started Oct 04 03:10:32 PM PDT 23
Finished Oct 04 03:12:32 PM PDT 23
Peak memory 236780 kb
Host smart-64adae57-a244-4f1b-82af-1ba262fc71e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518350187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1518350187
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3638390977
Short name T325
Test name
Test status
Simulation time 3254265527 ps
CPU time 16.39 seconds
Started Oct 04 03:09:22 PM PDT 23
Finished Oct 04 03:09:39 PM PDT 23
Peak memory 213304 kb
Host smart-5b8d7ff3-c7f4-4c1d-ba3d-a99496e9c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638390977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3638390977
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1188258723
Short name T242
Test name
Test status
Simulation time 1280037875 ps
CPU time 22.39 seconds
Started Oct 04 03:10:09 PM PDT 23
Finished Oct 04 03:10:31 PM PDT 23
Peak memory 215208 kb
Host smart-ae0722a9-7f9e-4096-be22-02cb21348800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188258723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1188258723
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1786819785
Short name T381
Test name
Test status
Simulation time 99970408249 ps
CPU time 3102.8 seconds
Started Oct 04 03:09:34 PM PDT 23
Finished Oct 04 04:01:17 PM PDT 23
Peak memory 229240 kb
Host smart-a871a801-f1c7-4232-b0ab-02f8bc552e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786819785 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1786819785
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1073994073
Short name T234
Test name
Test status
Simulation time 463167498 ps
CPU time 4.31 seconds
Started Oct 04 03:11:25 PM PDT 23
Finished Oct 04 03:11:30 PM PDT 23
Peak memory 211144 kb
Host smart-92e48303-977f-4c51-b386-92e7b5e0987a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073994073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1073994073
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1942268118
Short name T388
Test name
Test status
Simulation time 4642925310 ps
CPU time 149.83 seconds
Started Oct 04 03:11:26 PM PDT 23
Finished Oct 04 03:13:57 PM PDT 23
Peak memory 237132 kb
Host smart-3f8e9d96-1586-4582-9563-b49d823ce28b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942268118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1942268118
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1390016823
Short name T374
Test name
Test status
Simulation time 3346681335 ps
CPU time 14.49 seconds
Started Oct 04 03:10:01 PM PDT 23
Finished Oct 04 03:10:16 PM PDT 23
Peak memory 211132 kb
Host smart-92987b36-4c0f-4ef3-8e69-115021ce283b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1390016823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1390016823
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.681192279
Short name T197
Test name
Test status
Simulation time 2171691151 ps
CPU time 25.07 seconds
Started Oct 04 03:08:36 PM PDT 23
Finished Oct 04 03:09:02 PM PDT 23
Peak memory 212140 kb
Host smart-b02dd18e-4782-4bb9-944f-e0630968ef8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681192279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.681192279
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.742211868
Short name T260
Test name
Test status
Simulation time 4307481085 ps
CPU time 45.85 seconds
Started Oct 04 03:08:54 PM PDT 23
Finished Oct 04 03:09:40 PM PDT 23
Peak memory 212668 kb
Host smart-d78072f6-e9f9-46c1-a978-bbb43f206f06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742211868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.742211868
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2301059750
Short name T300
Test name
Test status
Simulation time 5828381650 ps
CPU time 12.94 seconds
Started Oct 04 03:11:51 PM PDT 23
Finished Oct 04 03:12:04 PM PDT 23
Peak memory 211148 kb
Host smart-ba2c8f7a-d1c2-4b9b-b8a6-3fdd1fc62e4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301059750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2301059750
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3656075986
Short name T250
Test name
Test status
Simulation time 6479457827 ps
CPU time 145.82 seconds
Started Oct 04 03:11:33 PM PDT 23
Finished Oct 04 03:14:00 PM PDT 23
Peak memory 212120 kb
Host smart-54adf08f-b4e4-4bb4-b495-78085af50d5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656075986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3656075986
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1486447349
Short name T264
Test name
Test status
Simulation time 755046193 ps
CPU time 10.09 seconds
Started Oct 04 03:11:26 PM PDT 23
Finished Oct 04 03:11:37 PM PDT 23
Peak memory 211084 kb
Host smart-12296796-ec7a-45af-92d1-752835bc0e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486447349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1486447349
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3101667955
Short name T394
Test name
Test status
Simulation time 177360770 ps
CPU time 7.04 seconds
Started Oct 04 03:12:12 PM PDT 23
Finished Oct 04 03:12:19 PM PDT 23
Peak memory 211104 kb
Host smart-29b9c87f-9ef6-43d4-aa6b-01114bfef091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3101667955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3101667955
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1344859092
Short name T313
Test name
Test status
Simulation time 9300483556 ps
CPU time 17.56 seconds
Started Oct 04 03:11:08 PM PDT 23
Finished Oct 04 03:11:26 PM PDT 23
Peak memory 213536 kb
Host smart-c5be543f-ce7c-4463-8c86-32ef5dd885dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344859092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1344859092
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3673495398
Short name T385
Test name
Test status
Simulation time 686287335 ps
CPU time 31.88 seconds
Started Oct 04 03:10:00 PM PDT 23
Finished Oct 04 03:10:32 PM PDT 23
Peak memory 215480 kb
Host smart-f570e0d2-4cee-4f27-a8b4-40480050eea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673495398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3673495398
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3274744075
Short name T297
Test name
Test status
Simulation time 1379250693 ps
CPU time 6.85 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:08 PM PDT 23
Peak memory 211092 kb
Host smart-2feaaba9-bd62-4d10-9205-4c8474dee39e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274744075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3274744075
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.1079103152
Short name T52
Test name
Test status
Simulation time 108394010617 ps
CPU time 294.54 seconds
Started Oct 04 03:08:51 PM PDT 23
Finished Oct 04 03:13:46 PM PDT 23
Peak memory 228588 kb
Host smart-b4192da2-e69c-42b2-adfc-cde7caa10916
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079103152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.1079103152
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3866732647
Short name T225
Test name
Test status
Simulation time 6119327229 ps
CPU time 18.34 seconds
Started Oct 04 03:11:51 PM PDT 23
Finished Oct 04 03:12:10 PM PDT 23
Peak memory 211912 kb
Host smart-5af5619c-1a2e-4026-9daf-e8f9b39f2448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866732647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3866732647
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3865012498
Short name T348
Test name
Test status
Simulation time 1903783271 ps
CPU time 16.8 seconds
Started Oct 04 03:10:07 PM PDT 23
Finished Oct 04 03:10:24 PM PDT 23
Peak memory 211096 kb
Host smart-c928ea1d-7c59-4cb0-a0c5-feb869cf7ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865012498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3865012498
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2294496133
Short name T179
Test name
Test status
Simulation time 616562939 ps
CPU time 14.72 seconds
Started Oct 04 03:08:50 PM PDT 23
Finished Oct 04 03:09:06 PM PDT 23
Peak memory 212016 kb
Host smart-1e644959-06e4-4d37-a9ff-aff65a35b369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294496133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2294496133
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3149019665
Short name T243
Test name
Test status
Simulation time 6845694592 ps
CPU time 63.1 seconds
Started Oct 04 03:14:14 PM PDT 23
Finished Oct 04 03:15:18 PM PDT 23
Peak memory 215672 kb
Host smart-5f074bef-51cb-44fe-96c0-8ec1b1f91f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149019665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3149019665
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1793269187
Short name T293
Test name
Test status
Simulation time 49055546659 ps
CPU time 697.92 seconds
Started Oct 04 03:09:19 PM PDT 23
Finished Oct 04 03:20:57 PM PDT 23
Peak memory 227668 kb
Host smart-994fa5c8-bdfe-43fa-a85c-316a97de4073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793269187 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1793269187
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2299333486
Short name T262
Test name
Test status
Simulation time 837256934 ps
CPU time 6.97 seconds
Started Oct 04 03:09:40 PM PDT 23
Finished Oct 04 03:09:47 PM PDT 23
Peak memory 210916 kb
Host smart-89bef762-f36a-4539-bc0b-fc9d8efef18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299333486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2299333486
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1908263635
Short name T3
Test name
Test status
Simulation time 9129027171 ps
CPU time 145.04 seconds
Started Oct 04 03:09:28 PM PDT 23
Finished Oct 04 03:11:53 PM PDT 23
Peak memory 236272 kb
Host smart-c74b8de9-e28d-4274-80b6-1fe1fae52b45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908263635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1908263635
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1376768759
Short name T395
Test name
Test status
Simulation time 582150531 ps
CPU time 14.05 seconds
Started Oct 04 03:09:21 PM PDT 23
Finished Oct 04 03:09:35 PM PDT 23
Peak memory 211228 kb
Host smart-e5578379-1760-43bd-87b9-9a30508afe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376768759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1376768759
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1318604066
Short name T343
Test name
Test status
Simulation time 2801609761 ps
CPU time 12.29 seconds
Started Oct 04 03:10:06 PM PDT 23
Finished Oct 04 03:10:18 PM PDT 23
Peak memory 211028 kb
Host smart-7e5ce013-d9a2-4879-a6cd-0efefb696511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318604066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1318604066
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1228108491
Short name T426
Test name
Test status
Simulation time 374680353 ps
CPU time 10.9 seconds
Started Oct 04 03:12:13 PM PDT 23
Finished Oct 04 03:12:24 PM PDT 23
Peak memory 211908 kb
Host smart-c5f9b871-c147-4886-a401-0acc6551e370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228108491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1228108491
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3780517748
Short name T235
Test name
Test status
Simulation time 13429324905 ps
CPU time 65.77 seconds
Started Oct 04 03:13:23 PM PDT 23
Finished Oct 04 03:14:29 PM PDT 23
Peak memory 214820 kb
Host smart-545f12a6-de40-4f80-a783-591a548f44ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780517748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3780517748
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.599547908
Short name T346
Test name
Test status
Simulation time 85635636 ps
CPU time 4.56 seconds
Started Oct 04 03:12:16 PM PDT 23
Finished Oct 04 03:12:21 PM PDT 23
Peak memory 211068 kb
Host smart-0208962d-410d-4ea9-a22f-c8bf904914b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599547908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.599547908
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3827885954
Short name T265
Test name
Test status
Simulation time 13543626833 ps
CPU time 172.18 seconds
Started Oct 04 03:09:47 PM PDT 23
Finished Oct 04 03:12:40 PM PDT 23
Peak memory 237792 kb
Host smart-5bf62c55-9bd2-4999-aab6-c2e2d060953e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827885954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3827885954
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3629023596
Short name T182
Test name
Test status
Simulation time 3076712026 ps
CPU time 27.62 seconds
Started Oct 04 03:10:54 PM PDT 23
Finished Oct 04 03:11:22 PM PDT 23
Peak memory 211304 kb
Host smart-2c87e1b9-482d-4355-b8e1-65d973269d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629023596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3629023596
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1235586150
Short name T205
Test name
Test status
Simulation time 101948367 ps
CPU time 6.14 seconds
Started Oct 04 03:13:20 PM PDT 23
Finished Oct 04 03:13:27 PM PDT 23
Peak memory 211004 kb
Host smart-39961593-94ee-4186-8d27-342e892bcc30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1235586150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1235586150
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3543264503
Short name T350
Test name
Test status
Simulation time 11812007034 ps
CPU time 31.68 seconds
Started Oct 04 03:09:30 PM PDT 23
Finished Oct 04 03:10:02 PM PDT 23
Peak memory 213236 kb
Host smart-6c3ad8fb-5e74-47cd-b144-0d2420e14820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543264503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3543264503
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.201169367
Short name T390
Test name
Test status
Simulation time 7122850063 ps
CPU time 71.65 seconds
Started Oct 04 03:10:52 PM PDT 23
Finished Oct 04 03:12:04 PM PDT 23
Peak memory 216132 kb
Host smart-3d9a96c3-de36-4ecf-83aa-fe14da51e83e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201169367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.201169367
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2824143382
Short name T183
Test name
Test status
Simulation time 14054537973 ps
CPU time 736.7 seconds
Started Oct 04 03:09:25 PM PDT 23
Finished Oct 04 03:21:44 PM PDT 23
Peak memory 227556 kb
Host smart-134d4595-5324-46ff-9339-2de55e08e635
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824143382 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2824143382
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2446011124
Short name T329
Test name
Test status
Simulation time 1629454797 ps
CPU time 14.45 seconds
Started Oct 04 03:08:52 PM PDT 23
Finished Oct 04 03:09:07 PM PDT 23
Peak memory 211156 kb
Host smart-4f683ab8-ee01-46cb-959a-885a2fcdab82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446011124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2446011124
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2250893830
Short name T157
Test name
Test status
Simulation time 18829512596 ps
CPU time 33.03 seconds
Started Oct 04 03:09:20 PM PDT 23
Finished Oct 04 03:09:54 PM PDT 23
Peak memory 211480 kb
Host smart-b100062d-8937-4550-8d31-0d41ed012d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250893830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2250893830
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.177063214
Short name T378
Test name
Test status
Simulation time 15839619496 ps
CPU time 12.4 seconds
Started Oct 04 03:08:58 PM PDT 23
Finished Oct 04 03:09:11 PM PDT 23
Peak memory 211188 kb
Host smart-ff2031ac-dbd1-463b-a074-12f95f7ec87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=177063214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.177063214
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1129528838
Short name T176
Test name
Test status
Simulation time 1037171488 ps
CPU time 10.14 seconds
Started Oct 04 03:09:34 PM PDT 23
Finished Oct 04 03:09:44 PM PDT 23
Peak memory 212856 kb
Host smart-4f3a5c38-ee25-4624-9f7b-543fc817b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129528838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1129528838
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1228053406
Short name T257
Test name
Test status
Simulation time 36137953230 ps
CPU time 46.62 seconds
Started Oct 04 03:10:53 PM PDT 23
Finished Oct 04 03:11:39 PM PDT 23
Peak memory 213960 kb
Host smart-cc4c5869-1e36-4c11-9619-627e0d36e5ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228053406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1228053406
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1790520965
Short name T170
Test name
Test status
Simulation time 161760909614 ps
CPU time 7898.14 seconds
Started Oct 04 03:11:51 PM PDT 23
Finished Oct 04 05:23:30 PM PDT 23
Peak memory 235836 kb
Host smart-51070c41-8d9a-45bc-adb0-d4457cf30f5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790520965 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1790520965
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1553447175
Short name T38
Test name
Test status
Simulation time 309100127 ps
CPU time 4.41 seconds
Started Oct 04 03:09:52 PM PDT 23
Finished Oct 04 03:09:57 PM PDT 23
Peak memory 211044 kb
Host smart-737a73e8-6aa8-4ca2-b8f1-fcad6a4fd04d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553447175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1553447175
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1757766617
Short name T271
Test name
Test status
Simulation time 47841430133 ps
CPU time 227.8 seconds
Started Oct 04 03:08:52 PM PDT 23
Finished Oct 04 03:12:40 PM PDT 23
Peak memory 228536 kb
Host smart-fab0a529-d404-41d2-9cfb-6a6582480431
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757766617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1757766617
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4170855064
Short name T17
Test name
Test status
Simulation time 177540774 ps
CPU time 9.71 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:08:47 PM PDT 23
Peak memory 211128 kb
Host smart-1d2d1165-a778-43e7-a63e-40f88758704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170855064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4170855064
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.45919179
Short name T186
Test name
Test status
Simulation time 911320471 ps
CPU time 10.93 seconds
Started Oct 04 03:08:34 PM PDT 23
Finished Oct 04 03:08:45 PM PDT 23
Peak memory 211092 kb
Host smart-8ea48d52-409d-4826-8f4a-995ad88fc75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45919179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.45919179
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3994531307
Short name T406
Test name
Test status
Simulation time 189495555 ps
CPU time 10.63 seconds
Started Oct 04 03:12:50 PM PDT 23
Finished Oct 04 03:13:01 PM PDT 23
Peak memory 212252 kb
Host smart-5b933697-243a-4467-a9f2-a2fb9c70448e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994531307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3994531307
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.4221416432
Short name T360
Test name
Test status
Simulation time 13910070169 ps
CPU time 39.15 seconds
Started Oct 04 03:10:43 PM PDT 23
Finished Oct 04 03:11:23 PM PDT 23
Peak memory 216748 kb
Host smart-76a02858-64f2-40f6-9ebc-e8d19e652366
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221416432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.4221416432
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3015783356
Short name T276
Test name
Test status
Simulation time 1953279878 ps
CPU time 15.49 seconds
Started Oct 04 03:11:31 PM PDT 23
Finished Oct 04 03:11:47 PM PDT 23
Peak memory 211004 kb
Host smart-17b30ff7-fc95-480c-ac04-356571452222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015783356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3015783356
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1480732607
Short name T239
Test name
Test status
Simulation time 206350619589 ps
CPU time 219.44 seconds
Started Oct 04 03:09:56 PM PDT 23
Finished Oct 04 03:13:36 PM PDT 23
Peak memory 228492 kb
Host smart-106614cf-5522-4f24-91f3-b8799a7cf4cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480732607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1480732607
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.133596125
Short name T366
Test name
Test status
Simulation time 8716258817 ps
CPU time 35.21 seconds
Started Oct 04 03:09:33 PM PDT 23
Finished Oct 04 03:10:08 PM PDT 23
Peak memory 211408 kb
Host smart-fccd140e-dc59-4dac-b524-c00591064d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133596125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.133596125
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2750208747
Short name T400
Test name
Test status
Simulation time 6251111469 ps
CPU time 13.65 seconds
Started Oct 04 03:13:12 PM PDT 23
Finished Oct 04 03:13:26 PM PDT 23
Peak memory 210780 kb
Host smart-01327a7d-fcec-4e74-920a-f49e94e5df43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750208747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2750208747
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3099359095
Short name T421
Test name
Test status
Simulation time 5743637423 ps
CPU time 30.86 seconds
Started Oct 04 03:09:10 PM PDT 23
Finished Oct 04 03:09:41 PM PDT 23
Peak memory 212700 kb
Host smart-ab0ea693-3e8a-4b49-8a4c-1536acbe22bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099359095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3099359095
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2969063054
Short name T47
Test name
Test status
Simulation time 11828284591 ps
CPU time 32.95 seconds
Started Oct 04 03:09:04 PM PDT 23
Finished Oct 04 03:09:37 PM PDT 23
Peak memory 214392 kb
Host smart-6717f4a1-2696-409b-b723-3ae8f8cce662
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969063054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2969063054
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.4179404456
Short name T153
Test name
Test status
Simulation time 50478786489 ps
CPU time 709.18 seconds
Started Oct 04 03:10:04 PM PDT 23
Finished Oct 04 03:21:54 PM PDT 23
Peak memory 232516 kb
Host smart-41414ff3-2611-4285-89a1-5dbb6a304272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179404456 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.4179404456
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1457184175
Short name T384
Test name
Test status
Simulation time 7571165174 ps
CPU time 16.41 seconds
Started Oct 04 03:08:33 PM PDT 23
Finished Oct 04 03:08:50 PM PDT 23
Peak memory 211220 kb
Host smart-b5096c77-e3a4-4c7b-af74-1bacdb588180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457184175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1457184175
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3330223001
Short name T356
Test name
Test status
Simulation time 65029639152 ps
CPU time 264.3 seconds
Started Oct 04 03:09:04 PM PDT 23
Finished Oct 04 03:13:29 PM PDT 23
Peak memory 234832 kb
Host smart-ce402b93-f9e6-4786-80d9-c970be98d227
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330223001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3330223001
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3690668101
Short name T415
Test name
Test status
Simulation time 3961938119 ps
CPU time 33.08 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:09:10 PM PDT 23
Peak memory 211396 kb
Host smart-e5ca056f-dcdd-4d2a-8d74-326132dbcad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690668101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3690668101
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2243082363
Short name T273
Test name
Test status
Simulation time 1576971308 ps
CPU time 14.14 seconds
Started Oct 04 03:08:32 PM PDT 23
Finished Oct 04 03:08:47 PM PDT 23
Peak memory 210992 kb
Host smart-ec2d668e-6cb2-47e6-b2e6-31e10b574e1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2243082363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2243082363
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3530160835
Short name T173
Test name
Test status
Simulation time 10928411547 ps
CPU time 27.01 seconds
Started Oct 04 03:09:41 PM PDT 23
Finished Oct 04 03:10:14 PM PDT 23
Peak memory 213696 kb
Host smart-310a0ef2-3c22-4293-adab-90f10f0a40e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530160835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3530160835
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3721232686
Short name T303
Test name
Test status
Simulation time 2262157001 ps
CPU time 32.48 seconds
Started Oct 04 03:08:36 PM PDT 23
Finished Oct 04 03:09:09 PM PDT 23
Peak memory 215660 kb
Host smart-c9eccc66-60bd-49d3-8da4-73caeba9a143
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721232686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3721232686
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3453754809
Short name T212
Test name
Test status
Simulation time 2146016130 ps
CPU time 17.23 seconds
Started Oct 04 03:09:15 PM PDT 23
Finished Oct 04 03:09:32 PM PDT 23
Peak memory 211104 kb
Host smart-4317256a-97c9-4a94-b60b-0122b5c924d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453754809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3453754809
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1396683874
Short name T416
Test name
Test status
Simulation time 152129518182 ps
CPU time 198.79 seconds
Started Oct 04 03:15:01 PM PDT 23
Finished Oct 04 03:18:21 PM PDT 23
Peak memory 228320 kb
Host smart-80acda45-2a31-44d2-a961-c0202ecb2c2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396683874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1396683874
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1446726507
Short name T275
Test name
Test status
Simulation time 693346593 ps
CPU time 9.48 seconds
Started Oct 04 03:08:33 PM PDT 23
Finished Oct 04 03:08:43 PM PDT 23
Peak memory 211296 kb
Host smart-6fb24e39-9c98-4c2e-935b-4f361d6a05a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446726507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1446726507
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.718962226
Short name T161
Test name
Test status
Simulation time 2299811768 ps
CPU time 17.61 seconds
Started Oct 04 03:09:54 PM PDT 23
Finished Oct 04 03:10:12 PM PDT 23
Peak memory 211304 kb
Host smart-31f88cf6-68c2-491e-aa36-693d599d33ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=718962226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.718962226
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4233394689
Short name T210
Test name
Test status
Simulation time 2232822975 ps
CPU time 13.77 seconds
Started Oct 04 03:09:18 PM PDT 23
Finished Oct 04 03:09:32 PM PDT 23
Peak memory 212196 kb
Host smart-ce9d2553-84b3-407e-be49-106c927ef575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233394689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4233394689
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.860773330
Short name T220
Test name
Test status
Simulation time 41879104983 ps
CPU time 87.73 seconds
Started Oct 04 03:11:26 PM PDT 23
Finished Oct 04 03:12:54 PM PDT 23
Peak memory 217232 kb
Host smart-6c3adc41-c66f-4383-a294-d89416c80c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860773330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.860773330
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3203576930
Short name T357
Test name
Test status
Simulation time 140477459 ps
CPU time 4.52 seconds
Started Oct 04 03:09:19 PM PDT 23
Finished Oct 04 03:09:25 PM PDT 23
Peak memory 211188 kb
Host smart-aa69757f-7c24-4a29-83bb-4ad40d71f38c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203576930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3203576930
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.185689581
Short name T215
Test name
Test status
Simulation time 40839822619 ps
CPU time 450.57 seconds
Started Oct 04 03:10:38 PM PDT 23
Finished Oct 04 03:18:10 PM PDT 23
Peak memory 237668 kb
Host smart-2e833083-cda1-419e-9abb-408587ff6fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185689581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.185689581
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.347604674
Short name T204
Test name
Test status
Simulation time 2784680642 ps
CPU time 25.42 seconds
Started Oct 04 03:11:36 PM PDT 23
Finished Oct 04 03:12:02 PM PDT 23
Peak memory 211372 kb
Host smart-764ba341-598d-4dce-aebc-b86dd540456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347604674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.347604674
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3445512065
Short name T100
Test name
Test status
Simulation time 807177194 ps
CPU time 9.66 seconds
Started Oct 04 03:09:30 PM PDT 23
Finished Oct 04 03:09:40 PM PDT 23
Peak memory 211080 kb
Host smart-fa3d8726-e469-403c-b6d6-30a058267d68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445512065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3445512065
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1022966420
Short name T35
Test name
Test status
Simulation time 851565892 ps
CPU time 56.58 seconds
Started Oct 04 03:08:15 PM PDT 23
Finished Oct 04 03:09:13 PM PDT 23
Peak memory 236624 kb
Host smart-ed6e5600-48b6-432e-8bb5-af707ecbf1ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022966420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1022966420
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1707316172
Short name T392
Test name
Test status
Simulation time 21376116078 ps
CPU time 23.02 seconds
Started Oct 04 03:09:29 PM PDT 23
Finished Oct 04 03:09:53 PM PDT 23
Peak memory 213328 kb
Host smart-1043dbac-bcf4-4d38-82d1-601808fd7de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707316172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1707316172
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4251056329
Short name T402
Test name
Test status
Simulation time 7163130572 ps
CPU time 40.05 seconds
Started Oct 04 03:09:42 PM PDT 23
Finished Oct 04 03:10:23 PM PDT 23
Peak memory 213000 kb
Host smart-4ed153d2-3380-4848-bfbd-0acff3c2eb55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251056329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.4251056329
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2409233985
Short name T167
Test name
Test status
Simulation time 29506332106 ps
CPU time 996.25 seconds
Started Oct 04 03:09:42 PM PDT 23
Finished Oct 04 03:26:19 PM PDT 23
Peak memory 235876 kb
Host smart-c33e1bae-fd3d-41e8-9448-84c0b1cf38db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409233985 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2409233985
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2403573367
Short name T39
Test name
Test status
Simulation time 6099488033 ps
CPU time 13.19 seconds
Started Oct 04 03:08:35 PM PDT 23
Finished Oct 04 03:08:49 PM PDT 23
Peak memory 211120 kb
Host smart-f1bf36d4-e518-462c-b6c0-8885d55fb458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403573367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2403573367
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.650001941
Short name T405
Test name
Test status
Simulation time 40324488651 ps
CPU time 184.28 seconds
Started Oct 04 03:13:48 PM PDT 23
Finished Oct 04 03:16:53 PM PDT 23
Peak memory 212376 kb
Host smart-e612a03b-b12e-4ab9-9782-8268b4bbed61
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650001941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.650001941
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3380758871
Short name T22
Test name
Test status
Simulation time 426691151 ps
CPU time 12.41 seconds
Started Oct 04 03:10:21 PM PDT 23
Finished Oct 04 03:10:34 PM PDT 23
Peak memory 211108 kb
Host smart-6864f326-5e22-4716-8241-15263a1cc34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380758871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3380758871
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3345784011
Short name T203
Test name
Test status
Simulation time 2623025331 ps
CPU time 13.1 seconds
Started Oct 04 03:09:51 PM PDT 23
Finished Oct 04 03:10:05 PM PDT 23
Peak memory 211172 kb
Host smart-b7a5303a-32ca-49b4-a02c-000f9d5eb70f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345784011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3345784011
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.426933822
Short name T363
Test name
Test status
Simulation time 193419520 ps
CPU time 10.7 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:08:48 PM PDT 23
Peak memory 212572 kb
Host smart-e11db33f-f356-4d69-869a-46d742a69ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426933822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.426933822
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3014509027
Short name T306
Test name
Test status
Simulation time 2754812566 ps
CPU time 29.64 seconds
Started Oct 04 03:08:39 PM PDT 23
Finished Oct 04 03:09:09 PM PDT 23
Peak memory 213308 kb
Host smart-acc6d159-c4bd-4132-b8dd-2cd790ba759e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014509027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3014509027
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.65111899
Short name T284
Test name
Test status
Simulation time 170801032106 ps
CPU time 3651.56 seconds
Started Oct 04 03:08:33 PM PDT 23
Finished Oct 04 04:09:25 PM PDT 23
Peak memory 235752 kb
Host smart-504bf981-6925-461c-a4bf-92f5413fe850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65111899 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.65111899
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1250194136
Short name T309
Test name
Test status
Simulation time 161742741 ps
CPU time 4.27 seconds
Started Oct 04 03:08:55 PM PDT 23
Finished Oct 04 03:09:00 PM PDT 23
Peak memory 211108 kb
Host smart-d4bccc1e-2ed5-466d-9281-3499fce6f940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250194136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1250194136
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3898555530
Short name T422
Test name
Test status
Simulation time 2348587790 ps
CPU time 123.01 seconds
Started Oct 04 03:08:51 PM PDT 23
Finished Oct 04 03:10:54 PM PDT 23
Peak memory 236312 kb
Host smart-27cda4e3-bb69-4383-a01a-9e78a8f2f637
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898555530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3898555530
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3304607983
Short name T4
Test name
Test status
Simulation time 723338467 ps
CPU time 9.72 seconds
Started Oct 04 03:12:11 PM PDT 23
Finished Oct 04 03:12:21 PM PDT 23
Peak memory 211072 kb
Host smart-a7341e7a-e74f-440f-8173-6642f868e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304607983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3304607983
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1884750450
Short name T163
Test name
Test status
Simulation time 193627884 ps
CPU time 5.64 seconds
Started Oct 04 03:09:54 PM PDT 23
Finished Oct 04 03:10:00 PM PDT 23
Peak memory 210976 kb
Host smart-aaf7da8b-e552-4953-8125-e4af308277d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884750450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1884750450
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1121016090
Short name T236
Test name
Test status
Simulation time 5711353802 ps
CPU time 29.16 seconds
Started Oct 04 03:08:41 PM PDT 23
Finished Oct 04 03:09:11 PM PDT 23
Peak memory 212940 kb
Host smart-ecfea615-e332-4a22-b633-ad7abe2e5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121016090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1121016090
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1764376735
Short name T255
Test name
Test status
Simulation time 6186417739 ps
CPU time 40.23 seconds
Started Oct 04 03:08:38 PM PDT 23
Finished Oct 04 03:09:19 PM PDT 23
Peak memory 216372 kb
Host smart-7d35db40-bf73-484f-a268-6e13f837985a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764376735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1764376735
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.410521637
Short name T11
Test name
Test status
Simulation time 48920630920 ps
CPU time 1959.86 seconds
Started Oct 04 03:08:41 PM PDT 23
Finished Oct 04 03:41:22 PM PDT 23
Peak memory 243968 kb
Host smart-44aae3dc-a443-4cbb-b396-acf17827b221
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410521637 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.410521637
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2481254123
Short name T46
Test name
Test status
Simulation time 500636622 ps
CPU time 7.74 seconds
Started Oct 04 03:08:50 PM PDT 23
Finished Oct 04 03:08:59 PM PDT 23
Peak memory 211000 kb
Host smart-dc2783ee-f43a-4ea9-b6a2-93a328449d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481254123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2481254123
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3608127045
Short name T414
Test name
Test status
Simulation time 6965925271 ps
CPU time 130.71 seconds
Started Oct 04 03:14:14 PM PDT 23
Finished Oct 04 03:16:26 PM PDT 23
Peak memory 212140 kb
Host smart-42dfbe50-0b88-476d-ba60-975af3e181e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608127045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3608127045
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3973732428
Short name T159
Test name
Test status
Simulation time 8194309259 ps
CPU time 21.96 seconds
Started Oct 04 03:13:02 PM PDT 23
Finished Oct 04 03:13:25 PM PDT 23
Peak memory 211948 kb
Host smart-1a0e2d5e-f3c0-4728-9194-c5d5990ca47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973732428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3973732428
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1267617517
Short name T91
Test name
Test status
Simulation time 1740475499 ps
CPU time 15.63 seconds
Started Oct 04 03:10:02 PM PDT 23
Finished Oct 04 03:10:18 PM PDT 23
Peak memory 211016 kb
Host smart-6e272f97-cc34-4410-abd0-13a913ca6444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267617517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1267617517
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.787552092
Short name T424
Test name
Test status
Simulation time 3437419560 ps
CPU time 28.79 seconds
Started Oct 04 03:08:41 PM PDT 23
Finished Oct 04 03:09:10 PM PDT 23
Peak memory 212636 kb
Host smart-1c8cdb70-032b-4dbc-8025-f5b742736d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787552092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.787552092
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3079018103
Short name T103
Test name
Test status
Simulation time 9421253383 ps
CPU time 83.12 seconds
Started Oct 04 03:09:56 PM PDT 23
Finished Oct 04 03:11:20 PM PDT 23
Peak memory 217384 kb
Host smart-67172933-2ca8-49b8-9c71-407f40400f7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079018103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3079018103
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.831209935
Short name T43
Test name
Test status
Simulation time 1229971505 ps
CPU time 9.64 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:11 PM PDT 23
Peak memory 211028 kb
Host smart-58805660-9a8d-4350-b031-4773d4311f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831209935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.831209935
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.970969098
Short name T218
Test name
Test status
Simulation time 16415933712 ps
CPU time 169 seconds
Started Oct 04 03:09:11 PM PDT 23
Finished Oct 04 03:12:00 PM PDT 23
Peak memory 237852 kb
Host smart-555f76fa-32b2-491f-af36-8df13e9b5529
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970969098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.970969098
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.49463541
Short name T174
Test name
Test status
Simulation time 370164748 ps
CPU time 9.8 seconds
Started Oct 04 03:08:55 PM PDT 23
Finished Oct 04 03:09:05 PM PDT 23
Peak memory 211012 kb
Host smart-92612e0b-ab37-4b67-ab70-248f4a0adf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49463541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.49463541
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.985755075
Short name T244
Test name
Test status
Simulation time 431422949 ps
CPU time 8.22 seconds
Started Oct 04 03:10:07 PM PDT 23
Finished Oct 04 03:10:15 PM PDT 23
Peak memory 211048 kb
Host smart-02c86d32-5c5f-4044-98ee-cc88d457c8de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985755075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.985755075
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3043851410
Short name T256
Test name
Test status
Simulation time 4458481443 ps
CPU time 42.23 seconds
Started Oct 04 03:08:35 PM PDT 23
Finished Oct 04 03:09:18 PM PDT 23
Peak memory 212652 kb
Host smart-ae728a50-2b6b-458c-95b6-1bb3ed6ee603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043851410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3043851410
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2504326456
Short name T279
Test name
Test status
Simulation time 13007297141 ps
CPU time 108.71 seconds
Started Oct 04 03:08:39 PM PDT 23
Finished Oct 04 03:10:28 PM PDT 23
Peak memory 217300 kb
Host smart-07051a3f-6d6f-4b20-be30-a3ed2d7c47cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504326456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2504326456
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2078335729
Short name T151
Test name
Test status
Simulation time 20633008924 ps
CPU time 1778.93 seconds
Started Oct 04 03:08:30 PM PDT 23
Finished Oct 04 03:38:09 PM PDT 23
Peak memory 220708 kb
Host smart-1d7d913d-b7fa-4321-8488-0ef48358ad68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078335729 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2078335729
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.945111009
Short name T358
Test name
Test status
Simulation time 2241343792 ps
CPU time 6.36 seconds
Started Oct 04 03:09:26 PM PDT 23
Finished Oct 04 03:09:33 PM PDT 23
Peak memory 211100 kb
Host smart-27076e91-932c-42de-9421-4c0e71283ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945111009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.945111009
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.535461538
Short name T307
Test name
Test status
Simulation time 85393060693 ps
CPU time 385.44 seconds
Started Oct 04 03:08:40 PM PDT 23
Finished Oct 04 03:15:06 PM PDT 23
Peak memory 213380 kb
Host smart-abf9f4e8-05ad-41ea-a459-b67cb9dbf2e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535461538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.535461538
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3826380654
Short name T308
Test name
Test status
Simulation time 691143074 ps
CPU time 9.7 seconds
Started Oct 04 03:08:53 PM PDT 23
Finished Oct 04 03:09:03 PM PDT 23
Peak memory 211228 kb
Host smart-79f23f80-0b67-422d-8025-b3017a260621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826380654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3826380654
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3446473235
Short name T368
Test name
Test status
Simulation time 4591052473 ps
CPU time 15.79 seconds
Started Oct 04 03:09:43 PM PDT 23
Finished Oct 04 03:09:59 PM PDT 23
Peak memory 211316 kb
Host smart-4aaea44f-a1fc-4424-a5f9-99b09854d612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3446473235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3446473235
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3606889050
Short name T252
Test name
Test status
Simulation time 3632356451 ps
CPU time 37.86 seconds
Started Oct 04 03:09:55 PM PDT 23
Finished Oct 04 03:10:34 PM PDT 23
Peak memory 212480 kb
Host smart-75317ea5-795b-49b4-82d4-5e3ae60c6d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606889050 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3606889050
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.4247528583
Short name T299
Test name
Test status
Simulation time 2883986674 ps
CPU time 31.74 seconds
Started Oct 04 03:14:37 PM PDT 23
Finished Oct 04 03:15:09 PM PDT 23
Peak memory 214336 kb
Host smart-0f700fce-0471-4301-a35f-7f7d869b3aad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247528583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.4247528583
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1427022724
Short name T45
Test name
Test status
Simulation time 415871108 ps
CPU time 7.86 seconds
Started Oct 04 03:10:59 PM PDT 23
Finished Oct 04 03:11:07 PM PDT 23
Peak memory 211016 kb
Host smart-e719c3b1-3719-484f-a1f7-e4034eb96235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427022724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1427022724
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1494455567
Short name T160
Test name
Test status
Simulation time 79435435815 ps
CPU time 250.85 seconds
Started Oct 04 03:08:57 PM PDT 23
Finished Oct 04 03:13:09 PM PDT 23
Peak memory 224940 kb
Host smart-8a73aed1-a28b-4914-8951-da2406d113f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494455567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1494455567
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3754274346
Short name T349
Test name
Test status
Simulation time 691139386 ps
CPU time 9.8 seconds
Started Oct 04 03:09:04 PM PDT 23
Finished Oct 04 03:09:14 PM PDT 23
Peak memory 211208 kb
Host smart-b33cc235-0d31-4de6-8e9a-f3b841e0d6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754274346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3754274346
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.364146673
Short name T274
Test name
Test status
Simulation time 340508038 ps
CPU time 5.49 seconds
Started Oct 04 03:09:11 PM PDT 23
Finished Oct 04 03:09:17 PM PDT 23
Peak memory 210980 kb
Host smart-37740c9a-559a-4acd-b6ac-c4a20bec3660
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364146673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.364146673
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.423598377
Short name T393
Test name
Test status
Simulation time 13606585185 ps
CPU time 29.14 seconds
Started Oct 04 03:10:14 PM PDT 23
Finished Oct 04 03:10:43 PM PDT 23
Peak memory 213560 kb
Host smart-d0200a17-7b9d-402a-a09d-9b243b594b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423598377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.423598377
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4189144455
Short name T314
Test name
Test status
Simulation time 820345176 ps
CPU time 23.91 seconds
Started Oct 04 03:08:59 PM PDT 23
Finished Oct 04 03:09:23 PM PDT 23
Peak memory 215292 kb
Host smart-192d25f7-124e-4764-986f-7ab7033c244a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189144455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4189144455
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.1888533085
Short name T13
Test name
Test status
Simulation time 282302447556 ps
CPU time 4018.81 seconds
Started Oct 04 03:11:52 PM PDT 23
Finished Oct 04 04:18:52 PM PDT 23
Peak memory 252196 kb
Host smart-a3dda90c-d7af-4f50-81fe-88669495bde0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888533085 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.1888533085
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.559593261
Short name T237
Test name
Test status
Simulation time 3567847941 ps
CPU time 6.62 seconds
Started Oct 04 03:09:20 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 211224 kb
Host smart-cc767743-968e-497e-82e1-36344443457e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559593261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.559593261
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3522328479
Short name T216
Test name
Test status
Simulation time 4247188552 ps
CPU time 132.38 seconds
Started Oct 04 03:10:51 PM PDT 23
Finished Oct 04 03:13:03 PM PDT 23
Peak memory 213352 kb
Host smart-583174f2-f0af-47ee-a44a-3a95dd041f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522328479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3522328479
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2260287750
Short name T23
Test name
Test status
Simulation time 4459152899 ps
CPU time 16.39 seconds
Started Oct 04 03:08:54 PM PDT 23
Finished Oct 04 03:09:11 PM PDT 23
Peak memory 211796 kb
Host smart-e572357b-2975-4a91-8265-e7165e00b20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260287750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2260287750
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3884336535
Short name T272
Test name
Test status
Simulation time 1016092466 ps
CPU time 11.34 seconds
Started Oct 04 03:09:48 PM PDT 23
Finished Oct 04 03:10:00 PM PDT 23
Peak memory 211004 kb
Host smart-42f90438-7ab9-4e4b-b513-0c97cc8e0665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884336535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3884336535
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.355436881
Short name T111
Test name
Test status
Simulation time 3640875803 ps
CPU time 15.8 seconds
Started Oct 04 03:09:29 PM PDT 23
Finished Oct 04 03:09:45 PM PDT 23
Peak memory 213144 kb
Host smart-abbd74b1-81df-4da8-b761-971bfec5ce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355436881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.355436881
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2810013963
Short name T404
Test name
Test status
Simulation time 2401472649 ps
CPU time 15.91 seconds
Started Oct 04 03:14:13 PM PDT 23
Finished Oct 04 03:14:30 PM PDT 23
Peak memory 210284 kb
Host smart-6eb1f600-8dc2-4406-8125-740ccc31dff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810013963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2810013963
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2672956410
Short name T99
Test name
Test status
Simulation time 4587806363 ps
CPU time 11.92 seconds
Started Oct 04 03:09:10 PM PDT 23
Finished Oct 04 03:09:23 PM PDT 23
Peak memory 211160 kb
Host smart-011e0ec1-ed90-4f6b-8b50-0a6c89bbc3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672956410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2672956410
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2429475381
Short name T96
Test name
Test status
Simulation time 32378099470 ps
CPU time 323.21 seconds
Started Oct 04 03:09:28 PM PDT 23
Finished Oct 04 03:14:52 PM PDT 23
Peak memory 227852 kb
Host smart-194d5208-4d65-4f79-89a4-bcc151c0e0e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429475381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2429475381
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.139209730
Short name T188
Test name
Test status
Simulation time 693493133 ps
CPU time 9.48 seconds
Started Oct 04 03:09:25 PM PDT 23
Finished Oct 04 03:09:36 PM PDT 23
Peak memory 211080 kb
Host smart-e63cb547-a436-4475-8dbc-87ecf97013f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139209730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.139209730
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1099914012
Short name T162
Test name
Test status
Simulation time 97980755 ps
CPU time 5.4 seconds
Started Oct 04 03:10:20 PM PDT 23
Finished Oct 04 03:10:25 PM PDT 23
Peak memory 211028 kb
Host smart-94eb24c2-76ee-45f1-a366-180a0e261f16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099914012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1099914012
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.410275776
Short name T280
Test name
Test status
Simulation time 2460512612 ps
CPU time 23.08 seconds
Started Oct 04 03:12:09 PM PDT 23
Finished Oct 04 03:12:32 PM PDT 23
Peak memory 212748 kb
Host smart-768d7a18-d1b7-4989-b806-1fb5ca1b2a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410275776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.410275776
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2075576654
Short name T365
Test name
Test status
Simulation time 6495529950 ps
CPU time 54.83 seconds
Started Oct 04 03:15:12 PM PDT 23
Finished Oct 04 03:16:07 PM PDT 23
Peak memory 213828 kb
Host smart-c4297e1b-ff49-4e61-8c1e-39a1b05d71f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075576654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2075576654
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2642888069
Short name T231
Test name
Test status
Simulation time 1707593499 ps
CPU time 14 seconds
Started Oct 04 03:14:13 PM PDT 23
Finished Oct 04 03:14:28 PM PDT 23
Peak memory 209316 kb
Host smart-ca59333e-c9d9-4ac1-a5be-7aab83ed37e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642888069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2642888069
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.151631042
Short name T361
Test name
Test status
Simulation time 6722424228 ps
CPU time 107.47 seconds
Started Oct 04 03:09:12 PM PDT 23
Finished Oct 04 03:11:00 PM PDT 23
Peak memory 228220 kb
Host smart-f9ee840d-d6d7-415d-8444-4dd7f3d959db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151631042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_c
orrupt_sig_fatal_chk.151631042
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.805966263
Short name T214
Test name
Test status
Simulation time 3732445457 ps
CPU time 31.08 seconds
Started Oct 04 03:09:44 PM PDT 23
Finished Oct 04 03:10:16 PM PDT 23
Peak memory 211400 kb
Host smart-dd21544d-fbbd-4cf8-aa82-65ac6e15b211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805966263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.805966263
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.981689061
Short name T431
Test name
Test status
Simulation time 31834788825 ps
CPU time 14.77 seconds
Started Oct 04 03:09:27 PM PDT 23
Finished Oct 04 03:09:42 PM PDT 23
Peak memory 211132 kb
Host smart-d8feca6c-7d1a-40da-94fc-5924a2c2c007
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=981689061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.981689061
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1328398931
Short name T110
Test name
Test status
Simulation time 4193832172 ps
CPU time 18.07 seconds
Started Oct 04 03:09:34 PM PDT 23
Finished Oct 04 03:09:53 PM PDT 23
Peak memory 213368 kb
Host smart-d0fb62b5-1493-481c-877c-d3800b857c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328398931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1328398931
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1447734543
Short name T156
Test name
Test status
Simulation time 3421691795 ps
CPU time 17.14 seconds
Started Oct 04 03:09:43 PM PDT 23
Finished Oct 04 03:10:01 PM PDT 23
Peak memory 211756 kb
Host smart-8592766c-0e86-4ee9-ad65-609945827217
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447734543 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1447734543
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.4207923070
Short name T93
Test name
Test status
Simulation time 67767356598 ps
CPU time 1303.59 seconds
Started Oct 04 03:09:33 PM PDT 23
Finished Oct 04 03:31:18 PM PDT 23
Peak memory 235768 kb
Host smart-769872da-e203-425e-ae41-cc9362b17801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207923070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.4207923070
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1500553806
Short name T345
Test name
Test status
Simulation time 6809517139 ps
CPU time 14.15 seconds
Started Oct 04 03:10:25 PM PDT 23
Finished Oct 04 03:10:40 PM PDT 23
Peak memory 211072 kb
Host smart-375fb9f2-acd5-41de-a36f-90d5cc87fabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500553806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1500553806
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3508715611
Short name T290
Test name
Test status
Simulation time 2868989951 ps
CPU time 91.93 seconds
Started Oct 04 03:15:35 PM PDT 23
Finished Oct 04 03:17:07 PM PDT 23
Peak memory 236756 kb
Host smart-b9f8af6e-d492-4103-b6ff-4b79e4d39e4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508715611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3508715611
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3158380974
Short name T336
Test name
Test status
Simulation time 24536703393 ps
CPU time 33.84 seconds
Started Oct 04 03:09:46 PM PDT 23
Finished Oct 04 03:10:20 PM PDT 23
Peak memory 211616 kb
Host smart-4ea07d15-6d95-4ffb-b989-89afc42fdc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158380974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3158380974
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1993427297
Short name T326
Test name
Test status
Simulation time 6729075608 ps
CPU time 15.81 seconds
Started Oct 04 03:08:53 PM PDT 23
Finished Oct 04 03:09:09 PM PDT 23
Peak memory 211340 kb
Host smart-eae00ebc-a8d1-4c88-b807-d295b2b19618
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1993427297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1993427297
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.938468594
Short name T342
Test name
Test status
Simulation time 2762291588 ps
CPU time 25.32 seconds
Started Oct 04 03:09:01 PM PDT 23
Finished Oct 04 03:09:26 PM PDT 23
Peak memory 212056 kb
Host smart-fba742bd-e61e-48e7-b88d-4b7a9ba49163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938468594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.938468594
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1001938636
Short name T407
Test name
Test status
Simulation time 40874440638 ps
CPU time 45.27 seconds
Started Oct 04 03:08:57 PM PDT 23
Finished Oct 04 03:09:43 PM PDT 23
Peak memory 216644 kb
Host smart-d418784a-8dec-488d-b15a-252fd75c7e26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001938636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.1001938636
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3225688552
Short name T341
Test name
Test status
Simulation time 48640084384 ps
CPU time 2319.88 seconds
Started Oct 04 03:09:19 PM PDT 23
Finished Oct 04 03:48:00 PM PDT 23
Peak memory 235868 kb
Host smart-1ace2ce5-313c-46a3-93bb-b7c5b14f7434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225688552 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3225688552
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.21673287
Short name T217
Test name
Test status
Simulation time 333362391 ps
CPU time 6.49 seconds
Started Oct 04 03:08:31 PM PDT 23
Finished Oct 04 03:08:38 PM PDT 23
Peak memory 211060 kb
Host smart-2a824c31-63df-4d82-837e-cc164c87e40d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.21673287
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1425420541
Short name T49
Test name
Test status
Simulation time 6443084157 ps
CPU time 77.55 seconds
Started Oct 04 03:09:09 PM PDT 23
Finished Oct 04 03:10:27 PM PDT 23
Peak memory 212632 kb
Host smart-861faa29-615f-4435-b395-7a81e4ece19a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425420541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1425420541
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3990432683
Short name T208
Test name
Test status
Simulation time 46544935856 ps
CPU time 30.48 seconds
Started Oct 04 03:09:13 PM PDT 23
Finished Oct 04 03:09:44 PM PDT 23
Peak memory 211684 kb
Host smart-372e22a6-4355-4e53-8e40-49da223e8626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990432683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3990432683
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.127311209
Short name T229
Test name
Test status
Simulation time 1798988934 ps
CPU time 10.73 seconds
Started Oct 04 03:08:08 PM PDT 23
Finished Oct 04 03:08:20 PM PDT 23
Peak memory 211036 kb
Host smart-912d398c-6ac4-420b-8cf3-68eabedbb274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127311209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.127311209
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2852157138
Short name T294
Test name
Test status
Simulation time 7889342734 ps
CPU time 37.95 seconds
Started Oct 04 03:08:12 PM PDT 23
Finished Oct 04 03:08:51 PM PDT 23
Peak memory 214036 kb
Host smart-d1d74570-a10c-46c9-b1df-d90e5251fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852157138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2852157138
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4255875836
Short name T98
Test name
Test status
Simulation time 269214186 ps
CPU time 18.99 seconds
Started Oct 04 03:08:07 PM PDT 23
Finished Oct 04 03:08:26 PM PDT 23
Peak memory 213248 kb
Host smart-a7973e91-00b1-4f3f-a809-8c4b459dcd93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255875836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4255875836
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3166111352
Short name T166
Test name
Test status
Simulation time 29691410103 ps
CPU time 3412.29 seconds
Started Oct 04 03:08:00 PM PDT 23
Finished Oct 04 04:04:53 PM PDT 23
Peak memory 234448 kb
Host smart-f5511bb9-d5cd-42af-afd0-ccafaa11df64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166111352 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.3166111352
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.841627404
Short name T347
Test name
Test status
Simulation time 596092548 ps
CPU time 7.82 seconds
Started Oct 04 03:08:37 PM PDT 23
Finished Oct 04 03:08:45 PM PDT 23
Peak memory 210948 kb
Host smart-8105095a-a0e2-4710-a331-b9e129596de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841627404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.841627404
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3296087882
Short name T267
Test name
Test status
Simulation time 143084797654 ps
CPU time 448.79 seconds
Started Oct 04 03:08:55 PM PDT 23
Finished Oct 04 03:16:24 PM PDT 23
Peak memory 236716 kb
Host smart-b15c2b41-dd85-4c24-94e5-9263df1ad5be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296087882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3296087882
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2363332752
Short name T9
Test name
Test status
Simulation time 8192860264 ps
CPU time 22.5 seconds
Started Oct 04 03:09:04 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 211904 kb
Host smart-45ff33d4-fb92-4fcd-9f96-b55255e8f612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363332752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2363332752
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.711801368
Short name T249
Test name
Test status
Simulation time 192904707 ps
CPU time 5.66 seconds
Started Oct 04 03:09:53 PM PDT 23
Finished Oct 04 03:09:59 PM PDT 23
Peak memory 211184 kb
Host smart-18d2c453-c615-451d-bea8-28d21014c214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=711801368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.711801368
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3721173078
Short name T311
Test name
Test status
Simulation time 190130913 ps
CPU time 10.59 seconds
Started Oct 04 03:08:34 PM PDT 23
Finished Oct 04 03:08:45 PM PDT 23
Peak memory 212736 kb
Host smart-d6e204d9-00fd-4822-b70f-a5387035a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721173078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3721173078
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1889126239
Short name T5
Test name
Test status
Simulation time 19270744604 ps
CPU time 105.66 seconds
Started Oct 04 03:08:33 PM PDT 23
Finished Oct 04 03:10:19 PM PDT 23
Peak memory 219284 kb
Host smart-4f74a1ac-aff5-48ec-8a5e-a7d3c1d32110
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889126239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1889126239
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1770885248
Short name T190
Test name
Test status
Simulation time 31268606711 ps
CPU time 2395.06 seconds
Started Oct 04 03:08:38 PM PDT 23
Finished Oct 04 03:48:33 PM PDT 23
Peak memory 233572 kb
Host smart-94108bc7-f499-4a78-aeb5-7f8de3ec4ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770885248 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1770885248
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2292466208
Short name T380
Test name
Test status
Simulation time 1873892142 ps
CPU time 7.09 seconds
Started Oct 04 03:10:41 PM PDT 23
Finished Oct 04 03:10:48 PM PDT 23
Peak memory 211000 kb
Host smart-bf61377c-f5c6-4a34-aa35-43f7cc41c2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292466208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2292466208
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2988948730
Short name T207
Test name
Test status
Simulation time 6067544404 ps
CPU time 194.24 seconds
Started Oct 04 03:10:41 PM PDT 23
Finished Oct 04 03:13:55 PM PDT 23
Peak memory 236740 kb
Host smart-042e24e4-6bcb-424a-849a-725e148b5450
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988948730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2988948730
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2343179489
Short name T18
Test name
Test status
Simulation time 176358350 ps
CPU time 9.64 seconds
Started Oct 04 03:09:17 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 211880 kb
Host smart-17859de6-e541-4415-89c4-bfb9d94790b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343179489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2343179489
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1812645665
Short name T420
Test name
Test status
Simulation time 17778231282 ps
CPU time 13.69 seconds
Started Oct 04 03:08:56 PM PDT 23
Finished Oct 04 03:09:10 PM PDT 23
Peak memory 211092 kb
Host smart-a75b0403-bad5-4d95-8a6b-4cf32386b9b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812645665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1812645665
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1946257820
Short name T158
Test name
Test status
Simulation time 186996571 ps
CPU time 10.23 seconds
Started Oct 04 03:08:59 PM PDT 23
Finished Oct 04 03:09:10 PM PDT 23
Peak memory 212440 kb
Host smart-48786917-a7ae-4faa-95b6-7e775f6fd497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946257820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1946257820
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3149067122
Short name T230
Test name
Test status
Simulation time 8338851194 ps
CPU time 77.2 seconds
Started Oct 04 03:08:35 PM PDT 23
Finished Oct 04 03:09:52 PM PDT 23
Peak memory 216896 kb
Host smart-4172828f-c5be-4fbf-8b7e-a66518edd1d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149067122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3149067122
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2497594310
Short name T228
Test name
Test status
Simulation time 19686177937 ps
CPU time 582.93 seconds
Started Oct 04 03:10:53 PM PDT 23
Finished Oct 04 03:20:36 PM PDT 23
Peak memory 227764 kb
Host smart-4641a6a5-6f7e-41a5-82cc-98cf028633f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497594310 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2497594310
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1218241641
Short name T270
Test name
Test status
Simulation time 8403285347 ps
CPU time 13.33 seconds
Started Oct 04 03:09:57 PM PDT 23
Finished Oct 04 03:10:10 PM PDT 23
Peak memory 211072 kb
Host smart-2cddcef7-3097-4dfe-b746-5de4bbee09df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218241641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1218241641
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1055349097
Short name T283
Test name
Test status
Simulation time 50969239614 ps
CPU time 306.24 seconds
Started Oct 04 03:09:11 PM PDT 23
Finished Oct 04 03:14:17 PM PDT 23
Peak memory 212360 kb
Host smart-f1e64711-3123-4832-ab39-75091a3833a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055349097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1055349097
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3301967176
Short name T397
Test name
Test status
Simulation time 169160696 ps
CPU time 9.68 seconds
Started Oct 04 03:09:17 PM PDT 23
Finished Oct 04 03:09:27 PM PDT 23
Peak memory 211748 kb
Host smart-a9c48052-6bdf-4ff0-9722-b92fffd04cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301967176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3301967176
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1058962584
Short name T194
Test name
Test status
Simulation time 103923094 ps
CPU time 5.82 seconds
Started Oct 04 03:09:24 PM PDT 23
Finished Oct 04 03:09:30 PM PDT 23
Peak memory 211016 kb
Host smart-fa518fc1-b1ff-4306-b84a-e7b9214a177a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058962584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1058962584
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.4031456597
Short name T177
Test name
Test status
Simulation time 3980448355 ps
CPU time 23.08 seconds
Started Oct 04 03:10:22 PM PDT 23
Finished Oct 04 03:10:46 PM PDT 23
Peak memory 213384 kb
Host smart-1c56ead3-0eea-462d-bd45-049a1efb290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031456597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.4031456597
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1059905392
Short name T1
Test name
Test status
Simulation time 1817252674 ps
CPU time 48.71 seconds
Started Oct 04 03:09:59 PM PDT 23
Finished Oct 04 03:10:47 PM PDT 23
Peak memory 215688 kb
Host smart-5f84b335-9014-400e-85b6-412cee750c9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059905392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1059905392
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2636222529
Short name T14
Test name
Test status
Simulation time 159528467674 ps
CPU time 912.33 seconds
Started Oct 04 03:12:12 PM PDT 23
Finished Oct 04 03:27:24 PM PDT 23
Peak memory 235816 kb
Host smart-a2238322-0c69-4841-9297-7e960e84fab2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636222529 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2636222529
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3230284453
Short name T266
Test name
Test status
Simulation time 1152878710 ps
CPU time 11.32 seconds
Started Oct 04 03:09:26 PM PDT 23
Finished Oct 04 03:09:38 PM PDT 23
Peak memory 211024 kb
Host smart-fe272218-d5f2-4185-a318-8ab5319f7d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230284453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3230284453
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.7073793
Short name T223
Test name
Test status
Simulation time 57939766428 ps
CPU time 525.33 seconds
Started Oct 04 03:10:40 PM PDT 23
Finished Oct 04 03:19:26 PM PDT 23
Peak memory 213596 kb
Host smart-286a6599-f7ce-4c3f-9cd9-f6cccf081303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7073793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_s
ig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corr
upt_sig_fatal_chk.7073793
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1984017416
Short name T409
Test name
Test status
Simulation time 16137182236 ps
CPU time 33.5 seconds
Started Oct 04 03:08:14 PM PDT 23
Finished Oct 04 03:08:47 PM PDT 23
Peak memory 211512 kb
Host smart-9c00edb7-403a-4806-924f-b174755ea077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984017416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1984017416
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1796125533
Short name T101
Test name
Test status
Simulation time 1127994382 ps
CPU time 5.69 seconds
Started Oct 04 03:10:14 PM PDT 23
Finished Oct 04 03:10:20 PM PDT 23
Peak memory 211148 kb
Host smart-d661a255-e35a-43d6-ae0a-597e801941ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796125533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1796125533
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1770414265
Short name T301
Test name
Test status
Simulation time 9863649580 ps
CPU time 17.51 seconds
Started Oct 04 03:08:31 PM PDT 23
Finished Oct 04 03:08:49 PM PDT 23
Peak memory 213628 kb
Host smart-55802ebf-ddb3-484c-868b-5112c31fe90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770414265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1770414265
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3545626695
Short name T298
Test name
Test status
Simulation time 34303983709 ps
CPU time 88.4 seconds
Started Oct 04 03:10:21 PM PDT 23
Finished Oct 04 03:11:50 PM PDT 23
Peak memory 219340 kb
Host smart-8829d283-172d-416b-aed5-0ce518e92053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545626695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3545626695
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3323471037
Short name T362
Test name
Test status
Simulation time 7168270176 ps
CPU time 98.95 seconds
Started Oct 04 03:14:13 PM PDT 23
Finished Oct 04 03:15:52 PM PDT 23
Peak memory 220520 kb
Host smart-989328c9-1ebf-4ce9-acbc-08edb8039fa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323471037 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3323471037
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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