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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 97.11 93.12 97.88 100.00 98.69 98.04 98.38


Total test records in report: 485
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T264 /workspace/coverage/default/21.rom_ctrl_smoke.1692170502 Oct 11 01:25:42 PM PDT 23 Oct 11 01:26:02 PM PDT 23 3880815396 ps
T265 /workspace/coverage/default/22.rom_ctrl_stress_all.791043779 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:32 PM PDT 23 966486110 ps
T266 /workspace/coverage/default/4.rom_ctrl_stress_all.563545709 Oct 11 01:25:22 PM PDT 23 Oct 11 01:25:39 PM PDT 23 1249129480 ps
T267 /workspace/coverage/default/22.rom_ctrl_smoke.1121021155 Oct 11 01:26:07 PM PDT 23 Oct 11 01:26:41 PM PDT 23 11123929070 ps
T268 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.580199041 Oct 11 01:25:26 PM PDT 23 Oct 11 01:30:58 PM PDT 23 50741056177 ps
T269 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1408455128 Oct 11 01:26:13 PM PDT 23 Oct 11 01:28:59 PM PDT 23 14053390162 ps
T270 /workspace/coverage/default/28.rom_ctrl_alert_test.2321373082 Oct 11 01:25:20 PM PDT 23 Oct 11 01:25:27 PM PDT 23 576449010 ps
T271 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.655977858 Oct 11 01:25:39 PM PDT 23 Oct 11 01:25:47 PM PDT 23 886377742 ps
T272 /workspace/coverage/default/1.rom_ctrl_stress_all.3484006144 Oct 11 01:25:27 PM PDT 23 Oct 11 01:26:13 PM PDT 23 5529313260 ps
T273 /workspace/coverage/default/31.rom_ctrl_stress_all.2365774548 Oct 11 01:25:23 PM PDT 23 Oct 11 01:26:46 PM PDT 23 6646640285 ps
T274 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2523227707 Oct 11 01:26:54 PM PDT 23 Oct 11 01:27:12 PM PDT 23 2196503185 ps
T275 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.43300587 Oct 11 01:25:22 PM PDT 23 Oct 11 02:07:33 PM PDT 23 41342831439 ps
T276 /workspace/coverage/default/15.rom_ctrl_stress_all.1359650525 Oct 11 01:26:03 PM PDT 23 Oct 11 01:27:54 PM PDT 23 12463505461 ps
T277 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3006620188 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:30 PM PDT 23 10648844320 ps
T278 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3602418023 Oct 11 01:25:33 PM PDT 23 Oct 11 01:25:45 PM PDT 23 4515609585 ps
T279 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1630132996 Oct 11 01:26:03 PM PDT 23 Oct 11 01:29:38 PM PDT 23 55177390492 ps
T280 /workspace/coverage/default/35.rom_ctrl_smoke.1797485270 Oct 11 01:25:50 PM PDT 23 Oct 11 01:26:18 PM PDT 23 3140662240 ps
T281 /workspace/coverage/default/38.rom_ctrl_alert_test.4134637685 Oct 11 01:26:51 PM PDT 23 Oct 11 01:27:06 PM PDT 23 6597612691 ps
T282 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2367300312 Oct 11 01:26:50 PM PDT 23 Oct 11 02:37:00 PM PDT 23 171433363787 ps
T283 /workspace/coverage/default/2.rom_ctrl_alert_test.4260159218 Oct 11 01:25:17 PM PDT 23 Oct 11 01:25:21 PM PDT 23 88036662 ps
T284 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2392179901 Oct 11 01:26:54 PM PDT 23 Oct 11 01:27:04 PM PDT 23 4483211591 ps
T285 /workspace/coverage/default/7.rom_ctrl_stress_all.605153491 Oct 11 01:25:00 PM PDT 23 Oct 11 01:26:00 PM PDT 23 6438437779 ps
T286 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2464976498 Oct 11 01:26:07 PM PDT 23 Oct 11 01:26:16 PM PDT 23 442194811 ps
T287 /workspace/coverage/default/25.rom_ctrl_stress_all.535188204 Oct 11 01:25:40 PM PDT 23 Oct 11 01:25:49 PM PDT 23 244931569 ps
T288 /workspace/coverage/default/16.rom_ctrl_stress_all.129337617 Oct 11 01:26:00 PM PDT 23 Oct 11 01:27:09 PM PDT 23 6112038021 ps
T289 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2469671635 Oct 11 01:25:58 PM PDT 23 Oct 11 01:30:58 PM PDT 23 40366228016 ps
T290 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3787624587 Oct 11 01:26:12 PM PDT 23 Oct 11 01:26:26 PM PDT 23 6344961886 ps
T291 /workspace/coverage/default/6.rom_ctrl_stress_all.2103339967 Oct 11 01:25:15 PM PDT 23 Oct 11 01:26:12 PM PDT 23 4494508802 ps
T292 /workspace/coverage/default/1.rom_ctrl_smoke.3973085334 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:35 PM PDT 23 15364038578 ps
T293 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1420408320 Oct 11 01:24:59 PM PDT 23 Oct 11 01:25:14 PM PDT 23 10307491945 ps
T294 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2512914562 Oct 11 01:26:00 PM PDT 23 Oct 11 01:26:09 PM PDT 23 1924819746 ps
T295 /workspace/coverage/default/8.rom_ctrl_smoke.2290782166 Oct 11 01:26:01 PM PDT 23 Oct 11 01:26:37 PM PDT 23 7747880919 ps
T296 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3700444818 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:18 PM PDT 23 186160926 ps
T297 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1407070641 Oct 11 01:25:19 PM PDT 23 Oct 11 01:27:53 PM PDT 23 12675906838 ps
T298 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3141071228 Oct 11 01:25:23 PM PDT 23 Oct 11 01:27:11 PM PDT 23 40975414301 ps
T299 /workspace/coverage/default/22.rom_ctrl_alert_test.3045216415 Oct 11 01:26:00 PM PDT 23 Oct 11 01:26:07 PM PDT 23 1696366361 ps
T300 /workspace/coverage/default/20.rom_ctrl_stress_all.3946583278 Oct 11 01:26:00 PM PDT 23 Oct 11 01:26:09 PM PDT 23 1232995122 ps
T301 /workspace/coverage/default/43.rom_ctrl_alert_test.3608709524 Oct 11 01:27:02 PM PDT 23 Oct 11 01:27:17 PM PDT 23 1877006372 ps
T302 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1774334556 Oct 11 01:26:14 PM PDT 23 Oct 11 01:31:07 PM PDT 23 50187318740 ps
T303 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3167937722 Oct 11 01:26:01 PM PDT 23 Oct 11 01:26:09 PM PDT 23 307904223 ps
T304 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3703803377 Oct 11 01:24:59 PM PDT 23 Oct 11 01:28:00 PM PDT 23 113503909090 ps
T305 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2884343850 Oct 11 01:26:09 PM PDT 23 Oct 11 01:26:26 PM PDT 23 2185254665 ps
T306 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1652833890 Oct 11 01:25:23 PM PDT 23 Oct 11 01:27:49 PM PDT 23 4381188155 ps
T307 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.683923400 Oct 11 01:26:10 PM PDT 23 Oct 11 01:26:30 PM PDT 23 2219784514 ps
T308 /workspace/coverage/default/43.rom_ctrl_smoke.2093144660 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:24 PM PDT 23 185364912 ps
T309 /workspace/coverage/default/27.rom_ctrl_stress_all.1806295294 Oct 11 01:26:15 PM PDT 23 Oct 11 01:26:33 PM PDT 23 28582784047 ps
T310 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1864293060 Oct 11 01:25:42 PM PDT 23 Oct 11 01:26:18 PM PDT 23 16741637582 ps
T108 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1250568200 Oct 11 01:26:53 PM PDT 23 Oct 11 02:03:27 PM PDT 23 104823857679 ps
T311 /workspace/coverage/default/6.rom_ctrl_alert_test.2267190591 Oct 11 01:25:02 PM PDT 23 Oct 11 01:25:13 PM PDT 23 1195928176 ps
T312 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1579815031 Oct 11 01:26:01 PM PDT 23 Oct 11 01:46:54 PM PDT 23 14055214817 ps
T313 /workspace/coverage/default/19.rom_ctrl_alert_test.367468187 Oct 11 01:25:33 PM PDT 23 Oct 11 01:25:45 PM PDT 23 1202303971 ps
T24 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4280667341 Oct 11 01:26:13 PM PDT 23 Oct 11 01:45:18 PM PDT 23 42258287772 ps
T314 /workspace/coverage/default/32.rom_ctrl_alert_test.2895137475 Oct 11 01:26:18 PM PDT 23 Oct 11 01:26:22 PM PDT 23 1036333151 ps
T315 /workspace/coverage/default/44.rom_ctrl_alert_test.1425722943 Oct 11 01:26:57 PM PDT 23 Oct 11 01:27:12 PM PDT 23 7245375353 ps
T316 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2345851281 Oct 11 01:25:18 PM PDT 23 Oct 11 01:27:46 PM PDT 23 8244689079 ps
T317 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2531381721 Oct 11 01:26:58 PM PDT 23 Oct 11 01:27:27 PM PDT 23 3176055547 ps
T318 /workspace/coverage/default/0.rom_ctrl_alert_test.2022516965 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:11 PM PDT 23 1282559288 ps
T319 /workspace/coverage/default/12.rom_ctrl_alert_test.3457921584 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:16 PM PDT 23 1424204294 ps
T320 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.373355047 Oct 11 01:25:22 PM PDT 23 Oct 11 01:25:32 PM PDT 23 379110015 ps
T321 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1419774222 Oct 11 01:25:23 PM PDT 23 Oct 11 01:28:26 PM PDT 23 2765227961 ps
T322 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1396603969 Oct 11 01:25:58 PM PDT 23 Oct 11 02:23:32 PM PDT 23 61003371810 ps
T323 /workspace/coverage/default/14.rom_ctrl_smoke.3204725236 Oct 11 01:25:05 PM PDT 23 Oct 11 01:25:23 PM PDT 23 12436592806 ps
T324 /workspace/coverage/default/0.rom_ctrl_smoke.2308346667 Oct 11 01:25:14 PM PDT 23 Oct 11 01:25:32 PM PDT 23 4648387440 ps
T325 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.76409236 Oct 11 01:25:43 PM PDT 23 Oct 11 03:00:15 PM PDT 23 77073707033 ps
T326 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3985455948 Oct 11 01:26:52 PM PDT 23 Oct 11 01:29:16 PM PDT 23 6534239258 ps
T327 /workspace/coverage/default/19.rom_ctrl_stress_all.2492299120 Oct 11 01:25:41 PM PDT 23 Oct 11 01:26:56 PM PDT 23 7230247075 ps
T328 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2041933736 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:19 PM PDT 23 394234468 ps
T329 /workspace/coverage/default/36.rom_ctrl_smoke.2484688812 Oct 11 01:26:50 PM PDT 23 Oct 11 01:27:07 PM PDT 23 4509960753 ps
T330 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3224456532 Oct 11 01:26:02 PM PDT 23 Oct 11 01:30:39 PM PDT 23 158913017079 ps
T331 /workspace/coverage/default/46.rom_ctrl_alert_test.2187135542 Oct 11 01:26:16 PM PDT 23 Oct 11 01:26:24 PM PDT 23 618559943 ps
T332 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4025472867 Oct 11 01:26:48 PM PDT 23 Oct 11 01:26:59 PM PDT 23 171743989 ps
T333 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1789574957 Oct 11 01:26:01 PM PDT 23 Oct 11 01:26:33 PM PDT 23 4239569424 ps
T334 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.773720836 Oct 11 01:26:02 PM PDT 23 Oct 11 03:00:07 PM PDT 23 164613200478 ps
T335 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.133277389 Oct 11 01:25:41 PM PDT 23 Oct 11 01:25:58 PM PDT 23 1863924741 ps
T336 /workspace/coverage/default/49.rom_ctrl_alert_test.4030113331 Oct 11 01:27:05 PM PDT 23 Oct 11 01:27:13 PM PDT 23 535241312 ps
T337 /workspace/coverage/default/33.rom_ctrl_stress_all.367585067 Oct 11 01:26:46 PM PDT 23 Oct 11 01:27:13 PM PDT 23 951984628 ps
T338 /workspace/coverage/default/29.rom_ctrl_smoke.2364668450 Oct 11 01:25:32 PM PDT 23 Oct 11 01:25:51 PM PDT 23 1665570184 ps
T339 /workspace/coverage/default/20.rom_ctrl_smoke.3869012211 Oct 11 01:25:25 PM PDT 23 Oct 11 01:25:51 PM PDT 23 2690413084 ps
T340 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1883756299 Oct 11 01:26:10 PM PDT 23 Oct 11 01:31:50 PM PDT 23 189004508612 ps
T341 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4201138609 Oct 11 01:26:12 PM PDT 23 Oct 11 02:03:06 PM PDT 23 237978966208 ps
T342 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1821535238 Oct 11 01:25:41 PM PDT 23 Oct 11 01:27:41 PM PDT 23 1813145089 ps
T343 /workspace/coverage/default/25.rom_ctrl_alert_test.766130688 Oct 11 01:25:20 PM PDT 23 Oct 11 01:25:28 PM PDT 23 1722774166 ps
T344 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2078168328 Oct 11 01:25:57 PM PDT 23 Oct 11 01:27:36 PM PDT 23 1640322512 ps
T345 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.561402176 Oct 11 01:26:04 PM PDT 23 Oct 11 01:29:35 PM PDT 23 14448413375 ps
T346 /workspace/coverage/default/47.rom_ctrl_stress_all.4264235904 Oct 11 01:26:57 PM PDT 23 Oct 11 01:27:15 PM PDT 23 2806289574 ps
T347 /workspace/coverage/default/36.rom_ctrl_alert_test.1731673147 Oct 11 01:26:53 PM PDT 23 Oct 11 01:26:58 PM PDT 23 519511835 ps
T348 /workspace/coverage/default/13.rom_ctrl_alert_test.649418125 Oct 11 01:25:26 PM PDT 23 Oct 11 01:25:38 PM PDT 23 5272811677 ps
T349 /workspace/coverage/default/33.rom_ctrl_smoke.3955693470 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:23 PM PDT 23 650974956 ps
T350 /workspace/coverage/default/28.rom_ctrl_smoke.1967945421 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:35 PM PDT 23 12180354288 ps
T351 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.12233923 Oct 11 01:26:53 PM PDT 23 Oct 11 01:27:16 PM PDT 23 2314413769 ps
T352 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1748404754 Oct 11 01:26:53 PM PDT 23 Oct 11 01:29:06 PM PDT 23 4114183761 ps
T353 /workspace/coverage/default/4.rom_ctrl_alert_test.858748682 Oct 11 01:24:58 PM PDT 23 Oct 11 01:25:10 PM PDT 23 2280234281 ps
T354 /workspace/coverage/default/7.rom_ctrl_alert_test.367215782 Oct 11 01:26:49 PM PDT 23 Oct 11 01:26:54 PM PDT 23 87279925 ps
T355 /workspace/coverage/default/11.rom_ctrl_alert_test.782848852 Oct 11 01:25:25 PM PDT 23 Oct 11 01:25:31 PM PDT 23 173997935 ps
T356 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3558126118 Oct 11 01:26:57 PM PDT 23 Oct 11 01:27:21 PM PDT 23 15876826335 ps
T357 /workspace/coverage/default/27.rom_ctrl_smoke.1937443089 Oct 11 01:25:33 PM PDT 23 Oct 11 01:25:44 PM PDT 23 354154577 ps
T358 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1331263550 Oct 11 01:27:01 PM PDT 23 Oct 11 01:29:24 PM PDT 23 42968201766 ps
T25 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1731220155 Oct 11 01:25:23 PM PDT 23 Oct 11 02:01:00 PM PDT 23 229711992327 ps
T359 /workspace/coverage/default/29.rom_ctrl_alert_test.3683392192 Oct 11 01:27:02 PM PDT 23 Oct 11 01:27:07 PM PDT 23 347381512 ps
T360 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2840977015 Oct 11 01:25:19 PM PDT 23 Oct 11 01:27:11 PM PDT 23 1854598539 ps
T361 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3954399784 Oct 11 01:27:00 PM PDT 23 Oct 11 01:27:06 PM PDT 23 190924067 ps
T362 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3800969830 Oct 11 01:26:53 PM PDT 23 Oct 11 01:31:16 PM PDT 23 51002613043 ps
T363 /workspace/coverage/default/39.rom_ctrl_alert_test.3013244915 Oct 11 01:26:15 PM PDT 23 Oct 11 01:26:31 PM PDT 23 1844500610 ps
T364 /workspace/coverage/default/5.rom_ctrl_stress_all.3532387035 Oct 11 01:25:02 PM PDT 23 Oct 11 01:25:56 PM PDT 23 22828493130 ps
T365 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.465321023 Oct 11 01:25:40 PM PDT 23 Oct 11 02:55:43 PM PDT 23 59460115785 ps
T366 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1715462232 Oct 11 01:27:09 PM PDT 23 Oct 11 03:27:09 PM PDT 23 137774918155 ps
T367 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2531943813 Oct 11 01:25:59 PM PDT 23 Oct 11 01:26:05 PM PDT 23 358088190 ps
T368 /workspace/coverage/default/16.rom_ctrl_alert_test.2530500373 Oct 11 01:25:24 PM PDT 23 Oct 11 01:25:36 PM PDT 23 4752624276 ps
T369 /workspace/coverage/default/23.rom_ctrl_smoke.1301891113 Oct 11 01:26:44 PM PDT 23 Oct 11 01:26:55 PM PDT 23 709036505 ps
T370 /workspace/coverage/default/10.rom_ctrl_smoke.263242141 Oct 11 01:25:19 PM PDT 23 Oct 11 01:25:45 PM PDT 23 3859968672 ps
T371 /workspace/coverage/default/14.rom_ctrl_alert_test.2673407904 Oct 11 01:26:11 PM PDT 23 Oct 11 01:26:16 PM PDT 23 334135822 ps
T372 /workspace/coverage/default/21.rom_ctrl_alert_test.1499541677 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:10 PM PDT 23 1603382918 ps
T373 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2021434064 Oct 11 01:25:27 PM PDT 23 Oct 11 01:25:53 PM PDT 23 11550186827 ps
T374 /workspace/coverage/default/3.rom_ctrl_alert_test.1606148584 Oct 11 01:25:23 PM PDT 23 Oct 11 01:25:28 PM PDT 23 164584038 ps
T375 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.678912409 Oct 11 01:27:00 PM PDT 23 Oct 11 01:27:17 PM PDT 23 8708266902 ps
T376 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4174769315 Oct 11 01:26:51 PM PDT 23 Oct 11 01:27:08 PM PDT 23 1079793519 ps
T377 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2899361066 Oct 11 01:25:19 PM PDT 23 Oct 11 01:31:38 PM PDT 23 139234161725 ps
T378 /workspace/coverage/default/33.rom_ctrl_alert_test.3349413455 Oct 11 01:26:49 PM PDT 23 Oct 11 01:27:03 PM PDT 23 1627399058 ps
T379 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3943839665 Oct 11 01:25:40 PM PDT 23 Oct 11 01:25:51 PM PDT 23 608549210 ps
T380 /workspace/coverage/default/38.rom_ctrl_stress_all.3977188380 Oct 11 01:26:11 PM PDT 23 Oct 11 01:27:10 PM PDT 23 25660191783 ps
T381 /workspace/coverage/default/30.rom_ctrl_alert_test.1796911416 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:03 PM PDT 23 88971185 ps
T382 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.205521033 Oct 11 01:25:26 PM PDT 23 Oct 11 01:25:34 PM PDT 23 384405197 ps
T383 /workspace/coverage/default/40.rom_ctrl_smoke.1189126034 Oct 11 01:26:10 PM PDT 23 Oct 11 01:26:40 PM PDT 23 11986725582 ps
T384 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.72615007 Oct 11 01:25:18 PM PDT 23 Oct 11 01:25:33 PM PDT 23 5318887839 ps
T385 /workspace/coverage/default/5.rom_ctrl_smoke.3613663561 Oct 11 01:25:14 PM PDT 23 Oct 11 01:25:38 PM PDT 23 2105729323 ps
T386 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4041431566 Oct 11 01:26:09 PM PDT 23 Oct 11 01:55:37 PM PDT 23 43096448623 ps
T387 /workspace/coverage/default/42.rom_ctrl_stress_all.3918561046 Oct 11 01:27:01 PM PDT 23 Oct 11 01:28:38 PM PDT 23 20099844631 ps
T388 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1392327558 Oct 11 01:25:45 PM PDT 23 Oct 11 01:30:21 PM PDT 23 31253048265 ps
T389 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1472756210 Oct 11 01:25:59 PM PDT 23 Oct 11 01:26:10 PM PDT 23 3151314913 ps
T390 /workspace/coverage/default/44.rom_ctrl_smoke.4037124318 Oct 11 01:27:00 PM PDT 23 Oct 11 01:27:18 PM PDT 23 1112685992 ps
T391 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.403014508 Oct 11 01:26:56 PM PDT 23 Oct 11 01:39:01 PM PDT 23 17838418861 ps
T392 /workspace/coverage/default/13.rom_ctrl_stress_all.1110929825 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:24 PM PDT 23 712647966 ps
T393 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3127193981 Oct 11 01:26:13 PM PDT 23 Oct 11 01:32:28 PM PDT 23 107947226389 ps
T394 /workspace/coverage/default/8.rom_ctrl_stress_all.2572133367 Oct 11 01:25:43 PM PDT 23 Oct 11 01:26:06 PM PDT 23 1520877831 ps
T395 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2569859043 Oct 11 01:26:56 PM PDT 23 Oct 11 01:27:02 PM PDT 23 95905759 ps
T396 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1424428297 Oct 11 01:26:12 PM PDT 23 Oct 11 01:26:27 PM PDT 23 3296213180 ps
T397 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3301192349 Oct 11 01:25:25 PM PDT 23 Oct 11 01:25:50 PM PDT 23 2477582794 ps
T398 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2778655948 Oct 11 01:26:48 PM PDT 23 Oct 11 01:32:18 PM PDT 23 138944075111 ps
T399 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3681466609 Oct 11 01:26:11 PM PDT 23 Oct 11 01:26:42 PM PDT 23 6983001652 ps
T400 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3864055872 Oct 11 01:25:02 PM PDT 23 Oct 11 01:29:43 PM PDT 23 79380445035 ps
T401 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2662879601 Oct 11 01:25:23 PM PDT 23 Oct 11 01:33:43 PM PDT 23 201193422849 ps
T402 /workspace/coverage/default/49.rom_ctrl_stress_all.499133768 Oct 11 01:26:10 PM PDT 23 Oct 11 01:26:50 PM PDT 23 2030757169 ps
T403 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2783830737 Oct 11 01:26:58 PM PDT 23 Oct 11 01:28:54 PM PDT 23 7562724656 ps
T404 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1941727428 Oct 11 01:25:21 PM PDT 23 Oct 11 01:25:31 PM PDT 23 757214484 ps
T405 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3492621444 Oct 11 01:26:12 PM PDT 23 Oct 11 01:31:19 PM PDT 23 325176525365 ps
T406 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.243639167 Oct 11 01:26:08 PM PDT 23 Oct 11 01:26:20 PM PDT 23 992005795 ps
T407 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.382301961 Oct 11 01:26:02 PM PDT 23 Oct 11 01:26:20 PM PDT 23 1334213181 ps
T408 /workspace/coverage/default/10.rom_ctrl_alert_test.887520939 Oct 11 01:25:02 PM PDT 23 Oct 11 01:25:17 PM PDT 23 2037942361 ps
T409 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1545550260 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:22 PM PDT 23 2674799094 ps
T410 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.587141362 Oct 11 01:26:09 PM PDT 23 Oct 11 01:26:23 PM PDT 23 1381177270 ps
T411 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3865639737 Oct 11 01:26:01 PM PDT 23 Oct 11 01:27:47 PM PDT 23 12104158280 ps
T412 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1116637674 Oct 11 01:25:26 PM PDT 23 Oct 11 01:25:48 PM PDT 23 2210350158 ps
T413 /workspace/coverage/default/26.rom_ctrl_stress_all.3002269394 Oct 11 01:25:21 PM PDT 23 Oct 11 01:25:57 PM PDT 23 3184277239 ps
T414 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2519995681 Oct 11 01:26:52 PM PDT 23 Oct 11 01:27:17 PM PDT 23 2482869021 ps
T415 /workspace/coverage/default/45.rom_ctrl_stress_all.3382965733 Oct 11 01:26:16 PM PDT 23 Oct 11 01:26:43 PM PDT 23 505628003 ps
T416 /workspace/coverage/default/34.rom_ctrl_stress_all.1375744221 Oct 11 01:26:51 PM PDT 23 Oct 11 01:27:09 PM PDT 23 1536216149 ps
T417 /workspace/coverage/default/26.rom_ctrl_alert_test.4279274943 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:13 PM PDT 23 12980351140 ps
T418 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2394905191 Oct 11 01:25:20 PM PDT 23 Oct 11 01:25:51 PM PDT 23 3823458402 ps
T41 /workspace/coverage/default/3.rom_ctrl_sec_cm.233672848 Oct 11 01:25:32 PM PDT 23 Oct 11 01:27:23 PM PDT 23 240608764 ps
T419 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2190082028 Oct 11 01:25:02 PM PDT 23 Oct 11 01:25:26 PM PDT 23 2278691622 ps
T420 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4147223862 Oct 11 01:26:18 PM PDT 23 Oct 11 01:26:30 PM PDT 23 1107814923 ps
T421 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1101163782 Oct 11 01:25:25 PM PDT 23 Oct 11 01:25:39 PM PDT 23 1348147031 ps
T422 /workspace/coverage/default/4.rom_ctrl_smoke.3060234353 Oct 11 01:25:33 PM PDT 23 Oct 11 01:26:06 PM PDT 23 15112473696 ps
T423 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1917854447 Oct 11 01:25:15 PM PDT 23 Oct 11 01:25:21 PM PDT 23 96552026 ps
T424 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1746430210 Oct 11 01:25:28 PM PDT 23 Oct 11 01:25:50 PM PDT 23 3622363185 ps
T425 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2031368371 Oct 11 01:26:13 PM PDT 23 Oct 11 01:26:20 PM PDT 23 382815835 ps
T426 /workspace/coverage/default/24.rom_ctrl_stress_all.1100946860 Oct 11 01:25:58 PM PDT 23 Oct 11 01:26:59 PM PDT 23 23751002502 ps
T427 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4023759352 Oct 11 01:26:03 PM PDT 23 Oct 11 01:26:09 PM PDT 23 95536515 ps
T428 /workspace/coverage/default/0.rom_ctrl_stress_all.2132678880 Oct 11 01:25:22 PM PDT 23 Oct 11 01:25:40 PM PDT 23 2311707191 ps
T429 /workspace/coverage/default/48.rom_ctrl_alert_test.229556430 Oct 11 01:26:50 PM PDT 23 Oct 11 01:26:56 PM PDT 23 820163100 ps
T430 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.860274637 Oct 11 01:26:59 PM PDT 23 Oct 11 01:27:34 PM PDT 23 22588942526 ps
T431 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2250527604 Oct 11 01:26:48 PM PDT 23 Oct 11 01:27:11 PM PDT 23 8220499549 ps
T432 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.632523281 Oct 11 01:26:00 PM PDT 23 Oct 11 02:02:07 PM PDT 23 165390939258 ps
T433 /workspace/coverage/default/5.rom_ctrl_alert_test.646246967 Oct 11 01:25:23 PM PDT 23 Oct 11 01:25:28 PM PDT 23 347505014 ps
T434 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2946273064 Oct 11 01:25:23 PM PDT 23 Oct 11 03:05:16 PM PDT 23 72448104434 ps
T42 /workspace/coverage/default/1.rom_ctrl_sec_cm.1503890025 Oct 11 01:26:10 PM PDT 23 Oct 11 01:27:12 PM PDT 23 2343611195 ps
T435 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.724394182 Oct 11 12:23:50 PM PDT 23 Oct 11 12:30:26 PM PDT 23 68886962540 ps
T436 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3265516332 Oct 11 12:23:04 PM PDT 23 Oct 11 12:23:16 PM PDT 23 3976061944 ps
T113 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.884737829 Oct 11 12:23:23 PM PDT 23 Oct 11 12:24:14 PM PDT 23 6185863108 ps
T85 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3350826725 Oct 11 12:24:05 PM PDT 23 Oct 11 12:25:36 PM PDT 23 13889075142 ps
T437 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1034554267 Oct 11 12:24:15 PM PDT 23 Oct 11 12:24:55 PM PDT 23 584484998 ps
T438 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.888697056 Oct 11 12:24:37 PM PDT 23 Oct 11 12:24:44 PM PDT 23 91901290 ps
T86 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3505897466 Oct 11 12:21:56 PM PDT 23 Oct 11 12:24:02 PM PDT 23 50836793160 ps
T439 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2140049710 Oct 11 12:23:15 PM PDT 23 Oct 11 12:23:23 PM PDT 23 3008719413 ps
T440 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1426155031 Oct 11 12:22:05 PM PDT 23 Oct 11 12:22:14 PM PDT 23 873136292 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2937828040 Oct 11 12:23:07 PM PDT 23 Oct 11 12:23:17 PM PDT 23 1649514742 ps
T442 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3972499737 Oct 11 12:24:41 PM PDT 23 Oct 11 12:24:56 PM PDT 23 13206409186 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3598570254 Oct 11 12:22:36 PM PDT 23 Oct 11 12:22:50 PM PDT 23 1547289802 ps
T444 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2724555280 Oct 11 12:23:27 PM PDT 23 Oct 11 12:23:42 PM PDT 23 26341618520 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1732696074 Oct 11 12:21:50 PM PDT 23 Oct 11 12:21:54 PM PDT 23 261692875 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.572469375 Oct 11 12:24:53 PM PDT 23 Oct 11 12:25:12 PM PDT 23 4250749926 ps
T447 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2299862258 Oct 11 12:24:27 PM PDT 23 Oct 11 12:24:33 PM PDT 23 3224765370 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.637393273 Oct 11 12:22:58 PM PDT 23 Oct 11 12:23:02 PM PDT 23 87185607 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3364678101 Oct 11 12:25:15 PM PDT 23 Oct 11 12:26:05 PM PDT 23 4143138560 ps
T87 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1267203949 Oct 11 12:24:07 PM PDT 23 Oct 11 12:26:18 PM PDT 23 28268488850 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2081777178 Oct 11 12:22:08 PM PDT 23 Oct 11 12:22:20 PM PDT 23 1921621820 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.802721121 Oct 11 12:23:18 PM PDT 23 Oct 11 12:23:30 PM PDT 23 1988431848 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2677940806 Oct 11 12:25:03 PM PDT 23 Oct 11 12:25:17 PM PDT 23 1606634540 ps
T452 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.822488761 Oct 11 12:25:14 PM PDT 23 Oct 11 12:29:29 PM PDT 23 28780744112 ps
T453 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3533545038 Oct 11 12:25:38 PM PDT 23 Oct 11 12:25:46 PM PDT 23 5476280748 ps
T116 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1852946557 Oct 11 12:22:04 PM PDT 23 Oct 11 12:22:47 PM PDT 23 325616156 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4069294898 Oct 11 12:25:29 PM PDT 23 Oct 11 12:25:34 PM PDT 23 701402824 ps
T455 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1960363403 Oct 11 12:21:56 PM PDT 23 Oct 11 12:22:09 PM PDT 23 7129579315 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.767314910 Oct 11 12:21:48 PM PDT 23 Oct 11 12:22:00 PM PDT 23 849031341 ps
T457 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1777301890 Oct 11 12:22:29 PM PDT 23 Oct 11 12:22:45 PM PDT 23 7056586088 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3529574513 Oct 11 12:22:36 PM PDT 23 Oct 11 12:22:45 PM PDT 23 1301488311 ps
T459 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3055204431 Oct 11 12:23:21 PM PDT 23 Oct 11 12:23:37 PM PDT 23 7435684104 ps
T460 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2246793186 Oct 11 12:22:34 PM PDT 23 Oct 11 12:22:46 PM PDT 23 1422061508 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3271384525 Oct 11 12:21:44 PM PDT 23 Oct 11 12:21:56 PM PDT 23 5099097221 ps
T462 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3710214876 Oct 11 12:25:17 PM PDT 23 Oct 11 12:26:54 PM PDT 23 1867002762 ps
T463 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1388994421 Oct 11 12:25:24 PM PDT 23 Oct 11 12:25:36 PM PDT 23 1317329168 ps
T464 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2515048369 Oct 11 12:22:36 PM PDT 23 Oct 11 12:22:50 PM PDT 23 1633374576 ps
T465 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4247138863 Oct 11 12:25:43 PM PDT 23 Oct 11 12:26:01 PM PDT 23 1835544940 ps
T466 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2090662736 Oct 11 12:24:20 PM PDT 23 Oct 11 12:24:27 PM PDT 23 380971758 ps
T467 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3668826282 Oct 11 12:25:40 PM PDT 23 Oct 11 12:25:49 PM PDT 23 1719712036 ps
T468 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3770186497 Oct 11 12:24:20 PM PDT 23 Oct 11 12:24:38 PM PDT 23 30149886751 ps
T469 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3487662591 Oct 11 12:24:03 PM PDT 23 Oct 11 12:24:08 PM PDT 23 755536394 ps
T88 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.739170567 Oct 11 12:24:01 PM PDT 23 Oct 11 12:29:00 PM PDT 23 31742991946 ps
T470 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.352453088 Oct 11 12:21:59 PM PDT 23 Oct 11 12:23:15 PM PDT 23 265035509 ps
T471 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1754866529 Oct 11 12:24:09 PM PDT 23 Oct 11 12:24:15 PM PDT 23 98049065 ps
T117 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.853385463 Oct 11 12:24:15 PM PDT 23 Oct 11 12:25:31 PM PDT 23 1989491486 ps
T472 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1164835186 Oct 11 12:22:09 PM PDT 23 Oct 11 12:22:14 PM PDT 23 171720901 ps
T473 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1006361193 Oct 11 12:23:26 PM PDT 23 Oct 11 12:24:17 PM PDT 23 300291809 ps
T474 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2505584944 Oct 11 12:25:32 PM PDT 23 Oct 11 12:25:40 PM PDT 23 89294277 ps
T475 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1664920111 Oct 11 12:25:01 PM PDT 23 Oct 11 12:29:36 PM PDT 23 83528478638 ps
T476 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1375125863 Oct 11 12:21:42 PM PDT 23 Oct 11 12:21:47 PM PDT 23 85694583 ps
T477 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.955822769 Oct 11 12:23:11 PM PDT 23 Oct 11 12:25:13 PM PDT 23 10658099648 ps
T478 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3231275634 Oct 11 12:25:20 PM PDT 23 Oct 11 12:25:41 PM PDT 23 5768516952 ps
T479 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1342492896 Oct 11 12:25:26 PM PDT 23 Oct 11 12:25:39 PM PDT 23 1421470667 ps
T480 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.711965808 Oct 11 12:22:49 PM PDT 23 Oct 11 12:22:56 PM PDT 23 1376616383 ps
T481 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3872621580 Oct 11 12:25:20 PM PDT 23 Oct 11 12:25:37 PM PDT 23 3736730188 ps
T482 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2228617324 Oct 11 12:22:02 PM PDT 23 Oct 11 12:22:12 PM PDT 23 3521847711 ps
T483 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1881319540 Oct 11 12:21:44 PM PDT 23 Oct 11 12:21:58 PM PDT 23 4802342312 ps
T484 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1201301891 Oct 11 12:23:51 PM PDT 23 Oct 11 12:24:07 PM PDT 23 4065787675 ps
T485 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1517425614 Oct 11 12:25:43 PM PDT 23 Oct 11 12:25:57 PM PDT 23 6742233674 ps

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.4259281943
Short name T21
Test name
Test status
Simulation time 1651888946 ps
CPU time 15.49 seconds
Started Oct 11 12:21:54 PM PDT 23
Finished Oct 11 12:22:10 PM PDT 23
Peak memory 210628 kb
Host smart-ccf2b66b-c5a7-4ef3-b6fe-bc5fddc23cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259281943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.4259281943
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4155372051
Short name T3
Test name
Test status
Simulation time 38614059722 ps
CPU time 6913 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 03:21:23 PM PDT 23
Peak memory 228360 kb
Host smart-66a9fd78-9dab-4178-ac43-0d6790cddd9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155372051 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.4155372051
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1861894139
Short name T34
Test name
Test status
Simulation time 175661925421 ps
CPU time 337.41 seconds
Started Oct 11 12:25:25 PM PDT 23
Finished Oct 11 12:31:03 PM PDT 23
Peak memory 210664 kb
Host smart-9e8ae90c-5b5c-41fe-8e86-fd5e8eefdb56
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861894139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1861894139
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.536440710
Short name T54
Test name
Test status
Simulation time 7608516730 ps
CPU time 15.44 seconds
Started Oct 11 12:23:17 PM PDT 23
Finished Oct 11 12:23:32 PM PDT 23
Peak memory 218888 kb
Host smart-3db1ef14-f24c-4cf3-83c4-6fe6d9170191
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536440710 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.536440710
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2010127121
Short name T63
Test name
Test status
Simulation time 1622009848 ps
CPU time 79.76 seconds
Started Oct 11 12:24:02 PM PDT 23
Finished Oct 11 12:25:23 PM PDT 23
Peak memory 209880 kb
Host smart-8779641f-4813-4e8f-b204-d1a7197ed6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010127121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2010127121
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.4126162075
Short name T19
Test name
Test status
Simulation time 9662989392 ps
CPU time 137.64 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:28:28 PM PDT 23
Peak memory 224896 kb
Host smart-80444df3-7204-415f-8c4d-b4aa606cde7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126162075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.4126162075
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2253544810
Short name T57
Test name
Test status
Simulation time 1573629158 ps
CPU time 18.34 seconds
Started Oct 11 12:23:19 PM PDT 23
Finished Oct 11 12:23:42 PM PDT 23
Peak memory 218804 kb
Host smart-59c18821-1de7-4349-9443-de823e073fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253544810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2253544810
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.601233191
Short name T9
Test name
Test status
Simulation time 38629293054 ps
CPU time 1447.85 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:49:32 PM PDT 23
Peak memory 235780 kb
Host smart-3419aeb6-0e4e-46b4-9cf2-20e817b53849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601233191 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.601233191
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1852946557
Short name T116
Test name
Test status
Simulation time 325616156 ps
CPU time 41.87 seconds
Started Oct 11 12:22:04 PM PDT 23
Finished Oct 11 12:22:47 PM PDT 23
Peak memory 211564 kb
Host smart-e402bf56-a83c-40ec-972d-784f0e47a624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852946557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1852946557
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.44553981
Short name T38
Test name
Test status
Simulation time 549817756 ps
CPU time 56.31 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 236700 kb
Host smart-a08fe9d2-74a4-4b7d-af32-73e9941951d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44553981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.44553981
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.4159577182
Short name T64
Test name
Test status
Simulation time 2193524042 ps
CPU time 82.65 seconds
Started Oct 11 12:21:48 PM PDT 23
Finished Oct 11 12:23:11 PM PDT 23
Peak memory 210836 kb
Host smart-ef7121b9-4d1a-4e5d-96b6-6e823192a493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159577182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.4159577182
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1731220155
Short name T25
Test name
Test status
Simulation time 229711992327 ps
CPU time 2136.2 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 02:01:00 PM PDT 23
Peak memory 243976 kb
Host smart-39a28e62-6a49-48ef-a7d4-154f7822f9e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731220155 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1731220155
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3356899259
Short name T32
Test name
Test status
Simulation time 1939150699 ps
CPU time 97.12 seconds
Started Oct 11 12:22:08 PM PDT 23
Finished Oct 11 12:23:46 PM PDT 23
Peak memory 210608 kb
Host smart-5f92ddca-561f-44e3-926f-65430231fe9e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356899259 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3356899259
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2037998648
Short name T218
Test name
Test status
Simulation time 65336479400 ps
CPU time 4008.29 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 02:32:15 PM PDT 23
Peak memory 237664 kb
Host smart-118b7bab-d24f-4548-b51c-a0bb7ffd6dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037998648 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2037998648
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3627514730
Short name T6
Test name
Test status
Simulation time 11120703709 ps
CPU time 26.83 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:49 PM PDT 23
Peak memory 211164 kb
Host smart-d284d0d4-0892-44d3-a650-5fa90b838401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627514730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3627514730
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1780963226
Short name T253
Test name
Test status
Simulation time 175406024 ps
CPU time 9.78 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 210984 kb
Host smart-2053dac5-720f-4c43-9c38-bc509bca3bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780963226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1780963226
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.4071780882
Short name T154
Test name
Test status
Simulation time 4352377300 ps
CPU time 17.75 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:40 PM PDT 23
Peak memory 211144 kb
Host smart-589343fc-9845-4010-9c7c-9f882be7ad87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071780882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.4071780882
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2393869587
Short name T27
Test name
Test status
Simulation time 193793244 ps
CPU time 5.9 seconds
Started Oct 11 01:25:39 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 211068 kb
Host smart-b3d9250e-a05b-4bba-a772-83f71567d2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393869587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2393869587
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2400406225
Short name T114
Test name
Test status
Simulation time 2332664938 ps
CPU time 84.71 seconds
Started Oct 11 12:21:44 PM PDT 23
Finished Oct 11 12:23:10 PM PDT 23
Peak memory 210968 kb
Host smart-b974bce2-7aff-4559-a53a-4f7cf7900d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400406225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2400406225
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1610582920
Short name T111
Test name
Test status
Simulation time 13430059847 ps
CPU time 45.42 seconds
Started Oct 11 12:23:41 PM PDT 23
Finished Oct 11 12:24:27 PM PDT 23
Peak memory 212068 kb
Host smart-6a7d74ec-41bc-4d64-9c11-4fb1fa841b58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610582920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1610582920
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.2537194058
Short name T106
Test name
Test status
Simulation time 141172639193 ps
CPU time 1458.16 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:50:33 PM PDT 23
Peak memory 239952 kb
Host smart-7f6e6a54-ec6a-43d8-8e4d-f70e4213a816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537194058 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.2537194058
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1764147932
Short name T129
Test name
Test status
Simulation time 851591432 ps
CPU time 9.35 seconds
Started Oct 11 12:23:22 PM PDT 23
Finished Oct 11 12:23:32 PM PDT 23
Peak memory 216784 kb
Host smart-a4cfda97-0e18-47df-add1-3e0d666fa29e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764147932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1764147932
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2724555280
Short name T444
Test name
Test status
Simulation time 26341618520 ps
CPU time 15.12 seconds
Started Oct 11 12:23:27 PM PDT 23
Finished Oct 11 12:23:42 PM PDT 23
Peak memory 210700 kb
Host smart-441f8334-733f-4b5f-a0da-32247b6606fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724555280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2724555280
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1754866529
Short name T471
Test name
Test status
Simulation time 98049065 ps
CPU time 6.11 seconds
Started Oct 11 12:24:09 PM PDT 23
Finished Oct 11 12:24:15 PM PDT 23
Peak memory 210628 kb
Host smart-a2e24e5d-9a06-4d87-a587-a44e6dbab1ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754866529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1754866529
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1768977301
Short name T135
Test name
Test status
Simulation time 344072875 ps
CPU time 4.41 seconds
Started Oct 11 12:22:45 PM PDT 23
Finished Oct 11 12:22:49 PM PDT 23
Peak memory 211092 kb
Host smart-dc65544c-3051-47eb-a252-6f56e5cf5101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768977301 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1768977301
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2299862258
Short name T447
Test name
Test status
Simulation time 3224765370 ps
CPU time 6.33 seconds
Started Oct 11 12:24:27 PM PDT 23
Finished Oct 11 12:24:33 PM PDT 23
Peak memory 210668 kb
Host smart-6dce3b32-6f84-4c2a-9be0-89ecc5e8ddff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299862258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2299862258
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3383201129
Short name T128
Test name
Test status
Simulation time 1145795184 ps
CPU time 7.55 seconds
Started Oct 11 12:23:58 PM PDT 23
Finished Oct 11 12:24:07 PM PDT 23
Peak memory 210620 kb
Host smart-1669c5d6-c22b-4c38-9923-491e3926f847
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383201129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3383201129
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.817249328
Short name T122
Test name
Test status
Simulation time 5045324398 ps
CPU time 11.51 seconds
Started Oct 11 12:23:16 PM PDT 23
Finished Oct 11 12:23:28 PM PDT 23
Peak memory 210688 kb
Host smart-b0c0ed23-7c50-456b-b459-b5e30a025959
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817249328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
817249328
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2224619655
Short name T70
Test name
Test status
Simulation time 86149215925 ps
CPU time 166.01 seconds
Started Oct 11 12:21:48 PM PDT 23
Finished Oct 11 12:24:35 PM PDT 23
Peak memory 218820 kb
Host smart-e0b5eeb5-23ed-4fba-9f20-b745212ec967
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224619655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2224619655
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3993059249
Short name T65
Test name
Test status
Simulation time 16220989957 ps
CPU time 16.33 seconds
Started Oct 11 12:21:44 PM PDT 23
Finished Oct 11 12:22:01 PM PDT 23
Peak memory 210676 kb
Host smart-a09c54f4-4827-4594-9ecd-b67fb14b8fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993059249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3993059249
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2260800737
Short name T110
Test name
Test status
Simulation time 5370496721 ps
CPU time 17.19 seconds
Started Oct 11 12:21:52 PM PDT 23
Finished Oct 11 12:22:10 PM PDT 23
Peak memory 218924 kb
Host smart-0b9620ed-860b-40c5-9b02-371cfe4baede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260800737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2260800737
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3834623364
Short name T52
Test name
Test status
Simulation time 1983046482 ps
CPU time 50.74 seconds
Started Oct 11 12:22:54 PM PDT 23
Finished Oct 11 12:23:46 PM PDT 23
Peak memory 211428 kb
Host smart-a9aa83d0-98f7-4989-bb9f-7a2e0ac71191
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834623364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3834623364
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1517425614
Short name T485
Test name
Test status
Simulation time 6742233674 ps
CPU time 13.08 seconds
Started Oct 11 12:25:43 PM PDT 23
Finished Oct 11 12:25:57 PM PDT 23
Peak memory 216624 kb
Host smart-e5ed1889-eab0-448d-bc38-194b39e955e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517425614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1517425614
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2140049710
Short name T439
Test name
Test status
Simulation time 3008719413 ps
CPU time 7.72 seconds
Started Oct 11 12:23:15 PM PDT 23
Finished Oct 11 12:23:23 PM PDT 23
Peak memory 210692 kb
Host smart-d0ba8308-d71e-45bf-a28d-56779ec89519
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140049710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2140049710
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.674982918
Short name T137
Test name
Test status
Simulation time 1687076977 ps
CPU time 5.96 seconds
Started Oct 11 12:21:38 PM PDT 23
Finished Oct 11 12:21:44 PM PDT 23
Peak memory 210596 kb
Host smart-3f02c4b3-1f6e-452e-b52b-2ece462ed82d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674982918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.674982918
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2136103688
Short name T29
Test name
Test status
Simulation time 1122439119 ps
CPU time 6.72 seconds
Started Oct 11 12:24:03 PM PDT 23
Finished Oct 11 12:24:11 PM PDT 23
Peak memory 213736 kb
Host smart-49ccf4f1-1172-43f1-8f73-019844ad746d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136103688 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2136103688
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.711965808
Short name T480
Test name
Test status
Simulation time 1376616383 ps
CPU time 6.59 seconds
Started Oct 11 12:22:49 PM PDT 23
Finished Oct 11 12:22:56 PM PDT 23
Peak memory 216240 kb
Host smart-7222c0e6-d389-40fc-bbc5-09c33f742f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711965808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.711965808
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1201301891
Short name T484
Test name
Test status
Simulation time 4065787675 ps
CPU time 15.38 seconds
Started Oct 11 12:23:51 PM PDT 23
Finished Oct 11 12:24:07 PM PDT 23
Peak memory 210688 kb
Host smart-b44e3258-4cf6-49ad-a783-c8397160feef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201301891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1201301891
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.4237356841
Short name T31
Test name
Test status
Simulation time 3398144883 ps
CPU time 9.1 seconds
Started Oct 11 12:21:54 PM PDT 23
Finished Oct 11 12:22:04 PM PDT 23
Peak memory 210684 kb
Host smart-97843c22-ee62-4ce2-b235-f57682368381
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237356841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.4237356841
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.4074049158
Short name T72
Test name
Test status
Simulation time 7761310988 ps
CPU time 102.46 seconds
Started Oct 11 12:21:40 PM PDT 23
Finished Oct 11 12:23:24 PM PDT 23
Peak memory 219048 kb
Host smart-dad0665d-2060-4fb6-ab5e-36546bc47d61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074049158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.4074049158
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2439711559
Short name T97
Test name
Test status
Simulation time 332936914 ps
CPU time 4.29 seconds
Started Oct 11 12:25:42 PM PDT 23
Finished Oct 11 12:25:47 PM PDT 23
Peak memory 210620 kb
Host smart-bfc749db-67f0-4201-a3cc-881bba3b92f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439711559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2439711559
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.870272162
Short name T78
Test name
Test status
Simulation time 640202904 ps
CPU time 6.77 seconds
Started Oct 11 12:22:53 PM PDT 23
Finished Oct 11 12:23:00 PM PDT 23
Peak memory 213740 kb
Host smart-0b780641-8f38-4a63-baaa-10e09d03bad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870272162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.870272162
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.4250151420
Short name T118
Test name
Test status
Simulation time 1263989024 ps
CPU time 7.83 seconds
Started Oct 11 12:23:26 PM PDT 23
Finished Oct 11 12:23:34 PM PDT 23
Peak memory 218856 kb
Host smart-c2d4ffef-206b-4310-a436-4a6e0e14da62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250151420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.4250151420
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2835172627
Short name T66
Test name
Test status
Simulation time 4710640203 ps
CPU time 8.41 seconds
Started Oct 11 12:24:40 PM PDT 23
Finished Oct 11 12:24:48 PM PDT 23
Peak memory 210668 kb
Host smart-d791e476-cdae-4362-b35c-babd9f965332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835172627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2835172627
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.724394182
Short name T435
Test name
Test status
Simulation time 68886962540 ps
CPU time 395.51 seconds
Started Oct 11 12:23:50 PM PDT 23
Finished Oct 11 12:30:26 PM PDT 23
Peak memory 210684 kb
Host smart-3d30438a-e071-425a-8c9b-286e66dfec69
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724394182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.724394182
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1426155031
Short name T440
Test name
Test status
Simulation time 873136292 ps
CPU time 9.03 seconds
Started Oct 11 12:22:05 PM PDT 23
Finished Oct 11 12:22:14 PM PDT 23
Peak memory 218088 kb
Host smart-744b1f03-3654-4938-b9fd-4a2f2c63bcea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426155031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1426155031
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.311969439
Short name T109
Test name
Test status
Simulation time 5037666461 ps
CPU time 10.25 seconds
Started Oct 11 12:24:37 PM PDT 23
Finished Oct 11 12:24:48 PM PDT 23
Peak memory 218896 kb
Host smart-ec8a3b7c-3240-4a2c-aae5-e0e91ba73d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311969439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.311969439
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1006361193
Short name T473
Test name
Test status
Simulation time 300291809 ps
CPU time 39.95 seconds
Started Oct 11 12:23:26 PM PDT 23
Finished Oct 11 12:24:17 PM PDT 23
Peak memory 211924 kb
Host smart-0d528177-3b4c-46e1-bf59-3fbf900ba43d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006361193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1006361193
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2648443659
Short name T140
Test name
Test status
Simulation time 873501416 ps
CPU time 9.67 seconds
Started Oct 11 12:23:49 PM PDT 23
Finished Oct 11 12:23:59 PM PDT 23
Peak memory 218832 kb
Host smart-1247de1e-279d-41d8-ac7d-599fbd99daac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648443659 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2648443659
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2854211895
Short name T103
Test name
Test status
Simulation time 1049594987 ps
CPU time 8.24 seconds
Started Oct 11 12:21:55 PM PDT 23
Finished Oct 11 12:22:04 PM PDT 23
Peak memory 210620 kb
Host smart-642e2b30-9f9a-47d7-ad03-76d2db04fbaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854211895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2854211895
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.663423831
Short name T68
Test name
Test status
Simulation time 16862109326 ps
CPU time 95.54 seconds
Started Oct 11 12:24:59 PM PDT 23
Finished Oct 11 12:26:35 PM PDT 23
Peak memory 210468 kb
Host smart-4a6f83fb-5a96-4b5b-837d-88c4df70546f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663423831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.663423831
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.443769970
Short name T96
Test name
Test status
Simulation time 23157995916 ps
CPU time 13.59 seconds
Started Oct 11 12:22:03 PM PDT 23
Finished Oct 11 12:22:17 PM PDT 23
Peak memory 210684 kb
Host smart-e58a8e25-baf7-4ae6-8569-e6f99ca4af45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443769970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.443769970
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2505584944
Short name T474
Test name
Test status
Simulation time 89294277 ps
CPU time 7.55 seconds
Started Oct 11 12:25:32 PM PDT 23
Finished Oct 11 12:25:40 PM PDT 23
Peak memory 218816 kb
Host smart-e68ee740-6514-4ebc-8999-28527a13b429
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505584944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.2505584944
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3265516332
Short name T436
Test name
Test status
Simulation time 3976061944 ps
CPU time 10.75 seconds
Started Oct 11 12:23:04 PM PDT 23
Finished Oct 11 12:23:16 PM PDT 23
Peak memory 213608 kb
Host smart-f891fcb2-0657-44bf-80aa-5f43c3adda6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265516332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3265516332
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1388994421
Short name T463
Test name
Test status
Simulation time 1317329168 ps
CPU time 11.78 seconds
Started Oct 11 12:25:24 PM PDT 23
Finished Oct 11 12:25:36 PM PDT 23
Peak memory 216912 kb
Host smart-116f2c72-eabe-4f6e-b5eb-5740ef1e707c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388994421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1388994421
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.955822769
Short name T477
Test name
Test status
Simulation time 10658099648 ps
CPU time 121.76 seconds
Started Oct 11 12:23:11 PM PDT 23
Finished Oct 11 12:25:13 PM PDT 23
Peak memory 210924 kb
Host smart-f5d24ad1-5297-4230-bfde-1ca4300b0b96
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955822769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.955822769
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3872621580
Short name T481
Test name
Test status
Simulation time 3736730188 ps
CPU time 16.3 seconds
Started Oct 11 12:25:20 PM PDT 23
Finished Oct 11 12:25:37 PM PDT 23
Peak memory 217628 kb
Host smart-5d69ae36-5766-4480-882c-b24c12584449
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872621580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3872621580
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1966114376
Short name T51
Test name
Test status
Simulation time 2846941403 ps
CPU time 16.37 seconds
Started Oct 11 12:23:18 PM PDT 23
Finished Oct 11 12:23:35 PM PDT 23
Peak memory 218872 kb
Host smart-8f3d1048-d803-4c30-a145-f711953ea9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966114376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1966114376
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.352453088
Short name T470
Test name
Test status
Simulation time 265035509 ps
CPU time 75.87 seconds
Started Oct 11 12:21:59 PM PDT 23
Finished Oct 11 12:23:15 PM PDT 23
Peak memory 218668 kb
Host smart-a30a7708-3e94-4284-b194-6c37507f598f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352453088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.352453088
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2557626721
Short name T59
Test name
Test status
Simulation time 434694504 ps
CPU time 6.91 seconds
Started Oct 11 12:25:35 PM PDT 23
Finished Oct 11 12:25:42 PM PDT 23
Peak memory 218832 kb
Host smart-b151ae9d-8a7d-4ef4-bec3-5dace35762b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557626721 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2557626721
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.140192617
Short name T83
Test name
Test status
Simulation time 1697633211 ps
CPU time 13.65 seconds
Started Oct 11 12:23:19 PM PDT 23
Finished Oct 11 12:23:33 PM PDT 23
Peak memory 217268 kb
Host smart-422767e1-8477-4684-bac3-46a3f420a1e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140192617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.140192617
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3617179452
Short name T73
Test name
Test status
Simulation time 28489914215 ps
CPU time 100.07 seconds
Started Oct 11 12:25:06 PM PDT 23
Finished Oct 11 12:26:46 PM PDT 23
Peak memory 210448 kb
Host smart-58a5435e-323e-433d-9529-c55621c6a642
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617179452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3617179452
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2585027532
Short name T134
Test name
Test status
Simulation time 4957861255 ps
CPU time 13.49 seconds
Started Oct 11 12:22:11 PM PDT 23
Finished Oct 11 12:22:24 PM PDT 23
Peak memory 210704 kb
Host smart-11ecc9a0-0bf5-40d4-b934-5ab38c3fbeb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585027532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2585027532
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1323860260
Short name T126
Test name
Test status
Simulation time 5058317627 ps
CPU time 13.42 seconds
Started Oct 11 12:25:25 PM PDT 23
Finished Oct 11 12:25:44 PM PDT 23
Peak memory 218900 kb
Host smart-d13bbd4d-ee83-4ef4-b76f-aa0907c5dfca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323860260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1323860260
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2406017931
Short name T60
Test name
Test status
Simulation time 4758248432 ps
CPU time 9.39 seconds
Started Oct 11 12:24:17 PM PDT 23
Finished Oct 11 12:24:27 PM PDT 23
Peak memory 212780 kb
Host smart-68698b30-1d32-4f53-81bc-e733bbeea0c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406017931 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2406017931
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3559745961
Short name T145
Test name
Test status
Simulation time 7529069491 ps
CPU time 14.43 seconds
Started Oct 11 12:24:03 PM PDT 23
Finished Oct 11 12:24:19 PM PDT 23
Peak memory 217152 kb
Host smart-3bf12990-6c2d-477b-8343-f52b9945dbf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559745961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3559745961
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3350826725
Short name T85
Test name
Test status
Simulation time 13889075142 ps
CPU time 90.2 seconds
Started Oct 11 12:24:05 PM PDT 23
Finished Oct 11 12:25:36 PM PDT 23
Peak memory 210464 kb
Host smart-d0cf65ed-c9b7-4edf-87e9-0b1493b9f877
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350826725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3350826725
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4172087700
Short name T94
Test name
Test status
Simulation time 2388834002 ps
CPU time 7.83 seconds
Started Oct 11 12:24:27 PM PDT 23
Finished Oct 11 12:24:35 PM PDT 23
Peak memory 216212 kb
Host smart-d921c956-57fe-427c-9a3c-a59e6d99a518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172087700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4172087700
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.74881822
Short name T144
Test name
Test status
Simulation time 2005018033 ps
CPU time 7.89 seconds
Started Oct 11 12:24:22 PM PDT 23
Finished Oct 11 12:24:32 PM PDT 23
Peak memory 213796 kb
Host smart-074ea1d2-7141-4370-af1d-7d0321188a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74881822 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.74881822
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.637393273
Short name T448
Test name
Test status
Simulation time 87185607 ps
CPU time 4.3 seconds
Started Oct 11 12:22:58 PM PDT 23
Finished Oct 11 12:23:02 PM PDT 23
Peak memory 210604 kb
Host smart-044296ae-e9fe-42cb-bab3-1cb4e01c75c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637393273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.637393273
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3401330510
Short name T71
Test name
Test status
Simulation time 29998414464 ps
CPU time 291.22 seconds
Started Oct 11 12:25:25 PM PDT 23
Finished Oct 11 12:30:17 PM PDT 23
Peak memory 210692 kb
Host smart-1d32a2d2-7831-4fc5-bc81-a8ba2bb36dd1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401330510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3401330510
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2246793186
Short name T460
Test name
Test status
Simulation time 1422061508 ps
CPU time 11.39 seconds
Started Oct 11 12:22:34 PM PDT 23
Finished Oct 11 12:22:46 PM PDT 23
Peak memory 210648 kb
Host smart-beecee0b-e3ca-4e2b-97d5-30ac1aa6a795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246793186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2246793186
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3972499737
Short name T442
Test name
Test status
Simulation time 13206409186 ps
CPU time 14.68 seconds
Started Oct 11 12:24:41 PM PDT 23
Finished Oct 11 12:24:56 PM PDT 23
Peak memory 218896 kb
Host smart-84e69d31-b81f-48db-bd0b-9d02c43a3c04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972499737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3972499737
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.3099252383
Short name T76
Test name
Test status
Simulation time 935453489 ps
CPU time 43.74 seconds
Started Oct 11 12:25:14 PM PDT 23
Finished Oct 11 12:25:58 PM PDT 23
Peak memory 211796 kb
Host smart-fa19c30e-c725-4ea7-9bed-b5ba39fb86ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099252383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.3099252383
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.81289935
Short name T131
Test name
Test status
Simulation time 1242028266 ps
CPU time 11.6 seconds
Started Oct 11 12:22:10 PM PDT 23
Finished Oct 11 12:22:22 PM PDT 23
Peak memory 213764 kb
Host smart-f2b8554b-5502-4c7e-ba24-59af13bbab08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81289935 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.81289935
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2981421213
Short name T100
Test name
Test status
Simulation time 6579767303 ps
CPU time 13.32 seconds
Started Oct 11 12:23:37 PM PDT 23
Finished Oct 11 12:23:51 PM PDT 23
Peak memory 217632 kb
Host smart-21d8dc70-55b0-4678-b633-7592d629f447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981421213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2981421213
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3710214876
Short name T462
Test name
Test status
Simulation time 1867002762 ps
CPU time 96.83 seconds
Started Oct 11 12:25:17 PM PDT 23
Finished Oct 11 12:26:54 PM PDT 23
Peak memory 210628 kb
Host smart-2f06ea6c-d316-4507-954b-f49280e2c72d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710214876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3710214876
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.83488874
Short name T130
Test name
Test status
Simulation time 3486218575 ps
CPU time 13.01 seconds
Started Oct 11 12:22:39 PM PDT 23
Finished Oct 11 12:22:53 PM PDT 23
Peak memory 218776 kb
Host smart-fb67639d-ee61-4927-a9a9-559f6e0254b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83488874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ct
rl_same_csr_outstanding.83488874
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2493926079
Short name T120
Test name
Test status
Simulation time 1028187746 ps
CPU time 8.04 seconds
Started Oct 11 12:24:58 PM PDT 23
Finished Oct 11 12:25:07 PM PDT 23
Peak memory 218848 kb
Host smart-29b25ba0-cffc-4616-8b0a-876f07b51b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493926079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2493926079
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3364678101
Short name T449
Test name
Test status
Simulation time 4143138560 ps
CPU time 49.56 seconds
Started Oct 11 12:25:15 PM PDT 23
Finished Oct 11 12:26:05 PM PDT 23
Peak memory 218856 kb
Host smart-ba0758f9-400b-436b-8e49-8b26416cc2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364678101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3364678101
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4069294898
Short name T454
Test name
Test status
Simulation time 701402824 ps
CPU time 4.34 seconds
Started Oct 11 12:25:29 PM PDT 23
Finished Oct 11 12:25:34 PM PDT 23
Peak memory 210684 kb
Host smart-251b95f3-70da-44f1-8362-0c18786822c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069294898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4069294898
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1407295149
Short name T101
Test name
Test status
Simulation time 226447623 ps
CPU time 4.14 seconds
Started Oct 11 12:25:30 PM PDT 23
Finished Oct 11 12:25:34 PM PDT 23
Peak memory 215880 kb
Host smart-689905de-dbf1-4225-9b8c-f296818f8e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407295149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1407295149
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1664920111
Short name T475
Test name
Test status
Simulation time 83528478638 ps
CPU time 274.33 seconds
Started Oct 11 12:25:01 PM PDT 23
Finished Oct 11 12:29:36 PM PDT 23
Peak memory 218572 kb
Host smart-f924a334-b591-46b1-bfa7-c2d5c24a4029
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664920111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1664920111
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1152831805
Short name T132
Test name
Test status
Simulation time 12688596412 ps
CPU time 15.04 seconds
Started Oct 11 12:25:12 PM PDT 23
Finished Oct 11 12:25:27 PM PDT 23
Peak memory 218136 kb
Host smart-f69a59d9-6491-4594-a6cb-d3b10d98183c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152831805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1152831805
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.4286450280
Short name T142
Test name
Test status
Simulation time 6149823037 ps
CPU time 17.67 seconds
Started Oct 11 12:21:56 PM PDT 23
Finished Oct 11 12:22:14 PM PDT 23
Peak memory 218860 kb
Host smart-e833f66a-2185-4b9d-a0cb-8d18bddadaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286450280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.4286450280
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.884737829
Short name T113
Test name
Test status
Simulation time 6185863108 ps
CPU time 50.97 seconds
Started Oct 11 12:23:23 PM PDT 23
Finished Oct 11 12:24:14 PM PDT 23
Peak memory 212184 kb
Host smart-b8505dd6-82d5-4cd2-ac07-383f5f735700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884737829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.884737829
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2677940806
Short name T451
Test name
Test status
Simulation time 1606634540 ps
CPU time 13.98 seconds
Started Oct 11 12:25:03 PM PDT 23
Finished Oct 11 12:25:17 PM PDT 23
Peak memory 213504 kb
Host smart-f33707f1-75d8-453b-b3ac-f5f05a1a2c99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677940806 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2677940806
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3529574513
Short name T458
Test name
Test status
Simulation time 1301488311 ps
CPU time 8.21 seconds
Started Oct 11 12:22:36 PM PDT 23
Finished Oct 11 12:22:45 PM PDT 23
Peak memory 215912 kb
Host smart-5ed28939-3c25-4149-8b75-7ee5e0fc0d45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529574513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3529574513
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2416512257
Short name T33
Test name
Test status
Simulation time 75761099034 ps
CPU time 237.71 seconds
Started Oct 11 12:25:11 PM PDT 23
Finished Oct 11 12:29:10 PM PDT 23
Peak memory 210688 kb
Host smart-272212ce-2850-4c1c-8fb6-41ef4f9294fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416512257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2416512257
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3770186497
Short name T468
Test name
Test status
Simulation time 30149886751 ps
CPU time 17.16 seconds
Started Oct 11 12:24:20 PM PDT 23
Finished Oct 11 12:24:38 PM PDT 23
Peak memory 217404 kb
Host smart-c0549e9e-bf27-403d-830f-4ab222ca5464
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770186497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3770186497
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2485042602
Short name T62
Test name
Test status
Simulation time 2146444865 ps
CPU time 19.07 seconds
Started Oct 11 12:23:22 PM PDT 23
Finished Oct 11 12:23:41 PM PDT 23
Peak memory 218844 kb
Host smart-b50dbce5-24f0-4aae-928a-1fd68874fac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485042602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2485042602
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.219497864
Short name T28
Test name
Test status
Simulation time 558275885 ps
CPU time 39.81 seconds
Started Oct 11 12:25:07 PM PDT 23
Finished Oct 11 12:25:47 PM PDT 23
Peak memory 218808 kb
Host smart-6722b439-f3ee-4263-9383-d4823fd12076
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219497864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.219497864
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1297710972
Short name T61
Test name
Test status
Simulation time 2993422077 ps
CPU time 13.64 seconds
Started Oct 11 12:25:45 PM PDT 23
Finished Oct 11 12:25:59 PM PDT 23
Peak memory 218876 kb
Host smart-5150aa25-51b8-4785-a854-294e56f7e752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297710972 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1297710972
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1790179021
Short name T133
Test name
Test status
Simulation time 753791099 ps
CPU time 4.35 seconds
Started Oct 11 12:24:02 PM PDT 23
Finished Oct 11 12:24:08 PM PDT 23
Peak memory 216304 kb
Host smart-ae0fed81-6d3a-4e72-b6f1-e9c6e04bd739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790179021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1790179021
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.739170567
Short name T88
Test name
Test status
Simulation time 31742991946 ps
CPU time 299.25 seconds
Started Oct 11 12:24:01 PM PDT 23
Finished Oct 11 12:29:00 PM PDT 23
Peak memory 210668 kb
Host smart-612b8d61-9d18-4292-8b09-3ffe3dfe6d4b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739170567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.739170567
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1222489799
Short name T67
Test name
Test status
Simulation time 4771229058 ps
CPU time 11.55 seconds
Started Oct 11 12:22:00 PM PDT 23
Finished Oct 11 12:22:12 PM PDT 23
Peak memory 210696 kb
Host smart-f66eed89-1514-446e-9a4c-a8ca950fcd12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222489799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1222489799
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3231275634
Short name T478
Test name
Test status
Simulation time 5768516952 ps
CPU time 19.77 seconds
Started Oct 11 12:25:20 PM PDT 23
Finished Oct 11 12:25:41 PM PDT 23
Peak memory 218888 kb
Host smart-1a68da55-28fe-42ba-87d4-e83e3d3eb212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231275634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3231275634
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3219209114
Short name T40
Test name
Test status
Simulation time 15907926476 ps
CPU time 76.78 seconds
Started Oct 11 12:25:50 PM PDT 23
Finished Oct 11 12:27:07 PM PDT 23
Peak memory 217712 kb
Host smart-6f7c26b4-126a-4a44-b3ad-2d6249fb1d69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219209114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3219209114
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2691023728
Short name T58
Test name
Test status
Simulation time 89301760 ps
CPU time 4.55 seconds
Started Oct 11 12:23:58 PM PDT 23
Finished Oct 11 12:24:04 PM PDT 23
Peak memory 210628 kb
Host smart-1a68a2ae-4e8d-4788-a1af-51cd815f4256
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691023728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2691023728
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1993736507
Short name T141
Test name
Test status
Simulation time 5024089949 ps
CPU time 11.88 seconds
Started Oct 11 12:21:47 PM PDT 23
Finished Oct 11 12:22:00 PM PDT 23
Peak memory 217176 kb
Host smart-9fef7134-1776-4d32-b701-6c85be5c16ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993736507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1993736507
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3055204431
Short name T459
Test name
Test status
Simulation time 7435684104 ps
CPU time 15.61 seconds
Started Oct 11 12:23:21 PM PDT 23
Finished Oct 11 12:23:37 PM PDT 23
Peak memory 218528 kb
Host smart-a53d31bc-8176-4ab6-9558-49e01fdde2e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055204431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3055204431
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.1753139942
Short name T125
Test name
Test status
Simulation time 2165418330 ps
CPU time 10.66 seconds
Started Oct 11 12:23:19 PM PDT 23
Finished Oct 11 12:23:30 PM PDT 23
Peak memory 210676 kb
Host smart-f0642a29-417f-4507-bf51-38ac49e0978c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753139942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.1753139942
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2928376927
Short name T30
Test name
Test status
Simulation time 377589107 ps
CPU time 4.12 seconds
Started Oct 11 12:25:29 PM PDT 23
Finished Oct 11 12:25:34 PM PDT 23
Peak memory 210632 kb
Host smart-7a1236fa-f0cc-4dbe-a88b-e404e3a41429
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928376927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2928376927
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1375125863
Short name T476
Test name
Test status
Simulation time 85694583 ps
CPU time 4.19 seconds
Started Oct 11 12:21:42 PM PDT 23
Finished Oct 11 12:21:47 PM PDT 23
Peak memory 210616 kb
Host smart-4f5db362-e64c-4551-a0fb-54cde4bb48cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375125863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1375125863
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2274044962
Short name T69
Test name
Test status
Simulation time 12812625820 ps
CPU time 119.11 seconds
Started Oct 11 12:24:46 PM PDT 23
Finished Oct 11 12:26:46 PM PDT 23
Peak memory 218140 kb
Host smart-870a6a29-b312-45f7-8d78-5059c19514f8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274044962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2274044962
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3487662591
Short name T469
Test name
Test status
Simulation time 755536394 ps
CPU time 4.27 seconds
Started Oct 11 12:24:03 PM PDT 23
Finished Oct 11 12:24:08 PM PDT 23
Peak memory 210616 kb
Host smart-c2e7f7d2-b660-4ada-bacf-5ec77db9578a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487662591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3487662591
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1881319540
Short name T483
Test name
Test status
Simulation time 4802342312 ps
CPU time 13.41 seconds
Started Oct 11 12:21:44 PM PDT 23
Finished Oct 11 12:21:58 PM PDT 23
Peak memory 214596 kb
Host smart-1bedbe88-f44c-4f1d-8157-9126c371a10e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881319540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1881319540
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1034554267
Short name T437
Test name
Test status
Simulation time 584484998 ps
CPU time 39.63 seconds
Started Oct 11 12:24:15 PM PDT 23
Finished Oct 11 12:24:55 PM PDT 23
Peak memory 211876 kb
Host smart-b5c0366e-759b-48fd-9c74-1be600de4520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034554267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1034554267
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1732696074
Short name T445
Test name
Test status
Simulation time 261692875 ps
CPU time 4.35 seconds
Started Oct 11 12:21:50 PM PDT 23
Finished Oct 11 12:21:54 PM PDT 23
Peak memory 216300 kb
Host smart-047ce396-4c4b-4eb0-8d76-bc8993468cf5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732696074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1732696074
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3598570254
Short name T443
Test name
Test status
Simulation time 1547289802 ps
CPU time 13.73 seconds
Started Oct 11 12:22:36 PM PDT 23
Finished Oct 11 12:22:50 PM PDT 23
Peak memory 216936 kb
Host smart-3f043bad-315f-43af-99d8-faaf7e5dbe1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598570254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3598570254
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.802721121
Short name T84
Test name
Test status
Simulation time 1988431848 ps
CPU time 11.32 seconds
Started Oct 11 12:23:18 PM PDT 23
Finished Oct 11 12:23:30 PM PDT 23
Peak memory 210636 kb
Host smart-591b8aac-3bce-4d19-9bca-f6e6d67de515
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802721121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.802721121
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.871085854
Short name T75
Test name
Test status
Simulation time 1810109317 ps
CPU time 10.16 seconds
Started Oct 11 12:21:37 PM PDT 23
Finished Oct 11 12:21:48 PM PDT 23
Peak memory 213716 kb
Host smart-c5249d36-0847-414a-9f3b-bd735f556550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871085854 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.871085854
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1174773726
Short name T35
Test name
Test status
Simulation time 86374722 ps
CPU time 4.24 seconds
Started Oct 11 12:21:44 PM PDT 23
Finished Oct 11 12:21:49 PM PDT 23
Peak memory 210576 kb
Host smart-ee299cbd-6a4d-46bb-b09e-6931a9d65464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174773726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1174773726
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1164835186
Short name T472
Test name
Test status
Simulation time 171720901 ps
CPU time 4.21 seconds
Started Oct 11 12:22:09 PM PDT 23
Finished Oct 11 12:22:14 PM PDT 23
Peak memory 210404 kb
Host smart-c7ced3c1-3194-4c9d-9fbf-9d22b4d7d3fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164835186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.1164835186
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.180342509
Short name T123
Test name
Test status
Simulation time 5670269555 ps
CPU time 9.03 seconds
Started Oct 11 12:24:10 PM PDT 23
Finished Oct 11 12:24:19 PM PDT 23
Peak memory 210684 kb
Host smart-57fcf35a-35c0-43f2-a7a1-2fe0ab7156a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180342509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
180342509
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1342492896
Short name T479
Test name
Test status
Simulation time 1421470667 ps
CPU time 12.18 seconds
Started Oct 11 12:25:26 PM PDT 23
Finished Oct 11 12:25:39 PM PDT 23
Peak memory 210612 kb
Host smart-88b22ee2-0ff0-43e8-ab18-207b348178f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342492896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1342492896
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2228617324
Short name T482
Test name
Test status
Simulation time 3521847711 ps
CPU time 9.56 seconds
Started Oct 11 12:22:02 PM PDT 23
Finished Oct 11 12:22:12 PM PDT 23
Peak memory 218908 kb
Host smart-84779181-193a-4ab4-adb9-724c1a4bd695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228617324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2228617324
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4266453013
Short name T55
Test name
Test status
Simulation time 232978267 ps
CPU time 39.17 seconds
Started Oct 11 12:21:42 PM PDT 23
Finished Oct 11 12:22:22 PM PDT 23
Peak memory 218772 kb
Host smart-b42f972b-1089-49a9-9a5c-88b84c8f4c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266453013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4266453013
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3707347619
Short name T102
Test name
Test status
Simulation time 3330877500 ps
CPU time 13.76 seconds
Started Oct 11 12:22:03 PM PDT 23
Finished Oct 11 12:22:17 PM PDT 23
Peak memory 210696 kb
Host smart-90e28355-f6e4-4d51-b0da-af4cbb673431
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707347619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3707347619
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.848428019
Short name T139
Test name
Test status
Simulation time 3445903764 ps
CPU time 9.89 seconds
Started Oct 11 12:23:18 PM PDT 23
Finished Oct 11 12:23:29 PM PDT 23
Peak memory 217296 kb
Host smart-b5d41848-dc59-484a-b487-2aff8f4e015d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848428019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.848428019
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.572469375
Short name T446
Test name
Test status
Simulation time 4250749926 ps
CPU time 18.17 seconds
Started Oct 11 12:24:53 PM PDT 23
Finished Oct 11 12:25:12 PM PDT 23
Peak memory 217460 kb
Host smart-fd076672-c8df-4647-b37b-2d17429a10f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572469375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.572469375
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2104222403
Short name T136
Test name
Test status
Simulation time 4159072762 ps
CPU time 10.55 seconds
Started Oct 11 12:25:26 PM PDT 23
Finished Oct 11 12:25:37 PM PDT 23
Peak memory 218868 kb
Host smart-e362cbe2-2c44-4961-8adb-9a241c36cc21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104222403 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2104222403
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3271384525
Short name T461
Test name
Test status
Simulation time 5099097221 ps
CPU time 11.73 seconds
Started Oct 11 12:21:44 PM PDT 23
Finished Oct 11 12:21:56 PM PDT 23
Peak memory 210676 kb
Host smart-22c3fc4d-6f5c-47d6-bf9e-0f6776198b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271384525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3271384525
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2937828040
Short name T441
Test name
Test status
Simulation time 1649514742 ps
CPU time 9.08 seconds
Started Oct 11 12:23:07 PM PDT 23
Finished Oct 11 12:23:17 PM PDT 23
Peak memory 210640 kb
Host smart-26ab1678-ae69-42dd-8faa-6001768703cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937828040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2937828040
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3668826282
Short name T467
Test name
Test status
Simulation time 1719712036 ps
CPU time 6.73 seconds
Started Oct 11 12:25:40 PM PDT 23
Finished Oct 11 12:25:49 PM PDT 23
Peak memory 210636 kb
Host smart-a81efd13-6648-42ca-9d64-6b1cc44b995a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668826282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3668826282
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1690637529
Short name T74
Test name
Test status
Simulation time 33549595177 ps
CPU time 195.74 seconds
Started Oct 11 12:23:26 PM PDT 23
Finished Oct 11 12:26:49 PM PDT 23
Peak memory 210688 kb
Host smart-40036308-7276-45e3-90b6-1e6d71299628
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690637529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1690637529
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2497932420
Short name T93
Test name
Test status
Simulation time 249474438 ps
CPU time 6.02 seconds
Started Oct 11 12:25:12 PM PDT 23
Finished Oct 11 12:25:19 PM PDT 23
Peak memory 210472 kb
Host smart-3d82069e-a409-4d94-b2df-848d88480a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497932420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2497932420
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.767314910
Short name T456
Test name
Test status
Simulation time 849031341 ps
CPU time 11.47 seconds
Started Oct 11 12:21:48 PM PDT 23
Finished Oct 11 12:22:00 PM PDT 23
Peak memory 218820 kb
Host smart-9c832883-1ffa-43ca-a3dc-82e53e4da047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767314910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.767314910
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1959822419
Short name T124
Test name
Test status
Simulation time 1160354404 ps
CPU time 10.86 seconds
Started Oct 11 12:24:37 PM PDT 23
Finished Oct 11 12:24:49 PM PDT 23
Peak memory 212076 kb
Host smart-aee1b836-168d-491c-bc2f-996e435dc711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959822419 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1959822419
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3533545038
Short name T453
Test name
Test status
Simulation time 5476280748 ps
CPU time 7.33 seconds
Started Oct 11 12:25:38 PM PDT 23
Finished Oct 11 12:25:46 PM PDT 23
Peak memory 216132 kb
Host smart-2addc87d-d3db-468b-966d-46a0d76fe7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533545038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3533545038
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1960363403
Short name T455
Test name
Test status
Simulation time 7129579315 ps
CPU time 12.46 seconds
Started Oct 11 12:21:56 PM PDT 23
Finished Oct 11 12:22:09 PM PDT 23
Peak memory 210656 kb
Host smart-34d430d9-52cb-48ec-bef0-63c6096c2d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960363403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1960363403
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.4247138863
Short name T465
Test name
Test status
Simulation time 1835544940 ps
CPU time 17.03 seconds
Started Oct 11 12:25:43 PM PDT 23
Finished Oct 11 12:26:01 PM PDT 23
Peak memory 218828 kb
Host smart-b7a3a1e6-b4d6-4b3e-aa65-3a529b2a972c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247138863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.4247138863
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4151709528
Short name T115
Test name
Test status
Simulation time 8515810255 ps
CPU time 79.08 seconds
Started Oct 11 12:25:22 PM PDT 23
Finished Oct 11 12:26:43 PM PDT 23
Peak memory 210388 kb
Host smart-866d7261-79f0-4aba-aedc-b05131b055e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151709528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4151709528
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2591310837
Short name T77
Test name
Test status
Simulation time 632605528 ps
CPU time 9.77 seconds
Started Oct 11 12:24:15 PM PDT 23
Finished Oct 11 12:24:25 PM PDT 23
Peak memory 218604 kb
Host smart-075a522e-53e2-41ac-b987-fade25a9a9b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591310837 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2591310837
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2515048369
Short name T464
Test name
Test status
Simulation time 1633374576 ps
CPU time 13.92 seconds
Started Oct 11 12:22:36 PM PDT 23
Finished Oct 11 12:22:50 PM PDT 23
Peak memory 210616 kb
Host smart-4bb92565-24be-4ccc-aac9-309ab987ec13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515048369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2515048369
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.822488761
Short name T452
Test name
Test status
Simulation time 28780744112 ps
CPU time 254.76 seconds
Started Oct 11 12:25:14 PM PDT 23
Finished Oct 11 12:29:29 PM PDT 23
Peak memory 210688 kb
Host smart-81df2050-7ca8-49d3-9d9a-c4f1f9816fc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822488761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.822488761
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.888697056
Short name T438
Test name
Test status
Simulation time 91901290 ps
CPU time 6.06 seconds
Started Oct 11 12:24:37 PM PDT 23
Finished Oct 11 12:24:44 PM PDT 23
Peak memory 210604 kb
Host smart-64f47013-a53a-4788-a0ae-d2da646b1e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888697056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.888697056
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1571374262
Short name T121
Test name
Test status
Simulation time 1836124204 ps
CPU time 15.15 seconds
Started Oct 11 12:23:12 PM PDT 23
Finished Oct 11 12:23:28 PM PDT 23
Peak memory 218840 kb
Host smart-5d9bd28b-6dfc-4b2b-a4fa-3fb59974f791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571374262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1571374262
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.681613713
Short name T112
Test name
Test status
Simulation time 1512664714 ps
CPU time 46.28 seconds
Started Oct 11 12:24:16 PM PDT 23
Finished Oct 11 12:25:03 PM PDT 23
Peak memory 218808 kb
Host smart-5fa65ba8-2578-4ef3-91b1-04426e670697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681613713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.681613713
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1969134014
Short name T53
Test name
Test status
Simulation time 994424813 ps
CPU time 10.29 seconds
Started Oct 11 12:22:42 PM PDT 23
Finished Oct 11 12:22:52 PM PDT 23
Peak memory 213192 kb
Host smart-b0d9d949-0768-400a-9199-e2f95aa7dfbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969134014 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1969134014
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2090662736
Short name T466
Test name
Test status
Simulation time 380971758 ps
CPU time 6.43 seconds
Started Oct 11 12:24:20 PM PDT 23
Finished Oct 11 12:24:27 PM PDT 23
Peak memory 210616 kb
Host smart-b7c7fc83-0775-4225-b026-5ed9d866f4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090662736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2090662736
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1267203949
Short name T87
Test name
Test status
Simulation time 28268488850 ps
CPU time 130.13 seconds
Started Oct 11 12:24:07 PM PDT 23
Finished Oct 11 12:26:18 PM PDT 23
Peak memory 209960 kb
Host smart-fb511d61-2dea-43c4-b86c-0955353f3616
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267203949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1267203949
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.186251674
Short name T95
Test name
Test status
Simulation time 4111701509 ps
CPU time 17.4 seconds
Started Oct 11 12:23:21 PM PDT 23
Finished Oct 11 12:23:39 PM PDT 23
Peak memory 218840 kb
Host smart-66c222ff-b8f4-4682-bfce-86ba572b8f3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186251674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.186251674
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2355026928
Short name T127
Test name
Test status
Simulation time 5507128633 ps
CPU time 14.17 seconds
Started Oct 11 12:21:56 PM PDT 23
Finished Oct 11 12:22:11 PM PDT 23
Peak memory 218880 kb
Host smart-969dbaa3-c49c-4bb8-ad5a-0162f4f62ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355026928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2355026928
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.853385463
Short name T117
Test name
Test status
Simulation time 1989491486 ps
CPU time 75.34 seconds
Started Oct 11 12:24:15 PM PDT 23
Finished Oct 11 12:25:31 PM PDT 23
Peak memory 210764 kb
Host smart-15fb0408-d426-4791-842f-5b999f3446ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853385463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.853385463
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2081777178
Short name T450
Test name
Test status
Simulation time 1921621820 ps
CPU time 12.13 seconds
Started Oct 11 12:22:08 PM PDT 23
Finished Oct 11 12:22:20 PM PDT 23
Peak memory 213308 kb
Host smart-809e4a83-9cf8-4ce4-83da-71ae309d9830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081777178 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2081777178
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1668253466
Short name T79
Test name
Test status
Simulation time 1841160708 ps
CPU time 14.94 seconds
Started Oct 11 12:22:43 PM PDT 23
Finished Oct 11 12:22:58 PM PDT 23
Peak memory 216968 kb
Host smart-630951bc-e979-4e71-a2b0-39edbfb9672b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668253466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1668253466
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2754383451
Short name T36
Test name
Test status
Simulation time 1203050414 ps
CPU time 12.56 seconds
Started Oct 11 12:24:11 PM PDT 23
Finished Oct 11 12:24:29 PM PDT 23
Peak memory 218864 kb
Host smart-68f81072-4faa-482c-895a-c4736f43a20b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754383451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2754383451
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.642901565
Short name T143
Test name
Test status
Simulation time 3843947625 ps
CPU time 47.14 seconds
Started Oct 11 12:26:07 PM PDT 23
Finished Oct 11 12:26:54 PM PDT 23
Peak memory 218920 kb
Host smart-f9f609e5-f095-402d-b71d-c3e41993359a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642901565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.642901565
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.4264665988
Short name T56
Test name
Test status
Simulation time 20475340748 ps
CPU time 10.83 seconds
Started Oct 11 12:25:32 PM PDT 23
Finished Oct 11 12:25:44 PM PDT 23
Peak memory 214456 kb
Host smart-b6f1e7a7-c993-4057-a365-0473588298ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264665988 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.4264665988
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2665454897
Short name T104
Test name
Test status
Simulation time 1954132147 ps
CPU time 14.72 seconds
Started Oct 11 12:25:17 PM PDT 23
Finished Oct 11 12:25:32 PM PDT 23
Peak memory 210624 kb
Host smart-233d1d31-462f-4d06-986b-42f541b32d6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665454897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2665454897
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.3505897466
Short name T86
Test name
Test status
Simulation time 50836793160 ps
CPU time 125.32 seconds
Started Oct 11 12:21:56 PM PDT 23
Finished Oct 11 12:24:02 PM PDT 23
Peak memory 210112 kb
Host smart-6e643805-1a99-430a-a1e4-6ecd04e71c72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505897466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.3505897466
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.1777301890
Short name T457
Test name
Test status
Simulation time 7056586088 ps
CPU time 15.5 seconds
Started Oct 11 12:22:29 PM PDT 23
Finished Oct 11 12:22:45 PM PDT 23
Peak memory 210684 kb
Host smart-6ab25dd8-2cbc-4b2e-9bff-9216960da49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777301890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.1777301890
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2838717437
Short name T119
Test name
Test status
Simulation time 3930842556 ps
CPU time 14.54 seconds
Started Oct 11 12:22:03 PM PDT 23
Finished Oct 11 12:22:18 PM PDT 23
Peak memory 218892 kb
Host smart-ef526991-afa3-44d4-a2dc-e06587e0c014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838717437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2838717437
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1319535506
Short name T138
Test name
Test status
Simulation time 276266683 ps
CPU time 73.47 seconds
Started Oct 11 12:25:16 PM PDT 23
Finished Oct 11 12:26:30 PM PDT 23
Peak memory 218812 kb
Host smart-d50a8452-72b4-4679-a738-022a1402c275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319535506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1319535506
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2022516965
Short name T318
Test name
Test status
Simulation time 1282559288 ps
CPU time 12.34 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:11 PM PDT 23
Peak memory 211064 kb
Host smart-bc4d2de6-53e7-422e-8703-1ccddf3d35e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022516965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2022516965
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1419774222
Short name T321
Test name
Test status
Simulation time 2765227961 ps
CPU time 183.04 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:28:26 PM PDT 23
Peak memory 236728 kb
Host smart-0368aad1-1b81-49f8-80b8-405a9bbf2ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419774222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1419774222
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1420408320
Short name T293
Test name
Test status
Simulation time 10307491945 ps
CPU time 14.32 seconds
Started Oct 11 01:24:59 PM PDT 23
Finished Oct 11 01:25:14 PM PDT 23
Peak memory 211124 kb
Host smart-f0f64ec0-6381-4023-a40e-bc7520898e69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420408320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1420408320
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2308346667
Short name T324
Test name
Test status
Simulation time 4648387440 ps
CPU time 17.62 seconds
Started Oct 11 01:25:14 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 213148 kb
Host smart-5eb73836-4ebd-45bb-9f53-ba9d39450c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308346667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2308346667
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2132678880
Short name T428
Test name
Test status
Simulation time 2311707191 ps
CPU time 17.54 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:40 PM PDT 23
Peak memory 213416 kb
Host smart-f7b34eac-1907-4fc0-a8a7-89531b60e4a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132678880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2132678880
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3517784964
Short name T225
Test name
Test status
Simulation time 1962996704 ps
CPU time 15.58 seconds
Started Oct 11 01:26:54 PM PDT 23
Finished Oct 11 01:27:10 PM PDT 23
Peak memory 211024 kb
Host smart-78ae8188-0dae-4058-9c41-5306b8c27227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517784964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3517784964
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3865639737
Short name T411
Test name
Test status
Simulation time 12104158280 ps
CPU time 106.12 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:27:47 PM PDT 23
Peak memory 212588 kb
Host smart-9294c4a1-c851-41e3-9a84-fa6d5b1ce1ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865639737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3865639737
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.761605761
Short name T18
Test name
Test status
Simulation time 3387422593 ps
CPU time 29.98 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:44 PM PDT 23
Peak memory 211292 kb
Host smart-1b6c18d1-29ff-4be5-90a8-020095b8848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761605761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.761605761
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.209060461
Short name T201
Test name
Test status
Simulation time 488800679 ps
CPU time 8.46 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:26:08 PM PDT 23
Peak memory 211052 kb
Host smart-4245e11c-a524-460f-a978-43a475d714f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=209060461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.209060461
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1503890025
Short name T42
Test name
Test status
Simulation time 2343611195 ps
CPU time 60.99 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:27:12 PM PDT 23
Peak memory 236840 kb
Host smart-a0fe81df-0204-423f-ae5e-4a9172bcc421
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503890025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1503890025
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3973085334
Short name T292
Test name
Test status
Simulation time 15364038578 ps
CPU time 31.14 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:35 PM PDT 23
Peak memory 213444 kb
Host smart-5738dc6a-0f80-455f-b845-9df3990c0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973085334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3973085334
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3484006144
Short name T272
Test name
Test status
Simulation time 5529313260 ps
CPU time 45.43 seconds
Started Oct 11 01:25:27 PM PDT 23
Finished Oct 11 01:26:13 PM PDT 23
Peak memory 215128 kb
Host smart-1d58c136-101b-4b69-a1e1-f2e20a84076a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484006144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3484006144
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.403014508
Short name T391
Test name
Test status
Simulation time 17838418861 ps
CPU time 724.04 seconds
Started Oct 11 01:26:56 PM PDT 23
Finished Oct 11 01:39:01 PM PDT 23
Peak memory 227624 kb
Host smart-fd46c953-1e9d-4534-bbc9-1e2f67c79039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403014508 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.403014508
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.887520939
Short name T408
Test name
Test status
Simulation time 2037942361 ps
CPU time 14.66 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:25:17 PM PDT 23
Peak memory 211032 kb
Host smart-6294e05f-f1be-4f09-bb76-d53e3a5d31d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887520939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.887520939
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3864055872
Short name T400
Test name
Test status
Simulation time 79380445035 ps
CPU time 280.2 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:29:43 PM PDT 23
Peak memory 236612 kb
Host smart-da0f3a4d-bb24-4c85-8606-690ec6799f0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864055872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3864055872
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1545550260
Short name T409
Test name
Test status
Simulation time 2674799094 ps
CPU time 24.21 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:22 PM PDT 23
Peak memory 211216 kb
Host smart-e7e7f497-b232-4a3a-951b-396aee18ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545550260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1545550260
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2747621483
Short name T90
Test name
Test status
Simulation time 19486912500 ps
CPU time 13.74 seconds
Started Oct 11 01:25:18 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 211184 kb
Host smart-1df4e6b0-651b-46d9-9ee7-541ed030319b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747621483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2747621483
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.263242141
Short name T370
Test name
Test status
Simulation time 3859968672 ps
CPU time 25.17 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 212740 kb
Host smart-c4f1e9e6-24a5-4b0c-a51f-c71802f95129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263242141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.263242141
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.757145156
Short name T193
Test name
Test status
Simulation time 237389166 ps
CPU time 16.82 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:40 PM PDT 23
Peak memory 212392 kb
Host smart-2cc42266-c022-454f-adea-f94b5f0e43b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757145156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.757145156
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.1054541793
Short name T216
Test name
Test status
Simulation time 26312435489 ps
CPU time 7069.65 seconds
Started Oct 11 01:25:00 PM PDT 23
Finished Oct 11 03:22:51 PM PDT 23
Peak memory 235816 kb
Host smart-1ea1ef62-d904-413d-ae7f-2af8e347a52b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054541793 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.1054541793
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.782848852
Short name T355
Test name
Test status
Simulation time 173997935 ps
CPU time 5.44 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:31 PM PDT 23
Peak memory 211060 kb
Host smart-e702db08-d932-4dcc-95e8-b3c1ff22fa25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782848852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.782848852
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3636197818
Short name T222
Test name
Test status
Simulation time 7988808322 ps
CPU time 132.09 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:27:33 PM PDT 23
Peak memory 228084 kb
Host smart-2adc4566-637a-412c-ad9f-f0fc3e453d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636197818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3636197818
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.341818950
Short name T180
Test name
Test status
Simulation time 3150150644 ps
CPU time 27.46 seconds
Started Oct 11 01:25:28 PM PDT 23
Finished Oct 11 01:25:55 PM PDT 23
Peak memory 211312 kb
Host smart-f4317f60-edc6-405f-be21-fa3af969b01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341818950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.341818950
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.72615007
Short name T384
Test name
Test status
Simulation time 5318887839 ps
CPU time 13.83 seconds
Started Oct 11 01:25:18 PM PDT 23
Finished Oct 11 01:25:33 PM PDT 23
Peak memory 211092 kb
Host smart-542684ab-f409-4f69-ad75-1ecce6811a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72615007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.72615007
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3259797478
Short name T204
Test name
Test status
Simulation time 4306888381 ps
CPU time 23.67 seconds
Started Oct 11 01:26:04 PM PDT 23
Finished Oct 11 01:26:28 PM PDT 23
Peak memory 213020 kb
Host smart-bf9a576d-777c-497f-9eef-bac1cd1273f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259797478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3259797478
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.4196461737
Short name T194
Test name
Test status
Simulation time 8377002388 ps
CPU time 27.75 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:48 PM PDT 23
Peak memory 214552 kb
Host smart-90230908-0b07-4957-b912-28eaf52da561
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196461737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.4196461737
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.1396603969
Short name T322
Test name
Test status
Simulation time 61003371810 ps
CPU time 3453.04 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 02:23:32 PM PDT 23
Peak memory 231100 kb
Host smart-da34fb4e-a970-4264-b49a-7c8417a6d74f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396603969 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.1396603969
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3457921584
Short name T319
Test name
Test status
Simulation time 1424204294 ps
CPU time 12.49 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:16 PM PDT 23
Peak memory 210984 kb
Host smart-27775ecb-7958-4ff4-a217-530c41209092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457921584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3457921584
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1407070641
Short name T297
Test name
Test status
Simulation time 12675906838 ps
CPU time 153.5 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:27:53 PM PDT 23
Peak memory 224380 kb
Host smart-3bbb9a30-edc6-4a7e-bdd1-fd42c11968d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407070641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1407070641
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2190082028
Short name T419
Test name
Test status
Simulation time 2278691622 ps
CPU time 23.72 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:25:26 PM PDT 23
Peak memory 211288 kb
Host smart-88e9bafe-dcdc-4729-9893-ad698d10a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190082028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2190082028
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2531943813
Short name T367
Test name
Test status
Simulation time 358088190 ps
CPU time 5.62 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:26:05 PM PDT 23
Peak memory 211092 kb
Host smart-100824be-5980-4e16-8773-ee42caee329c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531943813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2531943813
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.274840976
Short name T260
Test name
Test status
Simulation time 746245422 ps
CPU time 10.46 seconds
Started Oct 11 01:25:16 PM PDT 23
Finished Oct 11 01:25:27 PM PDT 23
Peak memory 212552 kb
Host smart-f00e84cb-f9a9-4540-99f3-a802cdd67a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274840976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.274840976
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.821639482
Short name T244
Test name
Test status
Simulation time 834167252 ps
CPU time 18.45 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:40 PM PDT 23
Peak memory 213240 kb
Host smart-debe738e-3e70-4f22-8bea-f47d9afb7e54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821639482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.821639482
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.773720836
Short name T334
Test name
Test status
Simulation time 164613200478 ps
CPU time 5643.88 seconds
Started Oct 11 01:26:02 PM PDT 23
Finished Oct 11 03:00:07 PM PDT 23
Peak memory 266152 kb
Host smart-c5183ead-1849-4b56-892a-ceb30d5a1682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773720836 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.773720836
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.649418125
Short name T348
Test name
Test status
Simulation time 5272811677 ps
CPU time 11.82 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:25:38 PM PDT 23
Peak memory 211172 kb
Host smart-9ebecdd1-581f-4e2a-a1eb-2d37c8991a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649418125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.649418125
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3423161155
Short name T49
Test name
Test status
Simulation time 121598245040 ps
CPU time 298.51 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:30:20 PM PDT 23
Peak memory 227696 kb
Host smart-8e60a9ed-7b81-4a36-8cf7-d493849026d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423161155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3423161155
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2238347422
Short name T203
Test name
Test status
Simulation time 3601503668 ps
CPU time 30.46 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:25:33 PM PDT 23
Peak memory 211284 kb
Host smart-2999c7a5-158e-40aa-9176-2d1320d386a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238347422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2238347422
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1472756210
Short name T389
Test name
Test status
Simulation time 3151314913 ps
CPU time 10.41 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:26:10 PM PDT 23
Peak memory 211208 kb
Host smart-d26e3e58-66a5-46e0-b5af-e038654a4b27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472756210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1472756210
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3462187441
Short name T187
Test name
Test status
Simulation time 5514129869 ps
CPU time 21.44 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:44 PM PDT 23
Peak memory 212852 kb
Host smart-d4721fc9-2fda-4fd3-866c-bb1387769567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462187441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3462187441
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1110929825
Short name T392
Test name
Test status
Simulation time 712647966 ps
CPU time 20.7 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:24 PM PDT 23
Peak memory 215848 kb
Host smart-5993abce-289c-414f-86e7-4f9179a6c6d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110929825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1110929825
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3601526848
Short name T155
Test name
Test status
Simulation time 184158007967 ps
CPU time 5998.5 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 03:05:58 PM PDT 23
Peak memory 233424 kb
Host smart-c32ab1d1-9967-491a-8805-4af1d3a60663
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601526848 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3601526848
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2673407904
Short name T371
Test name
Test status
Simulation time 334135822 ps
CPU time 4.48 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:26:16 PM PDT 23
Peak memory 211072 kb
Host smart-3820ed36-ef43-43b7-9c93-30bbd0da4fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673407904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2673407904
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2078168328
Short name T344
Test name
Test status
Simulation time 1640322512 ps
CPU time 98.75 seconds
Started Oct 11 01:25:57 PM PDT 23
Finished Oct 11 01:27:36 PM PDT 23
Peak memory 224376 kb
Host smart-1fa59954-9e0c-4812-91d9-1eef544491db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078168328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.2078168328
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3869525114
Short name T257
Test name
Test status
Simulation time 20778417985 ps
CPU time 26.95 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:48 PM PDT 23
Peak memory 212428 kb
Host smart-79fa7cdb-9eb3-42e4-bdf1-19398aba6a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869525114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3869525114
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2533742123
Short name T186
Test name
Test status
Simulation time 8708833495 ps
CPU time 17.16 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:26:29 PM PDT 23
Peak memory 211216 kb
Host smart-8ffb8970-8b7d-43f6-a43c-3d6e35bd39fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533742123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2533742123
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3204725236
Short name T323
Test name
Test status
Simulation time 12436592806 ps
CPU time 17.75 seconds
Started Oct 11 01:25:05 PM PDT 23
Finished Oct 11 01:25:23 PM PDT 23
Peak memory 213628 kb
Host smart-7ce90ed0-3303-44f1-bd50-c37629636196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204725236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3204725236
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1890116984
Short name T44
Test name
Test status
Simulation time 42715872860 ps
CPU time 83.84 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:26:50 PM PDT 23
Peak memory 218496 kb
Host smart-a640ac45-32a1-49f3-a857-6b528a78943c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890116984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1890116984
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.79885924
Short name T231
Test name
Test status
Simulation time 3783125026 ps
CPU time 10.23 seconds
Started Oct 11 01:25:00 PM PDT 23
Finished Oct 11 01:25:10 PM PDT 23
Peak memory 211156 kb
Host smart-c368b745-e0a7-440d-ab7a-7ea545fd81d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79885924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.79885924
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2304831888
Short name T242
Test name
Test status
Simulation time 3504527154 ps
CPU time 114.25 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:27:19 PM PDT 23
Peak memory 237800 kb
Host smart-f56b4783-9e83-4191-97ea-3a6aa1d3c436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304831888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2304831888
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3602418023
Short name T278
Test name
Test status
Simulation time 4515609585 ps
CPU time 11.17 seconds
Started Oct 11 01:25:33 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 211264 kb
Host smart-aac37417-cbbc-46d0-a201-c8af9bb63436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3602418023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3602418023
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1048951768
Short name T263
Test name
Test status
Simulation time 37892604537 ps
CPU time 22.39 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:25:47 PM PDT 23
Peak memory 213436 kb
Host smart-33c950e0-f48a-4dd2-9774-c867d22235e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048951768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1048951768
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1359650525
Short name T276
Test name
Test status
Simulation time 12463505461 ps
CPU time 110.21 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:27:54 PM PDT 23
Peak memory 216632 kb
Host smart-2620ee72-a7d8-4ccb-89a0-263e2ad977bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359650525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1359650525
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2530500373
Short name T368
Test name
Test status
Simulation time 4752624276 ps
CPU time 11.39 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:25:36 PM PDT 23
Peak memory 211184 kb
Host smart-a272f896-3b9f-4c89-8070-5271f0564049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530500373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2530500373
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3224456532
Short name T330
Test name
Test status
Simulation time 158913017079 ps
CPU time 276.18 seconds
Started Oct 11 01:26:02 PM PDT 23
Finished Oct 11 01:30:39 PM PDT 23
Peak memory 227576 kb
Host smart-956be4ff-ab9c-49ff-a55a-8617a7e63373
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224456532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3224456532
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2546346129
Short name T17
Test name
Test status
Simulation time 8236024400 ps
CPU time 33.34 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:55 PM PDT 23
Peak memory 211720 kb
Host smart-756c797d-5303-47aa-85d6-4fa986534837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546346129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2546346129
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.205521033
Short name T382
Test name
Test status
Simulation time 384405197 ps
CPU time 7.73 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:25:34 PM PDT 23
Peak memory 210960 kb
Host smart-1034e79f-433c-4999-9d6b-591eba3cfc6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=205521033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.205521033
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2934651456
Short name T192
Test name
Test status
Simulation time 7893500530 ps
CPU time 21.45 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 214044 kb
Host smart-614c0ed6-998c-45ea-970e-523c69e51ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934651456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2934651456
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.129337617
Short name T288
Test name
Test status
Simulation time 6112038021 ps
CPU time 68.68 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:27:09 PM PDT 23
Peak memory 215460 kb
Host smart-4460a39f-5425-4aa6-9f07-c3a106cbbc8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129337617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.129337617
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2469671635
Short name T289
Test name
Test status
Simulation time 40366228016 ps
CPU time 299.96 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:30:58 PM PDT 23
Peak memory 237724 kb
Host smart-ce8b20c7-b341-44c5-ae32-3619a949152d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469671635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2469671635
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2180662767
Short name T160
Test name
Test status
Simulation time 2571927883 ps
CPU time 24.53 seconds
Started Oct 11 01:25:16 PM PDT 23
Finished Oct 11 01:25:41 PM PDT 23
Peak memory 211992 kb
Host smart-80a11763-0e7b-4caf-9a06-2fbb6d34f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180662767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2180662767
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1101163782
Short name T421
Test name
Test status
Simulation time 1348147031 ps
CPU time 13.42 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:39 PM PDT 23
Peak memory 211068 kb
Host smart-043ea7c1-1d9b-41a4-a12d-29bac4e8cdc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1101163782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1101163782
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.339362721
Short name T80
Test name
Test status
Simulation time 5857945177 ps
CPU time 32.09 seconds
Started Oct 11 01:25:18 PM PDT 23
Finished Oct 11 01:25:50 PM PDT 23
Peak memory 213356 kb
Host smart-e056b8ae-00c0-431e-909d-7e93ca9c2bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339362721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.339362721
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2754588213
Short name T98
Test name
Test status
Simulation time 3201015219 ps
CPU time 24.29 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:25 PM PDT 23
Peak memory 215044 kb
Host smart-a73e7ff2-50b2-45b8-8e4a-a2917afbbc32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754588213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2754588213
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.147694235
Short name T230
Test name
Test status
Simulation time 34721536151 ps
CPU time 1629.75 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:52:34 PM PDT 23
Peak memory 235776 kb
Host smart-1b7dbc44-82a5-4925-88d9-7cb8eeea10fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147694235 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.147694235
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3630608945
Short name T211
Test name
Test status
Simulation time 168346970 ps
CPU time 4.31 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:27 PM PDT 23
Peak memory 211044 kb
Host smart-cfda12c3-3758-42dd-aebd-51117877cc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630608945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3630608945
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2662879601
Short name T401
Test name
Test status
Simulation time 201193422849 ps
CPU time 499.63 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:33:43 PM PDT 23
Peak memory 212372 kb
Host smart-76218c90-0d5c-4eb4-abe5-833607cde303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662879601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2662879601
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2127905947
Short name T251
Test name
Test status
Simulation time 2204140789 ps
CPU time 23.93 seconds
Started Oct 11 01:25:57 PM PDT 23
Finished Oct 11 01:26:21 PM PDT 23
Peak memory 211148 kb
Host smart-324cd560-bec2-45f6-bbcc-968969c8ebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127905947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2127905947
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.4082547000
Short name T233
Test name
Test status
Simulation time 3653064598 ps
CPU time 11.13 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 211184 kb
Host smart-9995e3b5-902a-494a-88d2-61751947b1fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082547000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.4082547000
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2996709880
Short name T243
Test name
Test status
Simulation time 2646333317 ps
CPU time 29.17 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:25:54 PM PDT 23
Peak memory 212744 kb
Host smart-8c359008-2f02-4265-9526-165bdcbb2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996709880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2996709880
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.59967958
Short name T150
Test name
Test status
Simulation time 1556299004 ps
CPU time 16.3 seconds
Started Oct 11 01:25:16 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 210940 kb
Host smart-51cf3bf6-31f4-4dc4-a7ad-093c75a10f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59967958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 18.rom_ctrl_stress_all.59967958
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.367468187
Short name T313
Test name
Test status
Simulation time 1202303971 ps
CPU time 11.72 seconds
Started Oct 11 01:25:33 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 211172 kb
Host smart-b74e0f0e-3097-4a1f-8411-9f63ecc3b368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367468187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.367468187
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1652833890
Short name T306
Test name
Test status
Simulation time 4381188155 ps
CPU time 145.84 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:27:49 PM PDT 23
Peak memory 234876 kb
Host smart-40dceb3d-aa24-472a-a740-33ac9ff49321
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652833890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1652833890
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2250527604
Short name T431
Test name
Test status
Simulation time 8220499549 ps
CPU time 22.37 seconds
Started Oct 11 01:26:48 PM PDT 23
Finished Oct 11 01:27:11 PM PDT 23
Peak memory 211848 kb
Host smart-91c178d3-5bd3-4d64-bcb9-2e8b1e337d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250527604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2250527604
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1651295924
Short name T105
Test name
Test status
Simulation time 8670729520 ps
CPU time 18.08 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:40 PM PDT 23
Peak memory 211132 kb
Host smart-897afaa1-5ba1-4800-87cd-b6906da5e184
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651295924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1651295924
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2121683317
Short name T14
Test name
Test status
Simulation time 19612186882 ps
CPU time 26.15 seconds
Started Oct 11 01:26:02 PM PDT 23
Finished Oct 11 01:26:29 PM PDT 23
Peak memory 213204 kb
Host smart-2bd147d2-d469-4329-b162-bd4e33ddff1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121683317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2121683317
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2492299120
Short name T327
Test name
Test status
Simulation time 7230247075 ps
CPU time 75.16 seconds
Started Oct 11 01:25:41 PM PDT 23
Finished Oct 11 01:26:56 PM PDT 23
Peak memory 215824 kb
Host smart-5eb19506-1a51-4065-ba86-893700924390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492299120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2492299120
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2586527135
Short name T173
Test name
Test status
Simulation time 91279399427 ps
CPU time 4005.83 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 02:32:46 PM PDT 23
Peak memory 232764 kb
Host smart-030d9936-7db0-4483-8826-113cba0f3d04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586527135 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2586527135
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4260159218
Short name T283
Test name
Test status
Simulation time 88036662 ps
CPU time 4.29 seconds
Started Oct 11 01:25:17 PM PDT 23
Finished Oct 11 01:25:21 PM PDT 23
Peak memory 211068 kb
Host smart-8df769f2-34d2-40d7-9545-78387bb232fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260159218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4260159218
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.580199041
Short name T268
Test name
Test status
Simulation time 50741056177 ps
CPU time 331.71 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:30:58 PM PDT 23
Peak memory 232992 kb
Host smart-743602ac-84ce-4720-bba9-5a9f230e9620
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580199041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.580199041
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3301192349
Short name T397
Test name
Test status
Simulation time 2477582794 ps
CPU time 24.47 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:50 PM PDT 23
Peak memory 211504 kb
Host smart-40a01a7a-9472-407b-a8e7-1c15e11a79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301192349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3301192349
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1150227272
Short name T206
Test name
Test status
Simulation time 99479791 ps
CPU time 5.97 seconds
Started Oct 11 01:25:41 PM PDT 23
Finished Oct 11 01:25:47 PM PDT 23
Peak memory 210996 kb
Host smart-8ecf6425-3399-4ee4-b719-4dfff6ca3091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150227272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1150227272
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3351315912
Short name T10
Test name
Test status
Simulation time 1363043981 ps
CPU time 64.97 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:26:30 PM PDT 23
Peak memory 235904 kb
Host smart-40752c3d-3b01-4ce7-9045-6b035e3cd01e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351315912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3351315912
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.860179123
Short name T220
Test name
Test status
Simulation time 353892299 ps
CPU time 10.49 seconds
Started Oct 11 01:25:42 PM PDT 23
Finished Oct 11 01:25:53 PM PDT 23
Peak memory 213280 kb
Host smart-4edad2ab-4995-49c9-9558-a587f67066e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860179123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.860179123
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3415298905
Short name T199
Test name
Test status
Simulation time 14720480422 ps
CPU time 65.55 seconds
Started Oct 11 01:26:49 PM PDT 23
Finished Oct 11 01:27:55 PM PDT 23
Peak memory 216520 kb
Host smart-8c344473-cec3-4905-9f16-58c65a074bb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415298905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3415298905
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.632523281
Short name T432
Test name
Test status
Simulation time 165390939258 ps
CPU time 2166.55 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 02:02:07 PM PDT 23
Peak memory 236152 kb
Host smart-cc78eabf-9bcf-4c58-af98-a361d4de5389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632523281 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.632523281
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3859377468
Short name T214
Test name
Test status
Simulation time 5726734861 ps
CPU time 12.57 seconds
Started Oct 11 01:26:07 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 211188 kb
Host smart-71da86ea-3913-40fc-b03c-754a0f0759d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859377468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3859377468
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.929954058
Short name T20
Test name
Test status
Simulation time 34950838072 ps
CPU time 226.17 seconds
Started Oct 11 01:25:44 PM PDT 23
Finished Oct 11 01:29:30 PM PDT 23
Peak memory 228104 kb
Host smart-8f66ccb8-b862-422b-b98b-597d7004f096
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929954058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.929954058
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.1435689406
Short name T248
Test name
Test status
Simulation time 2864683952 ps
CPU time 17.09 seconds
Started Oct 11 01:25:24 PM PDT 23
Finished Oct 11 01:25:42 PM PDT 23
Peak memory 211768 kb
Host smart-5979c9ad-b5e9-4d0c-a389-ac188dac2e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435689406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.1435689406
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.133277389
Short name T335
Test name
Test status
Simulation time 1863924741 ps
CPU time 16.65 seconds
Started Oct 11 01:25:41 PM PDT 23
Finished Oct 11 01:25:58 PM PDT 23
Peak memory 210964 kb
Host smart-43908d18-af53-4527-89f7-a0ce4312c7e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133277389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.133277389
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3869012211
Short name T339
Test name
Test status
Simulation time 2690413084 ps
CPU time 25.95 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:51 PM PDT 23
Peak memory 212348 kb
Host smart-86b1608f-b725-401e-b8fe-6363a67c75ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869012211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3869012211
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3946583278
Short name T300
Test name
Test status
Simulation time 1232995122 ps
CPU time 9.16 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:09 PM PDT 23
Peak memory 210828 kb
Host smart-8f708f8f-060c-4b59-9bfa-197e492acf66
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946583278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3946583278
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2946273064
Short name T434
Test name
Test status
Simulation time 72448104434 ps
CPU time 5992.32 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 03:05:16 PM PDT 23
Peak memory 248980 kb
Host smart-7b8b0879-6150-4d0a-9f3e-3f3c0a8a58e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946273064 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2946273064
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1499541677
Short name T372
Test name
Test status
Simulation time 1603382918 ps
CPU time 11.19 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:10 PM PDT 23
Peak memory 211028 kb
Host smart-d3887ac3-4e6f-4e55-81e3-69df7d2b36bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499541677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1499541677
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.209566736
Short name T197
Test name
Test status
Simulation time 49929386645 ps
CPU time 303.06 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:30:28 PM PDT 23
Peak memory 236636 kb
Host smart-c7233a13-c1a7-4d07-aaf1-a97f2be57221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209566736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.209566736
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.382301961
Short name T407
Test name
Test status
Simulation time 1334213181 ps
CPU time 18.33 seconds
Started Oct 11 01:26:02 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 211144 kb
Host smart-258325ae-cd15-4f2a-b2b5-c7146e543f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382301961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.382301961
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.956647662
Short name T161
Test name
Test status
Simulation time 288271200 ps
CPU time 5.53 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:18 PM PDT 23
Peak memory 210976 kb
Host smart-88779089-ea52-4eb2-a715-c511127e1633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956647662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.956647662
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1692170502
Short name T264
Test name
Test status
Simulation time 3880815396 ps
CPU time 20.02 seconds
Started Oct 11 01:25:42 PM PDT 23
Finished Oct 11 01:26:02 PM PDT 23
Peak memory 212884 kb
Host smart-adc8bbd8-2e65-43ac-b1c5-9f45d140293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692170502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1692170502
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1109377504
Short name T219
Test name
Test status
Simulation time 789220033 ps
CPU time 21.95 seconds
Started Oct 11 01:25:41 PM PDT 23
Finished Oct 11 01:26:03 PM PDT 23
Peak memory 215256 kb
Host smart-8d39ea1a-03c2-4d1d-b46e-7c7f4ad53ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109377504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1109377504
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.204271718
Short name T238
Test name
Test status
Simulation time 234155872471 ps
CPU time 4041.67 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 02:33:24 PM PDT 23
Peak memory 239604 kb
Host smart-e4224861-277e-43a1-813b-ea2285b74bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204271718 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.204271718
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3045216415
Short name T299
Test name
Test status
Simulation time 1696366361 ps
CPU time 6.45 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:07 PM PDT 23
Peak memory 211072 kb
Host smart-43d7b2e0-e483-444f-82af-e16c30e48d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045216415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3045216415
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3127193981
Short name T393
Test name
Test status
Simulation time 107947226389 ps
CPU time 374.28 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:32:28 PM PDT 23
Peak memory 233860 kb
Host smart-03f10267-6953-4774-89b7-5739aac14a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127193981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3127193981
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1864293060
Short name T310
Test name
Test status
Simulation time 16741637582 ps
CPU time 35.23 seconds
Started Oct 11 01:25:42 PM PDT 23
Finished Oct 11 01:26:18 PM PDT 23
Peak memory 211584 kb
Host smart-84d83bce-017f-4bee-a40b-e51bc2fac1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864293060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1864293060
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3167937722
Short name T303
Test name
Test status
Simulation time 307904223 ps
CPU time 7.65 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:26:09 PM PDT 23
Peak memory 211080 kb
Host smart-d62aa5b8-f64e-4d9d-8559-bb546bacddb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167937722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3167937722
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1121021155
Short name T267
Test name
Test status
Simulation time 11123929070 ps
CPU time 33.19 seconds
Started Oct 11 01:26:07 PM PDT 23
Finished Oct 11 01:26:41 PM PDT 23
Peak memory 213576 kb
Host smart-63301d82-387f-4800-b379-1ec66852fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121021155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1121021155
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.791043779
Short name T265
Test name
Test status
Simulation time 966486110 ps
CPU time 28.66 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:32 PM PDT 23
Peak memory 215664 kb
Host smart-f1e50e9f-2e4c-4ca1-b1d3-08adf68fd3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791043779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.791043779
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3921174725
Short name T246
Test name
Test status
Simulation time 2303202080 ps
CPU time 11.06 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:26:11 PM PDT 23
Peak memory 211100 kb
Host smart-c9bff352-5f38-42eb-84f4-8720e79fc5c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921174725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3921174725
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1570797562
Short name T8
Test name
Test status
Simulation time 4368764617 ps
CPU time 130.94 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:28:24 PM PDT 23
Peak memory 225724 kb
Host smart-6995d9f8-be83-4213-978a-7194adb8dede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570797562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1570797562
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.683923400
Short name T307
Test name
Test status
Simulation time 2219784514 ps
CPU time 20.04 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:26:30 PM PDT 23
Peak memory 211540 kb
Host smart-8b45ba3c-5365-4a44-aa6a-018dc9be6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683923400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.683923400
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1883267187
Short name T249
Test name
Test status
Simulation time 875620274 ps
CPU time 10.39 seconds
Started Oct 11 01:25:50 PM PDT 23
Finished Oct 11 01:26:01 PM PDT 23
Peak memory 210968 kb
Host smart-32a7200d-115c-4759-aa88-b9a2a6d9c083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883267187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1883267187
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1301891113
Short name T369
Test name
Test status
Simulation time 709036505 ps
CPU time 10.11 seconds
Started Oct 11 01:26:44 PM PDT 23
Finished Oct 11 01:26:55 PM PDT 23
Peak memory 211028 kb
Host smart-d2b71449-3601-4c51-b0a0-68a4ea51f7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301891113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1301891113
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4271037593
Short name T156
Test name
Test status
Simulation time 11323753077 ps
CPU time 31.04 seconds
Started Oct 11 01:25:32 PM PDT 23
Finished Oct 11 01:26:04 PM PDT 23
Peak memory 213512 kb
Host smart-7e48c26c-a411-4c87-897a-fb1466c2cd68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271037593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4271037593
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1902637814
Short name T202
Test name
Test status
Simulation time 1279328348 ps
CPU time 11.93 seconds
Started Oct 11 01:26:04 PM PDT 23
Finished Oct 11 01:26:16 PM PDT 23
Peak memory 211012 kb
Host smart-0dad9e7e-0e73-4510-b3af-80d39c74b367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902637814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1902637814
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3141071228
Short name T298
Test name
Test status
Simulation time 40975414301 ps
CPU time 108.39 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:27:11 PM PDT 23
Peak memory 212384 kb
Host smart-c59f83c8-d89b-400d-9d45-2ef36da4956b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141071228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3141071228
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1604583175
Short name T13
Test name
Test status
Simulation time 348325325 ps
CPU time 9.77 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:25:37 PM PDT 23
Peak memory 211100 kb
Host smart-2f05018c-f656-47bc-9027-e1075564ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604583175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1604583175
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.1578320871
Short name T189
Test name
Test status
Simulation time 1263170546 ps
CPU time 11.76 seconds
Started Oct 11 01:25:42 PM PDT 23
Finished Oct 11 01:25:54 PM PDT 23
Peak memory 211012 kb
Host smart-d95f2c51-dc0e-412d-824a-920b3f247749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1578320871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.1578320871
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3486737136
Short name T82
Test name
Test status
Simulation time 14425429093 ps
CPU time 36.65 seconds
Started Oct 11 01:26:15 PM PDT 23
Finished Oct 11 01:26:52 PM PDT 23
Peak memory 212960 kb
Host smart-ec8d2453-99ab-41db-8f8c-4cd2f1dfcbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486737136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3486737136
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1100946860
Short name T426
Test name
Test status
Simulation time 23751002502 ps
CPU time 61.3 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:59 PM PDT 23
Peak memory 217476 kb
Host smart-026f6178-c408-4c0e-b252-97cec45407cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100946860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1100946860
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.766130688
Short name T343
Test name
Test status
Simulation time 1722774166 ps
CPU time 7.05 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:28 PM PDT 23
Peak memory 211032 kb
Host smart-cd3d3a23-de86-4b2a-92de-b00a9d864b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766130688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.766130688
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1630132996
Short name T279
Test name
Test status
Simulation time 55177390492 ps
CPU time 214.71 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:29:38 PM PDT 23
Peak memory 228448 kb
Host smart-eee4c63f-ccb8-4394-80ef-cf3c0c88a44e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630132996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1630132996
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.656588568
Short name T169
Test name
Test status
Simulation time 1180590412 ps
CPU time 16.82 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:17 PM PDT 23
Peak memory 211096 kb
Host smart-e872969b-4c81-432b-99b5-93a7b6601d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656588568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.656588568
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.243639167
Short name T406
Test name
Test status
Simulation time 992005795 ps
CPU time 11.31 seconds
Started Oct 11 01:26:08 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 211084 kb
Host smart-7122c088-3a8b-466c-867e-ec021634bdfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243639167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.243639167
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.158529669
Short name T16
Test name
Test status
Simulation time 7632235576 ps
CPU time 21.74 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:22 PM PDT 23
Peak memory 213852 kb
Host smart-c3182c55-70d7-4cc8-a9a9-5e3397288b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158529669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.158529669
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.535188204
Short name T287
Test name
Test status
Simulation time 244931569 ps
CPU time 8.1 seconds
Started Oct 11 01:25:40 PM PDT 23
Finished Oct 11 01:25:49 PM PDT 23
Peak memory 211672 kb
Host smart-1fce3b7e-b8ad-4810-b911-3343e666d075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535188204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.535188204
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4279274943
Short name T417
Test name
Test status
Simulation time 12980351140 ps
CPU time 15.04 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:13 PM PDT 23
Peak memory 211140 kb
Host smart-b2e4f014-e9d8-4dfd-9b1e-e498758113fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279274943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4279274943
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1392327558
Short name T388
Test name
Test status
Simulation time 31253048265 ps
CPU time 275.37 seconds
Started Oct 11 01:25:45 PM PDT 23
Finished Oct 11 01:30:21 PM PDT 23
Peak memory 236708 kb
Host smart-6fae7128-7f14-45a4-8136-15eacf5f49e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392327558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1392327558
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3943839665
Short name T379
Test name
Test status
Simulation time 608549210 ps
CPU time 11.42 seconds
Started Oct 11 01:25:40 PM PDT 23
Finished Oct 11 01:25:51 PM PDT 23
Peak memory 211080 kb
Host smart-9c3a8ba9-69c0-42f0-a301-b9589cb42ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943839665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3943839665
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2894778875
Short name T163
Test name
Test status
Simulation time 103732239 ps
CPU time 5.78 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:28 PM PDT 23
Peak memory 210996 kb
Host smart-d53b5c5f-a831-45e9-a6b1-30abde9113b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894778875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2894778875
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1442880875
Short name T157
Test name
Test status
Simulation time 3716797607 ps
CPU time 30.94 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:44 PM PDT 23
Peak memory 212760 kb
Host smart-e977ca17-31dd-43e0-ad6e-386f93697f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442880875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1442880875
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3002269394
Short name T413
Test name
Test status
Simulation time 3184277239 ps
CPU time 35.91 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:57 PM PDT 23
Peak memory 212404 kb
Host smart-bb51afb6-66cf-43e5-aff4-185c1157b7f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002269394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3002269394
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3324570949
Short name T23
Test name
Test status
Simulation time 123574270698 ps
CPU time 1114.73 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:44:36 PM PDT 23
Peak memory 227784 kb
Host smart-30fdf24c-1503-44e7-b25e-fe69bfec471a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324570949 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3324570949
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3565155690
Short name T182
Test name
Test status
Simulation time 810351531 ps
CPU time 9.4 seconds
Started Oct 11 01:26:04 PM PDT 23
Finished Oct 11 01:26:14 PM PDT 23
Peak memory 211012 kb
Host smart-9b599efb-43ef-448d-9c3e-d794860ccb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565155690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3565155690
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.520926005
Short name T48
Test name
Test status
Simulation time 71365915832 ps
CPU time 222.29 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:29:08 PM PDT 23
Peak memory 232580 kb
Host smart-2cc8b987-2fd7-44d5-9c8f-fb7c1bf08c30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520926005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.520926005
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1789574957
Short name T333
Test name
Test status
Simulation time 4239569424 ps
CPU time 30.94 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:26:33 PM PDT 23
Peak memory 211300 kb
Host smart-57a1eceb-fd5e-4051-8e4b-b583b8a6fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789574957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1789574957
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1937443089
Short name T357
Test name
Test status
Simulation time 354154577 ps
CPU time 10.57 seconds
Started Oct 11 01:25:33 PM PDT 23
Finished Oct 11 01:25:44 PM PDT 23
Peak memory 212852 kb
Host smart-db5e1d59-6092-4930-997e-d71692bcbffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937443089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1937443089
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1806295294
Short name T309
Test name
Test status
Simulation time 28582784047 ps
CPU time 17.81 seconds
Started Oct 11 01:26:15 PM PDT 23
Finished Oct 11 01:26:33 PM PDT 23
Peak memory 211800 kb
Host smart-86b678e4-65da-4c85-8422-57a75d8807fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806295294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1806295294
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2321373082
Short name T270
Test name
Test status
Simulation time 576449010 ps
CPU time 6.31 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:27 PM PDT 23
Peak memory 211080 kb
Host smart-95955c32-52b7-4b62-babf-1ad320793aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321373082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2321373082
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.584240135
Short name T207
Test name
Test status
Simulation time 29347068817 ps
CPU time 192.65 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:29:12 PM PDT 23
Peak memory 228520 kb
Host smart-c018168c-880e-4aef-ad92-8a8cc79acac2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584240135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.584240135
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2303468993
Short name T152
Test name
Test status
Simulation time 21428410864 ps
CPU time 20.28 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:24 PM PDT 23
Peak memory 211516 kb
Host smart-ac8b7fd2-f20e-4efd-94ca-28cd5aa5d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303468993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2303468993
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.655977858
Short name T271
Test name
Test status
Simulation time 886377742 ps
CPU time 8.39 seconds
Started Oct 11 01:25:39 PM PDT 23
Finished Oct 11 01:25:47 PM PDT 23
Peak memory 210976 kb
Host smart-660d7995-1469-465a-a3da-47acfb72ed21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=655977858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.655977858
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1967945421
Short name T350
Test name
Test status
Simulation time 12180354288 ps
CPU time 31.48 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:35 PM PDT 23
Peak memory 213072 kb
Host smart-13b8b6ba-e8f8-4ab4-b2d4-d8f71dac995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967945421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1967945421
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2097038091
Short name T172
Test name
Test status
Simulation time 38977391354 ps
CPU time 112.15 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:27:15 PM PDT 23
Peak memory 219484 kb
Host smart-23aa1fad-3220-4956-a4fe-45cb0e627678
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097038091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2097038091
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1579815031
Short name T312
Test name
Test status
Simulation time 14055214817 ps
CPU time 1252.47 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:46:54 PM PDT 23
Peak memory 227564 kb
Host smart-9afdd7d4-a39a-42bc-affa-305c63d10379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579815031 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1579815031
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3683392192
Short name T359
Test name
Test status
Simulation time 347381512 ps
CPU time 4.35 seconds
Started Oct 11 01:27:02 PM PDT 23
Finished Oct 11 01:27:07 PM PDT 23
Peak memory 211072 kb
Host smart-7f583168-95d9-4365-a6e6-a2be7fcac985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683392192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3683392192
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1548353244
Short name T45
Test name
Test status
Simulation time 96952545356 ps
CPU time 449.31 seconds
Started Oct 11 01:25:45 PM PDT 23
Finished Oct 11 01:33:15 PM PDT 23
Peak memory 212388 kb
Host smart-f6da40fe-0193-405b-8c1c-488d4feb12c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548353244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.1548353244
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3558126118
Short name T356
Test name
Test status
Simulation time 15876826335 ps
CPU time 24.21 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 01:27:21 PM PDT 23
Peak memory 211648 kb
Host smart-51fe874d-2eea-4c57-be9b-d42b2054ef51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558126118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3558126118
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.587141362
Short name T410
Test name
Test status
Simulation time 1381177270 ps
CPU time 13.83 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 01:26:23 PM PDT 23
Peak memory 211024 kb
Host smart-e591a350-a61c-4d46-ae36-b6e8643eb016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587141362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.587141362
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2364668450
Short name T338
Test name
Test status
Simulation time 1665570184 ps
CPU time 18.45 seconds
Started Oct 11 01:25:32 PM PDT 23
Finished Oct 11 01:25:51 PM PDT 23
Peak memory 212352 kb
Host smart-ee33aa3f-e82a-4119-9ffb-06b647848cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364668450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2364668450
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1525263535
Short name T183
Test name
Test status
Simulation time 8828339505 ps
CPU time 32.37 seconds
Started Oct 11 01:25:40 PM PDT 23
Finished Oct 11 01:26:12 PM PDT 23
Peak memory 219384 kb
Host smart-1c85a840-22b9-4166-9438-9631e6177a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525263535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1525263535
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3107121700
Short name T107
Test name
Test status
Simulation time 37869769816 ps
CPU time 1512.78 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:51:26 PM PDT 23
Peak memory 236956 kb
Host smart-524c2a87-08e6-48c5-9f59-abc4b8479b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107121700 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3107121700
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1606148584
Short name T374
Test name
Test status
Simulation time 164584038 ps
CPU time 4.25 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:25:28 PM PDT 23
Peak memory 211244 kb
Host smart-bd35f693-6ec4-45f5-b8d6-ca334e30ea17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606148584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1606148584
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3327185243
Short name T210
Test name
Test status
Simulation time 2564478074 ps
CPU time 100.05 seconds
Started Oct 11 01:25:01 PM PDT 23
Finished Oct 11 01:26:41 PM PDT 23
Peak memory 228120 kb
Host smart-3d4c05b4-dc4c-49f5-97d7-a525a2ac434c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327185243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3327185243
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1116637674
Short name T412
Test name
Test status
Simulation time 2210350158 ps
CPU time 22.29 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:25:48 PM PDT 23
Peak memory 211384 kb
Host smart-d68006da-bda0-4d8b-bfb1-fa14e5f82713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116637674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1116637674
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1917854447
Short name T423
Test name
Test status
Simulation time 96552026 ps
CPU time 5.6 seconds
Started Oct 11 01:25:15 PM PDT 23
Finished Oct 11 01:25:21 PM PDT 23
Peak memory 211016 kb
Host smart-04a11d28-438c-486d-a3d2-cf5625da3491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1917854447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1917854447
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.233672848
Short name T41
Test name
Test status
Simulation time 240608764 ps
CPU time 110.56 seconds
Started Oct 11 01:25:32 PM PDT 23
Finished Oct 11 01:27:23 PM PDT 23
Peak memory 236784 kb
Host smart-b5c376f9-bd5a-4209-ba53-b6762ddb3b18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233672848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.233672848
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2031971215
Short name T164
Test name
Test status
Simulation time 180006159 ps
CPU time 9.82 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:25:29 PM PDT 23
Peak memory 212432 kb
Host smart-e45e890b-8aa0-4b78-8cd7-02072608f801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031971215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2031971215
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4049647184
Short name T43
Test name
Test status
Simulation time 30791927862 ps
CPU time 90.43 seconds
Started Oct 11 01:25:03 PM PDT 23
Finished Oct 11 01:26:33 PM PDT 23
Peak memory 216860 kb
Host smart-4c19907c-47ca-4775-9d89-5aee53609963
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049647184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4049647184
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1796911416
Short name T381
Test name
Test status
Simulation time 88971185 ps
CPU time 4.44 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:03 PM PDT 23
Peak memory 210972 kb
Host smart-206df6e9-2095-4453-a931-42948d5a3f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796911416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1796911416
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2318167372
Short name T46
Test name
Test status
Simulation time 48442770076 ps
CPU time 241.32 seconds
Started Oct 11 01:27:03 PM PDT 23
Finished Oct 11 01:31:05 PM PDT 23
Peak memory 237676 kb
Host smart-36b56b19-98df-485e-8bdc-eb3a8c7b23ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318167372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2318167372
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.860274637
Short name T430
Test name
Test status
Simulation time 22588942526 ps
CPU time 34.99 seconds
Started Oct 11 01:26:59 PM PDT 23
Finished Oct 11 01:27:34 PM PDT 23
Peak memory 211588 kb
Host smart-9713c7eb-ed54-4b19-9e51-93b936f9cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860274637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.860274637
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3954399784
Short name T361
Test name
Test status
Simulation time 190924067 ps
CPU time 5.72 seconds
Started Oct 11 01:27:00 PM PDT 23
Finished Oct 11 01:27:06 PM PDT 23
Peak memory 211044 kb
Host smart-e8f3b2fc-b40b-4ae0-a6a0-4fbf12a0973c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3954399784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3954399784
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2965715770
Short name T15
Test name
Test status
Simulation time 3153846784 ps
CPU time 27.09 seconds
Started Oct 11 01:26:58 PM PDT 23
Finished Oct 11 01:27:26 PM PDT 23
Peak memory 212484 kb
Host smart-dfd72b82-a3e5-4e52-b1fb-df2c6de89cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965715770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2965715770
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3073024158
Short name T245
Test name
Test status
Simulation time 10428864319 ps
CPU time 55.68 seconds
Started Oct 11 01:26:59 PM PDT 23
Finished Oct 11 01:27:56 PM PDT 23
Peak memory 216596 kb
Host smart-e15de967-06e9-4329-8594-6cae95ab9abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073024158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3073024158
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.200265088
Short name T241
Test name
Test status
Simulation time 74918661133 ps
CPU time 2013.05 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:59:35 PM PDT 23
Peak memory 235812 kb
Host smart-38cd4825-85a5-48fd-b934-994172010f53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200265088 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.200265088
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1698657882
Short name T149
Test name
Test status
Simulation time 920269794 ps
CPU time 6.09 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:19 PM PDT 23
Peak memory 211064 kb
Host smart-7688d3f6-24e9-49e7-8b60-7a9d8c687063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698657882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1698657882
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.561402176
Short name T345
Test name
Test status
Simulation time 14448413375 ps
CPU time 210.58 seconds
Started Oct 11 01:26:04 PM PDT 23
Finished Oct 11 01:29:35 PM PDT 23
Peak memory 237140 kb
Host smart-860b6f7d-caad-4047-92d0-656f1aae4818
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561402176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.561402176
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.373355047
Short name T320
Test name
Test status
Simulation time 379110015 ps
CPU time 9.55 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:32 PM PDT 23
Peak memory 211328 kb
Host smart-98e40c73-362d-4d3d-9fe2-a1f889e63aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373355047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.373355047
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2884343850
Short name T305
Test name
Test status
Simulation time 2185254665 ps
CPU time 17.06 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 01:26:26 PM PDT 23
Peak memory 211200 kb
Host smart-8efa3ea2-ed16-475d-a392-8f3dde7b9bbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2884343850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2884343850
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.2609089035
Short name T171
Test name
Test status
Simulation time 613266172 ps
CPU time 10.45 seconds
Started Oct 11 01:25:59 PM PDT 23
Finished Oct 11 01:26:10 PM PDT 23
Peak memory 212976 kb
Host smart-e39653cc-a306-4c8f-ae95-8897a3f747d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609089035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.2609089035
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2365774548
Short name T273
Test name
Test status
Simulation time 6646640285 ps
CPU time 82.31 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:26:46 PM PDT 23
Peak memory 217200 kb
Host smart-7c71ea90-bf0b-48fc-8415-32c161bb6f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365774548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2365774548
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.4041431566
Short name T386
Test name
Test status
Simulation time 43096448623 ps
CPU time 1766.97 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 01:55:37 PM PDT 23
Peak memory 228168 kb
Host smart-c5655239-86e1-463b-a3cc-17139e1c8eaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041431566 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.4041431566
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2895137475
Short name T314
Test name
Test status
Simulation time 1036333151 ps
CPU time 4.43 seconds
Started Oct 11 01:26:18 PM PDT 23
Finished Oct 11 01:26:22 PM PDT 23
Peak memory 210972 kb
Host smart-e9cfdd05-70e6-4e12-9b3c-9af8f3276a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895137475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2895137475
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2899361066
Short name T377
Test name
Test status
Simulation time 139234161725 ps
CPU time 378.91 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:31:38 PM PDT 23
Peak memory 224644 kb
Host smart-c2ccebdb-e324-429a-a3ee-514f1888038c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899361066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2899361066
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2531381721
Short name T317
Test name
Test status
Simulation time 3176055547 ps
CPU time 28.23 seconds
Started Oct 11 01:26:58 PM PDT 23
Finished Oct 11 01:27:27 PM PDT 23
Peak memory 211252 kb
Host smart-9e66cc64-cc48-43fe-995c-08403e3be685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531381721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2531381721
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.4023759352
Short name T427
Test name
Test status
Simulation time 95536515 ps
CPU time 5.58 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:09 PM PDT 23
Peak memory 211064 kb
Host smart-02a4ab1a-6bc9-4ffd-a369-b6bd7c856a0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023759352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.4023759352
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.4242805614
Short name T91
Test name
Test status
Simulation time 4457900717 ps
CPU time 25.76 seconds
Started Oct 11 01:26:08 PM PDT 23
Finished Oct 11 01:26:34 PM PDT 23
Peak memory 212768 kb
Host smart-ce67f876-4eba-4264-a001-23c0635cfef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242805614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.4242805614
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1002587722
Short name T184
Test name
Test status
Simulation time 757526848 ps
CPU time 11.76 seconds
Started Oct 11 01:26:08 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 210932 kb
Host smart-81b5679e-cf2d-4157-b1f0-76fd676f4b62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002587722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1002587722
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3349413455
Short name T378
Test name
Test status
Simulation time 1627399058 ps
CPU time 13.78 seconds
Started Oct 11 01:26:49 PM PDT 23
Finished Oct 11 01:27:03 PM PDT 23
Peak memory 211024 kb
Host smart-3a2543f8-e12f-4343-9436-3aa0237d0793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349413455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3349413455
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3573890992
Short name T11
Test name
Test status
Simulation time 175089562 ps
CPU time 9.73 seconds
Started Oct 11 01:26:50 PM PDT 23
Finished Oct 11 01:27:00 PM PDT 23
Peak memory 211160 kb
Host smart-3910068c-fc23-4b8c-85cf-da99e13f7ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573890992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3573890992
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3663949741
Short name T191
Test name
Test status
Simulation time 368431581 ps
CPU time 5.92 seconds
Started Oct 11 01:25:42 PM PDT 23
Finished Oct 11 01:25:49 PM PDT 23
Peak memory 210960 kb
Host smart-993a7c1f-881e-4542-8398-8fc884df3cdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663949741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3663949741
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3955693470
Short name T349
Test name
Test status
Simulation time 650974956 ps
CPU time 9.96 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:23 PM PDT 23
Peak memory 213976 kb
Host smart-f6868c9e-31cb-4704-8ba7-92d3966f2cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955693470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3955693470
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.367585067
Short name T337
Test name
Test status
Simulation time 951984628 ps
CPU time 26.01 seconds
Started Oct 11 01:26:46 PM PDT 23
Finished Oct 11 01:27:13 PM PDT 23
Peak memory 215048 kb
Host smart-c138191b-802a-40ca-9bf7-74b7ad5867b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367585067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.367585067
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.465321023
Short name T365
Test name
Test status
Simulation time 59460115785 ps
CPU time 5402.02 seconds
Started Oct 11 01:25:40 PM PDT 23
Finished Oct 11 02:55:43 PM PDT 23
Peak memory 236240 kb
Host smart-c1a521d4-4fad-404d-a3d3-c61d3f667366
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465321023 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.465321023
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.654212846
Short name T5
Test name
Test status
Simulation time 5580972294 ps
CPU time 14.73 seconds
Started Oct 11 01:26:50 PM PDT 23
Finished Oct 11 01:27:05 PM PDT 23
Peak memory 211128 kb
Host smart-43913430-db9f-4a13-8599-7f37bb7e9821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654212846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.654212846
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2778655948
Short name T398
Test name
Test status
Simulation time 138944075111 ps
CPU time 329.24 seconds
Started Oct 11 01:26:48 PM PDT 23
Finished Oct 11 01:32:18 PM PDT 23
Peak memory 237464 kb
Host smart-9164b181-56e6-4abb-accc-ba5b3dbded69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778655948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2778655948
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2755177787
Short name T255
Test name
Test status
Simulation time 9585128550 ps
CPU time 20.77 seconds
Started Oct 11 01:26:49 PM PDT 23
Finished Oct 11 01:27:10 PM PDT 23
Peak memory 211472 kb
Host smart-30c47c38-fc76-400e-826e-cd7ed5c0b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755177787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2755177787
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.2464976498
Short name T286
Test name
Test status
Simulation time 442194811 ps
CPU time 8.05 seconds
Started Oct 11 01:26:07 PM PDT 23
Finished Oct 11 01:26:16 PM PDT 23
Peak memory 211024 kb
Host smart-657c2da5-bb41-498d-9af4-411330bd4519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464976498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.2464976498
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1282171984
Short name T252
Test name
Test status
Simulation time 4002013265 ps
CPU time 16.8 seconds
Started Oct 11 01:26:52 PM PDT 23
Finished Oct 11 01:27:09 PM PDT 23
Peak memory 212488 kb
Host smart-61b3d540-885a-4edc-9970-ae96a380321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282171984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1282171984
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1375744221
Short name T416
Test name
Test status
Simulation time 1536216149 ps
CPU time 16.65 seconds
Started Oct 11 01:26:51 PM PDT 23
Finished Oct 11 01:27:09 PM PDT 23
Peak memory 212948 kb
Host smart-1043cad7-b6bf-4acb-81f2-5949a84f0be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375744221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1375744221
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.769478489
Short name T151
Test name
Test status
Simulation time 3251095791 ps
CPU time 14.59 seconds
Started Oct 11 01:26:54 PM PDT 23
Finished Oct 11 01:27:09 PM PDT 23
Peak memory 211124 kb
Host smart-8d308bf5-df9e-467a-b0bd-626a9ddf7e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769478489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.769478489
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.542000247
Short name T237
Test name
Test status
Simulation time 113718107571 ps
CPU time 233.13 seconds
Started Oct 11 01:25:40 PM PDT 23
Finished Oct 11 01:29:34 PM PDT 23
Peak memory 233744 kb
Host smart-d2a4db7e-9651-4e7d-82f1-ee1becfdb1d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542000247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.542000247
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4025472867
Short name T332
Test name
Test status
Simulation time 171743989 ps
CPU time 9.77 seconds
Started Oct 11 01:26:48 PM PDT 23
Finished Oct 11 01:26:59 PM PDT 23
Peak memory 211236 kb
Host smart-fda0afdf-15e4-4eb5-a5e6-a041ba6290ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025472867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4025472867
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3700444818
Short name T296
Test name
Test status
Simulation time 186160926 ps
CPU time 5.41 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:18 PM PDT 23
Peak memory 211056 kb
Host smart-07007077-a1b7-4266-bef9-68de6589c749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700444818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3700444818
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1797485270
Short name T280
Test name
Test status
Simulation time 3140662240 ps
CPU time 27.57 seconds
Started Oct 11 01:25:50 PM PDT 23
Finished Oct 11 01:26:18 PM PDT 23
Peak memory 212484 kb
Host smart-3499b142-6981-463e-a939-2860fb3e351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797485270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1797485270
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.4127526835
Short name T215
Test name
Test status
Simulation time 8022953799 ps
CPU time 84.23 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:27:34 PM PDT 23
Peak memory 217312 kb
Host smart-b6fdccbe-9a15-494d-98da-269c0fde50dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127526835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.4127526835
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2367300312
Short name T282
Test name
Test status
Simulation time 171433363787 ps
CPU time 4208.96 seconds
Started Oct 11 01:26:50 PM PDT 23
Finished Oct 11 02:37:00 PM PDT 23
Peak memory 235824 kb
Host smart-76aa9bad-8af8-4149-bfce-ce17de4e28d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367300312 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2367300312
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1731673147
Short name T347
Test name
Test status
Simulation time 519511835 ps
CPU time 4.33 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:26:58 PM PDT 23
Peak memory 210984 kb
Host smart-40d055b5-2ea3-4f4c-8d5e-bde8ebbd4b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731673147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1731673147
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1461695271
Short name T226
Test name
Test status
Simulation time 37880325371 ps
CPU time 322.98 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:31:33 PM PDT 23
Peak memory 233856 kb
Host smart-537e99ff-4d3c-4723-93b0-e1a013ceb67b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461695271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.1461695271
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4147223862
Short name T420
Test name
Test status
Simulation time 1107814923 ps
CPU time 9.9 seconds
Started Oct 11 01:26:18 PM PDT 23
Finished Oct 11 01:26:30 PM PDT 23
Peak memory 211056 kb
Host smart-3a80daca-f450-4191-b28f-1f6ef62b8b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147223862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4147223862
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2523227707
Short name T274
Test name
Test status
Simulation time 2196503185 ps
CPU time 17.36 seconds
Started Oct 11 01:26:54 PM PDT 23
Finished Oct 11 01:27:12 PM PDT 23
Peak memory 211136 kb
Host smart-f4d763a5-9c41-4969-9059-3ec579a81e43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2523227707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2523227707
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2484688812
Short name T329
Test name
Test status
Simulation time 4509960753 ps
CPU time 17.06 seconds
Started Oct 11 01:26:50 PM PDT 23
Finished Oct 11 01:27:07 PM PDT 23
Peak memory 213112 kb
Host smart-c75d3c51-765d-474b-b1bc-3104792f56e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484688812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2484688812
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.553450838
Short name T92
Test name
Test status
Simulation time 8932438253 ps
CPU time 81.52 seconds
Started Oct 11 01:26:15 PM PDT 23
Finished Oct 11 01:27:37 PM PDT 23
Peak memory 214992 kb
Host smart-030c0c23-eba9-440c-b784-7284f03af1c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553450838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.553450838
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.76409236
Short name T325
Test name
Test status
Simulation time 77073707033 ps
CPU time 5671.3 seconds
Started Oct 11 01:25:43 PM PDT 23
Finished Oct 11 03:00:15 PM PDT 23
Peak memory 235820 kb
Host smart-5c90fd46-846a-4f10-8e84-4b732b7596d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76409236 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.76409236
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3182849445
Short name T209
Test name
Test status
Simulation time 172002853 ps
CPU time 4.44 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:18 PM PDT 23
Peak memory 211076 kb
Host smart-8d6d0aa0-7a7f-4971-b774-d4acffdfeb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182849445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3182849445
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3399600117
Short name T47
Test name
Test status
Simulation time 62838327168 ps
CPU time 377.88 seconds
Started Oct 11 01:26:58 PM PDT 23
Finished Oct 11 01:33:17 PM PDT 23
Peak memory 233700 kb
Host smart-4f85d6d7-ab21-4746-8299-32df827e6520
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399600117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3399600117
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4174769315
Short name T376
Test name
Test status
Simulation time 1079793519 ps
CPU time 16.29 seconds
Started Oct 11 01:26:51 PM PDT 23
Finished Oct 11 01:27:08 PM PDT 23
Peak memory 211032 kb
Host smart-29115731-26ba-4738-aadf-f6b37301b8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174769315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4174769315
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.587959587
Short name T159
Test name
Test status
Simulation time 11241147054 ps
CPU time 17.72 seconds
Started Oct 11 01:25:49 PM PDT 23
Finished Oct 11 01:26:07 PM PDT 23
Peak memory 211164 kb
Host smart-1be4326c-fb8e-4685-a27d-9f5b5f4dc2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587959587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.587959587
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.3857289261
Short name T81
Test name
Test status
Simulation time 41966880300 ps
CPU time 42.46 seconds
Started Oct 11 01:26:51 PM PDT 23
Finished Oct 11 01:27:34 PM PDT 23
Peak memory 213104 kb
Host smart-9eb2bd57-eed9-4381-957c-ad81a4e786f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857289261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.3857289261
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.983472840
Short name T4
Test name
Test status
Simulation time 7617473445 ps
CPU time 60.12 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:27:12 PM PDT 23
Peak memory 216272 kb
Host smart-d05f94fe-eb4c-4d68-9c41-af44414523e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983472840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.983472840
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.685395471
Short name T26
Test name
Test status
Simulation time 15432995883 ps
CPU time 487.72 seconds
Started Oct 11 01:26:08 PM PDT 23
Finished Oct 11 01:34:17 PM PDT 23
Peak memory 224504 kb
Host smart-d1ea5431-8ce3-4409-9069-7733a42b53a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685395471 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.685395471
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4134637685
Short name T281
Test name
Test status
Simulation time 6597612691 ps
CPU time 14.48 seconds
Started Oct 11 01:26:51 PM PDT 23
Finished Oct 11 01:27:06 PM PDT 23
Peak memory 211172 kb
Host smart-2120376a-d8f5-4b85-8e1c-b23fe43e3976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134637685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4134637685
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1408455128
Short name T269
Test name
Test status
Simulation time 14053390162 ps
CPU time 165.74 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:28:59 PM PDT 23
Peak memory 233648 kb
Host smart-807c9840-7477-40d0-80a6-67de57a6d66f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408455128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1408455128
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.917417427
Short name T166
Test name
Test status
Simulation time 4358094516 ps
CPU time 33.01 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:45 PM PDT 23
Peak memory 211972 kb
Host smart-d2e0fd14-3b82-4858-a10b-09e117011ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917417427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.917417427
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.514940488
Short name T185
Test name
Test status
Simulation time 14690709281 ps
CPU time 13.29 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:26 PM PDT 23
Peak memory 211184 kb
Host smart-020b192f-aad8-47b4-b112-354e6d43c267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514940488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.514940488
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1002234091
Short name T228
Test name
Test status
Simulation time 3296855929 ps
CPU time 13.27 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:27:06 PM PDT 23
Peak memory 213020 kb
Host smart-33477a81-607c-4dd2-8cf0-b81c2891d8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002234091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1002234091
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3977188380
Short name T380
Test name
Test status
Simulation time 25660191783 ps
CPU time 58.96 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:27:10 PM PDT 23
Peak memory 216412 kb
Host smart-c88561b8-7eeb-4ccd-8074-9819ad49b97d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977188380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3977188380
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3013244915
Short name T363
Test name
Test status
Simulation time 1844500610 ps
CPU time 14.81 seconds
Started Oct 11 01:26:15 PM PDT 23
Finished Oct 11 01:26:31 PM PDT 23
Peak memory 211024 kb
Host smart-6e5dcdc7-1c36-4c87-87db-9fed867e1d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013244915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3013244915
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3800969830
Short name T362
Test name
Test status
Simulation time 51002613043 ps
CPU time 262.33 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:31:16 PM PDT 23
Peak memory 212388 kb
Host smart-c0709672-1e8c-4dc9-8063-0a6125947a9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800969830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3800969830
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3149519233
Short name T200
Test name
Test status
Simulation time 2757212944 ps
CPU time 26.17 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 01:26:36 PM PDT 23
Peak memory 211204 kb
Host smart-b618e96f-2865-40c6-af59-eeccc1ac9e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149519233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3149519233
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3006620188
Short name T277
Test name
Test status
Simulation time 10648844320 ps
CPU time 17.24 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:30 PM PDT 23
Peak memory 211248 kb
Host smart-d027ac4e-3787-4726-9e35-22943809ef28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3006620188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3006620188
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.2888301594
Short name T234
Test name
Test status
Simulation time 5905235909 ps
CPU time 31.46 seconds
Started Oct 11 01:26:16 PM PDT 23
Finished Oct 11 01:26:48 PM PDT 23
Peak memory 213128 kb
Host smart-e3b10191-65fb-4895-a398-a14d214521dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888301594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.2888301594
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.418410715
Short name T167
Test name
Test status
Simulation time 43028923866 ps
CPU time 92.8 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:27:44 PM PDT 23
Peak memory 217400 kb
Host smart-a20997e5-0698-45d2-92b7-dcaaaf29e1c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418410715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.418410715
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.4208316330
Short name T235
Test name
Test status
Simulation time 7395330901 ps
CPU time 135.42 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:28:30 PM PDT 23
Peak memory 221040 kb
Host smart-7c60a99a-a9fe-48b3-aaea-92e17cdcb5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208316330 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.4208316330
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.858748682
Short name T353
Test name
Test status
Simulation time 2280234281 ps
CPU time 11.56 seconds
Started Oct 11 01:24:58 PM PDT 23
Finished Oct 11 01:25:10 PM PDT 23
Peak memory 211140 kb
Host smart-a333c201-7804-4ec7-96f9-eb017d53a558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858748682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.858748682
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.460277003
Short name T213
Test name
Test status
Simulation time 124327635025 ps
CPU time 379.8 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:31:46 PM PDT 23
Peak memory 224948 kb
Host smart-eb8472c3-4c84-4b91-8997-73243dddc884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460277003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.460277003
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2394905191
Short name T418
Test name
Test status
Simulation time 3823458402 ps
CPU time 30.62 seconds
Started Oct 11 01:25:20 PM PDT 23
Finished Oct 11 01:25:51 PM PDT 23
Peak memory 212840 kb
Host smart-f1162802-81ad-45e6-8ab9-d6b1270f94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394905191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2394905191
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2512914562
Short name T294
Test name
Test status
Simulation time 1924819746 ps
CPU time 8.53 seconds
Started Oct 11 01:26:00 PM PDT 23
Finished Oct 11 01:26:09 PM PDT 23
Peak memory 211160 kb
Host smart-22d569c6-df84-49ef-b583-6348632ef5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512914562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2512914562
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.401911416
Short name T37
Test name
Test status
Simulation time 1216633329 ps
CPU time 59.74 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:26:26 PM PDT 23
Peak memory 236000 kb
Host smart-41922a34-c95a-4d52-b578-edbe429fa304
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401911416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.401911416
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3060234353
Short name T422
Test name
Test status
Simulation time 15112473696 ps
CPU time 32.68 seconds
Started Oct 11 01:25:33 PM PDT 23
Finished Oct 11 01:26:06 PM PDT 23
Peak memory 213264 kb
Host smart-b0255331-01ee-4805-bce0-b790e94d9054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060234353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3060234353
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.563545709
Short name T266
Test name
Test status
Simulation time 1249129480 ps
CPU time 16.62 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 01:25:39 PM PDT 23
Peak memory 214532 kb
Host smart-cda4625a-9287-4209-b23b-8e8df46bb48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563545709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.563545709
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1563850994
Short name T2
Test name
Test status
Simulation time 3216041765 ps
CPU time 13.52 seconds
Started Oct 11 01:27:02 PM PDT 23
Finished Oct 11 01:27:17 PM PDT 23
Peak memory 211192 kb
Host smart-25740148-7bf7-435f-900e-359c75da2b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563850994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1563850994
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1331263550
Short name T358
Test name
Test status
Simulation time 42968201766 ps
CPU time 142.27 seconds
Started Oct 11 01:27:01 PM PDT 23
Finished Oct 11 01:29:24 PM PDT 23
Peak memory 228208 kb
Host smart-e44c6bbd-6eaf-44c0-a2d0-58a22a0a86ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331263550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1331263550
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2421278288
Short name T174
Test name
Test status
Simulation time 9993060129 ps
CPU time 23.35 seconds
Started Oct 11 01:26:58 PM PDT 23
Finished Oct 11 01:27:21 PM PDT 23
Peak memory 211484 kb
Host smart-488a605d-8079-4ad9-9721-85d02288f4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421278288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2421278288
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2041933736
Short name T328
Test name
Test status
Simulation time 394234468 ps
CPU time 5.79 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:19 PM PDT 23
Peak memory 211064 kb
Host smart-3a389ce9-fea2-4df8-a639-4b49285372e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041933736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2041933736
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1189126034
Short name T383
Test name
Test status
Simulation time 11986725582 ps
CPU time 29.73 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:26:40 PM PDT 23
Peak memory 213304 kb
Host smart-f31595da-1099-4ac5-bae6-131271733c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189126034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1189126034
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2919474029
Short name T7
Test name
Test status
Simulation time 27597495401 ps
CPU time 71.55 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:27:25 PM PDT 23
Peak memory 217400 kb
Host smart-74f39ffd-0879-4b6c-abe7-409e6ac4b1f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919474029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2919474029
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1715462232
Short name T366
Test name
Test status
Simulation time 137774918155 ps
CPU time 7197.74 seconds
Started Oct 11 01:27:09 PM PDT 23
Finished Oct 11 03:27:09 PM PDT 23
Peak memory 240428 kb
Host smart-e8a9f525-9b1b-4178-a9ba-deae3baa8f6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715462232 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1715462232
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3952644302
Short name T240
Test name
Test status
Simulation time 6300553313 ps
CPU time 13.88 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:28 PM PDT 23
Peak memory 211188 kb
Host smart-38652e09-f486-469a-9a1c-2521c40f21f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952644302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3952644302
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1748404754
Short name T352
Test name
Test status
Simulation time 4114183761 ps
CPU time 132.19 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:29:06 PM PDT 23
Peak memory 237704 kb
Host smart-661f817c-ab4c-4985-8d72-87672f8988c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748404754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1748404754
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.3966947103
Short name T178
Test name
Test status
Simulation time 13361523217 ps
CPU time 29.8 seconds
Started Oct 11 01:26:18 PM PDT 23
Finished Oct 11 01:26:50 PM PDT 23
Peak memory 211444 kb
Host smart-6d439504-137b-443c-8384-024ed77c01fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966947103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.3966947103
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2567864951
Short name T239
Test name
Test status
Simulation time 2771290914 ps
CPU time 13.67 seconds
Started Oct 11 01:26:51 PM PDT 23
Finished Oct 11 01:27:05 PM PDT 23
Peak memory 211148 kb
Host smart-a2046e54-24b8-4f01-87e9-f27c7b043098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567864951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2567864951
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4088513623
Short name T217
Test name
Test status
Simulation time 19547493503 ps
CPU time 35.42 seconds
Started Oct 11 01:27:01 PM PDT 23
Finished Oct 11 01:27:37 PM PDT 23
Peak memory 213744 kb
Host smart-4cd25940-6885-4f5e-8be5-cdf1db2264e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088513623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4088513623
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.70312242
Short name T190
Test name
Test status
Simulation time 21243975192 ps
CPU time 54.15 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 01:27:51 PM PDT 23
Peak memory 219380 kb
Host smart-7c6db7c8-8dd5-49e2-974f-d3acf4ee762c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70312242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.70312242
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4070877538
Short name T158
Test name
Test status
Simulation time 1692341612 ps
CPU time 14 seconds
Started Oct 11 01:26:55 PM PDT 23
Finished Oct 11 01:27:09 PM PDT 23
Peak memory 211064 kb
Host smart-f2430fb9-ce0a-4fa1-a5aa-8d0e15246ad0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070877538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4070877538
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1883756299
Short name T340
Test name
Test status
Simulation time 189004508612 ps
CPU time 339.69 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:31:50 PM PDT 23
Peak memory 236492 kb
Host smart-43e20652-0501-40c6-ac96-15c365655815
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883756299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1883756299
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2006903355
Short name T146
Test name
Test status
Simulation time 3222461458 ps
CPU time 27.67 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:27:21 PM PDT 23
Peak memory 211220 kb
Host smart-41bf699b-37bc-48bb-998e-ba19de121d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006903355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2006903355
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4142598467
Short name T261
Test name
Test status
Simulation time 101867929 ps
CPU time 5.97 seconds
Started Oct 11 01:26:49 PM PDT 23
Finished Oct 11 01:26:56 PM PDT 23
Peak memory 211080 kb
Host smart-1d0b3b35-a235-4eb0-8bf5-71e61c072d8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142598467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4142598467
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.693795889
Short name T262
Test name
Test status
Simulation time 3602849342 ps
CPU time 29.72 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:42 PM PDT 23
Peak memory 213016 kb
Host smart-01b1174c-c586-4dd5-a2a5-592f533edae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693795889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.693795889
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3918561046
Short name T387
Test name
Test status
Simulation time 20099844631 ps
CPU time 96.19 seconds
Started Oct 11 01:27:01 PM PDT 23
Finished Oct 11 01:28:38 PM PDT 23
Peak memory 217212 kb
Host smart-587e8b9c-4e52-4a09-909d-36734fe14126
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918561046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3918561046
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2289673290
Short name T153
Test name
Test status
Simulation time 173086911476 ps
CPU time 3112.86 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 02:18:51 PM PDT 23
Peak memory 252208 kb
Host smart-d6dddc9f-72e0-4125-b3bd-b13eeeb18dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289673290 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2289673290
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3608709524
Short name T301
Test name
Test status
Simulation time 1877006372 ps
CPU time 14.83 seconds
Started Oct 11 01:27:02 PM PDT 23
Finished Oct 11 01:27:17 PM PDT 23
Peak memory 211100 kb
Host smart-0c98aaf1-e835-468c-b513-6e90e4952023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608709524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3608709524
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3492621444
Short name T405
Test name
Test status
Simulation time 325176525365 ps
CPU time 306.82 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:31:19 PM PDT 23
Peak memory 237744 kb
Host smart-84a18d6f-0790-470f-9d9b-5d7299be0251
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492621444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3492621444
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1216636195
Short name T205
Test name
Test status
Simulation time 6365215952 ps
CPU time 26.02 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:41 PM PDT 23
Peak memory 211864 kb
Host smart-f897c2c8-1122-4b45-8aad-03d761543778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216636195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1216636195
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.1424428297
Short name T396
Test name
Test status
Simulation time 3296213180 ps
CPU time 14.87 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:27 PM PDT 23
Peak memory 211156 kb
Host smart-907f754d-31d6-45ed-8176-ca4c024edfc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424428297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.1424428297
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2093144660
Short name T308
Test name
Test status
Simulation time 185364912 ps
CPU time 10.19 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:24 PM PDT 23
Peak memory 211124 kb
Host smart-8416d087-1bb1-48de-8ac0-867433a15a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093144660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2093144660
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1928432281
Short name T89
Test name
Test status
Simulation time 1205223102 ps
CPU time 9.42 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 211032 kb
Host smart-6a5b31fd-09bf-4d32-ab07-e97def2922bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928432281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1928432281
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1506043432
Short name T22
Test name
Test status
Simulation time 229025641169 ps
CPU time 737.31 seconds
Started Oct 11 01:26:59 PM PDT 23
Finished Oct 11 01:39:16 PM PDT 23
Peak memory 229052 kb
Host smart-a74b9f21-c1cc-417f-9470-9adceb34fd72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506043432 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1506043432
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1425722943
Short name T315
Test name
Test status
Simulation time 7245375353 ps
CPU time 15.27 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 01:27:12 PM PDT 23
Peak memory 211184 kb
Host smart-326029d7-95ac-4ba9-bf4d-c2389a6e6862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425722943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1425722943
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1774334556
Short name T302
Test name
Test status
Simulation time 50187318740 ps
CPU time 292.83 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:31:07 PM PDT 23
Peak memory 224584 kb
Host smart-830f1b54-c993-4749-af42-1f76a0ad0494
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774334556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1774334556
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.12233923
Short name T351
Test name
Test status
Simulation time 2314413769 ps
CPU time 22.71 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 01:27:16 PM PDT 23
Peak memory 211404 kb
Host smart-4e1d5060-6d7b-42c6-96c4-2d6e0cab5242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12233923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.12233923
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3787624587
Short name T290
Test name
Test status
Simulation time 6344961886 ps
CPU time 14.53 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:26 PM PDT 23
Peak memory 211212 kb
Host smart-e0587fcb-13dc-4ca7-8dc2-ddd4de3ab243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787624587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3787624587
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4037124318
Short name T390
Test name
Test status
Simulation time 1112685992 ps
CPU time 18.14 seconds
Started Oct 11 01:27:00 PM PDT 23
Finished Oct 11 01:27:18 PM PDT 23
Peak memory 212416 kb
Host smart-9c17d265-1ec2-49b7-ab60-dd06a5ec56a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037124318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4037124318
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1007594119
Short name T170
Test name
Test status
Simulation time 558059514 ps
CPU time 10.31 seconds
Started Oct 11 01:26:59 PM PDT 23
Finished Oct 11 01:27:10 PM PDT 23
Peak memory 210816 kb
Host smart-e9f362a6-35f1-4cf7-9af5-501124813dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007594119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1007594119
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.4201138609
Short name T341
Test name
Test status
Simulation time 237978966208 ps
CPU time 2212.94 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 02:03:06 PM PDT 23
Peak memory 244052 kb
Host smart-2fd74a02-33d9-4a03-b7b6-cc9134f038de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201138609 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.4201138609
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3494914735
Short name T221
Test name
Test status
Simulation time 346872380 ps
CPU time 4.36 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:19 PM PDT 23
Peak memory 211048 kb
Host smart-3cb16a49-8dc6-49f8-a38d-b391f28fa194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494914735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3494914735
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3985455948
Short name T326
Test name
Test status
Simulation time 6534239258 ps
CPU time 143.87 seconds
Started Oct 11 01:26:52 PM PDT 23
Finished Oct 11 01:29:16 PM PDT 23
Peak memory 237064 kb
Host smart-a3abeed6-1ec6-49e9-b64c-0c5e9d3a40c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985455948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3985455948
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2519995681
Short name T414
Test name
Test status
Simulation time 2482869021 ps
CPU time 24.37 seconds
Started Oct 11 01:26:52 PM PDT 23
Finished Oct 11 01:27:17 PM PDT 23
Peak memory 211300 kb
Host smart-4ff2d455-3df6-4fe2-8f3d-d2b53f75bac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519995681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2519995681
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2001966540
Short name T176
Test name
Test status
Simulation time 3019503409 ps
CPU time 14.12 seconds
Started Oct 11 01:26:55 PM PDT 23
Finished Oct 11 01:27:10 PM PDT 23
Peak memory 211092 kb
Host smart-253c03c0-0291-4f43-9b80-fc4fc8a4f78b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001966540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2001966540
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2827668930
Short name T212
Test name
Test status
Simulation time 3934227599 ps
CPU time 36.7 seconds
Started Oct 11 01:26:56 PM PDT 23
Finished Oct 11 01:27:33 PM PDT 23
Peak memory 213064 kb
Host smart-4f372348-b98d-48a9-8127-fa3acb615fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827668930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2827668930
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3382965733
Short name T415
Test name
Test status
Simulation time 505628003 ps
CPU time 27.15 seconds
Started Oct 11 01:26:16 PM PDT 23
Finished Oct 11 01:26:43 PM PDT 23
Peak memory 214324 kb
Host smart-d9b1f748-816d-4d45-8696-add38fe615c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382965733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3382965733
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2187135542
Short name T331
Test name
Test status
Simulation time 618559943 ps
CPU time 7.18 seconds
Started Oct 11 01:26:16 PM PDT 23
Finished Oct 11 01:26:24 PM PDT 23
Peak memory 211108 kb
Host smart-2341ca3f-c6f6-4b5e-8eee-58836aba4817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187135542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2187135542
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1292304405
Short name T223
Test name
Test status
Simulation time 141419808371 ps
CPU time 252.99 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:30:27 PM PDT 23
Peak memory 236764 kb
Host smart-7f40ba0c-487f-4504-9c1d-19e4ce3ea8f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292304405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1292304405
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2963079470
Short name T148
Test name
Test status
Simulation time 2478821172 ps
CPU time 24.34 seconds
Started Oct 11 01:26:56 PM PDT 23
Finished Oct 11 01:27:21 PM PDT 23
Peak memory 211160 kb
Host smart-95abe68d-bf53-4b2d-a3de-4dd5f85f55a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963079470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2963079470
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2569859043
Short name T395
Test name
Test status
Simulation time 95905759 ps
CPU time 5.67 seconds
Started Oct 11 01:26:56 PM PDT 23
Finished Oct 11 01:27:02 PM PDT 23
Peak memory 211068 kb
Host smart-7eb787e6-1496-4f9e-8d67-f557efe82590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569859043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2569859043
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.686422663
Short name T177
Test name
Test status
Simulation time 29545027907 ps
CPU time 22.99 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:38 PM PDT 23
Peak memory 213428 kb
Host smart-effb4ac5-4f81-4571-a63a-ee0ac09c68b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686422663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.686422663
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2126412143
Short name T168
Test name
Test status
Simulation time 2681525592 ps
CPU time 43.1 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:26:54 PM PDT 23
Peak memory 215840 kb
Host smart-6249c634-f02d-46ca-af66-1a965a92190a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126412143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2126412143
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4280667341
Short name T24
Test name
Test status
Simulation time 42258287772 ps
CPU time 1145.28 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:45:18 PM PDT 23
Peak memory 228948 kb
Host smart-36e5581b-7904-48dd-aa5b-bb7742d57090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280667341 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4280667341
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3424134029
Short name T232
Test name
Test status
Simulation time 2576518639 ps
CPU time 9.29 seconds
Started Oct 11 01:26:18 PM PDT 23
Finished Oct 11 01:26:29 PM PDT 23
Peak memory 211172 kb
Host smart-2f77909b-2f87-4c6a-be7b-880e6a58c599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424134029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3424134029
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2198036848
Short name T256
Test name
Test status
Simulation time 61248186222 ps
CPU time 301.01 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:31:13 PM PDT 23
Peak memory 228440 kb
Host smart-91090b79-9a4a-48ab-b696-19e06c5f4420
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198036848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.2198036848
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3681466609
Short name T399
Test name
Test status
Simulation time 6983001652 ps
CPU time 30.16 seconds
Started Oct 11 01:26:11 PM PDT 23
Finished Oct 11 01:26:42 PM PDT 23
Peak memory 211640 kb
Host smart-4e94ea73-e0bf-4896-8f56-b0bcd49d40da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681466609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3681466609
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.2031368371
Short name T425
Test name
Test status
Simulation time 382815835 ps
CPU time 5.95 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:20 PM PDT 23
Peak memory 211028 kb
Host smart-046700d5-c92e-4171-b5c2-a32554b47353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2031368371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.2031368371
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2006862044
Short name T162
Test name
Test status
Simulation time 3243224148 ps
CPU time 36.06 seconds
Started Oct 11 01:26:16 PM PDT 23
Finished Oct 11 01:26:53 PM PDT 23
Peak memory 212928 kb
Host smart-d539d46d-96e2-4211-a5be-8f88e645b493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006862044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2006862044
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4264235904
Short name T346
Test name
Test status
Simulation time 2806289574 ps
CPU time 17.89 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 01:27:15 PM PDT 23
Peak memory 214000 kb
Host smart-48a92874-7d17-4589-87bb-f201e3c3ee52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264235904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4264235904
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1250568200
Short name T108
Test name
Test status
Simulation time 104823857679 ps
CPU time 2193.62 seconds
Started Oct 11 01:26:53 PM PDT 23
Finished Oct 11 02:03:27 PM PDT 23
Peak memory 244008 kb
Host smart-e57963a6-b1a9-482f-8892-f38462adbc50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250568200 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1250568200
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.229556430
Short name T429
Test name
Test status
Simulation time 820163100 ps
CPU time 5.78 seconds
Started Oct 11 01:26:50 PM PDT 23
Finished Oct 11 01:26:56 PM PDT 23
Peak memory 211004 kb
Host smart-48ad4e1a-64b6-4e9f-a56e-60bee3f19f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229556430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.229556430
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2783830737
Short name T403
Test name
Test status
Simulation time 7562724656 ps
CPU time 115.87 seconds
Started Oct 11 01:26:58 PM PDT 23
Finished Oct 11 01:28:54 PM PDT 23
Peak memory 237672 kb
Host smart-d1bddf57-d29b-4358-beef-629296d9190a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783830737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2783830737
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3445748736
Short name T181
Test name
Test status
Simulation time 14877387931 ps
CPU time 33.69 seconds
Started Oct 11 01:26:59 PM PDT 23
Finished Oct 11 01:27:33 PM PDT 23
Peak memory 211476 kb
Host smart-63903a28-1168-4f79-9648-b5e7eae96edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445748736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3445748736
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.2392179901
Short name T284
Test name
Test status
Simulation time 4483211591 ps
CPU time 10 seconds
Started Oct 11 01:26:54 PM PDT 23
Finished Oct 11 01:27:04 PM PDT 23
Peak memory 211136 kb
Host smart-4ccb1003-4760-4124-8c86-c1476b6db7d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2392179901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.2392179901
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.4186289281
Short name T208
Test name
Test status
Simulation time 4256031836 ps
CPU time 29.98 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:26:44 PM PDT 23
Peak memory 213028 kb
Host smart-a80ba1fb-ee57-4b39-8f15-0590179e3a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186289281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.4186289281
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.134852605
Short name T227
Test name
Test status
Simulation time 10043235771 ps
CPU time 44.81 seconds
Started Oct 11 01:26:12 PM PDT 23
Finished Oct 11 01:26:57 PM PDT 23
Peak memory 217708 kb
Host smart-e875f085-3f04-4d64-88a5-016042d573a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134852605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.134852605
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2661691232
Short name T165
Test name
Test status
Simulation time 49977396493 ps
CPU time 5100.72 seconds
Started Oct 11 01:26:09 PM PDT 23
Finished Oct 11 02:51:11 PM PDT 23
Peak memory 233392 kb
Host smart-bb79f29e-d8b7-439c-8a14-690c544cd770
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661691232 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2661691232
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4030113331
Short name T336
Test name
Test status
Simulation time 535241312 ps
CPU time 7.89 seconds
Started Oct 11 01:27:05 PM PDT 23
Finished Oct 11 01:27:13 PM PDT 23
Peak memory 211008 kb
Host smart-9db50e39-1420-4761-8d09-df14808c50c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030113331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4030113331
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3194089095
Short name T250
Test name
Test status
Simulation time 11696273379 ps
CPU time 110.41 seconds
Started Oct 11 01:26:14 PM PDT 23
Finished Oct 11 01:28:05 PM PDT 23
Peak memory 236688 kb
Host smart-1e81c835-f4a1-4e5d-9692-0962771a6ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194089095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3194089095
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4252943150
Short name T12
Test name
Test status
Simulation time 175691527 ps
CPU time 9.75 seconds
Started Oct 11 01:26:15 PM PDT 23
Finished Oct 11 01:26:25 PM PDT 23
Peak memory 211588 kb
Host smart-02a64d0a-4d36-48fe-bd57-a357b5bc75be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252943150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4252943150
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.678912409
Short name T375
Test name
Test status
Simulation time 8708266902 ps
CPU time 16.84 seconds
Started Oct 11 01:27:00 PM PDT 23
Finished Oct 11 01:27:17 PM PDT 23
Peak memory 211172 kb
Host smart-75eb588a-861a-499a-9436-d24498fa7ad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=678912409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.678912409
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1206690361
Short name T247
Test name
Test status
Simulation time 1605041103 ps
CPU time 21.8 seconds
Started Oct 11 01:26:13 PM PDT 23
Finished Oct 11 01:26:35 PM PDT 23
Peak memory 212464 kb
Host smart-5e07f0ce-af34-44e8-ae3a-5e58b78bd6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206690361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1206690361
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.499133768
Short name T402
Test name
Test status
Simulation time 2030757169 ps
CPU time 39.86 seconds
Started Oct 11 01:26:10 PM PDT 23
Finished Oct 11 01:26:50 PM PDT 23
Peak memory 215376 kb
Host smart-42d0a0dd-7a62-4777-880d-86a3d1a99ac8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499133768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.499133768
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.1842233199
Short name T147
Test name
Test status
Simulation time 51098023567 ps
CPU time 1295.62 seconds
Started Oct 11 01:26:18 PM PDT 23
Finished Oct 11 01:47:56 PM PDT 23
Peak memory 233696 kb
Host smart-ca2b318e-7b51-4686-9394-f347b2d43027
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842233199 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.1842233199
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.646246967
Short name T433
Test name
Test status
Simulation time 347505014 ps
CPU time 4.39 seconds
Started Oct 11 01:25:23 PM PDT 23
Finished Oct 11 01:25:28 PM PDT 23
Peak memory 211096 kb
Host smart-88e7fdf0-70cd-40ee-ae5e-09ed9619c349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646246967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.646246967
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2840977015
Short name T360
Test name
Test status
Simulation time 1854598539 ps
CPU time 112.29 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:27:11 PM PDT 23
Peak memory 228332 kb
Host smart-1ec54f33-77c5-4a87-9ed1-30aa45555630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840977015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2840977015
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3838596932
Short name T179
Test name
Test status
Simulation time 5169440622 ps
CPU time 25.46 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 01:25:45 PM PDT 23
Peak memory 211640 kb
Host smart-d2ccfc27-2949-48ac-87c0-a66a8247b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838596932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3838596932
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1889844158
Short name T1
Test name
Test status
Simulation time 384365091 ps
CPU time 5.73 seconds
Started Oct 11 01:26:16 PM PDT 23
Finished Oct 11 01:26:22 PM PDT 23
Peak memory 211044 kb
Host smart-a2496850-53a9-487e-9592-1d6ea0434e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889844158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1889844158
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3613663561
Short name T385
Test name
Test status
Simulation time 2105729323 ps
CPU time 23.05 seconds
Started Oct 11 01:25:14 PM PDT 23
Finished Oct 11 01:25:38 PM PDT 23
Peak memory 212372 kb
Host smart-84982ae6-4807-4f3a-bac0-b97c90179c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613663561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3613663561
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3532387035
Short name T364
Test name
Test status
Simulation time 22828493130 ps
CPU time 53.77 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:25:56 PM PDT 23
Peak memory 216184 kb
Host smart-19865f7b-5e90-4587-9262-f4866131298e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532387035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3532387035
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2267190591
Short name T311
Test name
Test status
Simulation time 1195928176 ps
CPU time 11.1 seconds
Started Oct 11 01:25:02 PM PDT 23
Finished Oct 11 01:25:13 PM PDT 23
Peak memory 211060 kb
Host smart-f5a2b78c-10ae-4954-af2b-ec610d58390f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267190591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2267190591
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2345851281
Short name T316
Test name
Test status
Simulation time 8244689079 ps
CPU time 147.11 seconds
Started Oct 11 01:25:18 PM PDT 23
Finished Oct 11 01:27:46 PM PDT 23
Peak memory 228460 kb
Host smart-c3254e82-5f25-4886-93f3-a84a131042e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345851281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2345851281
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1941727428
Short name T404
Test name
Test status
Simulation time 757214484 ps
CPU time 9.37 seconds
Started Oct 11 01:25:21 PM PDT 23
Finished Oct 11 01:25:31 PM PDT 23
Peak memory 211340 kb
Host smart-cb73f3b6-338f-420b-9b07-1d9223bc0764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941727428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1941727428
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.567639678
Short name T99
Test name
Test status
Simulation time 100427923 ps
CPU time 5.71 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:31 PM PDT 23
Peak memory 211064 kb
Host smart-f839510a-932a-4bf6-9048-7b16316e88fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567639678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.567639678
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2965634162
Short name T236
Test name
Test status
Simulation time 3947876486 ps
CPU time 39.05 seconds
Started Oct 11 01:25:56 PM PDT 23
Finished Oct 11 01:26:36 PM PDT 23
Peak memory 212548 kb
Host smart-685e62f0-61db-4d22-9b47-0cf07eb82231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965634162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2965634162
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.2103339967
Short name T291
Test name
Test status
Simulation time 4494508802 ps
CPU time 56.23 seconds
Started Oct 11 01:25:15 PM PDT 23
Finished Oct 11 01:26:12 PM PDT 23
Peak memory 216264 kb
Host smart-b818811d-0c2f-4b5e-965a-800e24c2c8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103339967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.2103339967
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.367215782
Short name T354
Test name
Test status
Simulation time 87279925 ps
CPU time 4.47 seconds
Started Oct 11 01:26:49 PM PDT 23
Finished Oct 11 01:26:54 PM PDT 23
Peak memory 211048 kb
Host smart-32493946-17d1-4029-832c-41ebed0dc27f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367215782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.367215782
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1821535238
Short name T342
Test name
Test status
Simulation time 1813145089 ps
CPU time 119.37 seconds
Started Oct 11 01:25:41 PM PDT 23
Finished Oct 11 01:27:41 PM PDT 23
Peak memory 238880 kb
Host smart-f4e576ce-7f36-4890-b05f-c43afb2b250d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821535238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1821535238
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2021434064
Short name T373
Test name
Test status
Simulation time 11550186827 ps
CPU time 26.49 seconds
Started Oct 11 01:25:27 PM PDT 23
Finished Oct 11 01:25:53 PM PDT 23
Peak memory 212360 kb
Host smart-34abcebd-f2fc-45b3-b9dd-8a54532fed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021434064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2021434064
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1708915158
Short name T175
Test name
Test status
Simulation time 3690678095 ps
CPU time 15.24 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:26:17 PM PDT 23
Peak memory 211124 kb
Host smart-a734444f-f84a-443a-938c-ac362b6f67a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708915158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1708915158
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3017794628
Short name T259
Test name
Test status
Simulation time 179971372 ps
CPU time 10.14 seconds
Started Oct 11 01:25:58 PM PDT 23
Finished Oct 11 01:26:08 PM PDT 23
Peak memory 212684 kb
Host smart-315f7aa0-ed63-462f-bc42-fa1f4169bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017794628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3017794628
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.605153491
Short name T285
Test name
Test status
Simulation time 6438437779 ps
CPU time 60.05 seconds
Started Oct 11 01:25:00 PM PDT 23
Finished Oct 11 01:26:00 PM PDT 23
Peak memory 216088 kb
Host smart-a40f9a1e-02aa-4898-8fea-66d6ce913087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605153491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.605153491
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2354011051
Short name T195
Test name
Test status
Simulation time 34868675022 ps
CPU time 2764.8 seconds
Started Oct 11 01:25:19 PM PDT 23
Finished Oct 11 02:11:24 PM PDT 23
Peak memory 231304 kb
Host smart-e9426be0-9408-45d8-a7a0-cd9c47dcf5aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354011051 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2354011051
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3374471318
Short name T224
Test name
Test status
Simulation time 1038837715 ps
CPU time 4.33 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:29 PM PDT 23
Peak memory 211072 kb
Host smart-0c8708cb-6076-48ad-97b3-df7c4ccf778d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374471318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3374471318
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3940187325
Short name T50
Test name
Test status
Simulation time 42537958227 ps
CPU time 383.9 seconds
Started Oct 11 01:26:57 PM PDT 23
Finished Oct 11 01:33:22 PM PDT 23
Peak memory 237856 kb
Host smart-9e159b6e-041d-4108-a0ee-d84b1ecfceee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940187325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3940187325
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1746430210
Short name T424
Test name
Test status
Simulation time 3622363185 ps
CPU time 21.71 seconds
Started Oct 11 01:25:28 PM PDT 23
Finished Oct 11 01:25:50 PM PDT 23
Peak memory 211200 kb
Host smart-324f8ee9-a735-4a76-816d-d0112ce3e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746430210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1746430210
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2697371440
Short name T188
Test name
Test status
Simulation time 630338559 ps
CPU time 9.32 seconds
Started Oct 11 01:26:56 PM PDT 23
Finished Oct 11 01:27:06 PM PDT 23
Peak memory 211116 kb
Host smart-a884c396-cecd-47bc-bbfe-f2fc60b3b32f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697371440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2697371440
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2290782166
Short name T295
Test name
Test status
Simulation time 7747880919 ps
CPU time 35.98 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:26:37 PM PDT 23
Peak memory 214192 kb
Host smart-ea6ca6d4-ffef-4410-8d35-a12579dc3d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290782166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2290782166
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2572133367
Short name T394
Test name
Test status
Simulation time 1520877831 ps
CPU time 23.04 seconds
Started Oct 11 01:25:43 PM PDT 23
Finished Oct 11 01:26:06 PM PDT 23
Peak memory 215752 kb
Host smart-c27e7928-136d-4c30-8236-a792c0e14342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572133367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2572133367
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.8712341
Short name T196
Test name
Test status
Simulation time 110460199296 ps
CPU time 1011.91 seconds
Started Oct 11 01:25:32 PM PDT 23
Finished Oct 11 01:42:25 PM PDT 23
Peak memory 231184 kb
Host smart-e5d2b477-1a05-4571-a538-c52d3852ff89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8712341 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.8712341
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3682507029
Short name T39
Test name
Test status
Simulation time 1046353340 ps
CPU time 10.29 seconds
Started Oct 11 01:25:25 PM PDT 23
Finished Oct 11 01:25:36 PM PDT 23
Peak memory 211064 kb
Host smart-1eba0baa-add1-4fe7-a94e-c395af2b616b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682507029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3682507029
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3703803377
Short name T304
Test name
Test status
Simulation time 113503909090 ps
CPU time 180.41 seconds
Started Oct 11 01:24:59 PM PDT 23
Finished Oct 11 01:28:00 PM PDT 23
Peak memory 228424 kb
Host smart-d4406219-0581-4810-8e68-f3451e9b31cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703803377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3703803377
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.167259433
Short name T258
Test name
Test status
Simulation time 7938604050 ps
CPU time 27.78 seconds
Started Oct 11 01:26:03 PM PDT 23
Finished Oct 11 01:26:31 PM PDT 23
Peak memory 211932 kb
Host smart-980ff7d4-3055-48b4-ae67-318c3ce3dfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167259433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.167259433
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2471178953
Short name T198
Test name
Test status
Simulation time 2103251638 ps
CPU time 17.13 seconds
Started Oct 11 01:25:26 PM PDT 23
Finished Oct 11 01:25:43 PM PDT 23
Peak memory 211080 kb
Host smart-f907a522-9daa-484c-a7ab-5ddc3017a9fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471178953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2471178953
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.19994088
Short name T254
Test name
Test status
Simulation time 239805115 ps
CPU time 10.05 seconds
Started Oct 11 01:26:01 PM PDT 23
Finished Oct 11 01:26:12 PM PDT 23
Peak memory 212664 kb
Host smart-03f1d291-8b4a-425c-8e08-47e0832e7311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19994088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.19994088
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.4136490856
Short name T229
Test name
Test status
Simulation time 1336922286 ps
CPU time 14.94 seconds
Started Oct 11 01:25:27 PM PDT 23
Finished Oct 11 01:25:43 PM PDT 23
Peak memory 210888 kb
Host smart-9fa18344-f794-4f96-a538-caa6be4cad38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136490856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.4136490856
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.43300587
Short name T275
Test name
Test status
Simulation time 41342831439 ps
CPU time 2530.69 seconds
Started Oct 11 01:25:22 PM PDT 23
Finished Oct 11 02:07:33 PM PDT 23
Peak memory 232188 kb
Host smart-38750a0a-921a-44af-afe0-f74fe1ca5fc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43300587 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.43300587
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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