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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.62 97.11 93.27 97.88 100.00 99.02 97.89 98.14


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T268 /workspace/coverage/default/9.rom_ctrl_alert_test.1338962672 Oct 15 12:33:14 PM PDT 23 Oct 15 12:33:31 PM PDT 23 8595303872 ps
T269 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1441021622 Oct 15 12:34:42 PM PDT 23 Oct 15 12:35:10 PM PDT 23 5070412308 ps
T270 /workspace/coverage/default/1.rom_ctrl_stress_all.452911789 Oct 15 12:33:26 PM PDT 23 Oct 15 12:34:56 PM PDT 23 80928559866 ps
T271 /workspace/coverage/default/3.rom_ctrl_alert_test.1646699416 Oct 15 12:33:25 PM PDT 23 Oct 15 12:33:42 PM PDT 23 2477851200 ps
T272 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2566709704 Oct 15 12:34:27 PM PDT 23 Oct 15 12:34:37 PM PDT 23 1381896532 ps
T273 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2867311312 Oct 15 12:33:55 PM PDT 23 Oct 15 12:39:57 PM PDT 23 206937574247 ps
T274 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.10555864 Oct 15 12:33:57 PM PDT 23 Oct 15 01:00:44 PM PDT 23 34946408103 ps
T275 /workspace/coverage/default/47.rom_ctrl_alert_test.3807259877 Oct 15 12:34:44 PM PDT 23 Oct 15 12:35:00 PM PDT 23 3100508183 ps
T276 /workspace/coverage/default/42.rom_ctrl_alert_test.2141862614 Oct 15 12:34:28 PM PDT 23 Oct 15 12:34:39 PM PDT 23 3735934964 ps
T277 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.301211345 Oct 15 12:34:07 PM PDT 23 Oct 15 12:39:45 PM PDT 23 32481512390 ps
T278 /workspace/coverage/default/47.rom_ctrl_smoke.3049963834 Oct 15 12:34:14 PM PDT 23 Oct 15 12:34:24 PM PDT 23 742967448 ps
T279 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2463407548 Oct 15 12:34:26 PM PDT 23 Oct 15 12:36:54 PM PDT 23 31347171377 ps
T280 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.454534919 Oct 15 12:34:32 PM PDT 23 Oct 15 12:34:47 PM PDT 23 7223372541 ps
T281 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.991715745 Oct 15 12:33:35 PM PDT 23 Oct 15 12:36:30 PM PDT 23 58209028400 ps
T282 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.532946166 Oct 15 12:34:13 PM PDT 23 Oct 15 12:34:21 PM PDT 23 1189771079 ps
T283 /workspace/coverage/default/36.rom_ctrl_alert_test.929838737 Oct 15 12:34:10 PM PDT 23 Oct 15 12:34:21 PM PDT 23 4431577410 ps
T284 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.433869682 Oct 15 12:33:38 PM PDT 23 Oct 15 12:38:29 PM PDT 23 87285109916 ps
T285 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1888047172 Oct 15 12:34:07 PM PDT 23 Oct 15 12:34:27 PM PDT 23 1737425070 ps
T286 /workspace/coverage/default/48.rom_ctrl_smoke.837423517 Oct 15 12:34:22 PM PDT 23 Oct 15 12:34:43 PM PDT 23 1554581169 ps
T287 /workspace/coverage/default/26.rom_ctrl_alert_test.4008466384 Oct 15 12:34:19 PM PDT 23 Oct 15 12:34:27 PM PDT 23 1382670087 ps
T288 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2576150243 Oct 15 12:33:30 PM PDT 23 Oct 15 12:47:38 PM PDT 23 77326847993 ps
T289 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1972994535 Oct 15 12:33:55 PM PDT 23 Oct 15 12:34:04 PM PDT 23 428139874 ps
T290 /workspace/coverage/default/6.rom_ctrl_smoke.1912436217 Oct 15 12:33:29 PM PDT 23 Oct 15 12:34:05 PM PDT 23 3793648192 ps
T291 /workspace/coverage/default/2.rom_ctrl_smoke.1705175429 Oct 15 12:34:03 PM PDT 23 Oct 15 12:34:27 PM PDT 23 10229868958 ps
T292 /workspace/coverage/default/39.rom_ctrl_stress_all.1599503502 Oct 15 12:34:27 PM PDT 23 Oct 15 12:34:48 PM PDT 23 6973255242 ps
T293 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3471567974 Oct 15 12:34:00 PM PDT 23 Oct 15 01:09:01 PM PDT 23 35847021050 ps
T294 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1188121137 Oct 15 12:34:12 PM PDT 23 Oct 15 12:34:29 PM PDT 23 7852508007 ps
T295 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1448117626 Oct 15 12:33:57 PM PDT 23 Oct 15 12:34:18 PM PDT 23 14516210893 ps
T296 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4286339598 Oct 15 12:33:46 PM PDT 23 Oct 15 12:45:42 PM PDT 23 58888522834 ps
T297 /workspace/coverage/default/3.rom_ctrl_smoke.1886533964 Oct 15 12:33:30 PM PDT 23 Oct 15 12:33:56 PM PDT 23 10806699857 ps
T298 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.783848441 Oct 15 12:34:44 PM PDT 23 Oct 15 12:34:56 PM PDT 23 943132898 ps
T299 /workspace/coverage/default/35.rom_ctrl_alert_test.847116388 Oct 15 12:34:08 PM PDT 23 Oct 15 12:34:23 PM PDT 23 8008430257 ps
T300 /workspace/coverage/default/1.rom_ctrl_smoke.3072457187 Oct 15 12:33:24 PM PDT 23 Oct 15 12:33:35 PM PDT 23 184765234 ps
T301 /workspace/coverage/default/1.rom_ctrl_alert_test.3991078195 Oct 15 12:33:21 PM PDT 23 Oct 15 12:33:26 PM PDT 23 90076915 ps
T302 /workspace/coverage/default/23.rom_ctrl_smoke.1941889953 Oct 15 12:34:09 PM PDT 23 Oct 15 12:34:19 PM PDT 23 374266867 ps
T303 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3718009995 Oct 15 12:33:22 PM PDT 23 Oct 15 12:33:49 PM PDT 23 2891869061 ps
T304 /workspace/coverage/default/10.rom_ctrl_alert_test.1671784992 Oct 15 12:33:21 PM PDT 23 Oct 15 12:33:26 PM PDT 23 85511136 ps
T305 /workspace/coverage/default/9.rom_ctrl_stress_all.2331643309 Oct 15 12:33:21 PM PDT 23 Oct 15 12:33:37 PM PDT 23 627756848 ps
T306 /workspace/coverage/default/7.rom_ctrl_stress_all.2342092569 Oct 15 12:33:33 PM PDT 23 Oct 15 12:33:54 PM PDT 23 1629722213 ps
T307 /workspace/coverage/default/12.rom_ctrl_smoke.1164289240 Oct 15 12:33:36 PM PDT 23 Oct 15 12:33:46 PM PDT 23 711612329 ps
T308 /workspace/coverage/default/23.rom_ctrl_alert_test.2927985476 Oct 15 12:33:58 PM PDT 23 Oct 15 12:34:11 PM PDT 23 1600332032 ps
T309 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1309012896 Oct 15 12:33:25 PM PDT 23 Oct 15 12:44:24 PM PDT 23 73604413915 ps
T310 /workspace/coverage/default/46.rom_ctrl_alert_test.718370443 Oct 15 12:34:36 PM PDT 23 Oct 15 12:34:42 PM PDT 23 438002623 ps
T311 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1113576015 Oct 15 12:34:10 PM PDT 23 Oct 15 12:34:21 PM PDT 23 3260145550 ps
T312 /workspace/coverage/default/36.rom_ctrl_smoke.3867712578 Oct 15 12:34:12 PM PDT 23 Oct 15 12:34:51 PM PDT 23 4205390932 ps
T313 /workspace/coverage/default/30.rom_ctrl_alert_test.3224225076 Oct 15 12:33:56 PM PDT 23 Oct 15 12:34:06 PM PDT 23 925763177 ps
T314 /workspace/coverage/default/32.rom_ctrl_alert_test.2201116451 Oct 15 12:34:05 PM PDT 23 Oct 15 12:34:21 PM PDT 23 9631627089 ps
T315 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3309939317 Oct 15 12:34:36 PM PDT 23 Oct 15 12:34:43 PM PDT 23 438346950 ps
T316 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2977929949 Oct 15 12:33:15 PM PDT 23 Oct 15 12:33:35 PM PDT 23 23254318851 ps
T111 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3594829469 Oct 15 12:34:40 PM PDT 23 Oct 15 12:47:48 PM PDT 23 80717724118 ps
T317 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2319992461 Oct 15 12:33:58 PM PDT 23 Oct 15 12:34:23 PM PDT 23 31739940359 ps
T318 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1594409224 Oct 15 12:33:11 PM PDT 23 Oct 15 12:42:45 PM PDT 23 252273618743 ps
T319 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1104831272 Oct 15 12:34:02 PM PDT 23 Oct 15 12:34:20 PM PDT 23 2368157862 ps
T320 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1135711867 Oct 15 12:33:44 PM PDT 23 Oct 15 12:36:41 PM PDT 23 39580678904 ps
T321 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2936094343 Oct 15 12:34:16 PM PDT 23 Oct 15 12:36:22 PM PDT 23 7294399212 ps
T322 /workspace/coverage/default/33.rom_ctrl_stress_all.1095315790 Oct 15 12:34:14 PM PDT 23 Oct 15 12:36:03 PM PDT 23 54092390716 ps
T323 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2735874009 Oct 15 12:33:41 PM PDT 23 Oct 15 12:34:15 PM PDT 23 15620707083 ps
T324 /workspace/coverage/default/21.rom_ctrl_alert_test.1713511160 Oct 15 12:33:54 PM PDT 23 Oct 15 12:34:09 PM PDT 23 12564451211 ps
T325 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1192992353 Oct 15 12:34:08 PM PDT 23 Oct 15 12:34:25 PM PDT 23 1986465423 ps
T326 /workspace/coverage/default/47.rom_ctrl_stress_all.3110060664 Oct 15 12:34:51 PM PDT 23 Oct 15 12:35:38 PM PDT 23 34618574196 ps
T327 /workspace/coverage/default/32.rom_ctrl_stress_all.1056675765 Oct 15 12:34:15 PM PDT 23 Oct 15 12:35:00 PM PDT 23 3075326383 ps
T328 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2261362497 Oct 15 12:33:54 PM PDT 23 Oct 15 12:37:28 PM PDT 23 19386648202 ps
T329 /workspace/coverage/default/6.rom_ctrl_alert_test.51140801 Oct 15 12:33:28 PM PDT 23 Oct 15 12:33:33 PM PDT 23 826967493 ps
T330 /workspace/coverage/default/41.rom_ctrl_stress_all.65995099 Oct 15 12:34:04 PM PDT 23 Oct 15 12:35:05 PM PDT 23 4914501688 ps
T331 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1218421944 Oct 15 12:33:53 PM PDT 23 Oct 15 12:34:19 PM PDT 23 2540465582 ps
T332 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.304176086 Oct 15 12:34:19 PM PDT 23 Oct 15 12:34:33 PM PDT 23 1612380788 ps
T333 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3350002591 Oct 15 12:34:54 PM PDT 23 Oct 15 12:45:40 PM PDT 23 67681274746 ps
T334 /workspace/coverage/default/5.rom_ctrl_stress_all.753842168 Oct 15 12:34:12 PM PDT 23 Oct 15 12:35:29 PM PDT 23 36558464084 ps
T335 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1288476267 Oct 15 12:34:10 PM PDT 23 Oct 15 01:02:48 PM PDT 23 23990232526 ps
T336 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3548395738 Oct 15 12:34:28 PM PDT 23 Oct 15 12:38:50 PM PDT 23 116675554716 ps
T337 /workspace/coverage/default/4.rom_ctrl_smoke.594697358 Oct 15 12:33:16 PM PDT 23 Oct 15 12:33:27 PM PDT 23 713022461 ps
T338 /workspace/coverage/default/4.rom_ctrl_alert_test.1880308611 Oct 15 12:33:36 PM PDT 23 Oct 15 12:33:45 PM PDT 23 866816010 ps
T339 /workspace/coverage/default/15.rom_ctrl_stress_all.2358124601 Oct 15 12:33:54 PM PDT 23 Oct 15 12:35:00 PM PDT 23 30421445935 ps
T340 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1932140582 Oct 15 12:33:48 PM PDT 23 Oct 15 12:34:00 PM PDT 23 690571914 ps
T341 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.12470138 Oct 15 12:34:10 PM PDT 23 Oct 15 12:55:43 PM PDT 23 72449203693 ps
T342 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2879417835 Oct 15 12:33:34 PM PDT 23 Oct 15 12:33:47 PM PDT 23 2460231189 ps
T343 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.437203864 Oct 15 12:34:40 PM PDT 23 Oct 15 12:34:47 PM PDT 23 100636141 ps
T344 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.582862938 Oct 15 12:33:45 PM PDT 23 Oct 15 12:42:31 PM PDT 23 35655170012 ps
T345 /workspace/coverage/default/40.rom_ctrl_smoke.1037458408 Oct 15 12:34:31 PM PDT 23 Oct 15 12:35:07 PM PDT 23 12878672528 ps
T346 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3108602916 Oct 15 12:34:04 PM PDT 23 Oct 15 12:34:14 PM PDT 23 693039346 ps
T347 /workspace/coverage/default/41.rom_ctrl_alert_test.986974427 Oct 15 12:34:31 PM PDT 23 Oct 15 12:34:41 PM PDT 23 1023813138 ps
T37 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1086317322 Oct 15 12:34:15 PM PDT 23 Oct 15 12:34:29 PM PDT 23 494481125 ps
T348 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3744229842 Oct 15 12:34:16 PM PDT 23 Oct 15 12:34:28 PM PDT 23 172310115 ps
T349 /workspace/coverage/default/45.rom_ctrl_smoke.2489246667 Oct 15 12:34:07 PM PDT 23 Oct 15 12:34:48 PM PDT 23 13966063417 ps
T350 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.273485265 Oct 15 12:34:55 PM PDT 23 Oct 15 12:35:11 PM PDT 23 1736991197 ps
T351 /workspace/coverage/default/40.rom_ctrl_stress_all.2768549142 Oct 15 12:33:52 PM PDT 23 Oct 15 12:34:11 PM PDT 23 7381927205 ps
T352 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2366951122 Oct 15 12:33:52 PM PDT 23 Oct 15 01:13:22 PM PDT 23 97607217426 ps
T353 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.345870799 Oct 15 12:34:12 PM PDT 23 Oct 15 12:34:18 PM PDT 23 190079303 ps
T354 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3152035879 Oct 15 12:34:18 PM PDT 23 Oct 15 02:03:03 PM PDT 23 32557722531 ps
T355 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1080355849 Oct 15 12:33:37 PM PDT 23 Oct 15 12:34:05 PM PDT 23 6321920627 ps
T356 /workspace/coverage/default/12.rom_ctrl_stress_all.3877539466 Oct 15 12:33:22 PM PDT 23 Oct 15 12:34:45 PM PDT 23 33038757784 ps
T357 /workspace/coverage/default/27.rom_ctrl_alert_test.1572529438 Oct 15 12:33:53 PM PDT 23 Oct 15 12:34:09 PM PDT 23 4028520868 ps
T358 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.62425598 Oct 15 12:34:01 PM PDT 23 Oct 15 12:34:28 PM PDT 23 3326736559 ps
T39 /workspace/coverage/default/2.rom_ctrl_sec_cm.1212365002 Oct 15 12:33:26 PM PDT 23 Oct 15 12:35:17 PM PDT 23 652933669 ps
T52 /workspace/coverage/default/27.rom_ctrl_smoke.3079563731 Oct 15 12:34:14 PM PDT 23 Oct 15 12:34:44 PM PDT 23 3544159985 ps
T53 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2607020801 Oct 15 12:34:24 PM PDT 23 Oct 15 12:34:45 PM PDT 23 1971186199 ps
T40 /workspace/coverage/default/1.rom_ctrl_sec_cm.2803231 Oct 15 12:33:20 PM PDT 23 Oct 15 12:34:24 PM PDT 23 24951056741 ps
T359 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.532838054 Oct 15 12:34:10 PM PDT 23 Oct 15 12:34:16 PM PDT 23 364760569 ps
T360 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1369637507 Oct 15 12:33:51 PM PDT 23 Oct 15 12:34:07 PM PDT 23 1828375567 ps
T361 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1278942994 Oct 15 12:34:15 PM PDT 23 Oct 15 12:36:34 PM PDT 23 67704735357 ps
T362 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1418136565 Oct 15 12:33:20 PM PDT 23 Oct 15 12:33:26 PM PDT 23 379964324 ps
T363 /workspace/coverage/default/19.rom_ctrl_alert_test.1257893513 Oct 15 12:33:53 PM PDT 23 Oct 15 12:33:58 PM PDT 23 334406259 ps
T364 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3849649781 Oct 15 12:34:26 PM PDT 23 Oct 15 12:34:36 PM PDT 23 640355086 ps
T365 /workspace/coverage/default/27.rom_ctrl_stress_all.1732492686 Oct 15 12:34:22 PM PDT 23 Oct 15 12:34:32 PM PDT 23 332068354 ps
T366 /workspace/coverage/default/39.rom_ctrl_smoke.1729391377 Oct 15 12:34:11 PM PDT 23 Oct 15 12:34:42 PM PDT 23 2570765890 ps
T367 /workspace/coverage/default/44.rom_ctrl_alert_test.3499024639 Oct 15 12:34:20 PM PDT 23 Oct 15 12:34:30 PM PDT 23 87302470 ps
T368 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3906513956 Oct 15 12:33:44 PM PDT 23 Oct 15 12:34:04 PM PDT 23 6497930348 ps
T18 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2696136638 Oct 15 12:34:12 PM PDT 23 Oct 15 02:21:03 PM PDT 23 324709017832 ps
T369 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1718889087 Oct 15 12:33:59 PM PDT 23 Oct 15 12:37:10 PM PDT 23 16213923154 ps
T370 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2660003525 Oct 15 12:33:14 PM PDT 23 Oct 15 12:33:30 PM PDT 23 7167635263 ps
T371 /workspace/coverage/default/21.rom_ctrl_stress_all.2992247727 Oct 15 12:34:13 PM PDT 23 Oct 15 12:35:00 PM PDT 23 13796262698 ps
T372 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4060675063 Oct 15 12:34:17 PM PDT 23 Oct 15 12:37:22 PM PDT 23 6686988847 ps
T44 /workspace/coverage/default/3.rom_ctrl_sec_cm.1908586859 Oct 15 12:33:17 PM PDT 23 Oct 15 12:35:18 PM PDT 23 9274894850 ps
T373 /workspace/coverage/default/44.rom_ctrl_stress_all.3164837705 Oct 15 12:34:17 PM PDT 23 Oct 15 12:34:36 PM PDT 23 2190714942 ps
T374 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1616534366 Oct 15 12:33:52 PM PDT 23 Oct 15 12:34:08 PM PDT 23 1735539786 ps
T375 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3586735604 Oct 15 12:34:11 PM PDT 23 Oct 15 12:34:23 PM PDT 23 2136584518 ps
T376 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.304450192 Oct 15 12:33:47 PM PDT 23 Oct 15 12:34:20 PM PDT 23 23518183685 ps
T377 /workspace/coverage/default/49.rom_ctrl_smoke.4088648863 Oct 15 12:34:38 PM PDT 23 Oct 15 12:34:56 PM PDT 23 1086761563 ps
T378 /workspace/coverage/default/32.rom_ctrl_smoke.2758452488 Oct 15 12:34:32 PM PDT 23 Oct 15 12:35:11 PM PDT 23 4011603826 ps
T379 /workspace/coverage/default/11.rom_ctrl_smoke.2916675527 Oct 15 12:33:30 PM PDT 23 Oct 15 12:33:41 PM PDT 23 2191773245 ps
T380 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1265642959 Oct 15 12:33:53 PM PDT 23 Oct 15 12:36:02 PM PDT 23 7706368758 ps
T381 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2558478350 Oct 15 12:34:08 PM PDT 23 Oct 15 01:20:26 PM PDT 23 73143038799 ps
T382 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3387835173 Oct 15 12:34:18 PM PDT 23 Oct 15 12:34:24 PM PDT 23 381420836 ps
T383 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.697729840 Oct 15 12:34:05 PM PDT 23 Oct 15 12:39:38 PM PDT 23 121657572532 ps
T384 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1759933506 Oct 15 12:33:46 PM PDT 23 Oct 15 12:33:55 PM PDT 23 347452756 ps
T385 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2927616476 Oct 15 12:34:04 PM PDT 23 Oct 15 12:39:44 PM PDT 23 35150183842 ps
T45 /workspace/coverage/default/4.rom_ctrl_sec_cm.1555422086 Oct 15 12:33:36 PM PDT 23 Oct 15 12:34:40 PM PDT 23 4385258016 ps
T386 /workspace/coverage/default/14.rom_ctrl_alert_test.2996924720 Oct 15 12:34:01 PM PDT 23 Oct 15 12:34:07 PM PDT 23 256632146 ps
T387 /workspace/coverage/default/29.rom_ctrl_smoke.3343685312 Oct 15 12:33:58 PM PDT 23 Oct 15 12:34:26 PM PDT 23 11977443313 ps
T388 /workspace/coverage/default/49.rom_ctrl_stress_all.869618145 Oct 15 12:34:30 PM PDT 23 Oct 15 12:35:08 PM PDT 23 2821485884 ps
T389 /workspace/coverage/default/26.rom_ctrl_stress_all.3666425789 Oct 15 12:33:45 PM PDT 23 Oct 15 12:33:54 PM PDT 23 1591864323 ps
T390 /workspace/coverage/default/0.rom_ctrl_smoke.1247285737 Oct 15 12:33:19 PM PDT 23 Oct 15 12:33:46 PM PDT 23 11984375438 ps
T391 /workspace/coverage/default/46.rom_ctrl_smoke.1736048080 Oct 15 12:34:53 PM PDT 23 Oct 15 12:35:20 PM PDT 23 2650731714 ps
T392 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2554760476 Oct 15 12:34:06 PM PDT 23 Oct 15 12:36:14 PM PDT 23 4229928312 ps
T393 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3575399013 Oct 15 12:33:43 PM PDT 23 Oct 15 12:34:00 PM PDT 23 1943604899 ps
T394 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.445772576 Oct 15 12:33:29 PM PDT 23 Oct 15 12:45:06 PM PDT 23 39091069554 ps
T395 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3112795827 Oct 15 12:33:40 PM PDT 23 Oct 15 01:08:04 PM PDT 23 47439778333 ps
T396 /workspace/coverage/default/38.rom_ctrl_stress_all.1326097151 Oct 15 12:34:40 PM PDT 23 Oct 15 12:35:03 PM PDT 23 1583198031 ps
T397 /workspace/coverage/default/11.rom_ctrl_alert_test.233546195 Oct 15 12:33:42 PM PDT 23 Oct 15 12:33:59 PM PDT 23 2071220883 ps
T398 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1177496278 Oct 15 12:33:18 PM PDT 23 Oct 15 01:07:25 PM PDT 23 21534581620 ps
T399 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2742692569 Oct 15 12:34:23 PM PDT 23 Oct 15 12:34:54 PM PDT 23 23360776122 ps
T400 /workspace/coverage/default/28.rom_ctrl_alert_test.1694986283 Oct 15 12:33:54 PM PDT 23 Oct 15 12:34:00 PM PDT 23 4936082581 ps
T401 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.711644497 Oct 15 12:34:23 PM PDT 23 Oct 15 12:40:51 PM PDT 23 80794767268 ps
T402 /workspace/coverage/default/17.rom_ctrl_alert_test.642829475 Oct 15 12:33:51 PM PDT 23 Oct 15 12:34:08 PM PDT 23 8691517211 ps
T403 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4202076509 Oct 15 12:33:15 PM PDT 23 Oct 15 12:34:57 PM PDT 23 3524698914 ps
T404 /workspace/coverage/default/8.rom_ctrl_stress_all.3979412890 Oct 15 12:34:30 PM PDT 23 Oct 15 12:34:47 PM PDT 23 1511369040 ps
T405 /workspace/coverage/default/38.rom_ctrl_alert_test.2753679840 Oct 15 12:34:16 PM PDT 23 Oct 15 12:34:22 PM PDT 23 263861417 ps
T406 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.8252394 Oct 15 12:34:03 PM PDT 23 Oct 15 12:34:16 PM PDT 23 729037812 ps
T407 /workspace/coverage/default/8.rom_ctrl_alert_test.3547086816 Oct 15 12:33:27 PM PDT 23 Oct 15 12:33:33 PM PDT 23 254153885 ps
T408 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.623714592 Oct 15 12:33:50 PM PDT 23 Oct 15 12:39:10 PM PDT 23 60692921810 ps
T409 /workspace/coverage/default/25.rom_ctrl_smoke.4228103992 Oct 15 12:33:38 PM PDT 23 Oct 15 12:34:08 PM PDT 23 3395194702 ps
T410 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3906433522 Oct 15 12:33:47 PM PDT 23 Oct 15 12:33:53 PM PDT 23 189353331 ps
T411 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.387421533 Oct 15 12:34:28 PM PDT 23 Oct 15 12:34:38 PM PDT 23 874946622 ps
T412 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3949814399 Oct 15 12:33:56 PM PDT 23 Oct 15 12:34:02 PM PDT 23 137100414 ps
T413 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1571912732 Oct 15 12:33:48 PM PDT 23 Oct 15 12:38:40 PM PDT 23 111304220827 ps
T414 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4028504368 Oct 15 12:34:00 PM PDT 23 Oct 15 12:36:10 PM PDT 23 14211078950 ps
T415 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2507681207 Oct 15 12:34:12 PM PDT 23 Oct 15 12:36:29 PM PDT 23 16232086251 ps
T416 /workspace/coverage/default/18.rom_ctrl_stress_all.1557722527 Oct 15 12:33:35 PM PDT 23 Oct 15 12:35:10 PM PDT 23 9624829407 ps
T417 /workspace/coverage/default/37.rom_ctrl_alert_test.2665417804 Oct 15 12:34:04 PM PDT 23 Oct 15 12:34:17 PM PDT 23 2782841290 ps
T418 /workspace/coverage/default/24.rom_ctrl_smoke.775055472 Oct 15 12:34:40 PM PDT 23 Oct 15 12:35:01 PM PDT 23 3184579030 ps
T419 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3383679438 Oct 15 12:34:15 PM PDT 23 Oct 15 12:41:38 PM PDT 23 80188275850 ps
T420 /workspace/coverage/default/21.rom_ctrl_smoke.2686598645 Oct 15 12:33:43 PM PDT 23 Oct 15 12:33:54 PM PDT 23 1633595967 ps
T421 /workspace/coverage/default/6.rom_ctrl_stress_all.1762481975 Oct 15 12:33:33 PM PDT 23 Oct 15 12:36:10 PM PDT 23 16248557679 ps
T422 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4015199569 Oct 15 12:34:09 PM PDT 23 Oct 15 12:35:59 PM PDT 23 11135037762 ps
T423 /workspace/coverage/default/41.rom_ctrl_smoke.3297529563 Oct 15 12:34:37 PM PDT 23 Oct 15 12:34:48 PM PDT 23 190186005 ps
T424 /workspace/coverage/default/45.rom_ctrl_alert_test.165179720 Oct 15 12:34:43 PM PDT 23 Oct 15 12:34:59 PM PDT 23 1532647768 ps
T425 /workspace/coverage/default/40.rom_ctrl_alert_test.1757988938 Oct 15 12:34:27 PM PDT 23 Oct 15 12:34:41 PM PDT 23 3815328701 ps
T426 /workspace/coverage/default/2.rom_ctrl_alert_test.3430644375 Oct 15 12:33:45 PM PDT 23 Oct 15 12:34:01 PM PDT 23 1936467523 ps
T427 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3741296518 Oct 15 12:33:43 PM PDT 23 Oct 15 12:36:29 PM PDT 23 6456665521 ps
T428 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1368596460 Oct 15 12:33:59 PM PDT 23 Oct 15 12:36:16 PM PDT 23 4149773413 ps
T429 /workspace/coverage/default/31.rom_ctrl_smoke.614731583 Oct 15 12:34:12 PM PDT 23 Oct 15 12:34:40 PM PDT 23 3726469365 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2347719488 Oct 15 12:30:46 PM PDT 23 Oct 15 12:30:57 PM PDT 23 1648823836 ps
T431 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3953787420 Oct 15 12:31:20 PM PDT 23 Oct 15 12:31:29 PM PDT 23 2514935941 ps
T102 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.700985085 Oct 15 12:31:01 PM PDT 23 Oct 15 12:31:17 PM PDT 23 3907740109 ps
T103 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1193347320 Oct 15 12:32:20 PM PDT 23 Oct 15 12:34:59 PM PDT 23 18183391306 ps
T432 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3461501185 Oct 15 12:32:26 PM PDT 23 Oct 15 12:33:15 PM PDT 23 7637712779 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2506687122 Oct 15 12:31:23 PM PDT 23 Oct 15 12:31:32 PM PDT 23 119674847 ps
T117 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1269990750 Oct 15 12:31:02 PM PDT 23 Oct 15 12:31:45 PM PDT 23 3956061332 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1220895190 Oct 15 12:31:34 PM PDT 23 Oct 15 12:31:45 PM PDT 23 9483153824 ps
T435 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.629514368 Oct 15 12:30:48 PM PDT 23 Oct 15 12:32:11 PM PDT 23 1846949050 ps
T436 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3399776073 Oct 15 12:30:53 PM PDT 23 Oct 15 12:30:59 PM PDT 23 499198052 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2549619620 Oct 15 12:30:37 PM PDT 23 Oct 15 12:30:49 PM PDT 23 3903602797 ps
T438 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4249287389 Oct 15 12:31:52 PM PDT 23 Oct 15 12:32:01 PM PDT 23 424902184 ps
T439 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3441498376 Oct 15 12:31:02 PM PDT 23 Oct 15 12:31:07 PM PDT 23 830226167 ps
T99 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4051072733 Oct 15 12:31:20 PM PDT 23 Oct 15 12:31:35 PM PDT 23 7466281250 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2395888304 Oct 15 12:32:06 PM PDT 23 Oct 15 12:32:20 PM PDT 23 6420412232 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3229874700 Oct 15 12:30:55 PM PDT 23 Oct 15 12:31:04 PM PDT 23 1634850923 ps
T442 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.636679532 Oct 15 12:31:19 PM PDT 23 Oct 15 12:31:24 PM PDT 23 86420266 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1981521777 Oct 15 12:30:55 PM PDT 23 Oct 15 12:31:06 PM PDT 23 4075314448 ps
T97 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.6144123 Oct 15 12:31:08 PM PDT 23 Oct 15 12:31:15 PM PDT 23 745673272 ps
T444 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3264176385 Oct 15 12:31:31 PM PDT 23 Oct 15 12:31:43 PM PDT 23 1862694512 ps
T118 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3190849613 Oct 15 12:31:06 PM PDT 23 Oct 15 12:31:46 PM PDT 23 619702904 ps
T445 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3779892362 Oct 15 12:32:22 PM PDT 23 Oct 15 12:32:35 PM PDT 23 4429808745 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1013921881 Oct 15 12:32:02 PM PDT 23 Oct 15 12:32:48 PM PDT 23 5891742925 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4220410326 Oct 15 12:30:49 PM PDT 23 Oct 15 12:30:54 PM PDT 23 87299627 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3666933440 Oct 15 12:30:45 PM PDT 23 Oct 15 12:32:05 PM PDT 23 2329654632 ps
T449 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.497926023 Oct 15 12:32:25 PM PDT 23 Oct 15 12:33:04 PM PDT 23 155018305 ps
T450 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1295717977 Oct 15 12:30:53 PM PDT 23 Oct 15 12:31:10 PM PDT 23 1381447103 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2634962836 Oct 15 12:31:22 PM PDT 23 Oct 15 12:31:36 PM PDT 23 577825703 ps
T452 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.592723600 Oct 15 12:32:25 PM PDT 23 Oct 15 12:32:33 PM PDT 23 348325841 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2115162700 Oct 15 12:31:07 PM PDT 23 Oct 15 12:31:12 PM PDT 23 88142296 ps
T454 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.121438160 Oct 15 12:31:06 PM PDT 23 Oct 15 12:31:21 PM PDT 23 3843972879 ps
T455 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2113427310 Oct 15 12:30:53 PM PDT 23 Oct 15 12:31:10 PM PDT 23 2288264592 ps
T456 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3666582226 Oct 15 12:31:17 PM PDT 23 Oct 15 12:31:23 PM PDT 23 434148836 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2936342396 Oct 15 12:31:43 PM PDT 23 Oct 15 12:34:07 PM PDT 23 13212818636 ps
T458 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2272478839 Oct 15 12:31:19 PM PDT 23 Oct 15 12:31:37 PM PDT 23 1923041478 ps
T459 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3263650310 Oct 15 12:32:14 PM PDT 23 Oct 15 12:32:22 PM PDT 23 542877304 ps
T460 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2482918021 Oct 15 12:31:12 PM PDT 23 Oct 15 12:31:21 PM PDT 23 1892848283 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1178291853 Oct 15 12:30:59 PM PDT 23 Oct 15 12:31:19 PM PDT 23 1902860087 ps
T462 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2738791770 Oct 15 12:31:02 PM PDT 23 Oct 15 12:33:59 PM PDT 23 43668954509 ps
T463 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2051447519 Oct 15 12:31:00 PM PDT 23 Oct 15 12:31:07 PM PDT 23 4137497703 ps
T464 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3659078023 Oct 15 12:30:56 PM PDT 23 Oct 15 12:31:11 PM PDT 23 3745755153 ps
T465 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2783283378 Oct 15 12:31:05 PM PDT 23 Oct 15 12:31:16 PM PDT 23 465971549 ps
T466 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3855756662 Oct 15 12:32:20 PM PDT 23 Oct 15 12:33:42 PM PDT 23 6775488430 ps
T100 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3425642138 Oct 15 12:32:12 PM PDT 23 Oct 15 12:34:18 PM PDT 23 50917187039 ps
T467 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3157618738 Oct 15 12:32:10 PM PDT 23 Oct 15 12:32:28 PM PDT 23 1658729992 ps
T468 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3823091403 Oct 15 12:31:16 PM PDT 23 Oct 15 12:32:02 PM PDT 23 5208180674 ps
T101 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.730292297 Oct 15 12:30:50 PM PDT 23 Oct 15 12:31:43 PM PDT 23 4056282092 ps
T469 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1508520621 Oct 15 12:30:59 PM PDT 23 Oct 15 12:31:14 PM PDT 23 2099473461 ps
T470 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2306335498 Oct 15 12:31:16 PM PDT 23 Oct 15 12:31:24 PM PDT 23 725898230 ps
T471 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4257250453 Oct 15 12:31:22 PM PDT 23 Oct 15 12:32:08 PM PDT 23 14316992677 ps
T472 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1223023073 Oct 15 12:31:25 PM PDT 23 Oct 15 12:33:50 PM PDT 23 65083721349 ps
T473 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2550741512 Oct 15 12:31:20 PM PDT 23 Oct 15 12:31:36 PM PDT 23 7690819713 ps
T474 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4177312303 Oct 15 12:32:44 PM PDT 23 Oct 15 12:32:52 PM PDT 23 378367156 ps
T475 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3466160617 Oct 15 12:30:52 PM PDT 23 Oct 15 12:34:51 PM PDT 23 75460724715 ps
T476 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.299088447 Oct 15 12:31:55 PM PDT 23 Oct 15 12:35:07 PM PDT 23 13329559285 ps
T477 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1215429510 Oct 15 12:30:47 PM PDT 23 Oct 15 12:31:02 PM PDT 23 1632474755 ps
T478 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3012964753 Oct 15 12:31:54 PM PDT 23 Oct 15 12:32:02 PM PDT 23 3143831145 ps
T479 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4002060935 Oct 15 12:30:56 PM PDT 23 Oct 15 12:31:02 PM PDT 23 88229688 ps
T480 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4118046266 Oct 15 12:30:46 PM PDT 23 Oct 15 12:31:00 PM PDT 23 6515360746 ps
T481 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3591735564 Oct 15 12:31:20 PM PDT 23 Oct 15 12:31:34 PM PDT 23 2173951417 ps
T482 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3240553890 Oct 15 12:31:04 PM PDT 23 Oct 15 12:31:14 PM PDT 23 930498659 ps
T483 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1100051176 Oct 15 12:31:04 PM PDT 23 Oct 15 12:31:19 PM PDT 23 2956317727 ps

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.805868494
Short name T22
Test name
Test status
Simulation time 7136719514 ps
CPU time 13.58 seconds
Started Oct 15 12:32:47 PM PDT 23
Finished Oct 15 12:33:02 PM PDT 23
Peak memory 217136 kb
Host smart-3f694c3d-43f8-448f-9b40-c2f60e11068a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805868494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.805868494
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.281466617
Short name T5
Test name
Test status
Simulation time 5350929951 ps
CPU time 35.3 seconds
Started Oct 15 12:33:59 PM PDT 23
Finished Oct 15 12:34:34 PM PDT 23
Peak memory 216440 kb
Host smart-480aa9b5-cf68-48b1-a247-bb13c5f168a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281466617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.rom_ctrl_stress_all.281466617
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3776586186
Short name T79
Test name
Test status
Simulation time 53649478166 ps
CPU time 144.63 seconds
Started Oct 15 12:31:23 PM PDT 23
Finished Oct 15 12:33:48 PM PDT 23
Peak memory 210780 kb
Host smart-62ec2e4e-06b5-4492-9926-38230b8eda7b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776586186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3776586186
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.705630827
Short name T77
Test name
Test status
Simulation time 167829393 ps
CPU time 7.76 seconds
Started Oct 15 12:30:53 PM PDT 23
Finished Oct 15 12:31:01 PM PDT 23
Peak memory 218824 kb
Host smart-25de64b4-2b5d-46ae-8b1b-7e1047862ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705630827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.705630827
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2976214310
Short name T69
Test name
Test status
Simulation time 521379848 ps
CPU time 76.7 seconds
Started Oct 15 12:31:21 PM PDT 23
Finished Oct 15 12:32:38 PM PDT 23
Peak memory 211092 kb
Host smart-d6d691b1-d90c-41be-87c6-da221cdea788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976214310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2976214310
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.526251868
Short name T12
Test name
Test status
Simulation time 78812688109 ps
CPU time 1405.35 seconds
Started Oct 15 12:33:52 PM PDT 23
Finished Oct 15 12:57:18 PM PDT 23
Peak memory 233128 kb
Host smart-d9f36418-521d-4782-83eb-ad43521d2a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526251868 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.526251868
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1635856400
Short name T20
Test name
Test status
Simulation time 48089281843 ps
CPU time 187.71 seconds
Started Oct 15 12:33:26 PM PDT 23
Finished Oct 15 12:36:35 PM PDT 23
Peak memory 224612 kb
Host smart-01b1736f-05a6-4cb8-b1b6-08b72e810d0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635856400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1635856400
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3096542656
Short name T66
Test name
Test status
Simulation time 225441812 ps
CPU time 6.76 seconds
Started Oct 15 12:30:47 PM PDT 23
Finished Oct 15 12:30:54 PM PDT 23
Peak memory 218860 kb
Host smart-7fd38749-a2da-4484-b14e-874b836b78b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096542656 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3096542656
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1269990750
Short name T117
Test name
Test status
Simulation time 3956061332 ps
CPU time 42.9 seconds
Started Oct 15 12:31:02 PM PDT 23
Finished Oct 15 12:31:45 PM PDT 23
Peak memory 218816 kb
Host smart-9d7bde51-079e-44c3-8f24-82741a316e89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269990750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1269990750
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2803231
Short name T40
Test name
Test status
Simulation time 24951056741 ps
CPU time 63.17 seconds
Started Oct 15 12:33:20 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 237476 kb
Host smart-748c62ab-f10b-4920-9edd-e50fe68c503b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2803231
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3805018676
Short name T43
Test name
Test status
Simulation time 45312968964 ps
CPU time 125.14 seconds
Started Oct 15 12:30:55 PM PDT 23
Finished Oct 15 12:33:00 PM PDT 23
Peak memory 210680 kb
Host smart-ad76fb87-dbb4-4298-a686-0e9984af58fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805018676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3805018676
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2696136638
Short name T18
Test name
Test status
Simulation time 324709017832 ps
CPU time 6410.79 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 02:21:03 PM PDT 23
Peak memory 242732 kb
Host smart-e76cf33b-8fae-4376-8c77-605f4cbf6812
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696136638 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2696136638
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1659492864
Short name T166
Test name
Test status
Simulation time 50386819460 ps
CPU time 183.13 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:36:49 PM PDT 23
Peak memory 212600 kb
Host smart-2af4dd23-ec46-47b8-8105-5b1de12bb265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659492864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1659492864
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1457025332
Short name T76
Test name
Test status
Simulation time 1312836662 ps
CPU time 14.04 seconds
Started Oct 15 12:31:27 PM PDT 23
Finished Oct 15 12:31:41 PM PDT 23
Peak memory 218836 kb
Host smart-762c204d-a786-4eb5-8711-34ea0903efb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457025332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1457025332
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.847957697
Short name T177
Test name
Test status
Simulation time 1176838698 ps
CPU time 16.83 seconds
Started Oct 15 12:33:20 PM PDT 23
Finished Oct 15 12:33:37 PM PDT 23
Peak memory 211168 kb
Host smart-501fa6af-161d-45b9-8c97-b234bde5b317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847957697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.847957697
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.774021585
Short name T34
Test name
Test status
Simulation time 347870412 ps
CPU time 9.7 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:33:51 PM PDT 23
Peak memory 211516 kb
Host smart-b2d32e1f-ae08-4011-8feb-1043cc08fa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774021585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.774021585
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1086317322
Short name T37
Test name
Test status
Simulation time 494481125 ps
CPU time 12.99 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:29 PM PDT 23
Peak memory 211208 kb
Host smart-ad3f5e0d-bee7-41e1-9bc0-4524040e28ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086317322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1086317322
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2831832439
Short name T78
Test name
Test status
Simulation time 1750580702 ps
CPU time 79.59 seconds
Started Oct 15 12:31:11 PM PDT 23
Finished Oct 15 12:32:36 PM PDT 23
Peak memory 218904 kb
Host smart-8c224f91-0309-4630-967f-23770e51e6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831832439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2831832439
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2408447917
Short name T71
Test name
Test status
Simulation time 5814867521 ps
CPU time 79.62 seconds
Started Oct 15 12:31:04 PM PDT 23
Finished Oct 15 12:32:24 PM PDT 23
Peak memory 218952 kb
Host smart-37059a8e-c525-44c3-8c30-787800be2c1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408447917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2408447917
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3499908472
Short name T42
Test name
Test status
Simulation time 1195899620 ps
CPU time 11.49 seconds
Started Oct 15 12:33:23 PM PDT 23
Finished Oct 15 12:33:35 PM PDT 23
Peak memory 210928 kb
Host smart-0f7ccc87-13a3-4aad-867d-2183c6f6add0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499908472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3499908472
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3196649810
Short name T149
Test name
Test status
Simulation time 272853257 ps
CPU time 6.23 seconds
Started Oct 15 12:31:32 PM PDT 23
Finished Oct 15 12:31:39 PM PDT 23
Peak memory 210704 kb
Host smart-52888b61-7fa9-4261-8db8-793f53c9b615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196649810 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3196649810
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.898303936
Short name T115
Test name
Test status
Simulation time 4974055809 ps
CPU time 47.94 seconds
Started Oct 15 12:31:14 PM PDT 23
Finished Oct 15 12:32:02 PM PDT 23
Peak memory 218972 kb
Host smart-0ce170ae-95dc-4c98-bf9a-6785e186fb7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898303936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.898303936
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2052345508
Short name T13
Test name
Test status
Simulation time 42982334284 ps
CPU time 1688.19 seconds
Started Oct 15 12:34:26 PM PDT 23
Finished Oct 15 01:02:35 PM PDT 23
Peak memory 243924 kb
Host smart-504c4ffb-cb08-4d43-961f-2fbb4242b40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052345508 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2052345508
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.979794196
Short name T129
Test name
Test status
Simulation time 2068766551 ps
CPU time 15.76 seconds
Started Oct 15 12:32:10 PM PDT 23
Finished Oct 15 12:32:26 PM PDT 23
Peak memory 216960 kb
Host smart-a24eeebe-81ac-4f30-bb47-baeb2a9c5459
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979794196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.979794196
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1775030403
Short name T142
Test name
Test status
Simulation time 1274145312 ps
CPU time 11.85 seconds
Started Oct 15 12:31:03 PM PDT 23
Finished Oct 15 12:31:15 PM PDT 23
Peak memory 210604 kb
Host smart-30835885-2071-4a37-ae25-f563fe1f05e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775030403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1775030403
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.4167612737
Short name T23
Test name
Test status
Simulation time 1773716170 ps
CPU time 11.11 seconds
Started Oct 15 12:32:39 PM PDT 23
Finished Oct 15 12:32:52 PM PDT 23
Peak memory 209932 kb
Host smart-f922982b-165c-4aed-93ed-e50b6fe6c1cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167612737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.4167612737
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2306335498
Short name T470
Test name
Test status
Simulation time 725898230 ps
CPU time 8.4 seconds
Started Oct 15 12:31:16 PM PDT 23
Finished Oct 15 12:31:24 PM PDT 23
Peak memory 210628 kb
Host smart-f186275d-2cac-4aa5-8e38-c741f165f08c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306335498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.2306335498
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3865448219
Short name T136
Test name
Test status
Simulation time 2214243308 ps
CPU time 16.48 seconds
Started Oct 15 12:32:01 PM PDT 23
Finished Oct 15 12:32:18 PM PDT 23
Peak memory 210744 kb
Host smart-67760ddb-813f-4038-a79c-340f3300617d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865448219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3865448219
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1688857834
Short name T127
Test name
Test status
Simulation time 5084159374 ps
CPU time 11.08 seconds
Started Oct 15 12:31:07 PM PDT 23
Finished Oct 15 12:31:18 PM PDT 23
Peak memory 210708 kb
Host smart-e4568239-0fdf-4bdc-9662-aa9a3af1cb90
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688857834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1688857834
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3850754231
Short name T84
Test name
Test status
Simulation time 5684352965 ps
CPU time 50.44 seconds
Started Oct 15 12:32:10 PM PDT 23
Finished Oct 15 12:33:01 PM PDT 23
Peak memory 210768 kb
Host smart-d6dd5570-8a3a-4309-a5dc-7180227c3be6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850754231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3850754231
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2622882514
Short name T145
Test name
Test status
Simulation time 88163504 ps
CPU time 4.3 seconds
Started Oct 15 12:30:59 PM PDT 23
Finished Oct 15 12:31:04 PM PDT 23
Peak memory 209928 kb
Host smart-4b81653e-f9b3-4aa5-a9f6-3a460f65fb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622882514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2622882514
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3240553890
Short name T482
Test name
Test status
Simulation time 930498659 ps
CPU time 9.52 seconds
Started Oct 15 12:31:04 PM PDT 23
Finished Oct 15 12:31:14 PM PDT 23
Peak memory 218828 kb
Host smart-0c26476a-873e-4387-9cfd-a304743571ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240553890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3240553890
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2582243072
Short name T135
Test name
Test status
Simulation time 6471906396 ps
CPU time 13.3 seconds
Started Oct 15 12:31:02 PM PDT 23
Finished Oct 15 12:31:16 PM PDT 23
Peak memory 217408 kb
Host smart-3a48a550-c365-49dd-9c19-c476477637ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582243072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2582243072
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.4058350648
Short name T106
Test name
Test status
Simulation time 85434916 ps
CPU time 4.75 seconds
Started Oct 15 12:30:57 PM PDT 23
Finished Oct 15 12:31:02 PM PDT 23
Peak memory 210708 kb
Host smart-a5f28266-755c-487a-9118-61a17dd99f4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058350648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.4058350648
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3284131468
Short name T141
Test name
Test status
Simulation time 344950223 ps
CPU time 7.17 seconds
Started Oct 15 12:31:02 PM PDT 23
Finished Oct 15 12:31:10 PM PDT 23
Peak memory 210720 kb
Host smart-77319b4b-4a80-4c3a-babf-58e3927be2fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284131468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3284131468
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3659078023
Short name T464
Test name
Test status
Simulation time 3745755153 ps
CPU time 14.61 seconds
Started Oct 15 12:30:56 PM PDT 23
Finished Oct 15 12:31:11 PM PDT 23
Peak memory 210772 kb
Host smart-da9ecfbe-0b08-4e5c-8cea-bd1610f2729a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659078023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3659078023
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3399776073
Short name T436
Test name
Test status
Simulation time 499198052 ps
CPU time 4.99 seconds
Started Oct 15 12:30:53 PM PDT 23
Finished Oct 15 12:30:59 PM PDT 23
Peak memory 210704 kb
Host smart-a9d95662-6dbb-40b7-809c-396130071f88
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399776073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3399776073
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3229874700
Short name T441
Test name
Test status
Simulation time 1634850923 ps
CPU time 9.49 seconds
Started Oct 15 12:30:55 PM PDT 23
Finished Oct 15 12:31:04 PM PDT 23
Peak memory 210736 kb
Host smart-8be90fb6-f9f3-4ada-b1a8-5fdd912da589
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229874700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3229874700
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2738791770
Short name T462
Test name
Test status
Simulation time 43668954509 ps
CPU time 177.02 seconds
Started Oct 15 12:31:02 PM PDT 23
Finished Oct 15 12:33:59 PM PDT 23
Peak memory 210692 kb
Host smart-e1ccc63b-4ab1-4e8f-8cf1-1789ef85473e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738791770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2738791770
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3396412793
Short name T91
Test name
Test status
Simulation time 86402099 ps
CPU time 4.42 seconds
Started Oct 15 12:31:23 PM PDT 23
Finished Oct 15 12:31:28 PM PDT 23
Peak memory 216640 kb
Host smart-b9d7ecf8-bb26-4629-800a-c03c35ee3cb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396412793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3396412793
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1117281695
Short name T120
Test name
Test status
Simulation time 906584632 ps
CPU time 11.82 seconds
Started Oct 15 12:30:38 PM PDT 23
Finished Oct 15 12:30:50 PM PDT 23
Peak memory 218960 kb
Host smart-37df3b3c-94b1-4a25-bd48-aed6f65f3af2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117281695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1117281695
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2066830040
Short name T26
Test name
Test status
Simulation time 8352529625 ps
CPU time 50.23 seconds
Started Oct 15 12:31:28 PM PDT 23
Finished Oct 15 12:32:19 PM PDT 23
Peak memory 212168 kb
Host smart-319f0875-b7d6-46a9-a8a4-b7939bec93c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066830040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2066830040
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3908797874
Short name T31
Test name
Test status
Simulation time 1561811492 ps
CPU time 13.12 seconds
Started Oct 15 12:33:16 PM PDT 23
Finished Oct 15 12:33:29 PM PDT 23
Peak memory 213412 kb
Host smart-7d00a7c0-8f42-41d8-94f4-e62e979a1a44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908797874 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3908797874
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2554675584
Short name T92
Test name
Test status
Simulation time 171911271 ps
CPU time 4.34 seconds
Started Oct 15 12:31:46 PM PDT 23
Finished Oct 15 12:31:51 PM PDT 23
Peak memory 216288 kb
Host smart-f595a767-9fc4-4630-85d8-05d2720e8b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554675584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2554675584
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3425642138
Short name T100
Test name
Test status
Simulation time 50917187039 ps
CPU time 124.96 seconds
Started Oct 15 12:32:12 PM PDT 23
Finished Oct 15 12:34:18 PM PDT 23
Peak memory 210784 kb
Host smart-c1a1ad2a-52de-4482-9d0b-fb7b75faf0bb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425642138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3425642138
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1674661598
Short name T105
Test name
Test status
Simulation time 828479715 ps
CPU time 4.48 seconds
Started Oct 15 12:31:34 PM PDT 23
Finished Oct 15 12:31:39 PM PDT 23
Peak memory 210628 kb
Host smart-94a9397f-65c8-43ed-a162-80023480ada6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674661598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.1674661598
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.629514368
Short name T435
Test name
Test status
Simulation time 1846949050 ps
CPU time 82.6 seconds
Started Oct 15 12:30:48 PM PDT 23
Finished Oct 15 12:32:11 PM PDT 23
Peak memory 210928 kb
Host smart-5ba02bd1-bc8b-4949-9c3f-9b172b4fad57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629514368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.629514368
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3666582226
Short name T456
Test name
Test status
Simulation time 434148836 ps
CPU time 5.81 seconds
Started Oct 15 12:31:17 PM PDT 23
Finished Oct 15 12:31:23 PM PDT 23
Peak memory 210800 kb
Host smart-079f7953-f05a-4cc7-948b-eaf5ebda743a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666582226 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3666582226
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4177312303
Short name T474
Test name
Test status
Simulation time 378367156 ps
CPU time 6.61 seconds
Started Oct 15 12:32:44 PM PDT 23
Finished Oct 15 12:32:52 PM PDT 23
Peak memory 210404 kb
Host smart-30f2e2fb-b800-41a3-aaa4-4e4d6c98dfbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177312303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4177312303
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2602251590
Short name T86
Test name
Test status
Simulation time 169130215546 ps
CPU time 378.08 seconds
Started Oct 15 12:31:31 PM PDT 23
Finished Oct 15 12:37:49 PM PDT 23
Peak memory 218932 kb
Host smart-8564b386-4457-42e5-b417-ae0ad4c3f59e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602251590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2602251590
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.889363195
Short name T104
Test name
Test status
Simulation time 997941817 ps
CPU time 11.92 seconds
Started Oct 15 12:30:56 PM PDT 23
Finished Oct 15 12:31:09 PM PDT 23
Peak memory 218672 kb
Host smart-28ae948a-2a75-46af-976c-c6e39ec66dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889363195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.889363195
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.4218060225
Short name T75
Test name
Test status
Simulation time 288704924 ps
CPU time 6.16 seconds
Started Oct 15 12:31:48 PM PDT 23
Finished Oct 15 12:31:54 PM PDT 23
Peak memory 218892 kb
Host smart-5d1c8371-c02f-4cae-9836-1ee6d206235d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218060225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.4218060225
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2152592910
Short name T29
Test name
Test status
Simulation time 9697918585 ps
CPU time 43.57 seconds
Started Oct 15 12:31:26 PM PDT 23
Finished Oct 15 12:32:10 PM PDT 23
Peak memory 212212 kb
Host smart-782b0ea7-ffab-4b9b-bd74-f0a155f942bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152592910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2152592910
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.2395888304
Short name T440
Test name
Test status
Simulation time 6420412232 ps
CPU time 13.66 seconds
Started Oct 15 12:32:06 PM PDT 23
Finished Oct 15 12:32:20 PM PDT 23
Peak memory 219036 kb
Host smart-db3c9fb6-414c-4beb-9f4b-306d1e1f6715
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395888304 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.2395888304
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2972335498
Short name T74
Test name
Test status
Simulation time 415011974 ps
CPU time 4.3 seconds
Started Oct 15 12:32:33 PM PDT 23
Finished Oct 15 12:32:38 PM PDT 23
Peak memory 210716 kb
Host smart-7b9beaef-1762-4521-b4bc-b6f943a17de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972335498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2972335498
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3431119910
Short name T88
Test name
Test status
Simulation time 8988401599 ps
CPU time 103.27 seconds
Started Oct 15 12:32:11 PM PDT 23
Finished Oct 15 12:33:54 PM PDT 23
Peak memory 210688 kb
Host smart-b607c7f6-2869-4c92-86a8-28ff19985d39
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431119910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3431119910
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2238469468
Short name T150
Test name
Test status
Simulation time 165507425 ps
CPU time 4.4 seconds
Started Oct 15 12:32:20 PM PDT 23
Finished Oct 15 12:32:30 PM PDT 23
Peak memory 210712 kb
Host smart-78e4fb52-5f10-45e8-b85e-80687eab6ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238469468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2238469468
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1826367893
Short name T125
Test name
Test status
Simulation time 3742891989 ps
CPU time 18.48 seconds
Started Oct 15 12:32:16 PM PDT 23
Finished Oct 15 12:32:35 PM PDT 23
Peak memory 218916 kb
Host smart-f8633ac2-e04c-407a-9d6c-60ebf74722a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826367893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1826367893
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3850858620
Short name T68
Test name
Test status
Simulation time 2742776881 ps
CPU time 76.73 seconds
Started Oct 15 12:31:03 PM PDT 23
Finished Oct 15 12:32:21 PM PDT 23
Peak memory 218848 kb
Host smart-095a7d81-1d68-415d-99a8-c74679f3a488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850858620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3850858620
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3858947457
Short name T80
Test name
Test status
Simulation time 973029036 ps
CPU time 6.18 seconds
Started Oct 15 12:32:15 PM PDT 23
Finished Oct 15 12:32:21 PM PDT 23
Peak memory 213684 kb
Host smart-9f7ce222-721c-47af-9006-1a63475aae7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858947457 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3858947457
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3263650310
Short name T459
Test name
Test status
Simulation time 542877304 ps
CPU time 7.67 seconds
Started Oct 15 12:32:14 PM PDT 23
Finished Oct 15 12:32:22 PM PDT 23
Peak memory 210704 kb
Host smart-1104e9d7-90c1-437a-8c5e-759a1386ac1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263650310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3263650310
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1193347320
Short name T103
Test name
Test status
Simulation time 18183391306 ps
CPU time 158.4 seconds
Started Oct 15 12:32:20 PM PDT 23
Finished Oct 15 12:34:59 PM PDT 23
Peak memory 218856 kb
Host smart-5df50c6a-aea3-444d-9bd7-efd10bf327d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193347320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1193347320
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.345139010
Short name T139
Test name
Test status
Simulation time 4123639394 ps
CPU time 14.57 seconds
Started Oct 15 12:32:15 PM PDT 23
Finished Oct 15 12:32:30 PM PDT 23
Peak memory 210680 kb
Host smart-422e672c-32ad-47c6-8ca9-fd7a798f83b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345139010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.345139010
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3157618738
Short name T467
Test name
Test status
Simulation time 1658729992 ps
CPU time 17.35 seconds
Started Oct 15 12:32:10 PM PDT 23
Finished Oct 15 12:32:28 PM PDT 23
Peak memory 218944 kb
Host smart-aafeab75-6971-4fd3-bb50-0d6a01835a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157618738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3157618738
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3461501185
Short name T432
Test name
Test status
Simulation time 7637712779 ps
CPU time 48.84 seconds
Started Oct 15 12:32:26 PM PDT 23
Finished Oct 15 12:33:15 PM PDT 23
Peak memory 212164 kb
Host smart-3832750d-13db-4070-a880-6005c4de1f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461501185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3461501185
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2128569266
Short name T126
Test name
Test status
Simulation time 97955557 ps
CPU time 5.13 seconds
Started Oct 15 12:31:19 PM PDT 23
Finished Oct 15 12:31:24 PM PDT 23
Peak memory 213604 kb
Host smart-15b008a4-473f-49bb-955d-f67b72b60608
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128569266 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2128569266
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1780539544
Short name T146
Test name
Test status
Simulation time 142744780 ps
CPU time 4.27 seconds
Started Oct 15 12:32:14 PM PDT 23
Finished Oct 15 12:32:18 PM PDT 23
Peak memory 210616 kb
Host smart-d70e6307-2d9e-448c-a5ca-faf6566908d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780539544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1780539544
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3466160617
Short name T475
Test name
Test status
Simulation time 75460724715 ps
CPU time 238.69 seconds
Started Oct 15 12:30:52 PM PDT 23
Finished Oct 15 12:34:51 PM PDT 23
Peak memory 210780 kb
Host smart-eb6fed2b-4e6b-4185-abde-fdb27734884b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466160617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3466160617
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2244240405
Short name T134
Test name
Test status
Simulation time 210527911 ps
CPU time 6.3 seconds
Started Oct 15 12:32:05 PM PDT 23
Finished Oct 15 12:32:12 PM PDT 23
Peak memory 217488 kb
Host smart-223b7f79-07bf-43d2-b747-285ebab5b380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244240405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2244240405
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2447330304
Short name T113
Test name
Test status
Simulation time 531633495 ps
CPU time 11.07 seconds
Started Oct 15 12:31:10 PM PDT 23
Finished Oct 15 12:31:26 PM PDT 23
Peak memory 218856 kb
Host smart-dc1eec80-688c-414b-a79b-ff1a959e6556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447330304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2447330304
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.497926023
Short name T449
Test name
Test status
Simulation time 155018305 ps
CPU time 39.08 seconds
Started Oct 15 12:32:25 PM PDT 23
Finished Oct 15 12:33:04 PM PDT 23
Peak memory 211976 kb
Host smart-286b43a5-d9b3-4756-ab53-9631003929c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497926023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.497926023
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3621500157
Short name T70
Test name
Test status
Simulation time 204506958 ps
CPU time 4.92 seconds
Started Oct 15 12:32:25 PM PDT 23
Finished Oct 15 12:32:31 PM PDT 23
Peak memory 213836 kb
Host smart-b3bd93a7-e555-4d26-a472-b1331c0115ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621500157 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3621500157
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3445241000
Short name T27
Test name
Test status
Simulation time 5945267196 ps
CPU time 12.79 seconds
Started Oct 15 12:30:35 PM PDT 23
Finished Oct 15 12:30:54 PM PDT 23
Peak memory 217612 kb
Host smart-d4d08869-b178-4e15-98c9-9d92ed908f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445241000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3445241000
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4023063618
Short name T25
Test name
Test status
Simulation time 10949526713 ps
CPU time 53.38 seconds
Started Oct 15 12:31:13 PM PDT 23
Finished Oct 15 12:32:07 PM PDT 23
Peak memory 210696 kb
Host smart-6747a663-c3ce-4c37-93cc-ed2095a822ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023063618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4023063618
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.464052035
Short name T133
Test name
Test status
Simulation time 12334970418 ps
CPU time 11.24 seconds
Started Oct 15 12:30:51 PM PDT 23
Finished Oct 15 12:31:08 PM PDT 23
Peak memory 210636 kb
Host smart-01b8e7e5-c0a5-4226-8d39-62f23e79799b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464052035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.464052035
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2113427310
Short name T455
Test name
Test status
Simulation time 2288264592 ps
CPU time 15.92 seconds
Started Oct 15 12:30:53 PM PDT 23
Finished Oct 15 12:31:10 PM PDT 23
Peak memory 218988 kb
Host smart-01d774a9-5f95-4cea-99b4-8ea8e4eaa81d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113427310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2113427310
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1013921881
Short name T446
Test name
Test status
Simulation time 5891742925 ps
CPU time 45.36 seconds
Started Oct 15 12:32:02 PM PDT 23
Finished Oct 15 12:32:48 PM PDT 23
Peak memory 212076 kb
Host smart-b3721f8b-b186-498f-9564-9e35e69141d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013921881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1013921881
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.296671820
Short name T83
Test name
Test status
Simulation time 811994268 ps
CPU time 9.07 seconds
Started Oct 15 12:31:50 PM PDT 23
Finished Oct 15 12:32:00 PM PDT 23
Peak memory 213092 kb
Host smart-9bd584c7-b8f4-44a1-b553-ead9f1436a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296671820 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.296671820
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.166295578
Short name T96
Test name
Test status
Simulation time 416246066 ps
CPU time 4.24 seconds
Started Oct 15 12:32:11 PM PDT 23
Finished Oct 15 12:32:16 PM PDT 23
Peak memory 216096 kb
Host smart-fb251372-6555-498f-8262-184e5b4c3300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166295578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.166295578
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.299088447
Short name T476
Test name
Test status
Simulation time 13329559285 ps
CPU time 190.82 seconds
Started Oct 15 12:31:55 PM PDT 23
Finished Oct 15 12:35:07 PM PDT 23
Peak memory 218832 kb
Host smart-e58345b9-009f-4e83-bb31-ae43d4867eba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299088447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.299088447
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2272478839
Short name T458
Test name
Test status
Simulation time 1923041478 ps
CPU time 17.01 seconds
Started Oct 15 12:31:19 PM PDT 23
Finished Oct 15 12:31:37 PM PDT 23
Peak memory 210652 kb
Host smart-da1fe534-03a5-4f81-9426-2c8764913f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272478839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2272478839
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3264176385
Short name T444
Test name
Test status
Simulation time 1862694512 ps
CPU time 12.26 seconds
Started Oct 15 12:31:31 PM PDT 23
Finished Oct 15 12:31:43 PM PDT 23
Peak memory 218936 kb
Host smart-b83c8bd8-e4b5-4188-b7f7-0877b0573db8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264176385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3264176385
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.4257250453
Short name T471
Test name
Test status
Simulation time 14316992677 ps
CPU time 44.76 seconds
Started Oct 15 12:31:22 PM PDT 23
Finished Oct 15 12:32:08 PM PDT 23
Peak memory 212276 kb
Host smart-448fd922-7949-438e-99fb-7036df5f4048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257250453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.4257250453
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3953787420
Short name T431
Test name
Test status
Simulation time 2514935941 ps
CPU time 8.88 seconds
Started Oct 15 12:31:20 PM PDT 23
Finished Oct 15 12:31:29 PM PDT 23
Peak memory 218892 kb
Host smart-60de81d9-8ec6-4be0-a66d-c327cf87923d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953787420 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3953787420
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2115162700
Short name T453
Test name
Test status
Simulation time 88142296 ps
CPU time 4.36 seconds
Started Oct 15 12:31:07 PM PDT 23
Finished Oct 15 12:31:12 PM PDT 23
Peak memory 210700 kb
Host smart-34796e4a-68ac-4825-aa88-15565f2d677b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115162700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2115162700
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2020892264
Short name T85
Test name
Test status
Simulation time 74041460991 ps
CPU time 187.28 seconds
Started Oct 15 12:31:01 PM PDT 23
Finished Oct 15 12:34:09 PM PDT 23
Peak memory 210736 kb
Host smart-d3375549-bb61-495f-9d9a-6eee24155e84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020892264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2020892264
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.729814338
Short name T143
Test name
Test status
Simulation time 1020910185 ps
CPU time 10.85 seconds
Started Oct 15 12:31:21 PM PDT 23
Finished Oct 15 12:31:33 PM PDT 23
Peak memory 210708 kb
Host smart-4b4723c3-f6be-4691-a4f0-eadc009bde44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729814338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.729814338
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2760258808
Short name T124
Test name
Test status
Simulation time 503906192 ps
CPU time 9.81 seconds
Started Oct 15 12:30:43 PM PDT 23
Finished Oct 15 12:30:53 PM PDT 23
Peak memory 218840 kb
Host smart-523bdef8-58ea-4b8c-b5cf-a17ed23f529b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760258808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2760258808
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3753185098
Short name T72
Test name
Test status
Simulation time 4292893328 ps
CPU time 42.14 seconds
Started Oct 15 12:32:17 PM PDT 23
Finished Oct 15 12:33:00 PM PDT 23
Peak memory 211876 kb
Host smart-8ffecca9-16c5-4047-bfec-cab3e72cd6f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753185098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3753185098
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.1523170287
Short name T147
Test name
Test status
Simulation time 19204700546 ps
CPU time 12.69 seconds
Started Oct 15 12:30:38 PM PDT 23
Finished Oct 15 12:30:56 PM PDT 23
Peak memory 213248 kb
Host smart-13238199-a357-42d1-b5df-fc93d062bd39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523170287 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.1523170287
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1899291678
Short name T94
Test name
Test status
Simulation time 4135459600 ps
CPU time 16.09 seconds
Started Oct 15 12:32:19 PM PDT 23
Finished Oct 15 12:32:36 PM PDT 23
Peak memory 210756 kb
Host smart-4771e7a8-f163-4a39-9616-7b51616bc233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899291678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1899291678
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1628964052
Short name T95
Test name
Test status
Simulation time 52049369130 ps
CPU time 176.81 seconds
Started Oct 15 12:32:22 PM PDT 23
Finished Oct 15 12:35:19 PM PDT 23
Peak memory 210780 kb
Host smart-56d88f92-109a-46fa-b718-0b78e393668f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628964052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1628964052
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2634962836
Short name T451
Test name
Test status
Simulation time 577825703 ps
CPU time 7.9 seconds
Started Oct 15 12:31:22 PM PDT 23
Finished Oct 15 12:31:36 PM PDT 23
Peak memory 216132 kb
Host smart-3fcbfa07-9821-46b9-aec3-a86cfb358963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634962836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2634962836
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.592723600
Short name T452
Test name
Test status
Simulation time 348325841 ps
CPU time 6.77 seconds
Started Oct 15 12:32:25 PM PDT 23
Finished Oct 15 12:32:33 PM PDT 23
Peak memory 218916 kb
Host smart-1b33b181-bfd5-4d86-9c0e-9b363b50e444
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592723600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.592723600
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.636679532
Short name T442
Test name
Test status
Simulation time 86420266 ps
CPU time 4.58 seconds
Started Oct 15 12:31:19 PM PDT 23
Finished Oct 15 12:31:24 PM PDT 23
Peak memory 210852 kb
Host smart-3b56c610-1fea-4b91-9792-0bb06dda498e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636679532 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.636679532
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2419021097
Short name T28
Test name
Test status
Simulation time 423957533 ps
CPU time 6.91 seconds
Started Oct 15 12:31:26 PM PDT 23
Finished Oct 15 12:31:34 PM PDT 23
Peak memory 210620 kb
Host smart-0b6485a1-817c-41b8-b8c0-0a46d61ec28c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419021097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2419021097
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1223023073
Short name T472
Test name
Test status
Simulation time 65083721349 ps
CPU time 144.56 seconds
Started Oct 15 12:31:25 PM PDT 23
Finished Oct 15 12:33:50 PM PDT 23
Peak memory 210800 kb
Host smart-49f133f6-97ff-436d-a54b-44d286d0543e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223023073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1223023073
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1100051176
Short name T483
Test name
Test status
Simulation time 2956317727 ps
CPU time 14.52 seconds
Started Oct 15 12:31:04 PM PDT 23
Finished Oct 15 12:31:19 PM PDT 23
Peak memory 218712 kb
Host smart-d45df6fc-704d-4faf-97e2-3c264a44384b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100051176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1100051176
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.4249287389
Short name T438
Test name
Test status
Simulation time 424902184 ps
CPU time 7.82 seconds
Started Oct 15 12:31:52 PM PDT 23
Finished Oct 15 12:32:01 PM PDT 23
Peak memory 218836 kb
Host smart-923cfb8b-58c8-4cfd-b813-a2f9cd03f3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249287389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.4249287389
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.4051072733
Short name T99
Test name
Test status
Simulation time 7466281250 ps
CPU time 14.67 seconds
Started Oct 15 12:31:20 PM PDT 23
Finished Oct 15 12:31:35 PM PDT 23
Peak memory 210696 kb
Host smart-d7ea7da9-5294-4f6a-bf27-485ac0f7067c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051072733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.4051072733
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.4220410326
Short name T447
Test name
Test status
Simulation time 87299627 ps
CPU time 4.52 seconds
Started Oct 15 12:30:49 PM PDT 23
Finished Oct 15 12:30:54 PM PDT 23
Peak memory 215580 kb
Host smart-efb0b5ee-122a-4a37-b056-a3c4d358b2e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220410326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.4220410326
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1508520621
Short name T469
Test name
Test status
Simulation time 2099473461 ps
CPU time 13.83 seconds
Started Oct 15 12:30:59 PM PDT 23
Finished Oct 15 12:31:14 PM PDT 23
Peak memory 218064 kb
Host smart-48685a30-1693-4e9e-b902-5ec0127bbd86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508520621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1508520621
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3276720642
Short name T81
Test name
Test status
Simulation time 4030590214 ps
CPU time 15.86 seconds
Started Oct 15 12:31:18 PM PDT 23
Finished Oct 15 12:31:34 PM PDT 23
Peak memory 214644 kb
Host smart-ebb963b6-5341-4183-804c-d421af15e7fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276720642 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3276720642
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2482918021
Short name T460
Test name
Test status
Simulation time 1892848283 ps
CPU time 8.92 seconds
Started Oct 15 12:31:12 PM PDT 23
Finished Oct 15 12:31:21 PM PDT 23
Peak memory 210628 kb
Host smart-b1763c3d-d5d2-4b47-9729-17065c98f1f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482918021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2482918021
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1981521777
Short name T443
Test name
Test status
Simulation time 4075314448 ps
CPU time 10.81 seconds
Started Oct 15 12:30:55 PM PDT 23
Finished Oct 15 12:31:06 PM PDT 23
Peak memory 210776 kb
Host smart-0f3f410e-12e6-4139-8386-25c39eb22328
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981521777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1981521777
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4030523263
Short name T73
Test name
Test status
Simulation time 4166399901 ps
CPU time 15.79 seconds
Started Oct 15 12:32:16 PM PDT 23
Finished Oct 15 12:32:32 PM PDT 23
Peak memory 210696 kb
Host smart-ef7113c6-7c47-46b1-8c58-bad24d8d2687
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030523263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4030523263
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1335540317
Short name T98
Test name
Test status
Simulation time 43882464890 ps
CPU time 331.35 seconds
Started Oct 15 12:31:47 PM PDT 23
Finished Oct 15 12:37:19 PM PDT 23
Peak memory 218760 kb
Host smart-1984c0d9-f955-4541-988f-8e066549e4ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335540317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1335540317
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3779892362
Short name T445
Test name
Test status
Simulation time 4429808745 ps
CPU time 12.39 seconds
Started Oct 15 12:32:22 PM PDT 23
Finished Oct 15 12:32:35 PM PDT 23
Peak memory 218184 kb
Host smart-38728a34-ab2e-4121-a2fc-52ae131ccb94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779892362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3779892362
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4002060935
Short name T479
Test name
Test status
Simulation time 88229688 ps
CPU time 6.25 seconds
Started Oct 15 12:30:56 PM PDT 23
Finished Oct 15 12:31:02 PM PDT 23
Peak memory 212708 kb
Host smart-fd43892b-81cd-4acb-b381-c45cb417df0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002060935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4002060935
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3823091403
Short name T468
Test name
Test status
Simulation time 5208180674 ps
CPU time 45.5 seconds
Started Oct 15 12:31:16 PM PDT 23
Finished Oct 15 12:32:02 PM PDT 23
Peak memory 218924 kb
Host smart-bbb1f623-741c-4683-8324-d31e8b28d97c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823091403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3823091403
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.6144123
Short name T97
Test name
Test status
Simulation time 745673272 ps
CPU time 6.71 seconds
Started Oct 15 12:31:08 PM PDT 23
Finished Oct 15 12:31:15 PM PDT 23
Peak memory 210600 kb
Host smart-bd24f3ee-fa19-440c-8015-50e9fb142d92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6144123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasin
g.6144123
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1738111039
Short name T140
Test name
Test status
Simulation time 1278342389 ps
CPU time 11.97 seconds
Started Oct 15 12:31:56 PM PDT 23
Finished Oct 15 12:32:09 PM PDT 23
Peak memory 210632 kb
Host smart-4eb43193-a7b0-4753-89cb-d303bbef77ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738111039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1738111039
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2549619620
Short name T437
Test name
Test status
Simulation time 3903602797 ps
CPU time 11.53 seconds
Started Oct 15 12:30:37 PM PDT 23
Finished Oct 15 12:30:49 PM PDT 23
Peak memory 210672 kb
Host smart-ccb7ed1c-4f10-49b4-a14f-79307aea8cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549619620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2549619620
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2945560487
Short name T114
Test name
Test status
Simulation time 8013559774 ps
CPU time 12.86 seconds
Started Oct 15 12:31:11 PM PDT 23
Finished Oct 15 12:31:24 PM PDT 23
Peak memory 218952 kb
Host smart-2b28fe8a-208e-4f17-a1f2-02c481880150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945560487 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2945560487
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1216267424
Short name T132
Test name
Test status
Simulation time 6503935552 ps
CPU time 14.81 seconds
Started Oct 15 12:30:31 PM PDT 23
Finished Oct 15 12:30:47 PM PDT 23
Peak memory 217356 kb
Host smart-7c65e660-b593-4a9e-83d4-f09bff3d7d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216267424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1216267424
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2926186602
Short name T128
Test name
Test status
Simulation time 674499981 ps
CPU time 8.13 seconds
Started Oct 15 12:32:59 PM PDT 23
Finished Oct 15 12:33:07 PM PDT 23
Peak memory 210636 kb
Host smart-67d1dbe7-d18f-4291-8a7b-e6b68f17be87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926186602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2926186602
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.4118046266
Short name T480
Test name
Test status
Simulation time 6515360746 ps
CPU time 13.87 seconds
Started Oct 15 12:30:46 PM PDT 23
Finished Oct 15 12:31:00 PM PDT 23
Peak memory 210796 kb
Host smart-8266e4a4-a35e-4b92-971d-5573741eadc9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118046266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.4118046266
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.730292297
Short name T101
Test name
Test status
Simulation time 4056282092 ps
CPU time 52.35 seconds
Started Oct 15 12:30:50 PM PDT 23
Finished Oct 15 12:31:43 PM PDT 23
Peak memory 210780 kb
Host smart-15d090a6-8240-48bc-aacd-b316fc3acac2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730292297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.730292297
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.121438160
Short name T454
Test name
Test status
Simulation time 3843972879 ps
CPU time 14.68 seconds
Started Oct 15 12:31:06 PM PDT 23
Finished Oct 15 12:31:21 PM PDT 23
Peak memory 217248 kb
Host smart-eba5ee64-3471-4dc5-9feb-a5172793c26e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121438160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.121438160
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1003513096
Short name T112
Test name
Test status
Simulation time 4727825895 ps
CPU time 15.14 seconds
Started Oct 15 12:32:09 PM PDT 23
Finished Oct 15 12:32:25 PM PDT 23
Peak memory 218912 kb
Host smart-3166671c-5d33-4d19-b0a6-b3dba9916743
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003513096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1003513096
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3606335632
Short name T137
Test name
Test status
Simulation time 1725162622 ps
CPU time 14.12 seconds
Started Oct 15 12:31:35 PM PDT 23
Finished Oct 15 12:31:50 PM PDT 23
Peak memory 210720 kb
Host smart-c03cba7b-0f44-469d-af15-345a4be18d0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606335632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3606335632
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3591735564
Short name T481
Test name
Test status
Simulation time 2173951417 ps
CPU time 13.94 seconds
Started Oct 15 12:31:20 PM PDT 23
Finished Oct 15 12:31:34 PM PDT 23
Peak memory 210696 kb
Host smart-f4b9c38b-7058-4d69-bfc8-d9015ee0d9f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591735564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3591735564
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1244451221
Short name T123
Test name
Test status
Simulation time 1482420052 ps
CPU time 13.6 seconds
Started Oct 15 12:31:27 PM PDT 23
Finished Oct 15 12:31:41 PM PDT 23
Peak memory 213840 kb
Host smart-9356513e-4cca-4f77-bd77-430e7949c94b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244451221 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1244451221
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1188859515
Short name T144
Test name
Test status
Simulation time 977963947 ps
CPU time 10.02 seconds
Started Oct 15 12:31:01 PM PDT 23
Finished Oct 15 12:31:12 PM PDT 23
Peak memory 217116 kb
Host smart-ed7af6b4-c974-41a4-a5a9-3fd7a268432a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188859515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1188859515
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2924206170
Short name T130
Test name
Test status
Simulation time 3670932674 ps
CPU time 10.14 seconds
Started Oct 15 12:30:55 PM PDT 23
Finished Oct 15 12:31:05 PM PDT 23
Peak memory 210656 kb
Host smart-11898210-b0f5-4ee7-8c6c-5cd5e9b9ad56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924206170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2924206170
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2051447519
Short name T463
Test name
Test status
Simulation time 4137497703 ps
CPU time 6.31 seconds
Started Oct 15 12:31:00 PM PDT 23
Finished Oct 15 12:31:07 PM PDT 23
Peak memory 210692 kb
Host smart-8d7bb7c5-74fe-48be-9f91-267c2911887f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051447519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2051447519
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.205420922
Short name T89
Test name
Test status
Simulation time 10892015374 ps
CPU time 117.77 seconds
Started Oct 15 12:31:29 PM PDT 23
Finished Oct 15 12:33:27 PM PDT 23
Peak memory 218956 kb
Host smart-1bda1e2e-1da8-4d6b-85f3-29bdb7b0892e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205420922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.205420922
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1220895190
Short name T434
Test name
Test status
Simulation time 9483153824 ps
CPU time 10.18 seconds
Started Oct 15 12:31:34 PM PDT 23
Finished Oct 15 12:31:45 PM PDT 23
Peak memory 217832 kb
Host smart-0233c7f6-162a-42e2-9bac-8a15821dee3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220895190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1220895190
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1178291853
Short name T461
Test name
Test status
Simulation time 1902860087 ps
CPU time 19.35 seconds
Started Oct 15 12:30:59 PM PDT 23
Finished Oct 15 12:31:19 PM PDT 23
Peak memory 213476 kb
Host smart-e77e2735-78fe-4666-89ee-c848c9e28810
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178291853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1178291853
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3190849613
Short name T118
Test name
Test status
Simulation time 619702904 ps
CPU time 39.54 seconds
Started Oct 15 12:31:06 PM PDT 23
Finished Oct 15 12:31:46 PM PDT 23
Peak memory 218888 kb
Host smart-894f6eea-8ab7-4e43-ac84-80b71d1c20ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190849613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3190849613
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2783283378
Short name T465
Test name
Test status
Simulation time 465971549 ps
CPU time 5.77 seconds
Started Oct 15 12:31:05 PM PDT 23
Finished Oct 15 12:31:16 PM PDT 23
Peak memory 212516 kb
Host smart-5ff7a2c7-85ff-440d-99f8-1e4043232e4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783283378 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2783283378
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.700985085
Short name T102
Test name
Test status
Simulation time 3907740109 ps
CPU time 15.4 seconds
Started Oct 15 12:31:01 PM PDT 23
Finished Oct 15 12:31:17 PM PDT 23
Peak memory 217040 kb
Host smart-f6d81c48-c423-43af-9363-6169f29cfb40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700985085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.700985085
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3292386349
Short name T30
Test name
Test status
Simulation time 3104907556 ps
CPU time 10.76 seconds
Started Oct 15 12:30:57 PM PDT 23
Finished Oct 15 12:31:08 PM PDT 23
Peak memory 210804 kb
Host smart-3edc79d5-aa13-4283-88b8-b16916a5f2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292386349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3292386349
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3658770766
Short name T121
Test name
Test status
Simulation time 6684503030 ps
CPU time 16.82 seconds
Started Oct 15 12:31:26 PM PDT 23
Finished Oct 15 12:31:43 PM PDT 23
Peak memory 218932 kb
Host smart-ed7f214b-1bc3-4286-998f-e4de8bcf774a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658770766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3658770766
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3666933440
Short name T448
Test name
Test status
Simulation time 2329654632 ps
CPU time 79.64 seconds
Started Oct 15 12:30:45 PM PDT 23
Finished Oct 15 12:32:05 PM PDT 23
Peak memory 210912 kb
Host smart-46d81609-7e28-41c1-ab9f-588dd9a3c1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666933440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3666933440
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1215429510
Short name T477
Test name
Test status
Simulation time 1632474755 ps
CPU time 14.42 seconds
Started Oct 15 12:30:47 PM PDT 23
Finished Oct 15 12:31:02 PM PDT 23
Peak memory 218848 kb
Host smart-947e2db1-4deb-46db-adab-28c4aeb862cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215429510 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1215429510
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3012964753
Short name T478
Test name
Test status
Simulation time 3143831145 ps
CPU time 7.66 seconds
Started Oct 15 12:31:54 PM PDT 23
Finished Oct 15 12:32:02 PM PDT 23
Peak memory 215900 kb
Host smart-5637a8e2-06c1-4741-b266-6416b6803ed2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012964753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3012964753
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3441498376
Short name T439
Test name
Test status
Simulation time 830226167 ps
CPU time 4.19 seconds
Started Oct 15 12:31:02 PM PDT 23
Finished Oct 15 12:31:07 PM PDT 23
Peak memory 210600 kb
Host smart-f5edfaee-5a65-4da0-85c3-8e95e4b6a266
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441498376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3441498376
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1295717977
Short name T450
Test name
Test status
Simulation time 1381447103 ps
CPU time 15.96 seconds
Started Oct 15 12:30:53 PM PDT 23
Finished Oct 15 12:31:10 PM PDT 23
Peak memory 218936 kb
Host smart-1ad66792-4655-43bc-9da5-8b75b8b94d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295717977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1295717977
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2347719488
Short name T430
Test name
Test status
Simulation time 1648823836 ps
CPU time 10.06 seconds
Started Oct 15 12:30:46 PM PDT 23
Finished Oct 15 12:30:57 PM PDT 23
Peak memory 213636 kb
Host smart-613d808b-9345-4c5e-8797-e47ecf214b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347719488 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2347719488
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1385583519
Short name T93
Test name
Test status
Simulation time 89276128 ps
CPU time 4.33 seconds
Started Oct 15 12:32:58 PM PDT 23
Finished Oct 15 12:33:03 PM PDT 23
Peak memory 210636 kb
Host smart-00747961-16d9-4524-8f67-cc6adc476443
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385583519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1385583519
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2779707053
Short name T87
Test name
Test status
Simulation time 6604230606 ps
CPU time 71.74 seconds
Started Oct 15 12:31:17 PM PDT 23
Finished Oct 15 12:32:29 PM PDT 23
Peak memory 210796 kb
Host smart-85b0fe93-6b73-4908-8e16-22cbf81056c3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779707053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2779707053
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2067758754
Short name T148
Test name
Test status
Simulation time 9175162557 ps
CPU time 16.62 seconds
Started Oct 15 12:31:54 PM PDT 23
Finished Oct 15 12:32:16 PM PDT 23
Peak memory 210684 kb
Host smart-7d2ff349-1b9c-444d-8ba5-757095be5000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067758754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2067758754
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3496751599
Short name T116
Test name
Test status
Simulation time 3947072442 ps
CPU time 79.61 seconds
Started Oct 15 12:31:23 PM PDT 23
Finished Oct 15 12:32:43 PM PDT 23
Peak memory 218972 kb
Host smart-68d07783-2977-4172-b866-2e73f0e5434a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496751599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3496751599
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.566009132
Short name T67
Test name
Test status
Simulation time 1676157618 ps
CPU time 13.87 seconds
Started Oct 15 12:31:23 PM PDT 23
Finished Oct 15 12:31:37 PM PDT 23
Peak memory 218832 kb
Host smart-4a667562-00e6-46de-8d4a-81ef486d0861
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566009132 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.566009132
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2550741512
Short name T473
Test name
Test status
Simulation time 7690819713 ps
CPU time 15.39 seconds
Started Oct 15 12:31:20 PM PDT 23
Finished Oct 15 12:31:36 PM PDT 23
Peak memory 217624 kb
Host smart-5f843671-d3cb-4b93-8bb4-1b0e660a0862
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550741512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2550741512
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2936342396
Short name T457
Test name
Test status
Simulation time 13212818636 ps
CPU time 142.74 seconds
Started Oct 15 12:31:43 PM PDT 23
Finished Oct 15 12:34:07 PM PDT 23
Peak memory 218920 kb
Host smart-111e93e7-25ad-49fd-9203-c7881f9e94b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936342396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2936342396
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.496530798
Short name T90
Test name
Test status
Simulation time 3281523633 ps
CPU time 9.53 seconds
Started Oct 15 12:31:11 PM PDT 23
Finished Oct 15 12:31:21 PM PDT 23
Peak memory 216560 kb
Host smart-982c1c80-80d8-475c-8912-92c04912965c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496530798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ct
rl_same_csr_outstanding.496530798
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1351483848
Short name T82
Test name
Test status
Simulation time 1116938727 ps
CPU time 13.47 seconds
Started Oct 15 12:31:50 PM PDT 23
Finished Oct 15 12:32:04 PM PDT 23
Peak memory 218980 kb
Host smart-30266a31-3d35-4a3a-aa8f-4c4529e4e18a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351483848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1351483848
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3855756662
Short name T466
Test name
Test status
Simulation time 6775488430 ps
CPU time 82.13 seconds
Started Oct 15 12:32:20 PM PDT 23
Finished Oct 15 12:33:42 PM PDT 23
Peak memory 211308 kb
Host smart-5a6b24d5-c757-4342-b160-232b7f720277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855756662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3855756662
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1390046089
Short name T122
Test name
Test status
Simulation time 2852778942 ps
CPU time 16.3 seconds
Started Oct 15 12:32:43 PM PDT 23
Finished Oct 15 12:33:00 PM PDT 23
Peak memory 218892 kb
Host smart-41a81111-8e80-4b91-a014-b49fbe004e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390046089 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1390046089
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1074536957
Short name T138
Test name
Test status
Simulation time 3943093370 ps
CPU time 10.18 seconds
Started Oct 15 12:33:19 PM PDT 23
Finished Oct 15 12:33:29 PM PDT 23
Peak memory 216148 kb
Host smart-4f9130fb-a3ee-44c6-967a-bfb1349af227
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074536957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1074536957
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2386113945
Short name T24
Test name
Test status
Simulation time 2733856792 ps
CPU time 117.14 seconds
Started Oct 15 12:31:44 PM PDT 23
Finished Oct 15 12:33:42 PM PDT 23
Peak memory 218780 kb
Host smart-55c84ab8-43ca-4c18-b3c2-37e557facec3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386113945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2386113945
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.925018627
Short name T131
Test name
Test status
Simulation time 2566194676 ps
CPU time 15.87 seconds
Started Oct 15 12:32:18 PM PDT 23
Finished Oct 15 12:32:34 PM PDT 23
Peak memory 210744 kb
Host smart-b4c91f14-9237-4621-a3f8-346cbf7244c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925018627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.925018627
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2506687122
Short name T433
Test name
Test status
Simulation time 119674847 ps
CPU time 8.49 seconds
Started Oct 15 12:31:23 PM PDT 23
Finished Oct 15 12:31:32 PM PDT 23
Peak memory 218880 kb
Host smart-b9593a92-d1d5-4fce-a7bf-10325e18fa66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506687122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.2506687122
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3238102943
Short name T119
Test name
Test status
Simulation time 1511851669 ps
CPU time 79.81 seconds
Started Oct 15 12:31:49 PM PDT 23
Finished Oct 15 12:33:09 PM PDT 23
Peak memory 211036 kb
Host smart-85e7808c-1193-4eb3-99c5-82641f675b8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238102943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3238102943
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.791429007
Short name T193
Test name
Test status
Simulation time 28028176100 ps
CPU time 204.34 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:37:37 PM PDT 23
Peak memory 236600 kb
Host smart-ad833567-a393-4207-ae6a-41da8dbec38a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791429007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.791429007
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.304450192
Short name T376
Test name
Test status
Simulation time 23518183685 ps
CPU time 31.98 seconds
Started Oct 15 12:33:47 PM PDT 23
Finished Oct 15 12:34:20 PM PDT 23
Peak memory 211472 kb
Host smart-b966e8b7-f246-42b7-a691-6c98c744938c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304450192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.304450192
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3630495578
Short name T21
Test name
Test status
Simulation time 225209210 ps
CPU time 5.54 seconds
Started Oct 15 12:33:56 PM PDT 23
Finished Oct 15 12:34:02 PM PDT 23
Peak memory 210924 kb
Host smart-e455bde8-6cee-44e3-8d03-2c380d4b4755
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630495578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3630495578
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.292932673
Short name T38
Test name
Test status
Simulation time 378403997 ps
CPU time 109.49 seconds
Started Oct 15 12:33:16 PM PDT 23
Finished Oct 15 12:35:06 PM PDT 23
Peak memory 236336 kb
Host smart-72a02022-cfe8-4577-9b62-a11fefbf452c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292932673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.292932673
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1247285737
Short name T390
Test name
Test status
Simulation time 11984375438 ps
CPU time 25.98 seconds
Started Oct 15 12:33:19 PM PDT 23
Finished Oct 15 12:33:46 PM PDT 23
Peak memory 213556 kb
Host smart-301f9874-9a57-4a15-b572-52a1be8b878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247285737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1247285737
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.840355664
Short name T197
Test name
Test status
Simulation time 2215993006 ps
CPU time 28.38 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:34:02 PM PDT 23
Peak memory 213548 kb
Host smart-26b99847-62cb-4adb-9bef-a57304bfa15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840355664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.840355664
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3991078195
Short name T301
Test name
Test status
Simulation time 90076915 ps
CPU time 4.42 seconds
Started Oct 15 12:33:21 PM PDT 23
Finished Oct 15 12:33:26 PM PDT 23
Peak memory 210964 kb
Host smart-4081a313-324d-40d7-bfa2-624893360311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991078195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3991078195
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2660447325
Short name T250
Test name
Test status
Simulation time 36990067732 ps
CPU time 228.46 seconds
Started Oct 15 12:33:40 PM PDT 23
Finished Oct 15 12:37:29 PM PDT 23
Peak memory 224392 kb
Host smart-4fca2fb2-1c65-4590-8430-14d74244cde0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660447325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2660447325
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2977929949
Short name T316
Test name
Test status
Simulation time 23254318851 ps
CPU time 19.03 seconds
Started Oct 15 12:33:15 PM PDT 23
Finished Oct 15 12:33:35 PM PDT 23
Peak memory 211072 kb
Host smart-4114c713-c44e-4770-a04f-5ee8f92ac2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977929949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2977929949
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1972994535
Short name T289
Test name
Test status
Simulation time 428139874 ps
CPU time 8.03 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:34:04 PM PDT 23
Peak memory 210676 kb
Host smart-97979cfd-e174-4cf5-a752-6cafb13867c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972994535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1972994535
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3072457187
Short name T300
Test name
Test status
Simulation time 184765234 ps
CPU time 10.17 seconds
Started Oct 15 12:33:24 PM PDT 23
Finished Oct 15 12:33:35 PM PDT 23
Peak memory 210932 kb
Host smart-828768c5-8137-4d79-bb7a-76b87f2dcdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072457187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3072457187
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.452911789
Short name T270
Test name
Test status
Simulation time 80928559866 ps
CPU time 89.94 seconds
Started Oct 15 12:33:26 PM PDT 23
Finished Oct 15 12:34:56 PM PDT 23
Peak memory 219300 kb
Host smart-5fc7e84a-ae7d-4453-9f1d-6dab3da91703
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452911789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.452911789
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1671784992
Short name T304
Test name
Test status
Simulation time 85511136 ps
CPU time 4.35 seconds
Started Oct 15 12:33:21 PM PDT 23
Finished Oct 15 12:33:26 PM PDT 23
Peak memory 210964 kb
Host smart-8a6dd0f7-5360-4cac-88d7-bd113c15d436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671784992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1671784992
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3285069665
Short name T224
Test name
Test status
Simulation time 111283946127 ps
CPU time 341.9 seconds
Started Oct 15 12:33:47 PM PDT 23
Finished Oct 15 12:39:29 PM PDT 23
Peak memory 236804 kb
Host smart-f029cfb4-52b4-4ddb-a64f-01c9108da135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285069665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3285069665
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3718009995
Short name T303
Test name
Test status
Simulation time 2891869061 ps
CPU time 26.4 seconds
Started Oct 15 12:33:22 PM PDT 23
Finished Oct 15 12:33:49 PM PDT 23
Peak memory 211116 kb
Host smart-0fec19ce-9691-441d-ab2f-ea814a87a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718009995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3718009995
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.607933876
Short name T212
Test name
Test status
Simulation time 713561895 ps
CPU time 9.31 seconds
Started Oct 15 12:34:11 PM PDT 23
Finished Oct 15 12:34:25 PM PDT 23
Peak memory 210960 kb
Host smart-fdf43272-95fb-4805-8caf-c19c979d16da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=607933876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.607933876
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1046049071
Short name T50
Test name
Test status
Simulation time 13411681833 ps
CPU time 36.33 seconds
Started Oct 15 12:33:24 PM PDT 23
Finished Oct 15 12:34:01 PM PDT 23
Peak memory 213132 kb
Host smart-229e4ec2-1f3c-47ef-baf7-5ec70a3d4651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046049071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1046049071
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3591299959
Short name T255
Test name
Test status
Simulation time 9336084341 ps
CPU time 28.77 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:34:02 PM PDT 23
Peak memory 213464 kb
Host smart-823a0d63-59cd-4505-910e-d9f8a0b6a399
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591299959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3591299959
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.520709931
Short name T181
Test name
Test status
Simulation time 36129830329 ps
CPU time 1346.79 seconds
Started Oct 15 12:33:50 PM PDT 23
Finished Oct 15 12:56:17 PM PDT 23
Peak memory 233516 kb
Host smart-fbbe5ebe-b7c2-4335-b129-49a2f468b2da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520709931 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.520709931
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.233546195
Short name T397
Test name
Test status
Simulation time 2071220883 ps
CPU time 16.97 seconds
Started Oct 15 12:33:42 PM PDT 23
Finished Oct 15 12:33:59 PM PDT 23
Peak memory 211028 kb
Host smart-10d91864-d907-45bf-8fe8-7f4837f14256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233546195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.233546195
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.697729840
Short name T383
Test name
Test status
Simulation time 121657572532 ps
CPU time 333.27 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:39:38 PM PDT 23
Peak memory 237652 kb
Host smart-cef7bcfb-55b6-48e7-bc0d-a49039a335c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697729840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.697729840
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1448117626
Short name T295
Test name
Test status
Simulation time 14516210893 ps
CPU time 20.87 seconds
Started Oct 15 12:33:57 PM PDT 23
Finished Oct 15 12:34:18 PM PDT 23
Peak memory 211444 kb
Host smart-bdf5895f-b652-42fd-9bdc-c23c467691d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448117626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1448117626
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2660003525
Short name T370
Test name
Test status
Simulation time 7167635263 ps
CPU time 15.7 seconds
Started Oct 15 12:33:14 PM PDT 23
Finished Oct 15 12:33:30 PM PDT 23
Peak memory 211072 kb
Host smart-20b990c5-ab72-4a70-b1ca-000f81589f3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660003525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2660003525
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2916675527
Short name T379
Test name
Test status
Simulation time 2191773245 ps
CPU time 10.34 seconds
Started Oct 15 12:33:30 PM PDT 23
Finished Oct 15 12:33:41 PM PDT 23
Peak memory 212692 kb
Host smart-e007253c-01d1-43dc-ba09-8104b82d6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916675527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2916675527
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2897616248
Short name T162
Test name
Test status
Simulation time 4502324367 ps
CPU time 49.29 seconds
Started Oct 15 12:33:57 PM PDT 23
Finished Oct 15 12:34:47 PM PDT 23
Peak memory 215860 kb
Host smart-b2796aed-729b-44a1-a8e3-d446d0741762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897616248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2897616248
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4286339598
Short name T296
Test name
Test status
Simulation time 58888522834 ps
CPU time 716.16 seconds
Started Oct 15 12:33:46 PM PDT 23
Finished Oct 15 12:45:42 PM PDT 23
Peak memory 234376 kb
Host smart-234b6956-fdbf-4f85-ad2a-c48edd1b2aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286339598 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.4286339598
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1314342306
Short name T174
Test name
Test status
Simulation time 4249954103 ps
CPU time 17.02 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:34:41 PM PDT 23
Peak memory 211124 kb
Host smart-545b894e-f370-42b8-9d23-04e1b28a6892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314342306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1314342306
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3856615464
Short name T223
Test name
Test status
Simulation time 1350105603 ps
CPU time 13.13 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:33:59 PM PDT 23
Peak memory 210884 kb
Host smart-746cbe4a-b938-4b7f-9977-16a0ccaaab5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856615464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3856615464
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1164289240
Short name T307
Test name
Test status
Simulation time 711612329 ps
CPU time 10.01 seconds
Started Oct 15 12:33:36 PM PDT 23
Finished Oct 15 12:33:46 PM PDT 23
Peak memory 212432 kb
Host smart-85c3f60a-cbbd-4a1b-9000-514bed441558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164289240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1164289240
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3877539466
Short name T356
Test name
Test status
Simulation time 33038757784 ps
CPU time 83.09 seconds
Started Oct 15 12:33:22 PM PDT 23
Finished Oct 15 12:34:45 PM PDT 23
Peak memory 219328 kb
Host smart-9a1f6dfd-988b-4e62-ab09-23d8344f3783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877539466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3877539466
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.774451673
Short name T170
Test name
Test status
Simulation time 30161733590 ps
CPU time 14.9 seconds
Started Oct 15 12:33:30 PM PDT 23
Finished Oct 15 12:33:45 PM PDT 23
Peak memory 211048 kb
Host smart-8e215c0c-0102-41f2-ad84-deca7eaea22b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774451673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.774451673
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2261362497
Short name T328
Test name
Test status
Simulation time 19386648202 ps
CPU time 214.2 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:37:28 PM PDT 23
Peak memory 228484 kb
Host smart-263c40f9-17b3-4eb1-8533-8c058267bd12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261362497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2261362497
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1188121137
Short name T294
Test name
Test status
Simulation time 7852508007 ps
CPU time 16.8 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:34:29 PM PDT 23
Peak memory 211128 kb
Host smart-5c6d04b3-5e3f-4d67-95f2-0143912dcab6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188121137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1188121137
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2893812596
Short name T246
Test name
Test status
Simulation time 1251178640 ps
CPU time 17.61 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:33:59 PM PDT 23
Peak memory 213016 kb
Host smart-5ed231ee-98e2-4389-8323-8ddebc2014d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893812596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2893812596
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3633190232
Short name T182
Test name
Test status
Simulation time 590125487 ps
CPU time 15.94 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:34:09 PM PDT 23
Peak memory 214220 kb
Host smart-992377b6-5a46-47eb-a870-4680cbf14a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633190232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3633190232
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2996924720
Short name T386
Test name
Test status
Simulation time 256632146 ps
CPU time 6.12 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:34:07 PM PDT 23
Peak memory 210880 kb
Host smart-0fe90ca4-c69e-4550-802c-bf32dc2e06d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996924720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2996924720
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3739977171
Short name T59
Test name
Test status
Simulation time 44665653420 ps
CPU time 416.62 seconds
Started Oct 15 12:33:25 PM PDT 23
Finished Oct 15 12:40:22 PM PDT 23
Peak memory 237012 kb
Host smart-802e799c-405d-4580-a2af-40127f195efe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739977171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3739977171
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.477072551
Short name T157
Test name
Test status
Simulation time 677666347 ps
CPU time 14.39 seconds
Started Oct 15 12:33:22 PM PDT 23
Finished Oct 15 12:33:36 PM PDT 23
Peak memory 211020 kb
Host smart-c435f02a-9e04-4a91-a9c8-af932142da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477072551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.477072551
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2494324004
Short name T167
Test name
Test status
Simulation time 2706567083 ps
CPU time 11.56 seconds
Started Oct 15 12:33:26 PM PDT 23
Finished Oct 15 12:33:43 PM PDT 23
Peak memory 211028 kb
Host smart-7073ce05-d6c7-4fbe-a02f-8359b66cebe0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494324004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2494324004
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4077887774
Short name T241
Test name
Test status
Simulation time 13466069347 ps
CPU time 30.43 seconds
Started Oct 15 12:33:42 PM PDT 23
Finished Oct 15 12:34:13 PM PDT 23
Peak memory 213064 kb
Host smart-91b652c8-37dd-47f0-af13-144fd436edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077887774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4077887774
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.941132085
Short name T110
Test name
Test status
Simulation time 16721029412 ps
CPU time 122.62 seconds
Started Oct 15 12:33:31 PM PDT 23
Finished Oct 15 12:35:34 PM PDT 23
Peak memory 219332 kb
Host smart-c088b370-f5e4-4cf6-a194-cbbc44155e86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941132085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.941132085
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2547047567
Short name T173
Test name
Test status
Simulation time 347033770 ps
CPU time 4.2 seconds
Started Oct 15 12:33:31 PM PDT 23
Finished Oct 15 12:33:36 PM PDT 23
Peak memory 210924 kb
Host smart-7c105656-9608-4452-afea-9173910a2b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547047567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2547047567
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2413868961
Short name T54
Test name
Test status
Simulation time 13922651096 ps
CPU time 165.73 seconds
Started Oct 15 12:33:49 PM PDT 23
Finished Oct 15 12:36:35 PM PDT 23
Peak memory 236648 kb
Host smart-93d0ef0f-8ade-4665-b1b2-5e0fc31694fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413868961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2413868961
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1080355849
Short name T355
Test name
Test status
Simulation time 6321920627 ps
CPU time 27.26 seconds
Started Oct 15 12:33:37 PM PDT 23
Finished Oct 15 12:34:05 PM PDT 23
Peak memory 211796 kb
Host smart-6b3e9c83-435a-42eb-b9a8-8ef6e52b66e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080355849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1080355849
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3675457275
Short name T213
Test name
Test status
Simulation time 1574011110 ps
CPU time 14.22 seconds
Started Oct 15 12:33:23 PM PDT 23
Finished Oct 15 12:33:38 PM PDT 23
Peak memory 210952 kb
Host smart-6ff02bd6-cb05-42ec-9ec9-0aa1e7a97fd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3675457275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3675457275
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3771670252
Short name T227
Test name
Test status
Simulation time 5970671866 ps
CPU time 21.7 seconds
Started Oct 15 12:33:58 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 213400 kb
Host smart-9982c2ba-867a-4e3e-8afe-9226a18ececa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771670252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3771670252
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2358124601
Short name T339
Test name
Test status
Simulation time 30421445935 ps
CPU time 65.33 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:35:00 PM PDT 23
Peak memory 216668 kb
Host smart-c13002ea-88ff-4381-97d1-373c22a12538
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358124601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2358124601
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.582862938
Short name T344
Test name
Test status
Simulation time 35655170012 ps
CPU time 525.65 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:42:31 PM PDT 23
Peak memory 227568 kb
Host smart-a89dc1eb-54f5-4c7d-8f48-611ad087b2f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582862938 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.582862938
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1634505978
Short name T65
Test name
Test status
Simulation time 461642989 ps
CPU time 4.31 seconds
Started Oct 15 12:33:40 PM PDT 23
Finished Oct 15 12:33:45 PM PDT 23
Peak memory 210944 kb
Host smart-1f5bad5d-549a-4c39-bab2-171efc43b8e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634505978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1634505978
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1225902233
Short name T262
Test name
Test status
Simulation time 81522788038 ps
CPU time 205.87 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:37:21 PM PDT 23
Peak memory 228376 kb
Host smart-af13c2f6-56ba-4b64-a697-55400e4e8e24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225902233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1225902233
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1759933506
Short name T384
Test name
Test status
Simulation time 347452756 ps
CPU time 9.42 seconds
Started Oct 15 12:33:46 PM PDT 23
Finished Oct 15 12:33:55 PM PDT 23
Peak memory 211052 kb
Host smart-3b3c6138-f6b9-4e3f-b6c5-da2b975426d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759933506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1759933506
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1616534366
Short name T374
Test name
Test status
Simulation time 1735539786 ps
CPU time 15.29 seconds
Started Oct 15 12:33:52 PM PDT 23
Finished Oct 15 12:34:08 PM PDT 23
Peak memory 210900 kb
Host smart-5968ecb9-1d99-4431-abfa-74ebdf6b5fa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616534366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1616534366
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1791728130
Short name T184
Test name
Test status
Simulation time 4343001311 ps
CPU time 17.39 seconds
Started Oct 15 12:33:42 PM PDT 23
Finished Oct 15 12:34:00 PM PDT 23
Peak memory 212492 kb
Host smart-a5165f3a-738e-49dd-a731-fd54a79da478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791728130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1791728130
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3753780878
Short name T254
Test name
Test status
Simulation time 102254155089 ps
CPU time 73.94 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:35:09 PM PDT 23
Peak memory 215696 kb
Host smart-5bee7ad6-7e78-44c0-a760-6fcbc9b8ef5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753780878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3753780878
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3905375834
Short name T236
Test name
Test status
Simulation time 27434117741 ps
CPU time 1388.17 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:57:13 PM PDT 23
Peak memory 235688 kb
Host smart-fb8e987b-7b99-459b-95b0-309f8b8d1c04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905375834 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3905375834
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.642829475
Short name T402
Test name
Test status
Simulation time 8691517211 ps
CPU time 16.49 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:34:08 PM PDT 23
Peak memory 211152 kb
Host smart-ea3d3eee-db9c-4998-b2a5-804e0ee16bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642829475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.642829475
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3006163182
Short name T58
Test name
Test status
Simulation time 39527480851 ps
CPU time 160.69 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:36:32 PM PDT 23
Peak memory 231508 kb
Host smart-b3346973-59e3-425b-8b99-8a0bcee81989
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006163182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.3006163182
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.323085995
Short name T198
Test name
Test status
Simulation time 18803933320 ps
CPU time 31.63 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:34:13 PM PDT 23
Peak memory 211376 kb
Host smart-c08af4b8-d600-46a8-8cab-94afc979a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323085995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.323085995
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3575399013
Short name T393
Test name
Test status
Simulation time 1943604899 ps
CPU time 16.66 seconds
Started Oct 15 12:33:43 PM PDT 23
Finished Oct 15 12:34:00 PM PDT 23
Peak memory 210928 kb
Host smart-c72d7bdc-b8fd-4320-84e5-d43fee775074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575399013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3575399013
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.632061507
Short name T248
Test name
Test status
Simulation time 15079672809 ps
CPU time 31.55 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:34:05 PM PDT 23
Peak memory 212844 kb
Host smart-a865596f-9aea-4a1a-b14b-8e55420f5def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632061507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.632061507
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.618870775
Short name T155
Test name
Test status
Simulation time 2355268456 ps
CPU time 17.73 seconds
Started Oct 15 12:33:42 PM PDT 23
Finished Oct 15 12:34:01 PM PDT 23
Peak memory 213000 kb
Host smart-72234cb5-1d44-48b4-a5bc-24d7a0da775e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618870775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.618870775
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.342187152
Short name T208
Test name
Test status
Simulation time 297325031 ps
CPU time 4.17 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:33:58 PM PDT 23
Peak memory 210928 kb
Host smart-17e72cef-da53-4c1f-8c32-053c83a7e134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342187152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.342187152
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2927616476
Short name T385
Test name
Test status
Simulation time 35150183842 ps
CPU time 339.79 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:39:44 PM PDT 23
Peak memory 228432 kb
Host smart-696d6d91-d11c-4fb2-9e9f-f0cb6bfa9ba7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927616476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2927616476
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.990233460
Short name T158
Test name
Test status
Simulation time 1802280577 ps
CPU time 20.39 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:34:13 PM PDT 23
Peak memory 211044 kb
Host smart-95ee3a8c-2e4d-4cf7-8f9d-226d6b058e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990233460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.990233460
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1085474474
Short name T179
Test name
Test status
Simulation time 2008942520 ps
CPU time 16.37 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:34:01 PM PDT 23
Peak memory 210996 kb
Host smart-d99270f9-6af0-4700-83a1-db107b97caea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1085474474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1085474474
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.371812509
Short name T156
Test name
Test status
Simulation time 2623405655 ps
CPU time 29.47 seconds
Started Oct 15 12:34:25 PM PDT 23
Finished Oct 15 12:34:55 PM PDT 23
Peak memory 212300 kb
Host smart-1cbb791e-2357-4a88-9264-2cefe1012f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371812509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.371812509
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.1557722527
Short name T416
Test name
Test status
Simulation time 9624829407 ps
CPU time 94.8 seconds
Started Oct 15 12:33:35 PM PDT 23
Finished Oct 15 12:35:10 PM PDT 23
Peak memory 216792 kb
Host smart-b1519e62-8b32-4b47-af76-92d506b886d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557722527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.1557722527
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.12470138
Short name T341
Test name
Test status
Simulation time 72449203693 ps
CPU time 1292.37 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:55:43 PM PDT 23
Peak memory 235680 kb
Host smart-213c660e-f29a-48c6-9898-3a94c371ba73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470138 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.12470138
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1257893513
Short name T363
Test name
Test status
Simulation time 334406259 ps
CPU time 4.32 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:33:58 PM PDT 23
Peak memory 210972 kb
Host smart-8cb391b7-5d18-4574-9562-0d9c14b3371c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257893513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1257893513
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1265642959
Short name T380
Test name
Test status
Simulation time 7706368758 ps
CPU time 129.24 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:36:02 PM PDT 23
Peak memory 228092 kb
Host smart-ef675f56-7734-4cb1-bacc-3421ad315f59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265642959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1265642959
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4269781130
Short name T183
Test name
Test status
Simulation time 927211524 ps
CPU time 15.22 seconds
Started Oct 15 12:33:39 PM PDT 23
Finished Oct 15 12:33:55 PM PDT 23
Peak memory 211252 kb
Host smart-19025043-0d78-4c8a-a9ab-d3975f22216b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269781130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4269781130
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.27660863
Short name T47
Test name
Test status
Simulation time 1570886709 ps
CPU time 7.58 seconds
Started Oct 15 12:33:40 PM PDT 23
Finished Oct 15 12:33:49 PM PDT 23
Peak memory 210948 kb
Host smart-80a7cd55-4c4e-4eaf-b8d2-bc1e6a1f1edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27660863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.27660863
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1405372321
Short name T205
Test name
Test status
Simulation time 15720642083 ps
CPU time 31.96 seconds
Started Oct 15 12:34:00 PM PDT 23
Finished Oct 15 12:34:32 PM PDT 23
Peak memory 213436 kb
Host smart-5e57670d-e65f-4083-9b64-baf407284509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405372321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1405372321
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4203967104
Short name T194
Test name
Test status
Simulation time 11783802033 ps
CPU time 58.25 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:35:13 PM PDT 23
Peak memory 214020 kb
Host smart-4049a31c-64a8-4259-80db-5e8f0842fe56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203967104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4203967104
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.566107642
Short name T16
Test name
Test status
Simulation time 37806112057 ps
CPU time 590.76 seconds
Started Oct 15 12:33:47 PM PDT 23
Finished Oct 15 12:43:38 PM PDT 23
Peak memory 232284 kb
Host smart-a4da21d3-c596-4e0d-923d-34e0f0b858cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566107642 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.566107642
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3430644375
Short name T426
Test name
Test status
Simulation time 1936467523 ps
CPU time 15.65 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:34:01 PM PDT 23
Peak memory 210952 kb
Host smart-a3f43448-d322-401d-9698-32e0a5dfec67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430644375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3430644375
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3741296518
Short name T427
Test name
Test status
Simulation time 6456665521 ps
CPU time 165.66 seconds
Started Oct 15 12:33:43 PM PDT 23
Finished Oct 15 12:36:29 PM PDT 23
Peak memory 237744 kb
Host smart-4cf4e968-875c-4383-85e7-8cd61953720d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741296518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3741296518
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3906513956
Short name T368
Test name
Test status
Simulation time 6497930348 ps
CPU time 19 seconds
Started Oct 15 12:33:44 PM PDT 23
Finished Oct 15 12:34:04 PM PDT 23
Peak memory 211996 kb
Host smart-e8673b98-a228-4748-998d-66ddefeff6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906513956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3906513956
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1449470773
Short name T188
Test name
Test status
Simulation time 2144777757 ps
CPU time 16.83 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:33:50 PM PDT 23
Peak memory 210960 kb
Host smart-b6bdae2f-e35e-4999-9551-b3329b5fd3df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1449470773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1449470773
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.1212365002
Short name T39
Test name
Test status
Simulation time 652933669 ps
CPU time 110.81 seconds
Started Oct 15 12:33:26 PM PDT 23
Finished Oct 15 12:35:17 PM PDT 23
Peak memory 236648 kb
Host smart-fb1eee15-3867-4ee4-9e57-d22f000465db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212365002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1212365002
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1705175429
Short name T291
Test name
Test status
Simulation time 10229868958 ps
CPU time 23.58 seconds
Started Oct 15 12:34:03 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 213444 kb
Host smart-78711eba-96a9-462f-acdc-f4d419f205ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705175429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1705175429
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2364438287
Short name T215
Test name
Test status
Simulation time 10318740900 ps
CPU time 49.92 seconds
Started Oct 15 12:33:36 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 214992 kb
Host smart-42e5e3f0-4968-4a60-b9e0-999d90b98c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364438287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2364438287
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2576150243
Short name T288
Test name
Test status
Simulation time 77326847993 ps
CPU time 847.83 seconds
Started Oct 15 12:33:30 PM PDT 23
Finished Oct 15 12:47:38 PM PDT 23
Peak memory 234372 kb
Host smart-fac5ef72-1d5d-4607-9626-3079f33516cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576150243 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2576150243
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3349534805
Short name T163
Test name
Test status
Simulation time 346940602 ps
CPU time 4.32 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 210988 kb
Host smart-78499ac5-71ad-46bf-b930-fd0be54b0c0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349534805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3349534805
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4063188821
Short name T19
Test name
Test status
Simulation time 112296001773 ps
CPU time 138.06 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:36:35 PM PDT 23
Peak memory 236628 kb
Host smart-65ee3afd-fe9a-4958-adb8-d4da1138410a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063188821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4063188821
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.7985781
Short name T237
Test name
Test status
Simulation time 16293814738 ps
CPU time 32 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:34:33 PM PDT 23
Peak memory 211804 kb
Host smart-51c81829-6980-4937-b051-cc62e3835448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7985781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.7985781
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2966136470
Short name T238
Test name
Test status
Simulation time 3488854259 ps
CPU time 10.87 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:34:05 PM PDT 23
Peak memory 211076 kb
Host smart-778ec853-b00b-467a-be7b-5369835ec3e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966136470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2966136470
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2876227740
Short name T8
Test name
Test status
Simulation time 6557997032 ps
CPU time 19.19 seconds
Started Oct 15 12:34:03 PM PDT 23
Finished Oct 15 12:34:22 PM PDT 23
Peak memory 213380 kb
Host smart-244788ed-6a77-4684-8a4b-a190c192b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876227740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2876227740
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2386900858
Short name T258
Test name
Test status
Simulation time 9295480595 ps
CPU time 22.94 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:34:25 PM PDT 23
Peak memory 214676 kb
Host smart-ab852246-d57c-4bf1-bf3f-59e6301234ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386900858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2386900858
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1713511160
Short name T324
Test name
Test status
Simulation time 12564451211 ps
CPU time 14.99 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:34:09 PM PDT 23
Peak memory 211052 kb
Host smart-255e0404-ee2a-41a3-a5ec-47ac20a7e083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713511160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1713511160
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2533439423
Short name T55
Test name
Test status
Simulation time 37923200452 ps
CPU time 197.24 seconds
Started Oct 15 12:33:58 PM PDT 23
Finished Oct 15 12:37:16 PM PDT 23
Peak memory 224848 kb
Host smart-cdb75acf-acd3-4802-98b7-ddf06615190e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533439423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2533439423
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.123892236
Short name T204
Test name
Test status
Simulation time 10791889820 ps
CPU time 25.95 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 211480 kb
Host smart-09b170ee-3586-43f7-9466-51237edd0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123892236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.123892236
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4169297226
Short name T234
Test name
Test status
Simulation time 2707187932 ps
CPU time 9.43 seconds
Started Oct 15 12:34:26 PM PDT 23
Finished Oct 15 12:34:35 PM PDT 23
Peak memory 211060 kb
Host smart-a8c47c5a-03fa-4dde-9d61-24ac1d138c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169297226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4169297226
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2686598645
Short name T420
Test name
Test status
Simulation time 1633595967 ps
CPU time 10.15 seconds
Started Oct 15 12:33:43 PM PDT 23
Finished Oct 15 12:33:54 PM PDT 23
Peak memory 210944 kb
Host smart-54b0b09e-591d-4a88-98c2-ee51076dd3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686598645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2686598645
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2992247727
Short name T371
Test name
Test status
Simulation time 13796262698 ps
CPU time 46.1 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 12:35:00 PM PDT 23
Peak memory 216468 kb
Host smart-b4627367-5b5e-47fa-ac30-dd6ea73bf821
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992247727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2992247727
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3693036741
Short name T266
Test name
Test status
Simulation time 865290133 ps
CPU time 5.59 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:33:51 PM PDT 23
Peak memory 210932 kb
Host smart-43eba7f1-04ec-4932-bd1b-b85f2780ed9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693036741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3693036741
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.991715745
Short name T281
Test name
Test status
Simulation time 58209028400 ps
CPU time 174.25 seconds
Started Oct 15 12:33:35 PM PDT 23
Finished Oct 15 12:36:30 PM PDT 23
Peak memory 233676 kb
Host smart-209fffd7-26f0-4337-9f59-5db4e878ef90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991715745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.991715745
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1218421944
Short name T331
Test name
Test status
Simulation time 2540465582 ps
CPU time 24.86 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 211228 kb
Host smart-0a92abf0-ba72-4311-8e2c-55353fa1b94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218421944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1218421944
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2879417835
Short name T342
Test name
Test status
Simulation time 2460231189 ps
CPU time 12.27 seconds
Started Oct 15 12:33:34 PM PDT 23
Finished Oct 15 12:33:47 PM PDT 23
Peak memory 211116 kb
Host smart-8e18c911-77d1-46e2-a8fa-f09576769332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879417835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2879417835
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2677762941
Short name T244
Test name
Test status
Simulation time 367737084 ps
CPU time 10.09 seconds
Started Oct 15 12:33:47 PM PDT 23
Finished Oct 15 12:33:58 PM PDT 23
Peak memory 213944 kb
Host smart-815e79d5-f52a-4d2c-bfde-9fb8c60389bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677762941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2677762941
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.422046528
Short name T253
Test name
Test status
Simulation time 3449829339 ps
CPU time 31.52 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:34:51 PM PDT 23
Peak memory 212552 kb
Host smart-c0032a72-e24e-451e-be85-92edb036b9c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422046528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.422046528
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2927985476
Short name T308
Test name
Test status
Simulation time 1600332032 ps
CPU time 13.38 seconds
Started Oct 15 12:33:58 PM PDT 23
Finished Oct 15 12:34:11 PM PDT 23
Peak memory 210936 kb
Host smart-0db8125c-4da9-482b-bb8b-2a947741f3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927985476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2927985476
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.623714592
Short name T408
Test name
Test status
Simulation time 60692921810 ps
CPU time 319.08 seconds
Started Oct 15 12:33:50 PM PDT 23
Finished Oct 15 12:39:10 PM PDT 23
Peak memory 228556 kb
Host smart-822b363e-2b7d-45d4-8cdd-88e0d5c2f3f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623714592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.623714592
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2319992461
Short name T317
Test name
Test status
Simulation time 31739940359 ps
CPU time 24.7 seconds
Started Oct 15 12:33:58 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 211556 kb
Host smart-48ea54a7-4b43-4d63-bb91-7099bbad9fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319992461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2319992461
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2362518939
Short name T164
Test name
Test status
Simulation time 36436747481 ps
CPU time 17.58 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:34:09 PM PDT 23
Peak memory 211104 kb
Host smart-ff3f9775-5f30-4e24-bc8c-b20af6f4c2ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2362518939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2362518939
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1941889953
Short name T302
Test name
Test status
Simulation time 374266867 ps
CPU time 9.75 seconds
Started Oct 15 12:34:09 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 212844 kb
Host smart-f6189a71-654d-46b7-badb-67755038dae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941889953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1941889953
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.1288476267
Short name T335
Test name
Test status
Simulation time 23990232526 ps
CPU time 1717.18 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 01:02:48 PM PDT 23
Peak memory 227588 kb
Host smart-f79ffeef-5d9c-4744-9618-8c40ee595570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288476267 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.1288476267
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1394667322
Short name T256
Test name
Test status
Simulation time 1073245601 ps
CPU time 10.67 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:34:25 PM PDT 23
Peak memory 211004 kb
Host smart-baa0e1e0-cd4a-4a2f-9523-17db7269ff0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394667322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1394667322
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.502867377
Short name T36
Test name
Test status
Simulation time 348876841367 ps
CPU time 454.87 seconds
Started Oct 15 12:34:17 PM PDT 23
Finished Oct 15 12:41:52 PM PDT 23
Peak memory 224496 kb
Host smart-8d0fd116-7a7c-4e23-8018-b8108fdff59a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502867377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.502867377
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2742692569
Short name T399
Test name
Test status
Simulation time 23360776122 ps
CPU time 30.41 seconds
Started Oct 15 12:34:23 PM PDT 23
Finished Oct 15 12:34:54 PM PDT 23
Peak memory 211500 kb
Host smart-bb8f31eb-3c64-40bf-a431-3adb3f59dab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742692569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2742692569
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.8252394
Short name T406
Test name
Test status
Simulation time 729037812 ps
CPU time 6.81 seconds
Started Oct 15 12:34:03 PM PDT 23
Finished Oct 15 12:34:16 PM PDT 23
Peak memory 211012 kb
Host smart-a416f16f-e111-4334-8b56-6cf2c1ca97d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8252394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.8252394
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.775055472
Short name T418
Test name
Test status
Simulation time 3184579030 ps
CPU time 19.64 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:35:01 PM PDT 23
Peak memory 212552 kb
Host smart-4d8ddaea-d8fd-4422-aa34-b96cb9a210af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775055472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.775055472
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4135260447
Short name T220
Test name
Test status
Simulation time 4708322763 ps
CPU time 47.14 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:55 PM PDT 23
Peak memory 213580 kb
Host smart-6e82c011-e3ed-4e9c-809c-d8e67da284c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135260447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4135260447
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.4028504368
Short name T414
Test name
Test status
Simulation time 14211078950 ps
CPU time 129.76 seconds
Started Oct 15 12:34:00 PM PDT 23
Finished Oct 15 12:36:10 PM PDT 23
Peak memory 223304 kb
Host smart-f4999d3b-aad7-42f6-aaef-9b8511dbf7e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028504368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.4028504368
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4239379027
Short name T201
Test name
Test status
Simulation time 175011255 ps
CPU time 5.54 seconds
Started Oct 15 12:33:48 PM PDT 23
Finished Oct 15 12:33:53 PM PDT 23
Peak memory 211016 kb
Host smart-b3cd481b-4d64-4eb1-8e8b-ab9dfc3cdae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239379027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4239379027
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1718889087
Short name T369
Test name
Test status
Simulation time 16213923154 ps
CPU time 185.19 seconds
Started Oct 15 12:33:59 PM PDT 23
Finished Oct 15 12:37:10 PM PDT 23
Peak memory 224568 kb
Host smart-50e64138-665e-45b1-a4a7-ea82f565c11a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718889087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1718889087
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3937977549
Short name T6
Test name
Test status
Simulation time 1246097433 ps
CPU time 17.32 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 211252 kb
Host smart-8205d99f-0f26-4584-b869-041707f1fb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937977549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3937977549
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2694900925
Short name T245
Test name
Test status
Simulation time 609743652 ps
CPU time 7.44 seconds
Started Oct 15 12:33:46 PM PDT 23
Finished Oct 15 12:33:54 PM PDT 23
Peak memory 211000 kb
Host smart-750f2543-6189-467d-8e3a-ff8aacb3df20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694900925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2694900925
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4228103992
Short name T409
Test name
Test status
Simulation time 3395194702 ps
CPU time 29.73 seconds
Started Oct 15 12:33:38 PM PDT 23
Finished Oct 15 12:34:08 PM PDT 23
Peak memory 212568 kb
Host smart-ccf2f95a-5c4c-41a9-a6fb-bd4c0313d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228103992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4228103992
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.910550244
Short name T168
Test name
Test status
Simulation time 3641617047 ps
CPU time 30.69 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:34:46 PM PDT 23
Peak memory 212936 kb
Host smart-45bd6439-9258-4b75-bc27-68b5d95c0278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910550244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.rom_ctrl_stress_all.910550244
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.4008466384
Short name T287
Test name
Test status
Simulation time 1382670087 ps
CPU time 7.07 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 210944 kb
Host smart-ac5b8ef2-069b-4e7e-898f-1b119cfc7370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008466384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4008466384
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.923151122
Short name T46
Test name
Test status
Simulation time 56774979291 ps
CPU time 192.78 seconds
Started Oct 15 12:34:11 PM PDT 23
Finished Oct 15 12:37:24 PM PDT 23
Peak memory 228052 kb
Host smart-b4fedce2-3b50-4df7-a2cd-2e5da5b5329f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923151122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.923151122
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.230509779
Short name T267
Test name
Test status
Simulation time 13987715073 ps
CPU time 29.97 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:34:22 PM PDT 23
Peak memory 211356 kb
Host smart-9e6f35d1-cfb7-4ba3-856e-00ee76d24c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230509779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.230509779
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3309939317
Short name T315
Test name
Test status
Simulation time 438346950 ps
CPU time 5.3 seconds
Started Oct 15 12:34:36 PM PDT 23
Finished Oct 15 12:34:43 PM PDT 23
Peak memory 211044 kb
Host smart-bacc2300-a01f-4c56-acbb-4ddb995f3087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309939317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3309939317
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.4204454532
Short name T109
Test name
Test status
Simulation time 929699923 ps
CPU time 16.05 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 212212 kb
Host smart-e8fe1fca-9ab1-4cb8-950f-73ab1ff9176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204454532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.4204454532
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3666425789
Short name T389
Test name
Test status
Simulation time 1591864323 ps
CPU time 8.67 seconds
Started Oct 15 12:33:45 PM PDT 23
Finished Oct 15 12:33:54 PM PDT 23
Peak memory 211008 kb
Host smart-9057b8e8-5a50-4084-9a71-8c7ef5e93e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666425789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3666425789
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1572529438
Short name T357
Test name
Test status
Simulation time 4028520868 ps
CPU time 15.21 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:34:09 PM PDT 23
Peak memory 211132 kb
Host smart-60d880be-4d7b-4593-b43c-019657931b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572529438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1572529438
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4015199569
Short name T422
Test name
Test status
Simulation time 11135037762 ps
CPU time 109.32 seconds
Started Oct 15 12:34:09 PM PDT 23
Finished Oct 15 12:35:59 PM PDT 23
Peak memory 225512 kb
Host smart-26e7e0c6-72a7-407f-9e96-8f7ab199e54a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015199569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4015199569
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.590770363
Short name T249
Test name
Test status
Simulation time 2048882021 ps
CPU time 17.58 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:33 PM PDT 23
Peak memory 210944 kb
Host smart-9bbc1d89-b2a2-4202-bfef-b96b900444cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=590770363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.590770363
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3079563731
Short name T52
Test name
Test status
Simulation time 3544159985 ps
CPU time 28.95 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:34:44 PM PDT 23
Peak memory 212788 kb
Host smart-d5b15e3f-4621-431e-baa5-f67e075080da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079563731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3079563731
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1732492686
Short name T365
Test name
Test status
Simulation time 332068354 ps
CPU time 10.16 seconds
Started Oct 15 12:34:22 PM PDT 23
Finished Oct 15 12:34:32 PM PDT 23
Peak memory 211508 kb
Host smart-f0490bb4-a823-4dc6-8ab3-9a5ca9f3175b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732492686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1732492686
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.4125721750
Short name T17
Test name
Test status
Simulation time 46452965486 ps
CPU time 8167.4 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 02:50:27 PM PDT 23
Peak memory 235784 kb
Host smart-1ca72a23-6582-4016-8d92-ed437bb71c11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125721750 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.4125721750
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1694986283
Short name T400
Test name
Test status
Simulation time 4936082581 ps
CPU time 6.29 seconds
Started Oct 15 12:33:54 PM PDT 23
Finished Oct 15 12:34:00 PM PDT 23
Peak memory 211136 kb
Host smart-dee194c1-9e5b-46bc-9e72-584da5a56c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694986283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1694986283
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2867311312
Short name T273
Test name
Test status
Simulation time 206937574247 ps
CPU time 361.72 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:39:57 PM PDT 23
Peak memory 235776 kb
Host smart-b316f39b-06fb-4f1b-a590-c40e10241b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867311312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2867311312
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1095693112
Short name T10
Test name
Test status
Simulation time 6292482871 ps
CPU time 19.25 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 211492 kb
Host smart-aecfb0ab-50a4-4014-b0ff-5e12ad9cb679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095693112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1095693112
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1104831272
Short name T319
Test name
Test status
Simulation time 2368157862 ps
CPU time 17.58 seconds
Started Oct 15 12:34:02 PM PDT 23
Finished Oct 15 12:34:20 PM PDT 23
Peak memory 211072 kb
Host smart-8d1a6899-74fd-46d8-b2d4-91383b7b4bbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1104831272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1104831272
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1322325857
Short name T264
Test name
Test status
Simulation time 7562114758 ps
CPU time 24.26 seconds
Started Oct 15 12:34:18 PM PDT 23
Finished Oct 15 12:34:42 PM PDT 23
Peak memory 213400 kb
Host smart-e0181206-9249-4407-a9ab-04ae99bf69e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322325857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1322325857
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1151770728
Short name T261
Test name
Test status
Simulation time 3813510707 ps
CPU time 46.34 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:35:10 PM PDT 23
Peak memory 215692 kb
Host smart-d5675260-14ca-4c43-8031-bcccadacf9e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151770728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1151770728
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.3471567974
Short name T293
Test name
Test status
Simulation time 35847021050 ps
CPU time 2099.87 seconds
Started Oct 15 12:34:00 PM PDT 23
Finished Oct 15 01:09:01 PM PDT 23
Peak memory 230676 kb
Host smart-2d468ead-ae51-4159-a991-c67372850a46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471567974 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.3471567974
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3559642359
Short name T3
Test name
Test status
Simulation time 556172004 ps
CPU time 7.9 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 210968 kb
Host smart-6624b11e-72ad-45f4-8ed3-419c8cfc0ae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559642359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3559642359
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.301211345
Short name T277
Test name
Test status
Simulation time 32481512390 ps
CPU time 337.67 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:39:45 PM PDT 23
Peak memory 212352 kb
Host smart-654d7104-3578-44c0-9fab-6c0b4545e466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301211345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.301211345
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3401943460
Short name T229
Test name
Test status
Simulation time 8912205482 ps
CPU time 22.42 seconds
Started Oct 15 12:34:20 PM PDT 23
Finished Oct 15 12:34:43 PM PDT 23
Peak memory 211512 kb
Host smart-b1452e31-4075-421a-a937-10b355cead25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401943460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3401943460
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1105056820
Short name T51
Test name
Test status
Simulation time 1284098057 ps
CPU time 7.54 seconds
Started Oct 15 12:34:28 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 210948 kb
Host smart-7250dec7-24be-4e28-8722-953da39f4f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105056820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1105056820
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3343685312
Short name T387
Test name
Test status
Simulation time 11977443313 ps
CPU time 28.56 seconds
Started Oct 15 12:33:58 PM PDT 23
Finished Oct 15 12:34:26 PM PDT 23
Peak memory 213756 kb
Host smart-4f5806a3-163b-4004-8ccf-bd5b467b3cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343685312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3343685312
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3820356880
Short name T230
Test name
Test status
Simulation time 24200105112 ps
CPU time 95.07 seconds
Started Oct 15 12:34:18 PM PDT 23
Finished Oct 15 12:35:54 PM PDT 23
Peak memory 219280 kb
Host smart-5c2c18cc-8522-4ec0-8bc1-37276e8d399b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820356880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3820356880
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1646699416
Short name T271
Test name
Test status
Simulation time 2477851200 ps
CPU time 15.9 seconds
Started Oct 15 12:33:25 PM PDT 23
Finished Oct 15 12:33:42 PM PDT 23
Peak memory 211088 kb
Host smart-fc310855-730d-4cf4-b2a8-942f95d0bcd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646699416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1646699416
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3913871953
Short name T228
Test name
Test status
Simulation time 3089007255 ps
CPU time 19.36 seconds
Started Oct 15 12:33:27 PM PDT 23
Finished Oct 15 12:33:47 PM PDT 23
Peak memory 211272 kb
Host smart-e8106569-9fca-4d2e-8c37-7132698062ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913871953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3913871953
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2015173749
Short name T9
Test name
Test status
Simulation time 100298400 ps
CPU time 5.73 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:33:39 PM PDT 23
Peak memory 210972 kb
Host smart-a2e25a5a-49b8-42a0-b2cd-94f0c8c393df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015173749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2015173749
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1908586859
Short name T44
Test name
Test status
Simulation time 9274894850 ps
CPU time 120.55 seconds
Started Oct 15 12:33:17 PM PDT 23
Finished Oct 15 12:35:18 PM PDT 23
Peak memory 236800 kb
Host smart-67ca0d36-cfa4-4a90-a125-a350e20db271
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908586859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1908586859
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1886533964
Short name T297
Test name
Test status
Simulation time 10806699857 ps
CPU time 25.26 seconds
Started Oct 15 12:33:30 PM PDT 23
Finished Oct 15 12:33:56 PM PDT 23
Peak memory 213256 kb
Host smart-2e25b67c-1065-4ff9-96e3-f8464e4d5dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886533964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1886533964
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4133560401
Short name T175
Test name
Test status
Simulation time 12588480742 ps
CPU time 32.61 seconds
Started Oct 15 12:33:37 PM PDT 23
Finished Oct 15 12:34:10 PM PDT 23
Peak memory 213700 kb
Host smart-123a1256-bd8a-424d-8fbe-f2f8a3966103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133560401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4133560401
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1844418680
Short name T211
Test name
Test status
Simulation time 325650921184 ps
CPU time 5945.12 seconds
Started Oct 15 12:33:30 PM PDT 23
Finished Oct 15 02:12:36 PM PDT 23
Peak memory 248136 kb
Host smart-f7c24d56-bfcd-4949-850a-328b46918600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844418680 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1844418680
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3224225076
Short name T313
Test name
Test status
Simulation time 925763177 ps
CPU time 9.74 seconds
Started Oct 15 12:33:56 PM PDT 23
Finished Oct 15 12:34:06 PM PDT 23
Peak memory 211032 kb
Host smart-f2c14736-17a8-4a3a-898f-a85834cfc56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224225076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3224225076
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1571912732
Short name T413
Test name
Test status
Simulation time 111304220827 ps
CPU time 292.05 seconds
Started Oct 15 12:33:48 PM PDT 23
Finished Oct 15 12:38:40 PM PDT 23
Peak memory 213204 kb
Host smart-cd383874-7960-4daa-a850-37f52f9fb8d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571912732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1571912732
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.454534919
Short name T280
Test name
Test status
Simulation time 7223372541 ps
CPU time 13.79 seconds
Started Oct 15 12:34:32 PM PDT 23
Finished Oct 15 12:34:47 PM PDT 23
Peak memory 211872 kb
Host smart-3d70daa8-126a-4adc-b1e8-7252026f7bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454534919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.454534919
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.437203864
Short name T343
Test name
Test status
Simulation time 100636141 ps
CPU time 5.85 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:34:47 PM PDT 23
Peak memory 210988 kb
Host smart-44799b94-5c52-4dc3-a118-96f5fb49d5e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=437203864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.437203864
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1627733802
Short name T153
Test name
Test status
Simulation time 20904917796 ps
CPU time 31.16 seconds
Started Oct 15 12:33:52 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 213196 kb
Host smart-b4c2a769-a926-407c-b1ad-55106b4481ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627733802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1627733802
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1215378254
Short name T196
Test name
Test status
Simulation time 825966691 ps
CPU time 18.03 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:34:13 PM PDT 23
Peak memory 212644 kb
Host smart-071747a4-5dba-4ba0-904a-4c42d9e544f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215378254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1215378254
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2275340613
Short name T200
Test name
Test status
Simulation time 2141963396 ps
CPU time 16.83 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 210884 kb
Host smart-97cd7211-0ad3-4dd6-bd48-13b6bc12dbe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275340613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2275340613
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1278942994
Short name T361
Test name
Test status
Simulation time 67704735357 ps
CPU time 138.05 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:36:34 PM PDT 23
Peak memory 236904 kb
Host smart-4d846af8-5f01-4203-a477-c96061f6d965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278942994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1278942994
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3849649781
Short name T364
Test name
Test status
Simulation time 640355086 ps
CPU time 9.49 seconds
Started Oct 15 12:34:26 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 211480 kb
Host smart-e6362ebc-307e-450d-8181-4f407212ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849649781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3849649781
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1192992353
Short name T325
Test name
Test status
Simulation time 1986465423 ps
CPU time 16.93 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:25 PM PDT 23
Peak memory 211000 kb
Host smart-686cd006-3ed7-4dee-aa05-8d41d46be79b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192992353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1192992353
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.614731583
Short name T429
Test name
Test status
Simulation time 3726469365 ps
CPU time 27.46 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:34:40 PM PDT 23
Peak memory 213016 kb
Host smart-48ef45b7-4d69-4c39-9a40-690be2cc6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614731583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.614731583
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2569252400
Short name T247
Test name
Test status
Simulation time 1231011857 ps
CPU time 15.16 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 210868 kb
Host smart-55190509-e34f-462a-a76d-216ace25a6fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569252400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2569252400
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2201116451
Short name T314
Test name
Test status
Simulation time 9631627089 ps
CPU time 14.72 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211052 kb
Host smart-03a9e4a5-bcbb-4436-8197-cfa1a5501a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201116451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2201116451
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3563899107
Short name T56
Test name
Test status
Simulation time 87067876220 ps
CPU time 170.98 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:36:56 PM PDT 23
Peak memory 212336 kb
Host smart-8e9e7a72-0ecb-47b9-89d7-ce28a3f469e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563899107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3563899107
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3744229842
Short name T348
Test name
Test status
Simulation time 172310115 ps
CPU time 10.41 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:34:28 PM PDT 23
Peak memory 210184 kb
Host smart-639f607f-0de7-447b-9024-ba6e013b67a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744229842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3744229842
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3586735604
Short name T375
Test name
Test status
Simulation time 2136584518 ps
CPU time 11.36 seconds
Started Oct 15 12:34:11 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 210896 kb
Host smart-809ee058-72b5-42c4-9cc0-ff822d42012e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586735604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3586735604
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2758452488
Short name T378
Test name
Test status
Simulation time 4011603826 ps
CPU time 38.03 seconds
Started Oct 15 12:34:32 PM PDT 23
Finished Oct 15 12:35:11 PM PDT 23
Peak memory 212240 kb
Host smart-f2d8b4a5-cc23-4e0d-91a9-156631fddbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758452488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2758452488
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1056675765
Short name T327
Test name
Test status
Simulation time 3075326383 ps
CPU time 45.04 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:35:00 PM PDT 23
Peak memory 215232 kb
Host smart-d05c3c36-e04f-4a55-88ed-94f41d3aa8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056675765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1056675765
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.268690199
Short name T216
Test name
Test status
Simulation time 20892930502 ps
CPU time 1161.83 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:53:49 PM PDT 23
Peak memory 235360 kb
Host smart-fc73fd0b-4a4f-4873-85e6-9d6208b6329a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268690199 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.268690199
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1653095220
Short name T222
Test name
Test status
Simulation time 13735713616 ps
CPU time 14.49 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:33:56 PM PDT 23
Peak memory 211056 kb
Host smart-f4f27711-89b0-43b7-8f23-a1f4626a7abe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653095220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1653095220
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1368596460
Short name T428
Test name
Test status
Simulation time 4149773413 ps
CPU time 136.52 seconds
Started Oct 15 12:33:59 PM PDT 23
Finished Oct 15 12:36:16 PM PDT 23
Peak memory 232856 kb
Host smart-f2b12beb-645f-4335-ac4c-c1c63a2c0460
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368596460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1368596460
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1884678770
Short name T226
Test name
Test status
Simulation time 4971299268 ps
CPU time 24.88 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:33 PM PDT 23
Peak memory 211516 kb
Host smart-2b727411-1e83-491f-a498-d5ed5cd4df3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884678770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1884678770
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1924903118
Short name T218
Test name
Test status
Simulation time 385678156 ps
CPU time 5.98 seconds
Started Oct 15 12:34:00 PM PDT 23
Finished Oct 15 12:34:06 PM PDT 23
Peak memory 211012 kb
Host smart-d751001b-16f4-40de-ad83-eb469a2cc64b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924903118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1924903118
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2436548256
Short name T263
Test name
Test status
Simulation time 3246448955 ps
CPU time 28.54 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:34:34 PM PDT 23
Peak memory 212544 kb
Host smart-b0d778e3-18a0-4463-872a-402bd3935f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436548256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2436548256
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1095315790
Short name T322
Test name
Test status
Simulation time 54092390716 ps
CPU time 107.94 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:36:03 PM PDT 23
Peak memory 219256 kb
Host smart-49a2d351-a266-4ac4-ab7a-fe2dff7f8e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095315790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1095315790
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2558478350
Short name T381
Test name
Test status
Simulation time 73143038799 ps
CPU time 2777.19 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 01:20:26 PM PDT 23
Peak memory 243892 kb
Host smart-35b9e537-61e7-43f5-a2e1-abcb17a4c2a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558478350 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2558478350
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1401008522
Short name T199
Test name
Test status
Simulation time 1080420492 ps
CPU time 8.33 seconds
Started Oct 15 12:34:30 PM PDT 23
Finished Oct 15 12:34:39 PM PDT 23
Peak memory 210968 kb
Host smart-29c1d1ae-5dc8-43ac-96a1-153501fd43ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401008522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1401008522
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3383679438
Short name T419
Test name
Test status
Simulation time 80188275850 ps
CPU time 441.76 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:41:38 PM PDT 23
Peak memory 227944 kb
Host smart-3b447685-6535-42d8-9464-99dfc86cae34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383679438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3383679438
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.3449455476
Short name T2
Test name
Test status
Simulation time 10833566569 ps
CPU time 25.86 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211476 kb
Host smart-369f2eee-d0ed-42d3-bb5b-5a61a69054a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449455476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.3449455476
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1630611295
Short name T64
Test name
Test status
Simulation time 1740367684 ps
CPU time 9.41 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:17 PM PDT 23
Peak memory 211012 kb
Host smart-d476f2a0-e657-4c7d-bddd-1525f1b0fb3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630611295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1630611295
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2331098415
Short name T171
Test name
Test status
Simulation time 62740179145 ps
CPU time 34.37 seconds
Started Oct 15 12:34:21 PM PDT 23
Finished Oct 15 12:35:01 PM PDT 23
Peak memory 212824 kb
Host smart-574ac520-cee7-47a3-974c-58300512a761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331098415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2331098415
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3277566354
Short name T61
Test name
Test status
Simulation time 13800892266 ps
CPU time 84.14 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:35:25 PM PDT 23
Peak memory 217792 kb
Host smart-77f5f716-9716-4c95-a378-994026b0011d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277566354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3277566354
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.445772576
Short name T394
Test name
Test status
Simulation time 39091069554 ps
CPU time 696.06 seconds
Started Oct 15 12:33:29 PM PDT 23
Finished Oct 15 12:45:06 PM PDT 23
Peak memory 235692 kb
Host smart-0e77667d-a4d1-4a21-be6f-b4dd162eb65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445772576 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.445772576
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.847116388
Short name T299
Test name
Test status
Simulation time 8008430257 ps
CPU time 15.09 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 211080 kb
Host smart-a044be4c-e267-4f84-9894-ebe5c9d325c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847116388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.847116388
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2298571153
Short name T190
Test name
Test status
Simulation time 143424715282 ps
CPU time 323.77 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:39:30 PM PDT 23
Peak memory 236580 kb
Host smart-da4901c3-1912-47b5-909a-a85a3e5237bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298571153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2298571153
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.4205698228
Short name T151
Test name
Test status
Simulation time 14667607885 ps
CPU time 32.76 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:41 PM PDT 23
Peak memory 211448 kb
Host smart-2f80f84a-c2ba-423e-b1de-22507cf05e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205698228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.4205698228
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2520811488
Short name T11
Test name
Test status
Simulation time 7766884821 ps
CPU time 17.51 seconds
Started Oct 15 12:34:20 PM PDT 23
Finished Oct 15 12:34:38 PM PDT 23
Peak memory 211144 kb
Host smart-29c77d29-69d1-4fa6-b2cf-15ccabacccea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2520811488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2520811488
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.416476911
Short name T176
Test name
Test status
Simulation time 4428437547 ps
CPU time 33.01 seconds
Started Oct 15 12:34:08 PM PDT 23
Finished Oct 15 12:34:42 PM PDT 23
Peak memory 212572 kb
Host smart-cf89a2c7-1a44-47d4-9a6b-876ee77baf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416476911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.416476911
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.592036840
Short name T239
Test name
Test status
Simulation time 10492964778 ps
CPU time 56.69 seconds
Started Oct 15 12:33:42 PM PDT 23
Finished Oct 15 12:34:39 PM PDT 23
Peak memory 218360 kb
Host smart-ebaf01fc-9daf-478a-bac6-a59c1d894892
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592036840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.592036840
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3152035879
Short name T354
Test name
Test status
Simulation time 32557722531 ps
CPU time 5323.87 seconds
Started Oct 15 12:34:18 PM PDT 23
Finished Oct 15 02:03:03 PM PDT 23
Peak memory 233784 kb
Host smart-ec0bc108-af7a-440b-a82c-f51784938dd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152035879 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3152035879
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.929838737
Short name T283
Test name
Test status
Simulation time 4431577410 ps
CPU time 10.69 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211128 kb
Host smart-8c4ac9a8-52c1-45d5-ad1c-a93fea674023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929838737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.929838737
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3638130754
Short name T203
Test name
Test status
Simulation time 11732998950 ps
CPU time 200.33 seconds
Started Oct 15 12:34:02 PM PDT 23
Finished Oct 15 12:37:23 PM PDT 23
Peak memory 235408 kb
Host smart-2db74581-d5ae-4b64-9dda-772a9a75a031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638130754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3638130754
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.62425598
Short name T358
Test name
Test status
Simulation time 3326736559 ps
CPU time 27.06 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:34:28 PM PDT 23
Peak memory 216664 kb
Host smart-8c902c0a-40c6-4b9f-afa6-6656933c1a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62425598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.62425598
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.532946166
Short name T282
Test name
Test status
Simulation time 1189771079 ps
CPU time 7.44 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211004 kb
Host smart-c8cce620-b87e-4840-bd1d-7b4fa5ee9861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532946166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.532946166
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3867712578
Short name T312
Test name
Test status
Simulation time 4205390932 ps
CPU time 38.2 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:34:51 PM PDT 23
Peak memory 212376 kb
Host smart-577d0ab2-93e5-41ea-980e-420cf948d761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867712578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3867712578
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1111743990
Short name T257
Test name
Test status
Simulation time 1523559703 ps
CPU time 22.97 seconds
Started Oct 15 12:34:06 PM PDT 23
Finished Oct 15 12:34:29 PM PDT 23
Peak memory 213212 kb
Host smart-02ecd5f0-ba1b-4c36-a503-2b936ceaebb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111743990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1111743990
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2665417804
Short name T417
Test name
Test status
Simulation time 2782841290 ps
CPU time 12.33 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:34:17 PM PDT 23
Peak memory 211084 kb
Host smart-6249585e-53b0-4422-9463-b48cf5c9cc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665417804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2665417804
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2554760476
Short name T392
Test name
Test status
Simulation time 4229928312 ps
CPU time 127.46 seconds
Started Oct 15 12:34:06 PM PDT 23
Finished Oct 15 12:36:14 PM PDT 23
Peak memory 228156 kb
Host smart-d04f4b41-4dc0-42db-8333-9f7cc480a2ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554760476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2554760476
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3176512002
Short name T33
Test name
Test status
Simulation time 171967900 ps
CPU time 9.55 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:34:34 PM PDT 23
Peak memory 211296 kb
Host smart-89443628-9062-4bdf-82ec-6551491cd89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176512002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3176512002
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.532838054
Short name T359
Test name
Test status
Simulation time 364760569 ps
CPU time 5.53 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:34:16 PM PDT 23
Peak memory 211036 kb
Host smart-1c6f50fe-7488-4b58-b99d-48705b7d67bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=532838054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.532838054
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.786163745
Short name T159
Test name
Test status
Simulation time 708675985 ps
CPU time 10.13 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:34:29 PM PDT 23
Peak memory 212316 kb
Host smart-f483c17b-b1c7-413f-8f89-7f1955cd1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786163745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.786163745
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.856795576
Short name T180
Test name
Test status
Simulation time 6734241523 ps
CPU time 34.09 seconds
Started Oct 15 12:34:02 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 213248 kb
Host smart-b8172e3e-2735-4222-9c5d-8cb15ed2c278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856795576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.856795576
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2753679840
Short name T405
Test name
Test status
Simulation time 263861417 ps
CPU time 5.07 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:34:22 PM PDT 23
Peak memory 211052 kb
Host smart-793f3b11-cfcd-4b7c-b2fe-c02a4d8ec210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753679840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2753679840
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2936094343
Short name T321
Test name
Test status
Simulation time 7294399212 ps
CPU time 125.42 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:36:22 PM PDT 23
Peak memory 236720 kb
Host smart-87ca46df-820a-4f40-8e0b-e8a6ea35c935
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936094343 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2936094343
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1942076206
Short name T32
Test name
Test status
Simulation time 692934811 ps
CPU time 9.3 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 211140 kb
Host smart-71f80f19-24a0-409d-bf85-f02987d890a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942076206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1942076206
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1227615299
Short name T62
Test name
Test status
Simulation time 3128702704 ps
CPU time 10.44 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:18 PM PDT 23
Peak memory 211084 kb
Host smart-00c46fb9-366f-4f79-a59a-6fee4fcc9faa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1227615299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1227615299
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.621151523
Short name T154
Test name
Test status
Simulation time 2067944453 ps
CPU time 22.78 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:34:39 PM PDT 23
Peak memory 212472 kb
Host smart-0d67f14e-b2c0-45db-a59a-c81bcad78b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621151523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.621151523
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1326097151
Short name T396
Test name
Test status
Simulation time 1583198031 ps
CPU time 21.73 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:35:03 PM PDT 23
Peak memory 215436 kb
Host smart-6f01be89-a14d-46cb-9b68-8fff877a385f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326097151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1326097151
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2043209996
Short name T14
Test name
Test status
Simulation time 16290591787 ps
CPU time 615.06 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:44:30 PM PDT 23
Peak memory 234124 kb
Host smart-ee179e5b-f8fa-42a6-be3b-abc76a549679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043209996 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2043209996
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1705868313
Short name T240
Test name
Test status
Simulation time 553163488 ps
CPU time 4.27 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 210932 kb
Host smart-8be6fc21-2581-4c89-9041-7b168a5bed12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705868313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1705868313
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2765975776
Short name T57
Test name
Test status
Simulation time 55089487418 ps
CPU time 272.94 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:38:49 PM PDT 23
Peak memory 224344 kb
Host smart-e864e316-252f-4f00-9ded-1bfea70e04f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765975776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2765975776
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3108602916
Short name T346
Test name
Test status
Simulation time 693039346 ps
CPU time 9.47 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:34:14 PM PDT 23
Peak memory 210964 kb
Host smart-9a709a94-face-440a-a51c-0df0e758bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108602916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3108602916
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1113576015
Short name T311
Test name
Test status
Simulation time 3260145550 ps
CPU time 9.82 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211156 kb
Host smart-214e8495-6354-4d0e-b0f1-1e077e9c1780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113576015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1113576015
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1729391377
Short name T366
Test name
Test status
Simulation time 2570765890 ps
CPU time 30.33 seconds
Started Oct 15 12:34:11 PM PDT 23
Finished Oct 15 12:34:42 PM PDT 23
Peak memory 212596 kb
Host smart-d46df6eb-f4bb-4f19-b46e-3bf40565dec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729391377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1729391377
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1599503502
Short name T292
Test name
Test status
Simulation time 6973255242 ps
CPU time 21.05 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:34:48 PM PDT 23
Peak memory 211772 kb
Host smart-ad900bf6-6e36-477f-90ae-b068d390b263
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599503502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1599503502
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3594829469
Short name T111
Test name
Test status
Simulation time 80717724118 ps
CPU time 781.48 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:47:48 PM PDT 23
Peak memory 235800 kb
Host smart-05c426f5-782d-4e8f-8f6c-519e9c9bd825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594829469 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3594829469
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1880308611
Short name T338
Test name
Test status
Simulation time 866816010 ps
CPU time 7.97 seconds
Started Oct 15 12:33:36 PM PDT 23
Finished Oct 15 12:33:45 PM PDT 23
Peak memory 210024 kb
Host smart-cce8f1bd-cb6b-46a6-812b-7dd4675f7b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880308611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1880308611
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.433869682
Short name T284
Test name
Test status
Simulation time 87285109916 ps
CPU time 290.28 seconds
Started Oct 15 12:33:38 PM PDT 23
Finished Oct 15 12:38:29 PM PDT 23
Peak memory 234740 kb
Host smart-a4e6668c-9522-435f-bae6-59ee0c3da588
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433869682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.433869682
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.1844599621
Short name T231
Test name
Test status
Simulation time 50885142290 ps
CPU time 26.1 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:34:08 PM PDT 23
Peak memory 211672 kb
Host smart-5e07ac41-9416-493e-a40a-5ae944b2f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844599621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.1844599621
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1369637507
Short name T360
Test name
Test status
Simulation time 1828375567 ps
CPU time 15.58 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:34:07 PM PDT 23
Peak memory 210916 kb
Host smart-e2a39f00-1561-42d7-b177-fbcfe1ad591f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369637507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1369637507
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.1555422086
Short name T45
Test name
Test status
Simulation time 4385258016 ps
CPU time 63.68 seconds
Started Oct 15 12:33:36 PM PDT 23
Finished Oct 15 12:34:40 PM PDT 23
Peak memory 236692 kb
Host smart-921bdf75-c20d-47fc-a899-d03b9e9ba816
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555422086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1555422086
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.594697358
Short name T337
Test name
Test status
Simulation time 713022461 ps
CPU time 10.35 seconds
Started Oct 15 12:33:16 PM PDT 23
Finished Oct 15 12:33:27 PM PDT 23
Peak memory 210944 kb
Host smart-20bc01e3-ee2d-40a3-af2b-5bc72a399472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594697358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.594697358
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1417120090
Short name T265
Test name
Test status
Simulation time 415022125 ps
CPU time 23.13 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 214284 kb
Host smart-75fff458-ea52-4423-a5e3-5e77b27fc257
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417120090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1417120090
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2366951122
Short name T352
Test name
Test status
Simulation time 97607217426 ps
CPU time 2369.56 seconds
Started Oct 15 12:33:52 PM PDT 23
Finished Oct 15 01:13:22 PM PDT 23
Peak memory 235664 kb
Host smart-6bd22317-bb42-4092-957a-0d8d181b8110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366951122 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2366951122
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1757988938
Short name T425
Test name
Test status
Simulation time 3815328701 ps
CPU time 13.33 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:34:41 PM PDT 23
Peak memory 210864 kb
Host smart-6a532613-117c-4143-8e57-eeff66c57ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757988938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1757988938
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2844261748
Short name T233
Test name
Test status
Simulation time 16972768207 ps
CPU time 144.02 seconds
Started Oct 15 12:34:10 PM PDT 23
Finished Oct 15 12:36:34 PM PDT 23
Peak memory 236656 kb
Host smart-9f4cca57-3420-4f0a-8584-37bde3c29e77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844261748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2844261748
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2621729002
Short name T189
Test name
Test status
Simulation time 5235417759 ps
CPU time 17.92 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:34:45 PM PDT 23
Peak memory 211580 kb
Host smart-8bc3e0be-64bd-4cf3-962b-0c4df0d7b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621729002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2621729002
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3387835173
Short name T382
Test name
Test status
Simulation time 381420836 ps
CPU time 5.52 seconds
Started Oct 15 12:34:18 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 211008 kb
Host smart-a8fd9bf0-738e-421b-909d-5c17cb69c837
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387835173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3387835173
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1037458408
Short name T345
Test name
Test status
Simulation time 12878672528 ps
CPU time 35.45 seconds
Started Oct 15 12:34:31 PM PDT 23
Finished Oct 15 12:35:07 PM PDT 23
Peak memory 213552 kb
Host smart-776017e9-f23b-4155-92a6-b457c816023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037458408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1037458408
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2768549142
Short name T351
Test name
Test status
Simulation time 7381927205 ps
CPU time 19.34 seconds
Started Oct 15 12:33:52 PM PDT 23
Finished Oct 15 12:34:11 PM PDT 23
Peak memory 211656 kb
Host smart-958e975c-7278-4a3b-80eb-6c93916ad091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768549142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2768549142
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1472394031
Short name T206
Test name
Test status
Simulation time 91177156021 ps
CPU time 9537.26 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 03:13:15 PM PDT 23
Peak memory 235756 kb
Host smart-7257a1db-7e6d-4681-ac97-d5ffd7c35644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472394031 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1472394031
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.986974427
Short name T347
Test name
Test status
Simulation time 1023813138 ps
CPU time 10.1 seconds
Started Oct 15 12:34:31 PM PDT 23
Finished Oct 15 12:34:41 PM PDT 23
Peak memory 210872 kb
Host smart-abc67508-8837-4e53-a5b7-f61e0b5e5db7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986974427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.986974427
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3548395738
Short name T336
Test name
Test status
Simulation time 116675554716 ps
CPU time 261.36 seconds
Started Oct 15 12:34:28 PM PDT 23
Finished Oct 15 12:38:50 PM PDT 23
Peak memory 211540 kb
Host smart-0495ca5a-3cb5-44a6-93bb-a781b614e0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548395738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3548395738
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.783848441
Short name T298
Test name
Test status
Simulation time 943132898 ps
CPU time 11.57 seconds
Started Oct 15 12:34:44 PM PDT 23
Finished Oct 15 12:34:56 PM PDT 23
Peak memory 211200 kb
Host smart-cc4fb396-7b67-4d0f-b46a-7cc2eef802f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783848441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.783848441
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3681906821
Short name T165
Test name
Test status
Simulation time 706625652 ps
CPU time 7.42 seconds
Started Oct 15 12:34:32 PM PDT 23
Finished Oct 15 12:34:40 PM PDT 23
Peak memory 210960 kb
Host smart-2e3608d8-3412-4287-9cc8-d8c5bbe3d60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3681906821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3681906821
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3297529563
Short name T423
Test name
Test status
Simulation time 190186005 ps
CPU time 9.83 seconds
Started Oct 15 12:34:37 PM PDT 23
Finished Oct 15 12:34:48 PM PDT 23
Peak memory 212368 kb
Host smart-af033344-5c33-4b44-a72a-5ed447eeb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297529563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3297529563
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.65995099
Short name T330
Test name
Test status
Simulation time 4914501688 ps
CPU time 60.62 seconds
Started Oct 15 12:34:04 PM PDT 23
Finished Oct 15 12:35:05 PM PDT 23
Peak memory 217076 kb
Host smart-18a46620-e44b-466a-b0d2-7db1e71a5439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65995099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 41.rom_ctrl_stress_all.65995099
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.394515364
Short name T15
Test name
Test status
Simulation time 24915952943 ps
CPU time 939.31 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:49:46 PM PDT 23
Peak memory 229812 kb
Host smart-030499b8-aea9-4850-9ff5-328f56cb399d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394515364 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.394515364
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.2141862614
Short name T276
Test name
Test status
Simulation time 3735934964 ps
CPU time 10.35 seconds
Started Oct 15 12:34:28 PM PDT 23
Finished Oct 15 12:34:39 PM PDT 23
Peak memory 211112 kb
Host smart-b59b960c-719e-49e4-921a-c46b23295f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141862614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.2141862614
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2507681207
Short name T415
Test name
Test status
Simulation time 16232086251 ps
CPU time 136.57 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:36:29 PM PDT 23
Peak memory 212228 kb
Host smart-1d46fcdf-a32f-4133-81bc-5076e56afbff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507681207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2507681207
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2566709704
Short name T272
Test name
Test status
Simulation time 1381896532 ps
CPU time 9.75 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:34:37 PM PDT 23
Peak memory 211000 kb
Host smart-8174cb20-f6b7-482a-b4de-88f019d42ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566709704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2566709704
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3916068478
Short name T107
Test name
Test status
Simulation time 6863723249 ps
CPU time 15.29 seconds
Started Oct 15 12:34:22 PM PDT 23
Finished Oct 15 12:34:37 PM PDT 23
Peak memory 211040 kb
Host smart-cb72776d-4b78-479f-826d-ae836c683b2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916068478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3916068478
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.4174273021
Short name T1
Test name
Test status
Simulation time 3899575056 ps
CPU time 36.62 seconds
Started Oct 15 12:34:01 PM PDT 23
Finished Oct 15 12:34:38 PM PDT 23
Peak memory 212524 kb
Host smart-8f72ca7a-9399-4313-b76e-95a706fc8bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174273021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.4174273021
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2209380642
Short name T178
Test name
Test status
Simulation time 217589822 ps
CPU time 12.75 seconds
Started Oct 15 12:34:27 PM PDT 23
Finished Oct 15 12:34:41 PM PDT 23
Peak memory 212688 kb
Host smart-997d543c-3217-491f-8a1d-2e75d734aa21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209380642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2209380642
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3510314789
Short name T232
Test name
Test status
Simulation time 17568810372 ps
CPU time 1421.28 seconds
Started Oct 15 12:34:05 PM PDT 23
Finished Oct 15 12:57:47 PM PDT 23
Peak memory 222636 kb
Host smart-f7031fe9-8e17-4dc8-8cd0-61993c8ab139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510314789 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3510314789
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2466734267
Short name T221
Test name
Test status
Simulation time 1286249152 ps
CPU time 11.56 seconds
Started Oct 15 12:34:26 PM PDT 23
Finished Oct 15 12:34:38 PM PDT 23
Peak memory 210964 kb
Host smart-08470692-c627-4af0-98ec-5924f18f9e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466734267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2466734267
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.711644497
Short name T401
Test name
Test status
Simulation time 80794767268 ps
CPU time 386.64 seconds
Started Oct 15 12:34:23 PM PDT 23
Finished Oct 15 12:40:51 PM PDT 23
Peak memory 236620 kb
Host smart-1df61371-fe33-4928-bc76-a7a08330217a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711644497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.711644497
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2607020801
Short name T53
Test name
Test status
Simulation time 1971186199 ps
CPU time 20.91 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:34:45 PM PDT 23
Peak memory 211168 kb
Host smart-1681afbe-05ea-4757-bfe0-045a5c51c226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607020801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2607020801
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4270696911
Short name T209
Test name
Test status
Simulation time 376187831 ps
CPU time 5.33 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 210868 kb
Host smart-43cfd156-dc32-44bc-a223-d0a7239eae71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270696911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4270696911
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.3904308128
Short name T225
Test name
Test status
Simulation time 5501273479 ps
CPU time 21.68 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:34:38 PM PDT 23
Peak memory 213096 kb
Host smart-47077d49-0dce-460f-ba8f-543e0ad124b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904308128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.3904308128
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1799644913
Short name T185
Test name
Test status
Simulation time 11962004330 ps
CPU time 48.76 seconds
Started Oct 15 12:34:22 PM PDT 23
Finished Oct 15 12:35:11 PM PDT 23
Peak memory 214612 kb
Host smart-d86d22ad-7f60-4d9c-a9fc-d3aea1ba8d6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799644913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1799644913
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3350002591
Short name T333
Test name
Test status
Simulation time 67681274746 ps
CPU time 645.17 seconds
Started Oct 15 12:34:54 PM PDT 23
Finished Oct 15 12:45:40 PM PDT 23
Peak memory 235752 kb
Host smart-38e52f28-38a0-4d80-9e2f-24f56ba0ba2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350002591 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3350002591
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3499024639
Short name T367
Test name
Test status
Simulation time 87302470 ps
CPU time 4.35 seconds
Started Oct 15 12:34:20 PM PDT 23
Finished Oct 15 12:34:30 PM PDT 23
Peak memory 211076 kb
Host smart-7371174a-2b2a-4d52-be29-d125e18e4708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499024639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3499024639
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1478349526
Short name T60
Test name
Test status
Simulation time 4195500138 ps
CPU time 76.25 seconds
Started Oct 15 12:34:48 PM PDT 23
Finished Oct 15 12:36:04 PM PDT 23
Peak memory 228332 kb
Host smart-6f34533f-d1f8-4a22-a46b-24fd580c3507
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478349526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1478349526
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.387421533
Short name T411
Test name
Test status
Simulation time 874946622 ps
CPU time 9.77 seconds
Started Oct 15 12:34:28 PM PDT 23
Finished Oct 15 12:34:38 PM PDT 23
Peak memory 211116 kb
Host smart-b660debd-7fea-4daa-adea-5cff19222d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387421533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.387421533
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1771127313
Short name T191
Test name
Test status
Simulation time 1566552011 ps
CPU time 13.96 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:30 PM PDT 23
Peak memory 211040 kb
Host smart-d5a1d109-21fa-409d-9f8e-e094326d95df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771127313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1771127313
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.443813721
Short name T7
Test name
Test status
Simulation time 6237365816 ps
CPU time 31.42 seconds
Started Oct 15 12:34:38 PM PDT 23
Finished Oct 15 12:35:15 PM PDT 23
Peak memory 213304 kb
Host smart-e7919e5d-bfd2-4798-91fe-235074a1550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443813721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.443813721
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3164837705
Short name T373
Test name
Test status
Simulation time 2190714942 ps
CPU time 18.93 seconds
Started Oct 15 12:34:17 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 210908 kb
Host smart-cd42e483-25b7-43dd-95a5-fd5fd3cbc03b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164837705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3164837705
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.165179720
Short name T424
Test name
Test status
Simulation time 1532647768 ps
CPU time 13.51 seconds
Started Oct 15 12:34:43 PM PDT 23
Finished Oct 15 12:34:59 PM PDT 23
Peak memory 210984 kb
Host smart-8ddf8bf0-9d17-4eb6-ad5c-152ce504507e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165179720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.165179720
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4060675063
Short name T372
Test name
Test status
Simulation time 6686988847 ps
CPU time 184.31 seconds
Started Oct 15 12:34:17 PM PDT 23
Finished Oct 15 12:37:22 PM PDT 23
Peak memory 224472 kb
Host smart-12438e34-e962-453d-a703-a20f5970e617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060675063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4060675063
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3785251886
Short name T49
Test name
Test status
Simulation time 5825322163 ps
CPU time 17.81 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:34:59 PM PDT 23
Peak memory 211644 kb
Host smart-eb32e997-b109-4724-a85d-51789ca227d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785251886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3785251886
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.304176086
Short name T332
Test name
Test status
Simulation time 1612380788 ps
CPU time 14.52 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:34:33 PM PDT 23
Peak memory 210988 kb
Host smart-447165bc-6240-4df7-a6ce-caf5d368fb22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=304176086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.304176086
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2489246667
Short name T349
Test name
Test status
Simulation time 13966063417 ps
CPU time 40.68 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:48 PM PDT 23
Peak memory 213048 kb
Host smart-1b51947f-97bb-4637-aaec-eeeecf287d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489246667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2489246667
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.218185808
Short name T242
Test name
Test status
Simulation time 431973877 ps
CPU time 15.54 seconds
Started Oct 15 12:34:16 PM PDT 23
Finished Oct 15 12:34:32 PM PDT 23
Peak memory 212456 kb
Host smart-90c9bb45-29ba-418d-b2be-11f0b98e673f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218185808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.218185808
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.27161479
Short name T160
Test name
Test status
Simulation time 61200680925 ps
CPU time 2137.89 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 01:10:02 PM PDT 23
Peak memory 243892 kb
Host smart-0f0c7da7-445a-46f1-9993-75b91054c740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27161479 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.27161479
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.718370443
Short name T310
Test name
Test status
Simulation time 438002623 ps
CPU time 4.25 seconds
Started Oct 15 12:34:36 PM PDT 23
Finished Oct 15 12:34:42 PM PDT 23
Peak memory 210984 kb
Host smart-236a7c55-c1d6-44c4-bcee-3f4be575e5d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718370443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.718370443
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2463407548
Short name T279
Test name
Test status
Simulation time 31347171377 ps
CPU time 148.47 seconds
Started Oct 15 12:34:26 PM PDT 23
Finished Oct 15 12:36:54 PM PDT 23
Peak memory 237644 kb
Host smart-9fc1afb5-01c1-4f9e-ae3a-4e09d2199173
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463407548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2463407548
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2161960262
Short name T210
Test name
Test status
Simulation time 2588840549 ps
CPU time 13.17 seconds
Started Oct 15 12:34:44 PM PDT 23
Finished Oct 15 12:34:59 PM PDT 23
Peak memory 211316 kb
Host smart-93e08e58-25d3-4579-83dc-175c37ec1c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161960262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2161960262
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1762472306
Short name T259
Test name
Test status
Simulation time 689878585 ps
CPU time 8.06 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 12:34:22 PM PDT 23
Peak memory 210952 kb
Host smart-88715ce0-9c60-4f25-8896-7bda502b3d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762472306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1762472306
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.1736048080
Short name T391
Test name
Test status
Simulation time 2650731714 ps
CPU time 25.66 seconds
Started Oct 15 12:34:53 PM PDT 23
Finished Oct 15 12:35:20 PM PDT 23
Peak memory 212652 kb
Host smart-1f8660ca-1eb0-4a4e-a5e6-467719e43202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736048080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.1736048080
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1576782421
Short name T172
Test name
Test status
Simulation time 338095055 ps
CPU time 8.06 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 211252 kb
Host smart-3a67c06d-e459-4c72-838e-8bd161288a17
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576782421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1576782421
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.10555864
Short name T274
Test name
Test status
Simulation time 34946408103 ps
CPU time 1605.99 seconds
Started Oct 15 12:33:57 PM PDT 23
Finished Oct 15 01:00:44 PM PDT 23
Peak memory 233208 kb
Host smart-b12f658c-94ae-4897-88c0-b7889cca9498
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10555864 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.10555864
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3807259877
Short name T275
Test name
Test status
Simulation time 3100508183 ps
CPU time 14.76 seconds
Started Oct 15 12:34:44 PM PDT 23
Finished Oct 15 12:35:00 PM PDT 23
Peak memory 211112 kb
Host smart-7c755065-3713-45a9-a6fb-206379cef494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807259877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3807259877
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3297773606
Short name T202
Test name
Test status
Simulation time 87425995645 ps
CPU time 217.35 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:37:53 PM PDT 23
Peak memory 237636 kb
Host smart-8136d295-b023-4713-ae3d-9ebdcaa9ad1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297773606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3297773606
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.691937055
Short name T48
Test name
Test status
Simulation time 2884203445 ps
CPU time 24.81 seconds
Started Oct 15 12:33:53 PM PDT 23
Finished Oct 15 12:34:18 PM PDT 23
Peak memory 211696 kb
Host smart-3c63e7bf-413c-4a7c-b5e0-dee64d05e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691937055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.691937055
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.345870799
Short name T353
Test name
Test status
Simulation time 190079303 ps
CPU time 6.03 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:34:18 PM PDT 23
Peak memory 210952 kb
Host smart-982a5a48-3fac-40b0-8e18-462a6600e0d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345870799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.345870799
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3049963834
Short name T278
Test name
Test status
Simulation time 742967448 ps
CPU time 10.02 seconds
Started Oct 15 12:34:14 PM PDT 23
Finished Oct 15 12:34:24 PM PDT 23
Peak memory 212764 kb
Host smart-4e9d12ea-4234-430f-8f6e-953b2ace07f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049963834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3049963834
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3110060664
Short name T326
Test name
Test status
Simulation time 34618574196 ps
CPU time 46.72 seconds
Started Oct 15 12:34:51 PM PDT 23
Finished Oct 15 12:35:38 PM PDT 23
Peak memory 216524 kb
Host smart-371ac9ee-9831-4dab-a538-5d789f4b3199
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110060664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3110060664
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.831877173
Short name T217
Test name
Test status
Simulation time 62933375015 ps
CPU time 538.73 seconds
Started Oct 15 12:34:44 PM PDT 23
Finished Oct 15 12:43:43 PM PDT 23
Peak memory 233076 kb
Host smart-1f9c0d00-f32e-4442-965e-b8325b596940
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831877173 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.831877173
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.566916067
Short name T63
Test name
Test status
Simulation time 520525972 ps
CPU time 7.6 seconds
Started Oct 15 12:34:40 PM PDT 23
Finished Oct 15 12:34:49 PM PDT 23
Peak memory 211016 kb
Host smart-431f43d1-3533-49b2-bb3b-6c56da65769c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566916067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.566916067
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2589011527
Short name T35
Test name
Test status
Simulation time 31822422796 ps
CPU time 286.93 seconds
Started Oct 15 12:34:32 PM PDT 23
Finished Oct 15 12:39:20 PM PDT 23
Peak memory 233600 kb
Host smart-f4f43269-4956-4248-a532-c77e933d5edd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589011527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2589011527
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1441021622
Short name T269
Test name
Test status
Simulation time 5070412308 ps
CPU time 27.92 seconds
Started Oct 15 12:34:42 PM PDT 23
Finished Oct 15 12:35:10 PM PDT 23
Peak memory 211404 kb
Host smart-d016c185-a5bb-4417-a26c-6ac07925655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441021622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1441021622
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.300196060
Short name T169
Test name
Test status
Simulation time 2218826077 ps
CPU time 17.6 seconds
Started Oct 15 12:34:39 PM PDT 23
Finished Oct 15 12:34:58 PM PDT 23
Peak memory 211132 kb
Host smart-b7c5215d-59cd-4a2d-a055-4bbd9246ba71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300196060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.300196060
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.837423517
Short name T286
Test name
Test status
Simulation time 1554581169 ps
CPU time 19.96 seconds
Started Oct 15 12:34:22 PM PDT 23
Finished Oct 15 12:34:43 PM PDT 23
Peak memory 212880 kb
Host smart-aaa52bff-f254-4065-86af-a2ca44ddcdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837423517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.837423517
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.774303094
Short name T108
Test name
Test status
Simulation time 24169340043 ps
CPU time 106.62 seconds
Started Oct 15 12:34:19 PM PDT 23
Finished Oct 15 12:36:07 PM PDT 23
Peak memory 219292 kb
Host smart-8f436a53-81c1-4de7-9729-598bcd32b0e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774303094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.774303094
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2445204824
Short name T260
Test name
Test status
Simulation time 311941665 ps
CPU time 6.35 seconds
Started Oct 15 12:34:30 PM PDT 23
Finished Oct 15 12:34:36 PM PDT 23
Peak memory 210956 kb
Host smart-06677045-5051-40ba-8ccc-d54c690c682f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445204824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2445204824
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.996290092
Short name T243
Test name
Test status
Simulation time 33241106884 ps
CPU time 150.28 seconds
Started Oct 15 12:34:23 PM PDT 23
Finished Oct 15 12:36:54 PM PDT 23
Peak memory 237704 kb
Host smart-86dfdad0-779d-45b5-b0ea-5fcebb70f98a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996290092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.996290092
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1888047172
Short name T285
Test name
Test status
Simulation time 1737425070 ps
CPU time 20.39 seconds
Started Oct 15 12:34:07 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 210984 kb
Host smart-f00c51ff-6e60-4e4b-95f7-587519bc1f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888047172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1888047172
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.273485265
Short name T350
Test name
Test status
Simulation time 1736991197 ps
CPU time 14.87 seconds
Started Oct 15 12:34:55 PM PDT 23
Finished Oct 15 12:35:11 PM PDT 23
Peak memory 210960 kb
Host smart-cc655428-41ca-43db-8299-4afb8ff0c311
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273485265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.273485265
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.4088648863
Short name T377
Test name
Test status
Simulation time 1086761563 ps
CPU time 17.79 seconds
Started Oct 15 12:34:38 PM PDT 23
Finished Oct 15 12:34:56 PM PDT 23
Peak memory 212448 kb
Host smart-3fc82092-a6e6-4748-bc23-9ff0680b199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088648863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.4088648863
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.869618145
Short name T388
Test name
Test status
Simulation time 2821485884 ps
CPU time 37.32 seconds
Started Oct 15 12:34:30 PM PDT 23
Finished Oct 15 12:35:08 PM PDT 23
Peak memory 215544 kb
Host smart-459de68b-40a1-47be-9742-85dc63e6b734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869618145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.869618145
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3720511322
Short name T195
Test name
Test status
Simulation time 3699895448 ps
CPU time 14.75 seconds
Started Oct 15 12:33:12 PM PDT 23
Finished Oct 15 12:33:27 PM PDT 23
Peak memory 211136 kb
Host smart-128288b5-76d9-4641-8313-788595572532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720511322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3720511322
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1640845297
Short name T251
Test name
Test status
Simulation time 13699681226 ps
CPU time 181.5 seconds
Started Oct 15 12:34:03 PM PDT 23
Finished Oct 15 12:37:05 PM PDT 23
Peak memory 236660 kb
Host smart-a5c74935-9ed6-4c4a-942f-805c58bcb0e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640845297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1640845297
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2735874009
Short name T323
Test name
Test status
Simulation time 15620707083 ps
CPU time 32.9 seconds
Started Oct 15 12:33:41 PM PDT 23
Finished Oct 15 12:34:15 PM PDT 23
Peak memory 211384 kb
Host smart-575db506-3ce8-4910-a0fb-833f0e540688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735874009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2735874009
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1418136565
Short name T362
Test name
Test status
Simulation time 379964324 ps
CPU time 5.7 seconds
Started Oct 15 12:33:20 PM PDT 23
Finished Oct 15 12:33:26 PM PDT 23
Peak memory 211152 kb
Host smart-c776abde-4de7-4d44-b078-2825176d8d86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418136565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1418136565
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.4231896684
Short name T4
Test name
Test status
Simulation time 21827568338 ps
CPU time 27.17 seconds
Started Oct 15 12:33:51 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 213428 kb
Host smart-cd53c69a-6a3a-4188-8a8a-817e9f61ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231896684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.4231896684
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.753842168
Short name T334
Test name
Test status
Simulation time 36558464084 ps
CPU time 75.84 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:35:29 PM PDT 23
Peak memory 217044 kb
Host smart-d64493b4-5287-4139-8ef8-9356fc26a7f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753842168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.753842168
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.51140801
Short name T329
Test name
Test status
Simulation time 826967493 ps
CPU time 4.44 seconds
Started Oct 15 12:33:28 PM PDT 23
Finished Oct 15 12:33:33 PM PDT 23
Peak memory 210908 kb
Host smart-880f423b-8e66-4b46-9655-7b9ec10dbd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51140801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.51140801
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1309012896
Short name T309
Test name
Test status
Simulation time 73604413915 ps
CPU time 658.24 seconds
Started Oct 15 12:33:25 PM PDT 23
Finished Oct 15 12:44:24 PM PDT 23
Peak memory 213304 kb
Host smart-c6024200-32b3-4556-a1d0-394ba4c9a37d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309012896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1309012896
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2614353378
Short name T161
Test name
Test status
Simulation time 829426644 ps
CPU time 14.79 seconds
Started Oct 15 12:33:50 PM PDT 23
Finished Oct 15 12:34:06 PM PDT 23
Peak memory 211372 kb
Host smart-b9c702d6-be96-436d-a637-2c2250f5aaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614353378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2614353378
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.2246195162
Short name T207
Test name
Test status
Simulation time 2289165520 ps
CPU time 17.84 seconds
Started Oct 15 12:33:44 PM PDT 23
Finished Oct 15 12:34:02 PM PDT 23
Peak memory 211044 kb
Host smart-c07ff9db-b86c-48fd-89d4-8242aeceb9a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246195162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.2246195162
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1912436217
Short name T290
Test name
Test status
Simulation time 3793648192 ps
CPU time 35.35 seconds
Started Oct 15 12:33:29 PM PDT 23
Finished Oct 15 12:34:05 PM PDT 23
Peak memory 212956 kb
Host smart-2cc45ee4-3d51-44ca-b21e-4f6c6b9bc6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912436217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1912436217
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1762481975
Short name T421
Test name
Test status
Simulation time 16248557679 ps
CPU time 156.04 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:36:10 PM PDT 23
Peak memory 219304 kb
Host smart-3154b65a-405c-4882-b5c8-e02676a32c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762481975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1762481975
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2503317852
Short name T186
Test name
Test status
Simulation time 20869732644 ps
CPU time 1298.24 seconds
Started Oct 15 12:33:55 PM PDT 23
Finished Oct 15 12:55:33 PM PDT 23
Peak memory 235096 kb
Host smart-19dad38a-a7d0-4916-a970-dc4eb1a2ad8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503317852 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2503317852
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1029507524
Short name T41
Test name
Test status
Simulation time 3774244808 ps
CPU time 10.24 seconds
Started Oct 15 12:33:35 PM PDT 23
Finished Oct 15 12:33:46 PM PDT 23
Peak memory 211056 kb
Host smart-50a5f24d-269a-4a0b-a00d-faffda452795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029507524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1029507524
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.4202076509
Short name T403
Test name
Test status
Simulation time 3524698914 ps
CPU time 101.6 seconds
Started Oct 15 12:33:15 PM PDT 23
Finished Oct 15 12:34:57 PM PDT 23
Peak memory 236664 kb
Host smart-afabdc32-4926-446e-a935-9036d034900d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202076509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.4202076509
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.283301336
Short name T152
Test name
Test status
Simulation time 4179081605 ps
CPU time 33.2 seconds
Started Oct 15 12:33:48 PM PDT 23
Finished Oct 15 12:34:21 PM PDT 23
Peak memory 211252 kb
Host smart-ecfebba0-29e5-42c0-8e1d-9607a92aa559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283301336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.283301336
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3906433522
Short name T410
Test name
Test status
Simulation time 189353331 ps
CPU time 5.41 seconds
Started Oct 15 12:33:47 PM PDT 23
Finished Oct 15 12:33:53 PM PDT 23
Peak memory 210980 kb
Host smart-c4551113-6943-481c-93c1-6a9a7b4e5990
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3906433522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3906433522
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3368715079
Short name T214
Test name
Test status
Simulation time 271314840 ps
CPU time 11.88 seconds
Started Oct 15 12:33:20 PM PDT 23
Finished Oct 15 12:33:33 PM PDT 23
Peak memory 212608 kb
Host smart-7a8dcf2d-cdf5-4dbf-866e-683341f57079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368715079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3368715079
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2342092569
Short name T306
Test name
Test status
Simulation time 1629722213 ps
CPU time 20.41 seconds
Started Oct 15 12:33:33 PM PDT 23
Finished Oct 15 12:33:54 PM PDT 23
Peak memory 211292 kb
Host smart-e564c0b8-fe02-49ea-9df4-a5140d34e872
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342092569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2342092569
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1177496278
Short name T398
Test name
Test status
Simulation time 21534581620 ps
CPU time 2046.36 seconds
Started Oct 15 12:33:18 PM PDT 23
Finished Oct 15 01:07:25 PM PDT 23
Peak memory 234348 kb
Host smart-144cc4f1-0497-4aa0-975b-6a5ef642cc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177496278 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1177496278
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3547086816
Short name T407
Test name
Test status
Simulation time 254153885 ps
CPU time 6.18 seconds
Started Oct 15 12:33:27 PM PDT 23
Finished Oct 15 12:33:33 PM PDT 23
Peak memory 210992 kb
Host smart-c7d96d13-846b-48ac-b5ad-795f75c84974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547086816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3547086816
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1594409224
Short name T318
Test name
Test status
Simulation time 252273618743 ps
CPU time 572.62 seconds
Started Oct 15 12:33:11 PM PDT 23
Finished Oct 15 12:42:45 PM PDT 23
Peak memory 225600 kb
Host smart-1540e86e-ad71-4129-bc2e-6a6e283a5e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594409224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1594409224
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1932140582
Short name T340
Test name
Test status
Simulation time 690571914 ps
CPU time 11.87 seconds
Started Oct 15 12:33:48 PM PDT 23
Finished Oct 15 12:34:00 PM PDT 23
Peak memory 210248 kb
Host smart-2d318b25-794d-415f-9d1b-b84c0ea14532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932140582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1932140582
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3142108684
Short name T192
Test name
Test status
Simulation time 189608873 ps
CPU time 5.63 seconds
Started Oct 15 12:33:44 PM PDT 23
Finished Oct 15 12:33:50 PM PDT 23
Peak memory 210952 kb
Host smart-bd6ad921-6382-426a-b4d4-20ea0218b32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142108684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3142108684
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.664391022
Short name T219
Test name
Test status
Simulation time 3445014958 ps
CPU time 20.09 seconds
Started Oct 15 12:34:35 PM PDT 23
Finished Oct 15 12:34:56 PM PDT 23
Peak memory 212928 kb
Host smart-81ad5813-faed-401a-b08e-753d76152a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664391022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.664391022
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3979412890
Short name T404
Test name
Test status
Simulation time 1511369040 ps
CPU time 16.72 seconds
Started Oct 15 12:34:30 PM PDT 23
Finished Oct 15 12:34:47 PM PDT 23
Peak memory 212856 kb
Host smart-b9056e0d-df61-4133-b1f2-2fb71d5dbdd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979412890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3979412890
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3112795827
Short name T395
Test name
Test status
Simulation time 47439778333 ps
CPU time 2063.71 seconds
Started Oct 15 12:33:40 PM PDT 23
Finished Oct 15 01:08:04 PM PDT 23
Peak memory 235672 kb
Host smart-19746c7a-b10b-45c5-809a-d1448285732b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112795827 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3112795827
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1338962672
Short name T268
Test name
Test status
Simulation time 8595303872 ps
CPU time 16.04 seconds
Started Oct 15 12:33:14 PM PDT 23
Finished Oct 15 12:33:31 PM PDT 23
Peak memory 211032 kb
Host smart-0226160f-c377-482f-bd60-349caf8b24b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338962672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1338962672
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1135711867
Short name T320
Test name
Test status
Simulation time 39580678904 ps
CPU time 177.45 seconds
Started Oct 15 12:33:44 PM PDT 23
Finished Oct 15 12:36:41 PM PDT 23
Peak memory 228412 kb
Host smart-09a41e2d-8324-4b11-8722-61b0c0266902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135711867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1135711867
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2389553730
Short name T252
Test name
Test status
Simulation time 666993494 ps
CPU time 9.21 seconds
Started Oct 15 12:33:49 PM PDT 23
Finished Oct 15 12:33:59 PM PDT 23
Peak memory 211124 kb
Host smart-3887cf7a-d39a-4c74-9186-2d34ba9a6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389553730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2389553730
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3949814399
Short name T412
Test name
Test status
Simulation time 137100414 ps
CPU time 5.66 seconds
Started Oct 15 12:33:56 PM PDT 23
Finished Oct 15 12:34:02 PM PDT 23
Peak memory 210952 kb
Host smart-875aaa0d-c796-4169-8a50-63acc729c9e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949814399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3949814399
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.994371680
Short name T187
Test name
Test status
Simulation time 8024925595 ps
CPU time 37.45 seconds
Started Oct 15 12:33:39 PM PDT 23
Finished Oct 15 12:34:17 PM PDT 23
Peak memory 213364 kb
Host smart-bf08a2ab-760c-48d7-9f4e-ad0a92b0f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994371680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.994371680
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2331643309
Short name T305
Test name
Test status
Simulation time 627756848 ps
CPU time 15.59 seconds
Started Oct 15 12:33:21 PM PDT 23
Finished Oct 15 12:33:37 PM PDT 23
Peak memory 212284 kb
Host smart-1ece559a-e317-4aa1-a092-16292899626f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331643309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2331643309
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1320638620
Short name T235
Test name
Test status
Simulation time 125281597252 ps
CPU time 4218.27 seconds
Started Oct 15 12:34:13 PM PDT 23
Finished Oct 15 01:44:32 PM PDT 23
Peak memory 231736 kb
Host smart-0c8602df-8c65-4b56-b163-4c18d2714167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320638620 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1320638620
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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