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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T255 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.46052458639237884331556330878027649046372105795203314218593380028052580517045 Oct 18 12:25:54 PM PDT 23 Oct 18 12:26:07 PM PDT 23 3151732636 ps
T256 /workspace/coverage/default/22.rom_ctrl_stress_all.50031563144917162911289720612400803935655657646103383495531039480025114246787 Oct 18 12:29:41 PM PDT 23 Oct 18 12:30:23 PM PDT 23 9415977006 ps
T257 /workspace/coverage/default/46.rom_ctrl_alert_test.52047752663387721506191691204186107741210298112215073952842161628497415348895 Oct 18 12:24:57 PM PDT 23 Oct 18 12:25:10 PM PDT 23 3124113076 ps
T258 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.71746081440993430607377736586298441927236056686696235533766501598933205935151 Oct 18 12:28:20 PM PDT 23 Oct 18 12:33:58 PM PDT 23 69854280986 ps
T259 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.13403251205521674859563178778132770151566346927438799256475285461974278844988 Oct 18 12:29:01 PM PDT 23 Oct 18 12:29:16 PM PDT 23 3151732636 ps
T260 /workspace/coverage/default/21.rom_ctrl_alert_test.31334746073840417201797587990996454665391268285934037301388390607692655487790 Oct 18 12:27:49 PM PDT 23 Oct 18 12:28:01 PM PDT 23 3124113076 ps
T261 /workspace/coverage/default/2.rom_ctrl_alert_test.8075910023657294375923734462071388096122901019251026801906069099046839475344 Oct 18 12:27:37 PM PDT 23 Oct 18 12:27:49 PM PDT 23 3124113076 ps
T262 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.47001371200429504667049149029407149857825162885426948970737836314457582520691 Oct 18 12:26:15 PM PDT 23 Oct 18 12:26:41 PM PDT 23 6233818126 ps
T263 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.47327079387275159245872037368517708968560182764377637451077706392769931236961 Oct 18 12:26:02 PM PDT 23 Oct 18 12:26:16 PM PDT 23 3151732636 ps
T264 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.106593006359081372590530363320396333753421412118072941068922386229344899634833 Oct 18 12:27:01 PM PDT 23 Oct 18 12:27:16 PM PDT 23 3151732636 ps
T265 /workspace/coverage/default/40.rom_ctrl_stress_all.55638746558377344699854295334072267241911502405242844046431051875807242270982 Oct 18 12:24:05 PM PDT 23 Oct 18 12:24:50 PM PDT 23 9415977006 ps
T266 /workspace/coverage/default/38.rom_ctrl_stress_all.38540340665364921978332611748820842329833998955613534371754398985638736182303 Oct 18 12:26:08 PM PDT 23 Oct 18 12:26:51 PM PDT 23 9415977006 ps
T267 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.109008404845242402679155592371732183717331166594003257153099813604482863787695 Oct 18 12:27:29 PM PDT 23 Oct 18 12:27:42 PM PDT 23 3151732636 ps
T268 /workspace/coverage/default/32.rom_ctrl_stress_all.73794010856683722378855488402918759103804863656012169758721791533056502554042 Oct 18 12:28:10 PM PDT 23 Oct 18 12:28:52 PM PDT 23 9415977006 ps
T269 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.43041468698756746066892785137179634304166536388386320467294547549634366911919 Oct 18 12:27:24 PM PDT 23 Oct 18 12:27:50 PM PDT 23 6233818126 ps
T270 /workspace/coverage/default/37.rom_ctrl_smoke.83748862736120490553727817320205496206534963146321760813349408047954120851913 Oct 18 12:28:28 PM PDT 23 Oct 18 12:28:56 PM PDT 23 6265461576 ps
T271 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.8685680934972102793319122209240219805348413989637442920151341394271906864267 Oct 18 12:22:54 PM PDT 23 Oct 18 12:23:20 PM PDT 23 6233818126 ps
T272 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.106353760038440649660551754768141804294952695373621342928944908156068917066201 Oct 18 12:27:35 PM PDT 23 Oct 18 12:28:01 PM PDT 23 6233818126 ps
T273 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.34841222180344027739061698565054180012707621973345436432076328594104366046419 Oct 18 12:27:29 PM PDT 23 Oct 18 12:33:04 PM PDT 23 69854280986 ps
T274 /workspace/coverage/default/44.rom_ctrl_smoke.59308669398023017633519044147806215766362940333932548451556331126868734183986 Oct 18 12:26:41 PM PDT 23 Oct 18 12:27:10 PM PDT 23 6265461576 ps
T275 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.60161711906103933143286800030068879740799737976035463457598330842447901637695 Oct 18 12:26:51 PM PDT 23 Oct 18 12:27:18 PM PDT 23 6233818126 ps
T276 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.33215469199478692467966090719501214924010638328079780378982255648083422219815 Oct 18 12:25:59 PM PDT 23 Oct 18 12:26:13 PM PDT 23 3151732636 ps
T277 /workspace/coverage/default/31.rom_ctrl_stress_all.24294868436286598217933273315085106319279428198820995096405811776674610039077 Oct 18 12:25:48 PM PDT 23 Oct 18 12:26:32 PM PDT 23 9415977006 ps
T278 /workspace/coverage/default/22.rom_ctrl_alert_test.103889008687492579461048853189993728643183121826798880783198204600409343672145 Oct 18 12:25:33 PM PDT 23 Oct 18 12:25:46 PM PDT 23 3124113076 ps
T279 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.7615367351821730081843656033011968283987793738164442666889698638923140446555 Oct 18 12:25:34 PM PDT 23 Oct 18 12:25:48 PM PDT 23 3151732636 ps
T280 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.38281554543325166162283622620359808421543675589694644522051928456577479202171 Oct 18 12:28:17 PM PDT 23 Oct 18 12:28:31 PM PDT 23 3151732636 ps
T281 /workspace/coverage/default/25.rom_ctrl_stress_all.43507614170193820465381847881526464055358510408904844244081221131237897396621 Oct 18 12:27:41 PM PDT 23 Oct 18 12:28:28 PM PDT 23 9415977006 ps
T282 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.113051297793238686289028056367065993282423340230913877498129396308362810830941 Oct 18 12:29:15 PM PDT 23 Oct 18 12:29:28 PM PDT 23 3151732636 ps
T283 /workspace/coverage/default/38.rom_ctrl_alert_test.32666579411059531629684671964075802590018503959929287950419111962042519117122 Oct 18 12:27:54 PM PDT 23 Oct 18 12:28:07 PM PDT 23 3124113076 ps
T284 /workspace/coverage/default/27.rom_ctrl_alert_test.94815471045390771489337710133998957450348122013323729227436132868620964187208 Oct 18 12:26:15 PM PDT 23 Oct 18 12:26:28 PM PDT 23 3124113076 ps
T285 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.50011671590096477659821234260012670518041158876754850324469603782254178269026 Oct 18 12:26:12 PM PDT 23 Oct 18 12:26:37 PM PDT 23 6233818126 ps
T286 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.36641099575646819832645365005029473634882662329243884816615012329728109437137 Oct 18 12:24:24 PM PDT 23 Oct 18 12:30:12 PM PDT 23 69854280986 ps
T287 /workspace/coverage/default/44.rom_ctrl_alert_test.30162075760855233296155846035667327223164519075685253129518661797166043375157 Oct 18 12:26:21 PM PDT 23 Oct 18 12:26:34 PM PDT 23 3124113076 ps
T288 /workspace/coverage/default/20.rom_ctrl_stress_all.35720427669713264193516616660459557380749333360549894048249261516352808279840 Oct 18 12:26:06 PM PDT 23 Oct 18 12:26:49 PM PDT 23 9415977006 ps
T289 /workspace/coverage/default/25.rom_ctrl_smoke.92612064971052843021919622032823218159336958752081055724945828721313168425003 Oct 18 12:28:07 PM PDT 23 Oct 18 12:28:35 PM PDT 23 6265461576 ps
T290 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.18519492676090412987314932371550693554847507720726962038887043444685954911894 Oct 18 12:21:24 PM PDT 23 Oct 18 12:21:50 PM PDT 23 6233818126 ps
T291 /workspace/coverage/default/31.rom_ctrl_alert_test.47198024166090287052760071631353737283019362635582318102272554768795481618336 Oct 18 12:25:21 PM PDT 23 Oct 18 12:25:34 PM PDT 23 3124113076 ps
T292 /workspace/coverage/default/9.rom_ctrl_alert_test.31611047141479599114701907123956589595326556961137694337874015928280906693413 Oct 18 12:30:35 PM PDT 23 Oct 18 12:30:48 PM PDT 23 3124113076 ps
T293 /workspace/coverage/default/38.rom_ctrl_smoke.28709022678815705583380739160988730089640430703239345751329967805852865054722 Oct 18 12:26:49 PM PDT 23 Oct 18 12:27:17 PM PDT 23 6265461576 ps
T294 /workspace/coverage/default/30.rom_ctrl_stress_all.5766954460049267094226074066696791737381433153675987361939937315778407946452 Oct 18 12:23:14 PM PDT 23 Oct 18 12:24:00 PM PDT 23 9415977006 ps
T295 /workspace/coverage/default/47.rom_ctrl_stress_all.32354461203561707990071448987465217831041594454700760630490218209010943092118 Oct 18 12:26:53 PM PDT 23 Oct 18 12:27:37 PM PDT 23 9415977006 ps
T296 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.18175934877748570825408704963339310287785698123104370073775530894193586182340 Oct 18 12:25:56 PM PDT 23 Oct 18 12:26:22 PM PDT 23 6233818126 ps
T297 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.46963388613274874865734800441934235501424921826890392619099401666098999114848 Oct 18 12:30:55 PM PDT 23 Oct 18 12:36:38 PM PDT 23 69854280986 ps
T298 /workspace/coverage/default/39.rom_ctrl_stress_all.63276533902910149318829273679182141092826552732155470616609771259490412972385 Oct 18 12:28:06 PM PDT 23 Oct 18 12:28:49 PM PDT 23 9415977006 ps
T299 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.29136986637758506603256037311886511128681196615884960736696381978542540340418 Oct 18 12:26:59 PM PDT 23 Oct 18 12:32:31 PM PDT 23 69854280986 ps
T300 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.69753331940148627569118180114005801656113629416221165638980497761281925636499 Oct 18 12:28:13 PM PDT 23 Oct 18 12:33:55 PM PDT 23 69854280986 ps
T301 /workspace/coverage/default/40.rom_ctrl_alert_test.63002455573009043408328079857673113771631385937735999816938396104427610737462 Oct 18 12:26:05 PM PDT 23 Oct 18 12:26:18 PM PDT 23 3124113076 ps
T302 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.53934919908493955796878342790945801382783696210108024522864031758537982366069 Oct 18 12:26:38 PM PDT 23 Oct 18 12:27:03 PM PDT 23 6233818126 ps
T303 /workspace/coverage/default/12.rom_ctrl_stress_all.34353196501606020526605650528023884416451374588064099560909821755296843959528 Oct 18 12:32:43 PM PDT 23 Oct 18 12:33:26 PM PDT 23 9415977006 ps
T304 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.76357540123781037950096157673811022708109092584235785543134832079696651399043 Oct 18 12:30:31 PM PDT 23 Oct 18 12:36:13 PM PDT 23 69854280986 ps
T305 /workspace/coverage/default/17.rom_ctrl_alert_test.19782395960344337247013630300192153381397738043116405967260451950834197732426 Oct 18 12:26:08 PM PDT 23 Oct 18 12:26:21 PM PDT 23 3124113076 ps
T306 /workspace/coverage/default/1.rom_ctrl_alert_test.74032136880188780385260895180115337697616161449561548684130019678741963296170 Oct 18 12:25:14 PM PDT 23 Oct 18 12:25:27 PM PDT 23 3124113076 ps
T307 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.55820032197762037108103931879044354459793050941619685828467193685533584342248 Oct 18 12:27:29 PM PDT 23 Oct 18 12:33:02 PM PDT 23 69854280986 ps
T308 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.28252529011989240085151489213624521780640595984439606028617906245154811263515 Oct 18 12:33:20 PM PDT 23 Oct 18 12:33:46 PM PDT 23 6233818126 ps
T309 /workspace/coverage/default/41.rom_ctrl_stress_all.45047391510957282467794202423606547355621654411110807642031086465149999711799 Oct 18 12:27:28 PM PDT 23 Oct 18 12:28:10 PM PDT 23 9415977006 ps
T310 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.92285190260186966746282419900537443812964117870245348051590520680356533118844 Oct 18 12:26:12 PM PDT 23 Oct 18 12:31:50 PM PDT 23 69854280986 ps
T311 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.51805216077144397519842705634330900285715336682691507045804107903076420848187 Oct 18 12:40:31 PM PDT 23 Oct 18 12:40:57 PM PDT 23 6233818126 ps
T312 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.10606611974129725522584919021244875037505416380636177975387033333511368390802 Oct 18 12:27:50 PM PDT 23 Oct 18 12:33:31 PM PDT 23 69854280986 ps
T313 /workspace/coverage/default/3.rom_ctrl_stress_all.18610259784827173405860390159977680134070026195546688990028814655604526825936 Oct 18 12:21:24 PM PDT 23 Oct 18 12:22:08 PM PDT 23 9415977006 ps
T314 /workspace/coverage/default/23.rom_ctrl_smoke.61503804846929248051624065946106017191297112009023648356644708355954005140821 Oct 18 12:25:33 PM PDT 23 Oct 18 12:26:01 PM PDT 23 6265461576 ps
T315 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.50961519291933381754371858903888648009295491024108214686528943870041408987525 Oct 18 12:35:12 PM PDT 23 Oct 18 12:35:26 PM PDT 23 3151732636 ps
T316 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.77139953488220074833112039760792478222373015918584400642822135711907460599618 Oct 18 12:25:30 PM PDT 23 Oct 18 12:31:06 PM PDT 23 69854280986 ps
T317 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.15543864281235750257131551475388167883255877008403115643294658097787422706504 Oct 18 12:27:32 PM PDT 23 Oct 18 12:33:13 PM PDT 23 69854280986 ps
T318 /workspace/coverage/default/6.rom_ctrl_smoke.90642330756452547332936564742684005448800981223834349902496866572675858060385 Oct 18 12:28:16 PM PDT 23 Oct 18 12:28:44 PM PDT 23 6265461576 ps
T319 /workspace/coverage/default/24.rom_ctrl_smoke.106008788872681495348704806074628394943907391807560750632371651366826235943355 Oct 18 12:25:33 PM PDT 23 Oct 18 12:26:02 PM PDT 23 6265461576 ps
T320 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.73417865243965386805890820452540170967007887515154219230332533488594391306002 Oct 18 12:27:56 PM PDT 23 Oct 18 12:33:36 PM PDT 23 69854280986 ps
T321 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.39216764590472406933660798803637514601566244570648453296741510502206237686896 Oct 18 12:26:12 PM PDT 23 Oct 18 12:26:38 PM PDT 23 6233818126 ps
T32 /workspace/coverage/default/4.rom_ctrl_sec_cm.33146722127117040026174522249312357617892031060565714253622971378799997941371 Oct 18 12:26:49 PM PDT 23 Oct 18 12:28:47 PM PDT 23 3444857586 ps
T322 /workspace/coverage/default/28.rom_ctrl_alert_test.10550902172168126622887420652236518942061159936903193050826640221569166822959 Oct 18 12:26:11 PM PDT 23 Oct 18 12:26:24 PM PDT 23 3124113076 ps
T323 /workspace/coverage/default/14.rom_ctrl_stress_all.80915039510687636437474854684476398098332184997411960241785802876198793530428 Oct 18 12:36:41 PM PDT 23 Oct 18 12:37:25 PM PDT 23 9415977006 ps
T324 /workspace/coverage/default/3.rom_ctrl_alert_test.18314737517694558417949049652673550801344671233490819211949748501998345750957 Oct 18 12:29:44 PM PDT 23 Oct 18 12:29:57 PM PDT 23 3124113076 ps
T325 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.96106613505927001958135213950422658716155586329049938346453331106836646361520 Oct 18 12:27:28 PM PDT 23 Oct 18 12:27:54 PM PDT 23 6233818126 ps
T326 /workspace/coverage/default/11.rom_ctrl_smoke.111357685913146402549672784399460674561566375907630796316638242927851525954478 Oct 18 12:25:53 PM PDT 23 Oct 18 12:26:22 PM PDT 23 6265461576 ps
T327 /workspace/coverage/default/0.rom_ctrl_alert_test.66636143593620182789227885784840977687230767150020820369193006837437519512535 Oct 18 12:25:16 PM PDT 23 Oct 18 12:25:29 PM PDT 23 3124113076 ps
T328 /workspace/coverage/default/18.rom_ctrl_smoke.45902984530388782170818914208786879467048234351946725282558292092031470007196 Oct 18 12:36:42 PM PDT 23 Oct 18 12:37:10 PM PDT 23 6265461576 ps
T329 /workspace/coverage/default/49.rom_ctrl_smoke.68756759881485647521483856726124479991992115026496971907432195000319790248270 Oct 18 12:26:08 PM PDT 23 Oct 18 12:26:37 PM PDT 23 6265461576 ps
T330 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.73436344660075094863580118298038824053861094980031835256463969329133347709908 Oct 18 12:27:30 PM PDT 23 Oct 18 12:27:44 PM PDT 23 3151732636 ps
T331 /workspace/coverage/default/1.rom_ctrl_smoke.20169549910070710528264924161159178358974830656621902819247766055232682386533 Oct 18 12:22:37 PM PDT 23 Oct 18 12:23:06 PM PDT 23 6265461576 ps
T332 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.63772822416624621366876597190210749496240096411759873928604209724515839723891 Oct 18 12:25:01 PM PDT 23 Oct 18 12:30:45 PM PDT 23 69854280986 ps
T333 /workspace/coverage/default/26.rom_ctrl_alert_test.78279273885136098149885977238191297121992576435467602434119252149966896521361 Oct 18 12:27:56 PM PDT 23 Oct 18 12:28:09 PM PDT 23 3124113076 ps
T334 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.88441564882739312486708940089599622889661522279007385790736847130950197784286 Oct 18 12:26:06 PM PDT 23 Oct 18 12:26:19 PM PDT 23 3151732636 ps
T335 /workspace/coverage/default/37.rom_ctrl_alert_test.110118168673819274462373008706260461329637721926185783412635433520013127385024 Oct 18 12:27:38 PM PDT 23 Oct 18 12:27:51 PM PDT 23 3124113076 ps
T336 /workspace/coverage/default/2.rom_ctrl_stress_all.74862208963433039146667752564950905307528823198931652298438782601006668301160 Oct 18 12:22:40 PM PDT 23 Oct 18 12:23:23 PM PDT 23 9415977006 ps
T337 /workspace/coverage/default/43.rom_ctrl_alert_test.6858598967620650020729740002553099458181643725714336783190022453486662320000 Oct 18 12:26:44 PM PDT 23 Oct 18 12:26:56 PM PDT 23 3124113076 ps
T338 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.115258865824919728021387830141946096690863186393505514228524768465318147874704 Oct 18 12:25:51 PM PDT 23 Oct 18 12:31:29 PM PDT 23 69854280986 ps
T339 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.8123621901262964766180612811528652597555525030691353180353027242957643808073 Oct 18 12:27:52 PM PDT 23 Oct 18 12:28:06 PM PDT 23 3151732636 ps
T340 /workspace/coverage/default/4.rom_ctrl_smoke.99037438243306506265123289041347679205799037351407469091590526725707838462504 Oct 18 12:28:19 PM PDT 23 Oct 18 12:28:47 PM PDT 23 6265461576 ps
T341 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.19690247002594655042735198460370594303033378555786669877862248166720718484663 Oct 18 12:26:37 PM PDT 23 Oct 18 12:26:51 PM PDT 23 3151732636 ps
T342 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.18647276430820176147852795177245701722814421631864932971041356193752682704875 Oct 18 12:27:29 PM PDT 23 Oct 18 12:27:42 PM PDT 23 3151732636 ps
T343 /workspace/coverage/default/17.rom_ctrl_stress_all.77127515420766017163390053831601039277430954621614215011793321455400793903350 Oct 18 12:29:47 PM PDT 23 Oct 18 12:30:29 PM PDT 23 9415977006 ps
T344 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.83295947239638762653292642487841716730534596942138778244804939167292312276060 Oct 18 12:26:06 PM PDT 23 Oct 18 12:31:41 PM PDT 23 69854280986 ps
T345 /workspace/coverage/default/27.rom_ctrl_smoke.107008541538639775103240320201911175167945048731059414456834994409309863682678 Oct 18 12:26:11 PM PDT 23 Oct 18 12:26:41 PM PDT 23 6265461576 ps
T346 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.48373310918464815557155137505625881468572400468493627131327941021917051709895 Oct 18 12:26:21 PM PDT 23 Oct 18 12:26:35 PM PDT 23 3151732636 ps
T347 /workspace/coverage/default/19.rom_ctrl_smoke.113877360459186982993887278156514532663163365783324055406917387794870698698949 Oct 18 12:29:46 PM PDT 23 Oct 18 12:30:14 PM PDT 23 6265461576 ps
T348 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.78661556208792549032817346307770646159546341831122108710096114750942393354524 Oct 18 12:26:37 PM PDT 23 Oct 18 12:32:14 PM PDT 23 69854280986 ps
T349 /workspace/coverage/default/14.rom_ctrl_smoke.33972623378962478282778776760807621592296911847541711302573570855053238911565 Oct 18 12:26:09 PM PDT 23 Oct 18 12:26:38 PM PDT 23 6265461576 ps
T350 /workspace/coverage/default/45.rom_ctrl_smoke.95538875392790639094322516289945769496594786543130501827743828000559750020439 Oct 18 12:26:14 PM PDT 23 Oct 18 12:26:43 PM PDT 23 6265461576 ps
T351 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.79899161803765064360656080976534100507535963600830706785132279449662252658085 Oct 18 12:27:28 PM PDT 23 Oct 18 12:33:01 PM PDT 23 69854280986 ps
T352 /workspace/coverage/default/6.rom_ctrl_stress_all.33418691239580477436704908087917747771040703318230885816778255985309485847983 Oct 18 12:27:40 PM PDT 23 Oct 18 12:28:22 PM PDT 23 9415977006 ps
T353 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.100771431102907751424257502009679423183675043462773078805643341089674588057273 Oct 18 12:27:19 PM PDT 23 Oct 18 12:33:02 PM PDT 23 69854280986 ps
T354 /workspace/coverage/default/5.rom_ctrl_stress_all.101231524568719805779705929845294844120433206045757987966323637701087356594491 Oct 18 12:27:38 PM PDT 23 Oct 18 12:28:21 PM PDT 23 9415977006 ps
T355 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.80984221063610528913542852362743642081907750101355165109015756178064209774362 Oct 18 12:21:25 PM PDT 23 Oct 18 12:27:10 PM PDT 23 69854280986 ps
T356 /workspace/coverage/default/42.rom_ctrl_smoke.69799311987629528354936581983988860383478894095655070639685069088848758600513 Oct 18 12:24:49 PM PDT 23 Oct 18 12:25:17 PM PDT 23 6265461576 ps
T357 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.18022997598009402832224848796653901360662716599285495112274456822175900190436 Oct 18 12:28:13 PM PDT 23 Oct 18 12:28:38 PM PDT 23 6233818126 ps
T358 /workspace/coverage/default/20.rom_ctrl_alert_test.55847528363615500312379981683943519876773303541807802962677887405898501105112 Oct 18 12:25:50 PM PDT 23 Oct 18 12:26:02 PM PDT 23 3124113076 ps
T359 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.24977848824230751497539078437073830034361210969972836332079765016589724231028 Oct 18 01:34:50 PM PDT 23 Oct 18 01:35:02 PM PDT 23 3135422826 ps
T360 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.56011179875242692285603472339442498111977919945927524199393495067547778693178 Oct 18 01:34:23 PM PDT 23 Oct 18 01:34:38 PM PDT 23 3142303916 ps
T361 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.84353695148136854110691208900423480770266908890870873006673532875920804881485 Oct 18 01:33:25 PM PDT 23 Oct 18 01:34:46 PM PDT 23 3476453456 ps
T362 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.41312495295093241212948737703891098354762075403588449569494704229104175341485 Oct 18 01:34:06 PM PDT 23 Oct 18 01:34:19 PM PDT 23 3135422826 ps
T363 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.84120736027830832990379075304715007644176629563061845521564229669426951722067 Oct 18 01:33:32 PM PDT 23 Oct 18 01:33:44 PM PDT 23 3124113076 ps
T364 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.49044090199471624250673506737680958577528714626912683830602117801177135696576 Oct 18 01:33:55 PM PDT 23 Oct 18 01:34:08 PM PDT 23 3135422826 ps
T365 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.31881294165363230754730042156449692664239974901292221974008408289565354109014 Oct 18 01:34:03 PM PDT 23 Oct 18 01:35:24 PM PDT 23 3476453456 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.14416638692809249146571097606518721573086608737281731062187547825820562974090 Oct 18 01:33:15 PM PDT 23 Oct 18 01:33:28 PM PDT 23 3124113076 ps
T367 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.51939026572348591343891392880503445325531998436140399276840630318891096894564 Oct 18 01:33:27 PM PDT 23 Oct 18 01:34:48 PM PDT 23 3476453456 ps
T368 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.88946790070346025470397961985688854187588323911935225133740786022983923775156 Oct 18 01:34:07 PM PDT 23 Oct 18 01:34:21 PM PDT 23 3142303916 ps
T369 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.19868391328642317415001457906403691038727240189822446904374719642273093916658 Oct 18 01:34:21 PM PDT 23 Oct 18 01:34:36 PM PDT 23 3142303916 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.107586244678966089696290169914950843544985196943449878356218733860772850095989 Oct 18 01:34:22 PM PDT 23 Oct 18 01:34:35 PM PDT 23 3124113076 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.90645931402651205075661501144837523090559126490796604967105965086190463332001 Oct 18 01:33:15 PM PDT 23 Oct 18 01:33:32 PM PDT 23 3124113076 ps
T370 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.19208188779555116979730032118280623280625688939594791883911762366264016631331 Oct 18 01:34:09 PM PDT 23 Oct 18 01:34:22 PM PDT 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3997043880611415396529122167785695261517864361486661370696776899781341042077 Oct 18 01:34:41 PM PDT 23 Oct 18 01:34:55 PM PDT 23 3124113076 ps
T69 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.9832834214848336483796993292877261916876771124124772214385162847137266542191 Oct 18 01:34:03 PM PDT 23 Oct 18 01:38:49 PM PDT 23 65914678386 ps
T372 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.34001131582620451178663938977648254357780199735859089101370398002578005197742 Oct 18 01:34:07 PM PDT 23 Oct 18 01:38:56 PM PDT 23 65914678386 ps
T373 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.79971664071296861959676588982011364410002338769169036799124728834274761022023 Oct 18 01:33:53 PM PDT 23 Oct 18 01:34:06 PM PDT 23 3135422826 ps
T374 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.43656929942429114555088332264391624332590293662059172285191465393290706638668 Oct 18 01:33:14 PM PDT 23 Oct 18 01:33:28 PM PDT 23 3135422826 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.39659553639205202854632179637576563250994263853836833110406598628243574555405 Oct 18 01:33:26 PM PDT 23 Oct 18 01:33:41 PM PDT 23 3142303916 ps
T376 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.106476476029173717328022153096142329018474962881718661492328670829789572633079 Oct 18 01:34:41 PM PDT 23 Oct 18 01:34:59 PM PDT 23 3124113076 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.67646958477795875612744129407919484586753299202021255795883951591752875851811 Oct 18 01:34:25 PM PDT 23 Oct 18 01:34:39 PM PDT 23 3142303916 ps
T378 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.50283593413174912378320357126916488718334252771697599310551674149319832642539 Oct 18 01:35:12 PM PDT 23 Oct 18 01:35:27 PM PDT 23 3142303916 ps
T379 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.51517375645696499430732645408514942921765307476265603813276560468016339767283 Oct 18 01:33:58 PM PDT 23 Oct 18 01:34:11 PM PDT 23 3135422826 ps
T380 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.102255043133333112478086045198456733833926510883777091951795774941412224194982 Oct 18 01:34:03 PM PDT 23 Oct 18 01:34:16 PM PDT 23 3124113076 ps
T381 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.14101714119165179564954842163769279988916609054349785781391005178757453084189 Oct 18 01:34:06 PM PDT 23 Oct 18 01:34:18 PM PDT 23 3124113076 ps
T382 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.96799658918080794418370658126061203305202941334028132238030264696593869401058 Oct 18 01:33:58 PM PDT 23 Oct 18 01:34:11 PM PDT 23 3124113076 ps
T383 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.105191372180501029413335925655927836225593356642675714815378075940753148801742 Oct 18 01:34:30 PM PDT 23 Oct 18 01:35:50 PM PDT 23 3476453456 ps
T384 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.21126652048257666739543271835336924323782410109123873645020380873084180583408 Oct 18 01:33:27 PM PDT 23 Oct 18 01:33:42 PM PDT 23 3142303916 ps
T385 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.54206507710199004492091233150474697689563214777867512657890124714586862461954 Oct 18 01:34:44 PM PDT 23 Oct 18 01:39:32 PM PDT 23 65914678386 ps
T386 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.66922716637013987760612720496393802096929319906526432684690262817855615442956 Oct 18 01:33:28 PM PDT 23 Oct 18 01:33:40 PM PDT 23 3124113076 ps
T387 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.21180745270659958736159680448698848093512249662695711325538639114775950007231 Oct 18 01:33:27 PM PDT 23 Oct 18 01:33:43 PM PDT 23 3138518126 ps
T388 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.8315037991312935067850565687349347161588414751515856173055565881599119446484 Oct 18 01:34:26 PM PDT 23 Oct 18 01:35:47 PM PDT 23 3476453456 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.108968560018257749684076661580091441473992946803303807989191613343750505271452 Oct 18 01:33:32 PM PDT 23 Oct 18 01:33:45 PM PDT 23 3124113076 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.33018021825763971273988673589182068562893425948567063339595291453170790288831 Oct 18 01:34:44 PM PDT 23 Oct 18 01:34:57 PM PDT 23 3135422826 ps
T391 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.100511457418827141531549833355351540745268897995713910139523105090953432179805 Oct 18 01:33:56 PM PDT 23 Oct 18 01:38:38 PM PDT 23 65914678386 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.42469193054168011198105848015707895649810123473261230216471714228619101673720 Oct 18 01:33:27 PM PDT 23 Oct 18 01:33:40 PM PDT 23 3124113076 ps
T393 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3355076001764420778070693457517163324623984475111140302372118647804261981402 Oct 18 01:34:24 PM PDT 23 Oct 18 01:34:37 PM PDT 23 3135422826 ps
T394 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.28823063085982668600478722025550041245774206281900308016759960205624435499275 Oct 18 01:34:31 PM PDT 23 Oct 18 01:39:14 PM PDT 23 65914678386 ps
T395 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.71271337655579358866715627758650367603549390171999963128881426777208623276927 Oct 18 01:34:28 PM PDT 23 Oct 18 01:39:08 PM PDT 23 65914678386 ps
T396 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.17109229872855308313007370219241553169131774437441309699485099074739539353544 Oct 18 01:33:27 PM PDT 23 Oct 18 01:33:40 PM PDT 23 3124113076 ps
T397 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.99808429685661608886048724559236616947490599469295990227781778764030402262499 Oct 18 01:33:28 PM PDT 23 Oct 18 01:33:42 PM PDT 23 3142303916 ps
T398 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.15934268967139218117531149201426791517631268660414384159833976153833717964764 Oct 18 01:33:56 PM PDT 23 Oct 18 01:34:09 PM PDT 23 3124113076 ps
T399 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.77882112785372457251564360883705607841486115521699552950703966348209450433908 Oct 18 01:34:16 PM PDT 23 Oct 18 01:35:38 PM PDT 23 3476453456 ps
T400 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.65594471769021840931588185339781237139650027013731434153445801196808506093362 Oct 18 01:34:36 PM PDT 23 Oct 18 01:34:48 PM PDT 23 3124113076 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.106617431741367037168170506318264396544045140603767682773470481251457858774468 Oct 18 01:33:30 PM PDT 23 Oct 18 01:33:47 PM PDT 23 3124113076 ps
T402 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.26501785427474707341150607357234787581954414924160598666055125098565127338896 Oct 18 01:33:34 PM PDT 23 Oct 18 01:33:50 PM PDT 23 3124113076 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.63999074134791514287799247253721897722810192905077862567013914984924216323117 Oct 18 01:33:26 PM PDT 23 Oct 18 01:34:48 PM PDT 23 3476453456 ps
T404 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.18067839358400062314293648192076664095109395177485215362756019699698142909571 Oct 18 01:33:59 PM PDT 23 Oct 18 01:34:12 PM PDT 23 3124113076 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.81991321384304412908355881340445193659535498768443354136668393220703587536721 Oct 18 01:34:23 PM PDT 23 Oct 18 01:34:37 PM PDT 23 3142303916 ps
T406 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.77537119094190381737532629778832493948446202142700955599418350468352305619211 Oct 18 01:33:58 PM PDT 23 Oct 18 01:34:12 PM PDT 23 3135422826 ps
T407 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.17169560369918899842704979074747023683772511122135591909849863285571818497469 Oct 18 01:34:24 PM PDT 23 Oct 18 01:34:40 PM PDT 23 3124113076 ps
T408 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.72945552284681250035700171759387604338950880712720216137472563757758405544589 Oct 18 01:33:56 PM PDT 23 Oct 18 01:38:43 PM PDT 23 65914678386 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.40406491917946345912344344664669951302906800950734242842802360338525424849724 Oct 18 01:33:19 PM PDT 23 Oct 18 01:33:35 PM PDT 23 3138518126 ps
T410 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.83258291858658916988629910342599160916420099355022841293271692109132704225336 Oct 18 01:34:32 PM PDT 23 Oct 18 01:35:52 PM PDT 23 3476453456 ps
T411 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.31318885945953694854389127414743176536127760623236647267041977193513895905629 Oct 18 01:33:13 PM PDT 23 Oct 18 01:33:25 PM PDT 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1233989379821127559007457457857096385346207340035380662375531259306537767601 Oct 18 01:33:31 PM PDT 23 Oct 18 01:33:48 PM PDT 23 3124113076 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.54813549800996046569318362686651993262653361534358515222887059507051311956642 Oct 18 01:34:05 PM PDT 23 Oct 18 01:34:21 PM PDT 23 3138518126 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.32264699456302030081308098512729494258821902417683618884488367930487684455917 Oct 18 01:34:20 PM PDT 23 Oct 18 01:34:33 PM PDT 23 3135422826 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.16733712173945075981553897703026647073941352951203028814316519941676534636141 Oct 18 01:34:28 PM PDT 23 Oct 18 01:34:41 PM PDT 23 3135422826 ps
T416 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.27456712059854953646848917816897507980371516528274905908102435061933207352519 Oct 18 01:33:55 PM PDT 23 Oct 18 01:34:11 PM PDT 23 3124113076 ps
T417 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.40994989225262333626230157998540058965203863356626721403928015637080807778227 Oct 18 01:33:59 PM PDT 23 Oct 18 01:34:12 PM PDT 23 3124113076 ps
T418 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.24813512649335464124548083248425539601616195190373671386052853795360259181017 Oct 18 01:34:25 PM PDT 23 Oct 18 01:34:40 PM PDT 23 3142303916 ps
T419 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.107677552509671807955143243186944845400778820888908415187696158633816106320019 Oct 18 01:34:14 PM PDT 23 Oct 18 01:34:31 PM PDT 23 3124113076 ps
T420 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.54729904016926562341851239956679932570767818440683670012318852862269382663677 Oct 18 01:34:07 PM PDT 23 Oct 18 01:34:22 PM PDT 23 3142303916 ps
T421 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.33356352841404210452007933175735651925318861283587817026450315646422791622299 Oct 18 01:33:29 PM PDT 23 Oct 18 01:33:41 PM PDT 23 3124113076 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.43097014209941646349965532699915940814502305604700719356116577855199279050232 Oct 18 01:34:26 PM PDT 23 Oct 18 01:34:39 PM PDT 23 3124113076 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.17165916529220251376013681759971743326068153358518721625626752525874777340917 Oct 18 01:34:02 PM PDT 23 Oct 18 01:34:16 PM PDT 23 3142303916 ps
T424 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.44576046593274922496063175587422495273493694547820275870683962349589765239552 Oct 18 01:33:59 PM PDT 23 Oct 18 01:35:20 PM PDT 23 3476453456 ps
T425 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.11518979530783478723251213728374995888509934338158489182190240498155250890592 Oct 18 01:33:31 PM PDT 23 Oct 18 01:38:13 PM PDT 23 65914678386 ps
T426 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.24113270318281721648845387564804058684679391938200587124321401422058104395485 Oct 18 01:33:59 PM PDT 23 Oct 18 01:34:11 PM PDT 23 3135422826 ps
T427 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.103172486628843711969963932412211129747201036645797766148897411035252853166888 Oct 18 01:33:57 PM PDT 23 Oct 18 01:34:12 PM PDT 23 3142303916 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.58494476384983460422078299713391127373607283571332568137442308734874579440061 Oct 18 01:33:56 PM PDT 23 Oct 18 01:34:09 PM PDT 23 3124113076 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.87052845222180944880302691300626835513753333630801510954453851369958694895357 Oct 18 01:33:12 PM PDT 23 Oct 18 01:33:25 PM PDT 23 3135422826 ps
T430 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.103325251157966808932672746054926763451915744147169619179952538561284312337732 Oct 18 01:33:30 PM PDT 23 Oct 18 01:33:42 PM PDT 23 3124113076 ps
T431 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.83292364472467304210179295222651758811664688392379180461112126532549305579066 Oct 18 01:33:57 PM PDT 23 Oct 18 01:35:18 PM PDT 23 3476453456 ps
T432 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.77024620948490109841384708365754900933595679192343447715362495756677757922858 Oct 18 01:33:26 PM PDT 23 Oct 18 01:34:48 PM PDT 23 3476453456 ps
T433 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.30475163440906612953780959532734731273403878035738624019606890416893232362822 Oct 18 01:34:46 PM PDT 23 Oct 18 01:35:00 PM PDT 23 3124113076 ps
T434 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.10409765927404579228057000742762438635342955790243592601664811642068262252174 Oct 18 01:33:26 PM PDT 23 Oct 18 01:38:09 PM PDT 23 65914678386 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.35473635359050897136428777243383952392817328417466058067724809260459693950376 Oct 18 01:33:28 PM PDT 23 Oct 18 01:33:43 PM PDT 23 3142303916 ps
T436 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.14572314281957048279200456894554075530694517991374071009648125618319360502141 Oct 18 01:33:51 PM PDT 23 Oct 18 01:38:39 PM PDT 23 65914678386 ps
T437 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.16782798491778747358733751782628457346463905135629949237287613543761570491183 Oct 18 01:34:08 PM PDT 23 Oct 18 01:34:21 PM PDT 23 3124113076 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.88208369211337195212334057036583727741013727260170044664949379877692748399463 Oct 18 01:33:25 PM PDT 23 Oct 18 01:33:38 PM PDT 23 3124113076 ps
T439 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.103403920441897197000192481949566835114189510714621001451575086703100550755146 Oct 18 01:33:56 PM PDT 23 Oct 18 01:34:09 PM PDT 23 3124113076 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.18422475435010316224864077265782620766254726398721816491980296978201910429405 Oct 18 01:33:19 PM PDT 23 Oct 18 01:33:32 PM PDT 23 3124113076 ps
T441 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.9487006770142811980382559199927743987050866004521822437439330097776721016387 Oct 18 01:33:23 PM PDT 23 Oct 18 01:37:59 PM PDT 23 65914678386 ps
T442 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.14823479974385131037716670074940945257644114975754387427588156310352098373335 Oct 18 01:33:17 PM PDT 23 Oct 18 01:33:30 PM PDT 23 3124113076 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.9831264673891675946544615674804638225366923441659709566663955513916038210228 Oct 18 01:33:29 PM PDT 23 Oct 18 01:33:41 PM PDT 23 3135422826 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.47366885364771343341458162545822772294106530482504061650603663895914909428581 Oct 18 01:33:27 PM PDT 23 Oct 18 01:33:44 PM PDT 23 3124113076 ps
T445 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.82010620969933769695444678953452611856846993665031384458754333258439432048986 Oct 18 01:33:12 PM PDT 23 Oct 18 01:33:29 PM PDT 23 3124113076 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.36583888668424320388424609570146742198030802627789572299336729907167587759710 Oct 18 01:33:56 PM PDT 23 Oct 18 01:35:17 PM PDT 23 3476453456 ps
T447 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.45517890672785426930709290284772949485460587724690405923106955468153963640114 Oct 18 01:35:03 PM PDT 23 Oct 18 01:35:16 PM PDT 23 3124113076 ps
T448 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.96529510344617702295496753138152634422465221278480869279032612786251359384637 Oct 18 01:34:44 PM PDT 23 Oct 18 01:35:01 PM PDT 23 3124113076 ps
T449 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.88749665774520339020210759904884738394127415269178658272648366375227609007491 Oct 18 01:34:34 PM PDT 23 Oct 18 01:34:47 PM PDT 23 3135422826 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.71052427022677738081675388581939945311392976717451777858186734218355448261250 Oct 18 01:33:32 PM PDT 23 Oct 18 01:33:45 PM PDT 23 3135422826 ps

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.15909033229444133738880849734341400316058263416898119839079693193837978815466
Short name T17
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.94 seconds
Started Oct 18 01:34:39 PM PDT 23
Finished Oct 18 01:34:55 PM PDT 23
Peak memory 219084 kb
Host smart-afc9ca0b-1cc3-454b-8076-3edd47e4190a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15909033229444133738880849734341400316058263416898119839079693193837978815466 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.15909033229444133738880849734341400316058263416898119839079693193837978815466
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.43736369092341573172337295104827298133262968264496479693358870381524527735510
Short name T4
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.61 seconds
Started Oct 18 12:23:55 PM PDT 23
Finished Oct 18 12:29:38 PM PDT 23
Peak memory 237488 kb
Host smart-79d9f1c5-e054-4b71-981d-15376a055daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43736369092341573172337295104827298133262968264496479693358870381524527735510 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.437363690923415731723372951048272981332629682644964796933
58870381524527735510
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3107073004959619242627424769418752892464426772496192622771234219682546756859
Short name T18
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.76 seconds
Started Oct 18 01:33:25 PM PDT 23
Finished Oct 18 01:34:48 PM PDT 23
Peak memory 211144 kb
Host smart-71ffa19e-cecd-47ca-9917-3685bf28c4cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107073004959619242627424769418752892464426772496192622771234219682546756859 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.3107073004959619242627424769418752892464426772496192622771234219682546756859
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.28153867504323251518618230296334014384758497721729210457705389377063115776140
Short name T5
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.64 seconds
Started Oct 18 12:27:30 PM PDT 23
Finished Oct 18 12:28:13 PM PDT 23
Peak memory 212396 kb
Host smart-2a268f79-670c-4b50-96b1-122d2e30005a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281538675043232515186182302963340143847584977217292104577053893
77063115776140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.281538675043232515186182302963340143847584977217292
10457705389377063115776140
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.69383354609868767129862231251720008194322703352191105928025877255705065153897
Short name T19
Test name
Test status
Simulation time 65914678386 ps
CPU time 280.73 seconds
Started Oct 18 01:33:34 PM PDT 23
Finished Oct 18 01:38:15 PM PDT 23
Peak memory 218932 kb
Host smart-c51da9b5-8d54-4217-be39-d4717d20fa65
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69383354609868767129862231251720008194322703352191105928025877255705065153897 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.69383354609868767129862231251720008194322703352191105928
025877255705065153897
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.102255043133333112478086045198456733833926510883777091951795774941412224194982
Short name T380
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.78 seconds
Started Oct 18 01:34:03 PM PDT 23
Finished Oct 18 01:34:16 PM PDT 23
Peak memory 210836 kb
Host smart-5281c17d-59cd-49c6-a84b-be686e559699
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102255043133333112478086045198456733833926510883777091951795774941412224194982 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.102255043133333112478086045198456733833926510883777091951795774941412224194982
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.96853840103219633208699697683279143919089404556685788550956893506574514085128
Short name T29
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.93 seconds
Started Oct 18 12:21:25 PM PDT 23
Finished Oct 18 12:23:20 PM PDT 23
Peak memory 236548 kb
Host smart-446892ba-421c-4d6b-8d50-65ee2f46e2cb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96853840103219633208699697683279143919089404556685788550956893506574514085128 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.96853840103219633208699697683279143919089404556685788550956893506574514085128
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.80886118224051369475583076514232918717101470644666061215180595347749451917240
Short name T58
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.86 seconds
Started Oct 18 01:34:09 PM PDT 23
Finished Oct 18 01:34:23 PM PDT 23
Peak memory 210732 kb
Host smart-fe9ad2f0-f182-4a85-8d85-3c52651ad475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80886118224051369475583076514232918717101470644666061215180595347749451917240
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.80886118224051369475583076514232918717101470644666061
215180595347749451917240
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.41351450662037724272160859381000204930850416967457718486861290190727394372158
Short name T86
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.15 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:09 PM PDT 23
Peak memory 213384 kb
Host smart-dc69c929-22ef-43e0-822e-af877b44d273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135145066203772427216085938100020493085041
6967457718486861290190727394372158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.413514506620
37724272160859381000204930850416967457718486861290190727394372158
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.107586244678966089696290169914950843544985196943449878356218733860772850095989
Short name T89
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 18 01:34:22 PM PDT 23
Finished Oct 18 01:34:35 PM PDT 23
Peak memory 210864 kb
Host smart-dbd43d0b-fecc-44ac-8caa-ab8b9744008a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107586244678966089696290169914950843544985196943449878356218733860772850095989 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.107586244678966089696290169914950843544985196943449878356218733860772850095989
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.112578215577201729766457432876415641302250889673511779027019992923307077379071
Short name T105
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.18 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 211428 kb
Host smart-aa460275-8236-4628-8178-13f0dd52cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112578215577201729766457432876415641302250889673511779027019992923307077379071 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rom_ctrl_kmac_err_chk.112578215577201729766457432876415641302250889673511779027019992923307077379071
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.44947508919515513024180162972911517040382491297472619901124984997194130672776
Short name T72
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 18 12:30:02 PM PDT 23
Finished Oct 18 12:30:15 PM PDT 23
Peak memory 211088 kb
Host smart-81ae4ce9-5001-43c7-8eef-e66cbc8243bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44947508919515513024180162972911517040382491297472619901124984997194130672776 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.44947508919515513024180162972911517040382491297472619901124984997194130672776
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.20783705625484819647671591915421678745482824734133943409650934642195269630973
Short name T111
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Oct 18 12:31:07 PM PDT 23
Finished Oct 18 12:31:25 PM PDT 23
Peak memory 211060 kb
Host smart-9d1ac6c0-b65c-4d8c-8a87-c84e3583c0eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783705625484819647671591915421678745482824734133943409650934642195269630973 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.20783705625484819647671591915421678745482824734133943409650934642195269630973
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.42469193054168011198105848015707895649810123473261230216471714228619101673720
Short name T392
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.09 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:40 PM PDT 23
Peak memory 210864 kb
Host smart-4dba9e54-cfbd-4ccc-81f7-159870367986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42469193054168011198105848015707895649810123473261230216471714228619101673720 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.42469193054168011198105848015707895649810123473261230216471714228619101673720
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.10983024632079848418518585322315082995420733590846802216673313956444188812306
Short name T6
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.76 seconds
Started Oct 18 12:21:35 PM PDT 23
Finished Oct 18 12:22:05 PM PDT 23
Peak memory 212792 kb
Host smart-1982f3e7-b69f-4806-ae2b-4aee27ffa447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10983024632079848418518585322315082995420733590846802216673313956444188812306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_smoke.10983024632079848418518585322315082995420733590846802216673313956444188812306
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.46464257372819329645554421496701772886618988416166900518476807605150121489658
Short name T78
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.59 seconds
Started Oct 18 01:33:12 PM PDT 23
Finished Oct 18 01:33:28 PM PDT 23
Peak memory 210772 kb
Host smart-5504a5ab-86ab-48f0-b405-f0a7f3085f3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46464257372819329645554421496701772886618988416166900518476807605150121489658 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.46464257372819329645554421496701772886618988416166900518476807605150121489658
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.16733712173945075981553897703026647073941352951203028814316519941676534636141
Short name T415
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.19 seconds
Started Oct 18 01:34:28 PM PDT 23
Finished Oct 18 01:34:41 PM PDT 23
Peak memory 213444 kb
Host smart-acd30972-f94d-4027-8331-b5f4bd457db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673371217394507598155389770302664707394135
2951203028814316519941676534636141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1673371217394
5075981553897703026647073941352951203028814316519941676534636141
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.18422475435010316224864077265782620766254726398721816491980296978201910429405
Short name T440
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 18 01:33:19 PM PDT 23
Finished Oct 18 01:33:32 PM PDT 23
Peak memory 210836 kb
Host smart-8c64684b-7c65-4a11-917a-cffca1826881
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422475435010316224864077265782620766254726398721816491980296978201910429405 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.1842247543501031622486407726578262076625472639872181649198
0296978201910429405
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.102275497342827562673171079509744744011710564360859830180799205135877442238669
Short name T90
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Oct 18 01:34:04 PM PDT 23
Finished Oct 18 01:34:16 PM PDT 23
Peak memory 210860 kb
Host smart-56cd945e-01d0-4d11-afa0-e0fbcf61987d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102275497342827562673171079509744744011710564360859830180799205135877442238669 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.102275497342827562673171079509744744011710564360859830180799205135877442238669
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.17165916529220251376013681759971743326068153358518721625626752525874777340917
Short name T423
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.37 seconds
Started Oct 18 01:34:02 PM PDT 23
Finished Oct 18 01:34:16 PM PDT 23
Peak memory 210872 kb
Host smart-884f99c7-1389-400b-a5e4-41b481f0dd46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17165916529220251376013681759971743326068153358518721625626752525874777340917
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.171659165292202513760136817599717433260681533585187216
25626752525874777340917
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.99079729692766702421889200896447635784807684465578733845541927472167907806148
Short name T48
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.52 seconds
Started Oct 18 01:33:55 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 219124 kb
Host smart-7bfa642e-cf58-4be4-b711-a669af523df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99079729692766702421889200896447635784807684465578733845541927472167907806148 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.99079729692766702421889200896447635784807684465578733845541927472167907806148
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.64131543055118649143016834082032346913535766489897317339012705846392428085290
Short name T68
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 18 01:33:25 PM PDT 23
Finished Oct 18 01:33:37 PM PDT 23
Peak memory 210776 kb
Host smart-dd5479d1-8ec0-4d49-b098-7b20ad3aa050
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64131543055118649143016834082032346913535766489897317339012705846392428085290 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.64131543055118649143016834082032346913535766489897317339012705846392428085290
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.14823479974385131037716670074940945257644114975754387427588156310352098373335
Short name T442
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.66 seconds
Started Oct 18 01:33:17 PM PDT 23
Finished Oct 18 01:33:30 PM PDT 23
Peak memory 210808 kb
Host smart-88fe7377-2698-45de-b0c6-0fda0358ff93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823479974385131037716670074940945257644114975754387427588156310352098373335 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.14823479974385131037716670074940945257644114975754387427588156310352098373335
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.21180745270659958736159680448698848093512249662695711325538639114775950007231
Short name T387
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.18 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:43 PM PDT 23
Peak memory 210876 kb
Host smart-ee91a206-832c-4606-8766-0b4220958930
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180745270659958736159680448698848093512249662695711325538639114775950007231 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.21180745270659958736159680448698848093512249662695711325538639114775950007231
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.87052845222180944880302691300626835513753333630801510954453851369958694895357
Short name T429
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.43 seconds
Started Oct 18 01:33:12 PM PDT 23
Finished Oct 18 01:33:25 PM PDT 23
Peak memory 213424 kb
Host smart-2e88036a-3477-4a1c-8dad-5698e82c298f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8705284522218094488030269130062683551375333
3630801510954453851369958694895357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.8705284522218
0944880302691300626835513753333630801510954453851369958694895357
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.48750000729148192687099734461534150815709709462904407659408695133384828399258
Short name T95
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 18 01:33:13 PM PDT 23
Finished Oct 18 01:33:25 PM PDT 23
Peak memory 210820 kb
Host smart-31ce2919-9b71-42ac-a02e-93451a912f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48750000729148192687099734461534150815709709462904407659408695133384828399258 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.48750000729148192687099734461534150815709709462904407659408695133384828399258
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.103325251157966808932672746054926763451915744147169619179952538561284312337732
Short name T430
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.8 seconds
Started Oct 18 01:33:30 PM PDT 23
Finished Oct 18 01:33:42 PM PDT 23
Peak memory 210876 kb
Host smart-3aa2ae91-02d3-4814-92f2-bdee8131e57c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103325251157966808932672746054926763451915744147169619179952538561284312337732 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.103325251157966808932672746054926763451915744147169619179
952538561284312337732
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.17109229872855308313007370219241553169131774437441309699485099074739539353544
Short name T396
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:40 PM PDT 23
Peak memory 210840 kb
Host smart-0e0ca528-5940-4d04-9d18-bc0586aa3d7e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17109229872855308313007370219241553169131774437441309699485099074739539353544 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.17109229872855308313007370219241553169131774437441309699485099074739539353544
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.21830770187204959980953289823108690187162309721058657557206285739958462940105
Short name T64
Test name
Test status
Simulation time 65914678386 ps
CPU time 275.81 seconds
Started Oct 18 01:34:03 PM PDT 23
Finished Oct 18 01:38:39 PM PDT 23
Peak memory 218996 kb
Host smart-7c93b99d-dbf6-4f70-9905-a72702c5e8df
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21830770187204959980953289823108690187162309721058657557206285739958462940105 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.21830770187204959980953289823108690187162309721058657557
206285739958462940105
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.21126652048257666739543271835336924323782410109123873645020380873084180583408
Short name T384
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.7 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:42 PM PDT 23
Peak memory 210848 kb
Host smart-83788407-c150-4f8a-9460-0fb136074595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21126652048257666739543271835336924323782410109123873645020380873084180583408
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.211266520482576667395432718353369243237824101091238736
45020380873084180583408
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.107677552509671807955143243186944845400778820888908415187696158633816106320019
Short name T419
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.67 seconds
Started Oct 18 01:34:14 PM PDT 23
Finished Oct 18 01:34:31 PM PDT 23
Peak memory 219108 kb
Host smart-7fb5982f-98e3-4605-ac48-419ab94c4791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107677552509671807955143243186944845400778820888908415187696158633816106320019 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.107677552509671807955143243186944845400778820888908415187696158633816106320019
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.31881294165363230754730042156449692664239974901292221974008408289565354109014
Short name T365
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.65 seconds
Started Oct 18 01:34:03 PM PDT 23
Finished Oct 18 01:35:24 PM PDT 23
Peak memory 210964 kb
Host smart-0addc2f6-b722-4762-abf5-baadd42325db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881294165363230754730042156449692664239974901292221974008408289565354109014 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.31881294165363230754730042156449692664239974901292221974008408289565354109014
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.32264699456302030081308098512729494258821902417683618884488367930487684455917
Short name T414
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.36 seconds
Started Oct 18 01:34:20 PM PDT 23
Finished Oct 18 01:34:33 PM PDT 23
Peak memory 213444 kb
Host smart-b476c633-6c45-44da-a491-010135dfdb06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226469945630203008130809851272949425882190
2417683618884488367930487684455917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.322646994563
02030081308098512729494258821902417683618884488367930487684455917
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.18067839358400062314293648192076664095109395177485215362756019699698142909571
Short name T404
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 18 01:33:59 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 210900 kb
Host smart-c43cd2fa-8810-47f3-be75-32f6981bb764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067839358400062314293648192076664095109395177485215362756019699698142909571 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.18067839358400062314293648192076664095109395177485215362756019699698142909571
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.11518979530783478723251213728374995888509934338158489182190240498155250890592
Short name T425
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.95 seconds
Started Oct 18 01:33:31 PM PDT 23
Finished Oct 18 01:38:13 PM PDT 23
Peak memory 218996 kb
Host smart-6bd0612a-7d94-42ac-b66c-589af91163aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11518979530783478723251213728374995888509934338158489182190240498155250890592 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.1151897953078347872325121372837499588850993433815848918
2190240498155250890592
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.103172486628843711969963932412211129747201036645797766148897411035252853166888
Short name T427
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.04 seconds
Started Oct 18 01:33:57 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 210872 kb
Host smart-6354cb22-b3cc-4ab9-b442-e1eaa3567433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103172486628843711969963932412211129747201036645797766148897411035252853166888
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.1031724866288437119699639324122111297472010366457977
66148897411035252853166888
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.26501785427474707341150607357234787581954414924160598666055125098565127338896
Short name T402
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Oct 18 01:33:34 PM PDT 23
Finished Oct 18 01:33:50 PM PDT 23
Peak memory 219080 kb
Host smart-92216fe8-cb94-4013-849a-cdc354bfb981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501785427474707341150607357234787581954414924160598666055125098565127338896 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.26501785427474707341150607357234787581954414924160598666055125098565127338896
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.51939026572348591343891392880503445325531998436140399276840630318891096894564
Short name T367
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.8 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:34:48 PM PDT 23
Peak memory 211096 kb
Host smart-7cc34dda-4388-437f-840a-a36594bc2a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51939026572348591343891392880503445325531998436140399276840630318891096894564 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.51939026572348591343891392880503445325531998436140399276840630318891096894564
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.15934268967139218117531149201426791517631268660414384159833976153833717964764
Short name T398
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:09 PM PDT 23
Peak memory 210800 kb
Host smart-9fd6a251-716c-472e-82fe-617127cb1c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15934268967139218117531149201426791517631268660414384159833976153833717964764 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.15934268967139218117531149201426791517631268660414384159833976153833717964764
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.9487006770142811980382559199927743987050866004521822437439330097776721016387
Short name T441
Test name
Test status
Simulation time 65914678386 ps
CPU time 275.62 seconds
Started Oct 18 01:33:23 PM PDT 23
Finished Oct 18 01:37:59 PM PDT 23
Peak memory 218880 kb
Host smart-c8f5461f-3707-4957-9c50-9ecf7c98fec1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9487006770142811980382559199927743987050866004521822437439330097776721016387 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.94870067701428119803825591999277439870508660045218224374
39330097776721016387
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.82010620969933769695444678953452611856846993665031384458754333258439432048986
Short name T445
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.99 seconds
Started Oct 18 01:33:12 PM PDT 23
Finished Oct 18 01:33:29 PM PDT 23
Peak memory 219076 kb
Host smart-f69add13-587c-4b60-84e1-ce0e2e3bf594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82010620969933769695444678953452611856846993665031384458754333258439432048986 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.82010620969933769695444678953452611856846993665031384458754333258439432048986
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.77024620948490109841384708365754900933595679192343447715362495756677757922858
Short name T432
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.19 seconds
Started Oct 18 01:33:26 PM PDT 23
Finished Oct 18 01:34:48 PM PDT 23
Peak memory 211056 kb
Host smart-4b8f42e3-c497-43e5-af73-5d1b3c96b3dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77024620948490109841384708365754900933595679192343447715362495756677757922858 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.77024620948490109841384708365754900933595679192343447715362495756677757922858
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.24113270318281721648845387564804058684679391938200587124321401422058104395485
Short name T426
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.06 seconds
Started Oct 18 01:33:59 PM PDT 23
Finished Oct 18 01:34:11 PM PDT 23
Peak memory 213460 kb
Host smart-9363b59d-f005-4145-ab7a-7a24de2205c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411327031828172164884538756480405868467939
1938200587124321401422058104395485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.241132703182
81721648845387564804058684679391938200587124321401422058104395485
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.114636453911470470465111891323680833308269633474413675284867412742007942526583
Short name T96
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Oct 18 01:33:30 PM PDT 23
Finished Oct 18 01:33:43 PM PDT 23
Peak memory 210860 kb
Host smart-b0b2d48b-7298-4902-9bee-f1f0ff03dca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114636453911470470465111891323680833308269633474413675284867412742007942526583 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.114636453911470470465111891323680833308269633474413675284867412742007942526583
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.34001131582620451178663938977648254357780199735859089101370398002578005197742
Short name T372
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.97 seconds
Started Oct 18 01:34:07 PM PDT 23
Finished Oct 18 01:38:56 PM PDT 23
Peak memory 219024 kb
Host smart-b3b7f290-ea6a-49f7-93b1-3ce4b953532a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34001131582620451178663938977648254357780199735859089101370398002578005197742 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.3400113158262045117866393897764825435778019973585908910
1370398002578005197742
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.54729904016926562341851239956679932570767818440683670012318852862269382663677
Short name T420
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.25 seconds
Started Oct 18 01:34:07 PM PDT 23
Finished Oct 18 01:34:22 PM PDT 23
Peak memory 210852 kb
Host smart-38befc44-7d00-4aec-b17d-720b410aea4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54729904016926562341851239956679932570767818440683670012318852862269382663677
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.54729904016926562341851239956679932570767818440683670
012318852862269382663677
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.106617431741367037168170506318264396544045140603767682773470481251457858774468
Short name T401
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.98 seconds
Started Oct 18 01:33:30 PM PDT 23
Finished Oct 18 01:33:47 PM PDT 23
Peak memory 219076 kb
Host smart-e09d0f43-1ec1-4fb8-a3c5-42aad6fc7619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106617431741367037168170506318264396544045140603767682773470481251457858774468 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.106617431741367037168170506318264396544045140603767682773470481251457858774468
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.77882112785372457251564360883705607841486115521699552950703966348209450433908
Short name T399
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.99 seconds
Started Oct 18 01:34:16 PM PDT 23
Finished Oct 18 01:35:38 PM PDT 23
Peak memory 211060 kb
Host smart-c6159897-ff38-4e73-9f56-42219c062487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77882112785372457251564360883705607841486115521699552950703966348209450433908 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.77882112785372457251564360883705607841486115521699552950703966348209450433908
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3355076001764420778070693457517163324623984475111140302372118647804261981402
Short name T393
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.57 seconds
Started Oct 18 01:34:24 PM PDT 23
Finished Oct 18 01:34:37 PM PDT 23
Peak memory 213476 kb
Host smart-5263c346-e8bc-4c8e-851c-cbfe6544dd02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355076001764420778070693457517163324623984
475111140302372118647804261981402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3355076001764
420778070693457517163324623984475111140302372118647804261981402
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.58494476384983460422078299713391127373607283571332568137442308734874579440061
Short name T428
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:09 PM PDT 23
Peak memory 210844 kb
Host smart-d4567da7-f50b-4316-8fc1-a6772fae5378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58494476384983460422078299713391127373607283571332568137442308734874579440061 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.58494476384983460422078299713391127373607283571332568137442308734874579440061
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.72945552284681250035700171759387604338950880712720216137472563757758405544589
Short name T408
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.14 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:38:43 PM PDT 23
Peak memory 218940 kb
Host smart-77bde304-47af-414c-a7e6-d25ffeb434c9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72945552284681250035700171759387604338950880712720216137472563757758405544589 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.7294555228468125003570017175938760433895088071272021613
7472563757758405544589
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.103355939203471734407652650129203865304571473055356928478788354314221777387075
Short name T71
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.13 seconds
Started Oct 18 01:33:29 PM PDT 23
Finished Oct 18 01:33:44 PM PDT 23
Peak memory 210844 kb
Host smart-89a6c24b-f981-4388-9dfc-953c1655502b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103355939203471734407652650129203865304571473055356928478788354314221777387075
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.1033559392034717344076526501292038653045714730553569
28478788354314221777387075
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.27456712059854953646848917816897507980371516528274905908102435061933207352519
Short name T416
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.85 seconds
Started Oct 18 01:33:55 PM PDT 23
Finished Oct 18 01:34:11 PM PDT 23
Peak memory 219016 kb
Host smart-616627ed-8a64-413c-9b19-54e56cbb8fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27456712059854953646848917816897507980371516528274905908102435061933207352519 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.27456712059854953646848917816897507980371516528274905908102435061933207352519
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.16208963991317524880716257539548406552116859982176133232091008526260837959246
Short name T46
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.26 seconds
Started Oct 18 01:34:33 PM PDT 23
Finished Oct 18 01:35:54 PM PDT 23
Peak memory 211076 kb
Host smart-7f1c276b-54a9-45f9-a440-909ee2e8ce71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16208963991317524880716257539548406552116859982176133232091008526260837959246 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.16208963991317524880716257539548406552116859982176133232091008526260837959246
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.11043617189773569720714522500003813169967657926019665716922937169323905415484
Short name T56
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.92 seconds
Started Oct 18 01:34:21 PM PDT 23
Finished Oct 18 01:34:35 PM PDT 23
Peak memory 213448 kb
Host smart-7c3d19a4-5a18-4753-b8bb-24845c554b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104361718977356972071452250000381316996765
7926019665716922937169323905415484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.110436171897
73569720714522500003813169967657926019665716922937169323905415484
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.109906195729628378644725749600605935425923670999058365997610937435393802182261
Short name T87
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 18 01:34:23 PM PDT 23
Finished Oct 18 01:34:35 PM PDT 23
Peak memory 210824 kb
Host smart-1c32fd88-4dfb-4240-a8a2-9f1aacd4dea0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109906195729628378644725749600605935425923670999058365997610937435393802182261 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.109906195729628378644725749600605935425923670999058365997610937435393802182261
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.20294947367414284686390634593482275772200271646333563392398281119572184485379
Short name T24
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.79 seconds
Started Oct 18 01:34:24 PM PDT 23
Finished Oct 18 01:39:11 PM PDT 23
Peak memory 218960 kb
Host smart-009fa6be-5dae-4e7f-9da1-46f448ca1b8e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294947367414284686390634593482275772200271646333563392398281119572184485379 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.2029494736741428468639063459348227577220027164633356339
2398281119572184485379
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.56011179875242692285603472339442498111977919945927524199393495067547778693178
Short name T360
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.86 seconds
Started Oct 18 01:34:23 PM PDT 23
Finished Oct 18 01:34:38 PM PDT 23
Peak memory 210784 kb
Host smart-317e93e3-a4a9-4a23-9c74-9ea26f408c60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56011179875242692285603472339442498111977919945927524199393495067547778693178
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.56011179875242692285603472339442498111977919945927524
199393495067547778693178
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.96529510344617702295496753138152634422465221278480869279032612786251359384637
Short name T448
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.47 seconds
Started Oct 18 01:34:44 PM PDT 23
Finished Oct 18 01:35:01 PM PDT 23
Peak memory 219064 kb
Host smart-2bd10025-10de-4fc3-86ca-e1ad441df205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96529510344617702295496753138152634422465221278480869279032612786251359384637 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.96529510344617702295496753138152634422465221278480869279032612786251359384637
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.59873539804713189100254102247990298911071976975799051981023999622952906878832
Short name T91
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.54 seconds
Started Oct 18 01:34:38 PM PDT 23
Finished Oct 18 01:35:59 PM PDT 23
Peak memory 211084 kb
Host smart-52747647-f76a-4edd-8130-e5b7319f79ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59873539804713189100254102247990298911071976975799051981023999622952906878832 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.59873539804713189100254102247990298911071976975799051981023999622952906878832
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.88749665774520339020210759904884738394127415269178658272648366375227609007491
Short name T449
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.23 seconds
Started Oct 18 01:34:34 PM PDT 23
Finished Oct 18 01:34:47 PM PDT 23
Peak memory 213408 kb
Host smart-fc24ad95-5078-47d0-af54-b6ba8b1fb3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8874966577452033902021075990488473839412741
5269178658272648366375227609007491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.887496657745
20339020210759904884738394127415269178658272648366375227609007491
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.65594471769021840931588185339781237139650027013731434153445801196808506093362
Short name T400
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 18 01:34:36 PM PDT 23
Finished Oct 18 01:34:48 PM PDT 23
Peak memory 210876 kb
Host smart-fdb7ac6a-a904-4f2c-8d14-8f02b0ee41bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65594471769021840931588185339781237139650027013731434153445801196808506093362 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.65594471769021840931588185339781237139650027013731434153445801196808506093362
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.53891351619679642974972157512921366070500496714750963819222219324784774697562
Short name T65
Test name
Test status
Simulation time 65914678386 ps
CPU time 274.34 seconds
Started Oct 18 01:34:34 PM PDT 23
Finished Oct 18 01:39:09 PM PDT 23
Peak memory 219008 kb
Host smart-4ea5af20-ef28-4d9f-89a2-e6169de85e03
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53891351619679642974972157512921366070500496714750963819222219324784774697562 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.5389135161967964297497215751292136607050049671475096381
9222219324784774697562
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.24813512649335464124548083248425539601616195190373671386052853795360259181017
Short name T418
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.2 seconds
Started Oct 18 01:34:25 PM PDT 23
Finished Oct 18 01:34:40 PM PDT 23
Peak memory 210868 kb
Host smart-11f3e15d-5766-4c17-ae87-b165f88768c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24813512649335464124548083248425539601616195190373671386052853795360259181017
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.24813512649335464124548083248425539601616195190373671
386052853795360259181017
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.17169560369918899842704979074747023683772511122135591909849863285571818497469
Short name T407
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.05 seconds
Started Oct 18 01:34:24 PM PDT 23
Finished Oct 18 01:34:40 PM PDT 23
Peak memory 219064 kb
Host smart-5833cc69-3e9c-48c6-9387-1d3bc83ecdee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17169560369918899842704979074747023683772511122135591909849863285571818497469 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.17169560369918899842704979074747023683772511122135591909849863285571818497469
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.8315037991312935067850565687349347161588414751515856173055565881599119446484
Short name T388
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.22 seconds
Started Oct 18 01:34:26 PM PDT 23
Finished Oct 18 01:35:47 PM PDT 23
Peak memory 211092 kb
Host smart-539abef4-9d9c-409c-8976-8072dff79291
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8315037991312935067850565687349347161588414751515856173055565881599119446484 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.8315037991312935067850565687349347161588414751515856173055565881599119446484
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.24977848824230751497539078437073830034361210969972836332079765016589724231028
Short name T359
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.4 seconds
Started Oct 18 01:34:50 PM PDT 23
Finished Oct 18 01:35:02 PM PDT 23
Peak memory 213396 kb
Host smart-48201235-1caa-4cde-82ad-873fea88f388
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497784882423075149753907843707383003436121
0969972836332079765016589724231028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.249778488242
30751497539078437073830034361210969972836332079765016589724231028
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.30475163440906612953780959532734731273403878035738624019606890416893232362822
Short name T433
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.42 seconds
Started Oct 18 01:34:46 PM PDT 23
Finished Oct 18 01:35:00 PM PDT 23
Peak memory 210884 kb
Host smart-3ca36ebf-53ed-4dd7-bf07-5c9ac8add94f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30475163440906612953780959532734731273403878035738624019606890416893232362822 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.30475163440906612953780959532734731273403878035738624019606890416893232362822
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.75507051682333096218871807725929661430667962592330259047909066368613045327279
Short name T60
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.06 seconds
Started Oct 18 01:34:39 PM PDT 23
Finished Oct 18 01:39:23 PM PDT 23
Peak memory 218968 kb
Host smart-3d68364c-d4a2-4552-8d81-0b480c990472
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75507051682333096218871807725929661430667962592330259047909066368613045327279 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.7550705168233309621887180772592966143066796259233025904
7909066368613045327279
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.38963887131560896257113872299683658283678672767279969565972636015253643423688
Short name T77
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.02 seconds
Started Oct 18 01:34:37 PM PDT 23
Finished Oct 18 01:34:51 PM PDT 23
Peak memory 210872 kb
Host smart-0d041836-eec4-47c8-b6d0-ad5b12fcf18e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38963887131560896257113872299683658283678672767279969565972636015253643423688
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.38963887131560896257113872299683658283678672767279969
565972636015253643423688
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.16342714062866275081126848690037649825077688727207490651426013192519157021639
Short name T50
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.08 seconds
Started Oct 18 01:34:30 PM PDT 23
Finished Oct 18 01:35:51 PM PDT 23
Peak memory 210916 kb
Host smart-e2626cb8-e638-4828-933a-f2e7c1d63514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342714062866275081126848690037649825077688727207490651426013192519157021639 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.16342714062866275081126848690037649825077688727207490651426013192519157021639
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3440557889657376073751788350176682321505158906247380696043373025984989017168
Short name T94
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.33 seconds
Started Oct 18 01:34:24 PM PDT 23
Finished Oct 18 01:34:37 PM PDT 23
Peak memory 213432 kb
Host smart-e3beb48d-1336-4a13-bb4c-f17ac5120eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440557889657376073751788350176682321505158
906247380696043373025984989017168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3440557889657
376073751788350176682321505158906247380696043373025984989017168
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.45517890672785426930709290284772949485460587724690405923106955468153963640114
Short name T447
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Oct 18 01:35:03 PM PDT 23
Finished Oct 18 01:35:16 PM PDT 23
Peak memory 210788 kb
Host smart-136d4aae-aa90-47f3-9b93-c80070d48a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45517890672785426930709290284772949485460587724690405923106955468153963640114 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.45517890672785426930709290284772949485460587724690405923106955468153963640114
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.71271337655579358866715627758650367603549390171999963128881426777208623276927
Short name T395
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.46 seconds
Started Oct 18 01:34:28 PM PDT 23
Finished Oct 18 01:39:08 PM PDT 23
Peak memory 218916 kb
Host smart-1aa5491a-80a6-4326-b3bb-a3b1345b64d1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271337655579358866715627758650367603549390171999963128881426777208623276927 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.7127133765557935886671562775865036760354939017199996312
8881426777208623276927
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.67646958477795875612744129407919484586753299202021255795883951591752875851811
Short name T377
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.98 seconds
Started Oct 18 01:34:25 PM PDT 23
Finished Oct 18 01:34:39 PM PDT 23
Peak memory 210836 kb
Host smart-b87d242a-ba8f-4c63-96f5-1991b47e0abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67646958477795875612744129407919484586753299202021255795883951591752875851811
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.67646958477795875612744129407919484586753299202021255
795883951591752875851811
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.106476476029173717328022153096142329018474962881718661492328670829789572633079
Short name T376
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.5 seconds
Started Oct 18 01:34:41 PM PDT 23
Finished Oct 18 01:34:59 PM PDT 23
Peak memory 219016 kb
Host smart-059b3228-c77a-4cc0-8d33-7016fb1b3c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106476476029173717328022153096142329018474962881718661492328670829789572633079 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.106476476029173717328022153096142329018474962881718661492328670829789572633079
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.83258291858658916988629910342599160916420099355022841293271692109132704225336
Short name T410
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.08 seconds
Started Oct 18 01:34:32 PM PDT 23
Finished Oct 18 01:35:52 PM PDT 23
Peak memory 211052 kb
Host smart-3f96d1b7-1b09-4acf-a195-f16f80cf4c02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83258291858658916988629910342599160916420099355022841293271692109132704225336 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.83258291858658916988629910342599160916420099355022841293271692109132704225336
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.41312495295093241212948737703891098354762075403588449569494704229104175341485
Short name T362
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.27 seconds
Started Oct 18 01:34:06 PM PDT 23
Finished Oct 18 01:34:19 PM PDT 23
Peak memory 213452 kb
Host smart-90cbb49a-8413-4ac7-bdbe-b7b6db4ea3fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131249529509324121294873770389109835476207
5403588449569494704229104175341485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.413124952950
93241212948737703891098354762075403588449569494704229104175341485
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.92587158164195278707590769316999313540255574775084518250468187397757581450498
Short name T26
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.11 seconds
Started Oct 18 01:35:24 PM PDT 23
Finished Oct 18 01:35:36 PM PDT 23
Peak memory 210896 kb
Host smart-f90d673b-0abe-4be2-a344-6b8900096910
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92587158164195278707590769316999313540255574775084518250468187397757581450498 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.92587158164195278707590769316999313540255574775084518250468187397757581450498
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.28823063085982668600478722025550041245774206281900308016759960205624435499275
Short name T394
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.67 seconds
Started Oct 18 01:34:31 PM PDT 23
Finished Oct 18 01:39:14 PM PDT 23
Peak memory 219012 kb
Host smart-d7ef7e65-4e35-4d24-93bf-72c4309cb016
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823063085982668600478722025550041245774206281900308016759960205624435499275 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.2882306308598266860047872202555004124577420628190030801
6759960205624435499275
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.50283593413174912378320357126916488718334252771697599310551674149319832642539
Short name T378
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.89 seconds
Started Oct 18 01:35:12 PM PDT 23
Finished Oct 18 01:35:27 PM PDT 23
Peak memory 210748 kb
Host smart-15e5c95c-d70f-4e06-9da7-c99c69307864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50283593413174912378320357126916488718334252771697599310551674149319832642539
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.50283593413174912378320357126916488718334252771697599
310551674149319832642539
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.16042409369603851100323796437831016224841687075520869318985345679882163992667
Short name T52
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.8 seconds
Started Oct 18 01:34:45 PM PDT 23
Finished Oct 18 01:35:03 PM PDT 23
Peak memory 219056 kb
Host smart-e9fab112-47fa-4bcc-a721-c5b3b5920f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16042409369603851100323796437831016224841687075520869318985345679882163992667 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.16042409369603851100323796437831016224841687075520869318985345679882163992667
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.49684421896678304582983368322907177057602295485508888431843279558064564712772
Short name T49
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.38 seconds
Started Oct 18 01:35:15 PM PDT 23
Finished Oct 18 01:36:37 PM PDT 23
Peak memory 211052 kb
Host smart-bb2a8082-7e3e-45c1-b924-a864ac22d1d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49684421896678304582983368322907177057602295485508888431843279558064564712772 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.49684421896678304582983368322907177057602295485508888431843279558064564712772
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.79971664071296861959676588982011364410002338769169036799124728834274761022023
Short name T373
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.47 seconds
Started Oct 18 01:33:53 PM PDT 23
Finished Oct 18 01:34:06 PM PDT 23
Peak memory 213352 kb
Host smart-cf47b7b3-8b2e-4a7f-aa0e-b7f17b02b042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7997166407129686195967658898201136441000233
8769169036799124728834274761022023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.799716640712
96861959676588982011364410002338769169036799124728834274761022023
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.33356352841404210452007933175735651925318861283587817026450315646422791622299
Short name T421
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.32 seconds
Started Oct 18 01:33:29 PM PDT 23
Finished Oct 18 01:33:41 PM PDT 23
Peak memory 210832 kb
Host smart-dfec6278-a32a-444d-b3c4-7cb24972477e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356352841404210452007933175735651925318861283587817026450315646422791622299 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.33356352841404210452007933175735651925318861283587817026450315646422791622299
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.100511457418827141531549833355351540745268897995713910139523105090953432179805
Short name T391
Test name
Test status
Simulation time 65914678386 ps
CPU time 280.53 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:38:38 PM PDT 23
Peak memory 218940 kb
Host smart-bf8775f8-3331-4f98-a97e-3260364f664e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100511457418827141531549833355351540745268897995713910139523105090953432179805 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.100511457418827141531549833355351540745268897995713910
139523105090953432179805
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.57157481152593424568444305497195338820783705827975459915963549480578391011761
Short name T70
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.23 seconds
Started Oct 18 01:34:06 PM PDT 23
Finished Oct 18 01:34:20 PM PDT 23
Peak memory 210904 kb
Host smart-4dc4bbe1-987d-4348-911b-6db8d208e14a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57157481152593424568444305497195338820783705827975459915963549480578391011761
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.57157481152593424568444305497195338820783705827975459
915963549480578391011761
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.98647303456508637424460576925675095849394162012784721468119381869899146696784
Short name T55
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.58 seconds
Started Oct 18 01:34:17 PM PDT 23
Finished Oct 18 01:34:34 PM PDT 23
Peak memory 219132 kb
Host smart-0ac10483-6006-4b2f-a501-9920e3f28367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98647303456508637424460576925675095849394162012784721468119381869899146696784 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.98647303456508637424460576925675095849394162012784721468119381869899146696784
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.44576046593274922496063175587422495273493694547820275870683962349589765239552
Short name T424
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.21 seconds
Started Oct 18 01:33:59 PM PDT 23
Finished Oct 18 01:35:20 PM PDT 23
Peak memory 211096 kb
Host smart-e991edc1-7d4e-4015-a8f0-8fc246d6de08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44576046593274922496063175587422495273493694547820275870683962349589765239552 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.44576046593274922496063175587422495273493694547820275870683962349589765239552
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.40994989225262333626230157998540058965203863356626721403928015637080807778227
Short name T417
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.1 seconds
Started Oct 18 01:33:59 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 210768 kb
Host smart-baf9b458-f64a-4cb0-80dc-d04360c2f765
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994989225262333626230157998540058965203863356626721403928015637080807778227 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.40994989225262333626230157998540058965203863356626721403928015637080807778227
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.56072116725036624874843631228627179208684326743528089489555829875534222646473
Short name T76
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Oct 18 01:34:07 PM PDT 23
Finished Oct 18 01:34:20 PM PDT 23
Peak memory 210856 kb
Host smart-f6742329-7ed9-460b-ac6a-a892114fdf60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56072116725036624874843631228627179208684326743528089489555829875534222646473 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.56072116725036624874843631228627179208684326743528089489555829875534222646473
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.90357186175000913370022468034921881576381351878470182471103078019092169524841
Short name T21
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.89 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 210840 kb
Host smart-cfce6315-ac16-4e44-b441-570e838ee1a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90357186175000913370022468034921881576381351878470182471103078019092169524841 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.90357186175000913370022468034921881576381351878470182471103078019092169524841
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.9831264673891675946544615674804638225366923441659709566663955513916038210228
Short name T443
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.28 seconds
Started Oct 18 01:33:29 PM PDT 23
Finished Oct 18 01:33:41 PM PDT 23
Peak memory 213488 kb
Host smart-fe95e2f8-250d-4125-82e7-23989f9e3588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9831264673891675946544615674804638225366923
441659709566663955513916038210228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.98312646738916
75946544615674804638225366923441659709566663955513916038210228
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.66922716637013987760612720496393802096929319906526432684690262817855615442956
Short name T386
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 18 01:33:28 PM PDT 23
Finished Oct 18 01:33:40 PM PDT 23
Peak memory 210880 kb
Host smart-cdcf99cc-e521-48d8-b1ce-97d8300ae17b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66922716637013987760612720496393802096929319906526432684690262817855615442956 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.66922716637013987760612720496393802096929319906526432684690262817855615442956
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.31318885945953694854389127414743176536127760623236647267041977193513895905629
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 18 01:33:13 PM PDT 23
Finished Oct 18 01:33:25 PM PDT 23
Peak memory 210844 kb
Host smart-2ff3ff46-9d60-4b11-92c3-ded13cfe0ecc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31318885945953694854389127414743176536127760623236647267041977193513895905629 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.3131888594595369485438912741474317653612776062323664726704
1977193513895905629
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.14416638692809249146571097606518721573086608737281731062187547825820562974090
Short name T366
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 18 01:33:15 PM PDT 23
Finished Oct 18 01:33:28 PM PDT 23
Peak memory 210864 kb
Host smart-b3e93470-9ad7-4bf3-b9c9-f0474381e5f5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14416638692809249146571097606518721573086608737281731062187547825820562974090 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.14416638692809249146571097606518721573086608737281731062187547825820562974090
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.78002410352187702695134975193669446179795903253205842984976089447017667288615
Short name T62
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.39 seconds
Started Oct 18 01:33:29 PM PDT 23
Finished Oct 18 01:38:10 PM PDT 23
Peak memory 218996 kb
Host smart-88448935-27bf-49f7-99db-f5cb04d24237
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78002410352187702695134975193669446179795903253205842984976089447017667288615 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.78002410352187702695134975193669446179795903253205842984
976089447017667288615
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.35473635359050897136428777243383952392817328417466058067724809260459693950376
Short name T435
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.69 seconds
Started Oct 18 01:33:28 PM PDT 23
Finished Oct 18 01:33:43 PM PDT 23
Peak memory 210888 kb
Host smart-24c7c2a6-ea02-4274-9a19-dbe110d11e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473635359050897136428777243383952392817328417466058067724809260459693950376
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.354736353590508971364287772433839523928173284174660580
67724809260459693950376
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.90645931402651205075661501144837523090559126490796604967105965086190463332001
Short name T67
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.32 seconds
Started Oct 18 01:33:15 PM PDT 23
Finished Oct 18 01:33:32 PM PDT 23
Peak memory 219104 kb
Host smart-15b36e6c-8a5b-4edc-980a-96ff9738f44c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90645931402651205075661501144837523090559126490796604967105965086190463332001 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.90645931402651205075661501144837523090559126490796604967105965086190463332001
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.19484905040631540708067010375562011324597435939657073198155793511102223092343
Short name T25
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.46 seconds
Started Oct 18 01:33:24 PM PDT 23
Finished Oct 18 01:34:45 PM PDT 23
Peak memory 211052 kb
Host smart-f126adb1-f494-400a-a6f5-82d12f51418a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19484905040631540708067010375562011324597435939657073198155793511102223092343 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.19484905040631540708067010375562011324597435939657073198155793511102223092343
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.88208369211337195212334057036583727741013727260170044664949379877692748399463
Short name T438
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 18 01:33:25 PM PDT 23
Finished Oct 18 01:33:38 PM PDT 23
Peak memory 210872 kb
Host smart-19a57ae7-7e9f-4ab5-8cbe-ca4e169bb578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88208369211337195212334057036583727741013727260170044664949379877692748399463 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.88208369211337195212334057036583727741013727260170044664949379877692748399463
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.60302217640094477272167451620887759872184958019043865347879792231508906844093
Short name T59
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Oct 18 01:34:31 PM PDT 23
Finished Oct 18 01:34:45 PM PDT 23
Peak memory 210748 kb
Host smart-5be28272-3512-49b7-b482-746c395f28e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60302217640094477272167451620887759872184958019043865347879792231508906844093 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.60302217640094477272167451620887759872184958019043865347879792231508906844093
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.40406491917946345912344344664669951302906800950734242842802360338525424849724
Short name T409
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.75 seconds
Started Oct 18 01:33:19 PM PDT 23
Finished Oct 18 01:33:35 PM PDT 23
Peak memory 210796 kb
Host smart-bcf826d2-fae9-4ddf-9bb4-5e2649ca4f97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40406491917946345912344344664669951302906800950734242842802360338525424849724 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.40406491917946345912344344664669951302906800950734242842802360338525424849724
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.77537119094190381737532629778832493948446202142700955599418350468352305619211
Short name T406
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.52 seconds
Started Oct 18 01:33:58 PM PDT 23
Finished Oct 18 01:34:12 PM PDT 23
Peak memory 213432 kb
Host smart-439c5248-3507-4ca7-bc29-6635db130cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7753711909419038173753262977883249394844620
2142700955599418350468352305619211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.7753711909419
0381737532629778832493948446202142700955599418350468352305619211
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.16782798491778747358733751782628457346463905135629949237287613543761570491183
Short name T437
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.69 seconds
Started Oct 18 01:34:08 PM PDT 23
Finished Oct 18 01:34:21 PM PDT 23
Peak memory 210904 kb
Host smart-66a0fc0c-5758-4bdf-af85-3f57b85da1d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782798491778747358733751782628457346463905135629949237287613543761570491183 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.16782798491778747358733751782628457346463905135629949237287613543761570491183
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.19208188779555116979730032118280623280625688939594791883911762366264016631331
Short name T370
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 18 01:34:09 PM PDT 23
Finished Oct 18 01:34:22 PM PDT 23
Peak memory 210840 kb
Host smart-f86dd901-f04a-4970-802f-dedd42c9db1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208188779555116979730032118280623280625688939594791883911762366264016631331 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.1920818877955511697973003211828062328062568893959479188391
1762366264016631331
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.108968560018257749684076661580091441473992946803303807989191613343750505271452
Short name T389
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 18 01:33:32 PM PDT 23
Finished Oct 18 01:33:45 PM PDT 23
Peak memory 210724 kb
Host smart-fa6328fa-9039-40cc-b9af-1fcdcc00db03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108968560018257749684076661580091441473992946803303807989191613343750505271452 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.108968560018257749684076661580091441473992946803303807989191613343750505271452
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.98045444138871014136775545325057702883741430402256210660599928465863517987321
Short name T63
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.46 seconds
Started Oct 18 01:33:14 PM PDT 23
Finished Oct 18 01:38:00 PM PDT 23
Peak memory 218940 kb
Host smart-cf88c298-5ceb-4343-98a8-1300eabba053
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98045444138871014136775545325057702883741430402256210660599928465863517987321 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.98045444138871014136775545325057702883741430402256210660
599928465863517987321
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.81991321384304412908355881340445193659535498768443354136668393220703587536721
Short name T405
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.27 seconds
Started Oct 18 01:34:23 PM PDT 23
Finished Oct 18 01:34:37 PM PDT 23
Peak memory 210856 kb
Host smart-e0418d52-e886-4f9c-8df9-ec83b7f34b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81991321384304412908355881340445193659535498768443354136668393220703587536721
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.819913213843044129083558813404451936595354987684433541
36668393220703587536721
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.86374088700887337351518654024355172321039289611656494685744789613126625229428
Short name T47
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.28 seconds
Started Oct 18 01:33:09 PM PDT 23
Finished Oct 18 01:33:27 PM PDT 23
Peak memory 219116 kb
Host smart-4fef1dce-4b36-4777-884a-153fa600f5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86374088700887337351518654024355172321039289611656494685744789613126625229428 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.86374088700887337351518654024355172321039289611656494685744789613126625229428
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.32695158297173462724962835413600546733013604122903069832108666659916185627442
Short name T51
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.56 seconds
Started Oct 18 01:33:25 PM PDT 23
Finished Oct 18 01:34:47 PM PDT 23
Peak memory 211040 kb
Host smart-a6f1845c-7b44-4792-9e4f-242213546718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695158297173462724962835413600546733013604122903069832108666659916185627442 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.32695158297173462724962835413600546733013604122903069832108666659916185627442
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.25245665882095078804006702719708828131347490981056176874402185444875694469692
Short name T88
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 18 01:34:30 PM PDT 23
Finished Oct 18 01:34:43 PM PDT 23
Peak memory 210832 kb
Host smart-3173fad0-6624-4355-802f-7693aceb91df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245665882095078804006702719708828131347490981056176874402185444875694469692 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.25245665882095078804006702719708828131347490981056176874402185444875694469692
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.98707951056350471988995028622698428415715973424091660238783763762916172563001
Short name T85
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.83 seconds
Started Oct 18 01:34:02 PM PDT 23
Finished Oct 18 01:34:15 PM PDT 23
Peak memory 210752 kb
Host smart-a364989b-9375-4add-9203-9674ec8c20be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98707951056350471988995028622698428415715973424091660238783763762916172563001 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.98707951056350471988995028622698428415715973424091660238783763762916172563001
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.54813549800996046569318362686651993262653361534358515222887059507051311956642
Short name T413
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.69 seconds
Started Oct 18 01:34:05 PM PDT 23
Finished Oct 18 01:34:21 PM PDT 23
Peak memory 210808 kb
Host smart-0d46d967-0e73-4ef9-bb1a-397cde6be84f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54813549800996046569318362686651993262653361534358515222887059507051311956642 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.54813549800996046569318362686651993262653361534358515222887059507051311956642
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.33018021825763971273988673589182068562893425948567063339595291453170790288831
Short name T390
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.21 seconds
Started Oct 18 01:34:44 PM PDT 23
Finished Oct 18 01:34:57 PM PDT 23
Peak memory 213484 kb
Host smart-6ffd2722-7a7b-4e80-bb5f-d89604656792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301802182576397127398867358918206856289342
5948567063339595291453170790288831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3301802182576
3971273988673589182068562893425948567063339595291453170790288831
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.15335614989687244674091309112980838379371474706737013355894854347622978497011
Short name T93
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:08 PM PDT 23
Peak memory 210780 kb
Host smart-7369939d-37fb-400a-b92a-f54e84479ce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15335614989687244674091309112980838379371474706737013355894854347622978497011 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.15335614989687244674091309112980838379371474706737013355894854347622978497011
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.14101714119165179564954842163769279988916609054349785781391005178757453084189
Short name T381
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 18 01:34:06 PM PDT 23
Finished Oct 18 01:34:18 PM PDT 23
Peak memory 210844 kb
Host smart-92765645-efe7-4d71-abab-a3859fec96a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14101714119165179564954842163769279988916609054349785781391005178757453084189 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.1410171411916517956495484216376927998891660905434978578139
1005178757453084189
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3997043880611415396529122167785695261517864361486661370696776899781341042077
Short name T371
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.92 seconds
Started Oct 18 01:34:41 PM PDT 23
Finished Oct 18 01:34:55 PM PDT 23
Peak memory 210816 kb
Host smart-5ebf4c35-5da5-4537-9121-00bce5a57742
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997043880611415396529122167785695261517864361486661370696776899781341042077 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.3997043880611415396529122167785695261517864361486661370696776899781341042077
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.19061734515534818671669567773676539049314706516528677771620402596867555181057
Short name T61
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.63 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:38:42 PM PDT 23
Peak memory 218980 kb
Host smart-21a1a73a-d6be-4776-9265-641d8254aa6f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19061734515534818671669567773676539049314706516528677771620402596867555181057 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.19061734515534818671669567773676539049314706516528677771
620402596867555181057
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.88946790070346025470397961985688854187588323911935225133740786022983923775156
Short name T368
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.72 seconds
Started Oct 18 01:34:07 PM PDT 23
Finished Oct 18 01:34:21 PM PDT 23
Peak memory 210836 kb
Host smart-be080701-0fdf-4065-afe4-b25fab8c9c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88946790070346025470397961985688854187588323911935225133740786022983923775156
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.889467900703460254703979619856888541875883239119352251
33740786022983923775156
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.71749145759698525587307844609058500978337814538498177184510676200975361689188
Short name T53
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.01 seconds
Started Oct 18 01:34:18 PM PDT 23
Finished Oct 18 01:34:34 PM PDT 23
Peak memory 219072 kb
Host smart-9d1078a7-a368-49db-8b4c-647cc7a891a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71749145759698525587307844609058500978337814538498177184510676200975361689188 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.71749145759698525587307844609058500978337814538498177184510676200975361689188
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.36583888668424320388424609570146742198030802627789572299336729907167587759710
Short name T446
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.78 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:35:17 PM PDT 23
Peak memory 211000 kb
Host smart-a335adbe-adbd-44e7-94dc-73ce8712b8db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583888668424320388424609570146742198030802627789572299336729907167587759710 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.36583888668424320388424609570146742198030802627789572299336729907167587759710
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.43656929942429114555088332264391624332590293662059172285191465393290706638668
Short name T374
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.42 seconds
Started Oct 18 01:33:14 PM PDT 23
Finished Oct 18 01:33:28 PM PDT 23
Peak memory 213456 kb
Host smart-998dea11-0035-4036-a527-c7b0e71ff958
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4365692994242911455508833226439162433259029
3662059172285191465393290706638668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.4365692994242
9114555088332264391624332590293662059172285191465393290706638668
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.43097014209941646349965532699915940814502305604700719356116577855199279050232
Short name T422
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 18 01:34:26 PM PDT 23
Finished Oct 18 01:34:39 PM PDT 23
Peak memory 210768 kb
Host smart-fb478854-1b9d-4d20-a2a1-7f20c3f51892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43097014209941646349965532699915940814502305604700719356116577855199279050232 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.43097014209941646349965532699915940814502305604700719356116577855199279050232
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.54206507710199004492091233150474697689563214777867512657890124714586862461954
Short name T385
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.9 seconds
Started Oct 18 01:34:44 PM PDT 23
Finished Oct 18 01:39:32 PM PDT 23
Peak memory 219020 kb
Host smart-016b5f20-9597-4ff1-980a-df92a10405e3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54206507710199004492091233150474697689563214777867512657890124714586862461954 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.54206507710199004492091233150474697689563214777867512657
890124714586862461954
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.89394541212194165827222427443726489462471015943028798849662408498354721300194
Short name T79
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.13 seconds
Started Oct 18 01:34:54 PM PDT 23
Finished Oct 18 01:35:09 PM PDT 23
Peak memory 210876 kb
Host smart-b23fd761-b36b-4113-80b7-8f94ea5998d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89394541212194165827222427443726489462471015943028798849662408498354721300194
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.893945412121941658272224274437264894624710159430287988
49662408498354721300194
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.20978908098599858204363159202773032396246160753733741776287314529842240321118
Short name T66
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.15 seconds
Started Oct 18 01:34:23 PM PDT 23
Finished Oct 18 01:34:39 PM PDT 23
Peak memory 219108 kb
Host smart-b1b895f4-45ab-4880-9e19-461430521758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978908098599858204363159202773032396246160753733741776287314529842240321118 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.20978908098599858204363159202773032396246160753733741776287314529842240321118
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.105191372180501029413335925655927836225593356642675714815378075940753148801742
Short name T383
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.99 seconds
Started Oct 18 01:34:30 PM PDT 23
Finished Oct 18 01:35:50 PM PDT 23
Peak memory 210916 kb
Host smart-5a30155c-9fcc-4bdf-b261-3106c102e6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105191372180501029413335925655927836225593356642675714815378075940753148801742 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.105191372180501029413335925655927836225593356642675714815378075940753148801742
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.49044090199471624250673506737680958577528714626912683830602117801177135696576
Short name T364
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.48 seconds
Started Oct 18 01:33:55 PM PDT 23
Finished Oct 18 01:34:08 PM PDT 23
Peak memory 213424 kb
Host smart-e1e40755-eb2b-4b99-be27-9f6a8209d499
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4904409019947162425067350673768095857752871
4626912683830602117801177135696576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4904409019947
1624250673506737680958577528714626912683830602117801177135696576
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.84120736027830832990379075304715007644176629563061845521564229669426951722067
Short name T363
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.94 seconds
Started Oct 18 01:33:32 PM PDT 23
Finished Oct 18 01:33:44 PM PDT 23
Peak memory 210752 kb
Host smart-a8007c30-c1db-4403-90dc-207f78d1faf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84120736027830832990379075304715007644176629563061845521564229669426951722067 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.84120736027830832990379075304715007644176629563061845521564229669426951722067
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.9832834214848336483796993292877261916876771124124772214385162847137266542191
Short name T69
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.5 seconds
Started Oct 18 01:34:03 PM PDT 23
Finished Oct 18 01:38:49 PM PDT 23
Peak memory 218944 kb
Host smart-630eefd2-1c0a-46ed-a6e0-1ffab7fbbdb8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9832834214848336483796993292877261916876771124124772214385162847137266542191 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.983283421484833648379699329287726191687677112412477221438
5162847137266542191
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.99808429685661608886048724559236616947490599469295990227781778764030402262499
Short name T397
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.92 seconds
Started Oct 18 01:33:28 PM PDT 23
Finished Oct 18 01:33:42 PM PDT 23
Peak memory 210860 kb
Host smart-e12dafb7-84a1-4053-bfca-7e25fc5157fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99808429685661608886048724559236616947490599469295990227781778764030402262499
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.998084296856616088860487245592366169474905994692959902
27781778764030402262499
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.73893606091938258573354739961363605613720442936459997595803799276655999107652
Short name T22
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.55 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:44 PM PDT 23
Peak memory 219164 kb
Host smart-ab1faa8f-fa86-4b6a-b294-b1d01705f00c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73893606091938258573354739961363605613720442936459997595803799276655999107652 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.73893606091938258573354739961363605613720442936459997595803799276655999107652
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.84353695148136854110691208900423480770266908890870873006673532875920804881485
Short name T361
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.41 seconds
Started Oct 18 01:33:25 PM PDT 23
Finished Oct 18 01:34:46 PM PDT 23
Peak memory 211064 kb
Host smart-dbf6c0d4-c471-491b-81c0-9a00f32dea67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84353695148136854110691208900423480770266908890870873006673532875920804881485 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.84353695148136854110691208900423480770266908890870873006673532875920804881485
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.51517375645696499430732645408514942921765307476265603813276560468016339767283
Short name T379
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.5 seconds
Started Oct 18 01:33:58 PM PDT 23
Finished Oct 18 01:34:11 PM PDT 23
Peak memory 213424 kb
Host smart-0d326186-58f2-4ec4-808b-047d988f8a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5151737564569649943073264540851494292176530
7476265603813276560468016339767283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.5151737564569
6499430732645408514942921765307476265603813276560468016339767283
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.103403920441897197000192481949566835114189510714621001451575086703100550755146
Short name T439
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 18 01:33:56 PM PDT 23
Finished Oct 18 01:34:09 PM PDT 23
Peak memory 210892 kb
Host smart-1f757c7a-c6e5-4559-ac49-80eb85753786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103403920441897197000192481949566835114189510714621001451575086703100550755146 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.103403920441897197000192481949566835114189510714621001451575086703100550755146
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.10409765927404579228057000742762438635342955790243592601664811642068262252174
Short name T434
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.65 seconds
Started Oct 18 01:33:26 PM PDT 23
Finished Oct 18 01:38:09 PM PDT 23
Peak memory 218980 kb
Host smart-e4f680d0-8cad-49e0-bef8-620953136398
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409765927404579228057000742762438635342955790243592601664811642068262252174 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.10409765927404579228057000742762438635342955790243592601
664811642068262252174
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.39659553639205202854632179637576563250994263853836833110406598628243574555405
Short name T375
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.04 seconds
Started Oct 18 01:33:26 PM PDT 23
Finished Oct 18 01:33:41 PM PDT 23
Peak memory 210784 kb
Host smart-7791e7d9-3f56-4c49-bf3b-740850e4886c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39659553639205202854632179637576563250994263853836833110406598628243574555405
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.396595536392052028546321796375765632509942638538368331
10406598628243574555405
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.47366885364771343341458162545822772294106530482504061650603663895914909428581
Short name T444
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.02 seconds
Started Oct 18 01:33:27 PM PDT 23
Finished Oct 18 01:33:44 PM PDT 23
Peak memory 219124 kb
Host smart-86642cb0-2665-4b37-8fd2-180016875585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47366885364771343341458162545822772294106530482504061650603663895914909428581 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.47366885364771343341458162545822772294106530482504061650603663895914909428581
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.85669002667111492167293448555928864318793940537679959685134809594967205461272
Short name T92
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.81 seconds
Started Oct 18 01:33:32 PM PDT 23
Finished Oct 18 01:34:53 PM PDT 23
Peak memory 210960 kb
Host smart-1566927d-dff5-4522-98b7-16095b5b4696
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85669002667111492167293448555928864318793940537679959685134809594967205461272 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.85669002667111492167293448555928864318793940537679959685134809594967205461272
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.71052427022677738081675388581939945311392976717451777858186734218355448261250
Short name T450
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.38 seconds
Started Oct 18 01:33:32 PM PDT 23
Finished Oct 18 01:33:45 PM PDT 23
Peak memory 213424 kb
Host smart-d983c3ee-7cff-4b30-a8f1-05accdd4a0df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7105242702267773808167538858193994531139297
6717451777858186734218355448261250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.7105242702267
7738081675388581939945311392976717451777858186734218355448261250
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.61626612826328634424580526291569549566890616233094053379687092489756025664039
Short name T23
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Oct 18 01:33:14 PM PDT 23
Finished Oct 18 01:33:27 PM PDT 23
Peak memory 210868 kb
Host smart-3774a1de-445d-4f11-aa15-c81277e0be72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61626612826328634424580526291569549566890616233094053379687092489756025664039 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.61626612826328634424580526291569549566890616233094053379687092489756025664039
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.14572314281957048279200456894554075530694517991374071009648125618319360502141
Short name T436
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.65 seconds
Started Oct 18 01:33:51 PM PDT 23
Finished Oct 18 01:38:39 PM PDT 23
Peak memory 219060 kb
Host smart-f9116737-23dc-49e6-8804-34e290f649e7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14572314281957048279200456894554075530694517991374071009648125618319360502141 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.14572314281957048279200456894554075530694517991374071009
648125618319360502141
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.19868391328642317415001457906403691038727240189822446904374719642273093916658
Short name T369
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.24 seconds
Started Oct 18 01:34:21 PM PDT 23
Finished Oct 18 01:34:36 PM PDT 23
Peak memory 210892 kb
Host smart-74494599-4007-46a1-8b5b-6941b949a8c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868391328642317415001457906403691038727240189822446904374719642273093916658
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.198683913286423174150014579064036910387272401898224469
04374719642273093916658
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1233989379821127559007457457857096385346207340035380662375531259306537767601
Short name T412
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.49 seconds
Started Oct 18 01:33:31 PM PDT 23
Finished Oct 18 01:33:48 PM PDT 23
Peak memory 219060 kb
Host smart-e184e8cd-c8af-4ac2-a0ae-1a60cd65807a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233989379821127559007457457857096385346207340035380662375531259306537767601 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1233989379821127559007457457857096385346207340035380662375531259306537767601
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.83292364472467304210179295222651758811664688392379180461112126532549305579066
Short name T431
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.38 seconds
Started Oct 18 01:33:57 PM PDT 23
Finished Oct 18 01:35:18 PM PDT 23
Peak memory 211080 kb
Host smart-d98ebad0-5669-467b-9216-139fa7321487
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83292364472467304210179295222651758811664688392379180461112126532549305579066 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.83292364472467304210179295222651758811664688392379180461112126532549305579066
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.70640017349088118983357988298998174838640791846123420406998049788982742652544
Short name T20
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.29 seconds
Started Oct 18 01:33:13 PM PDT 23
Finished Oct 18 01:33:27 PM PDT 23
Peak memory 213388 kb
Host smart-9157102c-000c-40d2-83e8-cf15336450ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7064001734908811898335798829899817483864079
1846123420406998049788982742652544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.7064001734908
8118983357988298998174838640791846123420406998049788982742652544
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.96799658918080794418370658126061203305202941334028132238030264696593869401058
Short name T382
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Oct 18 01:33:58 PM PDT 23
Finished Oct 18 01:34:11 PM PDT 23
Peak memory 210860 kb
Host smart-e73d523d-a01d-4fda-92bf-bf7d2307b8ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96799658918080794418370658126061203305202941334028132238030264696593869401058 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.96799658918080794418370658126061203305202941334028132238030264696593869401058
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.56772615476420153581000382713708369331175793128929071501105776469946258088631
Short name T30
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.73 seconds
Started Oct 18 01:34:04 PM PDT 23
Finished Oct 18 01:38:51 PM PDT 23
Peak memory 219024 kb
Host smart-4af86008-73e9-4e11-beb0-8ccf3ef5d2cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56772615476420153581000382713708369331175793128929071501105776469946258088631 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.56772615476420153581000382713708369331175793128929071501
105776469946258088631
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.12385475151173409113655718711973966738132548423156655179575537352280444487149
Short name T57
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.39 seconds
Started Oct 18 01:33:19 PM PDT 23
Finished Oct 18 01:33:34 PM PDT 23
Peak memory 210840 kb
Host smart-18bec66d-485c-4558-a501-92ad508bc707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385475151173409113655718711973966738132548423156655179575537352280444487149
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.123854751511734091136557187119739667381325484231566551
79575537352280444487149
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.43363398988710361490413689540326262513375157360527621096532578545889375107550
Short name T54
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.24 seconds
Started Oct 18 01:33:15 PM PDT 23
Finished Oct 18 01:33:32 PM PDT 23
Peak memory 219096 kb
Host smart-459163bb-4ca1-4929-93e7-642c3aab7e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43363398988710361490413689540326262513375157360527621096532578545889375107550 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.43363398988710361490413689540326262513375157360527621096532578545889375107550
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.63999074134791514287799247253721897722810192905077862567013914984924216323117
Short name T403
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.18 seconds
Started Oct 18 01:33:26 PM PDT 23
Finished Oct 18 01:34:48 PM PDT 23
Peak memory 211112 kb
Host smart-4b7a0c14-eaf9-4795-98b7-a8c4e1c1153a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63999074134791514287799247253721897722810192905077862567013914984924216323117 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.63999074134791514287799247253721897722810192905077862567013914984924216323117
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.66636143593620182789227885784840977687230767150020820369193006837437519512535
Short name T327
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.87 seconds
Started Oct 18 12:25:16 PM PDT 23
Finished Oct 18 12:25:29 PM PDT 23
Peak memory 211348 kb
Host smart-bc3c5a19-26b7-472b-8e02-b072a4e0b092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66636143593620182789227885784840977687230767150020820369193006837437519512535 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.66636143593620182789227885784840977687230767150020820369193006837437519512535
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.80984221063610528913542852362743642081907750101355165109015756178064209774362
Short name T355
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.31 seconds
Started Oct 18 12:21:25 PM PDT 23
Finished Oct 18 12:27:10 PM PDT 23
Peak memory 237596 kb
Host smart-7a100e51-601c-4ae9-8b76-de5c3ac8d2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80984221063610528913542852362743642081907750101355165109015756178064209774362 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.8098422106361052891354285236274364208190775010135516510901
5756178064209774362
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.17416109307735599472868807191610250840433103140795536770879963226913209157518
Short name T153
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.97 seconds
Started Oct 18 12:27:46 PM PDT 23
Finished Oct 18 12:27:59 PM PDT 23
Peak memory 211084 kb
Host smart-e07ae987-8edc-45a4-8b79-13a6b51b53ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17416109307735599472868807191610250840433103140795536770879963226913209157518 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.17416109307735599472868807191610250840433103140795536770879963226913209157518
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.74032136880188780385260895180115337697616161449561548684130019678741963296170
Short name T306
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 18 12:25:14 PM PDT 23
Finished Oct 18 12:25:27 PM PDT 23
Peak memory 209748 kb
Host smart-7542bfa0-e48e-487d-9eeb-c3616511da9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74032136880188780385260895180115337697616161449561548684130019678741963296170 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.74032136880188780385260895180115337697616161449561548684130019678741963296170
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.34841222180344027739061698565054180012707621973345436432076328594104366046419
Short name T273
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.25 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:33:04 PM PDT 23
Peak memory 237328 kb
Host smart-d70f855b-d035-4335-8733-d2f03df1f301
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841222180344027739061698565054180012707621973345436432076328594104366046419 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.3484122218034402773906169856505418001270762197334543643207
6328594104366046419
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.43041468698756746066892785137179634304166536388386320467294547549634366911919
Short name T269
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.78 seconds
Started Oct 18 12:27:24 PM PDT 23
Finished Oct 18 12:27:50 PM PDT 23
Peak memory 210712 kb
Host smart-18c5cabc-ba75-470b-b9a1-a7273c984e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43041468698756746066892785137179634304166536388386320467294547549634366911919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rom_ctrl_kmac_err_chk.43041468698756746066892785137179634304166536388386320467294547549634366911919
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.4379341646838012327426937751563271133383702691322909728031468865266100328840
Short name T205
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Oct 18 12:25:18 PM PDT 23
Finished Oct 18 12:25:31 PM PDT 23
Peak memory 210764 kb
Host smart-273ce366-5720-4446-9e33-d3169e551dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4379341646838012327426937751563271133383702691322909728031468865266100328840 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.4379341646838012327426937751563271133383702691322909728031468865266100328840
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.19331984059970609280937453435313854228844236318999678996164296583223754697760
Short name T31
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.73 seconds
Started Oct 18 12:26:25 PM PDT 23
Finished Oct 18 12:28:20 PM PDT 23
Peak memory 236748 kb
Host smart-11a2fd10-e338-46d9-bc91-475e78641765
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331984059970609280937453435313854228844236318999678996164296583223754697760 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.19331984059970609280937453435313854228844236318999678996164296583223754697760
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.20169549910070710528264924161159178358974830656621902819247766055232682386533
Short name T331
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.53 seconds
Started Oct 18 12:22:37 PM PDT 23
Finished Oct 18 12:23:06 PM PDT 23
Peak memory 212940 kb
Host smart-7178a3cf-11f5-48bc-84f2-3f9a09bef509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20169549910070710528264924161159178358974830656621902819247766055232682386533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_smoke.20169549910070710528264924161159178358974830656621902819247766055232682386533
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.77356494154318121146819422294267747393698306765699523542814605032760968251990
Short name T194
Test name
Test status
Simulation time 9415977006 ps
CPU time 43 seconds
Started Oct 18 12:25:14 PM PDT 23
Finished Oct 18 12:25:58 PM PDT 23
Peak memory 211324 kb
Host smart-a0d9eef9-9a88-47f9-9cfd-45212dd0057e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773564941543181211468194222942677473936983067656995235428146050
32760968251990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.773564941543181211468194222942677473936983067656995
23542814605032760968251990
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.87733238586501743919500357603421428523445795043359407496975190371107308020396
Short name T122
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 18 12:26:26 PM PDT 23
Finished Oct 18 12:26:44 PM PDT 23
Peak memory 211080 kb
Host smart-760c3d7b-036f-4d54-afe0-520752d179dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87733238586501743919500357603421428523445795043359407496975190371107308020396 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.87733238586501743919500357603421428523445795043359407496975190371107308020396
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.76357540123781037950096157673811022708109092584235785543134832079696651399043
Short name T304
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.92 seconds
Started Oct 18 12:30:31 PM PDT 23
Finished Oct 18 12:36:13 PM PDT 23
Peak memory 237592 kb
Host smart-fd434c34-86a1-49a9-bd6a-58aa9215e38e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76357540123781037950096157673811022708109092584235785543134832079696651399043 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.763575401237810379500961576738110227081090925842357855431
34832079696651399043
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.28252529011989240085151489213624521780640595984439606028617906245154811263515
Short name T308
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.97 seconds
Started Oct 18 12:33:20 PM PDT 23
Finished Oct 18 12:33:46 PM PDT 23
Peak memory 211504 kb
Host smart-bb543554-9194-43ee-8372-bfeb49177dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28252529011989240085151489213624521780640595984439606028617906245154811263515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rom_ctrl_kmac_err_chk.28252529011989240085151489213624521780640595984439606028617906245154811263515
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.45149287337101943472823882772287955976141291502910119093440718745057975164966
Short name T211
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.85 seconds
Started Oct 18 12:23:19 PM PDT 23
Finished Oct 18 12:23:33 PM PDT 23
Peak memory 211060 kb
Host smart-cc18b5f6-8124-4890-952d-71af4c210cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45149287337101943472823882772287955976141291502910119093440718745057975164966 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.45149287337101943472823882772287955976141291502910119093440718745057975164966
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.18352034843374940240963680233243211688632254161629625775028814876878259619497
Short name T172
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.5 seconds
Started Oct 18 12:22:55 PM PDT 23
Finished Oct 18 12:23:24 PM PDT 23
Peak memory 212736 kb
Host smart-7cfe6724-7848-4725-8b11-43861962ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18352034843374940240963680233243211688632254161629625775028814876878259619497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.rom_ctrl_smoke.18352034843374940240963680233243211688632254161629625775028814876878259619497
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.50159783860905485536033712519760663955023124273637450636492842087387621225444
Short name T204
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.89 seconds
Started Oct 18 12:29:55 PM PDT 23
Finished Oct 18 12:30:39 PM PDT 23
Peak memory 213016 kb
Host smart-792ea266-bfe1-4923-99e9-3121ad12fc4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501597838609054855360337125197606639550231242736374506364928420
87387621225444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.50159783860905485536033712519760663955023124273637
450636492842087387621225444
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.77416568524229302065296374566233535176564754203770575769338372575901305706909
Short name T120
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.5 seconds
Started Oct 18 12:25:31 PM PDT 23
Finished Oct 18 12:25:44 PM PDT 23
Peak memory 210560 kb
Host smart-295840a0-614f-411a-849d-ce4ce19b0cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77416568524229302065296374566233535176564754203770575769338372575901305706909 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.77416568524229302065296374566233535176564754203770575769338372575901305706909
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.46963388613274874865734800441934235501424921826890392619099401666098999114848
Short name T297
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.96 seconds
Started Oct 18 12:30:55 PM PDT 23
Finished Oct 18 12:36:38 PM PDT 23
Peak memory 237576 kb
Host smart-4c4a6178-da28-4def-8113-c5190fb30bf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46963388613274874865734800441934235501424921826890392619099401666098999114848 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.469633886132748748657348004419342355014249218268903926190
99401666098999114848
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.13718709134593826787645727801475000309756269494677310426802969053331617682700
Short name T35
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.42 seconds
Started Oct 18 12:27:54 PM PDT 23
Finished Oct 18 12:28:19 PM PDT 23
Peak memory 211512 kb
Host smart-1d1e174b-f699-40a5-8246-703e17129ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13718709134593826787645727801475000309756269494677310426802969053331617682700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.rom_ctrl_kmac_err_chk.13718709134593826787645727801475000309756269494677310426802969053331617682700
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.111357685913146402549672784399460674561566375907630796316638242927851525954478
Short name T326
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.61 seconds
Started Oct 18 12:25:53 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 212404 kb
Host smart-01653715-d241-4837-bef9-eb9c84a0db23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111357685913146402549672784399460674561566375907630796316638242927851525954478 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_smoke.111357685913146402549672784399460674561566375907630796316638242927851525954478
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.14902709119831741986904646363503914894156110808336564213837931817394801056460
Short name T251
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.96 seconds
Started Oct 18 12:30:03 PM PDT 23
Finished Oct 18 12:30:45 PM PDT 23
Peak memory 212864 kb
Host smart-048ffc35-209d-4920-a6dd-2c49cb6f9ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149027091198317419869046463635039148941561108083365642138379318
17394801056460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.14902709119831741986904646363503914894156110808336
564213837931817394801056460
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.87332554765509797074871424340159872883688604038792297415559572132952663727133
Short name T156
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 18 12:39:41 PM PDT 23
Finished Oct 18 12:39:55 PM PDT 23
Peak memory 211092 kb
Host smart-65757bb2-2626-4163-8a2d-875d61400002
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87332554765509797074871424340159872883688604038792297415559572132952663727133 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.87332554765509797074871424340159872883688604038792297415559572132952663727133
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.25033249664288833455358138105291745388329597734722680368581404897361491892030
Short name T42
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.93 seconds
Started Oct 18 12:33:45 PM PDT 23
Finished Oct 18 12:39:25 PM PDT 23
Peak memory 237620 kb
Host smart-b7c5727d-6888-4a0d-a4c4-1a28286a8d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25033249664288833455358138105291745388329597734722680368581404897361491892030 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.250332496642888334553581381052917453883295977347226803685
81404897361491892030
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.18175934877748570825408704963339310287785698123104370073775530894193586182340
Short name T296
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Oct 18 12:25:56 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 210908 kb
Host smart-6bab985a-69ce-42c3-a93b-b825ea3bb0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18175934877748570825408704963339310287785698123104370073775530894193586182340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rom_ctrl_kmac_err_chk.18175934877748570825408704963339310287785698123104370073775530894193586182340
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.45393090700464440575316095265531439804198592584007403118623851316635734825736
Short name T196
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.18 seconds
Started Oct 18 12:34:27 PM PDT 23
Finished Oct 18 12:34:40 PM PDT 23
Peak memory 211088 kb
Host smart-9866abe8-2177-4611-b68d-2b4e2d3ddb32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45393090700464440575316095265531439804198592584007403118623851316635734825736 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.45393090700464440575316095265531439804198592584007403118623851316635734825736
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.92869807991657448922891581589567269370291789749394910874506087332703261938585
Short name T81
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.98 seconds
Started Oct 18 12:25:32 PM PDT 23
Finished Oct 18 12:26:00 PM PDT 23
Peak memory 212440 kb
Host smart-48927251-267b-4297-aec3-a1e91fab6ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92869807991657448922891581589567269370291789749394910874506087332703261938585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.rom_ctrl_smoke.92869807991657448922891581589567269370291789749394910874506087332703261938585
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.34353196501606020526605650528023884416451374588064099560909821755296843959528
Short name T303
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.7 seconds
Started Oct 18 12:32:43 PM PDT 23
Finished Oct 18 12:33:26 PM PDT 23
Peak memory 212852 kb
Host smart-7cc85da5-ed7a-4e59-83f2-6c0151ca6edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343531965016060205266056505280238844164513745880640995609098217
55296843959528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.34353196501606020526605650528023884416451374588064
099560909821755296843959528
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.59373896073893878341526157995160568756420010604842587932210929911213340197733
Short name T168
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 18 12:27:02 PM PDT 23
Finished Oct 18 12:27:15 PM PDT 23
Peak memory 211048 kb
Host smart-e35e754f-bfbd-4e1b-ab2b-fca4955e45ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59373896073893878341526157995160568756420010604842587932210929911213340197733 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.59373896073893878341526157995160568756420010604842587932210929911213340197733
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1056698456782484169474354211154378803438959286217213598121614043058304556873
Short name T163
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.5 seconds
Started Oct 18 12:33:25 PM PDT 23
Finished Oct 18 12:39:05 PM PDT 23
Peak memory 237668 kb
Host smart-d009198b-2b07-4829-b869-5f8578017661
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056698456782484169474354211154378803438959286217213598121614043058304556873 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.1056698456782484169474354211154378803438959286217213598121
614043058304556873
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.8685680934972102793319122209240219805348413989637442920151341394271906864267
Short name T271
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.69 seconds
Started Oct 18 12:22:54 PM PDT 23
Finished Oct 18 12:23:20 PM PDT 23
Peak memory 211648 kb
Host smart-2a24496c-0a43-48a7-930b-bff6bcaee511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8685680934972102793319122209240219805348413989637442920151341394271906864267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.rom_ctrl_kmac_err_chk.8685680934972102793319122209240219805348413989637442920151341394271906864267
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.8123621901262964766180612811528652597555525030691353180353027242957643808073
Short name T339
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 18 12:27:52 PM PDT 23
Finished Oct 18 12:28:06 PM PDT 23
Peak memory 210252 kb
Host smart-1596f017-b23c-4ff9-8e2c-2d5d268d6400
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8123621901262964766180612811528652597555525030691353180353027242957643808073 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.8123621901262964766180612811528652597555525030691353180353027242957643808073
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.102245517465782125229190592146619568354461674907675417825095475372267162627434
Short name T7
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.84 seconds
Started Oct 18 12:27:40 PM PDT 23
Finished Oct 18 12:28:09 PM PDT 23
Peak memory 212728 kb
Host smart-316e22b7-d4c5-4c57-b43e-a8c9946bf7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102245517465782125229190592146619568354461674907675417825095475372267162627434 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.rom_ctrl_smoke.102245517465782125229190592146619568354461674907675417825095475372267162627434
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.60776054697120462505261591685763454408920736498911881494956475638989670982809
Short name T121
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.2 seconds
Started Oct 18 12:28:21 PM PDT 23
Finished Oct 18 12:29:03 PM PDT 23
Peak memory 212832 kb
Host smart-09ef93f5-cc85-43d8-97b0-6f182cf9d56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607760546971204625052615916857634544089207364989118814949564756
38989670982809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.60776054697120462505261591685763454408920736498911
881494956475638989670982809
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.70403489173755483599828453870949798298641342490912375999780169344235086673990
Short name T176
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Oct 18 12:30:01 PM PDT 23
Finished Oct 18 12:30:14 PM PDT 23
Peak memory 211040 kb
Host smart-a5f9b8c1-f6f2-4a61-b3ba-deb6e16b55c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70403489173755483599828453870949798298641342490912375999780169344235086673990 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.70403489173755483599828453870949798298641342490912375999780169344235086673990
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.84551085324053748397019171056920899663770345967546605608885134774488857105625
Short name T41
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.69 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:31:48 PM PDT 23
Peak memory 237304 kb
Host smart-f5037fab-f786-4cad-ad39-ec2c1d519236
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84551085324053748397019171056920899663770345967546605608885134774488857105625 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.845510853240537483970191710569208996637703459675466056088
85134774488857105625
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.48857496110290294138327970005462136843658157421122460249807216350280775606724
Short name T209
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.29 seconds
Started Oct 18 12:26:04 PM PDT 23
Finished Oct 18 12:26:30 PM PDT 23
Peak memory 211184 kb
Host smart-51fa9142-8f2c-4af8-bcd3-319b201847a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48857496110290294138327970005462136843658157421122460249807216350280775606724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.48857496110290294138327970005462136843658157421122460249807216350280775606724
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.35030143819861698198521489357922650847025332458198431588829807928761510698806
Short name T157
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 210100 kb
Host smart-37ad4e2b-3d6d-4043-b2de-bb672cb40e8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35030143819861698198521489357922650847025332458198431588829807928761510698806 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.35030143819861698198521489357922650847025332458198431588829807928761510698806
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.33972623378962478282778776760807621592296911847541711302573570855053238911565
Short name T349
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.24 seconds
Started Oct 18 12:26:09 PM PDT 23
Finished Oct 18 12:26:38 PM PDT 23
Peak memory 212448 kb
Host smart-2c839f38-7de6-4c89-9040-d4cf6b7734bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33972623378962478282778776760807621592296911847541711302573570855053238911565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_smoke.33972623378962478282778776760807621592296911847541711302573570855053238911565
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.80915039510687636437474854684476398098332184997411960241785802876198793530428
Short name T323
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.75 seconds
Started Oct 18 12:36:41 PM PDT 23
Finished Oct 18 12:37:25 PM PDT 23
Peak memory 212876 kb
Host smart-155713fd-9c9c-4fa0-bf8f-bebc0afe513a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809150395106876364374748546844763980983321849974119602417858028
76198793530428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.80915039510687636437474854684476398098332184997411
960241785802876198793530428
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.70550021699252408915639684199867175566004800231770121564417580531278931009464
Short name T225
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 18 12:31:24 PM PDT 23
Finished Oct 18 12:31:36 PM PDT 23
Peak memory 211176 kb
Host smart-421845d4-b53b-40cf-9f9e-07d305dc3a70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70550021699252408915639684199867175566004800231770121564417580531278931009464 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.70550021699252408915639684199867175566004800231770121564417580531278931009464
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.18344607501662078169712791271503301932961680404691743492662962427302295151839
Short name T43
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.45 seconds
Started Oct 18 12:41:08 PM PDT 23
Finished Oct 18 12:46:51 PM PDT 23
Peak memory 237740 kb
Host smart-542252f0-e23d-4b99-aa42-62d846f90386
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344607501662078169712791271503301932961680404691743492662962427302295151839 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.183446075016620781697127912715033019329616804046917434926
62962427302295151839
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.51805216077144397519842705634330900285715336682691507045804107903076420848187
Short name T311
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.97 seconds
Started Oct 18 12:40:31 PM PDT 23
Finished Oct 18 12:40:57 PM PDT 23
Peak memory 211616 kb
Host smart-ca376780-9b2a-41e6-bcc6-0096c182d8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51805216077144397519842705634330900285715336682691507045804107903076420848187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.51805216077144397519842705634330900285715336682691507045804107903076420848187
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.30900893123672116561926472963605883704800487898567062984457598153468744786999
Short name T174
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.88 seconds
Started Oct 18 12:28:08 PM PDT 23
Finished Oct 18 12:28:23 PM PDT 23
Peak memory 211088 kb
Host smart-d18f6efa-6751-47c6-8938-33e05f779589
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30900893123672116561926472963605883704800487898567062984457598153468744786999 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.30900893123672116561926472963605883704800487898567062984457598153468744786999
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.18838217436469520205002036714692065036364765307766815948131576174398672310751
Short name T148
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.03 seconds
Started Oct 18 12:36:18 PM PDT 23
Finished Oct 18 12:36:47 PM PDT 23
Peak memory 212724 kb
Host smart-56e46724-1102-4ec6-842f-31792985cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18838217436469520205002036714692065036364765307766815948131576174398672310751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.18838217436469520205002036714692065036364765307766815948131576174398672310751
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.94409657340833113338575770406786434580383426305543186683976585817068850542117
Short name T107
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.8 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:27:04 PM PDT 23
Peak memory 212832 kb
Host smart-f77e95a9-4384-4dbc-8928-6229461b0471
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944096573408331133385757704067864345803834263055431866839765858
17068850542117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.94409657340833113338575770406786434580383426305543
186683976585817068850542117
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.37012269949649029671063469758919746879504796596362436467190646707731371441314
Short name T33
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 18 12:36:18 PM PDT 23
Finished Oct 18 12:36:30 PM PDT 23
Peak memory 211176 kb
Host smart-cf314925-0ecb-42da-a175-d2daa2408e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012269949649029671063469758919746879504796596362436467190646707731371441314 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.37012269949649029671063469758919746879504796596362436467190646707731371441314
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.50806273885185531155680467163216873863293996749260484131222066636187143850319
Short name T44
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.36 seconds
Started Oct 18 12:46:21 PM PDT 23
Finished Oct 18 12:52:02 PM PDT 23
Peak memory 237692 kb
Host smart-463154aa-6fe2-4537-800e-e85103e976ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50806273885185531155680467163216873863293996749260484131222066636187143850319 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.508062738851855311556804671632168738632939967492604841312
22066636187143850319
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.18022997598009402832224848796653901360662716599285495112274456822175900190436
Short name T357
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.04 seconds
Started Oct 18 12:28:13 PM PDT 23
Finished Oct 18 12:28:38 PM PDT 23
Peak memory 211496 kb
Host smart-c70d6cc7-e28a-4942-b385-e35a812d9020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18022997598009402832224848796653901360662716599285495112274456822175900190436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.rom_ctrl_kmac_err_chk.18022997598009402832224848796653901360662716599285495112274456822175900190436
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.13403251205521674859563178778132770151566346927438799256475285461974278844988
Short name T259
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Oct 18 12:29:01 PM PDT 23
Finished Oct 18 12:29:16 PM PDT 23
Peak memory 211076 kb
Host smart-b62c9894-a4da-467c-81dc-f7661c889bd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13403251205521674859563178778132770151566346927438799256475285461974278844988 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.13403251205521674859563178778132770151566346927438799256475285461974278844988
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.48093476220965147567780938798391090147023607481092937647550951918613795253536
Short name T127
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.63 seconds
Started Oct 18 12:25:58 PM PDT 23
Finished Oct 18 12:26:27 PM PDT 23
Peak memory 212804 kb
Host smart-e8f05d22-b7e5-4a8d-8dda-11a18863c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48093476220965147567780938798391090147023607481092937647550951918613795253536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_smoke.48093476220965147567780938798391090147023607481092937647550951918613795253536
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.77303886978807626668021345203022253207155556440422015059099638753369997196033
Short name T73
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.54 seconds
Started Oct 18 12:33:49 PM PDT 23
Finished Oct 18 12:34:31 PM PDT 23
Peak memory 212836 kb
Host smart-8dee10a3-414b-4cbc-b4be-b29c692ad6ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773038869788076266680213452030222532071555564404220150590996387
53369997196033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.77303886978807626668021345203022253207155556440422
015059099638753369997196033
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.19782395960344337247013630300192153381397738043116405967260451950834197732426
Short name T305
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:21 PM PDT 23
Peak memory 210684 kb
Host smart-01de24d2-8316-4c23-adae-db3130d488bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19782395960344337247013630300192153381397738043116405967260451950834197732426 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.19782395960344337247013630300192153381397738043116405967260451950834197732426
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.15263549307469727272604103557468995877919681518748773502246528839833397363677
Short name T118
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.67 seconds
Started Oct 18 12:31:59 PM PDT 23
Finished Oct 18 12:37:37 PM PDT 23
Peak memory 237580 kb
Host smart-0ada70ab-0af4-4b0d-9769-b3e002cbe174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15263549307469727272604103557468995877919681518748773502246528839833397363677 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.152635493074697272726041035574689958779196815187487735022
46528839833397363677
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.53934919908493955796878342790945801382783696210108024522864031758537982366069
Short name T302
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.43 seconds
Started Oct 18 12:26:38 PM PDT 23
Finished Oct 18 12:27:03 PM PDT 23
Peak memory 211260 kb
Host smart-e4a4c478-97da-472f-b939-fcbfd6bf7cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53934919908493955796878342790945801382783696210108024522864031758537982366069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rom_ctrl_kmac_err_chk.53934919908493955796878342790945801382783696210108024522864031758537982366069
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.37617995872549071275644181789308766446071834239115070771036242079087838592765
Short name T189
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 18 12:28:30 PM PDT 23
Finished Oct 18 12:28:44 PM PDT 23
Peak memory 211080 kb
Host smart-0ba4f505-f2db-4db9-8a3b-0c498e7a1970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37617995872549071275644181789308766446071834239115070771036242079087838592765 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.37617995872549071275644181789308766446071834239115070771036242079087838592765
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1631828405330394923345589771218573724517041431710943467650591539907674192386
Short name T138
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.09 seconds
Started Oct 18 12:22:40 PM PDT 23
Finished Oct 18 12:23:08 PM PDT 23
Peak memory 212716 kb
Host smart-29ffcce5-0641-47f4-9a14-806b894d5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631828405330394923345589771218573724517041431710943467650591539907674192386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.rom_ctrl_smoke.1631828405330394923345589771218573724517041431710943467650591539907674192386
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.77127515420766017163390053831601039277430954621614215011793321455400793903350
Short name T343
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.52 seconds
Started Oct 18 12:29:47 PM PDT 23
Finished Oct 18 12:30:29 PM PDT 23
Peak memory 212832 kb
Host smart-e5bcb092-46b3-4f43-8164-f7123df89dc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771275154207660171633900538316010392774309546216142150117933214
55400793903350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.77127515420766017163390053831601039277430954621614
215011793321455400793903350
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.31893163968295588546081359506838740150212630762427915121562996600602589541477
Short name T166
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.82 seconds
Started Oct 18 12:40:59 PM PDT 23
Finished Oct 18 12:46:44 PM PDT 23
Peak memory 237732 kb
Host smart-099f4e73-4181-48c0-8f24-3962c3ef4a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893163968295588546081359506838740150212630762427915121562996600602589541477 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.318931639682955885460813595068387401502126307624279151215
62996600602589541477
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.51437887902038283865343124168218280884483996667127039124879298806771364444526
Short name T10
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.75 seconds
Started Oct 18 12:30:04 PM PDT 23
Finished Oct 18 12:30:30 PM PDT 23
Peak memory 211596 kb
Host smart-61fbe744-f553-4df6-9a16-799cecb8892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51437887902038283865343124168218280884483996667127039124879298806771364444526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.51437887902038283865343124168218280884483996667127039124879298806771364444526
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.27500556017287460325975460570298433727828497909525672251476995815955061404746
Short name T197
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Oct 18 12:41:40 PM PDT 23
Finished Oct 18 12:41:54 PM PDT 23
Peak memory 211144 kb
Host smart-0b36dbfd-7cdd-4b2d-8a4e-99676bcb65f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27500556017287460325975460570298433727828497909525672251476995815955061404746 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.27500556017287460325975460570298433727828497909525672251476995815955061404746
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.45902984530388782170818914208786879467048234351946725282558292092031470007196
Short name T328
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.73 seconds
Started Oct 18 12:36:42 PM PDT 23
Finished Oct 18 12:37:10 PM PDT 23
Peak memory 212744 kb
Host smart-c7418257-9243-48d1-8d9b-a91c016bceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45902984530388782170818914208786879467048234351946725282558292092031470007196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.45902984530388782170818914208786879467048234351946725282558292092031470007196
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.815281720764133413642380962927562275793580847613409927909279041032498208821
Short name T124
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.34 seconds
Started Oct 18 12:30:44 PM PDT 23
Finished Oct 18 12:31:27 PM PDT 23
Peak memory 212824 kb
Host smart-a2afdecb-1ce6-4d75-8ba6-d1a25a1eb43a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815281720764133413642380962927562275793580847613409927909279041
032498208821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.8152817207641334136423809629275622757935808476134099
27909279041032498208821
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.69889226798808261929071285216822471161132171080940019978849773724505223017110
Short name T223
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:19 PM PDT 23
Peak memory 210132 kb
Host smart-e00d6667-f361-4c34-91ce-6a699f7367b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69889226798808261929071285216822471161132171080940019978849773724505223017110 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.69889226798808261929071285216822471161132171080940019978849773724505223017110
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.73417865243965386805890820452540170967007887515154219230332533488594391306002
Short name T320
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.6 seconds
Started Oct 18 12:27:56 PM PDT 23
Finished Oct 18 12:33:36 PM PDT 23
Peak memory 236804 kb
Host smart-a7f1a6c9-da89-47b9-b02a-3873bd07ed47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73417865243965386805890820452540170967007887515154219230332533488594391306002 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.734178652439653868058908204525401709670078875151542192303
32533488594391306002
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.71832948265174041256853682706920751349851354644557131922910065630314584338758
Short name T201
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.47 seconds
Started Oct 18 12:28:09 PM PDT 23
Finished Oct 18 12:28:35 PM PDT 23
Peak memory 211392 kb
Host smart-82b7dfed-2b1e-4b55-b904-61bb26fdbaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71832948265174041256853682706920751349851354644557131922910065630314584338758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.rom_ctrl_kmac_err_chk.71832948265174041256853682706920751349851354644557131922910065630314584338758
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.58976386871860556919576619571817586486871198639205528893420789302949539531956
Short name T244
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.04 seconds
Started Oct 18 12:28:11 PM PDT 23
Finished Oct 18 12:28:24 PM PDT 23
Peak memory 211044 kb
Host smart-dd225d7c-7ee2-4c69-86ee-c8bdfe9631c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58976386871860556919576619571817586486871198639205528893420789302949539531956 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.58976386871860556919576619571817586486871198639205528893420789302949539531956
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.113877360459186982993887278156514532663163365783324055406917387794870698698949
Short name T347
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.01 seconds
Started Oct 18 12:29:46 PM PDT 23
Finished Oct 18 12:30:14 PM PDT 23
Peak memory 212724 kb
Host smart-aaef9655-b86e-49f2-8548-ffc7ab375f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113877360459186982993887278156514532663163365783324055406917387794870698698949 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.rom_ctrl_smoke.113877360459186982993887278156514532663163365783324055406917387794870698698949
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.53615249447433716642710759780626379477079665604311871596541706434852955819902
Short name T182
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.05 seconds
Started Oct 18 12:27:55 PM PDT 23
Finished Oct 18 12:28:37 PM PDT 23
Peak memory 212820 kb
Host smart-bf7609b2-e30b-4046-b336-76da6e41eba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536152494474337166427107597806263794770796656043118715965417064
34852955819902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.53615249447433716642710759780626379477079665604311
871596541706434852955819902
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.8075910023657294375923734462071388096122901019251026801906069099046839475344
Short name T261
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.18 seconds
Started Oct 18 12:27:37 PM PDT 23
Finished Oct 18 12:27:49 PM PDT 23
Peak memory 211136 kb
Host smart-2de2c329-a9fa-43ed-8084-d2e01059692b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8075910023657294375923734462071388096122901019251026801906069099046839475344 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.8075910023657294375923734462071388096122901019251026801906069099046839475344
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.94985004963212682509563670798898128719362104693583226226153118568585084853957
Short name T150
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.69 seconds
Started Oct 18 12:25:14 PM PDT 23
Finished Oct 18 12:30:56 PM PDT 23
Peak memory 236136 kb
Host smart-9ba8a596-41b7-4c9b-b27a-8414f017b7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94985004963212682509563670798898128719362104693583226226153118568585084853957 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.9498500496321268250956367079889812871936210469358322622615
3118568585084853957
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.18519492676090412987314932371550693554847507720726962038887043444685954911894
Short name T290
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.35 seconds
Started Oct 18 12:21:24 PM PDT 23
Finished Oct 18 12:21:50 PM PDT 23
Peak memory 211412 kb
Host smart-1dd7b7c6-f465-4c90-813b-926fdfe76698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18519492676090412987314932371550693554847507720726962038887043444685954911894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.rom_ctrl_kmac_err_chk.18519492676090412987314932371550693554847507720726962038887043444685954911894
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.9869046819940951450665783505045061506201406620242435666121114333292429269203
Short name T180
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Oct 18 12:25:15 PM PDT 23
Finished Oct 18 12:25:28 PM PDT 23
Peak memory 210460 kb
Host smart-f2f42a1a-3b58-4720-b21b-6f5d40bdc098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9869046819940951450665783505045061506201406620242435666121114333292429269203 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.9869046819940951450665783505045061506201406620242435666121114333292429269203
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.95800812280330160374899081848463269644567760694905921890484339513616648208281
Short name T27
Test name
Test status
Simulation time 3444857586 ps
CPU time 119.32 seconds
Started Oct 18 12:23:32 PM PDT 23
Finished Oct 18 12:25:32 PM PDT 23
Peak memory 236788 kb
Host smart-ee19fee0-eca5-417a-a1cf-41bf4842a881
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95800812280330160374899081848463269644567760694905921890484339513616648208281 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.95800812280330160374899081848463269644567760694905921890484339513616648208281
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.34299820594332511156733877045220183267102585843285796635863281540376199267191
Short name T154
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.74 seconds
Started Oct 18 12:25:07 PM PDT 23
Finished Oct 18 12:25:36 PM PDT 23
Peak memory 212672 kb
Host smart-617a61e8-6331-45e1-a19e-9a0a0306bb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34299820594332511156733877045220183267102585843285796635863281540376199267191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.34299820594332511156733877045220183267102585843285796635863281540376199267191
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.74862208963433039146667752564950905307528823198931652298438782601006668301160
Short name T336
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.45 seconds
Started Oct 18 12:22:40 PM PDT 23
Finished Oct 18 12:23:23 PM PDT 23
Peak memory 212836 kb
Host smart-4c279500-cc6d-4ab8-a6eb-0efd598ad9fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748622089634330391466677525649509053075288231989316522984387826
01006668301160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.748622089634330391466677525649509053075288231989316
52298438782601006668301160
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.55847528363615500312379981683943519876773303541807802962677887405898501105112
Short name T358
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 18 12:25:50 PM PDT 23
Finished Oct 18 12:26:02 PM PDT 23
Peak memory 210652 kb
Host smart-737fe5d8-021e-4631-800b-670dc709aad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55847528363615500312379981683943519876773303541807802962677887405898501105112 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.55847528363615500312379981683943519876773303541807802962677887405898501105112
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.83295947239638762653292642487841716730534596942138778244804939167292312276060
Short name T344
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.74 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:31:41 PM PDT 23
Peak memory 237052 kb
Host smart-270b4506-d7dd-4d5c-bd97-280237074334
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83295947239638762653292642487841716730534596942138778244804939167292312276060 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.832959472396387626532926424878417167305345969421387782448
04939167292312276060
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.10282642590231750738038727755506610760042103807054160738083379670954479917952
Short name T99
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.01 seconds
Started Oct 18 12:25:53 PM PDT 23
Finished Oct 18 12:26:18 PM PDT 23
Peak memory 211256 kb
Host smart-63fd773e-f651-4d0e-8836-d5693da008e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10282642590231750738038727755506610760042103807054160738083379670954479917952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.rom_ctrl_kmac_err_chk.10282642590231750738038727755506610760042103807054160738083379670954479917952
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.64322527144292684159414774958745316994206733635157635999690102490699246724869
Short name T250
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Oct 18 12:24:18 PM PDT 23
Finished Oct 18 12:24:32 PM PDT 23
Peak memory 211292 kb
Host smart-096560c1-9ed3-4cf0-aa4d-a667a22ed2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64322527144292684159414774958745316994206733635157635999690102490699246724869 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.64322527144292684159414774958745316994206733635157635999690102490699246724869
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.114077695275273649356157510448300551777579214378896077544424916710481314602375
Short name T185
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.14 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 212232 kb
Host smart-93150bdb-59c7-4940-a07a-63556d11c41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114077695275273649356157510448300551777579214378896077544424916710481314602375 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.rom_ctrl_smoke.114077695275273649356157510448300551777579214378896077544424916710481314602375
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.35720427669713264193516616660459557380749333360549894048249261516352808279840
Short name T288
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.3 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:49 PM PDT 23
Peak memory 212840 kb
Host smart-c5e1fbef-80a6-41f5-b240-1fbeedd419c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357204276697132641935166166604595573807493333605498940482492615
16352808279840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.35720427669713264193516616660459557380749333360549
894048249261516352808279840
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.31334746073840417201797587990996454665391268285934037301388390607692655487790
Short name T260
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.99 seconds
Started Oct 18 12:27:49 PM PDT 23
Finished Oct 18 12:28:01 PM PDT 23
Peak memory 210832 kb
Host smart-ea01cf54-658f-4395-95b4-edf07ad0347b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31334746073840417201797587990996454665391268285934037301388390607692655487790 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.31334746073840417201797587990996454665391268285934037301388390607692655487790
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.85550781825634839846206636142526859136392473479418884777135454826023492786305
Short name T164
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.4 seconds
Started Oct 18 12:24:04 PM PDT 23
Finished Oct 18 12:29:51 PM PDT 23
Peak memory 237568 kb
Host smart-6baba5db-95a7-4f44-983c-68f9be71258b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85550781825634839846206636142526859136392473479418884777135454826023492786305 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.855507818256348398462066361425268591363924734794188847771
35454826023492786305
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.7453951027156124811492085941258378035710405312187395334248818751831069079092
Short name T113
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.13 seconds
Started Oct 18 12:25:32 PM PDT 23
Finished Oct 18 12:25:58 PM PDT 23
Peak memory 211256 kb
Host smart-be656339-d768-4846-b4de-d712606bad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7453951027156124811492085941258378035710405312187395334248818751831069079092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.rom_ctrl_kmac_err_chk.7453951027156124811492085941258378035710405312187395334248818751831069079092
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.97450455445252401519763192477291318202759900494744399980273173569190576124720
Short name T82
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 18 12:28:15 PM PDT 23
Finished Oct 18 12:28:30 PM PDT 23
Peak memory 209812 kb
Host smart-830d0062-da5b-4fd3-930e-f172f393696d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97450455445252401519763192477291318202759900494744399980273173569190576124720 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.97450455445252401519763192477291318202759900494744399980273173569190576124720
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.111940871521700486640678102399118963004442923637434955678700054886609946953375
Short name T253
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.75 seconds
Started Oct 18 12:25:31 PM PDT 23
Finished Oct 18 12:26:00 PM PDT 23
Peak memory 212444 kb
Host smart-2076e10d-177e-4511-aa12-d1c438016ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111940871521700486640678102399118963004442923637434955678700054886609946953375 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_smoke.111940871521700486640678102399118963004442923637434955678700054886609946953375
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.61651906867574429101801061045589775007437635430550339738091293655285751126749
Short name T169
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.28 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 212672 kb
Host smart-f87d4d4c-fdd4-4f43-b487-71fd16c070b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616519068675744291018010610455897750074376354305503397380912936
55285751126749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.61651906867574429101801061045589775007437635430550
339738091293655285751126749
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.103889008687492579461048853189993728643183121826798880783198204600409343672145
Short name T278
Test name
Test status
Simulation time 3124113076 ps
CPU time 13 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:25:46 PM PDT 23
Peak memory 210820 kb
Host smart-9c0fb5be-c2be-43e7-af8a-7594e9310da7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103889008687492579461048853189993728643183121826798880783198204600409343672145 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.103889008687492579461048853189993728643183121826798880783198204600409343672145
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.34749655276461575566632500101878552363049465137354083298072120639139076156420
Short name T45
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.89 seconds
Started Oct 18 12:25:13 PM PDT 23
Finished Oct 18 12:30:58 PM PDT 23
Peak memory 237584 kb
Host smart-3a0c4ff3-176f-4c1e-8969-bd54b121b9e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749655276461575566632500101878552363049465137354083298072120639139076156420 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.347496552764615755666325001018785523630494651373540832980
72120639139076156420
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.25650812284232759700503020018448789419400710792402721605871106369904294008130
Short name T152
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.06 seconds
Started Oct 18 12:28:06 PM PDT 23
Finished Oct 18 12:28:32 PM PDT 23
Peak memory 211480 kb
Host smart-ecd41991-0e5a-41a8-a450-7f3f0fbb9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25650812284232759700503020018448789419400710792402721605871106369904294008130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.rom_ctrl_kmac_err_chk.25650812284232759700503020018448789419400710792402721605871106369904294008130
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.88441564882739312486708940089599622889661522279007385790736847130950197784286
Short name T334
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:19 PM PDT 23
Peak memory 211084 kb
Host smart-b7ab7650-904c-48ac-b635-7c6b76841152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88441564882739312486708940089599622889661522279007385790736847130950197784286 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.88441564882739312486708940089599622889661522279007385790736847130950197784286
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.15651889483924444621350317813657422461488664671154593270990372562559204530574
Short name T149
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.06 seconds
Started Oct 18 12:27:40 PM PDT 23
Finished Oct 18 12:28:08 PM PDT 23
Peak memory 211924 kb
Host smart-f2703438-4b16-4df2-b171-b6e91d6ef9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15651889483924444621350317813657422461488664671154593270990372562559204530574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_smoke.15651889483924444621350317813657422461488664671154593270990372562559204530574
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.50031563144917162911289720612400803935655657646103383495531039480025114246787
Short name T256
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.34 seconds
Started Oct 18 12:29:41 PM PDT 23
Finished Oct 18 12:30:23 PM PDT 23
Peak memory 212828 kb
Host smart-0e641cfd-c993-4667-8bfc-bdfe4c3c18e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500315631449171629112897206124008039356556576461033834955310394
80025114246787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.50031563144917162911289720612400803935655657646103
383495531039480025114246787
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.23215581500514001306118841561917419721561179943457860857941280715307544519843
Short name T254
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 18 12:25:29 PM PDT 23
Finished Oct 18 12:25:42 PM PDT 23
Peak memory 210220 kb
Host smart-0c9bc2ff-fbcf-4673-85b2-68ba2b17dc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23215581500514001306118841561917419721561179943457860857941280715307544519843 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.23215581500514001306118841561917419721561179943457860857941280715307544519843
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.55456685890581829689196117634527537475021224939509609629062672178564952434111
Short name T240
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.36 seconds
Started Oct 18 12:25:34 PM PDT 23
Finished Oct 18 12:26:00 PM PDT 23
Peak memory 210388 kb
Host smart-3e3656b6-62ff-4849-b192-77912e5aa95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55456685890581829689196117634527537475021224939509609629062672178564952434111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.rom_ctrl_kmac_err_chk.55456685890581829689196117634527537475021224939509609629062672178564952434111
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.55746386319005273752392517928736607438437002284692159596116378897305127240714
Short name T155
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:25:47 PM PDT 23
Peak memory 210840 kb
Host smart-f353acf8-0566-4b5b-b121-0e6438293d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55746386319005273752392517928736607438437002284692159596116378897305127240714 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.55746386319005273752392517928736607438437002284692159596116378897305127240714
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.61503804846929248051624065946106017191297112009023648356644708355954005140821
Short name T314
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.89 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:26:01 PM PDT 23
Peak memory 212468 kb
Host smart-aba4a935-e098-451c-92b7-bbcf2dae12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61503804846929248051624065946106017191297112009023648356644708355954005140821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.61503804846929248051624065946106017191297112009023648356644708355954005140821
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.39693212035779318843696658160348734898832125877765862865718826507575614879368
Short name T227
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.26 seconds
Started Oct 18 12:27:55 PM PDT 23
Finished Oct 18 12:28:37 PM PDT 23
Peak memory 212540 kb
Host smart-c1c10aca-0590-4897-bbbe-b3bf56319fac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396932120357793188436966581603487348988321258777658628657188265
07575614879368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.39693212035779318843696658160348734898832125877765
862865718826507575614879368
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.51563087169009897256320146991906330827365715917059934869650558271109384359129
Short name T178
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 18 12:28:10 PM PDT 23
Finished Oct 18 12:28:23 PM PDT 23
Peak memory 211048 kb
Host smart-00fcc25d-aa0a-4a9b-bf22-e2179f0a8ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51563087169009897256320146991906330827365715917059934869650558271109384359129 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.51563087169009897256320146991906330827365715917059934869650558271109384359129
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.23212830093853160927441579536378886698078711676935215278715379541793271440435
Short name T173
Test name
Test status
Simulation time 69854280986 ps
CPU time 328.91 seconds
Started Oct 18 12:25:32 PM PDT 23
Finished Oct 18 12:31:02 PM PDT 23
Peak memory 237292 kb
Host smart-b42cb09c-a599-4237-b902-3f53cf4c2e34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23212830093853160927441579536378886698078711676935215278715379541793271440435 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.232128300938531609274415795363788866980787116769352152787
15379541793271440435
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.111590528641144748960081202647188235152854907509724509924124915302394608051821
Short name T16
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.42 seconds
Started Oct 18 12:33:44 PM PDT 23
Finished Oct 18 12:34:09 PM PDT 23
Peak memory 211584 kb
Host smart-689f893f-c6a8-446c-b0b7-a791a42644f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111590528641144748960081202647188235152854907509724509924124915302394608051821 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.rom_ctrl_kmac_err_chk.111590528641144748960081202647188235152854907509724509924124915302394608051821
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.7615367351821730081843656033011968283987793738164442666889698638923140446555
Short name T279
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 18 12:25:34 PM PDT 23
Finished Oct 18 12:25:48 PM PDT 23
Peak memory 210100 kb
Host smart-30b0f7ac-5619-4686-afb8-8b28878d2dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7615367351821730081843656033011968283987793738164442666889698638923140446555 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.7615367351821730081843656033011968283987793738164442666889698638923140446555
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.106008788872681495348704806074628394943907391807560750632371651366826235943355
Short name T319
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.18 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:26:02 PM PDT 23
Peak memory 212488 kb
Host smart-c7aaf29e-097a-47ba-b6e9-cdc6766cddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106008788872681495348704806074628394943907391807560750632371651366826235943355 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.rom_ctrl_smoke.106008788872681495348704806074628394943907391807560750632371651366826235943355
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.45604787733173080975247982641280784348098004853408589416592577281578628322602
Short name T137
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.04 seconds
Started Oct 18 12:29:17 PM PDT 23
Finished Oct 18 12:30:00 PM PDT 23
Peak memory 212800 kb
Host smart-c9ca19b3-6312-4353-8793-14a48ed5d8d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456047877331730809752479826412807843480980048534085894165925772
81578628322602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.45604787733173080975247982641280784348098004853408
589416592577281578628322602
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.77679649938231108761790005971347651697832046390049932966837582432841293945634
Short name T102
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.56 seconds
Started Oct 18 12:23:16 PM PDT 23
Finished Oct 18 12:23:28 PM PDT 23
Peak memory 211200 kb
Host smart-98245670-b49a-44db-9a87-a1612bf405d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77679649938231108761790005971347651697832046390049932966837582432841293945634 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.77679649938231108761790005971347651697832046390049932966837582432841293945634
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.84126453156226767155707364010562573344581603069564277509179536898138205439563
Short name T188
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.83 seconds
Started Oct 18 12:31:13 PM PDT 23
Finished Oct 18 12:36:53 PM PDT 23
Peak memory 237552 kb
Host smart-39cbc8a9-acf5-4782-bd5a-74d6561c6b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84126453156226767155707364010562573344581603069564277509179536898138205439563 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.841264531562267671557073640105625733445816030695642775091
79536898138205439563
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.105098325492553240999815110548383622235782893709786323847401038650843224959860
Short name T229
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.3 seconds
Started Oct 18 12:26:57 PM PDT 23
Finished Oct 18 12:27:24 PM PDT 23
Peak memory 211224 kb
Host smart-da3124ee-feb4-4003-b626-9d2cbebc47d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105098325492553240999815110548383622235782893709786323847401038650843224959860 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rom_ctrl_kmac_err_chk.105098325492553240999815110548383622235782893709786323847401038650843224959860
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.22566419455607103182011291125419835754687819973744720049473409534375602882462
Short name T213
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 18 12:28:41 PM PDT 23
Finished Oct 18 12:28:55 PM PDT 23
Peak memory 211096 kb
Host smart-901b123a-fe3c-4d48-b5b3-06c732d18987
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22566419455607103182011291125419835754687819973744720049473409534375602882462 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.22566419455607103182011291125419835754687819973744720049473409534375602882462
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.92612064971052843021919622032823218159336958752081055724945828721313168425003
Short name T289
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.12 seconds
Started Oct 18 12:28:07 PM PDT 23
Finished Oct 18 12:28:35 PM PDT 23
Peak memory 212688 kb
Host smart-c512cc95-d35e-4b10-aa3a-d6dc472402bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92612064971052843021919622032823218159336958752081055724945828721313168425003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_smoke.92612064971052843021919622032823218159336958752081055724945828721313168425003
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.43507614170193820465381847881526464055358510408904844244081221131237897396621
Short name T281
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.82 seconds
Started Oct 18 12:27:41 PM PDT 23
Finished Oct 18 12:28:28 PM PDT 23
Peak memory 212804 kb
Host smart-0f5403d1-4ec6-4f58-b828-839b0203d9e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435076141701938204653818478815264640553585104089048442440812211
31237897396621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.43507614170193820465381847881526464055358510408904
844244081221131237897396621
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.78279273885136098149885977238191297121992576435467602434119252149966896521361
Short name T333
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 18 12:27:56 PM PDT 23
Finished Oct 18 12:28:09 PM PDT 23
Peak memory 211044 kb
Host smart-bf046450-e5d5-4dd5-91a7-6b6c9490f306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78279273885136098149885977238191297121992576435467602434119252149966896521361 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.78279273885136098149885977238191297121992576435467602434119252149966896521361
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.87899300721459120983726214716830674217327538537190588495077318245281079147516
Short name T179
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.71 seconds
Started Oct 18 12:28:15 PM PDT 23
Finished Oct 18 12:33:53 PM PDT 23
Peak memory 236324 kb
Host smart-ffa851ad-edb3-494f-a567-79466ff04de5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87899300721459120983726214716830674217327538537190588495077318245281079147516 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.878993007214591209837262147168306742173275385371905884950
77318245281079147516
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.56902010407000512771864286202187933835551986962080194697614582548169113260594
Short name T143
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.79 seconds
Started Oct 18 12:23:54 PM PDT 23
Finished Oct 18 12:24:21 PM PDT 23
Peak memory 211720 kb
Host smart-017172e6-06c7-461f-96f6-bea973938b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56902010407000512771864286202187933835551986962080194697614582548169113260594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.56902010407000512771864286202187933835551986962080194697614582548169113260594
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.14473690386376732162421529586454017105893705952305784233054020513033353957199
Short name T123
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.01 seconds
Started Oct 18 12:34:13 PM PDT 23
Finished Oct 18 12:34:27 PM PDT 23
Peak memory 211040 kb
Host smart-e96e85c2-4a80-4bb9-9a53-4f2a21dcb681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14473690386376732162421529586454017105893705952305784233054020513033353957199 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.14473690386376732162421529586454017105893705952305784233054020513033353957199
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.16306039869262955754068386053877856657616354526998107386452193574425872251610
Short name T175
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.81 seconds
Started Oct 18 12:23:05 PM PDT 23
Finished Oct 18 12:23:34 PM PDT 23
Peak memory 212768 kb
Host smart-6c20ab06-0442-4c12-ae6c-3bc882705d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16306039869262955754068386053877856657616354526998107386452193574425872251610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.16306039869262955754068386053877856657616354526998107386452193574425872251610
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.35596996545700083962175272093208297012672589603410384557742648489373899959685
Short name T12
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.39 seconds
Started Oct 18 12:28:26 PM PDT 23
Finished Oct 18 12:29:09 PM PDT 23
Peak memory 212804 kb
Host smart-448682ab-907d-40b8-a087-082434f2555b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355969965457000839621752720932082970126725896034103845577426484
89373899959685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.35596996545700083962175272093208297012672589603410
384557742648489373899959685
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.94815471045390771489337710133998957450348122013323729227436132868620964187208
Short name T284
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.63 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:28 PM PDT 23
Peak memory 211024 kb
Host smart-8f1e6814-f4eb-4f29-8a6e-56bde5dcb617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94815471045390771489337710133998957450348122013323729227436132868620964187208 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.94815471045390771489337710133998957450348122013323729227436132868620964187208
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.77139953488220074833112039760792478222373015918584400642822135711907460599618
Short name T316
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.68 seconds
Started Oct 18 12:25:30 PM PDT 23
Finished Oct 18 12:31:06 PM PDT 23
Peak memory 237228 kb
Host smart-ced5a50a-20e4-4694-8418-5eaf9f368359
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77139953488220074833112039760792478222373015918584400642822135711907460599618 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.771399534882200748331120397607924782223730159185844006428
22135711907460599618
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.50024941409898042051464335456991796387918613364666346929494732038741494056236
Short name T146
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.34 seconds
Started Oct 18 12:24:39 PM PDT 23
Finished Oct 18 12:25:05 PM PDT 23
Peak memory 211516 kb
Host smart-ce7deffb-9391-4f9a-88a4-a52b944a776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50024941409898042051464335456991796387918613364666346929494732038741494056236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rom_ctrl_kmac_err_chk.50024941409898042051464335456991796387918613364666346929494732038741494056236
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.82665628134353133001917830855439469668257826860832067423286099950583056473753
Short name T83
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.8 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:26 PM PDT 23
Peak memory 211212 kb
Host smart-f221fc31-7c4a-43c7-9365-d184f2ce436b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82665628134353133001917830855439469668257826860832067423286099950583056473753 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.82665628134353133001917830855439469668257826860832067423286099950583056473753
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.107008541538639775103240320201911175167945048731059414456834994409309863682678
Short name T345
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.13 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 212828 kb
Host smart-53f9e979-24ab-44a9-ae36-0252fa6a1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107008541538639775103240320201911175167945048731059414456834994409309863682678 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.rom_ctrl_smoke.107008541538639775103240320201911175167945048731059414456834994409309863682678
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.51813699079227933369790569008151100404346664073512214247618767360114714281536
Short name T108
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.78 seconds
Started Oct 18 12:26:34 PM PDT 23
Finished Oct 18 12:27:17 PM PDT 23
Peak memory 212804 kb
Host smart-05264eb1-94d2-4b5e-94e8-74b966caa706
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518136990792279333697905690081511004043466640735122142476187673
60114714281536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.51813699079227933369790569008151100404346664073512
214247618767360114714281536
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.10550902172168126622887420652236518942061159936903193050826640221569166822959
Short name T322
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.8 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:24 PM PDT 23
Peak memory 210760 kb
Host smart-3b421e94-187b-4c49-8031-fe10d193ffa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550902172168126622887420652236518942061159936903193050826640221569166822959 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.10550902172168126622887420652236518942061159936903193050826640221569166822959
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.29136986637758506603256037311886511128681196615884960736696381978542540340418
Short name T299
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.63 seconds
Started Oct 18 12:26:59 PM PDT 23
Finished Oct 18 12:32:31 PM PDT 23
Peak memory 237444 kb
Host smart-56e19cd7-2f76-4f16-8772-23ecf8d2117c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136986637758506603256037311886511128681196615884960736696381978542540340418 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.291369866377585066032560373118865111286811966158849607366
96381978542540340418
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.59456396946824982833756431472176135421364280852448937677607081021015956622544
Short name T248
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.32 seconds
Started Oct 18 12:25:33 PM PDT 23
Finished Oct 18 12:26:00 PM PDT 23
Peak memory 211676 kb
Host smart-7194c9ab-61a3-46fa-a81b-ea8caf075113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59456396946824982833756431472176135421364280852448937677607081021015956622544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rom_ctrl_kmac_err_chk.59456396946824982833756431472176135421364280852448937677607081021015956622544
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.47327079387275159245872037368517708968560182764377637451077706392769931236961
Short name T263
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:26:16 PM PDT 23
Peak memory 210284 kb
Host smart-9e667141-5fa2-4e84-8849-748f2b5fb178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47327079387275159245872037368517708968560182764377637451077706392769931236961 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.47327079387275159245872037368517708968560182764377637451077706392769931236961
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.48561381089948121818281354392108284541974266031129361449289540295338759874715
Short name T116
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.93 seconds
Started Oct 18 12:26:32 PM PDT 23
Finished Oct 18 12:27:02 PM PDT 23
Peak memory 212776 kb
Host smart-fdee0162-9321-4831-8f3c-0db1e5356237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48561381089948121818281354392108284541974266031129361449289540295338759874715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.48561381089948121818281354392108284541974266031129361449289540295338759874715
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.19522656597088331695118481034429942488699023067008147987068445069659232064248
Short name T199
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.37 seconds
Started Oct 18 12:26:38 PM PDT 23
Finished Oct 18 12:27:22 PM PDT 23
Peak memory 212920 kb
Host smart-565cf11e-a438-4ef9-b021-cd1f1c2ecaaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195226565970883316951184810344299424886990230670081479870684450
69659232064248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.19522656597088331695118481034429942488699023067008
147987068445069659232064248
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.113185874763657928477833557536870198655357001727660920813577812241260415224420
Short name T104
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Oct 18 12:24:19 PM PDT 23
Finished Oct 18 12:24:32 PM PDT 23
Peak memory 211016 kb
Host smart-d7d967ff-6566-44bf-8453-21b9060bcfaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113185874763657928477833557536870198655357001727660920813577812241260415224420 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.113185874763657928477833557536870198655357001727660920813577812241260415224420
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.63772822416624621366876597190210749496240096411759873928604209724515839723891
Short name T332
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.81 seconds
Started Oct 18 12:25:01 PM PDT 23
Finished Oct 18 12:30:45 PM PDT 23
Peak memory 237552 kb
Host smart-d12f0953-ebbf-4b35-808d-7482e8c4391c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63772822416624621366876597190210749496240096411759873928604209724515839723891 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.637728224166246213668765971902107494962400964117598739286
04209724515839723891
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.50011671590096477659821234260012670518041158876754850324469603782254178269026
Short name T285
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.66 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:37 PM PDT 23
Peak memory 211232 kb
Host smart-708054cd-2700-4030-96a5-9557eb7f43c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50011671590096477659821234260012670518041158876754850324469603782254178269026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.50011671590096477659821234260012670518041158876754850324469603782254178269026
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.111112368749506454983435619188786564547377482886988621445711761371460783354422
Short name T231
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.57 seconds
Started Oct 18 12:23:49 PM PDT 23
Finished Oct 18 12:24:03 PM PDT 23
Peak memory 211072 kb
Host smart-bdd49a84-46cc-4fd1-9739-3f3c34e3dcee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111112368749506454983435619188786564547377482886988621445711761371460783354422 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.111112368749506454983435619188786564547377482886988621445711761371460783354422
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.111637830078021061892434108634062813634816777760619562216460254386525578178414
Short name T115
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.57 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:39 PM PDT 23
Peak memory 212388 kb
Host smart-323f09f7-beb7-4e1e-89cc-37ec08093dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111637830078021061892434108634062813634816777760619562216460254386525578178414 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.rom_ctrl_smoke.111637830078021061892434108634062813634816777760619562216460254386525578178414
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.75761034536224309479563357783522848663045982015075014404942469782699021043353
Short name T144
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.75 seconds
Started Oct 18 12:26:13 PM PDT 23
Finished Oct 18 12:26:55 PM PDT 23
Peak memory 212564 kb
Host smart-a484a3c0-26f0-4e0e-a7d3-581a51c19292
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757610345362243094795633577835228486630459820150750144049424697
82699021043353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.75761034536224309479563357783522848663045982015075
014404942469782699021043353
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.18314737517694558417949049652673550801344671233490819211949748501998345750957
Short name T324
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 18 12:29:44 PM PDT 23
Finished Oct 18 12:29:57 PM PDT 23
Peak memory 210804 kb
Host smart-e4f84889-8cc0-44cb-a7a1-c35881d44272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18314737517694558417949049652673550801344671233490819211949748501998345750957 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.18314737517694558417949049652673550801344671233490819211949748501998345750957
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.10606611974129725522584919021244875037505416380636177975387033333511368390802
Short name T312
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.11 seconds
Started Oct 18 12:27:50 PM PDT 23
Finished Oct 18 12:33:31 PM PDT 23
Peak memory 237608 kb
Host smart-d9ab79ab-94e4-4be1-ae61-12df4991e01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606611974129725522584919021244875037505416380636177975387033333511368390802 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.1060661197412972552258491902124487503750541638063617797538
7033333511368390802
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.51290330307683294068991192692117101123678206395657496530205291249463347654765
Short name T103
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.07 seconds
Started Oct 18 12:27:48 PM PDT 23
Finished Oct 18 12:28:14 PM PDT 23
Peak memory 211472 kb
Host smart-5f3d6466-4910-4bff-9e65-46f76bf99304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51290330307683294068991192692117101123678206395657496530205291249463347654765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.51290330307683294068991192692117101123678206395657496530205291249463347654765
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.72304966719452654240752073500559140078983355969300169927202948290984676183493
Short name T135
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.35 seconds
Started Oct 18 12:25:15 PM PDT 23
Finished Oct 18 12:25:29 PM PDT 23
Peak memory 209592 kb
Host smart-90ed91f1-dd33-4db8-845c-61e3d892c4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72304966719452654240752073500559140078983355969300169927202948290984676183493 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.72304966719452654240752073500559140078983355969300169927202948290984676183493
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.87469955516740787572632264868179660255653978574594078847078299093093615077973
Short name T28
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.1 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:28:08 PM PDT 23
Peak memory 236916 kb
Host smart-a6703ebf-78ed-48c5-9ab9-d94a0b9671b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87469955516740787572632264868179660255653978574594078847078299093093615077973 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.87469955516740787572632264868179660255653978574594078847078299093093615077973
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.67124775080644701418758403908473651364771320760430975067125619398282355236712
Short name T117
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.9 seconds
Started Oct 18 12:26:27 PM PDT 23
Finished Oct 18 12:26:56 PM PDT 23
Peak memory 212768 kb
Host smart-500220f4-6dcb-4a85-8eb2-7beb2edabafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67124775080644701418758403908473651364771320760430975067125619398282355236712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_smoke.67124775080644701418758403908473651364771320760430975067125619398282355236712
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.18610259784827173405860390159977680134070026195546688990028814655604526825936
Short name T313
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.18 seconds
Started Oct 18 12:21:24 PM PDT 23
Finished Oct 18 12:22:08 PM PDT 23
Peak memory 212852 kb
Host smart-31fccf3b-b315-48bf-b2af-10a48c85814f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186102597848271734058603901599776801340700261955466889900288146
55604526825936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.186102597848271734058603901599776801340700261955466
88990028814655604526825936
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.89245866773761168148361454843904275048564108832729322738001542113827075721825
Short name T9
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 18 12:26:17 PM PDT 23
Finished Oct 18 12:26:29 PM PDT 23
Peak memory 210772 kb
Host smart-360339dc-5ab0-464b-b717-48c15ce22876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89245866773761168148361454843904275048564108832729322738001542113827075721825 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.89245866773761168148361454843904275048564108832729322738001542113827075721825
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.33750230800935730400096451099057793761887285819737242001651164176702469444489
Short name T133
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.02 seconds
Started Oct 18 12:25:23 PM PDT 23
Finished Oct 18 12:31:11 PM PDT 23
Peak memory 237824 kb
Host smart-dfd8f53d-0766-4c62-95b6-830c7c6a8eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750230800935730400096451099057793761887285819737242001651164176702469444489 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.337502308009357304000964510990577937618872858197372420016
51164176702469444489
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.60161711906103933143286800030068879740799737976035463457598330842447901637695
Short name T275
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.87 seconds
Started Oct 18 12:26:51 PM PDT 23
Finished Oct 18 12:27:18 PM PDT 23
Peak memory 211512 kb
Host smart-5f7599f7-a7ea-48b0-900d-f161d5dca295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60161711906103933143286800030068879740799737976035463457598330842447901637695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.rom_ctrl_kmac_err_chk.60161711906103933143286800030068879740799737976035463457598330842447901637695
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.48373310918464815557155137505625881468572400468493627131327941021917051709895
Short name T346
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.45 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 210240 kb
Host smart-8b20e2e3-e58f-42ad-8abd-ad4892973879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=48373310918464815557155137505625881468572400468493627131327941021917051709895 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.48373310918464815557155137505625881468572400468493627131327941021917051709895
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.113723033491684677703085806000798091327798444663996024998459356612872446375286
Short name T222
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.14 seconds
Started Oct 18 12:26:39 PM PDT 23
Finished Oct 18 12:27:08 PM PDT 23
Peak memory 212760 kb
Host smart-eb66f8ad-a99d-4501-b083-90f43346c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113723033491684677703085806000798091327798444663996024998459356612872446375286 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_smoke.113723033491684677703085806000798091327798444663996024998459356612872446375286
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.5766954460049267094226074066696791737381433153675987361939937315778407946452
Short name T294
Test name
Test status
Simulation time 9415977006 ps
CPU time 45.2 seconds
Started Oct 18 12:23:14 PM PDT 23
Finished Oct 18 12:24:00 PM PDT 23
Peak memory 212916 kb
Host smart-b7fb2c23-cfde-42a8-b736-c99a8a020a87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576695446004926709422607406669679173738143315367598736193993731
5778407946452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.576695446004926709422607406669679173738143315367598
7361939937315778407946452
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.47198024166090287052760071631353737283019362635582318102272554768795481618336
Short name T291
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 18 12:25:21 PM PDT 23
Finished Oct 18 12:25:34 PM PDT 23
Peak memory 211384 kb
Host smart-2298290a-961c-469d-9592-69d000d94ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47198024166090287052760071631353737283019362635582318102272554768795481618336 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.47198024166090287052760071631353737283019362635582318102272554768795481618336
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.48632510570056376780766239215444896305939032637147879589974727836705121362596
Short name T238
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.69 seconds
Started Oct 18 12:25:30 PM PDT 23
Finished Oct 18 12:31:07 PM PDT 23
Peak memory 237224 kb
Host smart-2c2e76bd-7fd6-4834-8804-6de881e6dc94
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48632510570056376780766239215444896305939032637147879589974727836705121362596 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.486325105700563767807662392154448963059390326371478795899
74727836705121362596
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.39045019724792226686632382827649816873973083418142518354863322542962135418555
Short name T184
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.04 seconds
Started Oct 18 12:26:33 PM PDT 23
Finished Oct 18 12:26:58 PM PDT 23
Peak memory 211508 kb
Host smart-b8c29244-239c-4220-bf92-3ee43ac325e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39045019724792226686632382827649816873973083418142518354863322542962135418555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.rom_ctrl_kmac_err_chk.39045019724792226686632382827649816873973083418142518354863322542962135418555
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.107875484489545727075607744919169891414167246814319792634144375598773184227833
Short name T241
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.93 seconds
Started Oct 18 12:25:34 PM PDT 23
Finished Oct 18 12:25:47 PM PDT 23
Peak memory 210840 kb
Host smart-dea1dfe7-ab85-45d3-abf7-ebaf36bff2e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107875484489545727075607744919169891414167246814319792634144375598773184227833 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.107875484489545727075607744919169891414167246814319792634144375598773184227833
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.83216754887137189147812324476228279967792456463162250905203358006854028799131
Short name T218
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.21 seconds
Started Oct 18 12:26:17 PM PDT 23
Finished Oct 18 12:26:46 PM PDT 23
Peak memory 212452 kb
Host smart-54c57568-e7ae-4494-be6e-bb19b7350916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83216754887137189147812324476228279967792456463162250905203358006854028799131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.83216754887137189147812324476228279967792456463162250905203358006854028799131
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.24294868436286598217933273315085106319279428198820995096405811776674610039077
Short name T277
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.2 seconds
Started Oct 18 12:25:48 PM PDT 23
Finished Oct 18 12:26:32 PM PDT 23
Peak memory 212836 kb
Host smart-7d47105d-ba20-4e8f-a44f-65f89598924f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242948684362865982179332733150851063192794281988209950964058117
76674610039077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.24294868436286598217933273315085106319279428198820
995096405811776674610039077
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.41619816364870433600253112147780427378856961059105717100483323440810247588473
Short name T3
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 18 12:23:38 PM PDT 23
Finished Oct 18 12:23:51 PM PDT 23
Peak memory 211096 kb
Host smart-292ac807-f03d-4345-9275-78120e09dd5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41619816364870433600253112147780427378856961059105717100483323440810247588473 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.41619816364870433600253112147780427378856961059105717100483323440810247588473
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.79899161803765064360656080976534100507535963600830706785132279449662252658085
Short name T351
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.71 seconds
Started Oct 18 12:27:28 PM PDT 23
Finished Oct 18 12:33:01 PM PDT 23
Peak memory 236456 kb
Host smart-da03d72b-90ba-42e9-a98b-8be6d75c3b9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79899161803765064360656080976534100507535963600830706785132279449662252658085 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.798991618037650643606560809765341005075359636008307067851
32279449662252658085
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.96106613505927001958135213950422658716155586329049938346453331106836646361520
Short name T325
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.81 seconds
Started Oct 18 12:27:28 PM PDT 23
Finished Oct 18 12:27:54 PM PDT 23
Peak memory 210440 kb
Host smart-4abf70e0-72fc-4235-92bb-a87dd8d5d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96106613505927001958135213950422658716155586329049938346453331106836646361520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.rom_ctrl_kmac_err_chk.96106613505927001958135213950422658716155586329049938346453331106836646361520
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.109008404845242402679155592371732183717331166594003257153099813604482863787695
Short name T267
Test name
Test status
Simulation time 3151732636 ps
CPU time 13 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:42 PM PDT 23
Peak memory 210248 kb
Host smart-b00ac7b4-d9c6-4a8d-9302-182a4ece2811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=109008404845242402679155592371732183717331166594003257153099813604482863787695 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.109008404845242402679155592371732183717331166594003257153099813604482863787695
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.88520082950129849865832129355218582334463078543273486644500092629899313806836
Short name T228
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.69 seconds
Started Oct 18 12:28:10 PM PDT 23
Finished Oct 18 12:28:38 PM PDT 23
Peak memory 212716 kb
Host smart-c12384e3-54c2-42b4-abd4-66c332d12962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88520082950129849865832129355218582334463078543273486644500092629899313806836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.88520082950129849865832129355218582334463078543273486644500092629899313806836
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.73794010856683722378855488402918759103804863656012169758721791533056502554042
Short name T268
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.89 seconds
Started Oct 18 12:28:10 PM PDT 23
Finished Oct 18 12:28:52 PM PDT 23
Peak memory 212832 kb
Host smart-058c38d2-600e-4280-a513-6bf467974b60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737940108566837223788554884029187591038048636560121697587217915
33056502554042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.73794010856683722378855488402918759103804863656012
169758721791533056502554042
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.57907843738763409071924181465894043832274118155705483558050887886402014048982
Short name T125
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Oct 18 12:25:31 PM PDT 23
Finished Oct 18 12:25:44 PM PDT 23
Peak memory 210756 kb
Host smart-9c1e4930-004c-463a-a009-5f2341520201
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57907843738763409071924181465894043832274118155705483558050887886402014048982 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.57907843738763409071924181465894043832274118155705483558050887886402014048982
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.55820032197762037108103931879044354459793050941619685828467193685533584342248
Short name T307
Test name
Test status
Simulation time 69854280986 ps
CPU time 332.61 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:33:02 PM PDT 23
Peak memory 236976 kb
Host smart-fceea2fb-a081-498c-a00a-9feeabfe6d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55820032197762037108103931879044354459793050941619685828467193685533584342248 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.558200321977620371081039318790443544597930509416196858284
67193685533584342248
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.59363403626503941899393386451243096745407848442381927226426617587572325664266
Short name T110
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.26 seconds
Started Oct 18 12:26:23 PM PDT 23
Finished Oct 18 12:26:48 PM PDT 23
Peak memory 211468 kb
Host smart-daf4a62d-7a00-4998-a9d2-1547bc04f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59363403626503941899393386451243096745407848442381927226426617587572325664266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rom_ctrl_kmac_err_chk.59363403626503941899393386451243096745407848442381927226426617587572325664266
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.73436344660075094863580118298038824053861094980031835256463969329133347709908
Short name T330
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 18 12:27:30 PM PDT 23
Finished Oct 18 12:27:44 PM PDT 23
Peak memory 211072 kb
Host smart-3d4dccd4-45b1-4c71-9358-bd11d2cc00b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73436344660075094863580118298038824053861094980031835256463969329133347709908 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.73436344660075094863580118298038824053861094980031835256463969329133347709908
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.54403672524637218221195036233522065538361114010126845242571965587382580060912
Short name T246
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.54 seconds
Started Oct 18 12:27:13 PM PDT 23
Finished Oct 18 12:27:43 PM PDT 23
Peak memory 211912 kb
Host smart-542af28e-f0d5-4337-8b8b-6a7891e8550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54403672524637218221195036233522065538361114010126845242571965587382580060912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.rom_ctrl_smoke.54403672524637218221195036233522065538361114010126845242571965587382580060912
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.50789008036857107861016066567920386400161469686681489923595524158518684231298
Short name T141
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.48 seconds
Started Oct 18 12:26:13 PM PDT 23
Finished Oct 18 12:26:55 PM PDT 23
Peak memory 212224 kb
Host smart-95e52a7c-1ba5-41de-aa26-c4a4a8bb79cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507890080368571078610160665679203864001614696866814899235955241
58518684231298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.50789008036857107861016066567920386400161469686681
489923595524158518684231298
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4113521176812662862027639268354828859729733480778093332199385522908840550413
Short name T128
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 18 12:25:30 PM PDT 23
Finished Oct 18 12:25:42 PM PDT 23
Peak memory 211040 kb
Host smart-1049b699-c3ee-4b24-93d8-4bf90b83b8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113521176812662862027639268354828859729733480778093332199385522908840550413 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4113521176812662862027639268354828859729733480778093332199385522908840550413
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.78661556208792549032817346307770646159546341831122108710096114750942393354524
Short name T348
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.45 seconds
Started Oct 18 12:26:37 PM PDT 23
Finished Oct 18 12:32:14 PM PDT 23
Peak memory 237568 kb
Host smart-6f554086-225c-48cf-a04d-c0b2c6dd751d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78661556208792549032817346307770646159546341831122108710096114750942393354524 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.786615562087925490328173463077706461595463418311221087100
96114750942393354524
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.85186104649973695572238524206737008484704188523313094948861597590009130437208
Short name T162
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.86 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:32 PM PDT 23
Peak memory 211400 kb
Host smart-f577ac3a-dd03-4a07-bd9b-6dc1269f6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85186104649973695572238524206737008484704188523313094948861597590009130437208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rom_ctrl_kmac_err_chk.85186104649973695572238524206737008484704188523313094948861597590009130437208
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.15650292217963511670260499652002409171618790109533927637545725186498042427965
Short name T236
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.74 seconds
Started Oct 18 12:24:06 PM PDT 23
Finished Oct 18 12:24:20 PM PDT 23
Peak memory 211096 kb
Host smart-612fba90-ecf2-4d42-9c67-f6dd607e79ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15650292217963511670260499652002409171618790109533927637545725186498042427965 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.15650292217963511670260499652002409171618790109533927637545725186498042427965
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.5575775878702876240627321491456890263317901487726029331408307708841639696785
Short name T147
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.15 seconds
Started Oct 18 12:25:29 PM PDT 23
Finished Oct 18 12:25:57 PM PDT 23
Peak memory 211912 kb
Host smart-d7dd3bd8-32c6-4dba-ac32-b6221ab138aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5575775878702876240627321491456890263317901487726029331408307708841639696785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.rom_ctrl_smoke.5575775878702876240627321491456890263317901487726029331408307708841639696785
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.26033291832423511931202410810935760130378159782595089327017569988288213103813
Short name T252
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.26 seconds
Started Oct 18 12:24:07 PM PDT 23
Finished Oct 18 12:24:52 PM PDT 23
Peak memory 212852 kb
Host smart-53d16b4d-4e1c-4a9b-921b-1d26ed732795
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260332918324235119312024108109357601303781597825950893270175699
88288213103813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.26033291832423511931202410810935760130378159782595
089327017569988288213103813
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.57706558489089530680196296296024007391840613174281818243322882817592305500724
Short name T239
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 18 12:25:27 PM PDT 23
Finished Oct 18 12:25:40 PM PDT 23
Peak memory 211040 kb
Host smart-a065b5bb-9714-4c1b-81e5-584e0454212b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57706558489089530680196296296024007391840613174281818243322882817592305500724 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.57706558489089530680196296296024007391840613174281818243322882817592305500724
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.115258865824919728021387830141946096690863186393505514228524768465318147874704
Short name T338
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.59 seconds
Started Oct 18 12:25:51 PM PDT 23
Finished Oct 18 12:31:29 PM PDT 23
Peak memory 236792 kb
Host smart-5d95d840-ef86-4543-bd19-b832f35c6ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115258865824919728021387830141946096690863186393505514228524768465318147874704 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.11525886582491972802138783014194609669086318639350551422
8524768465318147874704
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.96933936972597098239175456672191582524062918013655002603287297528351396798105
Short name T38
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.34 seconds
Started Oct 18 12:25:29 PM PDT 23
Finished Oct 18 12:25:55 PM PDT 23
Peak memory 211468 kb
Host smart-989336aa-c1e7-4965-8843-bea821c701e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96933936972597098239175456672191582524062918013655002603287297528351396798105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rom_ctrl_kmac_err_chk.96933936972597098239175456672191582524062918013655002603287297528351396798105
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.46052458639237884331556330878027649046372105795203314218593380028052580517045
Short name T255
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.04 seconds
Started Oct 18 12:25:54 PM PDT 23
Finished Oct 18 12:26:07 PM PDT 23
Peak memory 210840 kb
Host smart-9fe6dfaf-4152-4f5a-a7b6-4347735a68f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46052458639237884331556330878027649046372105795203314218593380028052580517045 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.46052458639237884331556330878027649046372105795203314218593380028052580517045
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.87062088548957129756262080209257031934643573736338155791910332503571398514510
Short name T130
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.45 seconds
Started Oct 18 12:23:36 PM PDT 23
Finished Oct 18 12:24:06 PM PDT 23
Peak memory 212736 kb
Host smart-5d843935-08d8-4925-a932-5e38cf7c3b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87062088548957129756262080209257031934643573736338155791910332503571398514510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_smoke.87062088548957129756262080209257031934643573736338155791910332503571398514510
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.26321127537154970247042381691610083610216408224969199313981700211920497205654
Short name T177
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.23 seconds
Started Oct 18 12:25:53 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 212548 kb
Host smart-51d3ef73-f5dd-4277-b0a8-2d62a06f15ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263211275371549702470423816916100836102164082249691993139817002
11920497205654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.26321127537154970247042381691610083610216408224969
199313981700211920497205654
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.10234655403371304996927804706590158599830315663692778544458800171209727190011
Short name T234
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 18 12:26:04 PM PDT 23
Finished Oct 18 12:26:16 PM PDT 23
Peak memory 210816 kb
Host smart-3d51393b-19b9-44f6-bb52-60c2d954be63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234655403371304996927804706590158599830315663692778544458800171209727190011 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.10234655403371304996927804706590158599830315663692778544458800171209727190011
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.5312579142839607128324289390536479217657611589207128965189630341768362910705
Short name T14
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.78 seconds
Started Oct 18 12:27:20 PM PDT 23
Finished Oct 18 12:32:57 PM PDT 23
Peak memory 237132 kb
Host smart-ca912490-42de-4d3e-bd61-59751815191f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5312579142839607128324289390536479217657611589207128965189630341768362910705 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.5312579142839607128324289390536479217657611589207128965189
630341768362910705
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.85167374665956235473370172224976899160183030587572584223279466763405427137783
Short name T235
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.55 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:32 PM PDT 23
Peak memory 210200 kb
Host smart-7a7c3c48-f4a2-4215-b50a-98983f4c3fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85167374665956235473370172224976899160183030587572584223279466763405427137783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rom_ctrl_kmac_err_chk.85167374665956235473370172224976899160183030587572584223279466763405427137783
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.33215469199478692467966090719501214924010638328079780378982255648083422219815
Short name T276
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.32 seconds
Started Oct 18 12:25:59 PM PDT 23
Finished Oct 18 12:26:13 PM PDT 23
Peak memory 210280 kb
Host smart-9910462b-eac9-44fa-8fc0-cc70c4449bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33215469199478692467966090719501214924010638328079780378982255648083422219815 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.33215469199478692467966090719501214924010638328079780378982255648083422219815
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.16033945078629318775334446484273244938567677436756592720822109806510377357212
Short name T13
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.14 seconds
Started Oct 18 12:25:29 PM PDT 23
Finished Oct 18 12:25:58 PM PDT 23
Peak memory 212572 kb
Host smart-5e23eff4-3c77-4367-877c-acf328b616ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16033945078629318775334446484273244938567677436756592720822109806510377357212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_smoke.16033945078629318775334446484273244938567677436756592720822109806510377357212
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.14797338535965061558301178715856028647966870348464551917764460094681611598121
Short name T247
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.14 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:26:45 PM PDT 23
Peak memory 212560 kb
Host smart-ccff0a40-a019-4abe-b11d-df77d15ad55d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147973385359650615583011787158560286479668703484645519177644600
94681611598121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.14797338535965061558301178715856028647966870348464
551917764460094681611598121
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.110118168673819274462373008706260461329637721926185783412635433520013127385024
Short name T335
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 18 12:27:38 PM PDT 23
Finished Oct 18 12:27:51 PM PDT 23
Peak memory 211060 kb
Host smart-df5e2f53-c940-4a76-9951-33170ed7c497
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110118168673819274462373008706260461329637721926185783412635433520013127385024 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.110118168673819274462373008706260461329637721926185783412635433520013127385024
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.36641099575646819832645365005029473634882662329243884816615012329728109437137
Short name T286
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.57 seconds
Started Oct 18 12:24:24 PM PDT 23
Finished Oct 18 12:30:12 PM PDT 23
Peak memory 237740 kb
Host smart-eb691539-a59f-4adb-af2e-2f84defff912
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36641099575646819832645365005029473634882662329243884816615012329728109437137 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.366410995756468198326453650050294736348826623292438848166
15012329728109437137
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.108489435923830168189260144169840639217303927094555234640268579931218090098110
Short name T219
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.3 seconds
Started Oct 18 12:27:54 PM PDT 23
Finished Oct 18 12:28:20 PM PDT 23
Peak memory 211480 kb
Host smart-392ab11d-d007-4d16-85c7-eb553972d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108489435923830168189260144169840639217303927094555234640268579931218090098110 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.rom_ctrl_kmac_err_chk.108489435923830168189260144169840639217303927094555234640268579931218090098110
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.19827191617239379104202219990350399126442405291117289013365323982939046189895
Short name T195
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:20 PM PDT 23
Peak memory 210844 kb
Host smart-6de4f42e-a1d7-482b-8652-9aa5c0f691a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19827191617239379104202219990350399126442405291117289013365323982939046189895 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.19827191617239379104202219990350399126442405291117289013365323982939046189895
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.83748862736120490553727817320205496206534963146321760813349408047954120851913
Short name T270
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.02 seconds
Started Oct 18 12:28:28 PM PDT 23
Finished Oct 18 12:28:56 PM PDT 23
Peak memory 212812 kb
Host smart-489fa08b-6e9c-4dc8-a1c3-6fda643fafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83748862736120490553727817320205496206534963146321760813349408047954120851913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.83748862736120490553727817320205496206534963146321760813349408047954120851913
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.114059998610625239547503431767977442485142988829380408497286156950330495962268
Short name T167
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.35 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:49 PM PDT 23
Peak memory 211564 kb
Host smart-91a3b14a-5eb0-4ec4-ac91-3e1ca7ab867e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114059998610625239547503431767977442485142988829380408497286156
950330495962268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.1140599986106252395475034317679774424851429888293
80408497286156950330495962268
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.32666579411059531629684671964075802590018503959929287950419111962042519117122
Short name T283
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 18 12:27:54 PM PDT 23
Finished Oct 18 12:28:07 PM PDT 23
Peak memory 211072 kb
Host smart-b430db83-f123-4a76-9899-1bbdb926df8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32666579411059531629684671964075802590018503959929287950419111962042519117122 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.32666579411059531629684671964075802590018503959929287950419111962042519117122
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.42496592830055986793136236277777349061771659498603404235842158747840874061916
Short name T11
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.09 seconds
Started Oct 18 12:26:02 PM PDT 23
Finished Oct 18 12:31:37 PM PDT 23
Peak memory 237308 kb
Host smart-82dd2aa9-8d76-4622-a7fe-6b70e92a0202
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42496592830055986793136236277777349061771659498603404235842158747840874061916 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.424965928300559867931362362777773490617716594986034042358
42158747840874061916
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.34969562667428351645319081292733279797278241573054163336989233281947607887373
Short name T186
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Oct 18 12:27:32 PM PDT 23
Finished Oct 18 12:27:58 PM PDT 23
Peak memory 211496 kb
Host smart-30519ba3-4c3d-4048-8a4d-1fd9b38b09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34969562667428351645319081292733279797278241573054163336989233281947607887373 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rom_ctrl_kmac_err_chk.34969562667428351645319081292733279797278241573054163336989233281947607887373
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.88958154548028728766244080455231406446427592596760697456982278505565409983302
Short name T36
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 18 12:26:07 PM PDT 23
Finished Oct 18 12:26:21 PM PDT 23
Peak memory 210808 kb
Host smart-34c231e6-8903-434d-a910-4edf12db22ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88958154548028728766244080455231406446427592596760697456982278505565409983302 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.88958154548028728766244080455231406446427592596760697456982278505565409983302
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.28709022678815705583380739160988730089640430703239345751329967805852865054722
Short name T293
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.76 seconds
Started Oct 18 12:26:49 PM PDT 23
Finished Oct 18 12:27:17 PM PDT 23
Peak memory 212444 kb
Host smart-ded156bf-7786-4c33-80ad-35f8e943933a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28709022678815705583380739160988730089640430703239345751329967805852865054722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.28709022678815705583380739160988730089640430703239345751329967805852865054722
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.38540340665364921978332611748820842329833998955613534371754398985638736182303
Short name T266
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.23 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:51 PM PDT 23
Peak memory 212580 kb
Host smart-8a510d71-7ab4-4273-b18f-9e3daa8d68a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385403406653649219783326117488208423298339989556135343717543989
85638736182303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.38540340665364921978332611748820842329833998955613
534371754398985638736182303
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.45717528879084625002780854269722017365481018737129088584913970347118539631190
Short name T97
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.74 seconds
Started Oct 18 12:24:05 PM PDT 23
Finished Oct 18 12:24:19 PM PDT 23
Peak memory 211084 kb
Host smart-1e03fa7b-0b67-4c26-86cb-73d8ed1efb4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45717528879084625002780854269722017365481018737129088584913970347118539631190 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.45717528879084625002780854269722017365481018737129088584913970347118539631190
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.92285190260186966746282419900537443812964117870245348051590520680356533118844
Short name T310
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.55 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:31:50 PM PDT 23
Peak memory 236664 kb
Host smart-22cb8e0f-0711-4e42-ad36-9efa20b7ca73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92285190260186966746282419900537443812964117870245348051590520680356533118844 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.922851902601869667462824199005374438129641178702453480515
90520680356533118844
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.39216764590472406933660798803637514601566244570648453296741510502206237686896
Short name T321
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:26:38 PM PDT 23
Peak memory 210292 kb
Host smart-07862e2e-7cda-4048-9c67-bf4941291943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39216764590472406933660798803637514601566244570648453296741510502206237686896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rom_ctrl_kmac_err_chk.39216764590472406933660798803637514601566244570648453296741510502206237686896
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.19690247002594655042735198460370594303033378555786669877862248166720718484663
Short name T341
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.05 seconds
Started Oct 18 12:26:37 PM PDT 23
Finished Oct 18 12:26:51 PM PDT 23
Peak memory 210992 kb
Host smart-e0935cc0-6456-4036-994c-5204e399c475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19690247002594655042735198460370594303033378555786669877862248166720718484663 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.19690247002594655042735198460370594303033378555786669877862248166720718484663
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.5569294610475974068419797781156839341059331497972695320078216108468063336185
Short name T165
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.91 seconds
Started Oct 18 12:28:32 PM PDT 23
Finished Oct 18 12:29:01 PM PDT 23
Peak memory 212812 kb
Host smart-97d9f069-416e-4ce9-9593-73719b107ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5569294610475974068419797781156839341059331497972695320078216108468063336185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.rom_ctrl_smoke.5569294610475974068419797781156839341059331497972695320078216108468063336185
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.63276533902910149318829273679182141092826552732155470616609771259490412972385
Short name T298
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.08 seconds
Started Oct 18 12:28:06 PM PDT 23
Finished Oct 18 12:28:49 PM PDT 23
Peak memory 212832 kb
Host smart-228fcc74-af2c-4303-af31-fcd419c55a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632765339029101493188292736791821410928265527321554706166097712
59490412972385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.63276533902910149318829273679182141092826552732155
470616609771259490412972385
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.95640096891867795643333122982412976115036913321087984754448445539857164677656
Short name T245
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.96 seconds
Started Oct 18 12:27:37 PM PDT 23
Finished Oct 18 12:27:49 PM PDT 23
Peak memory 211136 kb
Host smart-bccae525-2fd8-4581-991d-50e2c7ecba6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95640096891867795643333122982412976115036913321087984754448445539857164677656 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.95640096891867795643333122982412976115036913321087984754448445539857164677656
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.56395193430905094460484157795345047946361492644470538520276418216012280243853
Short name T187
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.21 seconds
Started Oct 18 12:26:46 PM PDT 23
Finished Oct 18 12:32:21 PM PDT 23
Peak memory 237612 kb
Host smart-da0afb5d-32e9-40f7-a72c-419852ab3bbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56395193430905094460484157795345047946361492644470538520276418216012280243853 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.5639519343090509446048415779534504794636149264447053852027
6418216012280243853
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.108092156442040483083361980452163983749532687713103010832981287828545560374942
Short name T134
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.87 seconds
Started Oct 18 12:30:05 PM PDT 23
Finished Oct 18 12:30:30 PM PDT 23
Peak memory 211500 kb
Host smart-a0a0ca53-0b24-4a53-a299-e9b4524cc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108092156442040483083361980452163983749532687713103010832981287828545560374942 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.rom_ctrl_kmac_err_chk.108092156442040483083361980452163983749532687713103010832981287828545560374942
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3465617638215230385045361561111198689598343723745682947344609472641746706354
Short name T39
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.58 seconds
Started Oct 18 12:26:13 PM PDT 23
Finished Oct 18 12:26:27 PM PDT 23
Peak memory 211120 kb
Host smart-aeed1dcf-14d4-4178-bea3-bb2dcba3ed05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465617638215230385045361561111198689598343723745682947344609472641746706354 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3465617638215230385045361561111198689598343723745682947344609472641746706354
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.33146722127117040026174522249312357617892031060565714253622971378799997941371
Short name T32
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.67 seconds
Started Oct 18 12:26:49 PM PDT 23
Finished Oct 18 12:28:47 PM PDT 23
Peak memory 236620 kb
Host smart-35e87d26-31a4-4cec-bcb6-a574e3a6b73f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146722127117040026174522249312357617892031060565714253622971378799997941371 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.33146722127117040026174522249312357617892031060565714253622971378799997941371
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.99037438243306506265123289041347679205799037351407469091590526725707838462504
Short name T340
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.58 seconds
Started Oct 18 12:28:19 PM PDT 23
Finished Oct 18 12:28:47 PM PDT 23
Peak memory 212720 kb
Host smart-73f0b873-3d85-48f9-9f53-6378de82878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99037438243306506265123289041347679205799037351407469091590526725707838462504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.rom_ctrl_smoke.99037438243306506265123289041347679205799037351407469091590526725707838462504
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.4919724796242793446607653866639163186811881241838556266311002915607146758671
Short name T207
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.93 seconds
Started Oct 18 12:26:49 PM PDT 23
Finished Oct 18 12:27:31 PM PDT 23
Peak memory 212792 kb
Host smart-57e8a1a7-3248-420c-b3a5-a7ec3cec2169
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491972479624279344660765386663916318681188124183855626631100291
5607146758671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.4919724796242793446607653866639163186811881241838556
266311002915607146758671
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.63002455573009043408328079857673113771631385937735999816938396104427610737462
Short name T301
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.5 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:26:18 PM PDT 23
Peak memory 210808 kb
Host smart-570475c9-3cca-43c2-86b7-2384b2660dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63002455573009043408328079857673113771631385937735999816938396104427610737462 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.63002455573009043408328079857673113771631385937735999816938396104427610737462
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.100771431102907751424257502009679423183675043462773078805643341089674588057273
Short name T353
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.85 seconds
Started Oct 18 12:27:19 PM PDT 23
Finished Oct 18 12:33:02 PM PDT 23
Peak memory 237568 kb
Host smart-620fda37-8f44-403c-8353-5c50af960931
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100771431102907751424257502009679423183675043462773078805643341089674588057273 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.10077143110290775142425750200967942318367504346277307880
5643341089674588057273
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.75054153642774149372171697981721368668083376965346911002541830384509947681104
Short name T192
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.94 seconds
Started Oct 18 12:25:44 PM PDT 23
Finished Oct 18 12:26:12 PM PDT 23
Peak memory 211508 kb
Host smart-a4c7cba9-029f-4c9c-bd6c-5dde57d42509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75054153642774149372171697981721368668083376965346911002541830384509947681104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rom_ctrl_kmac_err_chk.75054153642774149372171697981721368668083376965346911002541830384509947681104
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.31365230726773712402797137857906192647319662459107582411749241948054077458688
Short name T114
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.42 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 209972 kb
Host smart-5d34b7c3-0d5a-40ae-af1b-25403aceb983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31365230726773712402797137857906192647319662459107582411749241948054077458688 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.31365230726773712402797137857906192647319662459107582411749241948054077458688
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.76152114326772274780367563731896812637002928917812108696242077429220806711033
Short name T158
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.92 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:50 PM PDT 23
Peak memory 211312 kb
Host smart-604493b5-1bed-414a-94f2-6a98ac8b5e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76152114326772274780367563731896812637002928917812108696242077429220806711033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_smoke.76152114326772274780367563731896812637002928917812108696242077429220806711033
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.55638746558377344699854295334072267241911502405242844046431051875807242270982
Short name T265
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.76 seconds
Started Oct 18 12:24:05 PM PDT 23
Finished Oct 18 12:24:50 PM PDT 23
Peak memory 212848 kb
Host smart-9015c3ba-49c4-417c-acde-cedf7a39dd27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556387465583773446998542953340722672419115024052428440464310518
75807242270982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.55638746558377344699854295334072267241911502405242
844046431051875807242270982
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.33957994844824963605412767673514532773929780108563012022896324020650094881637
Short name T215
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 18 12:26:16 PM PDT 23
Finished Oct 18 12:26:28 PM PDT 23
Peak memory 210824 kb
Host smart-3d154a55-a880-44b0-a0f4-a64d38b9bc2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957994844824963605412767673514532773929780108563012022896324020650094881637 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.33957994844824963605412767673514532773929780108563012022896324020650094881637
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.108337452491819519237407797680174959242182730083705324377936950355879997765811
Short name T203
Test name
Test status
Simulation time 69854280986 ps
CPU time 330.13 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:31:42 PM PDT 23
Peak memory 237348 kb
Host smart-abfcf8e0-c5a4-4356-b66c-ca0d414021cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108337452491819519237407797680174959242182730083705324377936950355879997765811 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.10833745249181951923740779768017495924218273008370532437
7936950355879997765811
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.60083250495535932095897087315578804527616469415991402253197596944162560864324
Short name T8
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.71 seconds
Started Oct 18 12:27:32 PM PDT 23
Finished Oct 18 12:27:57 PM PDT 23
Peak memory 211264 kb
Host smart-e7fe4cab-9003-49e1-9676-67c3d42b521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60083250495535932095897087315578804527616469415991402253197596944162560864324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.rom_ctrl_kmac_err_chk.60083250495535932095897087315578804527616469415991402253197596944162560864324
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.18647276430820176147852795177245701722814421631864932971041356193752682704875
Short name T342
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.88 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:42 PM PDT 23
Peak memory 210756 kb
Host smart-32151c28-e069-4897-99ab-7577886ccfb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18647276430820176147852795177245701722814421631864932971041356193752682704875 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.18647276430820176147852795177245701722814421631864932971041356193752682704875
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.1402182105054034830513172821701709786224279998442798895001809070246587103528
Short name T74
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.24 seconds
Started Oct 18 12:26:14 PM PDT 23
Finished Oct 18 12:26:42 PM PDT 23
Peak memory 212464 kb
Host smart-a939ee30-c7f8-4154-912c-12bfef818a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402182105054034830513172821701709786224279998442798895001809070246587103528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.rom_ctrl_smoke.1402182105054034830513172821701709786224279998442798895001809070246587103528
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.45047391510957282467794202423606547355621654411110807642031086465149999711799
Short name T309
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.61 seconds
Started Oct 18 12:27:28 PM PDT 23
Finished Oct 18 12:28:10 PM PDT 23
Peak memory 212320 kb
Host smart-349fe3f6-7bf7-4327-8708-f5e8d4638160
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450473915109572824677942024236065473556216544111108076420310864
65149999711799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.45047391510957282467794202423606547355621654411110
807642031086465149999711799
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.42252267947956178174906116830648991934048527225207374339887420590667804928106
Short name T106
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.11 seconds
Started Oct 18 12:28:14 PM PDT 23
Finished Oct 18 12:28:27 PM PDT 23
Peak memory 211052 kb
Host smart-b161458b-2528-403f-b70e-df97d2bb79ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42252267947956178174906116830648991934048527225207374339887420590667804928106 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.42252267947956178174906116830648991934048527225207374339887420590667804928106
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.69753331940148627569118180114005801656113629416221165638980497761281925636499
Short name T300
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.28 seconds
Started Oct 18 12:28:13 PM PDT 23
Finished Oct 18 12:33:55 PM PDT 23
Peak memory 237556 kb
Host smart-c28ab1a7-5d8d-417e-a3aa-f83b2a3ae7d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69753331940148627569118180114005801656113629416221165638980497761281925636499 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.697533319401486275691181801140058016561136294162211656389
80497761281925636499
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.21878214469087694652958796590774874088298291636656342893252075325601794052277
Short name T233
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.12 seconds
Started Oct 18 12:27:46 PM PDT 23
Finished Oct 18 12:28:11 PM PDT 23
Peak memory 211512 kb
Host smart-26d96346-912c-45b0-9da4-452703be2986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21878214469087694652958796590774874088298291636656342893252075325601794052277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.rom_ctrl_kmac_err_chk.21878214469087694652958796590774874088298291636656342893252075325601794052277
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.81506398985075469380583656417593544788915204639460320375702340511526977763668
Short name T145
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.96 seconds
Started Oct 18 12:27:19 PM PDT 23
Finished Oct 18 12:27:35 PM PDT 23
Peak memory 210252 kb
Host smart-6d4f9ddf-7b3d-4836-9d16-6dc23ece7437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81506398985075469380583656417593544788915204639460320375702340511526977763668 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.81506398985075469380583656417593544788915204639460320375702340511526977763668
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.69799311987629528354936581983988860383478894095655070639685069088848758600513
Short name T356
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.42 seconds
Started Oct 18 12:24:49 PM PDT 23
Finished Oct 18 12:25:17 PM PDT 23
Peak memory 212752 kb
Host smart-a84c3a79-7e71-4313-b0f4-8f0546041e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69799311987629528354936581983988860383478894095655070639685069088848758600513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.rom_ctrl_smoke.69799311987629528354936581983988860383478894095655070639685069088848758600513
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.353622376119774892268130468963472868601585478841460744859702283936355776571
Short name T221
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.3 seconds
Started Oct 18 12:26:44 PM PDT 23
Finished Oct 18 12:27:27 PM PDT 23
Peak memory 212544 kb
Host smart-729870ff-f07a-47ff-a972-989c79a2d3e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353622376119774892268130468963472868601585478841460744859702283
936355776571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.3536223761197748922681304689634728686015854788414607
44859702283936355776571
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.6858598967620650020729740002553099458181643725714336783190022453486662320000
Short name T337
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.88 seconds
Started Oct 18 12:26:44 PM PDT 23
Finished Oct 18 12:26:56 PM PDT 23
Peak memory 210768 kb
Host smart-8b52c5f0-f69b-4f31-8a83-0fa264772887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6858598967620650020729740002553099458181643725714336783190022453486662320000 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.6858598967620650020729740002553099458181643725714336783190022453486662320000
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.95856176000739991117180341990123451940278680766820628085757636274642552241448
Short name T136
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.54 seconds
Started Oct 18 12:27:47 PM PDT 23
Finished Oct 18 12:33:29 PM PDT 23
Peak memory 237580 kb
Host smart-d09d80c4-5e02-4d0b-a94b-7017a1b03091
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95856176000739991117180341990123451940278680766820628085757636274642552241448 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.958561760007399911171803419901234519402786807668206280857
57636274642552241448
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.59870795311210281262186280460582285901335190382181731560410794101064718207074
Short name T216
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.25 seconds
Started Oct 18 12:26:06 PM PDT 23
Finished Oct 18 12:26:32 PM PDT 23
Peak memory 211160 kb
Host smart-4b229e74-3861-4de9-aca0-2b33f06e314b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59870795311210281262186280460582285901335190382181731560410794101064718207074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.59870795311210281262186280460582285901335190382181731560410794101064718207074
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.38281554543325166162283622620359808421543675589694644522051928456577479202171
Short name T280
Test name
Test status
Simulation time 3151732636 ps
CPU time 13 seconds
Started Oct 18 12:28:17 PM PDT 23
Finished Oct 18 12:28:31 PM PDT 23
Peak memory 211068 kb
Host smart-09e8854d-4770-45f6-8686-8a7e57cad506
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38281554543325166162283622620359808421543675589694644522051928456577479202171 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.38281554543325166162283622620359808421543675589694644522051928456577479202171
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.101450844541941293608992928571687084757627069104546718219052146676842890772410
Short name T217
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.66 seconds
Started Oct 18 12:27:37 PM PDT 23
Finished Oct 18 12:28:07 PM PDT 23
Peak memory 212732 kb
Host smart-e70a0d04-3b7d-4c7f-b307-3d9750742e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101450844541941293608992928571687084757627069104546718219052146676842890772410 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_smoke.101450844541941293608992928571687084757627069104546718219052146676842890772410
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.85222937834983188807951440920201799807396665871715320249672345616282208932057
Short name T198
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.95 seconds
Started Oct 18 12:26:22 PM PDT 23
Finished Oct 18 12:27:04 PM PDT 23
Peak memory 212320 kb
Host smart-7a6dd1cb-6e59-4cf0-93c9-15dd20ab9f78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852229378349831888079514409202017998073966658717153202496723456
16282208932057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.85222937834983188807951440920201799807396665871715
320249672345616282208932057
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.30162075760855233296155846035667327223164519075685253129518661797166043375157
Short name T287
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.37 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:34 PM PDT 23
Peak memory 209512 kb
Host smart-ccbdf379-74ea-4006-a564-fb502ebdf743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162075760855233296155846035667327223164519075685253129518661797166043375157 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.30162075760855233296155846035667327223164519075685253129518661797166043375157
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.13428426721421236700021047121302892900096271177374681634322410346040411355583
Short name T212
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.65 seconds
Started Oct 18 12:27:13 PM PDT 23
Finished Oct 18 12:32:48 PM PDT 23
Peak memory 237500 kb
Host smart-09f77c22-c5aa-45b2-8dc7-48beb7539694
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13428426721421236700021047121302892900096271177374681634322410346040411355583 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.134284267214212367000210471213028929000962711773746816343
22410346040411355583
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.92681213613207968933144246256222743311518551041290330176747935925333171346340
Short name T226
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.32 seconds
Started Oct 18 12:25:06 PM PDT 23
Finished Oct 18 12:25:33 PM PDT 23
Peak memory 211596 kb
Host smart-88a6b563-9aec-40b4-89fe-93eee16f01ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92681213613207968933144246256222743311518551041290330176747935925333171346340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rom_ctrl_kmac_err_chk.92681213613207968933144246256222743311518551041290330176747935925333171346340
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.19396482430214209379293786172990496157320619144171135250220534413041295260453
Short name T131
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Oct 18 12:28:07 PM PDT 23
Finished Oct 18 12:28:22 PM PDT 23
Peak memory 211172 kb
Host smart-c19a04fd-8376-4988-9da4-9d4f2f9938d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19396482430214209379293786172990496157320619144171135250220534413041295260453 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.19396482430214209379293786172990496157320619144171135250220534413041295260453
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.59308669398023017633519044147806215766362940333932548451556331126868734183986
Short name T274
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.6 seconds
Started Oct 18 12:26:41 PM PDT 23
Finished Oct 18 12:27:10 PM PDT 23
Peak memory 211896 kb
Host smart-2b0497aa-4767-41ae-8c41-9fca7c170490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59308669398023017633519044147806215766362940333932548451556331126868734183986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.rom_ctrl_smoke.59308669398023017633519044147806215766362940333932548451556331126868734183986
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.48066966681994272009675888474553148356471319302120980875663765035478945856304
Short name T210
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.7 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:28:11 PM PDT 23
Peak memory 212400 kb
Host smart-db1d8e2f-eb73-479b-a463-20199b30f8ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480669666819942720096758884745531483564713193021209808756637650
35478945856304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.48066966681994272009675888474553148356471319302120
980875663765035478945856304
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2128214018064406381025790822011609197255864703210408454248901570322322281047
Short name T191
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.96 seconds
Started Oct 18 12:27:31 PM PDT 23
Finished Oct 18 12:27:43 PM PDT 23
Peak memory 211068 kb
Host smart-65638941-794c-449b-a866-88fdba9d35c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128214018064406381025790822011609197255864703210408454248901570322322281047 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2128214018064406381025790822011609197255864703210408454248901570322322281047
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.48728131740374095207863089062748850812546733793826884499408379518297360947674
Short name T202
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.38 seconds
Started Oct 18 12:26:37 PM PDT 23
Finished Oct 18 12:32:08 PM PDT 23
Peak memory 237280 kb
Host smart-a0a6e4bf-8649-4b19-9412-ec7f455d6080
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48728131740374095207863089062748850812546733793826884499408379518297360947674 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.487281317403740952078630890627488508125467337938268844994
08379518297360947674
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.112259565565391186382775758245735511961342026685784126832550010539600290628912
Short name T100
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.13 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 211504 kb
Host smart-f326e892-439e-48d9-b765-c3adfc2b6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112259565565391186382775758245735511961342026685784126832550010539600290628912 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.rom_ctrl_kmac_err_chk.112259565565391186382775758245735511961342026685784126832550010539600290628912
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.14890716829183135784795017584532988384779123578626000298983117765889258227001
Short name T242
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.97 seconds
Started Oct 18 12:27:13 PM PDT 23
Finished Oct 18 12:27:26 PM PDT 23
Peak memory 211084 kb
Host smart-83b1fbb8-8809-4c10-ad7f-bca641e3e092
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14890716829183135784795017584532988384779123578626000298983117765889258227001 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.14890716829183135784795017584532988384779123578626000298983117765889258227001
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.95538875392790639094322516289945769496594786543130501827743828000559750020439
Short name T350
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 18 12:26:14 PM PDT 23
Finished Oct 18 12:26:43 PM PDT 23
Peak memory 212404 kb
Host smart-dbd4bb86-fcf0-404d-8301-a96c9e990db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95538875392790639094322516289945769496594786543130501827743828000559750020439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.95538875392790639094322516289945769496594786543130501827743828000559750020439
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.100623969510999674344512557021347740772706088207381263997368840875073904627327
Short name T193
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.42 seconds
Started Oct 18 12:27:26 PM PDT 23
Finished Oct 18 12:28:09 PM PDT 23
Peak memory 212840 kb
Host smart-a0faef61-86c6-4fb9-afa9-f35fd0daebc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100623969510999674344512557021347740772706088207381263997368840
875073904627327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.1006239695109996743445125570213477407727060882073
81263997368840875073904627327
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.52047752663387721506191691204186107741210298112215073952842161628497415348895
Short name T257
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Oct 18 12:24:57 PM PDT 23
Finished Oct 18 12:25:10 PM PDT 23
Peak memory 211064 kb
Host smart-591f054e-95b0-470f-b0f2-e591f6aae3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52047752663387721506191691204186107741210298112215073952842161628497415348895 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.52047752663387721506191691204186107741210298112215073952842161628497415348895
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.15543864281235750257131551475388167883255877008403115643294658097787422706504
Short name T317
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.88 seconds
Started Oct 18 12:27:32 PM PDT 23
Finished Oct 18 12:33:13 PM PDT 23
Peak memory 237596 kb
Host smart-26487e7a-57fd-40a0-928a-2075c75a314c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15543864281235750257131551475388167883255877008403115643294658097787422706504 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.155438642812357502571315514753881678832558770084031156432
94658097787422706504
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.47001371200429504667049149029407149857825162885426948970737836314457582520691
Short name T262
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.32 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 211512 kb
Host smart-7d677a13-e9e3-46fe-971d-5217532d1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47001371200429504667049149029407149857825162885426948970737836314457582520691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rom_ctrl_kmac_err_chk.47001371200429504667049149029407149857825162885426948970737836314457582520691
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.30349554012404383888732453615758866329510084020691651658089142357853055545573
Short name T232
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Oct 18 12:26:13 PM PDT 23
Finished Oct 18 12:26:27 PM PDT 23
Peak memory 211120 kb
Host smart-c682d709-5c37-4d6e-860c-a8216b92601e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30349554012404383888732453615758866329510084020691651658089142357853055545573 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.30349554012404383888732453615758866329510084020691651658089142357853055545573
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.52491965536361721236265156181850387237146236418269999772783823251554974003609
Short name T112
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.13 seconds
Started Oct 18 12:26:15 PM PDT 23
Finished Oct 18 12:26:44 PM PDT 23
Peak memory 212720 kb
Host smart-e5c87a34-ffae-4440-a4d2-b3ec253870a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52491965536361721236265156181850387237146236418269999772783823251554974003609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_smoke.52491965536361721236265156181850387237146236418269999772783823251554974003609
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.9477413881255589010828634410922795796738898209628666170146695785314180517114
Short name T161
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.82 seconds
Started Oct 18 12:27:51 PM PDT 23
Finished Oct 18 12:28:35 PM PDT 23
Peak memory 212040 kb
Host smart-616368da-ee89-4107-b9c6-f9c6534f4f7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947741388125558901082863441092279579673889820962866617014669578
5314180517114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.947741388125558901082863441092279579673889820962866
6170146695785314180517114
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.27000662805784454362909379970024634227987248447790618472325730750161816537185
Short name T208
Test name
Test status
Simulation time 3124113076 ps
CPU time 13.37 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 210828 kb
Host smart-200d5f8e-b134-4e07-af69-1dbd9a05388f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000662805784454362909379970024634227987248447790618472325730750161816537185 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.27000662805784454362909379970024634227987248447790618472325730750161816537185
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.2642676772928384462553423559134928608203574175834585430683882593556260340931
Short name T15
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.74 seconds
Started Oct 18 12:27:53 PM PDT 23
Finished Oct 18 12:33:28 PM PDT 23
Peak memory 237564 kb
Host smart-bc2cdda7-13f1-43b4-b1c2-4da77fec13d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642676772928384462553423559134928608203574175834585430683882593556260340931 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.2642676772928384462553423559134928608203574175834585430683
882593556260340931
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.27733774206215612855807006106761673923416504519829127526687745156705126057039
Short name T101
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.03 seconds
Started Oct 18 12:25:48 PM PDT 23
Finished Oct 18 12:26:14 PM PDT 23
Peak memory 210808 kb
Host smart-211bcd32-acd3-4185-9ff0-0fa63a6f4631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27733774206215612855807006106761673923416504519829127526687745156705126057039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rom_ctrl_kmac_err_chk.27733774206215612855807006106761673923416504519829127526687745156705126057039
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.86892033359939779872295604577218669117339325490250719982257705682876700317222
Short name T80
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Oct 18 12:27:31 PM PDT 23
Finished Oct 18 12:27:45 PM PDT 23
Peak memory 210800 kb
Host smart-b14c3ae2-d19a-4355-953d-d209bf3b6a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86892033359939779872295604577218669117339325490250719982257705682876700317222 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.86892033359939779872295604577218669117339325490250719982257705682876700317222
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.76582355041156040118430173300016645879964790344554634559060302712627336602150
Short name T84
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.8 seconds
Started Oct 18 12:27:00 PM PDT 23
Finished Oct 18 12:27:28 PM PDT 23
Peak memory 212472 kb
Host smart-839d81b5-6c20-4e24-a897-9350e9a399d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76582355041156040118430173300016645879964790344554634559060302712627336602150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.rom_ctrl_smoke.76582355041156040118430173300016645879964790344554634559060302712627336602150
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.32354461203561707990071448987465217831041594454700760630490218209010943092118
Short name T295
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.26 seconds
Started Oct 18 12:26:53 PM PDT 23
Finished Oct 18 12:27:37 PM PDT 23
Peak memory 212040 kb
Host smart-4e97354e-a816-48f5-b57c-ae868ad5fbc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323544612035617079900714489874652178310415944547007606304902182
09010943092118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.32354461203561707990071448987465217831041594454700
760630490218209010943092118
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.115560389602500444387828553992118185860911732122414402534292644859299838531491
Short name T1
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 18 12:27:46 PM PDT 23
Finished Oct 18 12:28:04 PM PDT 23
Peak memory 211068 kb
Host smart-4a0033eb-653e-48b4-9a8f-bc810c287041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115560389602500444387828553992118185860911732122414402534292644859299838531491 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.115560389602500444387828553992118185860911732122414402534292644859299838531491
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.8195140240151740276414023755898506345604489362837407899266415450692659966404
Short name T181
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.17 seconds
Started Oct 18 12:25:22 PM PDT 23
Finished Oct 18 12:31:06 PM PDT 23
Peak memory 237636 kb
Host smart-6b2a2c57-8ad0-471c-87ae-c69432eba2c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8195140240151740276414023755898506345604489362837407899266415450692659966404 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.8195140240151740276414023755898506345604489362837407899266
415450692659966404
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.35428034497294358464164684824117893870428367485996780874718026682760727218823
Short name T132
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.12 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:55 PM PDT 23
Peak memory 210708 kb
Host smart-1db8e57e-c889-4f0d-86f1-ec68c92adb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35428034497294358464164684824117893870428367485996780874718026682760727218823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.35428034497294358464164684824117893870428367485996780874718026682760727218823
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.106593006359081372590530363320396333753421412118072941068922386229344899634833
Short name T264
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.43 seconds
Started Oct 18 12:27:01 PM PDT 23
Finished Oct 18 12:27:16 PM PDT 23
Peak memory 210236 kb
Host smart-ade6c827-a5a5-4809-a06d-e84c9bc86b89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106593006359081372590530363320396333753421412118072941068922386229344899634833 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.106593006359081372590530363320396333753421412118072941068922386229344899634833
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.38979660089686698096881859750622053392827480432847824096845230693422007003242
Short name T142
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.08 seconds
Started Oct 18 12:28:25 PM PDT 23
Finished Oct 18 12:28:54 PM PDT 23
Peak memory 212716 kb
Host smart-41bf349c-5cad-4ff5-9eee-ec63da218428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38979660089686698096881859750622053392827480432847824096845230693422007003242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.38979660089686698096881859750622053392827480432847824096845230693422007003242
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.73589705539155049228776532602565095806608552608586489034388002121929280374361
Short name T37
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.44 seconds
Started Oct 18 12:27:05 PM PDT 23
Finished Oct 18 12:27:48 PM PDT 23
Peak memory 212588 kb
Host smart-f36faa4c-30f1-4080-aef2-da9bbc231572
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735897055391550492287765326025650958066085526085864890343880021
21929280374361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.73589705539155049228776532602565095806608552608586
489034388002121929280374361
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.4543219598255673311567558218116169614263905519076043293559572301653906091337
Short name T230
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 18 12:27:46 PM PDT 23
Finished Oct 18 12:27:59 PM PDT 23
Peak memory 211092 kb
Host smart-5431b8d1-6e75-4301-89bc-063c53618c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4543219598255673311567558218116169614263905519076043293559572301653906091337 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.4543219598255673311567558218116169614263905519076043293559572301653906091337
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.71746081440993430607377736586298441927236056686696235533766501598933205935151
Short name T258
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.31 seconds
Started Oct 18 12:28:20 PM PDT 23
Finished Oct 18 12:33:58 PM PDT 23
Peak memory 237600 kb
Host smart-97f3b8a7-d187-4230-b740-e1cfd80bd0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71746081440993430607377736586298441927236056686696235533766501598933205935151 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.717460814409934306073777365862984419272360566866962355337
66501598933205935151
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.110789560033868139592954534853977329684817986216342978643235657627419376386940
Short name T129
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Oct 18 12:27:04 PM PDT 23
Finished Oct 18 12:27:30 PM PDT 23
Peak memory 211232 kb
Host smart-5938a091-e160-4468-b1f2-f5eb75327958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110789560033868139592954534853977329684817986216342978643235657627419376386940 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.rom_ctrl_kmac_err_chk.110789560033868139592954534853977329684817986216342978643235657627419376386940
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.8259686858336966871318859701435015968382545843600167623282968454513905160908
Short name T237
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.02 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 209744 kb
Host smart-be69646c-0219-4239-a973-5f856123cad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8259686858336966871318859701435015968382545843600167623282968454513905160908 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.8259686858336966871318859701435015968382545843600167623282968454513905160908
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.68756759881485647521483856726124479991992115026496971907432195000319790248270
Short name T329
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.08 seconds
Started Oct 18 12:26:08 PM PDT 23
Finished Oct 18 12:26:37 PM PDT 23
Peak memory 211292 kb
Host smart-95888ff4-1c1c-4262-aecd-bfd0323fd3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68756759881485647521483856726124479991992115026496971907432195000319790248270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.rom_ctrl_smoke.68756759881485647521483856726124479991992115026496971907432195000319790248270
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.11124406535607551481332101259809411060391107316678894073887140767816582663323
Short name T170
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.75 seconds
Started Oct 18 12:26:24 PM PDT 23
Finished Oct 18 12:27:06 PM PDT 23
Peak memory 212776 kb
Host smart-7fec3ea7-89b7-4901-a05f-123abbe06d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111244065356075514813321012598094110603911073166788940738871407
67816582663323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.11124406535607551481332101259809411060391107316678
894073887140767816582663323
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.109835613384169883416508767102300092563624929711060186043850222092401957811965
Short name T109
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 18 12:27:49 PM PDT 23
Finished Oct 18 12:28:02 PM PDT 23
Peak memory 211060 kb
Host smart-9c72ef2e-294a-4285-b1fa-e350ee0f3a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109835613384169883416508767102300092563624929711060186043850222092401957811965 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.109835613384169883416508767102300092563624929711060186043850222092401957811965
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.94034348603385948795389034708234331604192527106365889960706196873040193627352
Short name T220
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.73 seconds
Started Oct 18 12:22:41 PM PDT 23
Finished Oct 18 12:28:22 PM PDT 23
Peak memory 237592 kb
Host smart-49ac466c-778d-47d5-81bc-75220165b0f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94034348603385948795389034708234331604192527106365889960706196873040193627352 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.9403434860338594879538903470823433160419252710636588996070
6196873040193627352
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.43164695564653222034346292430585284644064925270839341403850843106588435444371
Short name T200
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.49 seconds
Started Oct 18 12:21:49 PM PDT 23
Finished Oct 18 12:22:17 PM PDT 23
Peak memory 211520 kb
Host smart-b285df11-7215-4e02-a242-55b620bccf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43164695564653222034346292430585284644064925270839341403850843106588435444371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.rom_ctrl_kmac_err_chk.43164695564653222034346292430585284644064925270839341403850843106588435444371
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.92453754593278870794289572870588862840802748165843543826204443769328918816489
Short name T214
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.89 seconds
Started Oct 18 12:26:04 PM PDT 23
Finished Oct 18 12:26:18 PM PDT 23
Peak memory 210848 kb
Host smart-13221472-f360-4ac7-8ba6-dc5f815b0880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92453754593278870794289572870588862840802748165843543826204443769328918816489 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.92453754593278870794289572870588862840802748165843543826204443769328918816489
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.62979690531501751714815368906500555201571163283511984221855530633849617648927
Short name T151
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Oct 18 12:28:33 PM PDT 23
Finished Oct 18 12:29:02 PM PDT 23
Peak memory 212696 kb
Host smart-238b9385-75cd-4202-a09c-778bbae944b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62979690531501751714815368906500555201571163283511984221855530633849617648927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_smoke.62979690531501751714815368906500555201571163283511984221855530633849617648927
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.101231524568719805779705929845294844120433206045757987966323637701087356594491
Short name T354
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.56 seconds
Started Oct 18 12:27:38 PM PDT 23
Finished Oct 18 12:28:21 PM PDT 23
Peak memory 212896 kb
Host smart-b97a43b8-4a42-4fb6-9056-dab27a4ec5d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101231524568719805779705929845294844120433206045757987966323637
701087356594491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.10123152456871980577970592984529484412043320604575
7987966323637701087356594491
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.20517183884590663196033329166864329266578793663446465733227064478689116368116
Short name T98
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 18 12:25:30 PM PDT 23
Finished Oct 18 12:25:43 PM PDT 23
Peak memory 210316 kb
Host smart-debdafcd-63aa-4627-8ae9-309d8b2fc783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20517183884590663196033329166864329266578793663446465733227064478689116368116 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.20517183884590663196033329166864329266578793663446465733227064478689116368116
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.85571440989827005767707555758556608668739242518993304687415519260491095947435
Short name T171
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.45 seconds
Started Oct 18 12:25:32 PM PDT 23
Finished Oct 18 12:31:05 PM PDT 23
Peak memory 237336 kb
Host smart-9fd26b2e-3f4e-4470-af59-93423b0423da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85571440989827005767707555758556608668739242518993304687415519260491095947435 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.8557144098982700576770755575855660866873924251899330468741
5519260491095947435
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.106353760038440649660551754768141804294952695373621342928944908156068917066201
Short name T272
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.36 seconds
Started Oct 18 12:27:35 PM PDT 23
Finished Oct 18 12:28:01 PM PDT 23
Peak memory 211500 kb
Host smart-ad971109-7619-45ed-addb-c2f866bc963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106353760038440649660551754768141804294952695373621342928944908156068917066201 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rom_ctrl_kmac_err_chk.106353760038440649660551754768141804294952695373621342928944908156068917066201
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.62435662313010572671486990487216914159357132825742943274311465948401300964428
Short name T249
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.32 seconds
Started Oct 18 12:22:42 PM PDT 23
Finished Oct 18 12:22:56 PM PDT 23
Peak memory 211120 kb
Host smart-807ff9f7-14f7-4c9b-9916-9e055288d856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62435662313010572671486990487216914159357132825742943274311465948401300964428 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.62435662313010572671486990487216914159357132825742943274311465948401300964428
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.90642330756452547332936564742684005448800981223834349902496866572675858060385
Short name T318
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.86 seconds
Started Oct 18 12:28:16 PM PDT 23
Finished Oct 18 12:28:44 PM PDT 23
Peak memory 212504 kb
Host smart-e7873971-554d-4ec6-84bc-4c6924520a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90642330756452547332936564742684005448800981223834349902496866572675858060385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_smoke.90642330756452547332936564742684005448800981223834349902496866572675858060385
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.33418691239580477436704908087917747771040703318230885816778255985309485847983
Short name T352
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.37 seconds
Started Oct 18 12:27:40 PM PDT 23
Finished Oct 18 12:28:22 PM PDT 23
Peak memory 212856 kb
Host smart-21ac22f6-5eda-40a2-8cbd-2ee425ecf483
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334186912395804774367049080879177477710407033182308858167782559
85309485847983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.334186912395804774367049080879177477710407033182308
85816778255985309485847983
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.52363534049389117770654350836218728406641097738313945751331688547912846042628
Short name T190
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.13 seconds
Started Oct 18 12:31:40 PM PDT 23
Finished Oct 18 12:31:53 PM PDT 23
Peak memory 211080 kb
Host smart-48ecb9d6-b68d-4a23-9b45-4d816ed09def
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52363534049389117770654350836218728406641097738313945751331688547912846042628 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.52363534049389117770654350836218728406641097738313945751331688547912846042628
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.89041523030324290352965192916117736011438437050567005406401078286721096917349
Short name T160
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.64 seconds
Started Oct 18 12:27:43 PM PDT 23
Finished Oct 18 12:33:21 PM PDT 23
Peak memory 237352 kb
Host smart-b415d4ac-e665-4c81-9abf-3f8302d9d4ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89041523030324290352965192916117736011438437050567005406401078286721096917349 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.8904152303032429035296519291611773601143843705056700540640
1078286721096917349
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.37347225471760018578596500804710434371279332709787706517918010359367691307776
Short name T139
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.4 seconds
Started Oct 18 12:28:03 PM PDT 23
Finished Oct 18 12:28:29 PM PDT 23
Peak memory 211540 kb
Host smart-6a3f9afd-e12d-4cc5-aab1-c2c126d1f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37347225471760018578596500804710434371279332709787706517918010359367691307776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.rom_ctrl_kmac_err_chk.37347225471760018578596500804710434371279332709787706517918010359367691307776
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.64661974274060875001617059261214541718911176764428818020085709431178757992810
Short name T2
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.46 seconds
Started Oct 18 12:35:34 PM PDT 23
Finished Oct 18 12:35:47 PM PDT 23
Peak memory 211136 kb
Host smart-6a538935-538b-431f-a88f-5c305b878dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64661974274060875001617059261214541718911176764428818020085709431178757992810 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.64661974274060875001617059261214541718911176764428818020085709431178757992810
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.40084974889866868586954109961758788809041640870076961878420365194006619255395
Short name T224
Test name
Test status
Simulation time 6265461576 ps
CPU time 30.29 seconds
Started Oct 18 12:22:38 PM PDT 23
Finished Oct 18 12:23:09 PM PDT 23
Peak memory 212852 kb
Host smart-50852010-8bb4-45bf-b77b-98067eff176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40084974889866868586954109961758788809041640870076961878420365194006619255395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.rom_ctrl_smoke.40084974889866868586954109961758788809041640870076961878420365194006619255395
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.110352641249043859871890532902917195139403826137341565377931627450135799211606
Short name T159
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.08 seconds
Started Oct 18 12:32:08 PM PDT 23
Finished Oct 18 12:32:51 PM PDT 23
Peak memory 212836 kb
Host smart-39d9c172-9a3a-4d14-812d-b2353734c639
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110352641249043859871890532902917195139403826137341565377931627
450135799211606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.11035264124904385987189053290291719513940382613734
1565377931627450135799211606
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.115682113408776696206274215020651477359327095239576869498874343167211129736756
Short name T34
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.11 seconds
Started Oct 18 12:28:12 PM PDT 23
Finished Oct 18 12:28:25 PM PDT 23
Peak memory 211052 kb
Host smart-155deb53-6014-4dfe-8e01-32b901060281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115682113408776696206274215020651477359327095239576869498874343167211129736756 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.115682113408776696206274215020651477359327095239576869498874343167211129736756
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.105864560032827920164823982096967624314400354730203231824175038985355838805205
Short name T40
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.64 seconds
Started Oct 18 12:29:03 PM PDT 23
Finished Oct 18 12:34:46 PM PDT 23
Peak memory 236984 kb
Host smart-a00e8b8a-44bc-467d-b52d-8c8aee1ac626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105864560032827920164823982096967624314400354730203231824175038985355838805205 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.105864560032827920164823982096967624314400354730203231824
175038985355838805205
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.21100092323189919998038740583279304491774631571296363121040890361358847046398
Short name T183
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.41 seconds
Started Oct 18 12:28:39 PM PDT 23
Finished Oct 18 12:29:05 PM PDT 23
Peak memory 211472 kb
Host smart-f049ec1d-fecb-432a-96b4-b4b1ec281a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21100092323189919998038740583279304491774631571296363121040890361358847046398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.21100092323189919998038740583279304491774631571296363121040890361358847046398
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.50961519291933381754371858903888648009295491024108214686528943870041408987525
Short name T315
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Oct 18 12:35:12 PM PDT 23
Finished Oct 18 12:35:26 PM PDT 23
Peak memory 211076 kb
Host smart-ca724e1c-422a-425a-bb52-09178711ecb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50961519291933381754371858903888648009295491024108214686528943870041408987525 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.50961519291933381754371858903888648009295491024108214686528943870041408987525
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.63723856494056724069055369601323624363804555764967322036288016304462576124512
Short name T243
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.08 seconds
Started Oct 18 12:28:14 PM PDT 23
Finished Oct 18 12:28:43 PM PDT 23
Peak memory 212292 kb
Host smart-00f8b083-9e0e-47e1-8700-bb9ab0f4fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63723856494056724069055369601323624363804555764967322036288016304462576124512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.63723856494056724069055369601323624363804555764967322036288016304462576124512
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.65192765278042447341201086380092083636934758842420450310100590758632359606460
Short name T126
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.81 seconds
Started Oct 18 12:27:18 PM PDT 23
Finished Oct 18 12:28:01 PM PDT 23
Peak memory 212804 kb
Host smart-b5338ed2-91ce-43b6-bfb6-90433eb69d1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651927652780424473412010863800920836369347588424204503101005907
58632359606460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.651927652780424473412010863800920836369347588424204
50310100590758632359606460
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.31611047141479599114701907123956589595326556961137694337874015928280906693413
Short name T292
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.37 seconds
Started Oct 18 12:30:35 PM PDT 23
Finished Oct 18 12:30:48 PM PDT 23
Peak memory 211164 kb
Host smart-a2a9badd-8730-4300-934f-ff8d308d4dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31611047141479599114701907123956589595326556961137694337874015928280906693413 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.31611047141479599114701907123956589595326556961137694337874015928280906693413
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1052719541856176385292053021262331714926911905594579066435208499409119735085
Short name T140
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.01 seconds
Started Oct 18 12:26:12 PM PDT 23
Finished Oct 18 12:31:50 PM PDT 23
Peak memory 236924 kb
Host smart-3c1406b1-e1e5-4e53-914a-be1a67279341
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052719541856176385292053021262331714926911905594579066435208499409119735085 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.10527195418561763852920530212623317149269119055945790664352
08499409119735085
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2600216843119055047666098940686327963923573050395322735926566408960517250984
Short name T206
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Oct 18 12:30:10 PM PDT 23
Finished Oct 18 12:30:37 PM PDT 23
Peak memory 211616 kb
Host smart-4bf5f614-d34b-4a1a-8711-e9cb90b27b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600216843119055047666098940686327963923573050395322735926566408960517250984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.rom_ctrl_kmac_err_chk.2600216843119055047666098940686327963923573050395322735926566408960517250984
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.113051297793238686289028056367065993282423340230913877498129396308362810830941
Short name T282
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.98 seconds
Started Oct 18 12:29:15 PM PDT 23
Finished Oct 18 12:29:28 PM PDT 23
Peak memory 211060 kb
Host smart-173ab713-9e8f-4efc-9b21-7b6a58a959d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113051297793238686289028056367065993282423340230913877498129396308362810830941 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.113051297793238686289028056367065993282423340230913877498129396308362810830941
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.62123564609470035734666658355672082187567262607243661658641214481476053899456
Short name T119
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.7 seconds
Started Oct 18 12:37:46 PM PDT 23
Finished Oct 18 12:38:15 PM PDT 23
Peak memory 212744 kb
Host smart-688906d0-c420-4a4a-b9e0-a60d49e12bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62123564609470035734666658355672082187567262607243661658641214481476053899456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.62123564609470035734666658355672082187567262607243661658641214481476053899456
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.9238146326932292097537676145711098372131674547242249064309170322526594634506
Short name T75
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.73 seconds
Started Oct 18 12:36:45 PM PDT 23
Finished Oct 18 12:37:28 PM PDT 23
Peak memory 212944 kb
Host smart-4ea595e1-8327-4ecd-a91d-3e2b8eab9fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923814632693229209753767614571109837213167454724224906430917032
2526594634506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.9238146326932292097537676145711098372131674547242249
064309170322526594634506
Directory /workspace/9.rom_ctrl_stress_all/latest
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