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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T267 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.32786117619233324303839702094959218636501515626538661986562550467772027125305 Oct 22 01:44:15 PM PDT 23 Oct 22 01:44:41 PM PDT 23 6233818126 ps
T268 /workspace/coverage/default/31.rom_ctrl_stress_all.24875824389688666748405201718973388751840972383827052873039071447823957441445 Oct 22 01:44:52 PM PDT 23 Oct 22 01:45:36 PM PDT 23 9415977006 ps
T269 /workspace/coverage/default/27.rom_ctrl_alert_test.54442687896894973361618659835122044955022085573057821555869453900859112532633 Oct 22 01:45:33 PM PDT 23 Oct 22 01:45:46 PM PDT 23 3124113076 ps
T270 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.50408432930438679550997214375115935894865767971257507566543300528636584735847 Oct 22 01:47:22 PM PDT 23 Oct 22 01:47:36 PM PDT 23 3151732636 ps
T271 /workspace/coverage/default/17.rom_ctrl_stress_all.55533468821644897208543275497273699605087186775994998542891468739182158834309 Oct 22 01:43:27 PM PDT 23 Oct 22 01:44:10 PM PDT 23 9415977006 ps
T272 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.56927764684425221433051665484996183510688428573416929894973217783716205099125 Oct 22 01:44:18 PM PDT 23 Oct 22 01:44:32 PM PDT 23 3151732636 ps
T273 /workspace/coverage/default/19.rom_ctrl_smoke.53211116174163506948709253411130923736778742529073952293971801802443211521782 Oct 22 01:44:16 PM PDT 23 Oct 22 01:44:45 PM PDT 23 6265461576 ps
T274 /workspace/coverage/default/36.rom_ctrl_stress_all.9491152166848735577679711254508660748232412370364814859918373984114722760637 Oct 22 01:47:28 PM PDT 23 Oct 22 01:48:11 PM PDT 23 9415977006 ps
T275 /workspace/coverage/default/30.rom_ctrl_smoke.33897871818529057881303248370941012511583745464188300934075478578933661189831 Oct 22 01:43:36 PM PDT 23 Oct 22 01:44:05 PM PDT 23 6265461576 ps
T276 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.85597543816255540722852496929736312380796218447776099265591728746448070921565 Oct 22 01:46:39 PM PDT 23 Oct 22 01:52:22 PM PDT 23 69854280986 ps
T277 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.5570743854261992658935159787929683957070572384863838445372008991089090549306 Oct 22 01:45:09 PM PDT 23 Oct 22 01:50:54 PM PDT 23 69854280986 ps
T278 /workspace/coverage/default/36.rom_ctrl_smoke.55569055860802939469448132101184485116746936519279541470918377037236879645448 Oct 22 01:46:11 PM PDT 23 Oct 22 01:46:41 PM PDT 23 6265461576 ps
T279 /workspace/coverage/default/33.rom_ctrl_smoke.13198884113295075762361772697748808331099468628491414106699419691174584968833 Oct 22 01:45:34 PM PDT 23 Oct 22 01:46:02 PM PDT 23 6265461576 ps
T280 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.55076213385498985022663870491075512854499824119298424470932220672716791448442 Oct 22 01:45:32 PM PDT 23 Oct 22 01:51:16 PM PDT 23 69854280986 ps
T281 /workspace/coverage/default/15.rom_ctrl_stress_all.75971862768366911314755243244877091928494526639243073686213543815382354480670 Oct 22 01:46:09 PM PDT 23 Oct 22 01:46:52 PM PDT 23 9415977006 ps
T282 /workspace/coverage/default/44.rom_ctrl_smoke.100601783114501810527295236563092289358442008079911945692166310188684493525646 Oct 22 01:45:47 PM PDT 23 Oct 22 01:46:17 PM PDT 23 6265461576 ps
T283 /workspace/coverage/default/14.rom_ctrl_smoke.38339808113658286242925856669332743904234674923807716983782283807281827672628 Oct 22 01:45:39 PM PDT 23 Oct 22 01:46:08 PM PDT 23 6265461576 ps
T284 /workspace/coverage/default/1.rom_ctrl_stress_all.64120585135866677094406006541489812491774675725009818861822243284907109857884 Oct 22 01:44:37 PM PDT 23 Oct 22 01:45:20 PM PDT 23 9415977006 ps
T285 /workspace/coverage/default/20.rom_ctrl_alert_test.14604062407912674997873309439771355898687544208413487812508147009820195027964 Oct 22 01:44:53 PM PDT 23 Oct 22 01:45:06 PM PDT 23 3124113076 ps
T286 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.59322178014528743944244048472047469284703779524432937910136155258500219499189 Oct 22 01:44:55 PM PDT 23 Oct 22 01:45:08 PM PDT 23 3151732636 ps
T287 /workspace/coverage/default/38.rom_ctrl_stress_all.68743235699008967740708781268549404952309157712564975663601216942451051258790 Oct 22 01:44:43 PM PDT 23 Oct 22 01:45:26 PM PDT 23 9415977006 ps
T288 /workspace/coverage/default/44.rom_ctrl_alert_test.72218090569384212017258182123871987136035336391761737671143726361161446188168 Oct 22 01:44:52 PM PDT 23 Oct 22 01:45:05 PM PDT 23 3124113076 ps
T289 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.46171941882538672391322125409546210318214899682615160947591169274084311640822 Oct 22 01:44:17 PM PDT 23 Oct 22 01:50:08 PM PDT 23 69854280986 ps
T290 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.50679490960563016057897118750913001961527311995536472701592471717862480303259 Oct 22 01:45:06 PM PDT 23 Oct 22 01:50:47 PM PDT 23 69854280986 ps
T291 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.26539860658492299638564413267232778909146256008186621256605184067096224132268 Oct 22 01:43:19 PM PDT 23 Oct 22 01:49:03 PM PDT 23 69854280986 ps
T292 /workspace/coverage/default/21.rom_ctrl_smoke.102158492327671686540611551646336727298148120995767405216401353372265021669268 Oct 22 01:43:25 PM PDT 23 Oct 22 01:43:55 PM PDT 23 6265461576 ps
T293 /workspace/coverage/default/21.rom_ctrl_stress_all.68234748694806394524830098075373895754615306235962939014794650382231791743576 Oct 22 01:45:01 PM PDT 23 Oct 22 01:45:44 PM PDT 23 9415977006 ps
T294 /workspace/coverage/default/23.rom_ctrl_alert_test.59965818014389148214705382362373005484531809201880951912970247758173836947205 Oct 22 01:45:55 PM PDT 23 Oct 22 01:46:07 PM PDT 23 3124113076 ps
T295 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.19751204246278106265520355341411598764716968717857174830484857986311616112510 Oct 22 01:44:34 PM PDT 23 Oct 22 01:44:47 PM PDT 23 3151732636 ps
T296 /workspace/coverage/default/49.rom_ctrl_stress_all.4002797932538090269710407117578333279750307739775569978703383268442394821617 Oct 22 01:46:27 PM PDT 23 Oct 22 01:47:10 PM PDT 23 9415977006 ps
T297 /workspace/coverage/default/8.rom_ctrl_alert_test.72544389004362606461964016508955953689923495175185274692318584812350124196378 Oct 22 01:43:21 PM PDT 23 Oct 22 01:43:34 PM PDT 23 3124113076 ps
T298 /workspace/coverage/default/13.rom_ctrl_alert_test.35971827465330026824934130307184271817544884265684429497737009547154981726420 Oct 22 01:45:35 PM PDT 23 Oct 22 01:45:48 PM PDT 23 3124113076 ps
T299 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.57391387092654888395554567685213657150015322591969329121684330355191883974438 Oct 22 01:46:08 PM PDT 23 Oct 22 01:46:22 PM PDT 23 3151732636 ps
T300 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.34728016892166736669099233686142532345146677918246743190204897711740293563117 Oct 22 01:45:53 PM PDT 23 Oct 22 01:46:07 PM PDT 23 3151732636 ps
T35 /workspace/coverage/default/3.rom_ctrl_sec_cm.17490179998387200916340540791079220503854751035017275330048247609843499056639 Oct 22 01:44:32 PM PDT 23 Oct 22 01:46:30 PM PDT 23 3444857586 ps
T301 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.42582516721607689127377578765918677592083863061385234032044044897228107179534 Oct 22 01:44:35 PM PDT 23 Oct 22 01:45:01 PM PDT 23 6233818126 ps
T302 /workspace/coverage/default/2.rom_ctrl_alert_test.15543184179129412105828707460013632297113600915687235482691984716394992965237 Oct 22 01:44:32 PM PDT 23 Oct 22 01:44:45 PM PDT 23 3124113076 ps
T303 /workspace/coverage/default/20.rom_ctrl_smoke.7468205839234881167420623361984803521387735991582910089942023658156933706056 Oct 22 01:45:13 PM PDT 23 Oct 22 01:45:42 PM PDT 23 6265461576 ps
T304 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.9787848014824438610527949525077618671279700318291320612541488722718787104313 Oct 22 01:43:25 PM PDT 23 Oct 22 01:43:51 PM PDT 23 6233818126 ps
T305 /workspace/coverage/default/24.rom_ctrl_alert_test.12908799538105954611671185580905096217874422681535107211275867926704829383035 Oct 22 01:45:34 PM PDT 23 Oct 22 01:45:47 PM PDT 23 3124113076 ps
T306 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.29039654437118359040102625168214252058913373493508994190227382355875453017592 Oct 22 01:45:46 PM PDT 23 Oct 22 01:46:13 PM PDT 23 6233818126 ps
T307 /workspace/coverage/default/34.rom_ctrl_stress_all.39257334392959307546964926524728933775109267327106983256955801836499690158801 Oct 22 01:46:39 PM PDT 23 Oct 22 01:47:22 PM PDT 23 9415977006 ps
T308 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.80111340591919012331501576119348543322477536169184715786944177626078027735819 Oct 22 01:45:08 PM PDT 23 Oct 22 01:45:21 PM PDT 23 3151732636 ps
T309 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.103134805728261796805619380147310683752676921640463348860568187487494334833269 Oct 22 01:45:07 PM PDT 23 Oct 22 01:50:50 PM PDT 23 69854280986 ps
T310 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.35610623515420075066385598817970216218350222644011722797371344519940344265898 Oct 22 01:45:06 PM PDT 23 Oct 22 01:45:20 PM PDT 23 3151732636 ps
T311 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.54370387605433676476565016837059978803260309034180676401404067950936457786540 Oct 22 01:45:51 PM PDT 23 Oct 22 01:46:05 PM PDT 23 3151732636 ps
T312 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.100138827244864824559064165210601170072785592818184354309260376155763294895552 Oct 22 01:43:28 PM PDT 23 Oct 22 01:43:54 PM PDT 23 6233818126 ps
T313 /workspace/coverage/default/0.rom_ctrl_stress_all.16656658156617630161602211689918231676373816841543471824204373442358944114153 Oct 22 01:44:50 PM PDT 23 Oct 22 01:45:32 PM PDT 23 9415977006 ps
T314 /workspace/coverage/default/48.rom_ctrl_stress_all.73238082186553246768249523454442690424296661665317256110353270573050273569056 Oct 22 01:47:24 PM PDT 23 Oct 22 01:48:07 PM PDT 23 9415977006 ps
T315 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.27159781839161526961387768572214993746507787743213641251354780210753688911541 Oct 22 01:43:24 PM PDT 23 Oct 22 01:49:11 PM PDT 23 69854280986 ps
T316 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.95839592497030832653259862368537504824634841836320004333048171409880882341171 Oct 22 01:47:22 PM PDT 23 Oct 22 01:47:36 PM PDT 23 3151732636 ps
T317 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.14592952362156500950213242105110201617854002366279078339682919733503607535305 Oct 22 01:45:31 PM PDT 23 Oct 22 01:51:10 PM PDT 23 69854280986 ps
T318 /workspace/coverage/default/45.rom_ctrl_stress_all.30664550718280682266524588226978636078892722734660132170568166499711683459993 Oct 22 01:45:07 PM PDT 23 Oct 22 01:45:50 PM PDT 23 9415977006 ps
T319 /workspace/coverage/default/29.rom_ctrl_stress_all.17154577748029636218222855352262535544323012000941383179243647113781863072800 Oct 22 01:43:39 PM PDT 23 Oct 22 01:44:22 PM PDT 23 9415977006 ps
T320 /workspace/coverage/default/10.rom_ctrl_stress_all.37103618389606444117451393042378750049374812554355091383078448084720052098072 Oct 22 01:44:13 PM PDT 23 Oct 22 01:44:59 PM PDT 23 9415977006 ps
T321 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.7466391513930257748182216444058664625354379971815367542627172902285880422958 Oct 22 01:43:29 PM PDT 23 Oct 22 01:43:56 PM PDT 23 6233818126 ps
T322 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.88515561967501203981212098506607776801249526397279524092666720562339892720304 Oct 22 01:44:31 PM PDT 23 Oct 22 01:44:57 PM PDT 23 6233818126 ps
T323 /workspace/coverage/default/39.rom_ctrl_stress_all.35774668031802376180609957146100603280771946413219290000578935820733336653333 Oct 22 01:44:50 PM PDT 23 Oct 22 01:45:35 PM PDT 23 9415977006 ps
T324 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.40887256441239022700951014003133547823384223115304473757614697510647887633686 Oct 22 01:44:53 PM PDT 23 Oct 22 01:50:33 PM PDT 23 69854280986 ps
T325 /workspace/coverage/default/34.rom_ctrl_alert_test.27740549435682238452016337564081841791825743596452614373537927259688638092259 Oct 22 01:46:35 PM PDT 23 Oct 22 01:46:47 PM PDT 23 3124113076 ps
T326 /workspace/coverage/default/12.rom_ctrl_alert_test.7163303313802146728205797577981464739009870824879250635237924316671492802953 Oct 22 01:45:16 PM PDT 23 Oct 22 01:45:28 PM PDT 23 3124113076 ps
T36 /workspace/coverage/default/0.rom_ctrl_sec_cm.11211936493406822610831749746788273169456173712642751351709178426503777404877 Oct 22 01:43:24 PM PDT 23 Oct 22 01:45:20 PM PDT 23 3444857586 ps
T327 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.54966830616330651747601376046929156520695912264873350916476185229706808303162 Oct 22 01:44:54 PM PDT 23 Oct 22 01:45:08 PM PDT 23 3151732636 ps
T328 /workspace/coverage/default/17.rom_ctrl_alert_test.49696316120032189962641668406071893430242089938326909299278321541860575279657 Oct 22 01:44:57 PM PDT 23 Oct 22 01:45:09 PM PDT 23 3124113076 ps
T329 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.83483342649761662144449675023876515880236758288135954996862682811258229561217 Oct 22 01:46:08 PM PDT 23 Oct 22 01:51:46 PM PDT 23 69854280986 ps
T330 /workspace/coverage/default/38.rom_ctrl_alert_test.80144965772711797487879678334673171547498249220313865045967708987780474226683 Oct 22 01:44:52 PM PDT 23 Oct 22 01:45:05 PM PDT 23 3124113076 ps
T331 /workspace/coverage/default/26.rom_ctrl_smoke.82965880963859182355043172865807501001580423583986048024671120436994678192726 Oct 22 01:45:04 PM PDT 23 Oct 22 01:45:33 PM PDT 23 6265461576 ps
T332 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2797430827045066809395888130794080683891054763345289409215213074616634432624 Oct 22 01:46:15 PM PDT 23 Oct 22 01:51:56 PM PDT 23 69854280986 ps
T333 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.17858669437941684517784123384188724772804501895672527645845878334208168527246 Oct 22 01:44:47 PM PDT 23 Oct 22 01:50:23 PM PDT 23 69854280986 ps
T334 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.33943789362933756939796791742659212863137640052635438575133169548816926895767 Oct 22 01:45:07 PM PDT 23 Oct 22 01:45:21 PM PDT 23 3151732636 ps
T335 /workspace/coverage/default/6.rom_ctrl_stress_all.100334074925461077110338313805857453201775123111973957136606839236586457170968 Oct 22 01:44:51 PM PDT 23 Oct 22 01:45:34 PM PDT 23 9415977006 ps
T336 /workspace/coverage/default/19.rom_ctrl_alert_test.24437660670399949200637017883554136657026487193453622715860177547753477673199 Oct 22 01:45:00 PM PDT 23 Oct 22 01:45:12 PM PDT 23 3124113076 ps
T337 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.69285323194842628146429892428492511719839980242076611317665684117060663597287 Oct 22 01:43:25 PM PDT 23 Oct 22 01:43:51 PM PDT 23 6233818126 ps
T338 /workspace/coverage/default/40.rom_ctrl_smoke.89191459188000997979560561217111609847287942661541165723553138677703278140431 Oct 22 01:43:33 PM PDT 23 Oct 22 01:44:02 PM PDT 23 6265461576 ps
T339 /workspace/coverage/default/34.rom_ctrl_smoke.13904754525308579062944305919741110863948695062954643460178315757177872075544 Oct 22 01:47:17 PM PDT 23 Oct 22 01:47:46 PM PDT 23 6265461576 ps
T340 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.34938222620071469734894507362915244406308362802761863445436299275413332710956 Oct 22 01:44:34 PM PDT 23 Oct 22 01:44:48 PM PDT 23 3151732636 ps
T341 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4501127297685155961056480558167473329371990763957749763039536767848651496753 Oct 22 01:43:23 PM PDT 23 Oct 22 01:43:49 PM PDT 23 6233818126 ps
T342 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.104082882096516691480319213317340184978649451209465557277321734937523835115858 Oct 22 01:44:18 PM PDT 23 Oct 22 01:44:44 PM PDT 23 6233818126 ps
T343 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.31510015683819375029765565601728839461799906208311603236570696417009528785918 Oct 22 01:43:27 PM PDT 23 Oct 22 01:49:18 PM PDT 23 69854280986 ps
T344 /workspace/coverage/default/46.rom_ctrl_smoke.25950274582097349994270865555189602835827850061514079308662297508607649142320 Oct 22 01:44:58 PM PDT 23 Oct 22 01:45:27 PM PDT 23 6265461576 ps
T345 /workspace/coverage/default/25.rom_ctrl_stress_all.35801876189940727231048981044272376445587792362752382233635365360050182333645 Oct 22 01:44:58 PM PDT 23 Oct 22 01:45:42 PM PDT 23 9415977006 ps
T346 /workspace/coverage/default/33.rom_ctrl_alert_test.91741479827855816353352768099440363234158441426642224454435768830458613844343 Oct 22 01:46:22 PM PDT 23 Oct 22 01:46:35 PM PDT 23 3124113076 ps
T347 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.15824295693215703957070214617034939703633726791275865780863411112948892523039 Oct 22 01:44:54 PM PDT 23 Oct 22 01:45:08 PM PDT 23 3151732636 ps
T348 /workspace/coverage/default/39.rom_ctrl_alert_test.8624179273559141196944578511241044462145330873514173200274272856571742102283 Oct 22 01:44:51 PM PDT 23 Oct 22 01:45:04 PM PDT 23 3124113076 ps
T349 /workspace/coverage/default/19.rom_ctrl_stress_all.30609832087215580200914962390945647567080302194099866422963699228285271203039 Oct 22 01:44:15 PM PDT 23 Oct 22 01:44:58 PM PDT 23 9415977006 ps
T350 /workspace/coverage/default/42.rom_ctrl_alert_test.51587498875147594926257216672993864222897465950695286432613447644159214639483 Oct 22 01:45:01 PM PDT 23 Oct 22 01:45:14 PM PDT 23 3124113076 ps
T351 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.43076070872172494731552324638381229497990564573416589178194555657085404596804 Oct 22 01:45:08 PM PDT 23 Oct 22 01:45:21 PM PDT 23 3151732636 ps
T352 /workspace/coverage/default/1.rom_ctrl_smoke.87758433211393223044043526212579857841935860205042746870273616440502962267961 Oct 22 01:44:36 PM PDT 23 Oct 22 01:45:05 PM PDT 23 6265461576 ps
T353 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.57748072609430298810678804711773523475652079669141029981298841455449922087429 Oct 22 01:45:36 PM PDT 23 Oct 22 01:45:51 PM PDT 23 3151732636 ps
T354 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.99137479798694569453407646612573177693166309516521662596764027648165491653236 Oct 22 01:43:27 PM PDT 23 Oct 22 01:43:40 PM PDT 23 3151732636 ps
T355 /workspace/coverage/default/29.rom_ctrl_alert_test.85434062348465067187216329799481301991515593175282394174630882885742439670906 Oct 22 01:44:58 PM PDT 23 Oct 22 01:45:10 PM PDT 23 3124113076 ps
T356 /workspace/coverage/default/48.rom_ctrl_alert_test.105419554002542809895734266038119076826733700813089262528806029941849687798243 Oct 22 01:46:21 PM PDT 23 Oct 22 01:46:34 PM PDT 23 3124113076 ps
T357 /workspace/coverage/default/23.rom_ctrl_stress_all.6339513469352275010137651205570252850761900464726912883776058024269932188798 Oct 22 01:45:20 PM PDT 23 Oct 22 01:46:05 PM PDT 23 9415977006 ps
T358 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.65389642319713550910208523532601637567152723530450653943338738636102413773860 Oct 22 01:44:33 PM PDT 23 Oct 22 01:44:59 PM PDT 23 6233818126 ps
T359 /workspace/coverage/default/46.rom_ctrl_stress_all.82562335624408366578152971311214784971179789651557636629421018972425801631234 Oct 22 01:45:01 PM PDT 23 Oct 22 01:45:44 PM PDT 23 9415977006 ps
T360 /workspace/coverage/default/28.rom_ctrl_stress_all.39761152401230908438710593147751030503000722004793398103792025556955655324506 Oct 22 01:45:33 PM PDT 23 Oct 22 01:46:17 PM PDT 23 9415977006 ps
T361 /workspace/coverage/default/49.rom_ctrl_alert_test.68049944314610932577176813415383676447225453513206426523741801495599992781641 Oct 22 01:47:27 PM PDT 23 Oct 22 01:47:40 PM PDT 23 3124113076 ps
T362 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.58097468289115001015838947580129147280991527313900496254068549383058278677032 Oct 22 01:45:02 PM PDT 23 Oct 22 01:45:27 PM PDT 23 6233818126 ps
T363 /workspace/coverage/default/4.rom_ctrl_stress_all.74544617862069692771009833531225670238008138603078344391763919276894502234786 Oct 22 01:43:26 PM PDT 23 Oct 22 01:44:10 PM PDT 23 9415977006 ps
T364 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.83642161276804491523279462518011793291895442645601152022452031450055018159113 Oct 22 01:43:26 PM PDT 23 Oct 22 01:43:40 PM PDT 23 3151732636 ps
T365 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.112571016605950046081487713457282614081587945519180331196878755199233055185228 Oct 22 01:45:33 PM PDT 23 Oct 22 01:45:47 PM PDT 23 3151732636 ps
T366 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.17097368837575620603941350506161621848598659676300757479547165905735022300498 Oct 22 01:45:38 PM PDT 23 Oct 22 01:45:52 PM PDT 23 3151732636 ps
T367 /workspace/coverage/default/26.rom_ctrl_alert_test.36108259574160923671921928662232677396313276028411494989895748761690939514576 Oct 22 01:44:55 PM PDT 23 Oct 22 01:45:08 PM PDT 23 3124113076 ps
T368 /workspace/coverage/default/17.rom_ctrl_smoke.105087020188195022986374776007529115865786095750640272636063027690344694722185 Oct 22 01:43:31 PM PDT 23 Oct 22 01:44:00 PM PDT 23 6265461576 ps
T369 /workspace/coverage/default/7.rom_ctrl_stress_all.26045615063093440171213830268811880232705637033024782839030024980370137084376 Oct 22 01:44:48 PM PDT 23 Oct 22 01:45:32 PM PDT 23 9415977006 ps
T57 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.57694410891052816341556897460221060935549578719445828947477959998104156142840 Oct 22 12:31:07 PM PDT 23 Oct 22 12:31:24 PM PDT 23 3124113076 ps
T59 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.90572492382922985073651139483343547799695945216756067335317648504621083582153 Oct 22 12:31:05 PM PDT 23 Oct 22 12:31:21 PM PDT 23 3124113076 ps
T370 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.41321875240412092853987361941358893402572188152580875847971897200759142607930 Oct 22 12:27:44 PM PDT 23 Oct 22 12:27:57 PM PDT 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.43266329329983420514115224686859919305279210433496268297446041789398560963510 Oct 22 12:26:26 PM PDT 23 Oct 22 12:26:38 PM PDT 23 3124113076 ps
T372 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.70431071245992212788067822123358512601901493942579469142154799998852233516855 Oct 22 12:27:22 PM PDT 23 Oct 22 12:27:35 PM PDT 23 3124113076 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.32100026899644805264584060709851287760485213515061769278926793883834088049568 Oct 22 12:26:49 PM PDT 23 Oct 22 12:27:02 PM PDT 23 3124113076 ps
T67 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.36781598124604960544048775501269903267724309787938733393211226052536297781775 Oct 22 12:31:21 PM PDT 23 Oct 22 12:35:55 PM PDT 23 65914678386 ps
T373 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3821546088914064557149359861365353811817027176656611691806698788243169862943 Oct 22 12:23:10 PM PDT 23 Oct 22 12:23:23 PM PDT 23 3124113076 ps
T374 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.63132653169656579687170394426596046941074848596652387728719122038440432628405 Oct 22 12:32:17 PM PDT 23 Oct 22 12:33:38 PM PDT 23 3476453456 ps
T375 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.77693269812622314036810106090171132578281654876622304107723338120122875182000 Oct 22 12:31:32 PM PDT 23 Oct 22 12:31:51 PM PDT 23 3142303916 ps
T376 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.90674833994554143745148093260594181803684330433497694916777162487408351075911 Oct 22 12:31:24 PM PDT 23 Oct 22 12:32:46 PM PDT 23 3476453456 ps
T60 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.35094805534943875939677452665690278933823398489265406688899800509494241009066 Oct 22 12:26:28 PM PDT 23 Oct 22 12:26:45 PM PDT 23 3124113076 ps
T377 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.71493047858644987375511118338847953631262301515825268787335749787231205790433 Oct 22 12:31:44 PM PDT 23 Oct 22 12:31:58 PM PDT 23 3142303916 ps
T68 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.47415415524105472290939630233866596252171329571764451014991728499107779190651 Oct 22 12:26:27 PM PDT 23 Oct 22 12:31:10 PM PDT 23 65914678386 ps
T378 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.81241308052941320685046803082746851668430680477789770113578275913601739532282 Oct 22 12:32:51 PM PDT 23 Oct 22 12:33:04 PM PDT 23 3135422826 ps
T379 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.61844480407613246263462065163368122267277163795561916310051591055634214542989 Oct 22 12:31:13 PM PDT 23 Oct 22 12:31:25 PM PDT 23 3135422826 ps
T380 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.28186684325619825282825885901037186634692753289162671430269389013693513915689 Oct 22 12:26:41 PM PDT 23 Oct 22 12:26:54 PM PDT 23 3135422826 ps
T381 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.89191661894563314134859614642863430195079383742373265453409160390490715974268 Oct 22 12:31:30 PM PDT 23 Oct 22 12:31:44 PM PDT 23 3142303916 ps
T382 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.23644807827568235306480791060497122663801125156474443227546018627214092105996 Oct 22 12:27:40 PM PDT 23 Oct 22 12:27:56 PM PDT 23 3138518126 ps
T69 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.65284213989509837492133935358411195450473695287309133618526549524576514222081 Oct 22 12:31:12 PM PDT 23 Oct 22 12:35:54 PM PDT 23 65914678386 ps
T383 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.23930121890306561593912190216286005584093411651081427652254927835424785182393 Oct 22 12:31:07 PM PDT 23 Oct 22 12:31:25 PM PDT 23 3135422826 ps
T384 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.57570542108160426149504957014773608767489431206562629304996457517504307258698 Oct 22 12:31:18 PM PDT 23 Oct 22 12:31:33 PM PDT 23 3142303916 ps
T385 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.5602025825634664379980654830970734664245049480264947228281999048173155379438 Oct 22 12:25:16 PM PDT 23 Oct 22 12:25:31 PM PDT 23 3142303916 ps
T386 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.82537322971987712981433162913951189123535363356683433543350911260904142828598 Oct 22 12:31:43 PM PDT 23 Oct 22 12:31:55 PM PDT 23 3135422826 ps
T387 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.87137922348931766430797516278495748275920805539449249225198721421075788473354 Oct 22 12:30:50 PM PDT 23 Oct 22 12:31:02 PM PDT 23 3135422826 ps
T70 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.15591925937367128492114502632717576707732977105244481656774230761746920938386 Oct 22 12:31:41 PM PDT 23 Oct 22 12:36:20 PM PDT 23 65914678386 ps
T61 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.78625349114691010049465356095275900943872689089906468464717716898185470653697 Oct 22 12:31:42 PM PDT 23 Oct 22 12:31:58 PM PDT 23 3124113076 ps
T388 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.111350223978423328295566120473415032894994081895404081162049393123516738942207 Oct 22 12:31:18 PM PDT 23 Oct 22 12:31:31 PM PDT 23 3135422826 ps
T389 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.93780652033771444266415811749666262982083554458052055853822672187318651358346 Oct 22 12:23:22 PM PDT 23 Oct 22 12:23:35 PM PDT 23 3135422826 ps
T71 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.39936326405434233304439924777139131017526695996107346410508953072853823546410 Oct 22 12:31:18 PM PDT 23 Oct 22 12:36:00 PM PDT 23 65914678386 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.64953892097717801309858664427377912789014481015086588374103181531269272824551 Oct 22 12:31:18 PM PDT 23 Oct 22 12:31:34 PM PDT 23 3124113076 ps
T391 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.9466009211722527390983936520711805207394758245879459264562234556989532865692 Oct 22 12:25:37 PM PDT 23 Oct 22 12:25:49 PM PDT 23 3124113076 ps
T392 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.72700568308006551907566853746400955058431432683415179663761726157826478293736 Oct 22 12:31:09 PM PDT 23 Oct 22 12:31:24 PM PDT 23 3142303916 ps
T393 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.14904540411539086803393871307486008647158217335619079654430076834723795973676 Oct 22 12:30:56 PM PDT 23 Oct 22 12:31:09 PM PDT 23 3124113076 ps
T394 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.112363037827029947260537951347758214884738782770164888846979789309088886071303 Oct 22 12:28:24 PM PDT 23 Oct 22 12:28:45 PM PDT 23 3138518126 ps
T72 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.37323017307246735977004305421005548964937360909092182306258925150083101750323 Oct 22 12:24:56 PM PDT 23 Oct 22 12:29:44 PM PDT 23 65914678386 ps
T395 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.103915948413156180517828657010232858677918115186433632896833440267511957423633 Oct 22 12:31:51 PM PDT 23 Oct 22 12:36:27 PM PDT 23 65914678386 ps
T396 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.38769960772891061182895901824138686473263889345107864255915531526892462080073 Oct 22 12:31:31 PM PDT 23 Oct 22 12:32:52 PM PDT 23 3476453456 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.50323400534103639302234758030993927626271023882837987147886137411765659750450 Oct 22 12:32:49 PM PDT 23 Oct 22 12:33:03 PM PDT 23 3142303916 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.57750918280806898497824631900752783451951727126233719188656763490389562953854 Oct 22 12:25:35 PM PDT 23 Oct 22 12:25:48 PM PDT 23 3124113076 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.70262191518506516004258398392933484042112648456095413609327631976178679103745 Oct 22 12:31:21 PM PDT 23 Oct 22 12:31:44 PM PDT 23 3124113076 ps
T400 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3822496896228761441865391213651644508782472047594309140223854109774550258926 Oct 22 12:25:41 PM PDT 23 Oct 22 12:25:54 PM PDT 23 3124113076 ps
T401 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.59583029743124747201445968043444899499690533504638036064335555924685836770770 Oct 22 12:31:45 PM PDT 23 Oct 22 12:32:00 PM PDT 23 3142303916 ps
T402 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.65219149515140713026929944498851065184535586042001022903333306733723474458989 Oct 22 12:31:11 PM PDT 23 Oct 22 12:31:25 PM PDT 23 3142303916 ps
T403 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.14583129027442057537221100131775927833089264636275262022766887721581041552825 Oct 22 12:22:40 PM PDT 23 Oct 22 12:22:57 PM PDT 23 3124113076 ps
T404 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.57080070469989436242703766765549493476251204823560281618974838247472618905840 Oct 22 12:25:15 PM PDT 23 Oct 22 12:25:28 PM PDT 23 3124113076 ps
T405 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.27397916012168106391910609133852081076654953023975413263179485597674088174569 Oct 22 12:31:25 PM PDT 23 Oct 22 12:36:07 PM PDT 23 65914678386 ps
T86 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3303386641343762211020842018734415969195527915022155491402760582620022680427 Oct 22 12:26:21 PM PDT 23 Oct 22 12:26:34 PM PDT 23 3124113076 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.64711595447368353132018194993494849439553496587747952367556771133817485850709 Oct 22 12:23:41 PM PDT 23 Oct 22 12:23:54 PM PDT 23 3124113076 ps
T406 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.83952324457938697937675572359497261373473254593600422268968831828808375812658 Oct 22 12:30:52 PM PDT 23 Oct 22 12:31:04 PM PDT 23 3124113076 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.28263754769901169066929167943878506676981847142167033988661266536703905307775 Oct 22 12:27:17 PM PDT 23 Oct 22 12:27:30 PM PDT 23 3124113076 ps
T407 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.102812695246781026805994657835187961766304863306877778939193175744001461748017 Oct 22 12:25:20 PM PDT 23 Oct 22 12:25:33 PM PDT 23 3135422826 ps
T408 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.11559722961602213128280183778057434670948251735404163796158686490339673117671 Oct 22 12:27:37 PM PDT 23 Oct 22 12:32:20 PM PDT 23 65914678386 ps
T409 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.110633556196020267812519416200931472288485676493912689599921913503809546306184 Oct 22 12:23:56 PM PDT 23 Oct 22 12:24:14 PM PDT 23 3124113076 ps
T410 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.19324197624959031573941488620298895256095849660103990487425857385039291951322 Oct 22 12:24:33 PM PDT 23 Oct 22 12:24:46 PM PDT 23 3124113076 ps
T411 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.91312895410737036451292597653466626578645660572390795743590590553697110065017 Oct 22 12:32:11 PM PDT 23 Oct 22 12:32:23 PM PDT 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.95529967632527628183271909436153529057697251932342438522473795904693057881025 Oct 22 12:31:15 PM PDT 23 Oct 22 12:35:49 PM PDT 23 65914678386 ps
T413 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.38167130456311184524113309096408227827653954217880549942258483464354225112146 Oct 22 12:23:56 PM PDT 23 Oct 22 12:24:14 PM PDT 23 3124113076 ps
T414 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.55044691085383187617725607545620071109350624366287499659438583447105285710263 Oct 22 12:32:26 PM PDT 23 Oct 22 12:32:42 PM PDT 23 3124113076 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.5389380004846105790607193443890238869625491893808955994163442787511814071849 Oct 22 12:30:51 PM PDT 23 Oct 22 12:31:04 PM PDT 23 3135422826 ps
T416 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.16043971309988628115605156500261453918823825507869208363377102188029618529214 Oct 22 12:25:20 PM PDT 23 Oct 22 12:26:40 PM PDT 23 3476453456 ps
T417 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.14192993759232769757162742246809209467300809049528574316989616659040834242141 Oct 22 12:31:13 PM PDT 23 Oct 22 12:31:29 PM PDT 23 3124113076 ps
T418 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.94929651995714663519886404046615004352359548113613671270299080726339636369817 Oct 22 12:26:41 PM PDT 23 Oct 22 12:26:56 PM PDT 23 3142303916 ps
T419 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.41586915471883892890778658070612312587330546423284572926279962689056891261079 Oct 22 12:24:41 PM PDT 23 Oct 22 12:29:27 PM PDT 23 65914678386 ps
T420 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.99351597142275496524217593988002104532322800984305561930516897971991548261837 Oct 22 12:31:14 PM PDT 23 Oct 22 12:31:27 PM PDT 23 3135422826 ps
T421 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.12871616196599753914868505381069686079523541227117440516363435083480086708154 Oct 22 12:23:37 PM PDT 23 Oct 22 12:23:54 PM PDT 23 3124113076 ps
T422 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.28059317374699208293736822440560243569225259925942115213396122886457459193110 Oct 22 12:31:36 PM PDT 23 Oct 22 12:31:49 PM PDT 23 3124113076 ps
T423 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.106808209727664828735043536337697606629284292378562125240185454346071056279675 Oct 22 12:27:16 PM PDT 23 Oct 22 12:27:28 PM PDT 23 3135422826 ps
T424 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.5979593651550499140128857003492726138578568344620720877660849689735567569853 Oct 22 12:25:31 PM PDT 23 Oct 22 12:25:46 PM PDT 23 3142303916 ps
T425 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.30454741413174162830933963941252199599258396935301386414064090390004735836715 Oct 22 12:27:43 PM PDT 23 Oct 22 12:32:25 PM PDT 23 65914678386 ps
T426 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3132515946212386294055722570895353768584640610413607913024690521684940731023 Oct 22 12:31:28 PM PDT 23 Oct 22 12:31:41 PM PDT 23 3135422826 ps
T427 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.107131889867464890456531041744664100666850369258183545457721201323304068270072 Oct 22 12:25:20 PM PDT 23 Oct 22 12:25:33 PM PDT 23 3124113076 ps
T428 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.72259527716321580364944874313157336238168173350607799662980515702047849810606 Oct 22 12:31:11 PM PDT 23 Oct 22 12:31:27 PM PDT 23 3124113076 ps
T429 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.91082946034391066539576043862492502901204748125332746187740268550529487128344 Oct 22 12:30:35 PM PDT 23 Oct 22 12:30:52 PM PDT 23 3124113076 ps
T430 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.114052777453743327658604508155083398604130977146429477754505305712622691930837 Oct 22 12:31:56 PM PDT 23 Oct 22 12:36:43 PM PDT 23 65914678386 ps
T431 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.68609579534349574325254426360016470812200724432020839498146872651227233634936 Oct 22 12:31:27 PM PDT 23 Oct 22 12:36:09 PM PDT 23 65914678386 ps
T432 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.46855978187230607689964825016173992339274185185091845941547350183316451901676 Oct 22 12:31:02 PM PDT 23 Oct 22 12:31:15 PM PDT 23 3124113076 ps
T433 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.103701720522690685787332088024155228572156043511651286189082340629743522425801 Oct 22 12:22:36 PM PDT 23 Oct 22 12:24:00 PM PDT 23 3476453456 ps
T434 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.87263877611327976735944387465455990435431811942303311092881140199169563165789 Oct 22 12:27:48 PM PDT 23 Oct 22 12:32:28 PM PDT 23 65914678386 ps
T435 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.36673615885710597686066383930466308975222582143729161318812463099803605826796 Oct 22 12:31:25 PM PDT 23 Oct 22 12:31:38 PM PDT 23 3135422826 ps
T436 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.57702599038420415714662957211829078600067860477193771624444871246995196278462 Oct 22 12:21:50 PM PDT 23 Oct 22 12:22:03 PM PDT 23 3124113076 ps
T437 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.5166010312979632025935889684079636162600157317978121286192138449150338315895 Oct 22 12:28:12 PM PDT 23 Oct 22 12:28:24 PM PDT 23 3135422826 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.98173326365236973909844892214282795916314853746757120153554895751616631258774 Oct 22 12:30:57 PM PDT 23 Oct 22 12:32:18 PM PDT 23 3476453456 ps
T439 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.5233193232348060546221627965730047649901186681098665041854092979765246414129 Oct 22 12:31:04 PM PDT 23 Oct 22 12:32:25 PM PDT 23 3476453456 ps
T440 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.51606217191036328683261221086540384016730319885350960384442701828946553481347 Oct 22 12:30:41 PM PDT 23 Oct 22 12:35:26 PM PDT 23 65914678386 ps
T441 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.96069767777379929740219756759943813867105727915029932040937184767385443723244 Oct 22 12:23:39 PM PDT 23 Oct 22 12:23:52 PM PDT 23 3124113076 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.86935114074757771652286285891667489488159646268996518252875623288684952798026 Oct 22 12:28:03 PM PDT 23 Oct 22 12:28:16 PM PDT 23 3124113076 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.36489862215927813608407771787737913458153929574895590856532431030219807863157 Oct 22 12:31:37 PM PDT 23 Oct 22 12:31:49 PM PDT 23 3124113076 ps
T444 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.25830509226823368413880391444226671630758520840553397686869966678597789333000 Oct 22 12:26:31 PM PDT 23 Oct 22 12:26:44 PM PDT 23 3135422826 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.41049438375069829859129003711896780153727282196253899855009063919329056631213 Oct 22 12:31:00 PM PDT 23 Oct 22 12:32:22 PM PDT 23 3476453456 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.108319229827181404188231168623266926426668319329606393776303720013558965728947 Oct 22 12:30:58 PM PDT 23 Oct 22 12:31:15 PM PDT 23 3124113076 ps
T447 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.72212688355288426115804295030372324046840593728379086680576082405945501546858 Oct 22 12:31:29 PM PDT 23 Oct 22 12:31:43 PM PDT 23 3142303916 ps
T448 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.23340538629856171616548198115060057618461947700139019628154403949423868382613 Oct 22 12:24:30 PM PDT 23 Oct 22 12:24:43 PM PDT 23 3135422826 ps
T449 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.84700626867173320420668158445363850524255970020029698214408794560637779709861 Oct 22 12:31:23 PM PDT 23 Oct 22 12:31:35 PM PDT 23 3124113076 ps
T450 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.53596979681315528429850176725436291770838681682945832836396707631545882627892 Oct 22 12:25:11 PM PDT 23 Oct 22 12:25:24 PM PDT 23 3124113076 ps

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.30997811420981129091703760558428257539785943174197231334486552753601857220387
Short name T23
Test name
Test status
Simulation time 65914678386 ps
CPU time 276.04 seconds
Started Oct 22 12:27:54 PM PDT 23
Finished Oct 22 12:32:41 PM PDT 23
Peak memory 218820 kb
Host smart-2256dfef-9d81-4f74-80c1-7687631dc383
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30997811420981129091703760558428257539785943174197231334486552753601857220387 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.30997811420981129091703760558428257539785943174197231334
486552753601857220387
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.84010781796474636496673857246969114623575949074482890920209153904479094485744
Short name T2
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.7 seconds
Started Oct 22 01:44:49 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 212912 kb
Host smart-9f49b2d1-cd17-497f-9d23-e49319c6553c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840107817964746364966738572469691146235759490744828909202091539
04479094485744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.84010781796474636496673857246969114623575949074482
890920209153904479094485744
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.97251969497023695185650402387159448194373760609564768353278712558538783763123
Short name T18
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.87 seconds
Started Oct 22 12:26:50 PM PDT 23
Finished Oct 22 12:27:03 PM PDT 23
Peak memory 210684 kb
Host smart-89a44c5f-5271-49c1-a52e-a9c6d2ca87d2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97251969497023695185650402387159448194373760609564768353278712558538783763123 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.9725196949702369518565040238715944819437376060956476835327
8712558538783763123
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.83981060380405183168178424178541835779065937928119200228476668981485777280024
Short name T31
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.68 seconds
Started Oct 22 12:28:26 PM PDT 23
Finished Oct 22 12:28:42 PM PDT 23
Peak memory 218920 kb
Host smart-713f65b0-db39-47b3-b11a-5b30d82559f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83981060380405183168178424178541835779065937928119200228476668981485777280024 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.83981060380405183168178424178541835779065937928119200228476668981485777280024
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.51628649342080825989868237184925885641527355354628663039491627391834263534441
Short name T46
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.34 seconds
Started Oct 22 12:24:51 PM PDT 23
Finished Oct 22 12:26:13 PM PDT 23
Peak memory 210828 kb
Host smart-b6e86678-6b93-4184-8ab9-620225aabd79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51628649342080825989868237184925885641527355354628663039491627391834263534441 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.51628649342080825989868237184925885641527355354628663039491627391834263534441
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.23306023812638158673719951956918562122690543548208941647393611961907050837759
Short name T16
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.79 seconds
Started Oct 22 01:43:38 PM PDT 23
Finished Oct 22 01:49:22 PM PDT 23
Peak memory 237728 kb
Host smart-b8faffa5-0ab5-48c6-94fe-ca1ac45749ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23306023812638158673719951956918562122690543548208941647393611961907050837759 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.2330602381263815867371995195691856212269054354820894164739
3611961907050837759
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.61844480407613246263462065163368122267277163795561916310051591055634214542989
Short name T379
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.3 seconds
Started Oct 22 12:31:13 PM PDT 23
Finished Oct 22 12:31:25 PM PDT 23
Peak memory 213292 kb
Host smart-653ae560-896e-4a02-9975-1e293e970e95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6184448040761324626346206516336812226727716
3795561916310051591055634214542989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.618444804076
13246263462065163368122267277163795561916310051591055634214542989
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.37626605522224399842225317903266129202145928466461395173592120742100723242260
Short name T8
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.92 seconds
Started Oct 22 01:43:23 PM PDT 23
Finished Oct 22 01:45:19 PM PDT 23
Peak memory 236808 kb
Host smart-fe40dc58-f7e5-48b4-872a-69c7a7fd90d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37626605522224399842225317903266129202145928466461395173592120742100723242260 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.37626605522224399842225317903266129202145928466461395173592120742100723242260
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.69686492494081087453525406823962136391826543530738088530303750375149585218072
Short name T77
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.85 seconds
Started Oct 22 12:30:54 PM PDT 23
Finished Oct 22 12:31:08 PM PDT 23
Peak memory 210672 kb
Host smart-1baa2dfe-2ea9-43a4-8d0b-453d185c5071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69686492494081087453525406823962136391826543530738088530303750375149585218072
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.69686492494081087453525406823962136391826543530738088
530303750375149585218072
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.57702599038420415714662957211829078600067860477193771624444871246995196278462
Short name T436
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.72 seconds
Started Oct 22 12:21:50 PM PDT 23
Finished Oct 22 12:22:03 PM PDT 23
Peak memory 210660 kb
Host smart-b98dbbc4-b1a0-45c5-b826-bd96953af787
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57702599038420415714662957211829078600067860477193771624444871246995196278462 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.57702599038420415714662957211829078600067860477193771624444871246995196278462
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.956022302945356060362986758254922531813454430704685242455668361701722690269
Short name T58
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.57 seconds
Started Oct 22 12:23:11 PM PDT 23
Finished Oct 22 12:23:24 PM PDT 23
Peak memory 210680 kb
Host smart-5c05ddcf-3d84-405f-a194-660a70cd0efa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956022302945356060362986758254922531813454430704685242455668361701722690269 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.956022302945356060362986758254922531813454430704685242455668361701722690269
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.31787240394975551789974187772773923371755883894365487347437400921072512634853
Short name T64
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:31:31 PM PDT 23
Peak memory 210712 kb
Host smart-5ed6ac2b-85f6-4e80-85e0-740652f954d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787240394975551789974187772773923371755883894365487347437400921072512634853 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.31787240394975551789974187772773923371755883894365487347437400921072512634853
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.104280848986256742025001650139671803807453334000066716871024799004402230846565
Short name T115
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.37 seconds
Started Oct 22 01:43:20 PM PDT 23
Finished Oct 22 01:43:45 PM PDT 23
Peak memory 211640 kb
Host smart-6f1c46ee-1f75-41a8-92dc-d0ed3a08c998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104280848986256742025001650139671803807453334000066716871024799004402230846565 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rom_ctrl_kmac_err_chk.104280848986256742025001650139671803807453334000066716871024799004402230846565
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.39777588111192541887986491738741550551448422423892214915544610055061754518923
Short name T116
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 22 01:44:40 PM PDT 23
Finished Oct 22 01:44:53 PM PDT 23
Peak memory 211228 kb
Host smart-36ae542f-0259-4a52-a0a3-1faa78b9b16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39777588111192541887986491738741550551448422423892214915544610055061754518923 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.39777588111192541887986491738741550551448422423892214915544610055061754518923
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.22737832769501651249790027814522013326060531248866906383082937949236062229291
Short name T10
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 22 01:43:20 PM PDT 23
Finished Oct 22 01:43:33 PM PDT 23
Peak memory 211180 kb
Host smart-f4026b09-da34-4ade-872f-069e6c1d6954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22737832769501651249790027814522013326060531248866906383082937949236062229291 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.22737832769501651249790027814522013326060531248866906383082937949236062229291
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.62529401128764614699052015221744062434633907320103777820652589856383100733103
Short name T104
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.15 seconds
Started Oct 22 01:45:04 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 212856 kb
Host smart-691c977f-3118-4de7-b8f5-97633719f99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62529401128764614699052015221744062434633907320103777820652589856383100733103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.rom_ctrl_smoke.62529401128764614699052015221744062434633907320103777820652589856383100733103
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.23644807827568235306480791060497122663801125156474443227546018627214092105996
Short name T382
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.36 seconds
Started Oct 22 12:27:40 PM PDT 23
Finished Oct 22 12:27:56 PM PDT 23
Peak memory 210464 kb
Host smart-cc8afc4a-50ca-4c43-9a91-01d0a1c3e360
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644807827568235306480791060497122663801125156474443227546018627214092105996 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.23644807827568235306480791060497122663801125156474443227546018627214092105996
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.102812695246781026805994657835187961766304863306877778939193175744001461748017
Short name T407
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.17 seconds
Started Oct 22 12:25:20 PM PDT 23
Finished Oct 22 12:25:33 PM PDT 23
Peak memory 211676 kb
Host smart-61734297-0adb-464d-a583-c9c91a2c95f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028126952467810268059946578351879617663048
63306877778939193175744001461748017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.102812695246
781026805994657835187961766304863306877778939193175744001461748017
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3821546088914064557149359861365353811817027176656611691806698788243169862943
Short name T373
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 22 12:23:10 PM PDT 23
Finished Oct 22 12:23:23 PM PDT 23
Peak memory 210676 kb
Host smart-ccaff826-a68c-41a1-acd2-00c3c55ebdbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821546088914064557149359861365353811817027176656611691806698788243169862943 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3821546088914064557149359861365353811817027176656611691806698788243169862943
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.73820409396272675783519796138768583791331793451480625229373792157186253498120
Short name T89
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 22 12:25:29 PM PDT 23
Finished Oct 22 12:25:42 PM PDT 23
Peak memory 210660 kb
Host smart-a0dcd2e6-c461-4c1a-8088-87d0275c6345
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73820409396272675783519796138768583791331793451480625229373792157186253498120 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.7382040939627267578351979613876858379133179345148062522937
3792157186253498120
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.19324197624959031573941488620298895256095849660103990487425857385039291951322
Short name T410
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.65 seconds
Started Oct 22 12:24:33 PM PDT 23
Finished Oct 22 12:24:46 PM PDT 23
Peak memory 210860 kb
Host smart-8c75fc5a-461b-4e32-b094-18b7947bd2e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19324197624959031573941488620298895256095849660103990487425857385039291951322 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.19324197624959031573941488620298895256095849660103990487425857385039291951322
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.64532392773114626429655419432612067045493682949046807647289223740694028586044
Short name T33
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.1 seconds
Started Oct 22 12:21:58 PM PDT 23
Finished Oct 22 12:26:41 PM PDT 23
Peak memory 218812 kb
Host smart-e373dbfc-93e4-4c49-921b-768fb3972079
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64532392773114626429655419432612067045493682949046807647289223740694028586044 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.64532392773114626429655419432612067045493682949046807647
289223740694028586044
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.94929651995714663519886404046615004352359548113613671270299080726339636369817
Short name T418
Test name
Test status
Simulation time 3142303916 ps
CPU time 14 seconds
Started Oct 22 12:26:41 PM PDT 23
Finished Oct 22 12:26:56 PM PDT 23
Peak memory 210652 kb
Host smart-5a3b7075-2c76-4ac4-a373-c41013b9ceb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94929651995714663519886404046615004352359548113613671270299080726339636369817
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.949296519957146635198864040466150043523595481136136712
70299080726339636369817
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.53596979681315528429850176725436291770838681682945832836396707631545882627892
Short name T450
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Oct 22 12:25:11 PM PDT 23
Finished Oct 22 12:25:24 PM PDT 23
Peak memory 210648 kb
Host smart-623efb5c-64cc-47bd-8a3e-37fbe1753e6f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53596979681315528429850176725436291770838681682945832836396707631545882627892 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.53596979681315528429850176725436291770838681682945832836396707631545882627892
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.32100026899644805264584060709851287760485213515061769278926793883834088049568
Short name T83
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.11 seconds
Started Oct 22 12:26:49 PM PDT 23
Finished Oct 22 12:27:02 PM PDT 23
Peak memory 210688 kb
Host smart-01cc3f9a-3eab-4daa-ad0c-eb38c51fbc57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100026899644805264584060709851287760485213515061769278926793883834088049568 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.32100026899644805264584060709851287760485213515061769278926793883834088049568
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.62711722989754499621175968993735624616868438648107505852313458739870583376600
Short name T87
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.68 seconds
Started Oct 22 12:21:41 PM PDT 23
Finished Oct 22 12:21:56 PM PDT 23
Peak memory 211048 kb
Host smart-46933c2e-7eba-4193-b9a9-3a5dc542a8ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62711722989754499621175968993735624616868438648107505852313458739870583376600 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.62711722989754499621175968993735624616868438648107505852313458739870583376600
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.5166010312979632025935889684079636162600157317978121286192138449150338315895
Short name T437
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.07 seconds
Started Oct 22 12:28:12 PM PDT 23
Finished Oct 22 12:28:24 PM PDT 23
Peak memory 213320 kb
Host smart-ee43d556-575a-446c-825b-59de511efbc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5166010312979632025935889684079636162600157
317978121286192138449150338315895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.51660103129796
32025935889684079636162600157317978121286192138449150338315895
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.9466009211722527390983936520711805207394758245879459264562234556989532865692
Short name T391
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.92 seconds
Started Oct 22 12:25:37 PM PDT 23
Finished Oct 22 12:25:49 PM PDT 23
Peak memory 210656 kb
Host smart-208a3b94-30c5-4487-89de-ed67c06990ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9466009211722527390983936520711805207394758245879459264562234556989532865692 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.9466009211722527390983936520711805207394758245879459264562234556989532865692
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.107131889867464890456531041744664100666850369258183545457721201323304068270072
Short name T427
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 22 12:25:20 PM PDT 23
Finished Oct 22 12:25:33 PM PDT 23
Peak memory 209184 kb
Host smart-109b3d7a-994f-4e86-902a-0314418ccc9c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107131889867464890456531041744664100666850369258183545457721201323304068270072 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.107131889867464890456531041744664100666850369258183545457721201323304068270072
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.87263877611327976735944387465455990435431811942303311092881140199169563165789
Short name T434
Test name
Test status
Simulation time 65914678386 ps
CPU time 279.97 seconds
Started Oct 22 12:27:48 PM PDT 23
Finished Oct 22 12:32:28 PM PDT 23
Peak memory 218800 kb
Host smart-408db76a-c2ad-4587-b1b1-a510da167493
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87263877611327976735944387465455990435431811942303311092881140199169563165789 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.87263877611327976735944387465455990435431811942303311092
881140199169563165789
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.5602025825634664379980654830970734664245049480264947228281999048173155379438
Short name T385
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.13 seconds
Started Oct 22 12:25:16 PM PDT 23
Finished Oct 22 12:25:31 PM PDT 23
Peak memory 210340 kb
Host smart-dd6b7451-cbf6-40ee-a5fc-b7a52758527d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5602025825634664379980654830970734664245049480264947228281999048173155379438 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.5602025825634664379980654830970734664245049480264947228
281999048173155379438
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.84110709028614397341961726094658919267537795625954087798648834385352788172780
Short name T45
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.53 seconds
Started Oct 22 12:21:40 PM PDT 23
Finished Oct 22 12:21:57 PM PDT 23
Peak memory 219304 kb
Host smart-11aa1f20-e86d-40dc-9281-66491677a5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84110709028614397341961726094658919267537795625954087798648834385352788172780 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.84110709028614397341961726094658919267537795625954087798648834385352788172780
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.63221808089626572379814196269775588029417378835917650798114665848294236782548
Short name T52
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.42 seconds
Started Oct 22 12:26:33 PM PDT 23
Finished Oct 22 12:27:56 PM PDT 23
Peak memory 210900 kb
Host smart-42c0b340-d0ba-40cc-925e-2aee216ef659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63221808089626572379814196269775588029417378835917650798114665848294236782548 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.63221808089626572379814196269775588029417378835917650798114665848294236782548
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.28059317374699208293736822440560243569225259925942115213396122886457459193110
Short name T422
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 22 12:31:36 PM PDT 23
Finished Oct 22 12:31:49 PM PDT 23
Peak memory 210672 kb
Host smart-fc0cdc44-917f-4ce7-9d4e-22269ca4cc93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28059317374699208293736822440560243569225259925942115213396122886457459193110 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.28059317374699208293736822440560243569225259925942115213396122886457459193110
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.39936326405434233304439924777139131017526695996107346410508953072853823546410
Short name T71
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.68 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:36:00 PM PDT 23
Peak memory 218848 kb
Host smart-f70c74cf-d0c5-4e28-96aa-8912bfc7bb53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39936326405434233304439924777139131017526695996107346410508953072853823546410 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.3993632640543423330443992477713913101752669599610734641
0508953072853823546410
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.55044691085383187617725607545620071109350624366287499659438583447105285710263
Short name T414
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.58 seconds
Started Oct 22 12:32:26 PM PDT 23
Finished Oct 22 12:32:42 PM PDT 23
Peak memory 218920 kb
Host smart-a96ba4fe-718a-49fc-b25c-848c6dda77bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55044691085383187617725607545620071109350624366287499659438583447105285710263 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.55044691085383187617725607545620071109350624366287499659438583447105285710263
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.41049438375069829859129003711896780153727282196253899855009063919329056631213
Short name T445
Test name
Test status
Simulation time 3476453456 ps
CPU time 82 seconds
Started Oct 22 12:31:00 PM PDT 23
Finished Oct 22 12:32:22 PM PDT 23
Peak memory 210868 kb
Host smart-95137b45-972f-4cce-9d6c-1d3a197943a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049438375069829859129003711896780153727282196253899855009063919329056631213 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.41049438375069829859129003711896780153727282196253899855009063919329056631213
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.87137922348931766430797516278495748275920805539449249225198721421075788473354
Short name T387
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.3 seconds
Started Oct 22 12:30:50 PM PDT 23
Finished Oct 22 12:31:02 PM PDT 23
Peak memory 213300 kb
Host smart-9bbc31f5-8d8c-41bd-8a1d-c6ebc112f790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8713792234893176643079751627849574827592080
5539449249225198721421075788473354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.871379223489
31766430797516278495748275920805539449249225198721421075788473354
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.83952324457938697937675572359497261373473254593600422268968831828808375812658
Short name T406
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.95 seconds
Started Oct 22 12:30:52 PM PDT 23
Finished Oct 22 12:31:04 PM PDT 23
Peak memory 210692 kb
Host smart-46214b70-d4e5-4e91-80bb-3e20dc9c746a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83952324457938697937675572359497261373473254593600422268968831828808375812658 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.83952324457938697937675572359497261373473254593600422268968831828808375812658
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.36781598124604960544048775501269903267724309787938733393211226052536297781775
Short name T67
Test name
Test status
Simulation time 65914678386 ps
CPU time 273.56 seconds
Started Oct 22 12:31:21 PM PDT 23
Finished Oct 22 12:35:55 PM PDT 23
Peak memory 218620 kb
Host smart-c96c7c75-34c8-4a63-aa72-672da39d18ab
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36781598124604960544048775501269903267724309787938733393211226052536297781775 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3678159812460496054404877550126990326772430978793873339
3211226052536297781775
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.72212688355288426115804295030372324046840593728379086680576082405945501546858
Short name T447
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.04 seconds
Started Oct 22 12:31:29 PM PDT 23
Finished Oct 22 12:31:43 PM PDT 23
Peak memory 210680 kb
Host smart-9aea451d-e819-47c3-acb6-46f78603cca5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72212688355288426115804295030372324046840593728379086680576082405945501546858
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.72212688355288426115804295030372324046840593728379086
680576082405945501546858
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.74597826226717174409200210308491459256649271185532435907910459051389220138620
Short name T53
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.98 seconds
Started Oct 22 12:32:02 PM PDT 23
Finished Oct 22 12:32:18 PM PDT 23
Peak memory 218912 kb
Host smart-eddf77c2-d703-4621-9545-b1b7dc092b03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74597826226717174409200210308491459256649271185532435907910459051389220138620 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.74597826226717174409200210308491459256649271185532435907910459051389220138620
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.50500719781392809879252214225437686531850675146601566793525550542867211916643
Short name T47
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.74 seconds
Started Oct 22 12:31:10 PM PDT 23
Finished Oct 22 12:32:31 PM PDT 23
Peak memory 210896 kb
Host smart-c0500fb8-e0f0-4c82-b680-1c8917dede0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50500719781392809879252214225437686531850675146601566793525550542867211916643 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.50500719781392809879252214225437686531850675146601566793525550542867211916643
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.81241308052941320685046803082746851668430680477789770113578275913601739532282
Short name T378
Test name
Test status
Simulation time 3135422826 ps
CPU time 11.92 seconds
Started Oct 22 12:32:51 PM PDT 23
Finished Oct 22 12:33:04 PM PDT 23
Peak memory 212112 kb
Host smart-25a493fc-3390-4efe-ba4e-2636e005b787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8124130805294132068504680308274685166843068
0477789770113578275913601739532282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.812413080529
41320685046803082746851668430680477789770113578275913601739532282
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.91312895410737036451292597653466626578645660572390795743590590553697110065017
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.84 seconds
Started Oct 22 12:32:11 PM PDT 23
Finished Oct 22 12:32:23 PM PDT 23
Peak memory 210468 kb
Host smart-a1a11c1b-e18e-4c0e-8c81-12e5a0856a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91312895410737036451292597653466626578645660572390795743590590553697110065017 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.91312895410737036451292597653466626578645660572390795743590590553697110065017
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.103915948413156180517828657010232858677918115186433632896833440267511957423633
Short name T395
Test name
Test status
Simulation time 65914678386 ps
CPU time 275.45 seconds
Started Oct 22 12:31:51 PM PDT 23
Finished Oct 22 12:36:27 PM PDT 23
Peak memory 218916 kb
Host smart-ffb7d99f-74a5-4ef5-aa03-1bc5c9c68583
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103915948413156180517828657010232858677918115186433632896833440267511957423633 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.103915948413156180517828657010232858677918115186433632
896833440267511957423633
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.88405280798114771803114608306618599967875645764833273693437805566013211915423
Short name T73
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.09 seconds
Started Oct 22 12:30:49 PM PDT 23
Finished Oct 22 12:31:03 PM PDT 23
Peak memory 210672 kb
Host smart-9b6c45e9-f7c0-4726-aff7-a99814fb750e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88405280798114771803114608306618599967875645764833273693437805566013211915423
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.88405280798114771803114608306618599967875645764833273
693437805566013211915423
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.91082946034391066539576043862492502901204748125332746187740268550529487128344
Short name T429
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.48 seconds
Started Oct 22 12:30:35 PM PDT 23
Finished Oct 22 12:30:52 PM PDT 23
Peak memory 219020 kb
Host smart-5d9c7a9e-f2ec-4afa-b625-a9fd9d531b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91082946034391066539576043862492502901204748125332746187740268550529487128344 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.91082946034391066539576043862492502901204748125332746187740268550529487128344
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.98173326365236973909844892214282795916314853746757120153554895751616631258774
Short name T438
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.69 seconds
Started Oct 22 12:30:57 PM PDT 23
Finished Oct 22 12:32:18 PM PDT 23
Peak memory 210904 kb
Host smart-0dff6c67-9674-40de-a140-5e85611a226e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98173326365236973909844892214282795916314853746757120153554895751616631258774 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.98173326365236973909844892214282795916314853746757120153554895751616631258774
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.87734556558128841519829350191367989980554130599135351660857158903675195815514
Short name T49
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.03 seconds
Started Oct 22 12:31:16 PM PDT 23
Finished Oct 22 12:31:28 PM PDT 23
Peak memory 212568 kb
Host smart-559e0f04-193a-4962-867b-6b11a304ef63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8773455655812884151982935019136798998055413
0599135351660857158903675195815514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.877345565581
28841519829350191367989980554130599135351660857158903675195815514
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.65284213989509837492133935358411195450473695287309133618526549524576514222081
Short name T69
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.76 seconds
Started Oct 22 12:31:12 PM PDT 23
Finished Oct 22 12:35:54 PM PDT 23
Peak memory 218808 kb
Host smart-072a961e-2b1d-48da-954a-51eba31617ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65284213989509837492133935358411195450473695287309133618526549524576514222081 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.6528421398950983749213393535841119545047369528730913361
8526549524576514222081
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.65219149515140713026929944498851065184535586042001022903333306733723474458989
Short name T402
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.65 seconds
Started Oct 22 12:31:11 PM PDT 23
Finished Oct 22 12:31:25 PM PDT 23
Peak memory 210664 kb
Host smart-fd9063ca-db41-41a2-adc2-dbf15a59e0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65219149515140713026929944498851065184535586042001022903333306733723474458989
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.65219149515140713026929944498851065184535586042001022
903333306733723474458989
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.90572492382922985073651139483343547799695945216756067335317648504621083582153
Short name T59
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.02 seconds
Started Oct 22 12:31:05 PM PDT 23
Finished Oct 22 12:31:21 PM PDT 23
Peak memory 219052 kb
Host smart-56853019-12f8-4ef2-98bb-c0b51165b924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90572492382922985073651139483343547799695945216756067335317648504621083582153 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.90572492382922985073651139483343547799695945216756067335317648504621083582153
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.90674833994554143745148093260594181803684330433497694916777162487408351075911
Short name T376
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.24 seconds
Started Oct 22 12:31:24 PM PDT 23
Finished Oct 22 12:32:46 PM PDT 23
Peak memory 210876 kb
Host smart-75e8bb3d-a433-4e70-ab2f-edab817acf51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90674833994554143745148093260594181803684330433497694916777162487408351075911 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.90674833994554143745148093260594181803684330433497694916777162487408351075911
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.111350223978423328295566120473415032894994081895404081162049393123516738942207
Short name T388
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.17 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:31:31 PM PDT 23
Peak memory 213300 kb
Host smart-688bcd96-4bfd-4e68-9241-50892bc1b93c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113502239784233282955661204734150328949940
81895404081162049393123516738942207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.11135022397
8423328295566120473415032894994081895404081162049393123516738942207
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.70262191518506516004258398392933484042112648456095413609327631976178679103745
Short name T399
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 22 12:31:21 PM PDT 23
Finished Oct 22 12:31:44 PM PDT 23
Peak memory 210692 kb
Host smart-2e28986d-8ef2-4a83-812f-12ebf5b3ac04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70262191518506516004258398392933484042112648456095413609327631976178679103745 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.70262191518506516004258398392933484042112648456095413609327631976178679103745
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.114052777453743327658604508155083398604130977146429477754505305712622691930837
Short name T430
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.53 seconds
Started Oct 22 12:31:56 PM PDT 23
Finished Oct 22 12:36:43 PM PDT 23
Peak memory 218840 kb
Host smart-1ea37d9a-2277-4c80-b916-d54321e7adf7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114052777453743327658604508155083398604130977146429477754505305712622691930837 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.114052777453743327658604508155083398604130977146429477
754505305712622691930837
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.71493047858644987375511118338847953631262301515825268787335749787231205790433
Short name T377
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.18 seconds
Started Oct 22 12:31:44 PM PDT 23
Finished Oct 22 12:31:58 PM PDT 23
Peak memory 210704 kb
Host smart-0dcb6313-c6c4-47dc-96c2-f12762b22e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71493047858644987375511118338847953631262301515825268787335749787231205790433
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.71493047858644987375511118338847953631262301515825268
787335749787231205790433
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.78625349114691010049465356095275900943872689089906468464717716898185470653697
Short name T61
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.65 seconds
Started Oct 22 12:31:42 PM PDT 23
Finished Oct 22 12:31:58 PM PDT 23
Peak memory 218916 kb
Host smart-3c336908-ef8e-4784-8d6b-1592a4157823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78625349114691010049465356095275900943872689089906468464717716898185470653697 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.78625349114691010049465356095275900943872689089906468464717716898185470653697
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2289788391713717381437281593262908373996521028507475975287372356587957104381
Short name T65
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.21 seconds
Started Oct 22 12:30:58 PM PDT 23
Finished Oct 22 12:32:19 PM PDT 23
Peak memory 210924 kb
Host smart-06e0aaac-1163-4fb6-b473-c9b5afc91057
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289788391713717381437281593262908373996521028507475975287372356587957104381 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.2289788391713717381437281593262908373996521028507475975287372356587957104381
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.99351597142275496524217593988002104532322800984305561930516897971991548261837
Short name T420
Test name
Test status
Simulation time 3135422826 ps
CPU time 11.98 seconds
Started Oct 22 12:31:14 PM PDT 23
Finished Oct 22 12:31:27 PM PDT 23
Peak memory 213328 kb
Host smart-3965ff35-5f1f-4943-a8db-197cc83f42f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9935159714227549652421759398800210453232280
0984305561930516897971991548261837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.993515971422
75496524217593988002104532322800984305561930516897971991548261837
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.36489862215927813608407771787737913458153929574895590856532431030219807863157
Short name T443
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 22 12:31:37 PM PDT 23
Finished Oct 22 12:31:49 PM PDT 23
Peak memory 210664 kb
Host smart-36b1c613-846d-4586-8ed0-e72bcdea8e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36489862215927813608407771787737913458153929574895590856532431030219807863157 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.36489862215927813608407771787737913458153929574895590856532431030219807863157
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.68609579534349574325254426360016470812200724432020839498146872651227233634936
Short name T431
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.15 seconds
Started Oct 22 12:31:27 PM PDT 23
Finished Oct 22 12:36:09 PM PDT 23
Peak memory 218980 kb
Host smart-16398758-62ec-4ba5-93cf-3d0d0f9af02a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68609579534349574325254426360016470812200724432020839498146872651227233634936 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.6860957953434957432525442636001647081220072443202083949
8146872651227233634936
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.72700568308006551907566853746400955058431432683415179663761726157826478293736
Short name T392
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.84 seconds
Started Oct 22 12:31:09 PM PDT 23
Finished Oct 22 12:31:24 PM PDT 23
Peak memory 210676 kb
Host smart-6f8ee519-6f92-46a4-9a6b-a53838a38a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72700568308006551907566853746400955058431432683415179663761726157826478293736
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.72700568308006551907566853746400955058431432683415179
663761726157826478293736
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.14192993759232769757162742246809209467300809049528574316989616659040834242141
Short name T417
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.56 seconds
Started Oct 22 12:31:13 PM PDT 23
Finished Oct 22 12:31:29 PM PDT 23
Peak memory 218896 kb
Host smart-015e0b35-252e-46b9-b8eb-ad576c46b1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14192993759232769757162742246809209467300809049528574316989616659040834242141 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.14192993759232769757162742246809209467300809049528574316989616659040834242141
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.61329311110361696497749255835224220315443208129272027231156036215403600103723
Short name T94
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.91 seconds
Started Oct 22 12:31:38 PM PDT 23
Finished Oct 22 12:33:00 PM PDT 23
Peak memory 210924 kb
Host smart-e77b19c3-6a49-4172-b99a-c4fcaa153773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61329311110361696497749255835224220315443208129272027231156036215403600103723 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.61329311110361696497749255835224220315443208129272027231156036215403600103723
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.82537322971987712981433162913951189123535363356683433543350911260904142828598
Short name T386
Test name
Test status
Simulation time 3135422826 ps
CPU time 11.76 seconds
Started Oct 22 12:31:43 PM PDT 23
Finished Oct 22 12:31:55 PM PDT 23
Peak memory 213296 kb
Host smart-26c411c6-f04c-4f17-865b-eaf353f24290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8253732297198771298143316291395118912353536
3356683433543350911260904142828598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.825373229719
87712981433162913951189123535363356683433543350911260904142828598
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.14904540411539086803393871307486008647158217335619079654430076834723795973676
Short name T393
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 22 12:30:56 PM PDT 23
Finished Oct 22 12:31:09 PM PDT 23
Peak memory 210676 kb
Host smart-46fa19d6-771b-463e-8c73-ba68c0ae7018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904540411539086803393871307486008647158217335619079654430076834723795973676 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.14904540411539086803393871307486008647158217335619079654430076834723795973676
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.95529967632527628183271909436153529057697251932342438522473795904693057881025
Short name T412
Test name
Test status
Simulation time 65914678386 ps
CPU time 272.53 seconds
Started Oct 22 12:31:15 PM PDT 23
Finished Oct 22 12:35:49 PM PDT 23
Peak memory 218032 kb
Host smart-972427e0-7dfb-433b-9896-d87071d7a0b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95529967632527628183271909436153529057697251932342438522473795904693057881025 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.9552996763252762818327190943615352905769725193234243852
2473795904693057881025
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.89191661894563314134859614642863430195079383742373265453409160390490715974268
Short name T381
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.5 seconds
Started Oct 22 12:31:30 PM PDT 23
Finished Oct 22 12:31:44 PM PDT 23
Peak memory 210652 kb
Host smart-41c74409-b189-4ab5-bb31-73b775c33749
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89191661894563314134859614642863430195079383742373265453409160390490715974268
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.89191661894563314134859614642863430195079383742373265
453409160390490715974268
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.57694410891052816341556897460221060935549578719445828947477959998104156142840
Short name T57
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.19 seconds
Started Oct 22 12:31:07 PM PDT 23
Finished Oct 22 12:31:24 PM PDT 23
Peak memory 218876 kb
Host smart-c326ab92-49a1-4088-9f4f-6147114d3513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57694410891052816341556897460221060935549578719445828947477959998104156142840 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.57694410891052816341556897460221060935549578719445828947477959998104156142840
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.34230023109812871639927333991007453284073097269205762022504542870582749607402
Short name T27
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.53 seconds
Started Oct 22 12:31:41 PM PDT 23
Finished Oct 22 12:33:01 PM PDT 23
Peak memory 210916 kb
Host smart-33f67587-6cb4-4595-b59f-6fe2761d49d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34230023109812871639927333991007453284073097269205762022504542870582749607402 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.34230023109812871639927333991007453284073097269205762022504542870582749607402
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3132515946212386294055722570895353768584640610413607913024690521684940731023
Short name T426
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.28 seconds
Started Oct 22 12:31:28 PM PDT 23
Finished Oct 22 12:31:41 PM PDT 23
Peak memory 213300 kb
Host smart-bf01e3bb-7a04-4527-a276-038ef00ee17c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132515946212386294055722570895353768584640
610413607913024690521684940731023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3132515946212
386294055722570895353768584640610413607913024690521684940731023
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.33211408489728749723297293686706655303182712962448416404439807097930143256225
Short name T93
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 22 12:31:45 PM PDT 23
Finished Oct 22 12:31:58 PM PDT 23
Peak memory 210684 kb
Host smart-9c82fcc2-5312-4acd-ab49-b9531eb89ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33211408489728749723297293686706655303182712962448416404439807097930143256225 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.33211408489728749723297293686706655303182712962448416404439807097930143256225
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.27397916012168106391910609133852081076654953023975413263179485597674088174569
Short name T405
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.55 seconds
Started Oct 22 12:31:25 PM PDT 23
Finished Oct 22 12:36:07 PM PDT 23
Peak memory 218804 kb
Host smart-30f88823-c33c-46cb-8a0e-fc021f089514
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27397916012168106391910609133852081076654953023975413263179485597674088174569 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.2739791601216810639191060913385208107665495302397541326
3179485597674088174569
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.59583029743124747201445968043444899499690533504638036064335555924685836770770
Short name T401
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.02 seconds
Started Oct 22 12:31:45 PM PDT 23
Finished Oct 22 12:32:00 PM PDT 23
Peak memory 210680 kb
Host smart-3f9879e0-9734-4173-b90e-2f7f5d4c9f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59583029743124747201445968043444899499690533504638036064335555924685836770770
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.59583029743124747201445968043444899499690533504638036
064335555924685836770770
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.72259527716321580364944874313157336238168173350607799662980515702047849810606
Short name T428
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.9 seconds
Started Oct 22 12:31:11 PM PDT 23
Finished Oct 22 12:31:27 PM PDT 23
Peak memory 218904 kb
Host smart-c29b5220-3aa0-4d95-b8fc-3e26167f19ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72259527716321580364944874313157336238168173350607799662980515702047849810606 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.72259527716321580364944874313157336238168173350607799662980515702047849810606
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.5233193232348060546221627965730047649901186681098665041854092979765246414129
Short name T439
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.83 seconds
Started Oct 22 12:31:04 PM PDT 23
Finished Oct 22 12:32:25 PM PDT 23
Peak memory 210996 kb
Host smart-1a21d61b-8d9f-4d03-91dc-a17d013f593f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5233193232348060546221627965730047649901186681098665041854092979765246414129 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.5233193232348060546221627965730047649901186681098665041854092979765246414129
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.5389380004846105790607193443890238869625491893808955994163442787511814071849
Short name T415
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.36 seconds
Started Oct 22 12:30:51 PM PDT 23
Finished Oct 22 12:31:04 PM PDT 23
Peak memory 213312 kb
Host smart-cd3cb9eb-17c6-41c3-93fd-af8df98fdef9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5389380004846105790607193443890238869625491
893808955994163442787511814071849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.5389380004846
105790607193443890238869625491893808955994163442787511814071849
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.11027136130560068683980991362199671342944232099629823716768368153468982100621
Short name T20
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.91 seconds
Started Oct 22 12:31:16 PM PDT 23
Finished Oct 22 12:31:28 PM PDT 23
Peak memory 210132 kb
Host smart-4ea53475-4c8a-4c96-ab02-dbc7606204a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11027136130560068683980991362199671342944232099629823716768368153468982100621 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.11027136130560068683980991362199671342944232099629823716768368153468982100621
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.15591925937367128492114502632717576707732977105244481656774230761746920938386
Short name T70
Test name
Test status
Simulation time 65914678386 ps
CPU time 279.25 seconds
Started Oct 22 12:31:41 PM PDT 23
Finished Oct 22 12:36:20 PM PDT 23
Peak memory 218808 kb
Host smart-23853c1f-dc7a-4e59-ae13-079e8fa51efe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591925937367128492114502632717576707732977105244481656774230761746920938386 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.1559192593736712849211450263271757670773297710524448165
6774230761746920938386
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.21936640788773658330080573521543339069229174303932372202774094998876800357010
Short name T62
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.68 seconds
Started Oct 22 12:30:09 PM PDT 23
Finished Oct 22 12:30:25 PM PDT 23
Peak memory 210696 kb
Host smart-28505b38-e64e-4e17-8a7a-865c25b75188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21936640788773658330080573521543339069229174303932372202774094998876800357010
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.21936640788773658330080573521543339069229174303932372
202774094998876800357010
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.67711939198406377151899188672540489740361255197791434200505853689424190160043
Short name T55
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.47 seconds
Started Oct 22 12:31:11 PM PDT 23
Finished Oct 22 12:31:26 PM PDT 23
Peak memory 218940 kb
Host smart-4dbef382-72a6-45d9-85fa-a37d2a02aa78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67711939198406377151899188672540489740361255197791434200505853689424190160043 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.67711939198406377151899188672540489740361255197791434200505853689424190160043
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.38707475903677788113145019342477713613650909270961262022408270915484693576222
Short name T98
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.29 seconds
Started Oct 22 12:30:42 PM PDT 23
Finished Oct 22 12:32:03 PM PDT 23
Peak memory 210904 kb
Host smart-b69f1693-5f2c-41f3-85ec-de2af9618611
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38707475903677788113145019342477713613650909270961262022408270915484693576222 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.38707475903677788113145019342477713613650909270961262022408270915484693576222
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.70069905501476987706726439123373338684723048555343437039509255389343625901876
Short name T56
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.55 seconds
Started Oct 22 12:30:42 PM PDT 23
Finished Oct 22 12:30:55 PM PDT 23
Peak memory 213288 kb
Host smart-619c032f-b0c1-4e01-a59b-0bb48478c3ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7006990550147698770672643912337333868472304
8555343437039509255389343625901876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.700699055014
76987706726439123373338684723048555343437039509255389343625901876
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.95946322424556400643121492291793232968120648297174703041160286999111116406727
Short name T25
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 22 12:30:52 PM PDT 23
Finished Oct 22 12:31:04 PM PDT 23
Peak memory 210692 kb
Host smart-6ce9e81e-6a7e-48ae-b7da-c4cd17481bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95946322424556400643121492291793232968120648297174703041160286999111116406727 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.95946322424556400643121492291793232968120648297174703041160286999111116406727
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.51606217191036328683261221086540384016730319885350960384442701828946553481347
Short name T440
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.7 seconds
Started Oct 22 12:30:41 PM PDT 23
Finished Oct 22 12:35:26 PM PDT 23
Peak memory 218844 kb
Host smart-5b33d75e-5481-4506-a8ef-c052eb06d616
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51606217191036328683261221086540384016730319885350960384442701828946553481347 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.5160621719103632868326122108654038401673031988535096038
4442701828946553481347
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.6651133571138752668500989894869638363297780215685252334765133727458764245349
Short name T75
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.62 seconds
Started Oct 22 12:32:49 PM PDT 23
Finished Oct 22 12:33:03 PM PDT 23
Peak memory 210696 kb
Host smart-1f0ee2d1-bb70-4543-ae55-ab996aaec23d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6651133571138752668500989894869638363297780215685252334765133727458764245349 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.665113357113875266850098989486963836329778021568525233
4765133727458764245349
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.108319229827181404188231168623266926426668319329606393776303720013558965728947
Short name T446
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.16 seconds
Started Oct 22 12:30:58 PM PDT 23
Finished Oct 22 12:31:15 PM PDT 23
Peak memory 218900 kb
Host smart-bf988038-ab13-4b3f-b867-825bd7dd3330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108319229827181404188231168623266926426668319329606393776303720013558965728947 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.108319229827181404188231168623266926426668319329606393776303720013558965728947
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.63132653169656579687170394426596046941074848596652387728719122038440432628405
Short name T374
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.34 seconds
Started Oct 22 12:32:17 PM PDT 23
Finished Oct 22 12:33:38 PM PDT 23
Peak memory 211040 kb
Host smart-cb2abff4-df4e-4086-86e9-6ec29c7dfbf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63132653169656579687170394426596046941074848596652387728719122038440432628405 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.63132653169656579687170394426596046941074848596652387728719122038440432628405
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.96069767777379929740219756759943813867105727915029932040937184767385443723244
Short name T441
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 22 12:23:39 PM PDT 23
Finished Oct 22 12:23:52 PM PDT 23
Peak memory 210744 kb
Host smart-bcb5dc0c-dbe2-4b94-bf15-f5c6d1253494
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96069767777379929740219756759943813867105727915029932040937184767385443723244 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.96069767777379929740219756759943813867105727915029932040937184767385443723244
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.28263754769901169066929167943878506676981847142167033988661266536703905307775
Short name T85
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.18 seconds
Started Oct 22 12:27:17 PM PDT 23
Finished Oct 22 12:27:30 PM PDT 23
Peak memory 210676 kb
Host smart-155666f4-0787-4aed-8ded-b1540c50a9ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263754769901169066929167943878506676981847142167033988661266536703905307775 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.28263754769901169066929167943878506676981847142167033988661266536703905307775
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.26264144290043135366612600296287946976957365586503127491564930794433449001873
Short name T19
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.39 seconds
Started Oct 22 12:25:35 PM PDT 23
Finished Oct 22 12:25:51 PM PDT 23
Peak memory 209856 kb
Host smart-be2a2598-470d-4368-b41d-3ae0b20f7efb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26264144290043135366612600296287946976957365586503127491564930794433449001873 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.26264144290043135366612600296287946976957365586503127491564930794433449001873
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.25830509226823368413880391444226671630758520840553397686869966678597789333000
Short name T444
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.14 seconds
Started Oct 22 12:26:31 PM PDT 23
Finished Oct 22 12:26:44 PM PDT 23
Peak memory 213268 kb
Host smart-faff3c87-8b01-430d-9894-10bd6714919f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583050922682336841388039144422667163075852
0840553397686869966678597789333000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2583050922682
3368413880391444226671630758520840553397686869966678597789333000
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.57750918280806898497824631900752783451951727126233719188656763490389562953854
Short name T398
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 22 12:25:35 PM PDT 23
Finished Oct 22 12:25:48 PM PDT 23
Peak memory 209632 kb
Host smart-1fd0b789-00dd-45b4-83f9-5522b3f499fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57750918280806898497824631900752783451951727126233719188656763490389562953854 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.57750918280806898497824631900752783451951727126233719188656763490389562953854
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.70431071245992212788067822123358512601901493942579469142154799998852233516855
Short name T372
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.07 seconds
Started Oct 22 12:27:22 PM PDT 23
Finished Oct 22 12:27:35 PM PDT 23
Peak memory 210664 kb
Host smart-3c644e75-c605-4f96-a5d0-6c89d60c074a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70431071245992212788067822123358512601901493942579469142154799998852233516855 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.7043107124599221278806782212335851260190149394257946914215
4799998852233516855
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3822496896228761441865391213651644508782472047594309140223854109774550258926
Short name T400
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.82 seconds
Started Oct 22 12:25:41 PM PDT 23
Finished Oct 22 12:25:54 PM PDT 23
Peak memory 210688 kb
Host smart-64ca6a33-bac0-4d10-864d-69498cce4aee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822496896228761441865391213651644508782472047594309140223854109774550258926 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.3822496896228761441865391213651644508782472047594309140223854109774550258926
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.47415415524105472290939630233866596252171329571764451014991728499107779190651
Short name T68
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.68 seconds
Started Oct 22 12:26:27 PM PDT 23
Finished Oct 22 12:31:10 PM PDT 23
Peak memory 218224 kb
Host smart-9b964dbc-59dc-4ddd-ac5d-5f3f84ba16b5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47415415524105472290939630233866596252171329571764451014991728499107779190651 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.47415415524105472290939630233866596252171329571764451014
991728499107779190651
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.38796108298186444894060521789407170243478059989188622198312887345119443629490
Short name T63
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.83 seconds
Started Oct 22 12:27:59 PM PDT 23
Finished Oct 22 12:28:13 PM PDT 23
Peak memory 210652 kb
Host smart-e35769a5-1f3e-41c6-8cb0-3433b19710a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38796108298186444894060521789407170243478059989188622198312887345119443629490
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.387961082981864448940605217894071702434780599891886221
98312887345119443629490
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.64137704694085424131329804823580382884495629630913529713925847193191099044707
Short name T54
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.42 seconds
Started Oct 22 12:24:37 PM PDT 23
Finished Oct 22 12:24:54 PM PDT 23
Peak memory 219160 kb
Host smart-6f8e8b5d-fe6b-484c-a395-76a60ed66abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64137704694085424131329804823580382884495629630913529713925847193191099044707 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.64137704694085424131329804823580382884495629630913529713925847193191099044707
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4818565554552759905952899128527717049485661854903250464722062949447791489728
Short name T48
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.91 seconds
Started Oct 22 12:26:27 PM PDT 23
Finished Oct 22 12:27:49 PM PDT 23
Peak memory 210888 kb
Host smart-b5b89d11-f494-453b-a558-b72558828335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4818565554552759905952899128527717049485661854903250464722062949447791489728 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.4818565554552759905952899128527717049485661854903250464722062949447791489728
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.83841441809387397181411985590531316580065087940340522951225452898686172887039
Short name T82
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Oct 22 12:25:43 PM PDT 23
Finished Oct 22 12:25:56 PM PDT 23
Peak memory 210656 kb
Host smart-15dd372c-cb3c-4c06-a5c2-824adbcbe5ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83841441809387397181411985590531316580065087940340522951225452898686172887039 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.83841441809387397181411985590531316580065087940340522951225452898686172887039
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.64711595447368353132018194993494849439553496587747952367556771133817485850709
Short name T84
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.98 seconds
Started Oct 22 12:23:41 PM PDT 23
Finished Oct 22 12:23:54 PM PDT 23
Peak memory 210916 kb
Host smart-848d4f85-061e-46b1-bc16-07bd8f56a40b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64711595447368353132018194993494849439553496587747952367556771133817485850709 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.64711595447368353132018194993494849439553496587747952367556771133817485850709
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.60096223536099424179798656860117577226884639821419226242291190711119790258604
Short name T90
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.11 seconds
Started Oct 22 12:26:37 PM PDT 23
Finished Oct 22 12:26:53 PM PDT 23
Peak memory 210704 kb
Host smart-06955726-4400-4b17-9911-e2abcaefcdfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60096223536099424179798656860117577226884639821419226242291190711119790258604 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.60096223536099424179798656860117577226884639821419226242291190711119790258604
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.93780652033771444266415811749666262982083554458052055853822672187318651358346
Short name T389
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.52 seconds
Started Oct 22 12:23:22 PM PDT 23
Finished Oct 22 12:23:35 PM PDT 23
Peak memory 213276 kb
Host smart-bf6d8e08-71d5-4697-aa19-e8fd53fa7a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9378065203377144426641581174966626298208355
4458052055853822672187318651358346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.9378065203377
1444266415811749666262982083554458052055853822672187318651358346
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.19427215002191153781360385673936995753866713695496199440841789519100928747986
Short name T22
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.85 seconds
Started Oct 22 12:27:42 PM PDT 23
Finished Oct 22 12:27:55 PM PDT 23
Peak memory 210664 kb
Host smart-177c3105-1eb4-48ac-9b1c-706dee3c8d01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19427215002191153781360385673936995753866713695496199440841789519100928747986 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.19427215002191153781360385673936995753866713695496199440841789519100928747986
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.66651934791405338384952863443566603838344714930503022120338505108249147425602
Short name T88
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 22 12:26:30 PM PDT 23
Finished Oct 22 12:26:43 PM PDT 23
Peak memory 210676 kb
Host smart-3559ea3d-2fc5-4c15-a906-ec4ce1442fd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66651934791405338384952863443566603838344714930503022120338505108249147425602 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.6665193479140533838495286344356660383834471493050302212033
8505108249147425602
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.57080070469989436242703766765549493476251204823560281618974838247472618905840
Short name T404
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 22 12:25:15 PM PDT 23
Finished Oct 22 12:25:28 PM PDT 23
Peak memory 210028 kb
Host smart-091c59d4-d6a4-412b-9470-17c123ae7298
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57080070469989436242703766765549493476251204823560281618974838247472618905840 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.57080070469989436242703766765549493476251204823560281618974838247472618905840
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.41586915471883892890778658070612312587330546423284572926279962689056891261079
Short name T419
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.11 seconds
Started Oct 22 12:24:41 PM PDT 23
Finished Oct 22 12:29:27 PM PDT 23
Peak memory 218812 kb
Host smart-afcab742-ee15-4c13-a725-63e51bdbaeda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41586915471883892890778658070612312587330546423284572926279962689056891261079 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.41586915471883892890778658070612312587330546423284572926
279962689056891261079
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.9617732865402754223093460483292462732227466201785139391042988289802994972908
Short name T74
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.22 seconds
Started Oct 22 12:23:36 PM PDT 23
Finished Oct 22 12:23:50 PM PDT 23
Peak memory 210804 kb
Host smart-b2b3e537-1325-48b6-b69b-10725dcbac12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9617732865402754223093460483292462732227466201785139391042988289802994972908 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.9617732865402754223093460483292462732227466201785139391
042988289802994972908
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.110633556196020267812519416200931472288485676493912689599921913503809546306184
Short name T409
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.61 seconds
Started Oct 22 12:23:56 PM PDT 23
Finished Oct 22 12:24:14 PM PDT 23
Peak memory 219020 kb
Host smart-3397a4e7-3c46-4de8-bb6b-fed9cbb8558b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110633556196020267812519416200931472288485676493912689599921913503809546306184 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.110633556196020267812519416200931472288485676493912689599921913503809546306184
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.106224584229921047639179209117392079827552242723526680769791108977368103691885
Short name T96
Test name
Test status
Simulation time 3476453456 ps
CPU time 84.38 seconds
Started Oct 22 12:22:18 PM PDT 23
Finished Oct 22 12:23:43 PM PDT 23
Peak memory 211136 kb
Host smart-71fce1e3-09e2-4e69-81a9-88d4dd41727a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106224584229921047639179209117392079827552242723526680769791108977368103691885 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.106224584229921047639179209117392079827552242723526680769791108977368103691885
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3303386641343762211020842018734415969195527915022155491402760582620022680427
Short name T86
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.13 seconds
Started Oct 22 12:26:21 PM PDT 23
Finished Oct 22 12:26:34 PM PDT 23
Peak memory 209980 kb
Host smart-bc29cce3-70f5-43ac-aca5-985c8f91ffff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303386641343762211020842018734415969195527915022155491402760582620022680427 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.3303386641343762211020842018734415969195527915022155491402760582620022680427
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.86935114074757771652286285891667489488159646268996518252875623288684952798026
Short name T442
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 22 12:28:03 PM PDT 23
Finished Oct 22 12:28:16 PM PDT 23
Peak memory 210680 kb
Host smart-96839e31-41cf-4a7d-8f61-78832da60ad6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86935114074757771652286285891667489488159646268996518252875623288684952798026 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.86935114074757771652286285891667489488159646268996518252875623288684952798026
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.112363037827029947260537951347758214884738782770164888846979789309088886071303
Short name T394
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.74 seconds
Started Oct 22 12:28:24 PM PDT 23
Finished Oct 22 12:28:45 PM PDT 23
Peak memory 210700 kb
Host smart-2a9bc8c3-7201-4eb3-ae77-cf819bbbb8bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112363037827029947260537951347758214884738782770164888846979789309088886071303 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.112363037827029947260537951347758214884738782770164888846979789309088886071303
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.28186684325619825282825885901037186634692753289162671430269389013693513915689
Short name T380
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.21 seconds
Started Oct 22 12:26:41 PM PDT 23
Finished Oct 22 12:26:54 PM PDT 23
Peak memory 213296 kb
Host smart-85945169-e66a-4f3f-8833-14c67a9b6dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818668432561982528282588590103718663469275
3289162671430269389013693513915689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2818668432561
9825282825885901037186634692753289162671430269389013693513915689
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.43266329329983420514115224686859919305279210433496268297446041789398560963510
Short name T371
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.9 seconds
Started Oct 22 12:26:26 PM PDT 23
Finished Oct 22 12:26:38 PM PDT 23
Peak memory 210692 kb
Host smart-58c81e64-7e42-42d5-946c-9efd3c0eba94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43266329329983420514115224686859919305279210433496268297446041789398560963510 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.43266329329983420514115224686859919305279210433496268297446041789398560963510
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.115610151522560614653405830323940319172607211006500415722202940518201088468361
Short name T92
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.97 seconds
Started Oct 22 12:26:32 PM PDT 23
Finished Oct 22 12:26:45 PM PDT 23
Peak memory 210648 kb
Host smart-ab786a31-bafe-4539-955e-482a0081169d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115610151522560614653405830323940319172607211006500415722202940518201088468361 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.115610151522560614653405830323940319172607211006500415722
202940518201088468361
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.41321875240412092853987361941358893402572188152580875847971897200759142607930
Short name T370
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.97 seconds
Started Oct 22 12:27:44 PM PDT 23
Finished Oct 22 12:27:57 PM PDT 23
Peak memory 209968 kb
Host smart-90d067ce-a0c2-48ba-bdb1-8706a9f96c25
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321875240412092853987361941358893402572188152580875847971897200759142607930 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.41321875240412092853987361941358893402572188152580875847971897200759142607930
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.37323017307246735977004305421005548964937360909092182306258925150083101750323
Short name T72
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.43 seconds
Started Oct 22 12:24:56 PM PDT 23
Finished Oct 22 12:29:44 PM PDT 23
Peak memory 218832 kb
Host smart-4cdef855-6161-4c91-9bf5-3e7e957bef8c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323017307246735977004305421005548964937360909092182306258925150083101750323 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.37323017307246735977004305421005548964937360909092182306
258925150083101750323
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.5979593651550499140128857003492726138578568344620720877660849689735567569853
Short name T424
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.16 seconds
Started Oct 22 12:25:31 PM PDT 23
Finished Oct 22 12:25:46 PM PDT 23
Peak memory 210792 kb
Host smart-b36fd21a-ad10-4590-bc26-bffce96c76ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5979593651550499140128857003492726138578568344620720877660849689735567569853 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.5979593651550499140128857003492726138578568344620720877
660849689735567569853
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.38167130456311184524113309096408227827653954217880549942258483464354225112146
Short name T413
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.87 seconds
Started Oct 22 12:23:56 PM PDT 23
Finished Oct 22 12:24:14 PM PDT 23
Peak memory 219032 kb
Host smart-9904ee72-7819-4bcd-a418-074387e03f87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38167130456311184524113309096408227827653954217880549942258483464354225112146 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.38167130456311184524113309096408227827653954217880549942258483464354225112146
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.103701720522690685787332088024155228572156043511651286189082340629743522425801
Short name T433
Test name
Test status
Simulation time 3476453456 ps
CPU time 83.1 seconds
Started Oct 22 12:22:36 PM PDT 23
Finished Oct 22 12:24:00 PM PDT 23
Peak memory 211280 kb
Host smart-87d1acbc-6ffa-4e4b-b92f-995ad1fc1f62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103701720522690685787332088024155228572156043511651286189082340629743522425801 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.103701720522690685787332088024155228572156043511651286189082340629743522425801
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.106808209727664828735043536337697606629284292378562125240185454346071056279675
Short name T423
Test name
Test status
Simulation time 3135422826 ps
CPU time 11.99 seconds
Started Oct 22 12:27:16 PM PDT 23
Finished Oct 22 12:27:28 PM PDT 23
Peak memory 213280 kb
Host smart-d4c2c913-3d9f-495e-a440-4bae7e99d54d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068082097276648287350435363376976066292842
92378562125240185454346071056279675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.106808209727
664828735043536337697606629284292378562125240185454346071056279675
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.92454205132599110589395383140516175404755416717994571050090148026842877709726
Short name T21
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 22 12:26:50 PM PDT 23
Finished Oct 22 12:27:03 PM PDT 23
Peak memory 210688 kb
Host smart-88d16ecc-df4d-4edd-baaf-1028bf374767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92454205132599110589395383140516175404755416717994571050090148026842877709726 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.92454205132599110589395383140516175404755416717994571050090148026842877709726
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.16873188667041896141238877426317401786167102828936910541003392871788828475541
Short name T50
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.03 seconds
Started Oct 22 12:26:30 PM PDT 23
Finished Oct 22 12:26:44 PM PDT 23
Peak memory 210680 kb
Host smart-5c7e5d0b-39f4-42a1-b38b-09511abc5c0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873188667041896141238877426317401786167102828936910541003392871788828475541
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.168731886670418961412388774263174017861671028289369105
41003392871788828475541
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.35094805534943875939677452665690278933823398489265406688899800509494241009066
Short name T60
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Oct 22 12:26:28 PM PDT 23
Finished Oct 22 12:26:45 PM PDT 23
Peak memory 218916 kb
Host smart-699edecd-403a-4390-8298-fef7cdf3f622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094805534943875939677452665690278933823398489265406688899800509494241009066 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.35094805534943875939677452665690278933823398489265406688899800509494241009066
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.89831461285301522500319754058392969393142354057993671010748912914993822977547
Short name T97
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.13 seconds
Started Oct 22 12:31:17 PM PDT 23
Finished Oct 22 12:32:40 PM PDT 23
Peak memory 210872 kb
Host smart-42f7b11a-337c-4173-bc7f-dc707ba95c66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89831461285301522500319754058392969393142354057993671010748912914993822977547 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.89831461285301522500319754058392969393142354057993671010748912914993822977547
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.23340538629856171616548198115060057618461947700139019628154403949423868382613
Short name T448
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.62 seconds
Started Oct 22 12:24:30 PM PDT 23
Finished Oct 22 12:24:43 PM PDT 23
Peak memory 213516 kb
Host smart-625f55a3-d96a-4323-99aa-593ddb7bab28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334053862985617161654819811506005761846194
7700139019628154403949423868382613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2334053862985
6171616548198115060057618461947700139019628154403949423868382613
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.35663883262126341020419162109542682235464035529788122325994854181774433638346
Short name T91
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.97 seconds
Started Oct 22 12:26:44 PM PDT 23
Finished Oct 22 12:26:58 PM PDT 23
Peak memory 210652 kb
Host smart-2c5d19d3-789f-41d1-84dd-285d53732107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35663883262126341020419162109542682235464035529788122325994854181774433638346 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.35663883262126341020419162109542682235464035529788122325994854181774433638346
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.30454741413174162830933963941252199599258396935301386414064090390004735836715
Short name T425
Test name
Test status
Simulation time 65914678386 ps
CPU time 280.33 seconds
Started Oct 22 12:27:43 PM PDT 23
Finished Oct 22 12:32:25 PM PDT 23
Peak memory 218124 kb
Host smart-08a5d6e6-2f55-486b-9ac2-c852172f45ad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30454741413174162830933963941252199599258396935301386414064090390004735836715 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.30454741413174162830933963941252199599258396935301386414
064090390004735836715
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.57531419272473313668616312897664818581684197396606421304534797668905180479822
Short name T66
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.11 seconds
Started Oct 22 12:26:48 PM PDT 23
Finished Oct 22 12:27:03 PM PDT 23
Peak memory 210644 kb
Host smart-7b1b9285-657d-4533-a3b6-42e4f411bd55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57531419272473313668616312897664818581684197396606421304534797668905180479822
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.575314192724733136686163128976648185816841973966064213
04534797668905180479822
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.14583129027442057537221100131775927833089264636275262022766887721581041552825
Short name T403
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.88 seconds
Started Oct 22 12:22:40 PM PDT 23
Finished Oct 22 12:22:57 PM PDT 23
Peak memory 219012 kb
Host smart-2c042b47-24dd-455e-a461-0c25ba337511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14583129027442057537221100131775927833089264636275262022766887721581041552825 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.14583129027442057537221100131775927833089264636275262022766887721581041552825
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.16043971309988628115605156500261453918823825507869208363377102188029618529214
Short name T416
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.74 seconds
Started Oct 22 12:25:20 PM PDT 23
Finished Oct 22 12:26:40 PM PDT 23
Peak memory 210916 kb
Host smart-49483699-9074-4d67-89e2-1a631f347d71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16043971309988628115605156500261453918823825507869208363377102188029618529214 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.16043971309988628115605156500261453918823825507869208363377102188029618529214
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.36673615885710597686066383930466308975222582143729161318812463099803605826796
Short name T435
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.37 seconds
Started Oct 22 12:31:25 PM PDT 23
Finished Oct 22 12:31:38 PM PDT 23
Peak memory 213296 kb
Host smart-1483929e-a134-44a8-8e4e-0e37a85b9f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667361588571059768606638393046630897522258
2143729161318812463099803605826796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3667361588571
0597686066383930466308975222582143729161318812463099803605826796
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.46855978187230607689964825016173992339274185185091845941547350183316451901676
Short name T432
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 22 12:31:02 PM PDT 23
Finished Oct 22 12:31:15 PM PDT 23
Peak memory 210692 kb
Host smart-4ab017ce-476f-4aaa-a2a2-bc193a7b4b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46855978187230607689964825016173992339274185185091845941547350183316451901676 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.46855978187230607689964825016173992339274185185091845941547350183316451901676
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.11559722961602213128280183778057434670948251735404163796158686490339673117671
Short name T408
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.39 seconds
Started Oct 22 12:27:37 PM PDT 23
Finished Oct 22 12:32:20 PM PDT 23
Peak memory 218816 kb
Host smart-45226bd1-21c5-482c-a4da-b86738c6ac76
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11559722961602213128280183778057434670948251735404163796158686490339673117671 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.11559722961602213128280183778057434670948251735404163796
158686490339673117671
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.77693269812622314036810106090171132578281654876622304107723338120122875182000
Short name T375
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.11 seconds
Started Oct 22 12:31:32 PM PDT 23
Finished Oct 22 12:31:51 PM PDT 23
Peak memory 210764 kb
Host smart-2a8d5ce7-aa06-46f7-b76d-be7a9b25bfc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77693269812622314036810106090171132578281654876622304107723338120122875182000
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.776932698126223140368101060901711325782816548766223041
07723338120122875182000
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.12871616196599753914868505381069686079523541227117440516363435083480086708154
Short name T421
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.53 seconds
Started Oct 22 12:23:37 PM PDT 23
Finished Oct 22 12:23:54 PM PDT 23
Peak memory 219112 kb
Host smart-e952ae00-e515-4a5f-9078-a7571a739899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12871616196599753914868505381069686079523541227117440516363435083480086708154 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.12871616196599753914868505381069686079523541227117440516363435083480086708154
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.40629488782557237471478599734848238669474649826072643928289399505068939040029
Short name T44
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.91 seconds
Started Oct 22 12:32:52 PM PDT 23
Finished Oct 22 12:34:12 PM PDT 23
Peak memory 210908 kb
Host smart-cc4d940d-6df0-433d-a423-7a7bd1790636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40629488782557237471478599734848238669474649826072643928289399505068939040029 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.40629488782557237471478599734848238669474649826072643928289399505068939040029
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.23930121890306561593912190216286005584093411651081427652254927835424785182393
Short name T383
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.26 seconds
Started Oct 22 12:31:07 PM PDT 23
Finished Oct 22 12:31:25 PM PDT 23
Peak memory 213300 kb
Host smart-24f1d988-aa26-44e2-815f-c91416768ca1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393012189030656159391219021628600558409341
1651081427652254927835424785182393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2393012189030
6561593912190216286005584093411651081427652254927835424785182393
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.73528812482403013745117739323565374320554402566625486370070739642537868892603
Short name T95
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.79 seconds
Started Oct 22 12:32:51 PM PDT 23
Finished Oct 22 12:33:03 PM PDT 23
Peak memory 210684 kb
Host smart-1cd03878-a7fb-4495-9a03-07ad76b05925
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73528812482403013745117739323565374320554402566625486370070739642537868892603 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.73528812482403013745117739323565374320554402566625486370070739642537868892603
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.20807930893876251368247737256197371516646079455624472684393942652783402937359
Short name T34
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.82 seconds
Started Oct 22 12:31:04 PM PDT 23
Finished Oct 22 12:35:47 PM PDT 23
Peak memory 218896 kb
Host smart-0f338053-ea9d-4484-8622-3b83ec3c20d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807930893876251368247737256197371516646079455624472684393942652783402937359 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.20807930893876251368247737256197371516646079455624472684
393942652783402937359
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.50323400534103639302234758030993927626271023882837987147886137411765659750450
Short name T397
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.55 seconds
Started Oct 22 12:32:49 PM PDT 23
Finished Oct 22 12:33:03 PM PDT 23
Peak memory 210452 kb
Host smart-d7b2405e-5bc9-4425-9147-38fae676a96f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50323400534103639302234758030993927626271023882837987147886137411765659750450
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.503234005341036393022347580309939276262710238828379871
47886137411765659750450
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.83504182562421535590884678189780960826346753193185136100186550243491962246723
Short name T32
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.93 seconds
Started Oct 22 12:31:03 PM PDT 23
Finished Oct 22 12:31:19 PM PDT 23
Peak memory 218916 kb
Host smart-ffc9270d-50fc-4676-a882-332f54972a7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83504182562421535590884678189780960826346753193185136100186550243491962246723 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.83504182562421535590884678189780960826346753193185136100186550243491962246723
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.18551449054851791776308006177002185395304286218048902135068142431761367186728
Short name T26
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.05 seconds
Started Oct 22 12:31:32 PM PDT 23
Finished Oct 22 12:32:52 PM PDT 23
Peak memory 210908 kb
Host smart-8e33bd9c-8032-459c-8a26-a052a7798002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551449054851791776308006177002185395304286218048902135068142431761367186728 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.18551449054851791776308006177002185395304286218048902135068142431761367186728
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.104608023772919052469477122345902099951460611423159918037414061406581645131426
Short name T24
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.32 seconds
Started Oct 22 12:31:27 PM PDT 23
Finished Oct 22 12:31:39 PM PDT 23
Peak memory 213300 kb
Host smart-779ed626-ffd9-4742-8de0-4b6d97361ec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046080237729190524694771223459020999514606
11423159918037414061406581645131426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.104608023772
919052469477122345902099951460611423159918037414061406581645131426
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.84700626867173320420668158445363850524255970020029698214408794560637779709861
Short name T449
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.89 seconds
Started Oct 22 12:31:23 PM PDT 23
Finished Oct 22 12:31:35 PM PDT 23
Peak memory 210684 kb
Host smart-7c3c81cb-bafb-42da-bd0f-30cffebc9ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84700626867173320420668158445363850524255970020029698214408794560637779709861 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.84700626867173320420668158445363850524255970020029698214408794560637779709861
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2725420625509706919203865593587332779611745272132929702914359651486233963448
Short name T51
Test name
Test status
Simulation time 65914678386 ps
CPU time 279.86 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:35:59 PM PDT 23
Peak memory 218860 kb
Host smart-fac39e1d-0ae7-4acf-a7de-5346fe389b75
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725420625509706919203865593587332779611745272132929702914359651486233963448 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.272542062550970691920386559358733277961174527213292970291
4359651486233963448
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.57570542108160426149504957014773608767489431206562629304996457517504307258698
Short name T384
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.9 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:31:33 PM PDT 23
Peak memory 210720 kb
Host smart-608e8f16-4ab3-4642-a3d2-4beeba1b14f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57570542108160426149504957014773608767489431206562629304996457517504307258698
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.575705421081604261495049570147736087674894312065626293
04996457517504307258698
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.64953892097717801309858664427377912789014481015086588374103181531269272824551
Short name T390
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.63 seconds
Started Oct 22 12:31:18 PM PDT 23
Finished Oct 22 12:31:34 PM PDT 23
Peak memory 218708 kb
Host smart-35a04d64-3009-446e-ade4-fc4d1c708b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64953892097717801309858664427377912789014481015086588374103181531269272824551 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.64953892097717801309858664427377912789014481015086588374103181531269272824551
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.38769960772891061182895901824138686473263889345107864255915531526892462080073
Short name T396
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.55 seconds
Started Oct 22 12:31:31 PM PDT 23
Finished Oct 22 12:32:52 PM PDT 23
Peak memory 210904 kb
Host smart-97395faf-b7af-466b-9171-5cb31863cebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38769960772891061182895901824138686473263889345107864255915531526892462080073 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.38769960772891061182895901824138686473263889345107864255915531526892462080073
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.27159781839161526961387768572214993746507787743213641251354780210753688911541
Short name T315
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.71 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:49:11 PM PDT 23
Peak memory 237724 kb
Host smart-53a224bc-e485-4618-9d7d-4050b18ce15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159781839161526961387768572214993746507787743213641251354780210753688911541 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.2715978183916152696138776857221499374650778774321364125135
4780210753688911541
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.42582516721607689127377578765918677592083863061385234032044044897228107179534
Short name T301
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.38 seconds
Started Oct 22 01:44:35 PM PDT 23
Finished Oct 22 01:45:01 PM PDT 23
Peak memory 211656 kb
Host smart-37ab6b19-9fbd-4286-ac45-cc4d4bf76adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42582516721607689127377578765918677592083863061385234032044044897228107179534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.rom_ctrl_kmac_err_chk.42582516721607689127377578765918677592083863061385234032044044897228107179534
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.83642161276804491523279462518011793291895442645601152022452031450055018159113
Short name T364
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.41 seconds
Started Oct 22 01:43:26 PM PDT 23
Finished Oct 22 01:43:40 PM PDT 23
Peak memory 211216 kb
Host smart-1559db39-952f-492e-9d08-0b66a44d0f3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83642161276804491523279462518011793291895442645601152022452031450055018159113 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.83642161276804491523279462518011793291895442645601152022452031450055018159113
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.11211936493406822610831749746788273169456173712642751351709178426503777404877
Short name T36
Test name
Test status
Simulation time 3444857586 ps
CPU time 115.27 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:45:20 PM PDT 23
Peak memory 236712 kb
Host smart-0c943051-974e-484b-86b4-04cd8340240e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11211936493406822610831749746788273169456173712642751351709178426503777404877 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.11211936493406822610831749746788273169456173712642751351709178426503777404877
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.112444020392748285211696418476108164282760610796775698789392650098326017283302
Short name T148
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.86 seconds
Started Oct 22 01:44:56 PM PDT 23
Finished Oct 22 01:45:25 PM PDT 23
Peak memory 212752 kb
Host smart-e87371dd-81bb-4f15-8ecc-749163d6341b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112444020392748285211696418476108164282760610796775698789392650098326017283302 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.rom_ctrl_smoke.112444020392748285211696418476108164282760610796775698789392650098326017283302
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.16656658156617630161602211689918231676373816841543471824204373442358944114153
Short name T313
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.63 seconds
Started Oct 22 01:44:50 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 212976 kb
Host smart-6afa21c6-d050-4bf3-86a7-d76caf12e540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166566581566176301616022116899182316763738168415434718242043734
42358944114153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.166566581566176301616022116899182316763738168415434
71824204373442358944114153
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.30395420079946914119730816750428025948164476058570573096383646597748384162141
Short name T143
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 22 01:44:57 PM PDT 23
Finished Oct 22 01:45:10 PM PDT 23
Peak memory 211212 kb
Host smart-07416365-930f-404a-99b8-24b743f30890
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395420079946914119730816750428025948164476058570573096383646597748384162141 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.30395420079946914119730816750428025948164476058570573096383646597748384162141
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.53579420457222813611975153062443937302462130290985296171818442242835220837604
Short name T198
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.77 seconds
Started Oct 22 01:43:26 PM PDT 23
Finished Oct 22 01:49:11 PM PDT 23
Peak memory 237676 kb
Host smart-a1724d50-40cf-48b8-bfb8-88c06e7000df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53579420457222813611975153062443937302462130290985296171818442242835220837604 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.5357942045722281361197515306244393730246213029098529617181
8442242835220837604
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.58097468289115001015838947580129147280991527313900496254068549383058278677032
Short name T362
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.06 seconds
Started Oct 22 01:45:02 PM PDT 23
Finished Oct 22 01:45:27 PM PDT 23
Peak memory 211656 kb
Host smart-2e7d6458-4fb8-40fa-a32d-c33fe8f5b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58097468289115001015838947580129147280991527313900496254068549383058278677032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rom_ctrl_kmac_err_chk.58097468289115001015838947580129147280991527313900496254068549383058278677032
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.67681771583049151393904372953458581913815248851734251141269734675508872578176
Short name T222
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.4 seconds
Started Oct 22 01:44:43 PM PDT 23
Finished Oct 22 01:44:57 PM PDT 23
Peak memory 211164 kb
Host smart-800994c0-ca29-4dd6-93e0-cfbc5b779535
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67681771583049151393904372953458581913815248851734251141269734675508872578176 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.67681771583049151393904372953458581913815248851734251141269734675508872578176
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.86061078365649813692886068657739572716071795775922789428184991022242816001840
Short name T29
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.99 seconds
Started Oct 22 01:44:16 PM PDT 23
Finished Oct 22 01:46:11 PM PDT 23
Peak memory 236792 kb
Host smart-0a5e5ad1-726e-421e-bc4e-7556a472ef52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86061078365649813692886068657739572716071795775922789428184991022242816001840 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.86061078365649813692886068657739572716071795775922789428184991022242816001840
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.87758433211393223044043526212579857841935860205042746870273616440502962267961
Short name T352
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.4 seconds
Started Oct 22 01:44:36 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 212804 kb
Host smart-39764f38-ebe3-461a-8f7b-bc9daa9b6c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87758433211393223044043526212579857841935860205042746870273616440502962267961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_smoke.87758433211393223044043526212579857841935860205042746870273616440502962267961
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.64120585135866677094406006541489812491774675725009818861822243284907109857884
Short name T284
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.28 seconds
Started Oct 22 01:44:37 PM PDT 23
Finished Oct 22 01:45:20 PM PDT 23
Peak memory 212860 kb
Host smart-b255bc2b-d325-4f7e-b226-3f025a182a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641205851358666770944060065414898124917746757250098188618222432
84907109857884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.641205851358666770944060065414898124917746757250098
18861822243284907109857884
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.115223878132155242423938992302066021776085357328775733325479238104817804902381
Short name T244
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 22 01:44:56 PM PDT 23
Finished Oct 22 01:45:09 PM PDT 23
Peak memory 211164 kb
Host smart-d92e23b1-9963-466d-a31a-aee6f13578ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115223878132155242423938992302066021776085357328775733325479238104817804902381 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.115223878132155242423938992302066021776085357328775733325479238104817804902381
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.84215126040000596856106620057647014374013125488926105661192047904269161673001
Short name T251
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.5 seconds
Started Oct 22 01:43:26 PM PDT 23
Finished Oct 22 01:49:11 PM PDT 23
Peak memory 237696 kb
Host smart-156d2d05-e987-4b11-a02f-b4000ae9afa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84215126040000596856106620057647014374013125488926105661192047904269161673001 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.842151260400005968561066200576470143740131254889261056611
92047904269161673001
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.53375290255861358210200944450270984761010269553251462428980248124659984165115
Short name T263
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.28 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:20 PM PDT 23
Peak memory 211600 kb
Host smart-65c65386-a4ca-4b3e-8faf-e6c78205a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53375290255861358210200944450270984761010269553251462428980248124659984165115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rom_ctrl_kmac_err_chk.53375290255861358210200944450270984761010269553251462428980248124659984165115
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.106243678347620209211640840869202192858988925767058615417793248311798103567888
Short name T169
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.54 seconds
Started Oct 22 01:45:08 PM PDT 23
Finished Oct 22 01:45:22 PM PDT 23
Peak memory 211136 kb
Host smart-6e64f125-e6f2-4a86-af29-5efabd98ff0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106243678347620209211640840869202192858988925767058615417793248311798103567888 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.106243678347620209211640840869202192858988925767058615417793248311798103567888
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.37103618389606444117451393042378750049374812554355091383078448084720052098072
Short name T320
Test name
Test status
Simulation time 9415977006 ps
CPU time 44 seconds
Started Oct 22 01:44:13 PM PDT 23
Finished Oct 22 01:44:59 PM PDT 23
Peak memory 212968 kb
Host smart-104c1714-a63e-4aa4-ab3a-9cfe614194b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371036183896064441174513930423787500493748125543550913830784480
84720052098072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.37103618389606444117451393042378750049374812554355
091383078448084720052098072
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.75511884607043088346628567281292631359150390761680835774066426342491091817212
Short name T3
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:43:36 PM PDT 23
Peak memory 211200 kb
Host smart-74c0bc12-e7aa-4f18-bfcd-79119621ef54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75511884607043088346628567281292631359150390761680835774066426342491091817212 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.75511884607043088346628567281292631359150390761680835774066426342491091817212
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.45582040630695906865071335618652667189879806606315089453489991597196181818135
Short name T255
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.45 seconds
Started Oct 22 01:44:38 PM PDT 23
Finished Oct 22 01:50:26 PM PDT 23
Peak memory 237656 kb
Host smart-932ef9ae-032a-4f30-8c84-53e2898891e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45582040630695906865071335618652667189879806606315089453489991597196181818135 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.455820406306959068650713356186526671898798066063150894534
89991597196181818135
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.19751204246278106265520355341411598764716968717857174830484857986311616112510
Short name T295
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.38 seconds
Started Oct 22 01:44:34 PM PDT 23
Finished Oct 22 01:44:47 PM PDT 23
Peak memory 211204 kb
Host smart-6104684b-01d6-4c87-ac4c-58d97b59e4b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19751204246278106265520355341411598764716968717857174830484857986311616112510 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.19751204246278106265520355341411598764716968717857174830484857986311616112510
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.36263545545397955504304605078031784101200581496059021965467523020650580030358
Short name T80
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.52 seconds
Started Oct 22 01:44:40 PM PDT 23
Finished Oct 22 01:45:09 PM PDT 23
Peak memory 212852 kb
Host smart-53a03a6e-82c9-4f36-9666-59546799d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36263545545397955504304605078031784101200581496059021965467523020650580030358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_smoke.36263545545397955504304605078031784101200581496059021965467523020650580030358
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.92394553810700182024397828405859791830075995164339444306354608386860812086898
Short name T101
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.25 seconds
Started Oct 22 01:43:22 PM PDT 23
Finished Oct 22 01:44:05 PM PDT 23
Peak memory 212936 kb
Host smart-c923b97c-0d01-47d0-a6bd-d31429d0a382
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923945538107001820243978284058597918300759951643394443063546083
86860812086898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.92394553810700182024397828405859791830075995164339
444306354608386860812086898
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.7163303313802146728205797577981464739009870824879250635237924316671492802953
Short name T326
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 22 01:45:16 PM PDT 23
Finished Oct 22 01:45:28 PM PDT 23
Peak memory 211152 kb
Host smart-c3b01c91-57de-4839-aaa5-03b399d8df3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7163303313802146728205797577981464739009870824879250635237924316671492802953 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.7163303313802146728205797577981464739009870824879250635237924316671492802953
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.97367219705596742663977459032173462944158885218857057922679122311991169451428
Short name T111
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.86 seconds
Started Oct 22 01:44:48 PM PDT 23
Finished Oct 22 01:50:35 PM PDT 23
Peak memory 237724 kb
Host smart-179ecc60-be1a-4926-9b5c-914aadafc196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97367219705596742663977459032173462944158885218857057922679122311991169451428 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.973672197055967426639774590321734629441588852188570579226
79122311991169451428
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.20269064266610687861582598714711944812712075323527236909977670817023369315890
Short name T196
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.71 seconds
Started Oct 22 01:45:34 PM PDT 23
Finished Oct 22 01:46:01 PM PDT 23
Peak memory 211652 kb
Host smart-1856bf25-0ee7-4bf2-af3f-b8962e823ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20269064266610687861582598714711944812712075323527236909977670817023369315890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rom_ctrl_kmac_err_chk.20269064266610687861582598714711944812712075323527236909977670817023369315890
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.33943789362933756939796791742659212863137640052635438575133169548816926895767
Short name T334
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 211104 kb
Host smart-28ee581a-a3fe-4e87-a4f7-e34af222db93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33943789362933756939796791742659212863137640052635438575133169548816926895767 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.33943789362933756939796791742659212863137640052635438575133169548816926895767
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.26353087521250776446305600928900499228713649096827555449752616220054081184329
Short name T76
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.95 seconds
Started Oct 22 01:44:12 PM PDT 23
Finished Oct 22 01:44:41 PM PDT 23
Peak memory 212852 kb
Host smart-b432ec82-d1a9-479b-b29f-d161acf3ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26353087521250776446305600928900499228713649096827555449752616220054081184329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.rom_ctrl_smoke.26353087521250776446305600928900499228713649096827555449752616220054081184329
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.85065037866865448056809063342815729142592614206461547057326536118460224566893
Short name T155
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.07 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:44:11 PM PDT 23
Peak memory 212968 kb
Host smart-00cd2041-baf5-40eb-8681-c0e477893970
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850650378668654480568090633428157291425926142064615470573265361
18460224566893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.85065037866865448056809063342815729142592614206461
547057326536118460224566893
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.35971827465330026824934130307184271817544884265684429497737009547154981726420
Short name T298
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.54 seconds
Started Oct 22 01:45:35 PM PDT 23
Finished Oct 22 01:45:48 PM PDT 23
Peak memory 211168 kb
Host smart-d05e8c6f-2401-4fe1-9fab-2e579f949cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971827465330026824934130307184271817544884265684429497737009547154981726420 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.35971827465330026824934130307184271817544884265684429497737009547154981726420
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.6913087734616866927930012865037985001028489512892016898250979069254070713506
Short name T141
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.3 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:50:52 PM PDT 23
Peak memory 237696 kb
Host smart-f44a6f48-d0a9-4e83-9039-9404cfca38a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6913087734616866927930012865037985001028489512892016898250979069254070713506 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.6913087734616866927930012865037985001028489512892016898250
979069254070713506
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.708227097504881963475798056517322272129395675466445203084244706181445149852
Short name T260
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.61 seconds
Started Oct 22 01:43:21 PM PDT 23
Finished Oct 22 01:43:47 PM PDT 23
Peak memory 211604 kb
Host smart-4befa079-3f2e-4601-be1d-f76b86bcd76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708227097504881963475798056517322272129395675466445203084244706181445149852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ba
se_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.rom_ctrl_kmac_err_chk.708227097504881963475798056517322272129395675466445203084244706181445149852
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.54370387605433676476565016837059978803260309034180676401404067950936457786540
Short name T311
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 22 01:45:51 PM PDT 23
Finished Oct 22 01:46:05 PM PDT 23
Peak memory 211136 kb
Host smart-2bd94a29-a4e7-46cf-b8f1-d5ee909bd4da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54370387605433676476565016837059978803260309034180676401404067950936457786540 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.54370387605433676476565016837059978803260309034180676401404067950936457786540
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2326888183338763896424967280129919985802623110023103975110821845403981683730
Short name T130
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.24 seconds
Started Oct 22 01:45:54 PM PDT 23
Finished Oct 22 01:46:23 PM PDT 23
Peak memory 212808 kb
Host smart-a22aa43f-c4f2-4659-b2d6-c7bc7dcb436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326888183338763896424967280129919985802623110023103975110821845403981683730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.rom_ctrl_smoke.2326888183338763896424967280129919985802623110023103975110821845403981683730
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1289689508760532222944301786274726258055781183825321357100102198159991131248
Short name T6
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.36 seconds
Started Oct 22 01:44:46 PM PDT 23
Finished Oct 22 01:45:29 PM PDT 23
Peak memory 212976 kb
Host smart-663bd2af-b24d-44a8-9ceb-8bc0fa24e674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128968950876053222294430178627472625805578118382532135710010219
8159991131248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.128968950876053222294430178627472625805578118382532
1357100102198159991131248
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.51837587108464524719957127598772007986767757882628365313525004651695030974973
Short name T248
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 22 01:46:07 PM PDT 23
Finished Oct 22 01:46:20 PM PDT 23
Peak memory 211192 kb
Host smart-48c14317-f6d9-44e8-97ee-7b1e7811a583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51837587108464524719957127598772007986767757882628365313525004651695030974973 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.51837587108464524719957127598772007986767757882628365313525004651695030974973
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.93150641373781828208524530480306475081627181270816379789619458513044265156456
Short name T183
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.77 seconds
Started Oct 22 01:45:59 PM PDT 23
Finished Oct 22 01:51:44 PM PDT 23
Peak memory 237752 kb
Host smart-45a8b894-0add-4daa-b79e-8451ecfd8b11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93150641373781828208524530480306475081627181270816379789619458513044265156456 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.931506413737818282085245304803064750816271812708163797896
19458513044265156456
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.79166955620854878582428064467122610105862508022740490254200782280692481567472
Short name T227
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.77 seconds
Started Oct 22 01:46:09 PM PDT 23
Finished Oct 22 01:46:35 PM PDT 23
Peak memory 211656 kb
Host smart-8a211cd1-a0e4-482a-9b19-52a7ec5c2117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79166955620854878582428064467122610105862508022740490254200782280692481567472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.79166955620854878582428064467122610105862508022740490254200782280692481567472
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.110617786132198739536666622755517738127605897178086149455494527537811840941787
Short name T166
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.44 seconds
Started Oct 22 01:46:07 PM PDT 23
Finished Oct 22 01:46:21 PM PDT 23
Peak memory 211156 kb
Host smart-fced1db6-f2fb-41d5-98cc-45c8fae817af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110617786132198739536666622755517738127605897178086149455494527537811840941787 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.110617786132198739536666622755517738127605897178086149455494527537811840941787
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.38339808113658286242925856669332743904234674923807716983782283807281827672628
Short name T283
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.43 seconds
Started Oct 22 01:45:39 PM PDT 23
Finished Oct 22 01:46:08 PM PDT 23
Peak memory 212776 kb
Host smart-5ff0f3a0-bab6-4f8e-9028-aba1bba08068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38339808113658286242925856669332743904234674923807716983782283807281827672628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_smoke.38339808113658286242925856669332743904234674923807716983782283807281827672628
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.57540373220597662174860819838386694661776007570466763863511853371447500173533
Short name T173
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.2 seconds
Started Oct 22 01:45:42 PM PDT 23
Finished Oct 22 01:46:26 PM PDT 23
Peak memory 212912 kb
Host smart-59a39aaf-fba9-4df0-8a9a-df538e085381
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575403732205976621748608198383866946617760075704667638635118533
71447500173533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.57540373220597662174860819838386694661776007570466
763863511853371447500173533
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.63309651759462860966519168139540702226054027298275716031381344157610426512642
Short name T128
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:43:39 PM PDT 23
Peak memory 211104 kb
Host smart-49e0bc9a-551a-4933-8ad1-e03f89111ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63309651759462860966519168139540702226054027298275716031381344157610426512642 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.63309651759462860966519168139540702226054027298275716031381344157610426512642
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.19772382125617487445134058212187083242184578525012265495233007979690093982179
Short name T262
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.73 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:49:12 PM PDT 23
Peak memory 237636 kb
Host smart-5d3b6bc7-93c5-4a11-aadd-f67d24d6ee14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772382125617487445134058212187083242184578525012265495233007979690093982179 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.197723821256174874451340582121870832421845785250122654952
33007979690093982179
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.66348759584145010262547186044356723795111075123405567525699805740491071495339
Short name T174
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.47 seconds
Started Oct 22 01:44:46 PM PDT 23
Finished Oct 22 01:45:12 PM PDT 23
Peak memory 211596 kb
Host smart-d005948d-4588-45a9-a1f2-22eb327175bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66348759584145010262547186044356723795111075123405567525699805740491071495339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.66348759584145010262547186044356723795111075123405567525699805740491071495339
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.52008680184524031470000130957296462147645622829875906410435473240701437283719
Short name T189
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.47 seconds
Started Oct 22 01:44:48 PM PDT 23
Finished Oct 22 01:45:02 PM PDT 23
Peak memory 211244 kb
Host smart-eb41906e-0b0d-490c-88db-a395e00b719a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52008680184524031470000130957296462147645622829875906410435473240701437283719 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.52008680184524031470000130957296462147645622829875906410435473240701437283719
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.96643087049515714436514935387223426744305071025247432625223171352713943161850
Short name T13
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.26 seconds
Started Oct 22 01:46:08 PM PDT 23
Finished Oct 22 01:46:37 PM PDT 23
Peak memory 212788 kb
Host smart-b24a4123-65cd-4cee-9bd7-0f009ce63f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96643087049515714436514935387223426744305071025247432625223171352713943161850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.96643087049515714436514935387223426744305071025247432625223171352713943161850
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.75971862768366911314755243244877091928494526639243073686213543815382354480670
Short name T281
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.68 seconds
Started Oct 22 01:46:09 PM PDT 23
Finished Oct 22 01:46:52 PM PDT 23
Peak memory 212968 kb
Host smart-c9a2f875-f3f3-44f9-9e78-081721836e59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759718627683669113147552432448770919284945266392430736862135438
15382354480670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.75971862768366911314755243244877091928494526639243
073686213543815382354480670
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.112518577769594547654562672503482466991451918941876538839444726673717393851429
Short name T124
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Oct 22 01:44:58 PM PDT 23
Finished Oct 22 01:45:11 PM PDT 23
Peak memory 211168 kb
Host smart-ad7f1087-4e5c-4d12-94c3-abcc1699c187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112518577769594547654562672503482466991451918941876538839444726673717393851429 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.112518577769594547654562672503482466991451918941876538839444726673717393851429
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.50142667514675169247120183193925068178858434227916167791174186760698561459544
Short name T205
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.23 seconds
Started Oct 22 01:44:32 PM PDT 23
Finished Oct 22 01:50:10 PM PDT 23
Peak memory 237664 kb
Host smart-6bb7040b-3dd3-4121-b41b-228475f184a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50142667514675169247120183193925068178858434227916167791174186760698561459544 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.501426675146751692471201831939250681788584342279161677911
74186760698561459544
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.9787848014824438610527949525077618671279700318291320612541488722718787104313
Short name T304
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.49 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:51 PM PDT 23
Peak memory 211648 kb
Host smart-7bd2f963-a602-46ed-a274-64f5680c3319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9787848014824438610527949525077618671279700318291320612541488722718787104313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.rom_ctrl_kmac_err_chk.9787848014824438610527949525077618671279700318291320612541488722718787104313
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1122161359804639594165142193934531187374398449087316985394043724187424728356
Short name T142
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.42 seconds
Started Oct 22 01:43:31 PM PDT 23
Finished Oct 22 01:44:00 PM PDT 23
Peak memory 212744 kb
Host smart-238191b2-3c99-442b-8fa1-be69a25db560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122161359804639594165142193934531187374398449087316985394043724187424728356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.rom_ctrl_smoke.1122161359804639594165142193934531187374398449087316985394043724187424728356
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.33221879563927829008845864216564953481225611392162724722017499459198540590882
Short name T242
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.65 seconds
Started Oct 22 01:44:38 PM PDT 23
Finished Oct 22 01:45:22 PM PDT 23
Peak memory 212984 kb
Host smart-59fc9a50-03f6-4cd1-af21-7cf0a34bbeb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332218795639278290088458642165649534812256113921627247220174994
59198540590882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.33221879563927829008845864216564953481225611392162
724722017499459198540590882
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.49696316120032189962641668406071893430242089938326909299278321541860575279657
Short name T328
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 22 01:44:57 PM PDT 23
Finished Oct 22 01:45:09 PM PDT 23
Peak memory 211188 kb
Host smart-8270a16e-8afe-4e79-b63c-c071b14e8c07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49696316120032189962641668406071893430242089938326909299278321541860575279657 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.49696316120032189962641668406071893430242089938326909299278321541860575279657
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.104361168825905755891663285071983955828446243010727034171672481934682150970283
Short name T259
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.39 seconds
Started Oct 22 01:43:38 PM PDT 23
Finished Oct 22 01:49:16 PM PDT 23
Peak memory 237612 kb
Host smart-6143bb9e-319d-4803-8df2-5f7dc262362a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104361168825905755891663285071983955828446243010727034171672481934682150970283 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.10436116882590575589166328507198395582844624301072703417
1672481934682150970283
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4501127297685155961056480558167473329371990763957749763039536767848651496753
Short name T341
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.68 seconds
Started Oct 22 01:43:23 PM PDT 23
Finished Oct 22 01:43:49 PM PDT 23
Peak memory 211652 kb
Host smart-f04dad27-f881-4112-908d-a619cc71a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4501127297685155961056480558167473329371990763957749763039536767848651496753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.rom_ctrl_kmac_err_chk.4501127297685155961056480558167473329371990763957749763039536767848651496753
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.72176504199040275002868434803253826518803563342831959904195997377247000797037
Short name T168
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 22 01:43:29 PM PDT 23
Finished Oct 22 01:43:43 PM PDT 23
Peak memory 211120 kb
Host smart-1bf4ef9d-762c-47d2-b1a1-b71125c2fe1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72176504199040275002868434803253826518803563342831959904195997377247000797037 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.72176504199040275002868434803253826518803563342831959904195997377247000797037
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.105087020188195022986374776007529115865786095750640272636063027690344694722185
Short name T368
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.3 seconds
Started Oct 22 01:43:31 PM PDT 23
Finished Oct 22 01:44:00 PM PDT 23
Peak memory 212864 kb
Host smart-5404bfbc-c07c-4fa8-89cc-51dcaca5c67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105087020188195022986374776007529115865786095750640272636063027690344694722185 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.rom_ctrl_smoke.105087020188195022986374776007529115865786095750640272636063027690344694722185
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.55533468821644897208543275497273699605087186775994998542891468739182158834309
Short name T271
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.69 seconds
Started Oct 22 01:43:27 PM PDT 23
Finished Oct 22 01:44:10 PM PDT 23
Peak memory 212988 kb
Host smart-dd27f196-e24c-43b3-9273-37628ad52e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555334688216448972085432754972736996050871867759949985428914687
39182158834309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.55533468821644897208543275497273699605087186775994
998542891468739182158834309
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.80763888916598555575749752233498215489118889957131749779228326847477681842768
Short name T144
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:37 PM PDT 23
Peak memory 211144 kb
Host smart-eaa6f58b-3316-4937-b003-3ed1f659b44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80763888916598555575749752233498215489118889957131749779228326847477681842768 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.80763888916598555575749752233498215489118889957131749779228326847477681842768
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3612944442116056474811478460737538856997536789455745572302735430464555428611
Short name T114
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.97 seconds
Started Oct 22 01:43:36 PM PDT 23
Finished Oct 22 01:49:18 PM PDT 23
Peak memory 237612 kb
Host smart-bebe1413-6937-4653-9d04-1c1adc5e5629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612944442116056474811478460737538856997536789455745572302735430464555428611 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.3612944442116056474811478460737538856997536789455745572302
735430464555428611
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.23567262271184635593054801774655645748641554070761581928076672853824310619382
Short name T107
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.09 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:43:55 PM PDT 23
Peak memory 211660 kb
Host smart-cebfc40f-c74c-4e76-bbd7-fc29b42560cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23567262271184635593054801774655645748641554070761581928076672853824310619382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.23567262271184635593054801774655645748641554070761581928076672853824310619382
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.39589922376286651025434818232854621315389142549427340072937010143918482079940
Short name T250
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Oct 22 01:45:00 PM PDT 23
Finished Oct 22 01:45:14 PM PDT 23
Peak memory 211160 kb
Host smart-d1883aa8-dda7-4039-b6c1-816403535c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39589922376286651025434818232854621315389142549427340072937010143918482079940 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.39589922376286651025434818232854621315389142549427340072937010143918482079940
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.27262110911789239311081207201662686923414467498786222894802085442050874669270
Short name T159
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.86 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:43:57 PM PDT 23
Peak memory 212848 kb
Host smart-d83e2eed-69ee-4a11-965f-ada4d076a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27262110911789239311081207201662686923414467498786222894802085442050874669270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.27262110911789239311081207201662686923414467498786222894802085442050874669270
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.84926171746485904270555428334687055551082619880946066781880485729038582777495
Short name T150
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.46 seconds
Started Oct 22 01:44:59 PM PDT 23
Finished Oct 22 01:45:42 PM PDT 23
Peak memory 212960 kb
Host smart-e81d1561-9b65-44cc-937c-6b0325f2a0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849261717464859042705554283346870555510826198809460667818804857
29038582777495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.84926171746485904270555428334687055551082619880946
066781880485729038582777495
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.24437660670399949200637017883554136657026487193453622715860177547753477673199
Short name T336
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Oct 22 01:45:00 PM PDT 23
Finished Oct 22 01:45:12 PM PDT 23
Peak memory 211148 kb
Host smart-eeb40318-eb8a-4155-8fd1-ea27ae1bbfaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437660670399949200637017883554136657026487193453622715860177547753477673199 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.24437660670399949200637017883554136657026487193453622715860177547753477673199
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.46171941882538672391322125409546210318214899682615160947591169274084311640822
Short name T289
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.08 seconds
Started Oct 22 01:44:17 PM PDT 23
Finished Oct 22 01:50:08 PM PDT 23
Peak memory 237704 kb
Host smart-dd75fc53-1b26-4d79-9158-b7cb66786228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46171941882538672391322125409546210318214899682615160947591169274084311640822 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.461719418825386723913221254095462103182148996826151609475
91169274084311640822
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.46280822640555313867514655170410718081141478712701589796832656068467472523110
Short name T176
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Oct 22 01:45:06 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 211592 kb
Host smart-66f51cd5-826a-49b4-9b3d-c8977d02373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46280822640555313867514655170410718081141478712701589796832656068467472523110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.rom_ctrl_kmac_err_chk.46280822640555313867514655170410718081141478712701589796832656068467472523110
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.6299136375590175019649050451955416701071460440926053273948479952025884202287
Short name T78
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.31 seconds
Started Oct 22 01:45:22 PM PDT 23
Finished Oct 22 01:45:36 PM PDT 23
Peak memory 211180 kb
Host smart-6928f8fa-839b-4266-b87e-25c9e71ab255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6299136375590175019649050451955416701071460440926053273948479952025884202287 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.6299136375590175019649050451955416701071460440926053273948479952025884202287
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.53211116174163506948709253411130923736778742529073952293971801802443211521782
Short name T273
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.73 seconds
Started Oct 22 01:44:16 PM PDT 23
Finished Oct 22 01:44:45 PM PDT 23
Peak memory 212800 kb
Host smart-13cd11cb-d38e-45b3-b683-e9a44efb81e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53211116174163506948709253411130923736778742529073952293971801802443211521782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_smoke.53211116174163506948709253411130923736778742529073952293971801802443211521782
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.30609832087215580200914962390945647567080302194099866422963699228285271203039
Short name T349
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.86 seconds
Started Oct 22 01:44:15 PM PDT 23
Finished Oct 22 01:44:58 PM PDT 23
Peak memory 212964 kb
Host smart-58954561-2c17-4e25-ae69-b98c44ea0a0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306098320872155802009149623909456475670803021940998664229636992
28285271203039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.30609832087215580200914962390945647567080302194099
866422963699228285271203039
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.15543184179129412105828707460013632297113600915687235482691984716394992965237
Short name T302
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 22 01:44:32 PM PDT 23
Finished Oct 22 01:44:45 PM PDT 23
Peak memory 211212 kb
Host smart-e541fc7a-8a2d-442f-a521-8cfab045f9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15543184179129412105828707460013632297113600915687235482691984716394992965237 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.15543184179129412105828707460013632297113600915687235482691984716394992965237
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.96586760286107951826346946944737001449593247361928040120058029665442121776812
Short name T134
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.05 seconds
Started Oct 22 01:43:21 PM PDT 23
Finished Oct 22 01:49:07 PM PDT 23
Peak memory 237664 kb
Host smart-fcde0775-1c40-4d13-9126-5f4bc36ce2c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96586760286107951826346946944737001449593247361928040120058029665442121776812 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.9658676028610795182634694694473700144959324736192804012005
8029665442121776812
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.89531229476075237463855646238528429514381614792770154080332577710765072431309
Short name T253
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.29 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 211632 kb
Host smart-fc4f3c0d-e175-4139-a086-32d2d5cbeba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89531229476075237463855646238528429514381614792770154080332577710765072431309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.rom_ctrl_kmac_err_chk.89531229476075237463855646238528429514381614792770154080332577710765072431309
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.15824295693215703957070214617034939703633726791275865780863411112948892523039
Short name T347
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211172 kb
Host smart-96768642-cba4-4996-8502-d962b0ba59cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15824295693215703957070214617034939703633726791275865780863411112948892523039 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.15824295693215703957070214617034939703633726791275865780863411112948892523039
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.30983671808450887094516467808425175124534820357959686178151195256120594465370
Short name T28
Test name
Test status
Simulation time 3444857586 ps
CPU time 115.65 seconds
Started Oct 22 01:44:38 PM PDT 23
Finished Oct 22 01:46:34 PM PDT 23
Peak memory 236824 kb
Host smart-8ece2fd7-7100-43a5-8839-cdc6b8efea28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983671808450887094516467808425175124534820357959686178151195256120594465370 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.30983671808450887094516467808425175124534820357959686178151195256120594465370
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.12953114667140408573725731164518605977282415451903063076911944755609364038600
Short name T210
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.07 seconds
Started Oct 22 01:45:14 PM PDT 23
Finished Oct 22 01:45:44 PM PDT 23
Peak memory 212856 kb
Host smart-df3d52d9-ccac-4e30-8dad-71b4b256f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12953114667140408573725731164518605977282415451903063076911944755609364038600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.12953114667140408573725731164518605977282415451903063076911944755609364038600
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.75828742078956083667858565313896273793826808680385496660286014491191096655863
Short name T184
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.36 seconds
Started Oct 22 01:44:17 PM PDT 23
Finished Oct 22 01:45:01 PM PDT 23
Peak memory 212940 kb
Host smart-c7a9d2c0-ccc7-45a2-bdcf-63a2bbe42262
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758287420789560836678585653138962737938268086803854966602860144
91191096655863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.758287420789560836678585653138962737938268086803854
96660286014491191096655863
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.14604062407912674997873309439771355898687544208413487812508147009820195027964
Short name T285
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.62 seconds
Started Oct 22 01:44:53 PM PDT 23
Finished Oct 22 01:45:06 PM PDT 23
Peak memory 211140 kb
Host smart-73c45797-ead6-44a0-b9fa-22b21c3f2fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14604062407912674997873309439771355898687544208413487812508147009820195027964 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.14604062407912674997873309439771355898687544208413487812508147009820195027964
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.49726824954380647378578536594046099060727687033690415134857693260709991096824
Short name T188
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.31 seconds
Started Oct 22 01:45:35 PM PDT 23
Finished Oct 22 01:51:21 PM PDT 23
Peak memory 237612 kb
Host smart-49d10520-f7a3-4cc9-a9b7-e03634e5cf08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49726824954380647378578536594046099060727687033690415134857693260709991096824 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.497268249543806473785785365940460990607276870336904151348
57693260709991096824
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.5834592486170539143404132150996626794652847756645567805910877044889957566770
Short name T254
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.25 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:46:03 PM PDT 23
Peak memory 211652 kb
Host smart-5ba791e8-93a1-4909-a8fe-15e45a0fea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5834592486170539143404132150996626794652847756645567805910877044889957566770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.rom_ctrl_kmac_err_chk.5834592486170539143404132150996626794652847756645567805910877044889957566770
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2573074689607598488562073448634139302401968235891733204360380043464209134398
Short name T154
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.48 seconds
Started Oct 22 01:44:53 PM PDT 23
Finished Oct 22 01:45:07 PM PDT 23
Peak memory 211188 kb
Host smart-2bc33327-5d61-42e9-9e61-d8f1beb9d4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573074689607598488562073448634139302401968235891733204360380043464209134398 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2573074689607598488562073448634139302401968235891733204360380043464209134398
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.7468205839234881167420623361984803521387735991582910089942023658156933706056
Short name T303
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.22 seconds
Started Oct 22 01:45:13 PM PDT 23
Finished Oct 22 01:45:42 PM PDT 23
Peak memory 212808 kb
Host smart-cc44f0e7-77df-45fb-b595-4b3abd16fead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7468205839234881167420623361984803521387735991582910089942023658156933706056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.rom_ctrl_smoke.7468205839234881167420623361984803521387735991582910089942023658156933706056
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.54609700013514110637907855047053516646255920546665108026938775325115599896587
Short name T219
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.18 seconds
Started Oct 22 01:45:04 PM PDT 23
Finished Oct 22 01:45:47 PM PDT 23
Peak memory 212908 kb
Host smart-0775751c-99b5-4018-8b9d-1d2ad9c1dc8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546097000135141106379078550470535166462559205466651080269387753
25115599896587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.54609700013514110637907855047053516646255920546665
108026938775325115599896587
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1677663437835951127874650845037026668160060628443736347425467878815147762599
Short name T30
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 22 01:43:29 PM PDT 23
Finished Oct 22 01:43:41 PM PDT 23
Peak memory 211152 kb
Host smart-cc64858f-c943-44d7-ae2d-fad392c48fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677663437835951127874650845037026668160060628443736347425467878815147762599 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1677663437835951127874650845037026668160060628443736347425467878815147762599
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.109029365952091025783873801981803474263411306297460907765983548339794826705618
Short name T249
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.31 seconds
Started Oct 22 01:44:57 PM PDT 23
Finished Oct 22 01:50:44 PM PDT 23
Peak memory 237792 kb
Host smart-701ff0c2-8291-44f9-8582-798154c65133
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109029365952091025783873801981803474263411306297460907765983548339794826705618 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.10902936595209102578387380198180347426341130629746090776
5983548339794826705618
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.7466391513930257748182216444058664625354379971815367542627172902285880422958
Short name T321
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.28 seconds
Started Oct 22 01:43:29 PM PDT 23
Finished Oct 22 01:43:56 PM PDT 23
Peak memory 211592 kb
Host smart-7e764e56-c47e-4a31-af68-ef2e16ea00ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7466391513930257748182216444058664625354379971815367542627172902285880422958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.rom_ctrl_kmac_err_chk.7466391513930257748182216444058664625354379971815367542627172902285880422958
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.17211320681875821913786671155577510550357366271228402459185586808871235855655
Short name T131
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 22 01:44:45 PM PDT 23
Finished Oct 22 01:44:59 PM PDT 23
Peak memory 211224 kb
Host smart-07809af4-368b-43e4-bb9d-00427e37acd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17211320681875821913786671155577510550357366271228402459185586808871235855655 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.17211320681875821913786671155577510550357366271228402459185586808871235855655
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.102158492327671686540611551646336727298148120995767405216401353372265021669268
Short name T292
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.54 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:55 PM PDT 23
Peak memory 212836 kb
Host smart-0c7acc34-421c-410a-99ad-fda9322906d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102158492327671686540611551646336727298148120995767405216401353372265021669268 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_smoke.102158492327671686540611551646336727298148120995767405216401353372265021669268
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.68234748694806394524830098075373895754615306235962939014794650382231791743576
Short name T293
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.42 seconds
Started Oct 22 01:45:01 PM PDT 23
Finished Oct 22 01:45:44 PM PDT 23
Peak memory 212968 kb
Host smart-d0a3a58a-8588-4844-a4ec-2b0022bf140c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682347486948063945248300980753738957546153062359629390147946503
82231791743576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.68234748694806394524830098075373895754615306235962
939014794650382231791743576
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.83160316035643485652085823782646463386129740542556389864911883475455552283908
Short name T233
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.6 seconds
Started Oct 22 01:44:12 PM PDT 23
Finished Oct 22 01:44:25 PM PDT 23
Peak memory 211196 kb
Host smart-dbb467c8-c0c3-4e84-bde4-171cf2d78a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83160316035643485652085823782646463386129740542556389864911883475455552283908 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.83160316035643485652085823782646463386129740542556389864911883475455552283908
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.67679370494685633790769203773887981529808507342008544628101834824250598980973
Short name T239
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.75 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:50:32 PM PDT 23
Peak memory 237648 kb
Host smart-fd218a9a-ad0b-46e8-aed7-0068779a0195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67679370494685633790769203773887981529808507342008544628101834824250598980973 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.676793704946856337907692037738879815298085073420085446281
01834824250598980973
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.38104254692221821656366584646943670269692833825802917678895623231918352292083
Short name T266
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.66 seconds
Started Oct 22 01:44:44 PM PDT 23
Finished Oct 22 01:45:10 PM PDT 23
Peak memory 211660 kb
Host smart-a603ad52-2d51-4a78-898a-1ca8e84a6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38104254692221821656366584646943670269692833825802917678895623231918352292083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.rom_ctrl_kmac_err_chk.38104254692221821656366584646943670269692833825802917678895623231918352292083
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.56927764684425221433051665484996183510688428573416929894973217783716205099125
Short name T272
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.47 seconds
Started Oct 22 01:44:18 PM PDT 23
Finished Oct 22 01:44:32 PM PDT 23
Peak memory 211204 kb
Host smart-7053b9ad-909b-4535-a2a7-3a3540467e2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=56927764684425221433051665484996183510688428573416929894973217783716205099125 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.56927764684425221433051665484996183510688428573416929894973217783716205099125
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.78348993355507301752013708580653382508156861427161037234288862673083959993202
Short name T209
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.04 seconds
Started Oct 22 01:44:39 PM PDT 23
Finished Oct 22 01:45:07 PM PDT 23
Peak memory 212808 kb
Host smart-6237f9f4-ae3c-419b-ba6e-dfd3b0cf6d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78348993355507301752013708580653382508156861427161037234288862673083959993202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_smoke.78348993355507301752013708580653382508156861427161037234288862673083959993202
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.97637324302315652739497160028353835176010657246572167661697094241886135122815
Short name T137
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.47 seconds
Started Oct 22 01:44:39 PM PDT 23
Finished Oct 22 01:45:22 PM PDT 23
Peak memory 212956 kb
Host smart-41da5303-0e51-4e88-b74c-ff1213e15cb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976373243023156527394971600283538351760106572465721676616970942
41886135122815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.97637324302315652739497160028353835176010657246572
167661697094241886135122815
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.59965818014389148214705382362373005484531809201880951912970247758173836947205
Short name T294
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 22 01:45:55 PM PDT 23
Finished Oct 22 01:46:07 PM PDT 23
Peak memory 211224 kb
Host smart-99dcfd29-31f2-432b-93f4-c0403063b15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59965818014389148214705382362373005484531809201880951912970247758173836947205 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.59965818014389148214705382362373005484531809201880951912970247758173836947205
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.45207071466569881386498364132278781974818495981312673764265744248611793322787
Short name T199
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.48 seconds
Started Oct 22 01:45:50 PM PDT 23
Finished Oct 22 01:51:30 PM PDT 23
Peak memory 237648 kb
Host smart-4584040b-cdff-4ad3-a99a-0ab20c4bd999
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45207071466569881386498364132278781974818495981312673764265744248611793322787 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.452070714665698813864983641322787819748184959813126737642
65744248611793322787
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.107949628622721684876702004460306137550606779430143493332940748434560946827571
Short name T100
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.16 seconds
Started Oct 22 01:45:55 PM PDT 23
Finished Oct 22 01:46:21 PM PDT 23
Peak memory 211584 kb
Host smart-a90a555e-4507-48a8-a2ad-2d39a5bd6394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107949628622721684876702004460306137550606779430143493332940748434560946827571 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.rom_ctrl_kmac_err_chk.107949628622721684876702004460306137550606779430143493332940748434560946827571
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.112571016605950046081487713457282614081587945519180331196878755199233055185228
Short name T365
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.42 seconds
Started Oct 22 01:45:33 PM PDT 23
Finished Oct 22 01:45:47 PM PDT 23
Peak memory 211236 kb
Host smart-8475057e-cef0-4972-ae84-7518d309f833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112571016605950046081487713457282614081587945519180331196878755199233055185228 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.112571016605950046081487713457282614081587945519180331196878755199233055185228
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.20721162023331005545059992007422114012481276898209231697712739137443986372517
Short name T256
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.24 seconds
Started Oct 22 01:45:22 PM PDT 23
Finished Oct 22 01:45:51 PM PDT 23
Peak memory 212856 kb
Host smart-a9f50c56-c865-4155-bd7b-50af66b046b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20721162023331005545059992007422114012481276898209231697712739137443986372517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.20721162023331005545059992007422114012481276898209231697712739137443986372517
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.6339513469352275010137651205570252850761900464726912883776058024269932188798
Short name T357
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.42 seconds
Started Oct 22 01:45:20 PM PDT 23
Finished Oct 22 01:46:05 PM PDT 23
Peak memory 212944 kb
Host smart-0d344496-011a-4b7a-9d5c-8e1f061c8c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633951346935227501013765120557025285076190046472691288377605802
4269932188798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.633951346935227501013765120557025285076190046472691
2883776058024269932188798
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.12908799538105954611671185580905096217874422681535107211275867926704829383035
Short name T305
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Oct 22 01:45:34 PM PDT 23
Finished Oct 22 01:45:47 PM PDT 23
Peak memory 211172 kb
Host smart-e9069ced-2c2c-4147-bccb-6f36953e4efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12908799538105954611671185580905096217874422681535107211275867926704829383035 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.12908799538105954611671185580905096217874422681535107211275867926704829383035
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.59514386631262676168448617003788095881548836351545726066154361718520100816231
Short name T43
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.9 seconds
Started Oct 22 01:45:41 PM PDT 23
Finished Oct 22 01:51:28 PM PDT 23
Peak memory 237724 kb
Host smart-8e43b1ce-4c06-48a6-b44a-afa8db701888
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59514386631262676168448617003788095881548836351545726066154361718520100816231 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.595143866312626761684486170037880958815488363515457260661
54361718520100816231
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.47793068677719149211393437576740209535807585858079002327685432088697696003756
Short name T192
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.99 seconds
Started Oct 22 01:45:56 PM PDT 23
Finished Oct 22 01:46:23 PM PDT 23
Peak memory 211656 kb
Host smart-3dcbb295-90c4-49f1-8894-4763116959bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47793068677719149211393437576740209535807585858079002327685432088697696003756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rom_ctrl_kmac_err_chk.47793068677719149211393437576740209535807585858079002327685432088697696003756
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.37445910863686890394769085526845277079248222346863742149516490947721611968328
Short name T11
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.19 seconds
Started Oct 22 01:45:25 PM PDT 23
Finished Oct 22 01:45:39 PM PDT 23
Peak memory 211168 kb
Host smart-cb54faee-8e29-4a9a-98ba-c687fa8989c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37445910863686890394769085526845277079248222346863742149516490947721611968328 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.37445910863686890394769085526845277079248222346863742149516490947721611968328
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.42744896032900702451203274163629222788415867134455676384548700114970531611759
Short name T37
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.49 seconds
Started Oct 22 01:45:34 PM PDT 23
Finished Oct 22 01:46:03 PM PDT 23
Peak memory 212768 kb
Host smart-ab742e7f-d445-4cbc-9d44-0ad7cc9dd3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42744896032900702451203274163629222788415867134455676384548700114970531611759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.rom_ctrl_smoke.42744896032900702451203274163629222788415867134455676384548700114970531611759
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.110309217050926168622001708724581470372031959284939205208235292160381757762207
Short name T103
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.73 seconds
Started Oct 22 01:45:02 PM PDT 23
Finished Oct 22 01:45:45 PM PDT 23
Peak memory 212972 kb
Host smart-612819ab-1863-48b8-a92c-a353b1b47be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110309217050926168622001708724581470372031959284939205208235292
160381757762207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.1103092170509261686220017087245814703720319592849
39205208235292160381757762207
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.55947283400553461441318771458782406765711326250211773478272199907856739802892
Short name T110
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Oct 22 01:44:49 PM PDT 23
Finished Oct 22 01:45:01 PM PDT 23
Peak memory 211188 kb
Host smart-df6ced14-3f4d-49b8-976e-8e77d893feb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55947283400553461441318771458782406765711326250211773478272199907856739802892 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.55947283400553461441318771458782406765711326250211773478272199907856739802892
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.31510015683819375029765565601728839461799906208311603236570696417009528785918
Short name T343
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.15 seconds
Started Oct 22 01:43:27 PM PDT 23
Finished Oct 22 01:49:18 PM PDT 23
Peak memory 237728 kb
Host smart-d1e75093-f168-4564-a9a6-fec72aa36390
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31510015683819375029765565601728839461799906208311603236570696417009528785918 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.315100156838193750297655656017288394617999062083116032365
70696417009528785918
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1632531807342774461663303980108923080838425878535138676757064030799788950507
Short name T149
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.55 seconds
Started Oct 22 01:45:01 PM PDT 23
Finished Oct 22 01:45:27 PM PDT 23
Peak memory 211588 kb
Host smart-10a816a0-dcb7-4733-84ad-0f5367b373e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632531807342774461663303980108923080838425878535138676757064030799788950507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.rom_ctrl_kmac_err_chk.1632531807342774461663303980108923080838425878535138676757064030799788950507
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.31434089389876490134948053156681120298761063823964867241828649941695163586069
Short name T223
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Oct 22 01:44:13 PM PDT 23
Finished Oct 22 01:44:27 PM PDT 23
Peak memory 211204 kb
Host smart-6c39fdc1-326d-4b6b-be52-b024733d81e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31434089389876490134948053156681120298761063823964867241828649941695163586069 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.31434089389876490134948053156681120298761063823964867241828649941695163586069
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.37096916534629342589670758824719667929786366720427833950136492124756441444755
Short name T162
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 22 01:43:27 PM PDT 23
Finished Oct 22 01:43:56 PM PDT 23
Peak memory 212852 kb
Host smart-6d5df327-4115-4950-aa09-2cdb04071f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37096916534629342589670758824719667929786366720427833950136492124756441444755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_smoke.37096916534629342589670758824719667929786366720427833950136492124756441444755
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.35801876189940727231048981044272376445587792362752382233635365360050182333645
Short name T345
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.38 seconds
Started Oct 22 01:44:58 PM PDT 23
Finished Oct 22 01:45:42 PM PDT 23
Peak memory 212976 kb
Host smart-8d98d5aa-1da1-424f-ba5e-c583b337ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358018761899407272310489810442723764455877923627523822336353653
60050182333645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.35801876189940727231048981044272376445587792362752
382233635365360050182333645
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.36108259574160923671921928662232677396313276028411494989895748761690939514576
Short name T367
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211200 kb
Host smart-52008024-5c4f-4cd0-a38e-9470da39a2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36108259574160923671921928662232677396313276028411494989895748761690939514576 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.36108259574160923671921928662232677396313276028411494989895748761690939514576
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.53250611982781503092703553890746625442088418174613227449325546252578390053505
Short name T40
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.9 seconds
Started Oct 22 01:44:16 PM PDT 23
Finished Oct 22 01:49:55 PM PDT 23
Peak memory 237728 kb
Host smart-22344a4c-7cec-4a24-9baa-f6c2a2f32041
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53250611982781503092703553890746625442088418174613227449325546252578390053505 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.532506119827815030927035538907466254420884181746132274493
25546252578390053505
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.79605110444614129888279628808177289037203125885457633194343468650617194071531
Short name T170
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.73 seconds
Started Oct 22 01:44:14 PM PDT 23
Finished Oct 22 01:44:41 PM PDT 23
Peak memory 211648 kb
Host smart-7360df8d-7caa-4fd5-b95a-73c2fee7c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79605110444614129888279628808177289037203125885457633194343468650617194071531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.79605110444614129888279628808177289037203125885457633194343468650617194071531
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.73744629053077497953075707772293545098692733311001871928033494637248666349855
Short name T238
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211168 kb
Host smart-9984631b-042c-4fa4-808d-8b47fefbb00d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73744629053077497953075707772293545098692733311001871928033494637248666349855 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.73744629053077497953075707772293545098692733311001871928033494637248666349855
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.82965880963859182355043172865807501001580423583986048024671120436994678192726
Short name T331
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.14 seconds
Started Oct 22 01:45:04 PM PDT 23
Finished Oct 22 01:45:33 PM PDT 23
Peak memory 212856 kb
Host smart-cb4938d6-b558-4430-94e0-3f31df1600e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82965880963859182355043172865807501001580423583986048024671120436994678192726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.82965880963859182355043172865807501001580423583986048024671120436994678192726
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.38692576857338333499057374910555387191259814164257052208669711610648593561997
Short name T108
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.96 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:44:07 PM PDT 23
Peak memory 212968 kb
Host smart-fc0a65d1-8971-4b5d-b33e-0f62fe35dccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386925768573383334990573749105553871912598141642570522086697116
10648593561997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.38692576857338333499057374910555387191259814164257
052208669711610648593561997
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.54442687896894973361618659835122044955022085573057821555869453900859112532633
Short name T269
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Oct 22 01:45:33 PM PDT 23
Finished Oct 22 01:45:46 PM PDT 23
Peak memory 211124 kb
Host smart-9a6f0132-1db9-49bc-bcd4-d19195f1040c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54442687896894973361618659835122044955022085573057821555869453900859112532633 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.54442687896894973361618659835122044955022085573057821555869453900859112532633
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.108274522985644371386999696391635501891712703895834545216463256901802299988780
Short name T117
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.53 seconds
Started Oct 22 01:45:36 PM PDT 23
Finished Oct 22 01:51:19 PM PDT 23
Peak memory 237708 kb
Host smart-f26fe982-fc92-4348-894d-27e5db61d5dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108274522985644371386999696391635501891712703895834545216463256901802299988780 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.10827452298564437138699969639163550189171270389583454521
6463256901802299988780
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.115160905316537512631942655700981786229967025488563633652538403364988872792971
Short name T171
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.41 seconds
Started Oct 22 01:45:37 PM PDT 23
Finished Oct 22 01:46:03 PM PDT 23
Peak memory 211616 kb
Host smart-b73df6ec-0dcb-41ad-8933-c50ddbffb161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115160905316537512631942655700981786229967025488563633652538403364988872792971 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.rom_ctrl_kmac_err_chk.115160905316537512631942655700981786229967025488563633652538403364988872792971
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.6041520863795788163608563238642228311077228157605198401734409511856941019424
Short name T81
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Oct 22 01:44:56 PM PDT 23
Finished Oct 22 01:45:10 PM PDT 23
Peak memory 211156 kb
Host smart-7fe7ad4a-d39a-4abd-93ff-01404e747118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6041520863795788163608563238642228311077228157605198401734409511856941019424 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.6041520863795788163608563238642228311077228157605198401734409511856941019424
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.71467655916705896027855287856133823357026941313340384513020552951293502391770
Short name T202
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.13 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 212848 kb
Host smart-6a73d776-ca98-4ba8-bf1e-8076987ff43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71467655916705896027855287856133823357026941313340384513020552951293502391770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_smoke.71467655916705896027855287856133823357026941313340384513020552951293502391770
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.96218736962780350199222504530663369379138555052646011253392659206140196949669
Short name T257
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.41 seconds
Started Oct 22 01:44:50 PM PDT 23
Finished Oct 22 01:45:33 PM PDT 23
Peak memory 212972 kb
Host smart-4a161a81-1bc9-47f8-88f8-70b034b3edd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962187369627803501992225045306633693791385550526460112533926592
06140196949669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.96218736962780350199222504530663369379138555052646
011253392659206140196949669
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.55276295769176752880922552845041897755246355390541034211164857427612956571454
Short name T182
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 22 01:45:27 PM PDT 23
Finished Oct 22 01:45:39 PM PDT 23
Peak memory 211180 kb
Host smart-5965714c-057c-4e39-bcac-397ba313710d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55276295769176752880922552845041897755246355390541034211164857427612956571454 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.55276295769176752880922552845041897755246355390541034211164857427612956571454
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.16633339978517783876128275298317104000836118919124569131146780762031376223332
Short name T226
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.67 seconds
Started Oct 22 01:45:55 PM PDT 23
Finished Oct 22 01:51:40 PM PDT 23
Peak memory 237680 kb
Host smart-dfec3fcd-b7f4-488d-971e-bea632929d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633339978517783876128275298317104000836118919124569131146780762031376223332 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.166333399785177838761282752983171040008361189191245691311
46780762031376223332
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.29039654437118359040102625168214252058913373493508994190227382355875453017592
Short name T306
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.72 seconds
Started Oct 22 01:45:46 PM PDT 23
Finished Oct 22 01:46:13 PM PDT 23
Peak memory 211644 kb
Host smart-1281bd55-b3d0-4467-8e67-b9d85a33cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29039654437118359040102625168214252058913373493508994190227382355875453017592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rom_ctrl_kmac_err_chk.29039654437118359040102625168214252058913373493508994190227382355875453017592
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.85241486271303871072527098241612135547580441270413541640164834440163937729999
Short name T178
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.22 seconds
Started Oct 22 01:45:37 PM PDT 23
Finished Oct 22 01:45:51 PM PDT 23
Peak memory 211156 kb
Host smart-07450ff7-d690-4799-bb2f-3bf1d575873d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85241486271303871072527098241612135547580441270413541640164834440163937729999 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.85241486271303871072527098241612135547580441270413541640164834440163937729999
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.18929074796776696314613551479846088719634551079231056068577133106594586170753
Short name T252
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.51 seconds
Started Oct 22 01:46:13 PM PDT 23
Finished Oct 22 01:46:42 PM PDT 23
Peak memory 212808 kb
Host smart-8f381a4d-eb60-4ad0-aa0d-63de933407ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18929074796776696314613551479846088719634551079231056068577133106594586170753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.18929074796776696314613551479846088719634551079231056068577133106594586170753
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.39761152401230908438710593147751030503000722004793398103792025556955655324506
Short name T360
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.51 seconds
Started Oct 22 01:45:33 PM PDT 23
Finished Oct 22 01:46:17 PM PDT 23
Peak memory 212964 kb
Host smart-57459ec0-eaa2-422e-be5e-c0d475a08c41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397611524012309084387105931477510305030007220047933981037920255
56955655324506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.39761152401230908438710593147751030503000722004793
398103792025556955655324506
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.85434062348465067187216329799481301991515593175282394174630882885742439670906
Short name T355
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 22 01:44:58 PM PDT 23
Finished Oct 22 01:45:10 PM PDT 23
Peak memory 211168 kb
Host smart-fe7f5b4e-d225-4086-ab02-c77b5ad715e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85434062348465067187216329799481301991515593175282394174630882885742439670906 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.85434062348465067187216329799481301991515593175282394174630882885742439670906
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.1874575501380163684333127863624705707364597367187336454087567039195591033885
Short name T140
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.17 seconds
Started Oct 22 01:45:03 PM PDT 23
Finished Oct 22 01:50:48 PM PDT 23
Peak memory 237644 kb
Host smart-9d46f425-09aa-4a3f-b46a-3e542841007f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874575501380163684333127863624705707364597367187336454087567039195591033885 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.1874575501380163684333127863624705707364597367187336454087
567039195591033885
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.10416520637565745945250719180140499547364038101626162425798131140479281864822
Short name T138
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.49 seconds
Started Oct 22 01:45:16 PM PDT 23
Finished Oct 22 01:45:43 PM PDT 23
Peak memory 211600 kb
Host smart-9ab7d32e-71f4-43f0-85e6-1ca99ec23c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10416520637565745945250719180140499547364038101626162425798131140479281864822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.10416520637565745945250719180140499547364038101626162425798131140479281864822
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.92919946954910409233024751997757063414430333892811912250544649885697354184968
Short name T179
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.31 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:43:42 PM PDT 23
Peak memory 211224 kb
Host smart-f52c1993-fb0d-4757-a038-9597258bd374
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92919946954910409233024751997757063414430333892811912250544649885697354184968 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.92919946954910409233024751997757063414430333892811912250544649885697354184968
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.57801951345043155948684919810490068215927050959959320998352028225273700602994
Short name T167
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.96 seconds
Started Oct 22 01:44:35 PM PDT 23
Finished Oct 22 01:45:04 PM PDT 23
Peak memory 212844 kb
Host smart-bda63a28-1e52-4fea-adca-4f1b97c9aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57801951345043155948684919810490068215927050959959320998352028225273700602994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.rom_ctrl_smoke.57801951345043155948684919810490068215927050959959320998352028225273700602994
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.17154577748029636218222855352262535544323012000941383179243647113781863072800
Short name T319
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.95 seconds
Started Oct 22 01:43:39 PM PDT 23
Finished Oct 22 01:44:22 PM PDT 23
Peak memory 212916 kb
Host smart-02507d2f-581b-46c2-b863-03995bcf538a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171545777480296362182228553522625355443230120009413831792436471
13781863072800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.17154577748029636218222855352262535544323012000941
383179243647113781863072800
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.105624331462282463718113909058066699213895836577254177207033721349225157566669
Short name T139
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.65 seconds
Started Oct 22 01:44:44 PM PDT 23
Finished Oct 22 01:44:57 PM PDT 23
Peak memory 211236 kb
Host smart-0a48b06e-e97e-4fc1-b334-a24f8133dde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105624331462282463718113909058066699213895836577254177207033721349225157566669 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.105624331462282463718113909058066699213895836577254177207033721349225157566669
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.75089907803346198500206596338414850074756902612361047774854504363547552748450
Short name T118
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.41 seconds
Started Oct 22 01:44:44 PM PDT 23
Finished Oct 22 01:45:10 PM PDT 23
Peak memory 211652 kb
Host smart-818f9d2c-9d90-4d8f-a47c-ea646c71eda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75089907803346198500206596338414850074756902612361047774854504363547552748450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.75089907803346198500206596338414850074756902612361047774854504363547552748450
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.59322178014528743944244048472047469284703779524432937910136155258500219499189
Short name T286
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.19 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211204 kb
Host smart-396af4d3-baf1-4914-9384-5c5c288f0b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59322178014528743944244048472047469284703779524432937910136155258500219499189 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.59322178014528743944244048472047469284703779524432937910136155258500219499189
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.17490179998387200916340540791079220503854751035017275330048247609843499056639
Short name T35
Test name
Test status
Simulation time 3444857586 ps
CPU time 118.15 seconds
Started Oct 22 01:44:32 PM PDT 23
Finished Oct 22 01:46:30 PM PDT 23
Peak memory 236752 kb
Host smart-007e2073-5ea9-4cae-bc01-94ca54fcf534
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490179998387200916340540791079220503854751035017275330048247609843499056639 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.17490179998387200916340540791079220503854751035017275330048247609843499056639
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.26053468466391135295785584251687137820015755262227453423174938712473610834884
Short name T206
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.79 seconds
Started Oct 22 01:43:33 PM PDT 23
Finished Oct 22 01:44:02 PM PDT 23
Peak memory 212804 kb
Host smart-ff3526d6-19c6-4ae5-a2a2-b924c564357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26053468466391135295785584251687137820015755262227453423174938712473610834884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_smoke.26053468466391135295785584251687137820015755262227453423174938712473610834884
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.86539960799101623412164511717307354270800168199384777821233959747633783435868
Short name T172
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.52 seconds
Started Oct 22 01:44:45 PM PDT 23
Finished Oct 22 01:45:28 PM PDT 23
Peak memory 212924 kb
Host smart-8cb1316c-0528-4ec4-ac8a-e9a624bbb8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865399607991016234121645117173073542708001681993847778212339597
47633783435868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.865399607991016234121645117173073542708001681993847
77821233959747633783435868
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.12275805076260310055395460816351094956255710862274900250455355757303662445199
Short name T220
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Oct 22 01:45:03 PM PDT 23
Finished Oct 22 01:45:16 PM PDT 23
Peak memory 211152 kb
Host smart-a572dae6-d0a6-46a8-aba9-ab1f25102fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12275805076260310055395460816351094956255710862274900250455355757303662445199 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.12275805076260310055395460816351094956255710862274900250455355757303662445199
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.63329900689483396352101983431731357566528184064868555112929801395884753165673
Short name T258
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.2 seconds
Started Oct 22 01:43:29 PM PDT 23
Finished Oct 22 01:49:16 PM PDT 23
Peak memory 237732 kb
Host smart-c88139e7-b177-4122-8b65-1d937648abff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63329900689483396352101983431731357566528184064868555112929801395884753165673 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.633299006894833963521019834317313575665281840648685551129
29801395884753165673
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.89969052569687288667130744994040776839680578078638567859956282076937838054157
Short name T261
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.64 seconds
Started Oct 22 01:43:45 PM PDT 23
Finished Oct 22 01:44:11 PM PDT 23
Peak memory 211596 kb
Host smart-cb8cc55e-3f5e-4a68-bf16-44ce9af30321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89969052569687288667130744994040776839680578078638567859956282076937838054157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.rom_ctrl_kmac_err_chk.89969052569687288667130744994040776839680578078638567859956282076937838054157
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.43076070872172494731552324638381229497990564573416589178194555657085404596804
Short name T351
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.22 seconds
Started Oct 22 01:45:08 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 211104 kb
Host smart-a11ae5e6-1624-4015-9664-86e7932a053a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=43076070872172494731552324638381229497990564573416589178194555657085404596804 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.43076070872172494731552324638381229497990564573416589178194555657085404596804
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.33897871818529057881303248370941012511583745464188300934075478578933661189831
Short name T275
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.07 seconds
Started Oct 22 01:43:36 PM PDT 23
Finished Oct 22 01:44:05 PM PDT 23
Peak memory 212856 kb
Host smart-02e997cd-8439-47ed-a625-53d116b6037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33897871818529057881303248370941012511583745464188300934075478578933661189831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_smoke.33897871818529057881303248370941012511583745464188300934075478578933661189831
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.15062272502384532793312452000105210786039905874163178019872592072097417294394
Short name T234
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.11 seconds
Started Oct 22 01:44:59 PM PDT 23
Finished Oct 22 01:45:41 PM PDT 23
Peak memory 212932 kb
Host smart-99b69aeb-0efe-45e4-812c-7a2d9cc6446c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150622725023845327933124520001052107860399058741631780198725920
72097417294394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.15062272502384532793312452000105210786039905874163
178019872592072097417294394
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3819645963785288913374998466103700841473055838800811501876655315368004584422
Short name T102
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211140 kb
Host smart-33d0b07e-dac7-4fee-8e04-99559abf85a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819645963785288913374998466103700841473055838800811501876655315368004584422 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3819645963785288913374998466103700841473055838800811501876655315368004584422
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.5570743854261992658935159787929683957070572384863838445372008991089090549306
Short name T277
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.33 seconds
Started Oct 22 01:45:09 PM PDT 23
Finished Oct 22 01:50:54 PM PDT 23
Peak memory 237572 kb
Host smart-54fefa3b-5e1e-4ae3-b0e0-df14187fb1d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5570743854261992658935159787929683957070572384863838445372008991089090549306 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.5570743854261992658935159787929683957070572384863838445372
008991089090549306
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.107823371089260387907781594427414483323089453871427797666951666102846263819581
Short name T225
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Oct 22 01:44:49 PM PDT 23
Finished Oct 22 01:45:15 PM PDT 23
Peak memory 211644 kb
Host smart-95fb77fd-b92a-4a46-9bf0-7a08e8087193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107823371089260387907781594427414483323089453871427797666951666102846263819581 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rom_ctrl_kmac_err_chk.107823371089260387907781594427414483323089453871427797666951666102846263819581
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.35610623515420075066385598817970216218350222644011722797371344519940344265898
Short name T310
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.5 seconds
Started Oct 22 01:45:06 PM PDT 23
Finished Oct 22 01:45:20 PM PDT 23
Peak memory 211152 kb
Host smart-fe1dc744-20df-4826-85d3-557ae0d1e5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35610623515420075066385598817970216218350222644011722797371344519940344265898 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.35610623515420075066385598817970216218350222644011722797371344519940344265898
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.37562762937303064455305526393168043251076998413355321259781995470231067668016
Short name T121
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.19 seconds
Started Oct 22 01:45:12 PM PDT 23
Finished Oct 22 01:45:46 PM PDT 23
Peak memory 212828 kb
Host smart-9166bece-3fac-4fb8-9a0e-843ca8e11ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37562762937303064455305526393168043251076998413355321259781995470231067668016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.37562762937303064455305526393168043251076998413355321259781995470231067668016
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.24875824389688666748405201718973388751840972383827052873039071447823957441445
Short name T268
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.19 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:45:36 PM PDT 23
Peak memory 212936 kb
Host smart-81e8d94a-0bcf-451b-97bf-cdad5f919a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248758243896886667484052017189733887518409723838270528730390714
47823957441445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.24875824389688666748405201718973388751840972383827
052873039071447823957441445
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.67305163569493265715349369219718375624641591362299143519480627541988470365372
Short name T245
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 22 01:45:43 PM PDT 23
Finished Oct 22 01:45:55 PM PDT 23
Peak memory 211100 kb
Host smart-e1dd827e-92bd-4567-aab8-f43a56188df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67305163569493265715349369219718375624641591362299143519480627541988470365372 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.67305163569493265715349369219718375624641591362299143519480627541988470365372
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.98772004258726224663622910571703283706529173550185712285187912913312995032253
Short name T41
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.32 seconds
Started Oct 22 01:45:40 PM PDT 23
Finished Oct 22 01:51:26 PM PDT 23
Peak memory 237724 kb
Host smart-1e81edd6-4255-498e-92b3-da46e1845311
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98772004258726224663622910571703283706529173550185712285187912913312995032253 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.987720042587262246636229105717032837065291735501857122851
87912913312995032253
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.42038274024320594407928762829649967676881649169323378199572459279867460681915
Short name T181
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.03 seconds
Started Oct 22 01:45:06 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 211624 kb
Host smart-b2222b9e-c24b-49ff-92a2-55a4d6d83e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42038274024320594407928762829649967676881649169323378199572459279867460681915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.rom_ctrl_kmac_err_chk.42038274024320594407928762829649967676881649169323378199572459279867460681915
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.77488674920011715520179448529065254408185302032981905728112126843724759384578
Short name T177
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 22 01:45:45 PM PDT 23
Finished Oct 22 01:45:59 PM PDT 23
Peak memory 211268 kb
Host smart-37fe1ca5-4f3d-4987-a0fa-44e314ac377b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77488674920011715520179448529065254408185302032981905728112126843724759384578 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.77488674920011715520179448529065254408185302032981905728112126843724759384578
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.39144024479078883315264500967387656083371264663494641327514700461076600829604
Short name T152
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.3 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:46:06 PM PDT 23
Peak memory 212860 kb
Host smart-41f801f5-59b5-479e-938f-6c034eeab0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39144024479078883315264500967387656083371264663494641327514700461076600829604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.39144024479078883315264500967387656083371264663494641327514700461076600829604
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.7549971254531497118541155209311931414611641098980440025803003997774612278270
Short name T15
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.71 seconds
Started Oct 22 01:45:02 PM PDT 23
Finished Oct 22 01:45:46 PM PDT 23
Peak memory 212988 kb
Host smart-425d0690-e213-4463-bda4-bb94fed9aa8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754997125453149711854115520931193141461164109898044002580300399
7774612278270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.754997125453149711854115520931193141461164109898044
0025803003997774612278270
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.91741479827855816353352768099440363234158441426642224454435768830458613844343
Short name T346
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 22 01:46:22 PM PDT 23
Finished Oct 22 01:46:35 PM PDT 23
Peak memory 211160 kb
Host smart-528538ef-e398-4cb2-9a52-a44eaa4e1bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91741479827855816353352768099440363234158441426642224454435768830458613844343 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.91741479827855816353352768099440363234158441426642224454435768830458613844343
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.83483342649761662144449675023876515880236758288135954996862682811258229561217
Short name T329
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.37 seconds
Started Oct 22 01:46:08 PM PDT 23
Finished Oct 22 01:51:46 PM PDT 23
Peak memory 237744 kb
Host smart-e00d614d-54b0-4781-bc84-56b0081782d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83483342649761662144449675023876515880236758288135954996862682811258229561217 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.834833426497616621444496750238765158802367582881359549968
62682811258229561217
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.20732061641945201714377705451397977710979145751524699442868037010338460314820
Short name T145
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.9 seconds
Started Oct 22 01:46:45 PM PDT 23
Finished Oct 22 01:47:11 PM PDT 23
Peak memory 211580 kb
Host smart-7a369c57-726f-43f4-b980-6994e1ccfa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20732061641945201714377705451397977710979145751524699442868037010338460314820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rom_ctrl_kmac_err_chk.20732061641945201714377705451397977710979145751524699442868037010338460314820
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.4848364989885532384746688368096346154493006117229523165472828908722998222105
Short name T216
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Oct 22 01:46:37 PM PDT 23
Finished Oct 22 01:46:51 PM PDT 23
Peak memory 211208 kb
Host smart-b53483db-abb8-4b14-8519-55b58cb0a097
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4848364989885532384746688368096346154493006117229523165472828908722998222105 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.4848364989885532384746688368096346154493006117229523165472828908722998222105
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.13198884113295075762361772697748808331099468628491414106699419691174584968833
Short name T279
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.31 seconds
Started Oct 22 01:45:34 PM PDT 23
Finished Oct 22 01:46:02 PM PDT 23
Peak memory 212800 kb
Host smart-73feef6c-4d83-4809-809c-903f51837cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13198884113295075762361772697748808331099468628491414106699419691174584968833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.rom_ctrl_smoke.13198884113295075762361772697748808331099468628491414106699419691174584968833
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.76649486264498333267029027348549876993404007241781796465015483828380595905835
Short name T231
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.52 seconds
Started Oct 22 01:45:53 PM PDT 23
Finished Oct 22 01:46:37 PM PDT 23
Peak memory 212976 kb
Host smart-664ae6a0-9765-4248-a6d3-6e5b19bf7b90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766494862644983332670290273485498769934040072417817964650154838
28380595905835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.76649486264498333267029027348549876993404007241781
796465015483828380595905835
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.27740549435682238452016337564081841791825743596452614373537927259688638092259
Short name T325
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Oct 22 01:46:35 PM PDT 23
Finished Oct 22 01:46:47 PM PDT 23
Peak memory 211160 kb
Host smart-afa9df15-6069-4ce3-b8cb-cdc0bc9e7791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27740549435682238452016337564081841791825743596452614373537927259688638092259 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.27740549435682238452016337564081841791825743596452614373537927259688638092259
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.74809448057017892112275568035420136487539724292422088115408482946273977684689
Short name T125
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.19 seconds
Started Oct 22 01:46:19 PM PDT 23
Finished Oct 22 01:52:01 PM PDT 23
Peak memory 237712 kb
Host smart-d7fd409b-474f-438a-940a-61d74cd5ee31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74809448057017892112275568035420136487539724292422088115408482946273977684689 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.748094480570178921122755680354201364875397242924220881154
08482946273977684689
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.56918921358463181856963849079228085848114892106172060368021436047989335880817
Short name T112
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.03 seconds
Started Oct 22 01:46:03 PM PDT 23
Finished Oct 22 01:46:29 PM PDT 23
Peak memory 211648 kb
Host smart-bfcb06eb-b9f4-4bb7-a0fc-53bcb6db0dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56918921358463181856963849079228085848114892106172060368021436047989335880817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rom_ctrl_kmac_err_chk.56918921358463181856963849079228085848114892106172060368021436047989335880817
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.59739728247749358554677569828735571018037244574180445715873054070617431935575
Short name T14
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:45:52 PM PDT 23
Peak memory 211180 kb
Host smart-be012f22-5e6d-490d-9588-a62d15958cdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59739728247749358554677569828735571018037244574180445715873054070617431935575 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.59739728247749358554677569828735571018037244574180445715873054070617431935575
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.13904754525308579062944305919741110863948695062954643460178315757177872075544
Short name T339
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Oct 22 01:47:17 PM PDT 23
Finished Oct 22 01:47:46 PM PDT 23
Peak memory 212848 kb
Host smart-64382498-d907-449d-a1ce-c32f6b2664ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13904754525308579062944305919741110863948695062954643460178315757177872075544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_smoke.13904754525308579062944305919741110863948695062954643460178315757177872075544
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.39257334392959307546964926524728933775109267327106983256955801836499690158801
Short name T307
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.14 seconds
Started Oct 22 01:46:39 PM PDT 23
Finished Oct 22 01:47:22 PM PDT 23
Peak memory 212924 kb
Host smart-701a0c97-7919-493e-93f7-8484b3a8f09e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392573343929593075469649265247289337751092673271069832569558018
36499690158801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.39257334392959307546964926524728933775109267327106
983256955801836499690158801
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.107261292620588620249543548989249731569781628535538777044958698196043526787270
Short name T240
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Oct 22 01:46:34 PM PDT 23
Finished Oct 22 01:46:47 PM PDT 23
Peak memory 211200 kb
Host smart-bfd31868-b0ff-4df3-aa8f-7f6b29a506ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107261292620588620249543548989249731569781628535538777044958698196043526787270 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.107261292620588620249543548989249731569781628535538777044958698196043526787270
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.66906451442742959673781115502081420188210543142603893952569333468537118961088
Short name T229
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.15 seconds
Started Oct 22 01:46:21 PM PDT 23
Finished Oct 22 01:52:05 PM PDT 23
Peak memory 237692 kb
Host smart-d69c6565-4050-4500-8e09-e3a75d4c0e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66906451442742959673781115502081420188210543142603893952569333468537118961088 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.669064514427429596737811155020814201882105431426038939525
69333468537118961088
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.59624716364685064719989350118420146793564664178764622545288101572883029217917
Short name T109
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.31 seconds
Started Oct 22 01:45:36 PM PDT 23
Finished Oct 22 01:46:02 PM PDT 23
Peak memory 211544 kb
Host smart-7c66533f-ccbe-444d-bd89-e48d6abb0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59624716364685064719989350118420146793564664178764622545288101572883029217917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rom_ctrl_kmac_err_chk.59624716364685064719989350118420146793564664178764622545288101572883029217917
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.95839592497030832653259862368537504824634841836320004333048171409880882341171
Short name T316
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.38 seconds
Started Oct 22 01:47:22 PM PDT 23
Finished Oct 22 01:47:36 PM PDT 23
Peak memory 211204 kb
Host smart-74097e13-ea8b-4edc-a583-4a6e95e33add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95839592497030832653259862368537504824634841836320004333048171409880882341171 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.95839592497030832653259862368537504824634841836320004333048171409880882341171
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.96392846020314237777675474716420283585092471821324710499758964540657402239555
Short name T79
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.76 seconds
Started Oct 22 01:46:43 PM PDT 23
Finished Oct 22 01:47:12 PM PDT 23
Peak memory 212872 kb
Host smart-93623d51-2c1e-4a17-b24f-1c1380e0e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96392846020314237777675474716420283585092471821324710499758964540657402239555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_smoke.96392846020314237777675474716420283585092471821324710499758964540657402239555
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.61536954932648358247258650464733230630739679393332803832741057763759592148864
Short name T194
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.75 seconds
Started Oct 22 01:46:08 PM PDT 23
Finished Oct 22 01:46:52 PM PDT 23
Peak memory 212964 kb
Host smart-d95b663b-1a4c-43c0-b8b4-76cdcea5a95c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615369549326483582472586504647332306307396793933328038327410577
63759592148864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.61536954932648358247258650464733230630739679393332
803832741057763759592148864
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.48184881813611849117426050527032631226155647373865562657460310630437563293189
Short name T123
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 22 01:47:46 PM PDT 23
Finished Oct 22 01:47:59 PM PDT 23
Peak memory 211172 kb
Host smart-d3e0458a-7608-4c86-b87d-8d276cb82138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48184881813611849117426050527032631226155647373865562657460310630437563293189 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.48184881813611849117426050527032631226155647373865562657460310630437563293189
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.85597543816255540722852496929736312380796218447776099265591728746448070921565
Short name T276
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.19 seconds
Started Oct 22 01:46:39 PM PDT 23
Finished Oct 22 01:52:22 PM PDT 23
Peak memory 237728 kb
Host smart-93c4a990-27ba-42c0-901a-ec50e8c4ced7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85597543816255540722852496929736312380796218447776099265591728746448070921565 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.855975438162555407228524969297363123807962184477760992655
91728746448070921565
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.58887819694545915574975595192196250663407310855945622338612170793476604851161
Short name T1
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.51 seconds
Started Oct 22 01:47:27 PM PDT 23
Finished Oct 22 01:47:53 PM PDT 23
Peak memory 211556 kb
Host smart-af4bd855-4cd0-470d-a6b2-d6edae52c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58887819694545915574975595192196250663407310855945622338612170793476604851161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rom_ctrl_kmac_err_chk.58887819694545915574975595192196250663407310855945622338612170793476604851161
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.50408432930438679550997214375115935894865767971257507566543300528636584735847
Short name T270
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Oct 22 01:47:22 PM PDT 23
Finished Oct 22 01:47:36 PM PDT 23
Peak memory 211164 kb
Host smart-ca502771-0ba3-4c51-8625-25330c1063e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50408432930438679550997214375115935894865767971257507566543300528636584735847 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.50408432930438679550997214375115935894865767971257507566543300528636584735847
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.55569055860802939469448132101184485116746936519279541470918377037236879645448
Short name T278
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.76 seconds
Started Oct 22 01:46:11 PM PDT 23
Finished Oct 22 01:46:41 PM PDT 23
Peak memory 212812 kb
Host smart-de7499ba-5628-433f-a5e2-46fe25d9e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55569055860802939469448132101184485116746936519279541470918377037236879645448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_smoke.55569055860802939469448132101184485116746936519279541470918377037236879645448
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.9491152166848735577679711254508660748232412370364814859918373984114722760637
Short name T274
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.29 seconds
Started Oct 22 01:47:28 PM PDT 23
Finished Oct 22 01:48:11 PM PDT 23
Peak memory 212968 kb
Host smart-3a959d2c-59fa-48df-b8b7-35587de9eb22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949115216684873557767971125450866074823241237036481485991837398
4114722760637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.949115216684873557767971125450866074823241237036481
4859918373984114722760637
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.63321602597007939539116142076953560684753394049866475841629287553998789388309
Short name T243
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.4 seconds
Started Oct 22 01:44:59 PM PDT 23
Finished Oct 22 01:45:12 PM PDT 23
Peak memory 211220 kb
Host smart-c5605a1d-2f31-4874-bd59-5db1a8687b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63321602597007939539116142076953560684753394049866475841629287553998789388309 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.63321602597007939539116142076953560684753394049866475841629287553998789388309
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.50679490960563016057897118750913001961527311995536472701592471717862480303259
Short name T290
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.54 seconds
Started Oct 22 01:45:06 PM PDT 23
Finished Oct 22 01:50:47 PM PDT 23
Peak memory 237724 kb
Host smart-e40c0547-9f52-4a56-9570-840111796502
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50679490960563016057897118750913001961527311995536472701592471717862480303259 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.506794909605630160578971187509130019615273119955364727015
92471717862480303259
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.32786117619233324303839702094959218636501515626538661986562550467772027125305
Short name T267
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.79 seconds
Started Oct 22 01:44:15 PM PDT 23
Finished Oct 22 01:44:41 PM PDT 23
Peak memory 211656 kb
Host smart-15f5d76d-658f-4fb9-9c3a-138ed0647992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32786117619233324303839702094959218636501515626538661986562550467772027125305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rom_ctrl_kmac_err_chk.32786117619233324303839702094959218636501515626538661986562550467772027125305
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.94575098647080668453158173821186608493711770187111069072380740027905285103803
Short name T106
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.28 seconds
Started Oct 22 01:44:47 PM PDT 23
Finished Oct 22 01:45:01 PM PDT 23
Peak memory 211168 kb
Host smart-e253bea9-92a9-4cf6-b70d-6a0f4fe8e875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94575098647080668453158173821186608493711770187111069072380740027905285103803 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.94575098647080668453158173821186608493711770187111069072380740027905285103803
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.78971160325959737354634838842996830308908256739402400121848354218083420571723
Short name T122
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.54 seconds
Started Oct 22 01:47:46 PM PDT 23
Finished Oct 22 01:48:15 PM PDT 23
Peak memory 212848 kb
Host smart-b0cc15a4-2f28-4fb9-99f4-a8121eb36600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78971160325959737354634838842996830308908256739402400121848354218083420571723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.78971160325959737354634838842996830308908256739402400121848354218083420571723
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.46002696043565624137607794219445031337392049656399399128217067943493801688358
Short name T120
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.04 seconds
Started Oct 22 01:47:37 PM PDT 23
Finished Oct 22 01:48:20 PM PDT 23
Peak memory 212936 kb
Host smart-63327c94-411d-43cc-9d8f-29112fcb26f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460026960435656241376077942194450313373920496563993991282170679
43493801688358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.46002696043565624137607794219445031337392049656399
399128217067943493801688358
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.80144965772711797487879678334673171547498249220313865045967708987780474226683
Short name T330
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 211224 kb
Host smart-879a39f0-8a13-4aee-b085-31fb3c63cb6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80144965772711797487879678334673171547498249220313865045967708987780474226683 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.80144965772711797487879678334673171547498249220313865045967708987780474226683
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.92725626102648536844089363381629385670275893484384650401881723706399828921680
Short name T211
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.49 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:50:37 PM PDT 23
Peak memory 237696 kb
Host smart-56e68805-e096-4cd7-a535-c2f7079cc9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92725626102648536844089363381629385670275893484384650401881723706399828921680 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.927256261026485368440893633816293856702758934843846504018
81723706399828921680
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.104082882096516691480319213317340184978649451209465557277321734937523835115858
Short name T342
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.81 seconds
Started Oct 22 01:44:18 PM PDT 23
Finished Oct 22 01:44:44 PM PDT 23
Peak memory 211632 kb
Host smart-a234473f-11a5-44bf-bd05-28f9c56d5b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104082882096516691480319213317340184978649451209465557277321734937523835115858 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.rom_ctrl_kmac_err_chk.104082882096516691480319213317340184978649451209465557277321734937523835115858
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.50843540319780260293491687567456993163995055927018631453351350843239840390757
Short name T175
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.25 seconds
Started Oct 22 01:44:51 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 211188 kb
Host smart-3f44e2fa-0f8b-4103-8f9a-65894053a8b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50843540319780260293491687567456993163995055927018631453351350843239840390757 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.50843540319780260293491687567456993163995055927018631453351350843239840390757
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.15277832279366915555657401427388350030621809881765879446074925792624217858594
Short name T218
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.85 seconds
Started Oct 22 01:44:14 PM PDT 23
Finished Oct 22 01:44:43 PM PDT 23
Peak memory 212840 kb
Host smart-7d9f9308-3c88-4c01-80cb-13f2e5d5607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15277832279366915555657401427388350030621809881765879446074925792624217858594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.15277832279366915555657401427388350030621809881765879446074925792624217858594
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.68743235699008967740708781268549404952309157712564975663601216942451051258790
Short name T287
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.27 seconds
Started Oct 22 01:44:43 PM PDT 23
Finished Oct 22 01:45:26 PM PDT 23
Peak memory 212976 kb
Host smart-2152576c-3e28-42d8-b2b3-793032a4f71a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687432356990089677407087812685494049523091577125649756636012169
42451051258790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.68743235699008967740708781268549404952309157712564
975663601216942451051258790
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.8624179273559141196944578511241044462145330873514173200274272856571742102283
Short name T348
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 22 01:44:51 PM PDT 23
Finished Oct 22 01:45:04 PM PDT 23
Peak memory 211188 kb
Host smart-ea44d957-9147-4769-8571-c2cb5b3fb34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8624179273559141196944578511241044462145330873514173200274272856571742102283 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.8624179273559141196944578511241044462145330873514173200274272856571742102283
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.14592952362156500950213242105110201617854002366279078339682919733503607535305
Short name T317
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.91 seconds
Started Oct 22 01:45:31 PM PDT 23
Finished Oct 22 01:51:10 PM PDT 23
Peak memory 237732 kb
Host smart-c8757c93-d85b-4450-abc8-ad2d749213e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592952362156500950213242105110201617854002366279078339682919733503607535305 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.145929523621565009502132421051102016178540023662790783396
82919733503607535305
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.39626996094587774902489449913543504018888793036195966636549778148831887696663
Short name T17
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.75 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:46:04 PM PDT 23
Peak memory 211592 kb
Host smart-118b6f08-acb9-4eea-aee8-bdd9a131ff36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39626996094587774902489449913543504018888793036195966636549778148831887696663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rom_ctrl_kmac_err_chk.39626996094587774902489449913543504018888793036195966636549778148831887696663
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.17097368837575620603941350506161621848598659676300757479547165905735022300498
Short name T366
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:45:52 PM PDT 23
Peak memory 211104 kb
Host smart-a18de307-0a4e-4630-ad4a-5dc24271a558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17097368837575620603941350506161621848598659676300757479547165905735022300498 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.17097368837575620603941350506161621848598659676300757479547165905735022300498
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.21043343940624755181679798934625283787027261046582012062372438867175907583846
Short name T4
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.3 seconds
Started Oct 22 01:45:54 PM PDT 23
Finished Oct 22 01:46:23 PM PDT 23
Peak memory 212828 kb
Host smart-ab48f7a7-78d3-467d-9802-a9cca9e66414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21043343940624755181679798934625283787027261046582012062372438867175907583846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.rom_ctrl_smoke.21043343940624755181679798934625283787027261046582012062372438867175907583846
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.35774668031802376180609957146100603280771946413219290000578935820733336653333
Short name T323
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.96 seconds
Started Oct 22 01:44:50 PM PDT 23
Finished Oct 22 01:45:35 PM PDT 23
Peak memory 212968 kb
Host smart-83efbaaf-ad2d-4a0c-b104-cd7c5841e07a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357746680318023761806099571461006032807719464132192900005789358
20733336653333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.35774668031802376180609957146100603280771946413219
290000578935820733336653333
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.86288376543273525562053394459724824517730979975339488303335789785235781081958
Short name T197
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 22 01:44:31 PM PDT 23
Finished Oct 22 01:44:43 PM PDT 23
Peak memory 211156 kb
Host smart-61d117aa-f076-47ec-b03b-7b55c7c652d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86288376543273525562053394459724824517730979975339488303335789785235781081958 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.86288376543273525562053394459724824517730979975339488303335789785235781081958
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.26539860658492299638564413267232778909146256008186621256605184067096224132268
Short name T291
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.24 seconds
Started Oct 22 01:43:19 PM PDT 23
Finished Oct 22 01:49:03 PM PDT 23
Peak memory 237756 kb
Host smart-9829e431-faa7-4a71-b074-cc66070ad6a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539860658492299638564413267232778909146256008186621256605184067096224132268 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.2653986065849229963856441326723277890914625600818662125660
5184067096224132268
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.74913843252556945495006610750848319374849630750160413194761130246444300796126
Short name T264
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.66 seconds
Started Oct 22 01:43:21 PM PDT 23
Finished Oct 22 01:43:47 PM PDT 23
Peak memory 211604 kb
Host smart-022da18e-3b7c-4b99-9be1-ea3269221b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74913843252556945495006610750848319374849630750160413194761130246444300796126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rom_ctrl_kmac_err_chk.74913843252556945495006610750848319374849630750160413194761130246444300796126
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.10866171003664920952164591573139767326371300930372609444467492547625432135813
Short name T193
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:38 PM PDT 23
Peak memory 211212 kb
Host smart-03ef8748-a3c8-4ae2-b6fd-40a566abf1fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10866171003664920952164591573139767326371300930372609444467492547625432135813 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.10866171003664920952164591573139767326371300930372609444467492547625432135813
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.109348544903865996357097898142034763770532845343397173727418892159970741555146
Short name T126
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.4 seconds
Started Oct 22 01:44:34 PM PDT 23
Finished Oct 22 01:45:03 PM PDT 23
Peak memory 212856 kb
Host smart-1f76cf8e-3f1e-4313-a2c8-fe02680020ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109348544903865996357097898142034763770532845343397173727418892159970741555146 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.rom_ctrl_smoke.109348544903865996357097898142034763770532845343397173727418892159970741555146
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.74544617862069692771009833531225670238008138603078344391763919276894502234786
Short name T363
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.97 seconds
Started Oct 22 01:43:26 PM PDT 23
Finished Oct 22 01:44:10 PM PDT 23
Peak memory 212972 kb
Host smart-7de09ab9-b513-4a28-9663-d28b3e989ff4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745446178620696927710098335312256702380081386030783443917639192
76894502234786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.745446178620696927710098335312256702380081386030783
44391763919276894502234786
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.60661478389057463239799626480650036300498429602211642827073565873784824479317
Short name T213
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 211224 kb
Host smart-7cc793fa-64cb-4300-9d3a-1172046853a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60661478389057463239799626480650036300498429602211642827073565873784824479317 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.60661478389057463239799626480650036300498429602211642827073565873784824479317
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.99914941725094688827405884978535293823801677236391201386333077330150697839851
Short name T42
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.98 seconds
Started Oct 22 01:43:39 PM PDT 23
Finished Oct 22 01:49:25 PM PDT 23
Peak memory 237700 kb
Host smart-05fc5aea-3b86-43e1-ad6d-203933f49336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99914941725094688827405884978535293823801677236391201386333077330150697839851 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.999149417250946888274058849785352938238016772363912013863
33077330150697839851
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1721215572040719763153309023818718243603295248709921530422198717004823931551
Short name T232
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.7 seconds
Started Oct 22 01:43:29 PM PDT 23
Finished Oct 22 01:43:56 PM PDT 23
Peak memory 211644 kb
Host smart-cf12493c-19e9-4de2-bdfe-e0b1852ea623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721215572040719763153309023818718243603295248709921530422198717004823931551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.rom_ctrl_kmac_err_chk.1721215572040719763153309023818718243603295248709921530422198717004823931551
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.105742302215717391284100490084030580070069473604630715050425549082989582121342
Short name T146
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.72 seconds
Started Oct 22 01:44:14 PM PDT 23
Finished Oct 22 01:44:28 PM PDT 23
Peak memory 211180 kb
Host smart-e4993045-e587-4227-86b0-7653c508c39b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105742302215717391284100490084030580070069473604630715050425549082989582121342 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.105742302215717391284100490084030580070069473604630715050425549082989582121342
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.89191459188000997979560561217111609847287942661541165723553138677703278140431
Short name T338
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.43 seconds
Started Oct 22 01:43:33 PM PDT 23
Finished Oct 22 01:44:02 PM PDT 23
Peak memory 212800 kb
Host smart-7971a6ab-5a9d-476c-973a-9619c27cc34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89191459188000997979560561217111609847287942661541165723553138677703278140431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_smoke.89191459188000997979560561217111609847287942661541165723553138677703278140431
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.60685339607926859204961832024858844247565300960610540988411736533675268493829
Short name T217
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.23 seconds
Started Oct 22 01:45:12 PM PDT 23
Finished Oct 22 01:46:00 PM PDT 23
Peak memory 212980 kb
Host smart-b67e919c-9713-4261-979a-c4a1507dccce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606853396079268592049618320248588442475653009606105409884117365
33675268493829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.60685339607926859204961832024858844247565300960610
540988411736533675268493829
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.76966125336810498668494516815960331497531183311674352196959563619895213439028
Short name T247
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 22 01:43:33 PM PDT 23
Finished Oct 22 01:43:46 PM PDT 23
Peak memory 211148 kb
Host smart-2c662604-1fac-4d32-bb15-ec68184bfbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76966125336810498668494516815960331497531183311674352196959563619895213439028 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.76966125336810498668494516815960331497531183311674352196959563619895213439028
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2335502243644611699190985191533711246597270078760436382383371395344882543446
Short name T132
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.71 seconds
Started Oct 22 01:44:17 PM PDT 23
Finished Oct 22 01:50:04 PM PDT 23
Peak memory 237712 kb
Host smart-59bb8117-6d63-40ef-aac8-5806eb57256a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335502243644611699190985191533711246597270078760436382383371395344882543446 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.2335502243644611699190985191533711246597270078760436382383
371395344882543446
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.100138827244864824559064165210601170072785592818184354309260376155763294895552
Short name T312
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.69 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:43:54 PM PDT 23
Peak memory 211692 kb
Host smart-cf913893-594e-43c1-a277-a6e06919529c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100138827244864824559064165210601170072785592818184354309260376155763294895552 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rom_ctrl_kmac_err_chk.100138827244864824559064165210601170072785592818184354309260376155763294895552
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.54966830616330651747601376046929156520695912264873350916476185229706808303162
Short name T327
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.28 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211224 kb
Host smart-5bd4a6e0-6e6d-4a11-985d-fc34813c4369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54966830616330651747601376046929156520695912264873350916476185229706808303162 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.54966830616330651747601376046929156520695912264873350916476185229706808303162
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.106604247883630990031374543050601630669939054322838033907191733073000648805303
Short name T207
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.59 seconds
Started Oct 22 01:43:54 PM PDT 23
Finished Oct 22 01:44:22 PM PDT 23
Peak memory 212812 kb
Host smart-ed138586-10bb-4482-b88b-db951045ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106604247883630990031374543050601630669939054322838033907191733073000648805303 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.rom_ctrl_smoke.106604247883630990031374543050601630669939054322838033907191733073000648805303
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.51587498875147594926257216672993864222897465950695286432613447644159214639483
Short name T350
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.68 seconds
Started Oct 22 01:45:01 PM PDT 23
Finished Oct 22 01:45:14 PM PDT 23
Peak memory 211188 kb
Host smart-4d014b05-d257-4656-899a-a257f136c95e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51587498875147594926257216672993864222897465950695286432613447644159214639483 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.51587498875147594926257216672993864222897465950695286432613447644159214639483
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.103134805728261796805619380147310683752676921640463348860568187487494334833269
Short name T309
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.62 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:50:50 PM PDT 23
Peak memory 237720 kb
Host smart-ba024bd2-3a73-438b-8229-b82cb8d943a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103134805728261796805619380147310683752676921640463348860568187487494334833269 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.10313480572826179680561938014731068375267692164046334886
0568187487494334833269
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.21836129536364402858710249018326519971012946013543882020483061044160709389013
Short name T9
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.85 seconds
Started Oct 22 01:45:38 PM PDT 23
Finished Oct 22 01:46:05 PM PDT 23
Peak memory 211664 kb
Host smart-1c06a4c2-8798-41cc-904a-245c3b082870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21836129536364402858710249018326519971012946013543882020483061044160709389013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.rom_ctrl_kmac_err_chk.21836129536364402858710249018326519971012946013543882020483061044160709389013
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.76052800772412387598825764034999494210023871278123410363129736724590952723408
Short name T135
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.8 seconds
Started Oct 22 01:44:54 PM PDT 23
Finished Oct 22 01:45:08 PM PDT 23
Peak memory 211188 kb
Host smart-4997d413-f91f-492a-88ff-f98128e7d045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76052800772412387598825764034999494210023871278123410363129736724590952723408 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.76052800772412387598825764034999494210023871278123410363129736724590952723408
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.81410486154488347246191795321556745090498388950686100578388849577832270166105
Short name T190
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:45:36 PM PDT 23
Peak memory 212848 kb
Host smart-788fa9fc-8aa5-4eb8-8434-deaa1c5a902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81410486154488347246191795321556745090498388950686100578388849577832270166105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.rom_ctrl_smoke.81410486154488347246191795321556745090498388950686100578388849577832270166105
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.89247401564019611397764702820150144345261588212177484046764207573642629054998
Short name T157
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.81 seconds
Started Oct 22 01:44:14 PM PDT 23
Finished Oct 22 01:44:58 PM PDT 23
Peak memory 212976 kb
Host smart-5cdc681f-2f97-4d5f-a1df-79dcacf27339
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892474015640196113977647028201501443452615882121774840467642075
73642629054998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.89247401564019611397764702820150144345261588212177
484046764207573642629054998
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.13406355269943938971079799717864771024678836372291320685097969953352741428864
Short name T164
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.63 seconds
Started Oct 22 01:45:33 PM PDT 23
Finished Oct 22 01:45:46 PM PDT 23
Peak memory 211172 kb
Host smart-cddbfbf3-0da1-4d2d-a4f3-49b80d9b2715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406355269943938971079799717864771024678836372291320685097969953352741428864 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.13406355269943938971079799717864771024678836372291320685097969953352741428864
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.11215194271775115994500200967998088569155391127751263276843923150407888877172
Short name T7
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.28 seconds
Started Oct 22 01:45:36 PM PDT 23
Finished Oct 22 01:51:25 PM PDT 23
Peak memory 237704 kb
Host smart-b29c7b52-6361-4715-8a7a-80c1fda9fc26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215194271775115994500200967998088569155391127751263276843923150407888877172 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.112151942717751159945002009679980885691553911277512632768
43923150407888877172
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.89036188255287987580813141808385116949684221943781854308496268746144341244637
Short name T191
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.93 seconds
Started Oct 22 01:44:53 PM PDT 23
Finished Oct 22 01:45:20 PM PDT 23
Peak memory 211620 kb
Host smart-4d120b41-61c8-4464-a42b-be8588dcdd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89036188255287987580813141808385116949684221943781854308496268746144341244637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.89036188255287987580813141808385116949684221943781854308496268746144341244637
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.34647399588908148178202190666347223334258135687941088862024702893828477121370
Short name T163
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Oct 22 01:45:34 PM PDT 23
Finished Oct 22 01:45:48 PM PDT 23
Peak memory 211180 kb
Host smart-d7c77b30-38bc-4b99-bf38-430ca786554d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34647399588908148178202190666347223334258135687941088862024702893828477121370 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.34647399588908148178202190666347223334258135687941088862024702893828477121370
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.55031010668460442930109179538299019283411623720184416590335999731729825462617
Short name T119
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Oct 22 01:45:00 PM PDT 23
Finished Oct 22 01:45:29 PM PDT 23
Peak memory 212856 kb
Host smart-86ecb4d9-8e4a-447d-b99f-6848ac41ecef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55031010668460442930109179538299019283411623720184416590335999731729825462617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.rom_ctrl_smoke.55031010668460442930109179538299019283411623720184416590335999731729825462617
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.61708870522444048806095812282306634521170256171097435431061693318563672022913
Short name T246
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.38 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:45:51 PM PDT 23
Peak memory 212920 kb
Host smart-08eb158c-ddb1-4f0c-ac0a-9d0d59b40ae0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617088705224440488060958122823066345211702561710974354310616933
18563672022913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.61708870522444048806095812282306634521170256171097
435431061693318563672022913
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.72218090569384212017258182123871987136035336391761737671143726361161446188168
Short name T288
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 211168 kb
Host smart-69af4b1a-a33c-4672-a823-2f80797a7e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72218090569384212017258182123871987136035336391761737671143726361161446188168 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.72218090569384212017258182123871987136035336391761737671143726361161446188168
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.83144835482364845827762318495757465422027329619298962538319771645324400962039
Short name T224
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.22 seconds
Started Oct 22 01:45:40 PM PDT 23
Finished Oct 22 01:51:23 PM PDT 23
Peak memory 237628 kb
Host smart-df3bd995-540b-428f-9371-43c575f47a3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83144835482364845827762318495757465422027329619298962538319771645324400962039 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.831448354823648458277623184957574654220273296192989625383
19771645324400962039
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.63324987112623614413752385318497423993407140894301626304462581799942459782614
Short name T203
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.04 seconds
Started Oct 22 01:44:19 PM PDT 23
Finished Oct 22 01:44:47 PM PDT 23
Peak memory 211652 kb
Host smart-12998e7c-d616-4671-84b9-f15f7e17953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63324987112623614413752385318497423993407140894301626304462581799942459782614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rom_ctrl_kmac_err_chk.63324987112623614413752385318497423993407140894301626304462581799942459782614
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.57748072609430298810678804711773523475652079669141029981298841455449922087429
Short name T353
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Oct 22 01:45:36 PM PDT 23
Finished Oct 22 01:45:51 PM PDT 23
Peak memory 211196 kb
Host smart-bb074b19-aafe-4499-b863-d7cc3cf65513
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57748072609430298810678804711773523475652079669141029981298841455449922087429 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.57748072609430298810678804711773523475652079669141029981298841455449922087429
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.100601783114501810527295236563092289358442008079911945692166310188684493525646
Short name T282
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.22 seconds
Started Oct 22 01:45:47 PM PDT 23
Finished Oct 22 01:46:17 PM PDT 23
Peak memory 212728 kb
Host smart-9ec698ca-663d-4401-9e9d-f71239ec09c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100601783114501810527295236563092289358442008079911945692166310188684493525646 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.rom_ctrl_smoke.100601783114501810527295236563092289358442008079911945692166310188684493525646
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.96570905673682606869653053205436611254144055553769901513153491427586620519695
Short name T265
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.78 seconds
Started Oct 22 01:46:09 PM PDT 23
Finished Oct 22 01:46:53 PM PDT 23
Peak memory 212928 kb
Host smart-7861f91c-8ea5-44dd-9082-cd2342df32c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965709056736826068696530532054366112541440555537699015131534914
27586620519695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.96570905673682606869653053205436611254144055553769
901513153491427586620519695
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.64954936363608182207684791705128763243940852547415498894747378954605516629763
Short name T185
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.3 seconds
Started Oct 22 01:44:15 PM PDT 23
Finished Oct 22 01:44:28 PM PDT 23
Peak memory 211164 kb
Host smart-c3c06f95-9203-4513-b2a3-9190af255f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64954936363608182207684791705128763243940852547415498894747378954605516629763 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.64954936363608182207684791705128763243940852547415498894747378954605516629763
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.23682393857114012299355655648121338321102136128907158166973339136748208182855
Short name T136
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.55 seconds
Started Oct 22 01:45:01 PM PDT 23
Finished Oct 22 01:50:39 PM PDT 23
Peak memory 237660 kb
Host smart-7c5526f8-0763-420f-88dc-0e149fe49d16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682393857114012299355655648121338321102136128907158166973339136748208182855 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.236823938571140122993556556481213383211021361289071581669
73339136748208182855
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.100362594960959971028458401858853419863593153921302748074914233221692565698270
Short name T153
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.63 seconds
Started Oct 22 01:44:18 PM PDT 23
Finished Oct 22 01:44:44 PM PDT 23
Peak memory 211552 kb
Host smart-855bc83c-0b53-4d3d-b9e8-2ac074970445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100362594960959971028458401858853419863593153921302748074914233221692565698270 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.rom_ctrl_kmac_err_chk.100362594960959971028458401858853419863593153921302748074914233221692565698270
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.80111340591919012331501576119348543322477536169184715786944177626078027735819
Short name T308
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.37 seconds
Started Oct 22 01:45:08 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 211104 kb
Host smart-62075804-677c-433d-bd7a-f9adfed480c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80111340591919012331501576119348543322477536169184715786944177626078027735819 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.80111340591919012331501576119348543322477536169184715786944177626078027735819
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.44095823753097717239634457757110946764182207819304398567396339547642775039280
Short name T236
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.69 seconds
Started Oct 22 01:45:06 PM PDT 23
Finished Oct 22 01:45:35 PM PDT 23
Peak memory 212856 kb
Host smart-ca1ab369-eaae-4408-80cf-c7bdac45cdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44095823753097717239634457757110946764182207819304398567396339547642775039280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.44095823753097717239634457757110946764182207819304398567396339547642775039280
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.30664550718280682266524588226978636078892722734660132170568166499711683459993
Short name T318
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.69 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:45:50 PM PDT 23
Peak memory 212944 kb
Host smart-6a5a7a4a-fb7d-444d-9c5e-08d1d0d32c67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306645507182806822665245882269786360788927227346601321705681664
99711683459993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.30664550718280682266524588226978636078892722734660
132170568166499711683459993
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.38454508809983918834855403041862207650977731675131387015709615331397235169643
Short name T241
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.51 seconds
Started Oct 22 01:45:55 PM PDT 23
Finished Oct 22 01:46:08 PM PDT 23
Peak memory 211220 kb
Host smart-f58bc478-b844-4c56-952c-f3bacd6f49ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454508809983918834855403041862207650977731675131387015709615331397235169643 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.38454508809983918834855403041862207650977731675131387015709615331397235169643
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.40887256441239022700951014003133547823384223115304473757614697510647887633686
Short name T324
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.02 seconds
Started Oct 22 01:44:53 PM PDT 23
Finished Oct 22 01:50:33 PM PDT 23
Peak memory 237632 kb
Host smart-2174cb20-770d-4f5e-a535-d130d72e13e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40887256441239022700951014003133547823384223115304473757614697510647887633686 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.408872564412390227009510140031335478233842231153044737576
14697510647887633686
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.32978718261187999189428278725964146129337738471849476990566797856272607985967
Short name T228
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.17 seconds
Started Oct 22 01:44:55 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 211620 kb
Host smart-1e1776a4-83ab-484a-b5a6-7a98333a7d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32978718261187999189428278725964146129337738471849476990566797856272607985967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rom_ctrl_kmac_err_chk.32978718261187999189428278725964146129337738471849476990566797856272607985967
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.53196949440992771461165948763486998339061812101501323340743459737586639263445
Short name T165
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.42 seconds
Started Oct 22 01:45:09 PM PDT 23
Finished Oct 22 01:45:23 PM PDT 23
Peak memory 211224 kb
Host smart-e8e51d60-261a-4609-b9ab-90a5e696b9e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53196949440992771461165948763486998339061812101501323340743459737586639263445 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.53196949440992771461165948763486998339061812101501323340743459737586639263445
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.25950274582097349994270865555189602835827850061514079308662297508607649142320
Short name T344
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.51 seconds
Started Oct 22 01:44:58 PM PDT 23
Finished Oct 22 01:45:27 PM PDT 23
Peak memory 212780 kb
Host smart-0db7ccac-81c6-4bb9-80b9-cc0fe9b370a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25950274582097349994270865555189602835827850061514079308662297508607649142320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_smoke.25950274582097349994270865555189602835827850061514079308662297508607649142320
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.82562335624408366578152971311214784971179789651557636629421018972425801631234
Short name T359
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.68 seconds
Started Oct 22 01:45:01 PM PDT 23
Finished Oct 22 01:45:44 PM PDT 23
Peak memory 212944 kb
Host smart-96766fa6-97c3-4b5a-b9b8-bb82050b7c6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825623356244083665781529713112147849711797896515576366294210189
72425801631234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.82562335624408366578152971311214784971179789651557
636629421018972425801631234
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.21486062185798325265930230682582632069121415610154740428162172995683987199329
Short name T133
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Oct 22 01:45:37 PM PDT 23
Finished Oct 22 01:45:50 PM PDT 23
Peak memory 211188 kb
Host smart-d0af4f6e-6f31-4ed1-94bb-03a5a36a4d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21486062185798325265930230682582632069121415610154740428162172995683987199329 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.21486062185798325265930230682582632069121415610154740428162172995683987199329
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.55076213385498985022663870491075512854499824119298424470932220672716791448442
Short name T280
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.64 seconds
Started Oct 22 01:45:32 PM PDT 23
Finished Oct 22 01:51:16 PM PDT 23
Peak memory 237732 kb
Host smart-6d8efcb5-d596-40d5-be02-18cb400501a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55076213385498985022663870491075512854499824119298424470932220672716791448442 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.550762133854989850226638704910755128544998241192984244709
32220672716791448442
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.44422813306927195133724647779962013632629761189749427422340927920514423100917
Short name T235
Test name
Test status
Simulation time 6233818126 ps
CPU time 26 seconds
Started Oct 22 01:45:53 PM PDT 23
Finished Oct 22 01:46:20 PM PDT 23
Peak memory 211636 kb
Host smart-c244dfb2-dd0c-4f04-a7e2-2b660e79c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44422813306927195133724647779962013632629761189749427422340927920514423100917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rom_ctrl_kmac_err_chk.44422813306927195133724647779962013632629761189749427422340927920514423100917
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.34728016892166736669099233686142532345146677918246743190204897711740293563117
Short name T300
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Oct 22 01:45:53 PM PDT 23
Finished Oct 22 01:46:07 PM PDT 23
Peak memory 211148 kb
Host smart-33ed383b-2b71-4d33-a15e-99399dda9671
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34728016892166736669099233686142532345146677918246743190204897711740293563117 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.34728016892166736669099233686142532345146677918246743190204897711740293563117
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.61717381033366954957383008516828557867269077415104811673652214154162707449616
Short name T156
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.28 seconds
Started Oct 22 01:45:40 PM PDT 23
Finished Oct 22 01:46:10 PM PDT 23
Peak memory 212852 kb
Host smart-183695a6-74be-400a-9f30-8f466e949be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61717381033366954957383008516828557867269077415104811673652214154162707449616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.rom_ctrl_smoke.61717381033366954957383008516828557867269077415104811673652214154162707449616
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.41320466219386544518349423807422934501409314170599754304777777664504660788187
Short name T127
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.09 seconds
Started Oct 22 01:45:07 PM PDT 23
Finished Oct 22 01:45:51 PM PDT 23
Peak memory 212952 kb
Host smart-5584f0ab-5ab5-4299-a4ee-a9c3f288a9ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413204662193865445183494238074229345014093141705997543047777776
64504660788187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.41320466219386544518349423807422934501409314170599
754304777777664504660788187
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.105419554002542809895734266038119076826733700813089262528806029941849687798243
Short name T356
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Oct 22 01:46:21 PM PDT 23
Finished Oct 22 01:46:34 PM PDT 23
Peak memory 211148 kb
Host smart-259b506b-7870-4530-9815-875339ef77a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105419554002542809895734266038119076826733700813089262528806029941849687798243 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.105419554002542809895734266038119076826733700813089262528806029941849687798243
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.78732304551736492712925186912497823393523007793611396178704412037330684949604
Short name T180
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.47 seconds
Started Oct 22 01:46:06 PM PDT 23
Finished Oct 22 01:51:42 PM PDT 23
Peak memory 237708 kb
Host smart-876bb3b1-8ace-446f-b3db-a1f2e4fb1968
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78732304551736492712925186912497823393523007793611396178704412037330684949604 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.787323045517364927129251869124978233935230077936113961787
04412037330684949604
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.82738310459144161980921521699750523491606149555178915775140314265101601289828
Short name T214
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.03 seconds
Started Oct 22 01:45:56 PM PDT 23
Finished Oct 22 01:46:22 PM PDT 23
Peak memory 211652 kb
Host smart-8c66a97f-f200-48aa-ac5f-841ab7642473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82738310459144161980921521699750523491606149555178915775140314265101601289828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.82738310459144161980921521699750523491606149555178915775140314265101601289828
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.57391387092654888395554567685213657150015322591969329121684330355191883974438
Short name T299
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.66 seconds
Started Oct 22 01:46:08 PM PDT 23
Finished Oct 22 01:46:22 PM PDT 23
Peak memory 211208 kb
Host smart-9a3a6854-aa58-4a07-ade9-2bdf1f0634bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57391387092654888395554567685213657150015322591969329121684330355191883974438 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.57391387092654888395554567685213657150015322591969329121684330355191883974438
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.48551173819056942457467360040097026414156964796668744261622767358262059653290
Short name T151
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.77 seconds
Started Oct 22 01:45:50 PM PDT 23
Finished Oct 22 01:46:19 PM PDT 23
Peak memory 212792 kb
Host smart-9d62d942-06fa-44cf-b873-45d944f96eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48551173819056942457467360040097026414156964796668744261622767358262059653290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.48551173819056942457467360040097026414156964796668744261622767358262059653290
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.73238082186553246768249523454442690424296661665317256110353270573050273569056
Short name T314
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.63 seconds
Started Oct 22 01:47:24 PM PDT 23
Finished Oct 22 01:48:07 PM PDT 23
Peak memory 212904 kb
Host smart-ab7a3ad0-00ad-497a-8f61-5a2ccdbdbdd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732380821865532467682495234544426904242966616653172561103532705
73050273569056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.73238082186553246768249523454442690424296661665317
256110353270573050273569056
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.68049944314610932577176813415383676447225453513206426523741801495599992781641
Short name T361
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 22 01:47:27 PM PDT 23
Finished Oct 22 01:47:40 PM PDT 23
Peak memory 211180 kb
Host smart-b038f623-664b-4cb7-bfef-b6add21a1ea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68049944314610932577176813415383676447225453513206426523741801495599992781641 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.68049944314610932577176813415383676447225453513206426523741801495599992781641
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2797430827045066809395888130794080683891054763345289409215213074616634432624
Short name T332
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.18 seconds
Started Oct 22 01:46:15 PM PDT 23
Finished Oct 22 01:51:56 PM PDT 23
Peak memory 237620 kb
Host smart-df823772-85b4-470a-9a8e-d5e0928582bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797430827045066809395888130794080683891054763345289409215213074616634432624 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.2797430827045066809395888130794080683891054763345289409215
213074616634432624
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.73909273566903960265489883497084372157485807734141167586008128902546069212525
Short name T113
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.73 seconds
Started Oct 22 01:47:22 PM PDT 23
Finished Oct 22 01:47:49 PM PDT 23
Peak memory 211636 kb
Host smart-76e85bcf-00ed-4ab7-9cee-8f446b937e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73909273566903960265489883497084372157485807734141167586008128902546069212525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.rom_ctrl_kmac_err_chk.73909273566903960265489883497084372157485807734141167586008128902546069212525
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.66145995752455990585161742978721459728824826095399563701483660641931881907130
Short name T215
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.44 seconds
Started Oct 22 01:46:20 PM PDT 23
Finished Oct 22 01:46:33 PM PDT 23
Peak memory 211136 kb
Host smart-a065c435-6345-4190-9c0e-73be184b89c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66145995752455990585161742978721459728824826095399563701483660641931881907130 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.66145995752455990585161742978721459728824826095399563701483660641931881907130
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.105491372580530633412665352895777938066307899328838271543995145520097536895750
Short name T161
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.15 seconds
Started Oct 22 01:46:22 PM PDT 23
Finished Oct 22 01:46:51 PM PDT 23
Peak memory 212868 kb
Host smart-b6f81aa8-8edb-4894-beae-6c2b745eaa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105491372580530633412665352895777938066307899328838271543995145520097536895750 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.rom_ctrl_smoke.105491372580530633412665352895777938066307899328838271543995145520097536895750
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4002797932538090269710407117578333279750307739775569978703383268442394821617
Short name T296
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.62 seconds
Started Oct 22 01:46:27 PM PDT 23
Finished Oct 22 01:47:10 PM PDT 23
Peak memory 212924 kb
Host smart-94cc64a8-1fb7-422e-8eed-83e992a71979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400279793253809026971040711757833327975030773977556997870338326
8442394821617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.400279793253809026971040711757833327975030773977556
9978703383268442394821617
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.88425398158056507018263879163627403306809799254422396323578913818308728917939
Short name T99
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.42 seconds
Started Oct 22 01:43:27 PM PDT 23
Finished Oct 22 01:43:39 PM PDT 23
Peak memory 211220 kb
Host smart-4487fff2-fa66-4c1b-8d88-0a95125d8732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88425398158056507018263879163627403306809799254422396323578913818308728917939 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.88425398158056507018263879163627403306809799254422396323578913818308728917939
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.62957676728234576678182597364232688618003780942173594557047128606319282673075
Short name T158
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.26 seconds
Started Oct 22 01:44:52 PM PDT 23
Finished Oct 22 01:50:32 PM PDT 23
Peak memory 237612 kb
Host smart-3df3fe81-fb26-4c0f-8a9a-e10515dda944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62957676728234576678182597364232688618003780942173594557047128606319282673075 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.6295767672823457667818259736423268861800378094217359455704
7128606319282673075
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.69285323194842628146429892428492511719839980242076611317665684117060663597287
Short name T337
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.84 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:51 PM PDT 23
Peak memory 211632 kb
Host smart-8885c00f-6508-4001-94a3-f5c9650db9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69285323194842628146429892428492511719839980242076611317665684117060663597287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.rom_ctrl_kmac_err_chk.69285323194842628146429892428492511719839980242076611317665684117060663597287
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.99137479798694569453407646612573177693166309516521662596764027648165491653236
Short name T354
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.5 seconds
Started Oct 22 01:43:27 PM PDT 23
Finished Oct 22 01:43:40 PM PDT 23
Peak memory 211216 kb
Host smart-4881e5a5-1d47-4e30-bfb4-f158066ce6da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99137479798694569453407646612573177693166309516521662596764027648165491653236 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.99137479798694569453407646612573177693166309516521662596764027648165491653236
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.114944434270779974797603534409173751660588807806334302493700841165367015891438
Short name T160
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.14 seconds
Started Oct 22 01:44:32 PM PDT 23
Finished Oct 22 01:45:01 PM PDT 23
Peak memory 212824 kb
Host smart-6b0e7042-f7b1-453b-9534-10f1ff48d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114944434270779974797603534409173751660588807806334302493700841165367015891438 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.rom_ctrl_smoke.114944434270779974797603534409173751660588807806334302493700841165367015891438
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.47008528433069493648114829879001439436800517820201666243540200653598530631650
Short name T230
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.92 seconds
Started Oct 22 01:43:26 PM PDT 23
Finished Oct 22 01:44:10 PM PDT 23
Peak memory 212976 kb
Host smart-9dd2d38d-f6a8-4d79-9ed8-07736d479bd4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470085284330694936481148298790014394368005178202016662435402006
53598530631650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.470085284330694936481148298790014394368005178202016
66243540200653598530631650
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.110324274974682674680146318131241942436060141938921593972482599468013154882460
Short name T201
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 22 01:44:35 PM PDT 23
Finished Oct 22 01:44:48 PM PDT 23
Peak memory 211228 kb
Host smart-042d5c20-7cff-4b3f-bf5b-2632c4cbc285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110324274974682674680146318131241942436060141938921593972482599468013154882460 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.110324274974682674680146318131241942436060141938921593972482599468013154882460
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.51629486126198337464625574120810491132823132470663039104057639326671151089875
Short name T38
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.25 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:49:05 PM PDT 23
Peak memory 237724 kb
Host smart-cc7ff6a0-0e30-4921-a63a-f30e286640a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51629486126198337464625574120810491132823132470663039104057639326671151089875 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.5162948612619833746462557412081049113282313247066303910405
7639326671151089875
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.88515561967501203981212098506607776801249526397279524092666720562339892720304
Short name T322
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.83 seconds
Started Oct 22 01:44:31 PM PDT 23
Finished Oct 22 01:44:57 PM PDT 23
Peak memory 211640 kb
Host smart-aaae898f-aa99-4c82-b4f5-637d888e4a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88515561967501203981212098506607776801249526397279524092666720562339892720304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.rom_ctrl_kmac_err_chk.88515561967501203981212098506607776801249526397279524092666720562339892720304
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.81793389496160414129978408674957799919877655289043882736449205501309162424807
Short name T12
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.13 seconds
Started Oct 22 01:43:22 PM PDT 23
Finished Oct 22 01:43:36 PM PDT 23
Peak memory 211180 kb
Host smart-efe095fe-30bf-4d7b-afbe-617509386748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81793389496160414129978408674957799919877655289043882736449205501309162424807 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.81793389496160414129978408674957799919877655289043882736449205501309162424807
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.77824327199989775097195534510285584135562490378267136875200887057051712240269
Short name T186
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:43:53 PM PDT 23
Peak memory 212820 kb
Host smart-801d9e46-3671-4ead-bc7f-bb5f825f67b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77824327199989775097195534510285584135562490378267136875200887057051712240269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_smoke.77824327199989775097195534510285584135562490378267136875200887057051712240269
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.100334074925461077110338313805857453201775123111973957136606839236586457170968
Short name T335
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.19 seconds
Started Oct 22 01:44:51 PM PDT 23
Finished Oct 22 01:45:34 PM PDT 23
Peak memory 212940 kb
Host smart-4fc437ab-434d-48bc-9cdc-6f54bf777009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100334074925461077110338313805857453201775123111973957136606839
236586457170968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.10033407492546107711033831380585745320177512311197
3957136606839236586457170968
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.48016516398900651016583250429479850071559675522542913758413815921618437958463
Short name T147
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 22 01:43:25 PM PDT 23
Finished Oct 22 01:43:39 PM PDT 23
Peak memory 211168 kb
Host smart-6faec2aa-6357-42d7-bc2b-3f9c5a51d8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48016516398900651016583250429479850071559675522542913758413815921618437958463 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.48016516398900651016583250429479850071559675522542913758413815921618437958463
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.40441321650227859780160453855145448390287371565080965460292550838742229471090
Short name T39
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.41 seconds
Started Oct 22 01:44:35 PM PDT 23
Finished Oct 22 01:50:18 PM PDT 23
Peak memory 237744 kb
Host smart-0de8a8b0-e6ff-4016-b1b5-5a640ecfc276
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441321650227859780160453855145448390287371565080965460292550838742229471090 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.4044132165022785978016045385514544839028737156508096546029
2550838742229471090
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.9184472679476746508182845196105229347072492277493948461231339741821135708909
Short name T208
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.13 seconds
Started Oct 22 01:44:49 PM PDT 23
Finished Oct 22 01:45:16 PM PDT 23
Peak memory 211668 kb
Host smart-f840f4a3-6250-4009-be74-b3b759625c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9184472679476746508182845196105229347072492277493948461231339741821135708909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.rom_ctrl_kmac_err_chk.9184472679476746508182845196105229347072492277493948461231339741821135708909
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.34938222620071469734894507362915244406308362802761863445436299275413332710956
Short name T340
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.37 seconds
Started Oct 22 01:44:34 PM PDT 23
Finished Oct 22 01:44:48 PM PDT 23
Peak memory 211176 kb
Host smart-c3722281-260e-4ee2-bb73-9147b82ad91d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34938222620071469734894507362915244406308362802761863445436299275413332710956 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.34938222620071469734894507362915244406308362802761863445436299275413332710956
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.111828937474828299963515554022272741885219082299248650192106894134844122679665
Short name T204
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.48 seconds
Started Oct 22 01:43:20 PM PDT 23
Finished Oct 22 01:43:49 PM PDT 23
Peak memory 212824 kb
Host smart-5fc59571-966d-4036-a296-60abfe6eef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111828937474828299963515554022272741885219082299248650192106894134844122679665 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_smoke.111828937474828299963515554022272741885219082299248650192106894134844122679665
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.26045615063093440171213830268811880232705637033024782839030024980370137084376
Short name T369
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.71 seconds
Started Oct 22 01:44:48 PM PDT 23
Finished Oct 22 01:45:32 PM PDT 23
Peak memory 212912 kb
Host smart-2b2ecd47-b26e-4412-b607-1d010b8205a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260456150630934401712138302688118802327056370330247828390300249
80370137084376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.260456150630934401712138302688118802327056370330247
82839030024980370137084376
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.72544389004362606461964016508955953689923495175185274692318584812350124196378
Short name T297
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Oct 22 01:43:21 PM PDT 23
Finished Oct 22 01:43:34 PM PDT 23
Peak memory 211204 kb
Host smart-85d45248-1df0-4ce7-bdbe-319e9ac38745
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72544389004362606461964016508955953689923495175185274692318584812350124196378 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.72544389004362606461964016508955953689923495175185274692318584812350124196378
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.91303730693600658472999091027320021588815730411945275303645030559341846220206
Short name T5
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.43 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:49:10 PM PDT 23
Peak memory 237724 kb
Host smart-2f5cb4ec-b725-45a6-aa49-7a93180d706b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91303730693600658472999091027320021588815730411945275303645030559341846220206 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.9130373069360065847299909102732002158881573041194527530364
5030559341846220206
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.65389642319713550910208523532601637567152723530450653943338738636102413773860
Short name T358
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.77 seconds
Started Oct 22 01:44:33 PM PDT 23
Finished Oct 22 01:44:59 PM PDT 23
Peak memory 211592 kb
Host smart-0f0cb155-9f9f-4bad-8e64-e8bb95dde2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65389642319713550910208523532601637567152723530450653943338738636102413773860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.65389642319713550910208523532601637567152723530450653943338738636102413773860
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.104211345705830343059459955143871089299560483044722089068878958565885320571576
Short name T195
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.32 seconds
Started Oct 22 01:44:42 PM PDT 23
Finished Oct 22 01:44:56 PM PDT 23
Peak memory 211168 kb
Host smart-deeab9cd-2154-489a-889f-ffbb63601974
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104211345705830343059459955143871089299560483044722089068878958565885320571576 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.104211345705830343059459955143871089299560483044722089068878958565885320571576
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.93108175263249932786847047940706691791311748743251268634199353831342840300185
Short name T237
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.05 seconds
Started Oct 22 01:43:24 PM PDT 23
Finished Oct 22 01:43:53 PM PDT 23
Peak memory 212840 kb
Host smart-bd80bd59-6463-4ea3-bf88-cb9da260d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93108175263249932786847047940706691791311748743251268634199353831342840300185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.93108175263249932786847047940706691791311748743251268634199353831342840300185
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.111651925368449575307262521710592631367584957223210248631252690343546723364060
Short name T129
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.48 seconds
Started Oct 22 01:44:38 PM PDT 23
Finished Oct 22 01:45:21 PM PDT 23
Peak memory 212964 kb
Host smart-bf4a49e5-8c04-46ac-9601-3a7a3994d986
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111651925368449575307262521710592631367584957223210248631252690
343546723364060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.11165192536844957530726252171059263136758495722321
0248631252690343546723364060
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.33544882593194407512173599555421433013155494745264424490552466381987316688678
Short name T212
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.51 seconds
Started Oct 22 01:44:15 PM PDT 23
Finished Oct 22 01:44:28 PM PDT 23
Peak memory 211220 kb
Host smart-a3a3cfa6-0c6f-4322-a40f-5e93819607ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544882593194407512173599555421433013155494745264424490552466381987316688678 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.33544882593194407512173599555421433013155494745264424490552466381987316688678
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.17858669437941684517784123384188724772804501895672527645845878334208168527246
Short name T333
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.56 seconds
Started Oct 22 01:44:47 PM PDT 23
Finished Oct 22 01:50:23 PM PDT 23
Peak memory 237656 kb
Host smart-16ac0068-4325-4b38-a836-6a04e1f4cfc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17858669437941684517784123384188724772804501895672527645845878334208168527246 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.1785866943794168451778412338418872477280450189567252764584
5878334208168527246
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.94485640552517358975692911944186216787188841005750875140070597906339094984238
Short name T187
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.11 seconds
Started Oct 22 01:45:03 PM PDT 23
Finished Oct 22 01:45:29 PM PDT 23
Peak memory 211600 kb
Host smart-f6726875-fbe6-48b0-a82b-7fd15ae27c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94485640552517358975692911944186216787188841005750875140070597906339094984238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rom_ctrl_kmac_err_chk.94485640552517358975692911944186216787188841005750875140070597906339094984238
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.85452652430512571792717681774592330467132656781431413182719648109897906980982
Short name T105
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 22 01:43:28 PM PDT 23
Finished Oct 22 01:43:42 PM PDT 23
Peak memory 211240 kb
Host smart-0d7a3299-f5e0-4cf6-b2e2-38392c24c965
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85452652430512571792717681774592330467132656781431413182719648109897906980982 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.85452652430512571792717681774592330467132656781431413182719648109897906980982
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.96031774154586954514291547795359404634745149423274288358237707841859781211575
Short name T221
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.99 seconds
Started Oct 22 01:44:36 PM PDT 23
Finished Oct 22 01:45:05 PM PDT 23
Peak memory 212860 kb
Host smart-caea3fc9-c8bc-4bd0-8896-c4300c684d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96031774154586954514291547795359404634745149423274288358237707841859781211575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.96031774154586954514291547795359404634745149423274288358237707841859781211575
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.49835970112070254897684205537997277446342222981399174477202716074353385768357
Short name T200
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.37 seconds
Started Oct 22 01:45:00 PM PDT 23
Finished Oct 22 01:45:43 PM PDT 23
Peak memory 212948 kb
Host smart-a5f6ea75-21b0-46c0-85cc-38c57cc1973e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498359701120702548976842055379972774463422229813991744772027160
74353385768357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.498359701120702548976842055379972774463422229813991
74477202716074353385768357
Directory /workspace/9.rom_ctrl_stress_all/latest
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