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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T261 /workspace/coverage/default/8.rom_ctrl_alert_test.14160606253921437256628817485323272474016990850256853862780703586958951703936 Oct 25 01:50:42 PM PDT 23 Oct 25 01:50:55 PM PDT 23 3124113076 ps
T262 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.98439406222991499777497598681107125408461369657681032813114742702955479020530 Oct 25 01:51:08 PM PDT 23 Oct 25 01:51:34 PM PDT 23 6233818126 ps
T263 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.112581381028142442577289294789193032981653742516079675515652459690362363471732 Oct 25 01:50:18 PM PDT 23 Oct 25 01:50:32 PM PDT 23 3151732636 ps
T264 /workspace/coverage/default/10.rom_ctrl_smoke.78826584503433977377815549142187255538596519366408884142383620292155243521053 Oct 25 01:50:47 PM PDT 23 Oct 25 01:51:16 PM PDT 23 6265461576 ps
T265 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.18730310428059470889917242453430368966930759746274249636137543700426492502195 Oct 25 01:50:21 PM PDT 23 Oct 25 01:50:48 PM PDT 23 6233818126 ps
T266 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.45163275656071106961540444470472489354743052331921453520184515957168145834304 Oct 25 01:51:13 PM PDT 23 Oct 25 01:51:39 PM PDT 23 6233818126 ps
T267 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.88154206387201476112688042999355307694276500274519502226041574451571215146653 Oct 25 01:51:24 PM PDT 23 Oct 25 01:57:10 PM PDT 23 69854280986 ps
T268 /workspace/coverage/default/10.rom_ctrl_stress_all.58752253954572708264345431214658868860280162960625412089405793999039365301842 Oct 25 01:50:57 PM PDT 23 Oct 25 01:51:40 PM PDT 23 9415977006 ps
T269 /workspace/coverage/default/41.rom_ctrl_smoke.75910057186160308235226408097474453548204271207871129790509000775533143095444 Oct 25 01:51:24 PM PDT 23 Oct 25 01:51:53 PM PDT 23 6265461576 ps
T270 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.33236551593092573286401432950760184946510313179061378239951726555210189111586 Oct 25 01:51:42 PM PDT 23 Oct 25 01:51:56 PM PDT 23 3151732636 ps
T271 /workspace/coverage/default/34.rom_ctrl_smoke.21377403237144929752217005945792821609998846162819265418257445690850296034565 Oct 25 01:51:12 PM PDT 23 Oct 25 01:51:41 PM PDT 23 6265461576 ps
T272 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.41159401433570963339736974888406594036464123648012559613761329096203010999486 Oct 25 01:51:44 PM PDT 23 Oct 25 01:51:58 PM PDT 23 3151732636 ps
T273 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.91313860817494121865138761313836250332610435785929917049743536155977056802593 Oct 25 01:51:21 PM PDT 23 Oct 25 01:51:48 PM PDT 23 6233818126 ps
T274 /workspace/coverage/default/47.rom_ctrl_stress_all.64959111839931508700586959220987599230339755080451057567219471124470306588391 Oct 25 01:51:25 PM PDT 23 Oct 25 01:52:09 PM PDT 23 9415977006 ps
T275 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.44212596168788975874556725723127073541090180700081095966175110165292277106078 Oct 25 01:51:45 PM PDT 23 Oct 25 01:57:25 PM PDT 23 69854280986 ps
T276 /workspace/coverage/default/28.rom_ctrl_smoke.23547028898985109043097752905490376056060170071601606242242713496861808993670 Oct 25 01:51:41 PM PDT 23 Oct 25 01:52:11 PM PDT 23 6265461576 ps
T277 /workspace/coverage/default/7.rom_ctrl_alert_test.54161823283329701393108836351598717094508330548684767905323405585038302763485 Oct 25 01:50:43 PM PDT 23 Oct 25 01:50:56 PM PDT 23 3124113076 ps
T278 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.112085921513153749569304280095811123387857081107524843257003267247992236739509 Oct 25 01:50:21 PM PDT 23 Oct 25 01:50:47 PM PDT 23 6233818126 ps
T279 /workspace/coverage/default/18.rom_ctrl_smoke.31502318635663113031216945386845546931479828188267252266839664718950609698673 Oct 25 01:51:02 PM PDT 23 Oct 25 01:51:31 PM PDT 23 6265461576 ps
T280 /workspace/coverage/default/42.rom_ctrl_alert_test.106674625879119593918498454556267748542601381805643937087934290368654112911397 Oct 25 01:51:45 PM PDT 23 Oct 25 01:51:58 PM PDT 23 3124113076 ps
T281 /workspace/coverage/default/42.rom_ctrl_stress_all.2591256430438153934581805063006831913875347191793726282653175837911028878851 Oct 25 01:51:40 PM PDT 23 Oct 25 01:52:24 PM PDT 23 9415977006 ps
T282 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.109381942560824735157860987062892162405387851223929717008052599516265142987127 Oct 25 01:51:00 PM PDT 23 Oct 25 01:51:26 PM PDT 23 6233818126 ps
T283 /workspace/coverage/default/22.rom_ctrl_smoke.52302131493331631160847009114670911224041503879099547183587740754666588314332 Oct 25 01:50:46 PM PDT 23 Oct 25 01:51:15 PM PDT 23 6265461576 ps
T284 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.96047967401340523606771056628705402091876641001623423715079502247796428057678 Oct 25 01:50:21 PM PDT 23 Oct 25 01:50:47 PM PDT 23 6233818126 ps
T285 /workspace/coverage/default/11.rom_ctrl_alert_test.110431882945379342736679503334999992493031645193534658118878465534328846412484 Oct 25 01:50:48 PM PDT 23 Oct 25 01:51:02 PM PDT 23 3124113076 ps
T286 /workspace/coverage/default/21.rom_ctrl_stress_all.63224968927396733853912417311088553827899258995391998967446885985132228429316 Oct 25 01:50:46 PM PDT 23 Oct 25 01:51:29 PM PDT 23 9415977006 ps
T287 /workspace/coverage/default/30.rom_ctrl_stress_all.9769672060639822100242104924902300092847879939114042420463024009875922480467 Oct 25 01:51:13 PM PDT 23 Oct 25 01:51:57 PM PDT 23 9415977006 ps
T288 /workspace/coverage/default/1.rom_ctrl_stress_all.52321675425581696615828806776023169770267249803331679077124421697374103044732 Oct 25 01:50:25 PM PDT 23 Oct 25 01:51:07 PM PDT 23 9415977006 ps
T289 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.79910293326339791721914539141282176866775952800192488658427327517341882384471 Oct 25 01:50:42 PM PDT 23 Oct 25 01:56:24 PM PDT 23 69854280986 ps
T290 /workspace/coverage/default/27.rom_ctrl_alert_test.42652161496699722547113926129366932390081151966592210365066345097376587061320 Oct 25 01:50:42 PM PDT 23 Oct 25 01:50:55 PM PDT 23 3124113076 ps
T291 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.83702548070830791850988412360116818498173717348674249398468275451221132580867 Oct 25 01:51:53 PM PDT 23 Oct 25 01:52:21 PM PDT 23 6233818126 ps
T292 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.17933249588873055508174266533615771447143498843983882062614841456564577469035 Oct 25 01:51:38 PM PDT 23 Oct 25 01:57:23 PM PDT 23 69854280986 ps
T293 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.34930931602922939247552241173205363147804901933665172327605309849928073658705 Oct 25 01:50:43 PM PDT 23 Oct 25 01:50:57 PM PDT 23 3151732636 ps
T294 /workspace/coverage/default/41.rom_ctrl_alert_test.64479784201662158440237308363272486020896700253189994662744771179685831116053 Oct 25 01:51:46 PM PDT 23 Oct 25 01:51:59 PM PDT 23 3124113076 ps
T295 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.107092044521127261916485982359067502145765062336031476005910257314066339935511 Oct 25 01:51:47 PM PDT 23 Oct 25 01:52:01 PM PDT 23 3151732636 ps
T296 /workspace/coverage/default/10.rom_ctrl_alert_test.71299432409709236216976626268475636990212075301108808773166522786163940031400 Oct 25 01:51:27 PM PDT 23 Oct 25 01:51:40 PM PDT 23 3124113076 ps
T297 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.35000777589083585169643335359596961968798568792184222449431463351563486199673 Oct 25 01:50:56 PM PDT 23 Oct 25 01:51:10 PM PDT 23 3151732636 ps
T298 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.99917500934010537766886269450287418010392606545495416562040365262876676838830 Oct 25 01:50:24 PM PDT 23 Oct 25 01:50:38 PM PDT 23 3151732636 ps
T299 /workspace/coverage/default/11.rom_ctrl_smoke.74963690685086110696684591749136879463191234223794897111798769973399051088859 Oct 25 01:50:48 PM PDT 23 Oct 25 01:51:16 PM PDT 23 6265461576 ps
T300 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.60222639026101593952093102875582288790077630262496152500228928784111779550217 Oct 25 01:50:43 PM PDT 23 Oct 25 01:51:09 PM PDT 23 6233818126 ps
T301 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.25435520629886520626196196878423333755584562243643681648669847322287137682957 Oct 25 01:50:21 PM PDT 23 Oct 25 01:56:05 PM PDT 23 69854280986 ps
T302 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.91673046129464985904573047524024264572285987143601639905607942117835105237277 Oct 25 01:50:57 PM PDT 23 Oct 25 01:51:10 PM PDT 23 3151732636 ps
T303 /workspace/coverage/default/7.rom_ctrl_stress_all.34874118263332846408896042770419171471801620293753508100038307568432251978868 Oct 25 01:50:23 PM PDT 23 Oct 25 01:51:06 PM PDT 23 9415977006 ps
T304 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.80374349210003994999805166967873175906521842811684388506546570964530085866118 Oct 25 01:50:23 PM PDT 23 Oct 25 01:56:09 PM PDT 23 69854280986 ps
T305 /workspace/coverage/default/6.rom_ctrl_smoke.79251803801235228013817843661684135115496614164508651067912861280715003250776 Oct 25 01:50:20 PM PDT 23 Oct 25 01:50:50 PM PDT 23 6265461576 ps
T306 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.56413556761706762447370877438784686073793191057652009425817144008424680767537 Oct 25 01:51:45 PM PDT 23 Oct 25 01:57:36 PM PDT 23 69854280986 ps
T307 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.52346513891310821670585565433667097708683132157402794563607214353592078118510 Oct 25 01:51:13 PM PDT 23 Oct 25 01:51:27 PM PDT 23 3151732636 ps
T308 /workspace/coverage/default/1.rom_ctrl_alert_test.30116395089921157691147127347087408020300595789969344248949117782396387730079 Oct 25 01:50:42 PM PDT 23 Oct 25 01:50:54 PM PDT 23 3124113076 ps
T309 /workspace/coverage/default/17.rom_ctrl_stress_all.92861098180936132951013940796652617068483810540158858878866117239745688715487 Oct 25 01:51:26 PM PDT 23 Oct 25 01:52:10 PM PDT 23 9415977006 ps
T34 /workspace/coverage/default/0.rom_ctrl_sec_cm.106470952250699353703735985289767064327086567879866048869701417017877044824426 Oct 25 01:50:23 PM PDT 23 Oct 25 01:52:20 PM PDT 23 3444857586 ps
T310 /workspace/coverage/default/46.rom_ctrl_smoke.84624156404161748887407614111180488369043912044280484947726842357179869812364 Oct 25 01:51:52 PM PDT 23 Oct 25 01:52:20 PM PDT 23 6265461576 ps
T311 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.44399375701471461466727337509424470821523089055853153446343254263011522762307 Oct 25 01:51:21 PM PDT 23 Oct 25 01:51:48 PM PDT 23 6233818126 ps
T312 /workspace/coverage/default/42.rom_ctrl_smoke.7491678184895086404836404245450614907942390033009683679345333465148390590461 Oct 25 01:51:31 PM PDT 23 Oct 25 01:52:01 PM PDT 23 6265461576 ps
T313 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.13825765439329901214992244743805399175531409119393822573386675080263126782234 Oct 25 01:51:45 PM PDT 23 Oct 25 01:52:11 PM PDT 23 6233818126 ps
T314 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.39146776310723939150102288309153411934943411962634363395426355136268797065042 Oct 25 01:51:38 PM PDT 23 Oct 25 01:51:52 PM PDT 23 3151732636 ps
T315 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.65325808162086150729594729994907550398813970684916708917977941654513489287394 Oct 25 01:50:43 PM PDT 23 Oct 25 01:50:57 PM PDT 23 3151732636 ps
T316 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.102302345415004402395672065674966368036485827880419363829263873675013555267082 Oct 25 01:51:07 PM PDT 23 Oct 25 01:51:21 PM PDT 23 3151732636 ps
T317 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3478149215723151188638582971437039938759102382980034373899562301557917787701 Oct 25 01:50:37 PM PDT 23 Oct 25 01:50:51 PM PDT 23 3151732636 ps
T318 /workspace/coverage/default/22.rom_ctrl_alert_test.67600999347607047614830088183732953027154338595496859692052027158121215166701 Oct 25 01:50:45 PM PDT 23 Oct 25 01:50:57 PM PDT 23 3124113076 ps
T319 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.84324729973453394031233671920330996603056997680066166983294726676151487287522 Oct 25 01:50:43 PM PDT 23 Oct 25 01:56:32 PM PDT 23 69854280986 ps
T320 /workspace/coverage/default/12.rom_ctrl_stress_all.16442651201201691585313493967739642928320863147936446050517878818334494929588 Oct 25 01:50:40 PM PDT 23 Oct 25 01:51:23 PM PDT 23 9415977006 ps
T321 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.72784814663772109180069799592557523630541135513309905109164354682808940022499 Oct 25 01:51:38 PM PDT 23 Oct 25 01:57:26 PM PDT 23 69854280986 ps
T322 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.73266721107218989835500619869307475858515623257051183069732053563615903571232 Oct 25 01:51:28 PM PDT 23 Oct 25 01:57:15 PM PDT 23 69854280986 ps
T323 /workspace/coverage/default/15.rom_ctrl_alert_test.3540774199931160834672508672075250171065519341234863280252266865056609087569 Oct 25 01:50:47 PM PDT 23 Oct 25 01:50:59 PM PDT 23 3124113076 ps
T324 /workspace/coverage/default/16.rom_ctrl_alert_test.57971711685404697666214599026258419712413037558094257715006449290132658828748 Oct 25 01:51:25 PM PDT 23 Oct 25 01:51:38 PM PDT 23 3124113076 ps
T325 /workspace/coverage/default/36.rom_ctrl_smoke.61572653659569545026216136415161476036939275352612829490043181640636369277580 Oct 25 01:51:42 PM PDT 23 Oct 25 01:52:11 PM PDT 23 6265461576 ps
T326 /workspace/coverage/default/20.rom_ctrl_smoke.92086214487933461450259610286389485245676451702248901709386833810510484874417 Oct 25 01:51:40 PM PDT 23 Oct 25 01:52:09 PM PDT 23 6265461576 ps
T327 /workspace/coverage/default/23.rom_ctrl_stress_all.36355330076157251391429669207652487209344622566020923233313642683413660883754 Oct 25 01:51:24 PM PDT 23 Oct 25 01:52:07 PM PDT 23 9415977006 ps
T328 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.72749621395426975038623036124083505245534850802685688693233610778241878852438 Oct 25 01:50:39 PM PDT 23 Oct 25 01:56:24 PM PDT 23 69854280986 ps
T329 /workspace/coverage/default/31.rom_ctrl_smoke.30582538762021442350842591842836838095646816722320002744431987257180881106930 Oct 25 01:51:05 PM PDT 23 Oct 25 01:51:34 PM PDT 23 6265461576 ps
T330 /workspace/coverage/default/23.rom_ctrl_alert_test.41997549314454287768639830420999761355908375664018203456842572511311853147746 Oct 25 01:51:11 PM PDT 23 Oct 25 01:51:24 PM PDT 23 3124113076 ps
T331 /workspace/coverage/default/46.rom_ctrl_stress_all.81081392934620608960177772226930666065185248664146206825944801194767067576917 Oct 25 01:51:52 PM PDT 23 Oct 25 01:52:36 PM PDT 23 9415977006 ps
T332 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.13245769766790534820527585229607441006946277090327748773938574940185271219028 Oct 25 01:51:45 PM PDT 23 Oct 25 01:57:14 PM PDT 23 69854280986 ps
T333 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.56534613107955738652041580103541025169998612872011430437867953261729272174064 Oct 25 01:51:50 PM PDT 23 Oct 25 01:52:16 PM PDT 23 6233818126 ps
T334 /workspace/coverage/default/14.rom_ctrl_smoke.19112228119090998847309136274367013521164770014778152141311621780629287138060 Oct 25 01:50:42 PM PDT 23 Oct 25 01:51:11 PM PDT 23 6265461576 ps
T335 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.14020198836874579354020117286801213497694311940205057260033972900096968747872 Oct 25 01:50:21 PM PDT 23 Oct 25 01:50:35 PM PDT 23 3151732636 ps
T336 /workspace/coverage/default/27.rom_ctrl_smoke.2613785975847600308227128197275508602896391935188234837508219174394004179160 Oct 25 01:51:48 PM PDT 23 Oct 25 01:52:17 PM PDT 23 6265461576 ps
T337 /workspace/coverage/default/36.rom_ctrl_alert_test.1398731985242406828054610693207388981117654061272280515635903653753914312680 Oct 25 01:51:48 PM PDT 23 Oct 25 01:52:01 PM PDT 23 3124113076 ps
T338 /workspace/coverage/default/29.rom_ctrl_smoke.16083162351351054961900952206052237549548774348055627619970416067657692319428 Oct 25 01:50:40 PM PDT 23 Oct 25 01:51:09 PM PDT 23 6265461576 ps
T339 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.20872926029523391952424820782683402402156918757004416578542945627681718941499 Oct 25 01:50:42 PM PDT 23 Oct 25 01:56:24 PM PDT 23 69854280986 ps
T340 /workspace/coverage/default/17.rom_ctrl_smoke.80021178892017252620655018343707969242625847119452563063289651198501660783610 Oct 25 01:51:01 PM PDT 23 Oct 25 01:51:30 PM PDT 23 6265461576 ps
T341 /workspace/coverage/default/33.rom_ctrl_alert_test.105078189088797087977634041179519375786083231481073298202057280967621089280426 Oct 25 01:50:58 PM PDT 23 Oct 25 01:51:11 PM PDT 23 3124113076 ps
T342 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.52896346381073103909235271867855076505059446718310227087000654627125160692649 Oct 25 01:50:48 PM PDT 23 Oct 25 01:56:30 PM PDT 23 69854280986 ps
T343 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.55023511958357416762469391341356421242775455853766814930781549247544600773413 Oct 25 01:51:47 PM PDT 23 Oct 25 01:52:13 PM PDT 23 6233818126 ps
T344 /workspace/coverage/default/46.rom_ctrl_alert_test.82131926670691535814666308308326971516390755031606184634302023955481203347079 Oct 25 01:50:56 PM PDT 23 Oct 25 01:51:09 PM PDT 23 3124113076 ps
T345 /workspace/coverage/default/9.rom_ctrl_stress_all.66262569916677710926110621747105768361290169759725309503449273234362984033139 Oct 25 01:50:45 PM PDT 23 Oct 25 01:51:28 PM PDT 23 9415977006 ps
T346 /workspace/coverage/default/20.rom_ctrl_stress_all.36126366708351199345681862750742218698848317625677166398468069740075964437976 Oct 25 01:51:40 PM PDT 23 Oct 25 01:52:24 PM PDT 23 9415977006 ps
T347 /workspace/coverage/default/45.rom_ctrl_alert_test.49135192142813418228511174903443069348965897216031672465658587956682376673011 Oct 25 01:51:52 PM PDT 23 Oct 25 01:52:05 PM PDT 23 3124113076 ps
T348 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.21568189639469790982939358501964180640094511138236538994948585326738803984516 Oct 25 01:51:49 PM PDT 23 Oct 25 01:52:15 PM PDT 23 6233818126 ps
T349 /workspace/coverage/default/32.rom_ctrl_smoke.54238669174049735076450611179591481670200069363845546505609797739249473776496 Oct 25 01:51:24 PM PDT 23 Oct 25 01:51:53 PM PDT 23 6265461576 ps
T350 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.115697888519955528321490460135215541491569994851420393446258710418634485160325 Oct 25 01:51:28 PM PDT 23 Oct 25 01:51:42 PM PDT 23 3151732636 ps
T351 /workspace/coverage/default/28.rom_ctrl_alert_test.11294675020283138443969550814732396310778359941994882334294762046464108943244 Oct 25 01:50:45 PM PDT 23 Oct 25 01:50:58 PM PDT 23 3124113076 ps
T352 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.74154160383439238366445679466676014782442875033397243473600501524216351024081 Oct 25 01:51:12 PM PDT 23 Oct 25 01:56:56 PM PDT 23 69854280986 ps
T353 /workspace/coverage/default/5.rom_ctrl_alert_test.101676887876504693477955853829986992865126548948973598243123265518915279985947 Oct 25 01:50:17 PM PDT 23 Oct 25 01:50:30 PM PDT 23 3124113076 ps
T354 /workspace/coverage/default/0.rom_ctrl_alert_test.20708341059294745687921148740897772282026978889526760313893182994585042718521 Oct 25 01:50:40 PM PDT 23 Oct 25 01:50:53 PM PDT 23 3124113076 ps
T355 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.25005879884391215509976412331433716010429227088280896153091103491728933972931 Oct 25 01:50:44 PM PDT 23 Oct 25 01:50:58 PM PDT 23 3151732636 ps
T356 /workspace/coverage/default/20.rom_ctrl_alert_test.12257284349584766324387958405937284835367593959232337517260783518172221201612 Oct 25 01:51:48 PM PDT 23 Oct 25 01:52:01 PM PDT 23 3124113076 ps
T357 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.44686282498600432837988570848567846545694389790502300038780100361575146324147 Oct 25 01:52:40 PM PDT 23 Oct 25 01:52:54 PM PDT 23 3151732636 ps
T358 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.72481618609829054089797006468490254772405945644403277913756594939019890951925 Oct 25 01:50:44 PM PDT 23 Oct 25 01:56:17 PM PDT 23 69854280986 ps
T359 /workspace/coverage/default/8.rom_ctrl_smoke.33193503699368623818491969748661342158356951783105973118580746346236839389131 Oct 25 01:50:43 PM PDT 23 Oct 25 01:51:11 PM PDT 23 6265461576 ps
T360 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.21318616681447905071838771675399452694672752635459530760624099235239188991812 Oct 25 01:50:42 PM PDT 23 Oct 25 01:51:08 PM PDT 23 6233818126 ps
T361 /workspace/coverage/default/2.rom_ctrl_alert_test.113141245629704814505922618556283320891720005613536879246190159442537071861140 Oct 25 01:50:48 PM PDT 23 Oct 25 01:51:00 PM PDT 23 3124113076 ps
T362 /workspace/coverage/default/14.rom_ctrl_alert_test.70272224019913376876707474105998191800071078075315638427339193040910114387007 Oct 25 01:50:42 PM PDT 23 Oct 25 01:50:56 PM PDT 23 3124113076 ps
T363 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.88750376292431747727625037228595006538581485633650194494503719710264602369003 Oct 25 01:50:51 PM PDT 23 Oct 25 01:51:17 PM PDT 23 6233818126 ps
T364 /workspace/coverage/default/19.rom_ctrl_smoke.79179924468537915168460582477630846624509178320300820403297837879234104349217 Oct 25 01:51:23 PM PDT 23 Oct 25 01:51:53 PM PDT 23 6265461576 ps
T83 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.89315303392967609021853590459425879914500378632909148120413189355018312859472 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:48 PM PDT 23 3124113076 ps
T365 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.66791788968533834412146023390632750262889529338411851231138256834243261508374 Oct 25 02:12:18 PM PDT 23 Oct 25 02:13:41 PM PDT 23 3476453456 ps
T366 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.8366128816141669883431541666896541199724430302282767850183497889394674342338 Oct 25 02:12:33 PM PDT 23 Oct 25 02:12:46 PM PDT 23 3135422826 ps
T367 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.77442177955655428611501614708514437338405394480951131578911515560266220538080 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:30 PM PDT 23 3135422826 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.15358930453656360999138323757553837035433170221778303422280403122193700059502 Oct 25 02:12:05 PM PDT 23 Oct 25 02:12:18 PM PDT 23 3135422826 ps
T369 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.74562571482101053528603974262656408125257989693350719291304762210655588447053 Oct 25 02:12:53 PM PDT 23 Oct 25 02:13:08 PM PDT 23 3142303916 ps
T370 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.14343080715500295261006622722902512697521098715164968334971013888075186143445 Oct 25 02:13:04 PM PDT 23 Oct 25 02:13:17 PM PDT 23 3135422826 ps
T60 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.18105034296742016729385549240069736572828411552061006341332511018096699819100 Oct 25 02:11:20 PM PDT 23 Oct 25 02:11:37 PM PDT 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.53446207252400643822431187024658041530448846970324796924963191274287435286311 Oct 25 02:12:54 PM PDT 23 Oct 25 02:14:16 PM PDT 23 3476453456 ps
T372 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.81645420369537888724847646190869569711742089331113605714969584142726680833026 Oct 25 02:11:20 PM PDT 23 Oct 25 02:12:42 PM PDT 23 3476453456 ps
T373 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.66548614425844367886550002182678498076781860110650930113125630623884586650610 Oct 25 02:12:42 PM PDT 23 Oct 25 02:12:57 PM PDT 23 3142303916 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.57880027342747248833694496449373240427999195371353065448667091667467468219734 Oct 25 02:12:58 PM PDT 23 Oct 25 02:13:11 PM PDT 23 3124113076 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.107392733457819169727633378261348106316691857039284132492609494427491979323909 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:29 PM PDT 23 3124113076 ps
T85 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.100081235254067205504126260913157042390127662352542299811448685075266301993646 Oct 25 02:12:13 PM PDT 23 Oct 25 02:12:26 PM PDT 23 3124113076 ps
T375 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.113625699654488959036471369585117403900381322876238106507001961469792805160508 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:47 PM PDT 23 3124113076 ps
T376 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.110738601903960959814269979858380303324225024036317319951165876766148753608239 Oct 25 02:12:41 PM PDT 23 Oct 25 02:14:03 PM PDT 23 3476453456 ps
T377 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.30429096732386064851116300970336548265052581325666965626189582513455356084010 Oct 25 02:12:55 PM PDT 23 Oct 25 02:13:08 PM PDT 23 3124113076 ps
T61 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.28605833359293721118899368574862784556956232087303386433805442989801411919614 Oct 25 02:12:21 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3124113076 ps
T378 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.36195853133396648584044853204873719666459541862530350601823518034998858105691 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:46 PM PDT 23 3124113076 ps
T379 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.14912279575112737665023801560590107711694184992292141138057881295715183481384 Oct 25 02:12:19 PM PDT 23 Oct 25 02:12:31 PM PDT 23 3124113076 ps
T380 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.51188876014612797557746456548165983164138222747855278810969242946555269437858 Oct 25 02:11:29 PM PDT 23 Oct 25 02:12:50 PM PDT 23 3476453456 ps
T66 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.16900648021389943322180325859823089102672168024976440062348746758677914723562 Oct 25 02:12:07 PM PDT 23 Oct 25 02:16:53 PM PDT 23 65914678386 ps
T381 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.37253571761062241050679161037117805147815238434163526105220059256240722779905 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:48 PM PDT 23 3135422826 ps
T382 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.110830407100179515544561573703703493446914652649033483672223011227373042276031 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:27 PM PDT 23 3124113076 ps
T67 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.71129858699759589158028451038700050884097563999232779322186952298185808332873 Oct 25 02:12:22 PM PDT 23 Oct 25 02:17:05 PM PDT 23 65914678386 ps
T383 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.64824830970221786681254836238824663432088205984557359720035942815360701393594 Oct 25 02:12:41 PM PDT 23 Oct 25 02:14:05 PM PDT 23 3476453456 ps
T384 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.22245287265653880453550686666855053069866607847440767204775133403440402780822 Oct 25 02:12:21 PM PDT 23 Oct 25 02:12:34 PM PDT 23 3124113076 ps
T68 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.6647904190257086932532471983325909939584637239022533714815204545156811244774 Oct 25 02:12:18 PM PDT 23 Oct 25 02:17:01 PM PDT 23 65914678386 ps
T385 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.28753750002362687992358831833390709413452920877903396295864384711827669164823 Oct 25 02:11:20 PM PDT 23 Oct 25 02:11:34 PM PDT 23 3142303916 ps
T69 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.58006132121654729147749527869680410710362641533350791326978129757811770765972 Oct 25 02:11:20 PM PDT 23 Oct 25 02:16:06 PM PDT 23 65914678386 ps
T386 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.12043948793129122675024805069575774060118503478854768530186290296382877563398 Oct 25 02:12:08 PM PDT 23 Oct 25 02:12:21 PM PDT 23 3124113076 ps
T387 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.94160831084887710771511534614717852789996174903714458513224673229688951375428 Oct 25 02:12:33 PM PDT 23 Oct 25 02:12:48 PM PDT 23 3142303916 ps
T388 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.11603249498625009186419567667300647987299957161130927259633150426039446528147 Oct 25 02:12:41 PM PDT 23 Oct 25 02:17:28 PM PDT 23 65914678386 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.55175152357235713300262253742664126526260125078797179808634502744779367654004 Oct 25 02:12:59 PM PDT 23 Oct 25 02:14:22 PM PDT 23 3476453456 ps
T390 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.90532740308077152833154211881146952926565838685587681923865880231319861815805 Oct 25 02:12:42 PM PDT 23 Oct 25 02:12:58 PM PDT 23 3124113076 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.20003575626553813547446548070875406074393308532767824406685990001510314854809 Oct 25 02:12:14 PM PDT 23 Oct 25 02:12:27 PM PDT 23 3124113076 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.37271611401441762487611268812322399405015408199954792676679293829958299496014 Oct 25 02:12:16 PM PDT 23 Oct 25 02:17:01 PM PDT 23 65914678386 ps
T393 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.110803389748547661926194997844737323254338190982474118000068623974351174923075 Oct 25 02:12:53 PM PDT 23 Oct 25 02:13:05 PM PDT 23 3124113076 ps
T394 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.55633759754117501074467919207690276408378281772467211328683898012744329236159 Oct 25 02:12:15 PM PDT 23 Oct 25 02:17:03 PM PDT 23 65914678386 ps
T395 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.22534738428822139923601300865797151830062087805860435112714805591869677546681 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:28 PM PDT 23 3124113076 ps
T396 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.20833436596369555271158670600607835731183229926403608923985433788580449890005 Oct 25 02:12:18 PM PDT 23 Oct 25 02:13:41 PM PDT 23 3476453456 ps
T397 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.34188939834075798069232783478301550446742833450575475129171969084805096898208 Oct 25 02:12:54 PM PDT 23 Oct 25 02:17:41 PM PDT 23 65914678386 ps
T398 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42164926662996590705266961228593883889105183585250531025072190750055965896374 Oct 25 02:12:08 PM PDT 23 Oct 25 02:12:20 PM PDT 23 3124113076 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.47978501686155455232213209936689961812970700254077518626980156217482270649384 Oct 25 02:11:32 PM PDT 23 Oct 25 02:11:45 PM PDT 23 3124113076 ps
T400 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.67739899498700339371788302488836430630785420562330508370441840306444615802450 Oct 25 02:12:20 PM PDT 23 Oct 25 02:12:34 PM PDT 23 3135422826 ps
T401 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.25330725618398707510413595741204959573486852105932842358876039257553099818017 Oct 25 02:11:57 PM PDT 23 Oct 25 02:12:13 PM PDT 23 3138518126 ps
T402 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.74449314783511187972027826842743828751520241920587429759479504005497277289956 Oct 25 02:12:33 PM PDT 23 Oct 25 02:12:47 PM PDT 23 3142303916 ps
T403 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.46352965709477229457603967056075592626125941989949014003654477203898517799934 Oct 25 02:11:40 PM PDT 23 Oct 25 02:11:53 PM PDT 23 3135422826 ps
T404 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2009208418079832635269665101892337713711699002134834538373949351017448268105 Oct 25 02:12:54 PM PDT 23 Oct 25 02:14:15 PM PDT 23 3476453456 ps
T405 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.65781169510655440932565448480700887570839991502488043964551689941655461500904 Oct 25 02:12:16 PM PDT 23 Oct 25 02:12:30 PM PDT 23 3142303916 ps
T406 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.90504250243512685964687534337617584444566090427617175889501224453418948429633 Oct 25 02:12:18 PM PDT 23 Oct 25 02:17:05 PM PDT 23 65914678386 ps
T407 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.43422173963324039197963589263448133652931502267300372545330522214954349756073 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:31 PM PDT 23 3124113076 ps
T408 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.53542668875053034217679079760568122427127559651543134808818082611523693157376 Oct 25 02:11:37 PM PDT 23 Oct 25 02:16:22 PM PDT 23 65914678386 ps
T409 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.81100271731038332658106121045706571911082045664635684612277253613571976697017 Oct 25 02:12:14 PM PDT 23 Oct 25 02:13:37 PM PDT 23 3476453456 ps
T410 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.40211981134278325007723582850677081500599719025015094311731891333153858717822 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:30 PM PDT 23 3135422826 ps
T411 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.47340540287768478345443245431012818381794148625041686709536115676799209602276 Oct 25 02:12:20 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.77544954322527650631208271107472612601400551652168163890155216511017416729367 Oct 25 02:12:53 PM PDT 23 Oct 25 02:13:05 PM PDT 23 3124113076 ps
T413 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.113888880325344483921938746080600537612987240945390977439440180213500652565222 Oct 25 02:11:41 PM PDT 23 Oct 25 02:11:58 PM PDT 23 3124113076 ps
T414 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.84772407952897796607192503916765939781007046713502522462655829101070005713706 Oct 25 02:12:21 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3124113076 ps
T415 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.76561594949925012420148898308095105700338374573683493300072047250327169056280 Oct 25 02:11:17 PM PDT 23 Oct 25 02:11:30 PM PDT 23 3135422826 ps
T416 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.94163882731208137987175024663621766572986698822384460197848590807496668075660 Oct 25 02:12:04 PM PDT 23 Oct 25 02:12:19 PM PDT 23 3142303916 ps
T417 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.96156255512441943983891423614076809487808311887961470065505325527529466765713 Oct 25 02:12:25 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3135422826 ps
T418 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.18569429513467157880227370633602161927189884614319487440615452331888474968851 Oct 25 02:12:39 PM PDT 23 Oct 25 02:17:23 PM PDT 23 65914678386 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.16997351103174594261889458474013213943356335681407236596077973761038790242355 Oct 25 02:12:22 PM PDT 23 Oct 25 02:13:42 PM PDT 23 3476453456 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.88862797762955300338220754630783412704133332287991054667900436939785992391594 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:48 PM PDT 23 3124113076 ps
T421 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.98654915784177088723491480254901866808854051768604220178090493714125386117464 Oct 25 02:12:53 PM PDT 23 Oct 25 02:17:41 PM PDT 23 65914678386 ps
T422 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.74560554740654596318677826019124104052660179868073744837216286757239570374002 Oct 25 02:12:37 PM PDT 23 Oct 25 02:12:54 PM PDT 23 3124113076 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.76016836124505887689709003510319862801986155915068512352219608563032578990585 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:29 PM PDT 23 3124113076 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.19317552672696759743737596530365992234583193817760325598712208423115394274484 Oct 25 02:12:55 PM PDT 23 Oct 25 02:17:41 PM PDT 23 65914678386 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.76017325712157561370627740035135295275174199231542955278385019874759338793341 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:35 PM PDT 23 3124113076 ps
T426 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.69454382618736108393392573079559414851309602932001690253367133482408582202579 Oct 25 02:13:01 PM PDT 23 Oct 25 02:13:17 PM PDT 23 3124113076 ps
T427 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.41427318732895465665568891423265359907808246030525003603532949774217985256657 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:25 PM PDT 23 3124113076 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.66275854297431192584939399362787938459143734168635577513138705693396241778413 Oct 25 02:12:23 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3142303916 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.77307586025227276689553424768849244920391409442420631171492830640169759655730 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:33 PM PDT 23 3124113076 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.52495687054736197510475509082275682365382147202121198608752918611088644390850 Oct 25 02:12:59 PM PDT 23 Oct 25 02:13:11 PM PDT 23 3135422826 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.5438944785255640721842670353561927383463769839102625676213065092981373344518 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:34 PM PDT 23 3124113076 ps
T432 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.41635098011633129243651790769163260515815277466364738700502806432893122027470 Oct 25 02:11:30 PM PDT 23 Oct 25 02:11:46 PM PDT 23 3138518126 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.16707806903091376280561649643479700930281553797619365651187356383011915429768 Oct 25 02:12:39 PM PDT 23 Oct 25 02:12:52 PM PDT 23 3135422826 ps
T434 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.44664137605957325989200063549743043974865853770525439477128879370371145428517 Oct 25 02:12:21 PM PDT 23 Oct 25 02:12:34 PM PDT 23 3124113076 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.16214402616323081284671341901615812731174676999946738366005810295699626813056 Oct 25 02:11:27 PM PDT 23 Oct 25 02:11:39 PM PDT 23 3124113076 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.41136752772080482936774067991046772627887316856004225385407742783237550996953 Oct 25 02:12:22 PM PDT 23 Oct 25 02:17:06 PM PDT 23 65914678386 ps
T437 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.85725358664303044599578497449423538151346934346090196747672140941730024758914 Oct 25 02:13:01 PM PDT 23 Oct 25 02:13:14 PM PDT 23 3135422826 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.19956269954774861166636240518762424932713623036975129401308593711638962493791 Oct 25 02:12:07 PM PDT 23 Oct 25 02:12:20 PM PDT 23 3135422826 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.39925369310659943114495736719368250520097468436605277140575241753849882383567 Oct 25 02:12:17 PM PDT 23 Oct 25 02:13:39 PM PDT 23 3476453456 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.35361056133715408908034286000540888881338839351515920137057945934286586424152 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:50 PM PDT 23 3142303916 ps
T441 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.64399926650434745879135656547916457758677388137908855483505425052954899628418 Oct 25 02:12:35 PM PDT 23 Oct 25 02:13:58 PM PDT 23 3476453456 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.61588653688284051476403661722923069582477500214824105024064299111017193325113 Oct 25 02:12:20 PM PDT 23 Oct 25 02:12:38 PM PDT 23 3124113076 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.67850211424531528912655901049440574769795985189107037714495425783295138174349 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:47 PM PDT 23 3124113076 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.61097846965160551911167349871198997900658932112470018786758039779405991426822 Oct 25 02:12:13 PM PDT 23 Oct 25 02:12:26 PM PDT 23 3124113076 ps
T445 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.5565972212153058907475273591324547671952890742735709767677232686987939398194 Oct 25 02:12:59 PM PDT 23 Oct 25 02:13:14 PM PDT 23 3142303916 ps
T446 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.107436989279380555095113434056379123568101755293807590872698512987278075893825 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:30 PM PDT 23 3124113076 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.20594008272960405865419989768602956106705571835684769087481475247105390781979 Oct 25 02:12:19 PM PDT 23 Oct 25 02:12:33 PM PDT 23 3124113076 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.25403962385607914850400510595776745614553748088349214544169926856528629431576 Oct 25 02:12:08 PM PDT 23 Oct 25 02:12:20 PM PDT 23 3124113076 ps
T449 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.102496765372594456238388202864214505731960323708896510855595092932657111682246 Oct 25 02:12:41 PM PDT 23 Oct 25 02:12:53 PM PDT 23 3124113076 ps
T450 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.98414735465051135401525987331513056577728008266309341227434406869096793332488 Oct 25 02:12:55 PM PDT 23 Oct 25 02:13:09 PM PDT 23 3142303916 ps

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.99095808676317244655646507098343978543302605331965845676130372215541807705
Short name T17
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.91 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 210744 kb
Host smart-b563c0cb-8856-4e12-ac1b-eeab1567a717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99095808676317244655646507098343978543302605331965845676130372215541807705 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.99095808676317244655646507098343978543302605331965845676130372215541807705
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.76518877848667189804580336916631432215909266195868656975795298902534370644828
Short name T4
Test name
Test status
Simulation time 69854280986 ps
CPU time 355.09 seconds
Started Oct 25 01:50:17 PM PDT 23
Finished Oct 25 01:56:13 PM PDT 23
Peak memory 237816 kb
Host smart-468abf6a-07ab-4597-928e-2ff48ab562d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76518877848667189804580336916631432215909266195868656975795298902534370644828 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.7651887784866718980458033691663143221590926619586865697579
5298902534370644828
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.100807950079350204213884058498464992638216470120402060166752117104015080762288
Short name T21
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.44 seconds
Started Oct 25 02:12:57 PM PDT 23
Finished Oct 25 02:13:14 PM PDT 23
Peak memory 218964 kb
Host smart-a58d1571-5d6a-48ba-89e8-0d63f407ec49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100807950079350204213884058498464992638216470120402060166752117104015080762288 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.100807950079350204213884058498464992638216470120402060166752117104015080762288
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.7889273294157981779476956604617118558423257797222703209929909070046811234461
Short name T43
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.67 seconds
Started Oct 25 02:12:52 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 211048 kb
Host smart-14f48c31-8ffc-45be-a7f6-9dd8938bd424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7889273294157981779476956604617118558423257797222703209929909070046811234461 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.7889273294157981779476956604617118558423257797222703209929909070046811234461
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.115493131488583046942794371578001915159975816892911508439496741818968853710262
Short name T5
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.64 seconds
Started Oct 25 01:50:58 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 212964 kb
Host smart-2aaa49ce-cb3f-4b64-bb50-50d8829eea6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115493131488583046942794371578001915159975816892911508439496741
818968853710262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.1154931314885830469427943715780019151599758168929
11508439496741818968853710262
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.16900648021389943322180325859823089102672168024976440062348746758677914723562
Short name T66
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.25 seconds
Started Oct 25 02:12:07 PM PDT 23
Finished Oct 25 02:16:53 PM PDT 23
Peak memory 218980 kb
Host smart-617282d0-dcd7-49a3-ac8a-68c9aa3c1bb1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16900648021389943322180325859823089102672168024976440062348746758677914723562 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.16900648021389943322180325859823089102672168024976440062
348746758677914723562
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.101961244463266604389794875430241253999465984243919472768737857519892958202023
Short name T52
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.96 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:31 PM PDT 23
Peak memory 210880 kb
Host smart-202cd427-f466-4390-9f31-9957a3ffa559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101961244463266604389794875430241253999465984243919472768737857519892958202023
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.1019612444632666043897948754302412539994659842439194
72768737857519892958202023
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.114226614131426637174840515081056467975908266672911867688913022400834344102575
Short name T27
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.1 seconds
Started Oct 25 01:50:39 PM PDT 23
Finished Oct 25 01:52:37 PM PDT 23
Peak memory 236720 kb
Host smart-3a240751-cbcc-4338-ae02-2932b87017ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114226614131426637174840515081056467975908266672911867688913022400834344102575 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.114226614131426637174840515081056467975908266672911867688913022400834344102575
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.89315303392967609021853590459425879914500378632909148120413189355018312859472
Short name T83
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:48 PM PDT 23
Peak memory 210876 kb
Host smart-49cca9a6-c449-4afc-8a10-9628a3376b1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89315303392967609021853590459425879914500378632909148120413189355018312859472 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.89315303392967609021853590459425879914500378632909148120413189355018312859472
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.22534738428822139923601300865797151830062087805860435112714805591869677546681
Short name T395
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:28 PM PDT 23
Peak memory 210856 kb
Host smart-56dc42da-1a84-449a-93cf-c75f379a51bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534738428822139923601300865797151830062087805860435112714805591869677546681 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.22534738428822139923601300865797151830062087805860435112714805591869677546681
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.25595761235565518280388254415667485469499862242397383645946788788925016971880
Short name T7
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:50:58 PM PDT 23
Peak memory 211052 kb
Host smart-30833d2c-c6b1-4aae-ae40-de2308247c9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25595761235565518280388254415667485469499862242397383645946788788925016971880 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.25595761235565518280388254415667485469499862242397383645946788788925016971880
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.100325597850163488751637402306449140697230129025169511331583326888206280435656
Short name T97
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.46 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:08 PM PDT 23
Peak memory 211628 kb
Host smart-0b1899f8-2df0-4ff6-ac04-44037f7235c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100325597850163488751637402306449140697230129025169511331583326888206280435656 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.rom_ctrl_kmac_err_chk.100325597850163488751637402306449140697230129025169511331583326888206280435656
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.15358930453656360999138323757553837035433170221778303422280403122193700059502
Short name T368
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.32 seconds
Started Oct 25 02:12:05 PM PDT 23
Finished Oct 25 02:12:18 PM PDT 23
Peak memory 213468 kb
Host smart-2985b3f9-dfb3-47e0-aab2-08d2f61ef56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535893045365636099913832375755383703543317
0221778303422280403122193700059502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.153589304536
56360999138323757553837035433170221778303422280403122193700059502
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.97144021162680918047688567049350293810057755390211655415346774690259920895935
Short name T142
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:50:53 PM PDT 23
Peak memory 211160 kb
Host smart-1c78b19b-8592-4608-8bda-19449c3e91e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97144021162680918047688567049350293810057755390211655415346774690259920895935 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.97144021162680918047688567049350293810057755390211655415346774690259920895935
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.89744818484118123400586314644075552101253331904530585517542892085923134475182
Short name T11
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.56 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 212740 kb
Host smart-f836e18a-3227-467d-af37-28964cb7a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89744818484118123400586314644075552101253331904530585517542892085923134475182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.89744818484118123400586314644075552101253331904530585517542892085923134475182
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.107392733457819169727633378261348106316691857039284132492609494427491979323909
Short name T84
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:29 PM PDT 23
Peak memory 210868 kb
Host smart-e1183080-a3aa-41cd-a2f1-019705d8d2ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107392733457819169727633378261348106316691857039284132492609494427491979323909 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.107392733457819169727633378261348106316691857039284132492609494427491979323909
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.90260317623038376085679643438868403561766134786869224279943181429481108292556
Short name T92
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.91 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:32 PM PDT 23
Peak memory 210936 kb
Host smart-2d136361-3f80-478b-ae93-467ed224ea14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90260317623038376085679643438868403561766134786869224279943181429481108292556 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.90260317623038376085679643438868403561766134786869224279943181429481108292556
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.76561594949925012420148898308095105700338374573683493300072047250327169056280
Short name T415
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.73 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:11:30 PM PDT 23
Peak memory 213308 kb
Host smart-c8feb4c1-8cce-42dc-bb28-a1e93b7ca79e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7656159494992501242014889830809510570033837
4573683493300072047250327169056280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.7656159494992
5012420148898308095105700338374573683493300072047250327169056280
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.41427318732895465665568891423265359907808246030525003603532949774217985256657
Short name T427
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:25 PM PDT 23
Peak memory 210864 kb
Host smart-7669983f-4180-4cf6-aa96-fc516b28daa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427318732895465665568891423265359907808246030525003603532949774217985256657 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.41427318732895465665568891423265359907808246030525003603532949774217985256657
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.76016836124505887689709003510319862801986155915068512352219608563032578990585
Short name T423
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:29 PM PDT 23
Peak memory 210912 kb
Host smart-30d2790b-5316-44f7-a196-35ae5a9608f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76016836124505887689709003510319862801986155915068512352219608563032578990585 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.7601683612450588768970900351031986280198615591506851235221
9608563032578990585
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.65046738601559845187074837792852564683875115244474119832997691063705137098173
Short name T86
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 25 02:11:57 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 210868 kb
Host smart-7089371c-314a-4d19-af0d-0d0235b043e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65046738601559845187074837792852564683875115244474119832997691063705137098173 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.65046738601559845187074837792852564683875115244474119832997691063705137098173
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.109715670056169635005149739011800518768450116202768320728578202252557145660191
Short name T25
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.61 seconds
Started Oct 25 02:12:06 PM PDT 23
Finished Oct 25 02:16:53 PM PDT 23
Peak memory 218944 kb
Host smart-6348c7f6-d7ce-4d9b-a18e-f290b0d75e1f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109715670056169635005149739011800518768450116202768320728578202252557145660191 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.1097156700561696350051497390118005187684501162027683207
28578202252557145660191
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.28753750002362687992358831833390709413452920877903396295864384711827669164823
Short name T385
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.99 seconds
Started Oct 25 02:11:20 PM PDT 23
Finished Oct 25 02:11:34 PM PDT 23
Peak memory 210752 kb
Host smart-9bf72cf1-18e2-439e-ba46-97bd1ebcca60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28753750002362687992358831833390709413452920877903396295864384711827669164823
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.287537500023626879923588318333907094134529208779033962
95864384711827669164823
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.113888880325344483921938746080600537612987240945390977439440180213500652565222
Short name T413
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Oct 25 02:11:41 PM PDT 23
Finished Oct 25 02:11:58 PM PDT 23
Peak memory 218948 kb
Host smart-ec3e2ec2-aef4-450f-90f9-60a8b44f6e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113888880325344483921938746080600537612987240945390977439440180213500652565222 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.113888880325344483921938746080600537612987240945390977439440180213500652565222
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.39925369310659943114495736719368250520097468436605277140575241753849882383567
Short name T439
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.13 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:13:39 PM PDT 23
Peak memory 210948 kb
Host smart-548d2959-6aea-4ed7-ad9a-c07485a0e9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39925369310659943114495736719368250520097468436605277140575241753849882383567 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.39925369310659943114495736719368250520097468436605277140575241753849882383567
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.88862797762955300338220754630783412704133332287991054667900436939785992391594
Short name T420
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:48 PM PDT 23
Peak memory 210824 kb
Host smart-b99ad426-ca27-4f2d-9a79-959d7e2bcfb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88862797762955300338220754630783412704133332287991054667900436939785992391594 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.88862797762955300338220754630783412704133332287991054667900436939785992391594
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.21263574323856321005281673385861712107942227413993551213094299010294970495674
Short name T64
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.35 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:33 PM PDT 23
Peak memory 210884 kb
Host smart-344c38ef-12d5-4aff-9e81-bf21e25a41c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21263574323856321005281673385861712107942227413993551213094299010294970495674 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.21263574323856321005281673385861712107942227413993551213094299010294970495674
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.37253571761062241050679161037117805147815238434163526105220059256240722779905
Short name T381
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.71 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:48 PM PDT 23
Peak memory 213540 kb
Host smart-1b3a3746-a304-4837-a627-d9f832c5b758
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725357176106224105067916103711780514781523
8434163526105220059256240722779905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3725357176106
2241050679161037117805147815238434163526105220059256240722779905
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.67850211424531528912655901049440574769795985189107037714495425783295138174349
Short name T443
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:47 PM PDT 23
Peak memory 210820 kb
Host smart-f8a7d6d7-28ea-4cac-8611-3096957bf99e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67850211424531528912655901049440574769795985189107037714495425783295138174349 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.67850211424531528912655901049440574769795985189107037714495425783295138174349
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.110830407100179515544561573703703493446914652649033483672223011227373042276031
Short name T382
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.01 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:27 PM PDT 23
Peak memory 210764 kb
Host smart-41911b52-daae-4152-8ae3-f7c8f3860d47
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110830407100179515544561573703703493446914652649033483672223011227373042276031 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.110830407100179515544561573703703493446914652649033483672
223011227373042276031
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.27813862541388316199988718028586642612925540367406971823162711448808107543145
Short name T57
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:11:30 PM PDT 23
Peak memory 210692 kb
Host smart-30d735a9-cb24-4bb0-abc1-ea7d34704af4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27813862541388316199988718028586642612925540367406971823162711448808107543145 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.27813862541388316199988718028586642612925540367406971823162711448808107543145
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.58006132121654729147749527869680410710362641533350791326978129757811770765972
Short name T69
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.62 seconds
Started Oct 25 02:11:20 PM PDT 23
Finished Oct 25 02:16:06 PM PDT 23
Peak memory 218908 kb
Host smart-ae3e9dc2-f43e-4ebb-8935-12355a6dc828
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58006132121654729147749527869680410710362641533350791326978129757811770765972 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.58006132121654729147749527869680410710362641533350791326
978129757811770765972
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.35361056133715408908034286000540888881338839351515920137057945934286586424152
Short name T440
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.26 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:50 PM PDT 23
Peak memory 210920 kb
Host smart-23d1661a-ded7-49b2-a1c9-d7f702559458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35361056133715408908034286000540888881338839351515920137057945934286586424152
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.353610561337154089080342860005408888813388393515159201
37057945934286586424152
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.18105034296742016729385549240069736572828411552061006341332511018096699819100
Short name T60
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.14 seconds
Started Oct 25 02:11:20 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 219000 kb
Host smart-ca1d8317-2a78-4bbe-9430-45f2c45fce58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105034296742016729385549240069736572828411552061006341332511018096699819100 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.18105034296742016729385549240069736572828411552061006341332511018096699819100
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.81645420369537888724847646190869569711742089331113605714969584142726680833026
Short name T372
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.06 seconds
Started Oct 25 02:11:20 PM PDT 23
Finished Oct 25 02:12:42 PM PDT 23
Peak memory 210996 kb
Host smart-72f9f7b4-2cba-4dfd-9057-23324861cf5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81645420369537888724847646190869569711742089331113605714969584142726680833026 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.81645420369537888724847646190869569711742089331113605714969584142726680833026
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.40211981134278325007723582850677081500599719025015094311731891333153858717822
Short name T410
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.55 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 213488 kb
Host smart-f5b91fc1-2711-441f-8731-56ca47824e9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021198113427832500772358285067708150059971
9025015094311731891333153858717822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.402119811342
78325007723582850677081500599719025015094311731891333153858717822
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.20003575626553813547446548070875406074393308532767824406685990001510314854809
Short name T391
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:27 PM PDT 23
Peak memory 210864 kb
Host smart-64f962ba-2134-4242-a0c5-53e1482874fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20003575626553813547446548070875406074393308532767824406685990001510314854809 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.20003575626553813547446548070875406074393308532767824406685990001510314854809
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.41136752772080482936774067991046772627887316856004225385407742783237550996953
Short name T436
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.18 seconds
Started Oct 25 02:12:22 PM PDT 23
Finished Oct 25 02:17:06 PM PDT 23
Peak memory 218980 kb
Host smart-be86c305-1e7c-4297-af71-36eb63620d01
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136752772080482936774067991046772627887316856004225385407742783237550996953 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.4113675277208048293677406799104677262788731685600422538
5407742783237550996953
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.28176529496586730149097636313239654967375278294112385050613050096154286033307
Short name T90
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.28 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:13:09 PM PDT 23
Peak memory 210864 kb
Host smart-a0f5e8f4-d6d8-4075-869d-0c38a7a89032
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28176529496586730149097636313239654967375278294112385050613050096154286033307
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.28176529496586730149097636313239654967375278294112385
050613050096154286033307
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.55175152357235713300262253742664126526260125078797179808634502744779367654004
Short name T389
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.44 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:14:22 PM PDT 23
Peak memory 211052 kb
Host smart-7a6cb12e-ff66-4b9a-932b-09fe5aff0087
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55175152357235713300262253742664126526260125078797179808634502744779367654004 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.55175152357235713300262253742664126526260125078797179808634502744779367654004
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.49766331235547991498268135863030559015786848947539294191036559164920165835929
Short name T95
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 210776 kb
Host smart-cea9369c-7d12-4742-a72b-c2f6d4375964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49766331235547991498268135863030559015786848947539294191036559164920165835929 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.49766331235547991498268135863030559015786848947539294191036559164920165835929
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.37271611401441762487611268812322399405015408199954792676679293829958299496014
Short name T392
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.73 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:17:01 PM PDT 23
Peak memory 218960 kb
Host smart-61e01034-cb70-4f27-9bf0-30eaf536b059
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37271611401441762487611268812322399405015408199954792676679293829958299496014 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.3727161140144176248761126881232239940501540819995479267
6679293829958299496014
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.5438944785255640721842670353561927383463769839102625676213065092981373344518
Short name T431
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.42 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 218940 kb
Host smart-b15477d2-cd13-4364-92e6-8ec83e742280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5438944785255640721842670353561927383463769839102625676213065092981373344518 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.5438944785255640721842670353561927383463769839102625676213065092981373344518
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.20833436596369555271158670600607835731183229926403608923985433788580449890005
Short name T396
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.93 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:13:41 PM PDT 23
Peak memory 211100 kb
Host smart-d18864bc-2a93-4d76-bef0-f5c80f2ce11c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20833436596369555271158670600607835731183229926403608923985433788580449890005 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.20833436596369555271158670600607835731183229926403608923985433788580449890005
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.30208299471596960691613813713321984729673031435328090311651892706868939493237
Short name T47
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.49 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:31 PM PDT 23
Peak memory 213468 kb
Host smart-aab43491-3f40-41ba-be54-92fa7fa9f53b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020829947159696069161381371332198472967303
1435328090311651892706868939493237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.302082994715
96960691613813713321984729673031435328090311651892706868939493237
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.39846496323832446155392448457685843725945259290513965478093874272914481855071
Short name T65
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.13 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 210776 kb
Host smart-4b2ea3e9-f8a4-4885-be30-e1e0fe05d2e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846496323832446155392448457685843725945259290513965478093874272914481855071 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.39846496323832446155392448457685843725945259290513965478093874272914481855071
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.55633759754117501074467919207690276408378281772467211328683898012744329236159
Short name T394
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.07 seconds
Started Oct 25 02:12:15 PM PDT 23
Finished Oct 25 02:17:03 PM PDT 23
Peak memory 219008 kb
Host smart-a684a228-3648-4c81-b254-1e580328d00c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55633759754117501074467919207690276408378281772467211328683898012744329236159 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.5563375975411750107446791920769027640837828177246721132
8683898012744329236159
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.85419773180907262175713926023667160302406463010627478049699948421003738192718
Short name T75
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.39 seconds
Started Oct 25 02:12:35 PM PDT 23
Finished Oct 25 02:12:50 PM PDT 23
Peak memory 210848 kb
Host smart-468ed152-7f40-46ea-bf6d-d88059d1e093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85419773180907262175713926023667160302406463010627478049699948421003738192718
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.85419773180907262175713926023667160302406463010627478
049699948421003738192718
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.94449058106650297303242996659499901304758198027019993556205194298324329995182
Short name T20
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 219096 kb
Host smart-43da39ee-f773-428a-a8d9-40212412a1dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94449058106650297303242996659499901304758198027019993556205194298324329995182 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.94449058106650297303242996659499901304758198027019993556205194298324329995182
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.64399926650434745879135656547916457758677388137908855483505425052954899628418
Short name T441
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.59 seconds
Started Oct 25 02:12:35 PM PDT 23
Finished Oct 25 02:13:58 PM PDT 23
Peak memory 210928 kb
Host smart-c7bb3476-6c69-4177-bb46-3046b0cb6357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64399926650434745879135656547916457758677388137908855483505425052954899628418 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.64399926650434745879135656547916457758677388137908855483505425052954899628418
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.96156255512441943983891423614076809487808311887961470065505325527529466765713
Short name T417
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.34 seconds
Started Oct 25 02:12:25 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 213428 kb
Host smart-66d4d9a7-17ff-4075-9266-4ae4ed5b9df1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9615625551244194398389142361407680948780831
1887961470065505325527529466765713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.961562555124
41943983891423614076809487808311887961470065505325527529466765713
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.22245287265653880453550686666855053069866607847440767204775133403440402780822
Short name T384
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 210856 kb
Host smart-6acd949a-6698-4095-9f8e-2764dc191b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245287265653880453550686666855053069866607847440767204775133403440402780822 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.22245287265653880453550686666855053069866607847440767204775133403440402780822
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.71129858699759589158028451038700050884097563999232779322186952298185808332873
Short name T67
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.17 seconds
Started Oct 25 02:12:22 PM PDT 23
Finished Oct 25 02:17:05 PM PDT 23
Peak memory 218972 kb
Host smart-eb4c4136-8239-41b8-ab20-efe352641d2e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71129858699759589158028451038700050884097563999232779322186952298185808332873 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.7112985869975958915802845103870005088409756399923277932
2186952298185808332873
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.66275854297431192584939399362787938459143734168635577513138705693396241778413
Short name T428
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.94 seconds
Started Oct 25 02:12:23 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 210812 kb
Host smart-aa7a1d6f-5851-46fc-b355-a1a7f2449fe0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66275854297431192584939399362787938459143734168635577513138705693396241778413
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.66275854297431192584939399362787938459143734168635577
513138705693396241778413
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.74560554740654596318677826019124104052660179868073744837216286757239570374002
Short name T422
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.72 seconds
Started Oct 25 02:12:37 PM PDT 23
Finished Oct 25 02:12:54 PM PDT 23
Peak memory 219088 kb
Host smart-9856b6ec-bc86-46df-b10e-2ad8ae71ae5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74560554740654596318677826019124104052660179868073744837216286757239570374002 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.74560554740654596318677826019124104052660179868073744837216286757239570374002
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.16997351103174594261889458474013213943356335681407236596077973761038790242355
Short name T419
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.87 seconds
Started Oct 25 02:12:22 PM PDT 23
Finished Oct 25 02:13:42 PM PDT 23
Peak memory 211080 kb
Host smart-68219b80-69dd-470a-a253-f5bf0f72d706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16997351103174594261889458474013213943356335681407236596077973761038790242355 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.16997351103174594261889458474013213943356335681407236596077973761038790242355
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.48956566314924446608247465279068619467789936974356897458147860137466150028581
Short name T49
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.5 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:12:54 PM PDT 23
Peak memory 213472 kb
Host smart-3474c1c2-60b4-4a14-9031-e5170e90463e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4895656631492444660824746527906861946778993
6974356897458147860137466150028581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.489565663149
24446608247465279068619467789936974356897458147860137466150028581
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.60300004330060427882708867503314078538188506262787416460038640259402788096270
Short name T19
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 25 02:12:38 PM PDT 23
Finished Oct 25 02:12:52 PM PDT 23
Peak memory 210852 kb
Host smart-4a74e397-6d93-4ea5-8587-2d405b3cf7bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60300004330060427882708867503314078538188506262787416460038640259402788096270 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.60300004330060427882708867503314078538188506262787416460038640259402788096270
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.90504250243512685964687534337617584444566090427617175889501224453418948429633
Short name T406
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.39 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:17:05 PM PDT 23
Peak memory 219008 kb
Host smart-d47e580d-e797-4387-96d2-3d88716052e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90504250243512685964687534337617584444566090427617175889501224453418948429633 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.9050425024351268596468753433761758444456609042761717588
9501224453418948429633
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.51072711964185906007772717437316120402272962168909280823107914832145467457460
Short name T71
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.49 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:12:55 PM PDT 23
Peak memory 210856 kb
Host smart-09fc36a3-8064-4d7f-9c88-de3b4fa37674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51072711964185906007772717437316120402272962168909280823107914832145467457460
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.51072711964185906007772717437316120402272962168909280
823107914832145467457460
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.76017325712157561370627740035135295275174199231542955278385019874759338793341
Short name T425
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.42 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:35 PM PDT 23
Peak memory 219092 kb
Host smart-00786040-15cd-4b1e-83ab-a664f49861f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76017325712157561370627740035135295275174199231542955278385019874759338793341 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.76017325712157561370627740035135295275174199231542955278385019874759338793341
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.64824830970221786681254836238824663432088205984557359720035942815360701393594
Short name T383
Test name
Test status
Simulation time 3476453456 ps
CPU time 83.01 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:14:05 PM PDT 23
Peak memory 211112 kb
Host smart-14318991-f65d-4f42-8fd7-e8edabba431c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64824830970221786681254836238824663432088205984557359720035942815360701393594 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.64824830970221786681254836238824663432088205984557359720035942815360701393594
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.8366128816141669883431541666896541199724430302282767850183497889394674342338
Short name T366
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.53 seconds
Started Oct 25 02:12:33 PM PDT 23
Finished Oct 25 02:12:46 PM PDT 23
Peak memory 213472 kb
Host smart-698182cb-66c9-4fb2-a39f-70aee0a16396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8366128816141669883431541666896541199724430
302282767850183497889394674342338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.8366128816141
669883431541666896541199724430302282767850183497889394674342338
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.14912279575112737665023801560590107711694184992292141138057881295715183481384
Short name T379
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.32 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:31 PM PDT 23
Peak memory 210940 kb
Host smart-ed495c8c-f940-474e-ace3-02035182777f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14912279575112737665023801560590107711694184992292141138057881295715183481384 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.14912279575112737665023801560590107711694184992292141138057881295715183481384
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.20505477492240797952809782939642610020476120602235753899955307868034937189432
Short name T54
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.87 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:17:01 PM PDT 23
Peak memory 218964 kb
Host smart-5495d4d5-942a-4d51-b185-d358ca28d91d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20505477492240797952809782939642610020476120602235753899955307868034937189432 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.2050547749224079795280978293964261002047612060223575389
9955307868034937189432
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.74449314783511187972027826842743828751520241920587429759479504005497277289956
Short name T402
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.75 seconds
Started Oct 25 02:12:33 PM PDT 23
Finished Oct 25 02:12:47 PM PDT 23
Peak memory 210764 kb
Host smart-598a5b20-d8c8-4555-a32a-585729d836b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74449314783511187972027826842743828751520241920587429759479504005497277289956
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.74449314783511187972027826842743828751520241920587429
759479504005497277289956
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.28605833359293721118899368574862784556956232087303386433805442989801411919614
Short name T61
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.31 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 218968 kb
Host smart-1fe67f2b-4722-4444-920f-ff6a37b638cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605833359293721118899368574862784556956232087303386433805442989801411919614 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.28605833359293721118899368574862784556956232087303386433805442989801411919614
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.66791788968533834412146023390632750262889529338411851231138256834243261508374
Short name T365
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.51 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:13:41 PM PDT 23
Peak memory 211048 kb
Host smart-a89b829d-1d67-428d-826f-1cb847b65e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66791788968533834412146023390632750262889529338411851231138256834243261508374 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.66791788968533834412146023390632750262889529338411851231138256834243261508374
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.85725358664303044599578497449423538151346934346090196747672140941730024758914
Short name T437
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.41 seconds
Started Oct 25 02:13:01 PM PDT 23
Finished Oct 25 02:13:14 PM PDT 23
Peak memory 213436 kb
Host smart-ed26dec6-3f41-4f87-952f-ba284487969d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8572535866430304459957849744942353815134693
4346090196747672140941730024758914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.857253586643
03044599578497449423538151346934346090196747672140941730024758914
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.77544954322527650631208271107472612601400551652168163890155216511017416729367
Short name T412
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 210792 kb
Host smart-14918839-49e3-4ca8-83f4-f5704494464f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77544954322527650631208271107472612601400551652168163890155216511017416729367 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.77544954322527650631208271107472612601400551652168163890155216511017416729367
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.10704725405965438980276148069689161232443801453897999282534990780608099261679
Short name T32
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.3 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:17:26 PM PDT 23
Peak memory 219008 kb
Host smart-2679af1a-21ae-46bb-aad9-d3c7c5bc783c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10704725405965438980276148069689161232443801453897999282534990780608099261679 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.1070472540596543898027614806968916123244380145389799928
2534990780608099261679
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.98414735465051135401525987331513056577728008266309341227434406869096793332488
Short name T450
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.19 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:13:09 PM PDT 23
Peak memory 210752 kb
Host smart-7ecb10e4-b6ed-4819-bf28-d74106f84f12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98414735465051135401525987331513056577728008266309341227434406869096793332488
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.98414735465051135401525987331513056577728008266309341
227434406869096793332488
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.84772407952897796607192503916765939781007046713502522462655829101070005713706
Short name T414
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.92 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 219080 kb
Host smart-209d5cc2-3d55-4b8f-98a2-b1c813ffdda9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84772407952897796607192503916765939781007046713502522462655829101070005713706 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.84772407952897796607192503916765939781007046713502522462655829101070005713706
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.14343080715500295261006622722902512697521098715164968334971013888075186143445
Short name T370
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.53 seconds
Started Oct 25 02:13:04 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 212812 kb
Host smart-d6d45d7d-c393-4c8d-94f1-afd042bc183c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434308071550029526100662272290251269752109
8715164968334971013888075186143445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.143430807155
00295261006622722902512697521098715164968334971013888075186143445
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.30429096732386064851116300970336548265052581325666965626189582513455356084010
Short name T377
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:13:08 PM PDT 23
Peak memory 210904 kb
Host smart-6b76f580-32e7-49af-831f-f8722d8c5f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30429096732386064851116300970336548265052581325666965626189582513455356084010 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.30429096732386064851116300970336548265052581325666965626189582513455356084010
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.98654915784177088723491480254901866808854051768604220178090493714125386117464
Short name T421
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.33 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:17:41 PM PDT 23
Peak memory 219024 kb
Host smart-f34e1e31-c789-4d8a-8b99-70350db7dae8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98654915784177088723491480254901866808854051768604220178090493714125386117464 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.9865491578417708872349148025490186680885405176860422017
8090493714125386117464
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.5565972212153058907475273591324547671952890742735709767677232686987939398194
Short name T445
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.27 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:14 PM PDT 23
Peak memory 210832 kb
Host smart-0d7d27f0-494b-4a08-a22e-15c816ec567e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5565972212153058907475273591324547671952890742735709767677232686987939398194 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.556597221215305890747527359132454767195289074273570976
7677232686987939398194
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.99390690768002136841129330326331313204114210194559789932453475720560225585518
Short name T44
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.11 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:13:12 PM PDT 23
Peak memory 219080 kb
Host smart-90d16ed0-3c11-4499-88a9-f1318900d37c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99390690768002136841129330326331313204114210194559789932453475720560225585518 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.99390690768002136841129330326331313204114210194559789932453475720560225585518
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2009208418079832635269665101892337713711699002134834538373949351017448268105
Short name T404
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.21 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 211008 kb
Host smart-25ee9d68-68e1-4224-b191-f7dd6e51ea78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009208418079832635269665101892337713711699002134834538373949351017448268105 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.2009208418079832635269665101892337713711699002134834538373949351017448268105
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.29673162037000871001408806215093431165777278082761525659859502786988548403552
Short name T96
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.57 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 213480 kb
Host smart-ce210c2a-5538-46ec-9ba0-371370ee93ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967316203700087100140880621509343116577727
8082761525659859502786988548403552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.296731620370
00871001408806215093431165777278082761525659859502786988548403552
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.57880027342747248833694496449373240427999195371353065448667091667467468219734
Short name T374
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 25 02:12:58 PM PDT 23
Finished Oct 25 02:13:11 PM PDT 23
Peak memory 210824 kb
Host smart-4dd383a7-5e49-42de-816a-e2c769005fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57880027342747248833694496449373240427999195371353065448667091667467468219734 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.57880027342747248833694496449373240427999195371353065448667091667467468219734
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.34188939834075798069232783478301550446742833450575475129171969084805096898208
Short name T397
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.02 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:17:41 PM PDT 23
Peak memory 218956 kb
Host smart-0247f3ef-29ba-485f-b8bc-184b8d6abb6e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188939834075798069232783478301550446742833450575475129171969084805096898208 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.3418893983407579806923278347830155044674283345057547512
9171969084805096898208
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.8602721858713289566392926196519477515065763211827920364954835763520185739842
Short name T62
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.28 seconds
Started Oct 25 02:12:57 PM PDT 23
Finished Oct 25 02:13:12 PM PDT 23
Peak memory 210756 kb
Host smart-e5e34dbc-5b5a-4adc-8a94-2f5849b197b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8602721858713289566392926196519477515065763211827920364954835763520185739842 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.860272185871328956639292619651947751506576321182792036
4954835763520185739842
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.69454382618736108393392573079559414851309602932001690253367133482408582202579
Short name T426
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.1 seconds
Started Oct 25 02:13:01 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 218944 kb
Host smart-18589f96-6a49-4f2a-8c19-dbfc4baf1eca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69454382618736108393392573079559414851309602932001690253367133482408582202579 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.69454382618736108393392573079559414851309602932001690253367133482408582202579
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.53446207252400643822431187024658041530448846970324796924963191274287435286311
Short name T371
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.23 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 211068 kb
Host smart-5ae3b05c-41ce-41bd-8f2e-235be445476e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53446207252400643822431187024658041530448846970324796924963191274287435286311 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.53446207252400643822431187024658041530448846970324796924963191274287435286311
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.115207884043351946855530081159768968266460492549107661961545794688167851065465
Short name T89
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.4 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 213376 kb
Host smart-4d4605f2-bb0f-41bc-aa81-e387ec7f350a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152078840433519468555300811597689682664604
92549107661961545794688167851065465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.11520788404
3351946855530081159768968266460492549107661961545794688167851065465
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.6647904190257086932532471983325909939584637239022533714815204545156811244774
Short name T68
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.86 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:17:01 PM PDT 23
Peak memory 218992 kb
Host smart-d59d2021-bce1-4aae-86d4-95faa6fddede
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6647904190257086932532471983325909939584637239022533714815204545156811244774 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.66479041902570869325324719833259099395846372390225337148
15204545156811244774
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.65781169510655440932565448480700887570839991502488043964551689941655461500904
Short name T405
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.97 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 210848 kb
Host smart-afdb89c9-f85a-4638-9f4b-3b1fc043f747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65781169510655440932565448480700887570839991502488043964551689941655461500904
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.65781169510655440932565448480700887570839991502488043
964551689941655461500904
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.102115415037161622521041325334559634154980869204767968949356863715677861406477
Short name T48
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.69 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 219108 kb
Host smart-68ed6f56-7b75-4cc2-b451-3a25362d50a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102115415037161622521041325334559634154980869204767968949356863715677861406477 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.102115415037161622521041325334559634154980869204767968949356863715677861406477
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.81100271731038332658106121045706571911082045664635684612277253613571976697017
Short name T409
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.45 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:13:37 PM PDT 23
Peak memory 211052 kb
Host smart-60437533-d56a-4161-a604-b99ad59e0255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81100271731038332658106121045706571911082045664635684612277253613571976697017 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.81100271731038332658106121045706571911082045664635684612277253613571976697017
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.63342510194837993642164406469792518608250970569577585105739682342729646954933
Short name T63
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.32 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:43 PM PDT 23
Peak memory 210860 kb
Host smart-53abaf7e-1c30-4fc7-9322-9e657a4b2549
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63342510194837993642164406469792518608250970569577585105739682342729646954933 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.63342510194837993642164406469792518608250970569577585105739682342729646954933
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.111022066376814665175527260872285973321202594373131481306036298225377481001004
Short name T53
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:47 PM PDT 23
Peak memory 210860 kb
Host smart-2de0bd59-0de5-4f58-bd3d-78ae46fb9314
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111022066376814665175527260872285973321202594373131481306036298225377481001004 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.111022066376814665175527260872285973321202594373131481306036298225377481001004
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.41635098011633129243651790769163260515815277466364738700502806432893122027470
Short name T432
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.59 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:46 PM PDT 23
Peak memory 210704 kb
Host smart-370f01ae-98e9-4127-990a-b413e59e5898
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41635098011633129243651790769163260515815277466364738700502806432893122027470 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.41635098011633129243651790769163260515815277466364738700502806432893122027470
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.46352965709477229457603967056075592626125941989949014003654477203898517799934
Short name T403
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.23 seconds
Started Oct 25 02:11:40 PM PDT 23
Finished Oct 25 02:11:53 PM PDT 23
Peak memory 213344 kb
Host smart-57fbb030-77c8-4a28-973c-6d812141d061
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4635296570947722945760396705607559262612594
1989949014003654477203898517799934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4635296570947
7229457603967056075592626125941989949014003654477203898517799934
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.16214402616323081284671341901615812731174676999946738366005810295699626813056
Short name T435
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.86 seconds
Started Oct 25 02:11:27 PM PDT 23
Finished Oct 25 02:11:39 PM PDT 23
Peak memory 210852 kb
Host smart-6bf6eb14-572d-4589-9a6f-98fcb50c0a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214402616323081284671341901615812731174676999946738366005810295699626813056 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.16214402616323081284671341901615812731174676999946738366005810295699626813056
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.113625699654488959036471369585117403900381322876238106507001961469792805160508
Short name T375
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:47 PM PDT 23
Peak memory 210888 kb
Host smart-87a3be85-4f3c-4c3a-bbaf-4ddef4772a39
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113625699654488959036471369585117403900381322876238106507001961469792805160508 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.113625699654488959036471369585117403900381322876238106507
001961469792805160508
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.36195853133396648584044853204873719666459541862530350601823518034998858105691
Short name T378
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:46 PM PDT 23
Peak memory 210836 kb
Host smart-dbd51cf5-75e6-4002-b7d5-bfe2bd143f8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36195853133396648584044853204873719666459541862530350601823518034998858105691 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.36195853133396648584044853204873719666459541862530350601823518034998858105691
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.68208197830336935470983752668350384393092537480242238337023153582651193016283
Short name T56
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.26 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:16:02 PM PDT 23
Peak memory 219016 kb
Host smart-3c3ab681-7b4b-4a02-b8db-8b9bacbcf464
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68208197830336935470983752668350384393092537480242238337023153582651193016283 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.68208197830336935470983752668350384393092537480242238337
023153582651193016283
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.94163882731208137987175024663621766572986698822384460197848590807496668075660
Short name T416
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.22 seconds
Started Oct 25 02:12:04 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 210724 kb
Host smart-39537d6b-fbf7-4b48-9dd6-848bda601618
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94163882731208137987175024663621766572986698822384460197848590807496668075660
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.941638827312081379871750246636217665729866988223844601
97848590807496668075660
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.110020352795886482618216303525557790593358203919413968312493957387187838149308
Short name T59
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.54 seconds
Started Oct 25 02:11:38 PM PDT 23
Finished Oct 25 02:11:55 PM PDT 23
Peak memory 218928 kb
Host smart-e9ae91a6-d753-4408-88ce-0b87e9e84f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110020352795886482618216303525557790593358203919413968312493957387187838149308 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.110020352795886482618216303525557790593358203919413968312493957387187838149308
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.51188876014612797557746456548165983164138222747855278810969242946555269437858
Short name T380
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.45 seconds
Started Oct 25 02:11:29 PM PDT 23
Finished Oct 25 02:12:50 PM PDT 23
Peak memory 211068 kb
Host smart-82f3f99c-a482-4787-9c24-c3babb0ac863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51188876014612797557746456548165983164138222747855278810969242946555269437858 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.51188876014612797557746456548165983164138222747855278810969242946555269437858
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.82515053221630782601988668519226365794155692511317861805007063556291958965048
Short name T82
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 210852 kb
Host smart-ce8b73a3-5c8c-4422-9479-e44f0062b927
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82515053221630782601988668519226365794155692511317861805007063556291958965048 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.82515053221630782601988668519226365794155692511317861805007063556291958965048
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.12043948793129122675024805069575774060118503478854768530186290296382877563398
Short name T386
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.69 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 210848 kb
Host smart-4b1214b2-0117-4d6f-84cc-f1d17c431849
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12043948793129122675024805069575774060118503478854768530186290296382877563398 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.12043948793129122675024805069575774060118503478854768530186290296382877563398
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.25330725618398707510413595741204959573486852105932842358876039257553099818017
Short name T401
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.85 seconds
Started Oct 25 02:11:57 PM PDT 23
Finished Oct 25 02:12:13 PM PDT 23
Peak memory 210892 kb
Host smart-32e0f63c-d881-4a6c-a603-c361a86a06ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330725618398707510413595741204959573486852105932842358876039257553099818017 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.25330725618398707510413595741204959573486852105932842358876039257553099818017
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.19956269954774861166636240518762424932713623036975129401308593711638962493791
Short name T438
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.58 seconds
Started Oct 25 02:12:07 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 213440 kb
Host smart-d1ee5e87-8736-4adf-9a86-71c349547012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995626995477486116663624051876242493271362
3036975129401308593711638962493791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1995626995477
4861166636240518762424932713623036975129401308593711638962493791
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.111973918365497370210416064474914631762890357704472371317975174732688725008926
Short name T26
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 25 02:11:56 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 210808 kb
Host smart-daab012d-cb02-422b-ac2a-04447ec69bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111973918365497370210416064474914631762890357704472371317975174732688725008926 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.111973918365497370210416064474914631762890357704472371317975174732688725008926
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.18784890014394152600311093216498764597493088832201627939056348917293077728121
Short name T93
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.85 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:48 PM PDT 23
Peak memory 210868 kb
Host smart-8339ebb5-3a29-4ee1-9d8b-08a4dc5222ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784890014394152600311093216498764597493088832201627939056348917293077728121 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.1878489001439415260031109321649876459749308883220162793905
6348917293077728121
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.47978501686155455232213209936689961812970700254077518626980156217482270649384
Short name T399
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 25 02:11:32 PM PDT 23
Finished Oct 25 02:11:45 PM PDT 23
Peak memory 210852 kb
Host smart-1553d181-cc5c-44e1-b4ca-3bebb1bf710f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47978501686155455232213209936689961812970700254077518626980156217482270649384 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.47978501686155455232213209936689961812970700254077518626980156217482270649384
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.53542668875053034217679079760568122427127559651543134808818082611523693157376
Short name T408
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.23 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:16:22 PM PDT 23
Peak memory 218996 kb
Host smart-9f499f62-49d3-4486-98d7-a8049ae26476
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53542668875053034217679079760568122427127559651543134808818082611523693157376 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.53542668875053034217679079760568122427127559651543134808
818082611523693157376
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.60766181193410415438379065732235267835951045839118402690890023422296044961542
Short name T87
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.13 seconds
Started Oct 25 02:12:06 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 210772 kb
Host smart-7558dfd1-b4e1-4041-ad6b-4eaa0652c5a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60766181193410415438379065732235267835951045839118402690890023422296044961542
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.607661811934104154383790657322352678359510458391184026
90890023422296044961542
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.95856068017394534228581622124856461164100122188970886891219372422672125370907
Short name T45
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.65 seconds
Started Oct 25 02:11:38 PM PDT 23
Finished Oct 25 02:11:55 PM PDT 23
Peak memory 219068 kb
Host smart-75130dbc-edc8-47f6-a434-418945ac9964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95856068017394534228581622124856461164100122188970886891219372422672125370907 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.95856068017394534228581622124856461164100122188970886891219372422672125370907
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.19107055363816890030719961027822077948214018853182644376334076217438059269294
Short name T88
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.41 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:12:59 PM PDT 23
Peak memory 211088 kb
Host smart-18d6d06f-7f97-4a04-976b-899603e07929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19107055363816890030719961027822077948214018853182644376334076217438059269294 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.19107055363816890030719961027822077948214018853182644376334076217438059269294
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.100081235254067205504126260913157042390127662352542299811448685075266301993646
Short name T85
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Oct 25 02:12:13 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 210768 kb
Host smart-a3908bc2-9325-4e60-a474-190f3d6db32d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100081235254067205504126260913157042390127662352542299811448685075266301993646 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.100081235254067205504126260913157042390127662352542299811448685075266301993646
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.61097846965160551911167349871198997900658932112470018786758039779405991426822
Short name T444
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 25 02:12:13 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 210640 kb
Host smart-cbd9c960-4472-4bfb-902b-134bebc51641
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61097846965160551911167349871198997900658932112470018786758039779405991426822 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.61097846965160551911167349871198997900658932112470018786758039779405991426822
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.12399319812182284340849751811229038378538489856091295847913051804858398099056
Short name T91
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.91 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:31 PM PDT 23
Peak memory 210856 kb
Host smart-dfa4bad5-059d-4dd1-b963-4cd53f033a95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399319812182284340849751811229038378538489856091295847913051804858398099056 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.12399319812182284340849751811229038378538489856091295847913051804858398099056
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.77442177955655428611501614708514437338405394480951131578911515560266220538080
Short name T367
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.43 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 213452 kb
Host smart-196b41d3-90b8-4a54-bd2f-cf8994c0448f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7744217795565542861150161470851443733840539
4480951131578911515560266220538080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.7744217795565
5428611501614708514437338405394480951131578911515560266220538080
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.25403962385607914850400510595776745614553748088349214544169926856528629431576
Short name T448
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 210844 kb
Host smart-9e4e9370-978a-447e-9219-8f6cc81dee84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25403962385607914850400510595776745614553748088349214544169926856528629431576 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.25403962385607914850400510595776745614553748088349214544169926856528629431576
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42164926662996590705266961228593883889105183585250531025072190750055965896374
Short name T398
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.94 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 210848 kb
Host smart-caa04c6b-b2ce-4253-8879-621b58fc76fd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164926662996590705266961228593883889105183585250531025072190750055965896374 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.4216492666299659070526696122859388388910518358525053102507
2190750055965896374
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.43422173963324039197963589263448133652931502267300372545330522214954349756073
Short name T407
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:31 PM PDT 23
Peak memory 210876 kb
Host smart-b116db67-3459-43b3-a46e-a4bdb228ad7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43422173963324039197963589263448133652931502267300372545330522214954349756073 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.43422173963324039197963589263448133652931502267300372545330522214954349756073
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1060146872207455294014283618519036275995038601341983887697315730503208876845
Short name T23
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.18 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:29 PM PDT 23
Peak memory 210872 kb
Host smart-530e2e40-42b6-4156-89bd-e6364804c6a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060146872207455294014283618519036275995038601341983887697315730503208876845 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.1060146872207455294014283618519036275995038601341983887
697315730503208876845
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.149088630074776981726435524098997646183734943773346757152585717680138126146
Short name T58
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.27 seconds
Started Oct 25 02:11:56 PM PDT 23
Finished Oct 25 02:12:13 PM PDT 23
Peak memory 218952 kb
Host smart-9559f932-96a8-4df2-afeb-535fdda412aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149088630074776981726435524098997646183734943773346757152585717680138126146 -assert nopostproc +UVM
_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.149088630074776981726435524098997646183734943773346757152585717680138126146
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.67062101987135509025468477545277240918760671134265698108207652753208934174165
Short name T50
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.7 seconds
Started Oct 25 02:12:34 PM PDT 23
Finished Oct 25 02:13:56 PM PDT 23
Peak memory 211116 kb
Host smart-938d25d4-4f79-4485-8ca5-e8b414c92578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67062101987135509025468477545277240918760671134265698108207652753208934174165 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.67062101987135509025468477545277240918760671134265698108207652753208934174165
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.67739899498700339371788302488836430630785420562330508370441840306444615802450
Short name T400
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.38 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 213516 kb
Host smart-31c3a8ab-cc49-4026-8015-713517ff9877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6773989949870033937178830248883643063078542
0562330508370441840306444615802450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.6773989949870
0339371788302488836430630785420562330508370441840306444615802450
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.44664137605957325989200063549743043974865853770525439477128879370371145428517
Short name T434
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:34 PM PDT 23
Peak memory 210876 kb
Host smart-0ba43b0d-9cc4-4ca7-b44b-085cd68a9071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44664137605957325989200063549743043974865853770525439477128879370371145428517 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.44664137605957325989200063549743043974865853770525439477128879370371145428517
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.106315765456241584676921494422990361170277610507605533641449793514655361650735
Short name T31
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.8 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:17:01 PM PDT 23
Peak memory 218872 kb
Host smart-79596783-1ee1-4449-b1fe-ba9a64921b7d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106315765456241584676921494422990361170277610507605533641449793514655361650735 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.1063157654562415846769214944229903611702776105076055336
41449793514655361650735
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.94160831084887710771511534614717852789996174903714458513224673229688951375428
Short name T387
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.04 seconds
Started Oct 25 02:12:33 PM PDT 23
Finished Oct 25 02:12:48 PM PDT 23
Peak memory 210792 kb
Host smart-fd669b91-7233-45ff-a6e5-99327c0436d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94160831084887710771511534614717852789996174903714458513224673229688951375428
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.941608310848877107715115346147178527899961749037144585
13224673229688951375428
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.61588653688284051476403661722923069582477500214824105024064299111017193325113
Short name T442
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.17 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 219144 kb
Host smart-3632bcf4-d9ac-408b-9412-213108d0b8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61588653688284051476403661722923069582477500214824105024064299111017193325113 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.61588653688284051476403661722923069582477500214824105024064299111017193325113
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.60997478347382225022189588608074662154886821872594444064096368251932540613979
Short name T42
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.42 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:13:43 PM PDT 23
Peak memory 211072 kb
Host smart-6227e1ef-abfe-494f-8642-655b939d936d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60997478347382225022189588608074662154886821872594444064096368251932540613979 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.60997478347382225022189588608074662154886821872594444064096368251932540613979
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.106550173087798356874953306675032963101252185287240844736442927360609187625512
Short name T24
Test name
Test status
Simulation time 3135422826 ps
CPU time 13.06 seconds
Started Oct 25 02:12:36 PM PDT 23
Finished Oct 25 02:12:50 PM PDT 23
Peak memory 213472 kb
Host smart-029ac01f-c324-4069-b7dd-6b9af3834a63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065501730877983568749533066750329631012521
85287240844736442927360609187625512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.106550173087
798356874953306675032963101252185287240844736442927360609187625512
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.20594008272960405865419989768602956106705571835684769087481475247105390781979
Short name T447
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:33 PM PDT 23
Peak memory 210836 kb
Host smart-e5216ad2-c502-4f01-ab08-3ae4b6ba60d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20594008272960405865419989768602956106705571835684769087481475247105390781979 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.20594008272960405865419989768602956106705571835684769087481475247105390781979
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.43882352361195353068183462749561629574262138801402347314579547869085430430989
Short name T55
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.6 seconds
Started Oct 25 02:12:34 PM PDT 23
Finished Oct 25 02:17:20 PM PDT 23
Peak memory 218916 kb
Host smart-a1b6cb5d-6777-4639-8433-eecf734f9bc5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43882352361195353068183462749561629574262138801402347314579547869085430430989 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.43882352361195353068183462749561629574262138801402347314
579547869085430430989
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.57643619664380930257266211354673114519160569022093997308558682678365558046864
Short name T70
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.46 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:36 PM PDT 23
Peak memory 210832 kb
Host smart-0827f7e1-a07b-4db1-9b14-12097f6d4c5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57643619664380930257266211354673114519160569022093997308558682678365558046864
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.576436196643809302572662113546731145191605690220939973
08558682678365558046864
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.47340540287768478345443245431012818381794148625041686709536115676799209602276
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.4 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:12:38 PM PDT 23
Peak memory 219116 kb
Host smart-5d7f27d2-6041-4043-a213-bc38b3519877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47340540287768478345443245431012818381794148625041686709536115676799209602276 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.47340540287768478345443245431012818381794148625041686709536115676799209602276
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.7852681800869110949932119510875729358502030451984528507565725394096101876718
Short name T46
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.5 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:13:39 PM PDT 23
Peak memory 211060 kb
Host smart-1db81201-3d79-4fca-95ee-ccff04192e96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7852681800869110949932119510875729358502030451984528507565725394096101876718 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.7852681800869110949932119510875729358502030451984528507565725394096101876718
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.16707806903091376280561649643479700930281553797619365651187356383011915429768
Short name T433
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.37 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:52 PM PDT 23
Peak memory 213424 kb
Host smart-710efdf8-77be-42ca-a00c-b069d303e0d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670780690309137628056164964347970093028155
3797619365651187356383011915429768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1670780690309
1376280561649643479700930281553797619365651187356383011915429768
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.107436989279380555095113434056379123568101755293807590872698512987278075893825
Short name T446
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 210836 kb
Host smart-d55e27d0-9016-43f6-9011-78ae5222282b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107436989279380555095113434056379123568101755293807590872698512987278075893825 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.107436989279380555095113434056379123568101755293807590872698512987278075893825
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.18569429513467157880227370633602161927189884614319487440615452331888474968851
Short name T418
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.82 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:17:23 PM PDT 23
Peak memory 218864 kb
Host smart-5d196f68-bf42-48e2-80c4-297ddec405cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569429513467157880227370633602161927189884614319487440615452331888474968851 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.18569429513467157880227370633602161927189884614319487440
615452331888474968851
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.66548614425844367886550002182678498076781860110650930113125630623884586650610
Short name T373
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.64 seconds
Started Oct 25 02:12:42 PM PDT 23
Finished Oct 25 02:12:57 PM PDT 23
Peak memory 210888 kb
Host smart-8a59cbad-bbb6-471e-a590-dd66aa044cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66548614425844367886550002182678498076781860110650930113125630623884586650610
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.665486144258443678865500021826784980767818601106509301
13125630623884586650610
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.77307586025227276689553424768849244920391409442420631171492830640169759655730
Short name T429
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.22 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:33 PM PDT 23
Peak memory 219076 kb
Host smart-bad07fbb-5702-45c5-915b-25bb8d543f75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77307586025227276689553424768849244920391409442420631171492830640169759655730 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.77307586025227276689553424768849244920391409442420631171492830640169759655730
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.49756032459899527324412186481909223638889668113636331503234247378443502916734
Short name T22
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.46 seconds
Started Oct 25 02:12:42 PM PDT 23
Finished Oct 25 02:14:05 PM PDT 23
Peak memory 211112 kb
Host smart-4df7ab69-6e59-4158-936c-46844cd9e0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49756032459899527324412186481909223638889668113636331503234247378443502916734 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.49756032459899527324412186481909223638889668113636331503234247378443502916734
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.61267467533226707403032083799573129062669654515754066375612096260625824516461
Short name T18
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.27 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:12 PM PDT 23
Peak memory 213520 kb
Host smart-2b669a5a-087f-48cf-a314-5a792d28eb48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6126746753322670740303208379957312906266965
4515754066375612096260625824516461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.6126746753322
6707403032083799573129062669654515754066375612096260625824516461
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.102496765372594456238388202864214505731960323708896510855595092932657111682246
Short name T449
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.09 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:12:53 PM PDT 23
Peak memory 210744 kb
Host smart-7ac0e008-c008-4b68-9a07-ceee2b892b63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102496765372594456238388202864214505731960323708896510855595092932657111682246 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.102496765372594456238388202864214505731960323708896510855595092932657111682246
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.11603249498625009186419567667300647987299957161130927259633150426039446528147
Short name T388
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.7 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:17:28 PM PDT 23
Peak memory 218892 kb
Host smart-e56f454e-61ae-437a-b87b-067591b7e440
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11603249498625009186419567667300647987299957161130927259633150426039446528147 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.11603249498625009186419567667300647987299957161130927259
633150426039446528147
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.26763955336758940513044860622672325245837779824504754631728937538636705000820
Short name T72
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.28 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:13:09 PM PDT 23
Peak memory 210832 kb
Host smart-2907f193-4b66-48b6-877d-56d57dfe97bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763955336758940513044860622672325245837779824504754631728937538636705000820
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.267639553367589405130448606226723252458377798245047546
31728937538636705000820
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.33703275470909831431497657418451780042736214899557345573973863516829485793253
Short name T51
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.33 seconds
Started Oct 25 02:12:25 PM PDT 23
Finished Oct 25 02:12:42 PM PDT 23
Peak memory 219048 kb
Host smart-f5934fda-dc5a-4c45-afbc-374d5e6b6ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33703275470909831431497657418451780042736214899557345573973863516829485793253 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.33703275470909831431497657418451780042736214899557345573973863516829485793253
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.110738601903960959814269979858380303324225024036317319951165876766148753608239
Short name T376
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.62 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:14:03 PM PDT 23
Peak memory 210984 kb
Host smart-a632647a-8067-490e-bb12-b0eb901eeb61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110738601903960959814269979858380303324225024036317319951165876766148753608239 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.110738601903960959814269979858380303324225024036317319951165876766148753608239
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.52495687054736197510475509082275682365382147202121198608752918611088644390850
Short name T430
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.04 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:11 PM PDT 23
Peak memory 213520 kb
Host smart-a5789eda-b744-4461-9108-011dc0a02b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5249568705473619751047550908227568236538214
7202121198608752918611088644390850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.5249568705473
6197510475509082275682365382147202121198608752918611088644390850
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.110803389748547661926194997844737323254338190982474118000068623974351174923075
Short name T393
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 210872 kb
Host smart-f4db9418-3808-47f0-b4d9-f05f138ef61e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110803389748547661926194997844737323254338190982474118000068623974351174923075 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.110803389748547661926194997844737323254338190982474118000068623974351174923075
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.19317552672696759743737596530365992234583193817760325598712208423115394274484
Short name T424
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.58 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:17:41 PM PDT 23
Peak memory 218996 kb
Host smart-ac57fa0e-aed1-485a-95ac-489475610d4c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19317552672696759743737596530365992234583193817760325598712208423115394274484 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.19317552672696759743737596530365992234583193817760325598
712208423115394274484
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.74562571482101053528603974262656408125257989693350719291304762210655588447053
Short name T369
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.14 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:13:08 PM PDT 23
Peak memory 210752 kb
Host smart-7b7cf8db-c3a8-4a4e-9ed1-baaf5061cc3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74562571482101053528603974262656408125257989693350719291304762210655588447053
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.745625714821010535286039742626564081252579896933507192
91304762210655588447053
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.90532740308077152833154211881146952926565838685587681923865880231319861815805
Short name T390
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.32 seconds
Started Oct 25 02:12:42 PM PDT 23
Finished Oct 25 02:12:58 PM PDT 23
Peak memory 219108 kb
Host smart-924b2964-6723-4939-b378-6444725dc1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90532740308077152833154211881146952926565838685587681923865880231319861815805 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.90532740308077152833154211881146952926565838685587681923865880231319861815805
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.55861925533418732454101330055762481436243118303138110907812222125431442804723
Short name T94
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.28 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 211064 kb
Host smart-2716b2a4-734b-48a0-8418-a483a402c7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55861925533418732454101330055762481436243118303138110907812222125431442804723 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.55861925533418732454101330055762481436243118303138110907812222125431442804723
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.20708341059294745687921148740897772282026978889526760313893182994585042718521
Short name T354
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.51 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:50:53 PM PDT 23
Peak memory 211108 kb
Host smart-5b0b052c-2474-4ab3-a049-04003cfbb7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20708341059294745687921148740897772282026978889526760313893182994585042718521 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.20708341059294745687921148740897772282026978889526760313893182994585042718521
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.87079949363834419149734776357264144659590489866693392694445515395914235229893
Short name T221
Test name
Test status
Simulation time 69854280986 ps
CPU time 342 seconds
Started Oct 25 01:50:39 PM PDT 23
Finished Oct 25 01:56:22 PM PDT 23
Peak memory 237764 kb
Host smart-ff648494-3613-4a0e-a8da-a9bddc3d094c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87079949363834419149734776357264144659590489866693392694445515395914235229893 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.8707994936383441914973477635726414465959048986669339269444
5515395914235229893
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.35522950516634858160644326182781135523474323102135794357581767996249968928706
Short name T202
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.93 seconds
Started Oct 25 01:50:20 PM PDT 23
Finished Oct 25 01:50:46 PM PDT 23
Peak memory 211616 kb
Host smart-c4124c7c-bd66-40e4-8b05-311714f477bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35522950516634858160644326182781135523474323102135794357581767996249968928706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.rom_ctrl_kmac_err_chk.35522950516634858160644326182781135523474323102135794357581767996249968928706
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.41339601820384020932930843455966798073358566652582672750180159079321701342463
Short name T163
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.42 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:56 PM PDT 23
Peak memory 211096 kb
Host smart-37dae3a6-49d1-4fdf-abd2-9c4cf3b1a2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41339601820384020932930843455966798073358566652582672750180159079321701342463 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.41339601820384020932930843455966798073358566652582672750180159079321701342463
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.106470952250699353703735985289767064327086567879866048869701417017877044824426
Short name T34
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.28 seconds
Started Oct 25 01:50:23 PM PDT 23
Finished Oct 25 01:52:20 PM PDT 23
Peak memory 236680 kb
Host smart-306f452b-993a-457d-a349-887c145e1dbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106470952250699353703735985289767064327086567879866048869701417017877044824426 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.106470952250699353703735985289767064327086567879866048869701417017877044824426
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.59934012140166634589516272224068997034916991084632131165019788517840072843958
Short name T243
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.43 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:50:50 PM PDT 23
Peak memory 212852 kb
Host smart-79addb38-35cb-4443-b4b8-7d1da6a4d991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59934012140166634589516272224068997034916991084632131165019788517840072843958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_smoke.59934012140166634589516272224068997034916991084632131165019788517840072843958
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.78526122897210288919438375994096793545329296170420862226615086342199973529102
Short name T208
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.73 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:51:04 PM PDT 23
Peak memory 212980 kb
Host smart-8a85c1f7-08b9-4b18-b4c3-ac68d838f8d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785261228972102889194383759940967935453292961704208622266150863
42199973529102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.785261228972102889194383759940967935453292961704208
62226615086342199973529102
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.30116395089921157691147127347087408020300595789969344248949117782396387730079
Short name T308
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:54 PM PDT 23
Peak memory 211080 kb
Host smart-c6ebc5d4-204b-483a-a415-a223e4d676f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30116395089921157691147127347087408020300595789969344248949117782396387730079 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.30116395089921157691147127347087408020300595789969344248949117782396387730079
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.10823228706233911596696260594226458546583057172089347544977129168446553632609
Short name T137
Test name
Test status
Simulation time 69854280986 ps
CPU time 353.44 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:56:36 PM PDT 23
Peak memory 237752 kb
Host smart-8d272483-b8a7-4ec7-8875-a6b6c518872a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823228706233911596696260594226458546583057172089347544977129168446553632609 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.1082322870623391159669626059422645854658305717208934754497
7129168446553632609
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.112747360008839005951174418970348408375496984905881976712045966151182293824561
Short name T205
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 211424 kb
Host smart-55977e63-98f3-4680-b3d6-da1cb79fed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112747360008839005951174418970348408375496984905881976712045966151182293824561 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.rom_ctrl_kmac_err_chk.112747360008839005951174418970348408375496984905881976712045966151182293824561
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.99917500934010537766886269450287418010392606545495416562040365262876676838830
Short name T298
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 25 01:50:24 PM PDT 23
Finished Oct 25 01:50:38 PM PDT 23
Peak memory 211152 kb
Host smart-76faba04-c3a6-4457-a9fe-aefb8d8eb2b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=99917500934010537766886269450287418010392606545495416562040365262876676838830 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.99917500934010537766886269450287418010392606545495416562040365262876676838830
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.31673875258573000902543293031769024772765130843582147368667380569255236779980
Short name T176
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.88 seconds
Started Oct 25 01:50:25 PM PDT 23
Finished Oct 25 01:50:53 PM PDT 23
Peak memory 212664 kb
Host smart-5ce8e58e-928c-4e30-b11b-35afe25ad178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31673875258573000902543293031769024772765130843582147368667380569255236779980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_smoke.31673875258573000902543293031769024772765130843582147368667380569255236779980
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.52321675425581696615828806776023169770267249803331679077124421697374103044732
Short name T288
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.67 seconds
Started Oct 25 01:50:25 PM PDT 23
Finished Oct 25 01:51:07 PM PDT 23
Peak memory 212768 kb
Host smart-d66b85dd-1889-4781-a901-ff98620d9f8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523216754255816966158288067760231697702672498033316790771244216
97374103044732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.523216754255816966158288067760231697702672498033316
79077124421697374103044732
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.71299432409709236216976626268475636990212075301108808773166522786163940031400
Short name T296
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:51:40 PM PDT 23
Peak memory 211188 kb
Host smart-69503ab4-d840-44c9-8030-f5301274770c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71299432409709236216976626268475636990212075301108808773166522786163940031400 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.71299432409709236216976626268475636990212075301108808773166522786163940031400
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.74182756263868344844975519053936743798041685793664634429143300187962575052114
Short name T35
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.53 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:56:28 PM PDT 23
Peak memory 237744 kb
Host smart-2b34d1ee-72c4-49a2-89b7-fba85d4fec96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74182756263868344844975519053936743798041685793664634429143300187962575052114 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.741827562638683448449755190539367437980416857936646344291
43300187962575052114
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.22625769501177258801250890515611991162984009871004975632971504519706571220317
Short name T235
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.76 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:14 PM PDT 23
Peak memory 211724 kb
Host smart-08e1db8f-a4e9-4e21-9b65-bfbe1ac4d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22625769501177258801250890515611991162984009871004975632971504519706571220317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rom_ctrl_kmac_err_chk.22625769501177258801250890515611991162984009871004975632971504519706571220317
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.53432745682378404537993780989686189374346437555202535407207659949880402405994
Short name T109
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.18 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:13 PM PDT 23
Peak memory 211192 kb
Host smart-b3751470-de08-4a82-87fb-e0c7192f7052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53432745682378404537993780989686189374346437555202535407207659949880402405994 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.53432745682378404537993780989686189374346437555202535407207659949880402405994
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.78826584503433977377815549142187255538596519366408884142383620292155243521053
Short name T264
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 212936 kb
Host smart-5fa663a7-690f-466a-96c7-489c584bf292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78826584503433977377815549142187255538596519366408884142383620292155243521053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.rom_ctrl_smoke.78826584503433977377815549142187255538596519366408884142383620292155243521053
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.58752253954572708264345431214658868860280162960625412089405793999039365301842
Short name T268
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.46 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:40 PM PDT 23
Peak memory 212852 kb
Host smart-f9fc9367-2a29-4390-9263-673e68b680ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587522539545727082643454312146588688602801629606254120894057939
99039365301842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.58752253954572708264345431214658868860280162960625
412089405793999039365301842
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.110431882945379342736679503334999992493031645193534658118878465534328846412484
Short name T285
Test name
Test status
Simulation time 3124113076 ps
CPU time 13.02 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:02 PM PDT 23
Peak memory 211220 kb
Host smart-b18636e6-0c79-4613-9924-afbc9e5aa5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110431882945379342736679503334999992493031645193534658118878465534328846412484 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.110431882945379342736679503334999992493031645193534658118878465534328846412484
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.20872926029523391952424820782683402402156918757004416578542945627681718941499
Short name T339
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.82 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:56:24 PM PDT 23
Peak memory 237640 kb
Host smart-9189215d-a5ce-4842-a675-b0c282bd8304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20872926029523391952424820782683402402156918757004416578542945627681718941499 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.208729260295233919524248207826834024021569187570044165785
42945627681718941499
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.49251061944704203117331313027606836316637270632784570847188600292850108342896
Short name T217
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.47 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:14 PM PDT 23
Peak memory 211640 kb
Host smart-84f267e3-e20f-4929-b4f3-38d097169856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49251061944704203117331313027606836316637270632784570847188600292850108342896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.rom_ctrl_kmac_err_chk.49251061944704203117331313027606836316637270632784570847188600292850108342896
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.108678163648296594495258250377672449023618912993102963643090811217278677324723
Short name T123
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Oct 25 01:51:03 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 210908 kb
Host smart-bb4969ef-219b-49c7-866c-8c1414bccd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108678163648296594495258250377672449023618912993102963643090811217278677324723 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.108678163648296594495258250377672449023618912993102963643090811217278677324723
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.74963690685086110696684591749136879463191234223794897111798769973399051088859
Short name T299
Test name
Test status
Simulation time 6265461576 ps
CPU time 28 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 212756 kb
Host smart-4388f345-7bf3-4535-8c98-2b64530e2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74963690685086110696684591749136879463191234223794897111798769973399051088859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_smoke.74963690685086110696684591749136879463191234223794897111798769973399051088859
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.81791140798317279467082581348707938113700164332020289134943104324853557382211
Short name T188
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.43 seconds
Started Oct 25 01:51:20 PM PDT 23
Finished Oct 25 01:52:04 PM PDT 23
Peak memory 213004 kb
Host smart-10b46bb0-589b-4128-991f-656404fc7e0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817911407983172794670825813487079381137001643320202891349431043
24853557382211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.81791140798317279467082581348707938113700164332020
289134943104324853557382211
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.10578833642007874471995549927783518464140334099560487738030030261750639081908
Short name T140
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.48 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:56:32 PM PDT 23
Peak memory 237680 kb
Host smart-a595f08c-ed54-416d-9ee6-47e904adfcfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578833642007874471995549927783518464140334099560487738030030261750639081908 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.105788336420078744719955499277835184641403340995604877380
30030261750639081908
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3478149215723151188638582971437039938759102382980034373899562301557917787701
Short name T317
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 25 01:50:37 PM PDT 23
Finished Oct 25 01:50:51 PM PDT 23
Peak memory 211292 kb
Host smart-87c9d22b-e6b1-4da1-a4fb-a365fdfce9c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478149215723151188638582971437039938759102382980034373899562301557917787701 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3478149215723151188638582971437039938759102382980034373899562301557917787701
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.104355251573035615347402850509870535997374446596747316070977507305938235671638
Short name T132
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 212744 kb
Host smart-dc95bf1b-af34-4b6c-a231-7ec7632fdfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104355251573035615347402850509870535997374446596747316070977507305938235671638 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.rom_ctrl_smoke.104355251573035615347402850509870535997374446596747316070977507305938235671638
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.16442651201201691585313493967739642928320863147936446050517878818334494929588
Short name T320
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.23 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:23 PM PDT 23
Peak memory 212924 kb
Host smart-b029591b-cc3f-4b0f-89d8-7df049095e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164426512012016915853134939677396429283208631479364460505178788
18334494929588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.16442651201201691585313493967739642928320863147936
446050517878818334494929588
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.64489952248551676575009132804895645084429921896542967199063106795789245037302
Short name T146
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:50:53 PM PDT 23
Peak memory 211188 kb
Host smart-05984192-b966-4c45-a0dd-0518e2e6ca7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64489952248551676575009132804895645084429921896542967199063106795789245037302 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.64489952248551676575009132804895645084429921896542967199063106795789245037302
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.84324729973453394031233671920330996603056997680066166983294726676151487287522
Short name T319
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.7 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:56:32 PM PDT 23
Peak memory 237700 kb
Host smart-d2c50dcc-1a7c-4af3-8419-6b96e8fcc33d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84324729973453394031233671920330996603056997680066166983294726676151487287522 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.843247299734533940312336719203309966030569976800661669832
94726676151487287522
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.37918211734674200932620478860417428347692094315133703105096546901512518817464
Short name T209
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.66 seconds
Started Oct 25 01:50:39 PM PDT 23
Finished Oct 25 01:51:06 PM PDT 23
Peak memory 211636 kb
Host smart-edb510a5-3af0-4116-a763-829b334881f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37918211734674200932620478860417428347692094315133703105096546901512518817464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.rom_ctrl_kmac_err_chk.37918211734674200932620478860417428347692094315133703105096546901512518817464
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.65325808162086150729594729994907550398813970684916708917977941654513489287394
Short name T315
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:50:57 PM PDT 23
Peak memory 211132 kb
Host smart-b107f68c-8219-448b-b1a1-5b9a73075b81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65325808162086150729594729994907550398813970684916708917977941654513489287394 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.65325808162086150729594729994907550398813970684916708917977941654513489287394
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.97984005370848778919647397741175644148981896155886780020563577057948887583684
Short name T225
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.85 seconds
Started Oct 25 01:50:51 PM PDT 23
Finished Oct 25 01:51:20 PM PDT 23
Peak memory 212800 kb
Host smart-eeae45fb-c834-4ed0-998a-536eae55802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97984005370848778919647397741175644148981896155886780020563577057948887583684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.rom_ctrl_smoke.97984005370848778919647397741175644148981896155886780020563577057948887583684
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.74814514955425341363239193809706786992055102714041579418110285063438644707179
Short name T153
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.88 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:51:28 PM PDT 23
Peak memory 212940 kb
Host smart-d63974ee-f240-4a9c-ab2d-397bfecce5fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748145149554253413632391938097067869920551027140415794181102850
63438644707179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.74814514955425341363239193809706786992055102714041
579418110285063438644707179
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.70272224019913376876707474105998191800071078075315638427339193040910114387007
Short name T362
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.75 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:56 PM PDT 23
Peak memory 211260 kb
Host smart-be02e457-9826-45ef-841d-a589245031dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70272224019913376876707474105998191800071078075315638427339193040910114387007 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.70272224019913376876707474105998191800071078075315638427339193040910114387007
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.12432252675762171554267312137255716407502695571145451750555829239383310381936
Short name T161
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.7 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:56:23 PM PDT 23
Peak memory 237732 kb
Host smart-ea330939-7f4d-402a-84ea-520172d5c398
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432252675762171554267312137255716407502695571145451750555829239383310381936 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.124322526757621715542673121372557164075026955711454517505
55829239383310381936
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.15199094345068120208775041665464779672474955185869089213510928470398199637276
Short name T220
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.09 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:08 PM PDT 23
Peak memory 211580 kb
Host smart-22cde0be-5b14-4af9-ac46-ebb9ba2b5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15199094345068120208775041665464779672474955185869089213510928470398199637276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.15199094345068120208775041665464779672474955185869089213510928470398199637276
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.45270245082745326438260746805510093699492014087104027713754050262371817976086
Short name T106
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:50:54 PM PDT 23
Peak memory 211168 kb
Host smart-b6e1f8b8-e19b-4e86-a620-b819df168a3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45270245082745326438260746805510093699492014087104027713754050262371817976086 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.45270245082745326438260746805510093699492014087104027713754050262371817976086
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.19112228119090998847309136274367013521164770014778152141311621780629287138060
Short name T334
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.88 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 212748 kb
Host smart-d1013df4-eac5-4f38-bf5c-cb3d4141cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19112228119090998847309136274367013521164770014778152141311621780629287138060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_smoke.19112228119090998847309136274367013521164770014778152141311621780629287138060
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.73282515639309853341325457925565351353118305034922580125430688159683730453244
Short name T258
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.68 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 212824 kb
Host smart-e863d7ad-479d-482e-9d7e-26aba02493c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732825156393098533413254579255653513531183050349225801254306881
59683730453244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.73282515639309853341325457925565351353118305034922
580125430688159683730453244
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3540774199931160834672508672075250171065519341234863280252266865056609087569
Short name T323
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.14 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:50:59 PM PDT 23
Peak memory 211204 kb
Host smart-d99720ef-2bbb-45fb-a13a-d09f7d40845e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540774199931160834672508672075250171065519341234863280252266865056609087569 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3540774199931160834672508672075250171065519341234863280252266865056609087569
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.99753291783724117543947575840116032428140877727354895239080432570430790846988
Short name T154
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.98 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:56:28 PM PDT 23
Peak memory 237608 kb
Host smart-9e6a866d-96fe-4a22-bd75-dc3568f4f76d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99753291783724117543947575840116032428140877727354895239080432570430790846988 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.997532917837241175439475758401160324281408777273548952390
80432570430790846988
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.21318616681447905071838771675399452694672752635459530760624099235239188991812
Short name T360
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:08 PM PDT 23
Peak memory 211620 kb
Host smart-a2533f3f-38ff-4723-839b-a9721f80bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21318616681447905071838771675399452694672752635459530760624099235239188991812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.21318616681447905071838771675399452694672752635459530760624099235239188991812
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.28588135358578695652126684046510029006757882755238320408931580131205515165562
Short name T230
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.44 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:24 PM PDT 23
Peak memory 212952 kb
Host smart-d9a8b72e-2b05-427d-ab59-32ae6897be34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285881353585786956521266840465100290067578827552383204089315801
31205515165562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.28588135358578695652126684046510029006757882755238
320408931580131205515165562
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.57971711685404697666214599026258419712413037558094257715006449290132658828748
Short name T324
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.61 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:51:38 PM PDT 23
Peak memory 211160 kb
Host smart-949aab56-9fd6-437c-9db4-092d99a2c5e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57971711685404697666214599026258419712413037558094257715006449290132658828748 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.57971711685404697666214599026258419712413037558094257715006449290132658828748
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.111396864695637080407824647723267304875408286300025878850945739984562578486393
Short name T13
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.15 seconds
Started Oct 25 01:51:14 PM PDT 23
Finished Oct 25 01:56:58 PM PDT 23
Peak memory 237744 kb
Host smart-f9c5090a-696c-4d17-992b-d2ac541cb782
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111396864695637080407824647723267304875408286300025878850945739984562578486393 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.11139686469563708040782464772326730487540828630002587885
0945739984562578486393
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.110821965937504906131370093989465576557039708557903643445065247089927712607635
Short name T103
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.93 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:23 PM PDT 23
Peak memory 211652 kb
Host smart-05dbb2a5-f2a9-462a-9ca4-230346d6ffd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110821965937504906131370093989465576557039708557903643445065247089927712607635 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rom_ctrl_kmac_err_chk.110821965937504906131370093989465576557039708557903643445065247089927712607635
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.81459283110085070838589575148348824183618625724857629577395354283423424569403
Short name T238
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:01 PM PDT 23
Peak memory 211096 kb
Host smart-2f240050-f050-4e78-beb7-f2e528e25a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=81459283110085070838589575148348824183618625724857629577395354283423424569403 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.81459283110085070838589575148348824183618625724857629577395354283423424569403
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.98957501467550050048446347320976040239475522610623794012764896234519654218359
Short name T252
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.85 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:51:15 PM PDT 23
Peak memory 212868 kb
Host smart-56ea91b0-487a-41ed-ab5a-4e5e5888e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98957501467550050048446347320976040239475522610623794012764896234519654218359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_smoke.98957501467550050048446347320976040239475522610623794012764896234519654218359
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.36251205762857793268637671554520781499983753565916109082495387033016881245048
Short name T171
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.94 seconds
Started Oct 25 01:50:56 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 212936 kb
Host smart-d54b5157-1947-4af8-8261-1fb9d87e91ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362512057628577932686376715545207814999837535659161090824953870
33016881245048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.36251205762857793268637671554520781499983753565916
109082495387033016881245048
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.48881058697435831408652558653214528471597642850076216573369916038682175166421
Short name T251
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 25 01:51:12 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 211128 kb
Host smart-73f58fff-882e-4f9b-9f4b-44b1ee36299e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48881058697435831408652558653214528471597642850076216573369916038682175166421 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.48881058697435831408652558653214528471597642850076216573369916038682175166421
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.19595859319370994279574869574383657729647792950084101621584603334095399413857
Short name T240
Test name
Test status
Simulation time 69854280986 ps
CPU time 348.14 seconds
Started Oct 25 01:51:14 PM PDT 23
Finished Oct 25 01:57:03 PM PDT 23
Peak memory 237692 kb
Host smart-48ba7243-e476-40f4-9a3f-7e8337c15da3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19595859319370994279574869574383657729647792950084101621584603334095399413857 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.195958593193709942795748695743836577296477929500841016215
84603334095399413857
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.50667994554896655762723477565819182298221331217188432436828868061860162930303
Short name T178
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.33 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 211520 kb
Host smart-28eef2d7-5124-4d08-ac82-34e1a77c7c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50667994554896655762723477565819182298221331217188432436828868061860162930303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rom_ctrl_kmac_err_chk.50667994554896655762723477565819182298221331217188432436828868061860162930303
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.105287427175117997463286317966566600384282111485070849980506164097976421219799
Short name T162
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.38 seconds
Started Oct 25 01:50:56 PM PDT 23
Finished Oct 25 01:51:10 PM PDT 23
Peak memory 211128 kb
Host smart-3e953571-6588-4190-9c25-1149138d517f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105287427175117997463286317966566600384282111485070849980506164097976421219799 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.105287427175117997463286317966566600384282111485070849980506164097976421219799
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.80021178892017252620655018343707969242625847119452563063289651198501660783610
Short name T340
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.18 seconds
Started Oct 25 01:51:01 PM PDT 23
Finished Oct 25 01:51:30 PM PDT 23
Peak memory 212812 kb
Host smart-77491027-412e-4b33-bc16-bf11efe5609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80021178892017252620655018343707969242625847119452563063289651198501660783610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.rom_ctrl_smoke.80021178892017252620655018343707969242625847119452563063289651198501660783610
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.92861098180936132951013940796652617068483810540158858878866117239745688715487
Short name T309
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.4 seconds
Started Oct 25 01:51:26 PM PDT 23
Finished Oct 25 01:52:10 PM PDT 23
Peak memory 212900 kb
Host smart-eb73b305-ebf0-470a-a449-548b1d38baa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928610981809361329510139407966526170684838105401588588788661172
39745688715487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.92861098180936132951013940796652617068483810540158
858878866117239745688715487
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.58120246752323959630478059347600193968736893054437813857028029093997036219814
Short name T149
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 25 01:51:29 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 211184 kb
Host smart-96cbb3b5-b69e-4b7f-ace4-6d353cd44607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58120246752323959630478059347600193968736893054437813857028029093997036219814 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.58120246752323959630478059347600193968736893054437813857028029093997036219814
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.33188934793580063577141652385837951140466408270771154878704459134028175961840
Short name T212
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.53 seconds
Started Oct 25 01:51:02 PM PDT 23
Finished Oct 25 01:56:45 PM PDT 23
Peak memory 237692 kb
Host smart-51db25ee-0f87-45d8-a498-e807205ec89e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33188934793580063577141652385837951140466408270771154878704459134028175961840 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.331889347935800635771416523858379511404664082707711548787
04459134028175961840
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.49892462450521287299003171486800117491095977875715939132790497007073550955979
Short name T148
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.32 seconds
Started Oct 25 01:51:02 PM PDT 23
Finished Oct 25 01:51:28 PM PDT 23
Peak memory 211616 kb
Host smart-b2aa4091-91ac-45d2-a6da-0c7d03bad90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49892462450521287299003171486800117491095977875715939132790497007073550955979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.49892462450521287299003171486800117491095977875715939132790497007073550955979
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.19944421776482744961321720117030494443350648982800368944208242546228445296882
Short name T222
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Oct 25 01:51:03 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 211084 kb
Host smart-d07c9c4c-8146-4fb7-9d44-8a8e1b1c0f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19944421776482744961321720117030494443350648982800368944208242546228445296882 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.19944421776482744961321720117030494443350648982800368944208242546228445296882
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.31502318635663113031216945386845546931479828188267252266839664718950609698673
Short name T279
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.86 seconds
Started Oct 25 01:51:02 PM PDT 23
Finished Oct 25 01:51:31 PM PDT 23
Peak memory 212956 kb
Host smart-bf0a7718-50e5-41be-8b3f-3c2935f19c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31502318635663113031216945386845546931479828188267252266839664718950609698673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.31502318635663113031216945386845546931479828188267252266839664718950609698673
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.17952188918396008284965828233881550622923992067213686468729882995218693819370
Short name T102
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.87 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:52:12 PM PDT 23
Peak memory 212896 kb
Host smart-4aa099b5-b490-49d8-b412-8bb0729279b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179521889183960082849658282338815506229239920672136864687298829
95218693819370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.17952188918396008284965828233881550622923992067213
686468729882995218693819370
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.25074041329286272080639224269168888269945186600080628188854707468709388009010
Short name T129
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:51:53 PM PDT 23
Peak memory 211028 kb
Host smart-d5036123-9ceb-42c1-b4e9-e0949a9713d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074041329286272080639224269168888269945186600080628188854707468709388009010 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.25074041329286272080639224269168888269945186600080628188854707468709388009010
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.56413556761706762447370877438784686073793191057652009425817144008424680767537
Short name T306
Test name
Test status
Simulation time 69854280986 ps
CPU time 350.38 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:57:36 PM PDT 23
Peak memory 237748 kb
Host smart-01688dd7-096e-4d5e-be53-e6186e492054
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56413556761706762447370877438784686073793191057652009425817144008424680767537 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.564135567617067624473708774387846860737931910576520094258
17144008424680767537
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.29277536993600348960868870692420371499620722992440713763312460319707081801857
Short name T257
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:52:09 PM PDT 23
Peak memory 211600 kb
Host smart-77142a8b-292b-43c9-947b-d1813211d15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29277536993600348960868870692420371499620722992440713763312460319707081801857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.rom_ctrl_kmac_err_chk.29277536993600348960868870692420371499620722992440713763312460319707081801857
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.33236551593092573286401432950760184946510313179061378239951726555210189111586
Short name T270
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:51:56 PM PDT 23
Peak memory 211208 kb
Host smart-151ea10d-691c-4844-aed2-968aba1d8f99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33236551593092573286401432950760184946510313179061378239951726555210189111586 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.33236551593092573286401432950760184946510313179061378239951726555210189111586
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.79179924468537915168460582477630846624509178320300820403297837879234104349217
Short name T364
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.3 seconds
Started Oct 25 01:51:23 PM PDT 23
Finished Oct 25 01:51:53 PM PDT 23
Peak memory 212836 kb
Host smart-c50fc0d4-c15a-485c-a887-a18630521bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79179924468537915168460582477630846624509178320300820403297837879234104349217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_smoke.79179924468537915168460582477630846624509178320300820403297837879234104349217
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.45536974826992784591859716710361855215824558484293720892233722876715160883604
Short name T200
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.8 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:52:25 PM PDT 23
Peak memory 212852 kb
Host smart-7d46d01a-a8f0-4ac4-8ebe-11a4d2cbc6b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455369748269927845918597167103618552158245584842937208922337228
76715160883604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.45536974826992784591859716710361855215824558484293
720892233722876715160883604
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.113141245629704814505922618556283320891720005613536879246190159442537071861140
Short name T361
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:00 PM PDT 23
Peak memory 211076 kb
Host smart-d977534d-f592-4aa6-a436-4db68041a790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113141245629704814505922618556283320891720005613536879246190159442537071861140 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.113141245629704814505922618556283320891720005613536879246190159442537071861140
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.72749621395426975038623036124083505245534850802685688693233610778241878852438
Short name T328
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.24 seconds
Started Oct 25 01:50:39 PM PDT 23
Finished Oct 25 01:56:24 PM PDT 23
Peak memory 237848 kb
Host smart-ca619332-5855-4a8f-ae6d-60b832a1d8ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72749621395426975038623036124083505245534850802685688693233610778241878852438 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.7274962139542697503862303612408350524553485080268568869323
3610778241878852438
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.15796805565845623235063901188122464775307207034604639292131664225556676429026
Short name T98
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.75 seconds
Started Oct 25 01:50:46 PM PDT 23
Finished Oct 25 01:51:12 PM PDT 23
Peak memory 211508 kb
Host smart-2d444063-3432-4fdd-bf08-7793f1489446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15796805565845623235063901188122464775307207034604639292131664225556676429026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.rom_ctrl_kmac_err_chk.15796805565845623235063901188122464775307207034604639292131664225556676429026
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.34930931602922939247552241173205363147804901933665172327605309849928073658705
Short name T293
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.14 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:50:57 PM PDT 23
Peak memory 211136 kb
Host smart-9fe265dd-4e65-48a8-8536-7a5396d1444f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=34930931602922939247552241173205363147804901933665172327605309849928073658705 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.34930931602922939247552241173205363147804901933665172327605309849928073658705
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.105375894599538127739815706744947729476295488499076707453814136708275145222502
Short name T33
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.79 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:52:40 PM PDT 23
Peak memory 236820 kb
Host smart-fe338318-c7af-4b0e-874a-bbade760412f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105375894599538127739815706744947729476295488499076707453814136708275145222502 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.105375894599538127739815706744947729476295488499076707453814136708275145222502
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.22511902296427408091294080495904662497733763352817554773443864899018305192511
Short name T213
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 212860 kb
Host smart-f7f82795-db94-4d67-9961-affe4a3040e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22511902296427408091294080495904662497733763352817554773443864899018305192511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.22511902296427408091294080495904662497733763352817554773443864899018305192511
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.79454227885342900930118444577595587475751558213864460665994054631538526815186
Short name T170
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.28 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 212832 kb
Host smart-3cb8a317-8d65-4dca-bb57-6e484d3a8ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794542278853429009301184445775955874757515582138644606659940546
31538526815186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.794542278853429009301184445775955874757515582138644
60665994054631538526815186
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.12257284349584766324387958405937284835367593959232337517260783518172221201612
Short name T356
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211164 kb
Host smart-370a1fcf-70a6-48b5-b47c-15cadf0f0ac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12257284349584766324387958405937284835367593959232337517260783518172221201612 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.12257284349584766324387958405937284835367593959232337517260783518172221201612
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.13245769766790534820527585229607441006946277090327748773938574940185271219028
Short name T332
Test name
Test status
Simulation time 69854280986 ps
CPU time 328.18 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:57:14 PM PDT 23
Peak memory 237524 kb
Host smart-fc77c95f-0cd3-4205-8ba3-5aa77542ea90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13245769766790534820527585229607441006946277090327748773938574940185271219028 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.132457697667905348205275852296074410069462770903277487739
38574940185271219028
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.21568189639469790982939358501964180640094511138236538994948585326738803984516
Short name T348
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.33 seconds
Started Oct 25 01:51:49 PM PDT 23
Finished Oct 25 01:52:15 PM PDT 23
Peak memory 211524 kb
Host smart-c3b41e38-48dd-4656-a44d-93581594d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21568189639469790982939358501964180640094511138236538994948585326738803984516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.rom_ctrl_kmac_err_chk.21568189639469790982939358501964180640094511138236538994948585326738803984516
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.107092044521127261916485982359067502145765062336031476005910257314066339935511
Short name T295
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 25 01:51:47 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211020 kb
Host smart-f457adb1-c66e-4175-8153-0bd74e41ff4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107092044521127261916485982359067502145765062336031476005910257314066339935511 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.107092044521127261916485982359067502145765062336031476005910257314066339935511
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.92086214487933461450259610286389485245676451702248901709386833810510484874417
Short name T326
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.08 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:52:09 PM PDT 23
Peak memory 212820 kb
Host smart-1d0549bb-cf23-4980-aaea-37553c4df0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92086214487933461450259610286389485245676451702248901709386833810510484874417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.rom_ctrl_smoke.92086214487933461450259610286389485245676451702248901709386833810510484874417
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.36126366708351199345681862750742218698848317625677166398468069740075964437976
Short name T346
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.42 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:52:24 PM PDT 23
Peak memory 212900 kb
Host smart-2f67a433-ccc3-4564-93a1-e3f80767cac5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361263667083511993456818627507422186988483176256771663984680697
40075964437976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.36126366708351199345681862750742218698848317625677
166398468069740075964437976
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.33917652423285851615139249147457509810127102707808441347202974551966608998945
Short name T233
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Oct 25 01:50:38 PM PDT 23
Finished Oct 25 01:50:51 PM PDT 23
Peak memory 211128 kb
Host smart-83efc2ba-36c1-46d9-9eff-4dcddedab67d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33917652423285851615139249147457509810127102707808441347202974551966608998945 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.33917652423285851615139249147457509810127102707808441347202974551966608998945
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.72481618609829054089797006468490254772405945644403277913756594939019890951925
Short name T358
Test name
Test status
Simulation time 69854280986 ps
CPU time 332.49 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:56:17 PM PDT 23
Peak memory 237564 kb
Host smart-ee6051a3-29f9-43c0-8033-61acd5734479
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72481618609829054089797006468490254772405945644403277913756594939019890951925 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.724816186098290540897970064684902547724059456444032779137
56594939019890951925
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.27191296645398448195589232022879600002335441198931320107208822503142217452014
Short name T105
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.27 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:13 PM PDT 23
Peak memory 211652 kb
Host smart-b7154d87-6a4f-4dca-8682-fd7a973136d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27191296645398448195589232022879600002335441198931320107208822503142217452014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rom_ctrl_kmac_err_chk.27191296645398448195589232022879600002335441198931320107208822503142217452014
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.72328070726290740815812592208151887514383959254149506559380218255202942905501
Short name T81
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:50:54 PM PDT 23
Peak memory 210972 kb
Host smart-52231e8c-69c8-4cde-b321-69888fc08d50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72328070726290740815812592208151887514383959254149506559380218255202942905501 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.72328070726290740815812592208151887514383959254149506559380218255202942905501
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.105917047930097536605467771100199469458310259205069945139160424589452278627757
Short name T134
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.17 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 212868 kb
Host smart-9cd5b5fd-0e10-41a9-ab74-b7a8b236cbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105917047930097536605467771100199469458310259205069945139160424589452278627757 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.rom_ctrl_smoke.105917047930097536605467771100199469458310259205069945139160424589452278627757
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.63224968927396733853912417311088553827899258995391998967446885985132228429316
Short name T286
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.83 seconds
Started Oct 25 01:50:46 PM PDT 23
Finished Oct 25 01:51:29 PM PDT 23
Peak memory 212980 kb
Host smart-ffe6723c-0eb6-4dbb-bcde-a42cd2535020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632249689273967338539124173110885538278992589953919989674468859
85132228429316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.63224968927396733853912417311088553827899258995391
998967446885985132228429316
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.67600999347607047614830088183732953027154338595496859692052027158121215166701
Short name T318
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:50:57 PM PDT 23
Peak memory 211264 kb
Host smart-31dec2d6-c046-447b-ad33-eac46bc5db66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67600999347607047614830088183732953027154338595496859692052027158121215166701 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.67600999347607047614830088183732953027154338595496859692052027158121215166701
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.6679422299961449445885790967599011571951315056836918041977393728011808582259
Short name T254
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.18 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:56:23 PM PDT 23
Peak memory 237740 kb
Host smart-df59d061-89d8-4a19-b5a8-9c443ee9a034
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6679422299961449445885790967599011571951315056836918041977393728011808582259 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.6679422299961449445885790967599011571951315056836918041977
393728011808582259
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.113835948769523678150900185404057278327767034701135564349104386573721472541544
Short name T248
Test name
Test status
Simulation time 6233818126 ps
CPU time 26 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 211728 kb
Host smart-f1a1361c-60e3-4da1-9faa-69c61c48b42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113835948769523678150900185404057278327767034701135564349104386573721472541544 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rom_ctrl_kmac_err_chk.113835948769523678150900185404057278327767034701135564349104386573721472541544
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.46539076448028304080897217796736389282296785105646610279958385806196937051724
Short name T234
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:56 PM PDT 23
Peak memory 211176 kb
Host smart-ef10d0bb-b527-41d1-834b-6c380be00c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46539076448028304080897217796736389282296785105646610279958385806196937051724 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.46539076448028304080897217796736389282296785105646610279958385806196937051724
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.52302131493331631160847009114670911224041503879099547183587740754666588314332
Short name T283
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Oct 25 01:50:46 PM PDT 23
Finished Oct 25 01:51:15 PM PDT 23
Peak memory 212760 kb
Host smart-f455a939-ccc1-4da4-a4fe-f69037104692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52302131493331631160847009114670911224041503879099547183587740754666588314332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_smoke.52302131493331631160847009114670911224041503879099547183587740754666588314332
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.6346712868817546944338292613915161974971043588054626351669467203323959364552
Short name T177
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.36 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 212940 kb
Host smart-dfb2d407-1d25-4c85-be45-b2f4b070a1c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634671286881754694433829261391516197497104358805462635166946720
3323959364552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.634671286881754694433829261391516197497104358805462
6351669467203323959364552
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.41997549314454287768639830420999761355908375664018203456842572511311853147746
Short name T330
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Oct 25 01:51:11 PM PDT 23
Finished Oct 25 01:51:24 PM PDT 23
Peak memory 211172 kb
Host smart-9a80830b-81c4-46d0-ba1c-773bfd61f91f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997549314454287768639830420999761355908375664018203456842572511311853147746 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.41997549314454287768639830420999761355908375664018203456842572511311853147746
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2564458123981746460729382424227673012831199700149479356269628837743360444245
Short name T192
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.85 seconds
Started Oct 25 01:50:55 PM PDT 23
Finished Oct 25 01:56:36 PM PDT 23
Peak memory 237640 kb
Host smart-213957f5-bd60-4c74-a32e-d642a3b0ca4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564458123981746460729382424227673012831199700149479356269628837743360444245 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.2564458123981746460729382424227673012831199700149479356269
628837743360444245
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.45163275656071106961540444470472489354743052331921453520184515957168145834304
Short name T266
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.79 seconds
Started Oct 25 01:51:13 PM PDT 23
Finished Oct 25 01:51:39 PM PDT 23
Peak memory 211644 kb
Host smart-a73031cb-24fc-44c6-9605-40e4dbac0d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45163275656071106961540444470472489354743052331921453520184515957168145834304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.rom_ctrl_kmac_err_chk.45163275656071106961540444470472489354743052331921453520184515957168145834304
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.77890295907538824783592058231484913917027712210826207315546405203695605877462
Short name T167
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:01 PM PDT 23
Peak memory 211096 kb
Host smart-bbb2aed9-764e-4059-a24d-cede2b19306b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77890295907538824783592058231484913917027712210826207315546405203695605877462 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.77890295907538824783592058231484913917027712210826207315546405203695605877462
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.35585959570437091853550629365277382823128129859480996265931445731740986203298
Short name T191
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.76 seconds
Started Oct 25 01:50:58 PM PDT 23
Finished Oct 25 01:51:27 PM PDT 23
Peak memory 212884 kb
Host smart-0451a0a4-b5f0-4b7b-b768-c49bd3deffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35585959570437091853550629365277382823128129859480996265931445731740986203298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.35585959570437091853550629365277382823128129859480996265931445731740986203298
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.36355330076157251391429669207652487209344622566020923233313642683413660883754
Short name T327
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.27 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:52:07 PM PDT 23
Peak memory 212708 kb
Host smart-e77f5314-b51d-4110-b520-859265e7b9b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363553300761572513914296692076524872093446225660209232333136426
83413660883754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.36355330076157251391429669207652487209344622566020
923233313642683413660883754
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.33494997911307694758738520801541226066679759502400351876127469300636061907137
Short name T247
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.4 seconds
Started Oct 25 01:51:02 PM PDT 23
Finished Oct 25 01:51:15 PM PDT 23
Peak memory 211320 kb
Host smart-99b38f68-9108-4407-b211-3e0dea6e41bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33494997911307694758738520801541226066679759502400351876127469300636061907137 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.33494997911307694758738520801541226066679759502400351876127469300636061907137
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.52896346381073103909235271867855076505059446718310227087000654627125160692649
Short name T342
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.24 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:56:30 PM PDT 23
Peak memory 237564 kb
Host smart-dff3c285-b993-496b-820a-1dd070fddc93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52896346381073103909235271867855076505059446718310227087000654627125160692649 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.528963463810731039092352718678550765050594467183102270870
00654627125160692649
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.44399375701471461466727337509424470821523089055853153446343254263011522762307
Short name T311
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.26 seconds
Started Oct 25 01:51:21 PM PDT 23
Finished Oct 25 01:51:48 PM PDT 23
Peak memory 211584 kb
Host smart-93eab65d-d5be-483b-8698-ac01f445cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44399375701471461466727337509424470821523089055853153446343254263011522762307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rom_ctrl_kmac_err_chk.44399375701471461466727337509424470821523089055853153446343254263011522762307
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.5529943624986994713517017992656958627572440875668715288090158995188831196968
Short name T193
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.25 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:13 PM PDT 23
Peak memory 211100 kb
Host smart-8ffd9288-f75e-407d-86da-165747ccb842
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5529943624986994713517017992656958627572440875668715288090158995188831196968 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.5529943624986994713517017992656958627572440875668715288090158995188831196968
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4291026980715758224351933773567531168243194542483739994528750700450836322598
Short name T255
Test name
Test status
Simulation time 6265461576 ps
CPU time 29 seconds
Started Oct 25 01:50:56 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 212756 kb
Host smart-09449158-c852-468e-9ae9-9c086ac5e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291026980715758224351933773567531168243194542483739994528750700450836322598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.rom_ctrl_smoke.4291026980715758224351933773567531168243194542483739994528750700450836322598
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.66139260356249271761660996869276109183480151969408314654077961679595582994951
Short name T12
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.23 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:31 PM PDT 23
Peak memory 212968 kb
Host smart-45a64531-5091-4c24-8c64-627eaa2abfe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661392603562492717616609968692761091834801519694083146540779616
79595582994951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.66139260356249271761660996869276109183480151969408
314654077961679595582994951
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.49529176885805989658609551351561862834316853223519856959028603004577223697886
Short name T239
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.66 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:51:37 PM PDT 23
Peak memory 211144 kb
Host smart-fa3c7b26-f0c7-4a02-8c82-218b0aac9bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49529176885805989658609551351561862834316853223519856959028603004577223697886 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.49529176885805989658609551351561862834316853223519856959028603004577223697886
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.73266721107218989835500619869307475858515623257051183069732053563615903571232
Short name T322
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.93 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:57:15 PM PDT 23
Peak memory 237660 kb
Host smart-a4f11ff2-9d6c-48c8-9d5b-d2338a45fd68
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73266721107218989835500619869307475858515623257051183069732053563615903571232 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.732667211072189898355006198693074758585156232570511830697
32053563615903571232
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.91313860817494121865138761313836250332610435785929917049743536155977056802593
Short name T273
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.83 seconds
Started Oct 25 01:51:21 PM PDT 23
Finished Oct 25 01:51:48 PM PDT 23
Peak memory 211660 kb
Host smart-8d6c1155-8b3e-4c45-bfd2-41edc9e3ea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91313860817494121865138761313836250332610435785929917049743536155977056802593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.rom_ctrl_kmac_err_chk.91313860817494121865138761313836250332610435785929917049743536155977056802593
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.102302345415004402395672065674966368036485827880419363829263873675013555267082
Short name T316
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.61 seconds
Started Oct 25 01:51:07 PM PDT 23
Finished Oct 25 01:51:21 PM PDT 23
Peak memory 211328 kb
Host smart-2ec5b9a1-8aab-446c-b3e1-c5a31739ca11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102302345415004402395672065674966368036485827880419363829263873675013555267082 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.102302345415004402395672065674966368036485827880419363829263873675013555267082
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.58977691704504755914485599953207410800395908842293414291965417759082720737811
Short name T80
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.62 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:51:58 PM PDT 23
Peak memory 212820 kb
Host smart-545a3d49-2390-4d14-ace6-babd281e84a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58977691704504755914485599953207410800395908842293414291965417759082720737811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_smoke.58977691704504755914485599953207410800395908842293414291965417759082720737811
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.77841740747549278398550517936488771204226180924891701024954994506226719890257
Short name T119
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211208 kb
Host smart-00704b14-ded9-43e3-869a-a50570f0572b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77841740747549278398550517936488771204226180924891701024954994506226719890257 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.77841740747549278398550517936488771204226180924891701024954994506226719890257
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.56411468800933160438009935060050671375933442018714705130493500376375836345252
Short name T199
Test name
Test status
Simulation time 69854280986 ps
CPU time 328.93 seconds
Started Oct 25 01:51:46 PM PDT 23
Finished Oct 25 01:57:16 PM PDT 23
Peak memory 237620 kb
Host smart-ceced732-1f98-414d-8093-6dcd3310a013
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56411468800933160438009935060050671375933442018714705130493500376375836345252 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.564114688009331604380099350600506713759334420187147051304
93500376375836345252
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.20568881006187115918966554651847962008751296557222802202570896365979885310517
Short name T172
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Oct 25 01:51:39 PM PDT 23
Finished Oct 25 01:52:07 PM PDT 23
Peak memory 211660 kb
Host smart-35e4e2bc-3339-46b9-9b57-d023e225da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20568881006187115918966554651847962008751296557222802202570896365979885310517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.20568881006187115918966554651847962008751296557222802202570896365979885310517
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2047829412745450237038466788547239172332186482903947956726489787192347299190
Short name T76
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.46 seconds
Started Oct 25 01:51:38 PM PDT 23
Finished Oct 25 01:51:54 PM PDT 23
Peak memory 211128 kb
Host smart-f3e507e4-ce1d-4411-9140-763be2ef2c83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2047829412745450237038466788547239172332186482903947956726489787192347299190 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2047829412745450237038466788547239172332186482903947956726489787192347299190
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.91052121879511718668396354090017986344615602935418649079658047558878300042719
Short name T168
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.5 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:51:57 PM PDT 23
Peak memory 212792 kb
Host smart-416a7707-9232-4bf3-981f-cc968240dee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91052121879511718668396354090017986344615602935418649079658047558878300042719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.91052121879511718668396354090017986344615602935418649079658047558878300042719
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.76040235308855905554434972233896846453982398831329026232510108841676706485315
Short name T9
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.13 seconds
Started Oct 25 01:51:31 PM PDT 23
Finished Oct 25 01:52:16 PM PDT 23
Peak memory 212940 kb
Host smart-5a3b5b66-5491-48bb-b743-00f19325229e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760402353088559055544349722338968464539823988313290262325101088
41676706485315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.76040235308855905554434972233896846453982398831329
026232510108841676706485315
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.42652161496699722547113926129366932390081151966592210365066345097376587061320
Short name T290
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.62 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:55 PM PDT 23
Peak memory 211080 kb
Host smart-b0cf02b5-8f39-42ff-ab21-bab557d2ec83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652161496699722547113926129366932390081151966592210365066345097376587061320 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.42652161496699722547113926129366932390081151966592210365066345097376587061320
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.17933249588873055508174266533615771447143498843983882062614841456564577469035
Short name T292
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.24 seconds
Started Oct 25 01:51:38 PM PDT 23
Finished Oct 25 01:57:23 PM PDT 23
Peak memory 237704 kb
Host smart-d12ece90-ccdb-4a9f-830a-6b132e280c24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933249588873055508174266533615771447143498843983882062614841456564577469035 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.179332495888730555081742665336157714471434988439838820626
14841456564577469035
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.92032139355095862926905609559562230814908990521825193479197801661503469951464
Short name T112
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.85 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:51:54 PM PDT 23
Peak memory 211736 kb
Host smart-05102b14-471e-4446-a7be-1eb78ec0b969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92032139355095862926905609559562230814908990521825193479197801661503469951464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rom_ctrl_kmac_err_chk.92032139355095862926905609559562230814908990521825193479197801661503469951464
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.27804716209998251250966675654842469445398201145642232871100087582402952776930
Short name T237
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:51:54 PM PDT 23
Peak memory 211224 kb
Host smart-d7c229a2-a9da-479d-a9b4-5d13764ac505
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27804716209998251250966675654842469445398201145642232871100087582402952776930 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.27804716209998251250966675654842469445398201145642232871100087582402952776930
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2613785975847600308227128197275508602896391935188234837508219174394004179160
Short name T336
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:52:17 PM PDT 23
Peak memory 212820 kb
Host smart-05011819-a521-4e33-a685-f2ccec3406b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613785975847600308227128197275508602896391935188234837508219174394004179160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.rom_ctrl_smoke.2613785975847600308227128197275508602896391935188234837508219174394004179160
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.16064713043306287427835354267842987984076604837206856847483206538173716622489
Short name T136
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.71 seconds
Started Oct 25 01:51:38 PM PDT 23
Finished Oct 25 01:52:20 PM PDT 23
Peak memory 212824 kb
Host smart-38a1188e-7d72-4f9d-83c2-9b2c7a803071
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160647130433062874278353542678429879840766048372068568474832065
38173716622489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.16064713043306287427835354267842987984076604837206
856847483206538173716622489
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.11294675020283138443969550814732396310778359941994882334294762046464108943244
Short name T351
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:50:58 PM PDT 23
Peak memory 211208 kb
Host smart-7ae4380d-c5b8-4407-bc39-1fa1d5b334ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11294675020283138443969550814732396310778359941994882334294762046464108943244 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.11294675020283138443969550814732396310778359941994882334294762046464108943244
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.21785170814655261643240161568804044913819566429698994637059801028437811346660
Short name T150
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.8 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:56:31 PM PDT 23
Peak memory 237756 kb
Host smart-08405c6f-e809-4927-9d5c-afcebc2727e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21785170814655261643240161568804044913819566429698994637059801028437811346660 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.217851708146552616432401615688040449138195664296989946370
59801028437811346660
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.90604756354026553854857247856341671169084529472594280033415443246719908527137
Short name T197
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:14 PM PDT 23
Peak memory 211548 kb
Host smart-20c13be8-459a-430f-962d-bbeaf982acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90604756354026553854857247856341671169084529472594280033415443246719908527137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rom_ctrl_kmac_err_chk.90604756354026553854857247856341671169084529472594280033415443246719908527137
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.5709722666584434240401790024765762334019530555005203029157283095430708829221
Short name T117
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:55 PM PDT 23
Peak memory 211212 kb
Host smart-b58bc8d3-5e61-4793-88ea-804ca6e99559
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5709722666584434240401790024765762334019530555005203029157283095430708829221 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.5709722666584434240401790024765762334019530555005203029157283095430708829221
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.23547028898985109043097752905490376056060170071601606242242713496861808993670
Short name T276
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.61 seconds
Started Oct 25 01:51:41 PM PDT 23
Finished Oct 25 01:52:11 PM PDT 23
Peak memory 212812 kb
Host smart-3c75746a-ec56-4437-a5df-dde5ac9db1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23547028898985109043097752905490376056060170071601606242242713496861808993670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.23547028898985109043097752905490376056060170071601606242242713496861808993670
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.109638893880449397994960176612624504972238655242865231406222454545837571019419
Short name T157
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.12 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:51:27 PM PDT 23
Peak memory 212820 kb
Host smart-6fa2c0a6-2743-4677-acb5-73de5b68dd95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109638893880449397994960176612624504972238655242865231406222454
545837571019419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.1096388938804493979949601766126245049722386552428
65231406222454545837571019419
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.78978514686398037912583074871555735914878032045325573052784529397917443128929
Short name T189
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.85 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:12 PM PDT 23
Peak memory 211152 kb
Host smart-b799ae1a-2121-4907-90a8-37eeb8dbe1ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78978514686398037912583074871555735914878032045325573052784529397917443128929 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.78978514686398037912583074871555735914878032045325573052784529397917443128929
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.23107294613847716123890660194657503981343783833432984672673603771527267243094
Short name T185
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.82 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:56:32 PM PDT 23
Peak memory 237616 kb
Host smart-8176eeba-0f7a-4a85-ba74-2f4717c58584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107294613847716123890660194657503981343783833432984672673603771527267243094 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.231072946138477161238906601946575039813437838334329846726
73603771527267243094
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.38160079204752985772960150359059495919286825466884290843004202405180636869928
Short name T15
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.85 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 211484 kb
Host smart-adf39eb5-005d-4f7f-8633-b5ebab4eb0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38160079204752985772960150359059495919286825466884290843004202405180636869928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.38160079204752985772960150359059495919286825466884290843004202405180636869928
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.35000777589083585169643335359596961968798568792184222449431463351563486199673
Short name T297
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.65 seconds
Started Oct 25 01:50:56 PM PDT 23
Finished Oct 25 01:51:10 PM PDT 23
Peak memory 211204 kb
Host smart-ab19067d-4558-43b7-98e8-1688aa133d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35000777589083585169643335359596961968798568792184222449431463351563486199673 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.35000777589083585169643335359596961968798568792184222449431463351563486199673
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.16083162351351054961900952206052237549548774348055627619970416067657692319428
Short name T338
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.38 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 212800 kb
Host smart-fd85cec6-f1eb-41e3-b8d2-bc534b124291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16083162351351054961900952206052237549548774348055627619970416067657692319428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.rom_ctrl_smoke.16083162351351054961900952206052237549548774348055627619970416067657692319428
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.60296394711269459849360506274303040335665325425331707569062401020267032359524
Short name T244
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.66 seconds
Started Oct 25 01:50:39 PM PDT 23
Finished Oct 25 01:51:24 PM PDT 23
Peak memory 213040 kb
Host smart-14994ed7-1353-415d-aa02-1588bc23a3b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602963947112694598493605062743030403356653254253317075690624010
20267032359524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.60296394711269459849360506274303040335665325425331
707569062401020267032359524
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.50670483001665197061555147849721304045156292573329223791872724750372005344296
Short name T249
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:12 PM PDT 23
Peak memory 211076 kb
Host smart-130a7dc4-6205-484f-b52d-7dac398c7194
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50670483001665197061555147849721304045156292573329223791872724750372005344296 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.50670483001665197061555147849721304045156292573329223791872724750372005344296
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.79910293326339791721914539141282176866775952800192488658427327517341882384471
Short name T289
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.06 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:56:24 PM PDT 23
Peak memory 237664 kb
Host smart-2ce75b78-0d7a-4eb3-9bbb-2398419d98b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79910293326339791721914539141282176866775952800192488658427327517341882384471 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.7991029332633979172191453914128217686677595280019248865842
7327517341882384471
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.23352291621037329167761830378001825075853517168190699730981123368903132391946
Short name T180
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.72 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:14 PM PDT 23
Peak memory 211536 kb
Host smart-b8659ae4-6445-433f-a5c8-1d89c6908163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23352291621037329167761830378001825075853517168190699730981123368903132391946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.23352291621037329167761830378001825075853517168190699730981123368903132391946
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.60941545395392044182473835545454261800203800613284602944516259309867184742438
Short name T100
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:50:59 PM PDT 23
Peak memory 211152 kb
Host smart-d7fdf610-098e-4754-a7d8-5d01a321706a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60941545395392044182473835545454261800203800613284602944516259309867184742438 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.60941545395392044182473835545454261800203800613284602944516259309867184742438
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.115677434720130049914552097613769976901079374977242985120212382015752853712685
Short name T16
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.42 seconds
Started Oct 25 01:51:01 PM PDT 23
Finished Oct 25 01:52:59 PM PDT 23
Peak memory 236748 kb
Host smart-4614aca1-5097-4678-bc69-051a757c7292
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115677434720130049914552097613769976901079374977242985120212382015752853712685 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.115677434720130049914552097613769976901079374977242985120212382015752853712685
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.56975635875404220786710848206947927035408425821346277688498364885154133739298
Short name T256
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.63 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:17 PM PDT 23
Peak memory 212936 kb
Host smart-a1277f79-231e-46b0-89e9-a4d7e9cf9cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56975635875404220786710848206947927035408425821346277688498364885154133739298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_smoke.56975635875404220786710848206947927035408425821346277688498364885154133739298
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.87304314510543538859585456299728068918809746070916081394184755818960095228215
Short name T113
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.65 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 212916 kb
Host smart-047befa9-23f4-40d7-b1d0-6a90d413f965
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873043145105435388595854562997280689188097460709160813941847558
18960095228215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.873043145105435388595854562997280689188097460709160
81394184755818960095228215
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.94237170006778416162781159953467110970372256950783852892512262126591021587940
Short name T175
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.74 seconds
Started Oct 25 01:51:11 PM PDT 23
Finished Oct 25 01:51:24 PM PDT 23
Peak memory 210972 kb
Host smart-06144770-c911-437f-85d5-84ba8b6a3268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94237170006778416162781159953467110970372256950783852892512262126591021587940 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.94237170006778416162781159953467110970372256950783852892512262126591021587940
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.19803418964118463129683486316130074108069069907585057160763202476443180964632
Short name T126
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.12 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:56:24 PM PDT 23
Peak memory 237788 kb
Host smart-8c837ac5-5fa9-4923-9d8a-17b122619c27
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19803418964118463129683486316130074108069069907585057160763202476443180964632 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.198034189641184631296834863161300741080690699075850571607
63202476443180964632
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.91599200935926318388525578377542938794447577299447115330502001027614042900347
Short name T138
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.2 seconds
Started Oct 25 01:51:03 PM PDT 23
Finished Oct 25 01:51:28 PM PDT 23
Peak memory 211648 kb
Host smart-a1b3c52f-429b-419e-b571-6bb6606b6afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91599200935926318388525578377542938794447577299447115330502001027614042900347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.rom_ctrl_kmac_err_chk.91599200935926318388525578377542938794447577299447115330502001027614042900347
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.73562956828362929016159336773667653031305303477562887602620657073642329726156
Short name T122
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.52 seconds
Started Oct 25 01:50:59 PM PDT 23
Finished Oct 25 01:51:13 PM PDT 23
Peak memory 211276 kb
Host smart-b195bb7a-c8f2-454b-aea9-31a090abd1eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73562956828362929016159336773667653031305303477562887602620657073642329726156 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.73562956828362929016159336773667653031305303477562887602620657073642329726156
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.91787239415374391452489457049448562218387450581927802614068592438359359443087
Short name T147
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.45 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:16 PM PDT 23
Peak memory 212712 kb
Host smart-615e58b2-3e24-4a19-9efa-8d79782c4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91787239415374391452489457049448562218387450581927802614068592438359359443087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_smoke.91787239415374391452489457049448562218387450581927802614068592438359359443087
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.9769672060639822100242104924902300092847879939114042420463024009875922480467
Short name T287
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.36 seconds
Started Oct 25 01:51:13 PM PDT 23
Finished Oct 25 01:51:57 PM PDT 23
Peak memory 212936 kb
Host smart-d87a2dcb-cfd4-401e-a763-6de648b523da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976967206063982210024210492490230009284787993911404242046302400
9875922480467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.976967206063982210024210492490230009284787993911404
2420463024009875922480467
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.7593375755892787868603327550026443502164533720808543705549959762319722551542
Short name T165
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 25 01:51:12 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 211020 kb
Host smart-1d555db8-5057-4a89-89bd-4c620f2ae2e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7593375755892787868603327550026443502164533720808543705549959762319722551542 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.7593375755892787868603327550026443502164533720808543705549959762319722551542
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.22888180621449181010788103822187866152935597138948464354120567911907781124278
Short name T10
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.86 seconds
Started Oct 25 01:51:16 PM PDT 23
Finished Oct 25 01:57:01 PM PDT 23
Peak memory 237724 kb
Host smart-6383e926-45e6-4929-9073-cc04006b9eed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888180621449181010788103822187866152935597138948464354120567911907781124278 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.228881806214491810107881038221878661529355971389484643541
20567911907781124278
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1809455308286733607400212414142628756691240657304484308127463420320391252036
Short name T128
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.32 seconds
Started Oct 25 01:50:58 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 211384 kb
Host smart-9ca135d8-223a-488d-8d4c-67a7d71df7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809455308286733607400212414142628756691240657304484308127463420320391252036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.rom_ctrl_kmac_err_chk.1809455308286733607400212414142628756691240657304484308127463420320391252036
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.51592220516841408854923534629310745711811653440796756266705542067316137141099
Short name T259
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 211292 kb
Host smart-a26193bb-58c4-4d88-8150-fd199e92fdf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51592220516841408854923534629310745711811653440796756266705542067316137141099 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.51592220516841408854923534629310745711811653440796756266705542067316137141099
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.30582538762021442350842591842836838095646816722320002744431987257180881106930
Short name T329
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.85 seconds
Started Oct 25 01:51:05 PM PDT 23
Finished Oct 25 01:51:34 PM PDT 23
Peak memory 212712 kb
Host smart-f61e4a60-5f5c-4f79-a79c-654e80ff0680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30582538762021442350842591842836838095646816722320002744431987257180881106930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.30582538762021442350842591842836838095646816722320002744431987257180881106930
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.11125232520198732357736399139972501500424202620643224979657688626883460000827
Short name T246
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.21 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:52:08 PM PDT 23
Peak memory 212844 kb
Host smart-4268b861-adb4-4228-8fe5-73362835a681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111252325201987323577363991399725015004242026206432249796576886
26883460000827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.11125232520198732357736399139972501500424202620643
224979657688626883460000827
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.69637023525432473376977378641253001967808662392338390499457416629330500732856
Short name T1
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.46 seconds
Started Oct 25 01:50:55 PM PDT 23
Finished Oct 25 01:51:08 PM PDT 23
Peak memory 211164 kb
Host smart-eba81bcb-fce1-4202-855a-7bdcb7f0bf85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69637023525432473376977378641253001967808662392338390499457416629330500732856 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.69637023525432473376977378641253001967808662392338390499457416629330500732856
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.474703689001183387735019292412221244147215508460288784227449870642990531578
Short name T160
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.31 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:57:09 PM PDT 23
Peak memory 237624 kb
Host smart-7b212ce4-9b97-450b-b486-19448537dc47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474703689001183387735019292412221244147215508460288784227449870642990531578 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.47470368900118338773501929241222124414721550846028878422744
9870642990531578
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.102838399832530495077243412282366618962289332281785408077163958259784821594574
Short name T114
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:50:54 PM PDT 23
Finished Oct 25 01:51:20 PM PDT 23
Peak memory 211592 kb
Host smart-84daf6e6-650a-4653-89ac-76b6c4f15e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102838399832530495077243412282366618962289332281785408077163958259784821594574 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.rom_ctrl_kmac_err_chk.102838399832530495077243412282366618962289332281785408077163958259784821594574
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.6934617802752801291249243348678546510661766666848865290941973951458681192895
Short name T111
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 25 01:50:58 PM PDT 23
Finished Oct 25 01:51:12 PM PDT 23
Peak memory 211324 kb
Host smart-52173ac0-2e5f-4de7-a279-c3d7fba1b5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6934617802752801291249243348678546510661766666848865290941973951458681192895 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.6934617802752801291249243348678546510661766666848865290941973951458681192895
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.54238669174049735076450611179591481670200069363845546505609797739249473776496
Short name T349
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.63 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:51:53 PM PDT 23
Peak memory 212820 kb
Host smart-40420d27-aab4-4150-9709-e50f5ef8978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54238669174049735076450611179591481670200069363845546505609797739249473776496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.54238669174049735076450611179591481670200069363845546505609797739249473776496
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.49885274664611490879675467240660333514572694905140771158859256132934991030354
Short name T207
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.68 seconds
Started Oct 25 01:51:17 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 213016 kb
Host smart-9684fdad-b82d-4762-b0bf-808fe0255dad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498852746646114908796754672406603335145726949051407711588592561
32934991030354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.49885274664611490879675467240660333514572694905140
771158859256132934991030354
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.105078189088797087977634041179519375786083231481073298202057280967621089280426
Short name T341
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Oct 25 01:50:58 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 211240 kb
Host smart-1cd2d826-bec1-4bfa-99a2-78cf0a0ef772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105078189088797087977634041179519375786083231481073298202057280967621089280426 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.105078189088797087977634041179519375786083231481073298202057280967621089280426
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.42035850504115008557611900158966219540452214732851264785724987811997747486953
Short name T155
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.56 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:57:07 PM PDT 23
Peak memory 237508 kb
Host smart-19ccf8be-67b1-4c35-a307-1ab7b3754eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42035850504115008557611900158966219540452214732851264785724987811997747486953 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.420358505041150085576119001589662195404522147328512647857
24987811997747486953
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.91774530658433182954091891239229664029676334225434892856025395563634933067942
Short name T14
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.86 seconds
Started Oct 25 01:51:11 PM PDT 23
Finished Oct 25 01:51:37 PM PDT 23
Peak memory 211624 kb
Host smart-b7a6bae4-0280-4f19-8901-34f6d6a93ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91774530658433182954091891239229664029676334225434892856025395563634933067942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rom_ctrl_kmac_err_chk.91774530658433182954091891239229664029676334225434892856025395563634933067942
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.52346513891310821670585565433667097708683132157402794563607214353592078118510
Short name T307
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Oct 25 01:51:13 PM PDT 23
Finished Oct 25 01:51:27 PM PDT 23
Peak memory 211192 kb
Host smart-edae56b6-6572-490d-8063-4ed661d15f2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52346513891310821670585565433667097708683132157402794563607214353592078118510 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.52346513891310821670585565433667097708683132157402794563607214353592078118510
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.6623878052229893273803367047334466481558696229443216848544248658198838140765
Short name T107
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Oct 25 01:51:10 PM PDT 23
Finished Oct 25 01:51:39 PM PDT 23
Peak memory 212736 kb
Host smart-aed0deaf-89b3-4e9f-b7fc-871694715f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6623878052229893273803367047334466481558696229443216848544248658198838140765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.rom_ctrl_smoke.6623878052229893273803367047334466481558696229443216848544248658198838140765
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.10345853059852840085043956049775302302066247477685096190532319984147661356921
Short name T231
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.34 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:40 PM PDT 23
Peak memory 212980 kb
Host smart-fce663ae-76d3-40a7-9603-0745a71a04ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103458530598528400850439560497753023020662474776850961905323199
84147661356921 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.10345853059852840085043956049775302302066247477685
096190532319984147661356921
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.56770866456749931177040906097946463736604709508149271957457370347380950175003
Short name T190
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 211152 kb
Host smart-8b93dee0-85f4-4364-b1ba-504d2a0e05cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56770866456749931177040906097946463736604709508149271957457370347380950175003 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.56770866456749931177040906097946463736604709508149271957457370347380950175003
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.68800062473811064775665234727669967513322732151609201147383872956924896502908
Short name T245
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.76 seconds
Started Oct 25 01:51:03 PM PDT 23
Finished Oct 25 01:56:41 PM PDT 23
Peak memory 237464 kb
Host smart-7a31fc1c-aa31-4be5-81c6-b8a89dab343b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68800062473811064775665234727669967513322732151609201147383872956924896502908 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.688000624738110647756652347276699675133227321516092011473
83872956924896502908
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.37636622817780074903542219005847521264735185497790977266468235678802366999323
Short name T108
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.76 seconds
Started Oct 25 01:51:08 PM PDT 23
Finished Oct 25 01:51:34 PM PDT 23
Peak memory 211436 kb
Host smart-1b8eb3a4-1714-4e11-8baa-28bccdd88d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37636622817780074903542219005847521264735185497790977266468235678802366999323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rom_ctrl_kmac_err_chk.37636622817780074903542219005847521264735185497790977266468235678802366999323
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.86410146905162972398316793170383347254312040125973032861289035455264340640590
Short name T183
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.18 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:51:39 PM PDT 23
Peak memory 211212 kb
Host smart-5eb355a3-8a7e-4f8f-998e-45c1f2ef9712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86410146905162972398316793170383347254312040125973032861289035455264340640590 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.86410146905162972398316793170383347254312040125973032861289035455264340640590
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.21377403237144929752217005945792821609998846162819265418257445690850296034565
Short name T271
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.28 seconds
Started Oct 25 01:51:12 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 212836 kb
Host smart-d274735a-6c20-4010-984f-fd04566b9851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21377403237144929752217005945792821609998846162819265418257445690850296034565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_smoke.21377403237144929752217005945792821609998846162819265418257445690850296034565
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.53340913733252963207776253977212255532598752749393955018226732991633332786440
Short name T236
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.16 seconds
Started Oct 25 01:51:23 PM PDT 23
Finished Oct 25 01:52:07 PM PDT 23
Peak memory 212936 kb
Host smart-f68b5e75-f37a-43ff-a3aa-44460df17b0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533409137332529632077762539772122555325987527493939550182267329
91633332786440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.53340913733252963207776253977212255532598752749393
955018226732991633332786440
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.75691516338954502998143777913766047252543134776566677511655988409766376998934
Short name T186
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 25 01:51:43 PM PDT 23
Finished Oct 25 01:51:56 PM PDT 23
Peak memory 211184 kb
Host smart-b242ab8c-2238-4741-9a7b-2ca4933602b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75691516338954502998143777913766047252543134776566677511655988409766376998934 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.75691516338954502998143777913766047252543134776566677511655988409766376998934
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.44212596168788975874556725723127073541090180700081095966175110165292277106078
Short name T275
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.82 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:57:25 PM PDT 23
Peak memory 237728 kb
Host smart-55bddf29-b366-4bfa-8a7e-f480af57901d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44212596168788975874556725723127073541090180700081095966175110165292277106078 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.442125961687889758745567257231270735410901807000810959661
75110165292277106078
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.11956363103490168492649216061611660966515933701860806742131930202382369295610
Short name T115
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Oct 25 01:51:39 PM PDT 23
Finished Oct 25 01:52:06 PM PDT 23
Peak memory 211504 kb
Host smart-1e09b6b8-d114-426b-9ff2-7eac3f6c6092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11956363103490168492649216061611660966515933701860806742131930202382369295610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rom_ctrl_kmac_err_chk.11956363103490168492649216061611660966515933701860806742131930202382369295610
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.98473416675407555511832223358191206729914559912780239973937228457734062455653
Short name T144
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Oct 25 01:51:30 PM PDT 23
Finished Oct 25 01:51:44 PM PDT 23
Peak memory 211028 kb
Host smart-d2b26921-f087-42f6-826e-05aeb05732f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98473416675407555511832223358191206729914559912780239973937228457734062455653 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.98473416675407555511832223358191206729914559912780239973937228457734062455653
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.74753741705535599408983556472447814823709975572417665317145899352127486331813
Short name T3
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.13 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:51:56 PM PDT 23
Peak memory 212936 kb
Host smart-207d7d9a-8e12-47e5-934d-5475318c9ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74753741705535599408983556472447814823709975572417665317145899352127486331813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_smoke.74753741705535599408983556472447814823709975572417665317145899352127486331813
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.22917176844765367815529121708442274608863510560970198508624527492836266987435
Short name T250
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.76 seconds
Started Oct 25 01:51:44 PM PDT 23
Finished Oct 25 01:52:26 PM PDT 23
Peak memory 212760 kb
Host smart-4a8cc687-4ce0-4edd-9ddc-dc5da4a46cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229171768447653678155291217084422746088635105609701985086245274
92836266987435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.22917176844765367815529121708442274608863510560970
198508624527492836266987435
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1398731985242406828054610693207388981117654061272280515635903653753914312680
Short name T337
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211128 kb
Host smart-2908b57d-b861-4b4d-9092-ea44606687b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398731985242406828054610693207388981117654061272280515635903653753914312680 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1398731985242406828054610693207388981117654061272280515635903653753914312680
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.94066895027595238429901481499988845515577527997007388333547510003305055518623
Short name T40
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.52 seconds
Started Oct 25 01:51:46 PM PDT 23
Finished Oct 25 01:57:23 PM PDT 23
Peak memory 237608 kb
Host smart-eba13af4-f19d-4ccc-8c3e-dc0b4b486806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94066895027595238429901481499988845515577527997007388333547510003305055518623 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.940668950275952384299014814999888455155775279970073883335
47510003305055518623
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.75325890024136386773121317059731242751852243022367154271696587816227289485788
Short name T143
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.38 seconds
Started Oct 25 01:51:49 PM PDT 23
Finished Oct 25 01:52:15 PM PDT 23
Peak memory 211532 kb
Host smart-d0e8bffa-ec56-4af1-bb05-dab5f34d12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75325890024136386773121317059731242751852243022367154271696587816227289485788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rom_ctrl_kmac_err_chk.75325890024136386773121317059731242751852243022367154271696587816227289485788
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.5016402856824862855948968879022613279801834044282975699727843451890840342006
Short name T260
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:51:59 PM PDT 23
Peak memory 211228 kb
Host smart-66bc4900-f4b1-4a8c-9d9e-b2c9d4b41e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5016402856824862855948968879022613279801834044282975699727843451890840342006 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.5016402856824862855948968879022613279801834044282975699727843451890840342006
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.61572653659569545026216136415161476036939275352612829490043181640636369277580
Short name T325
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.05 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:52:11 PM PDT 23
Peak memory 212852 kb
Host smart-3d5e113a-2a68-475f-99f0-0ebb31990b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61572653659569545026216136415161476036939275352612829490043181640636369277580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_smoke.61572653659569545026216136415161476036939275352612829490043181640636369277580
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.644979349778237151155993327809143792496466153081283214223565161736579391649
Short name T118
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.8 seconds
Started Oct 25 01:51:41 PM PDT 23
Finished Oct 25 01:52:25 PM PDT 23
Peak memory 212992 kb
Host smart-3e453c18-fb69-4379-8a75-018caf44ff8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644979349778237151155993327809143792496466153081283214223565161
736579391649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.6449793497782371511559933278091437924964661530812832
14223565161736579391649
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.61795156961383644444969339025592979712389851491328415645849822342300849477347
Short name T169
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.4 seconds
Started Oct 25 01:51:49 PM PDT 23
Finished Oct 25 01:52:02 PM PDT 23
Peak memory 211092 kb
Host smart-c269ae55-141f-4b56-bf94-19f895f3bf1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61795156961383644444969339025592979712389851491328415645849822342300849477347 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.61795156961383644444969339025592979712389851491328415645849822342300849477347
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.36795176666423916739977687693751021633749620308284747188767760269586053960219
Short name T36
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.8 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:57:28 PM PDT 23
Peak memory 237624 kb
Host smart-3f37451d-b3d6-4ffa-ac99-055682ffdda2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36795176666423916739977687693751021633749620308284747188767760269586053960219 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.367951766664239167399776876937510216337496203082847471887
67760269586053960219
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.56534613107955738652041580103541025169998612872011430437867953261729272174064
Short name T333
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.06 seconds
Started Oct 25 01:51:50 PM PDT 23
Finished Oct 25 01:52:16 PM PDT 23
Peak memory 211592 kb
Host smart-8065ccc2-3cef-40b6-863c-c541242db701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56534613107955738652041580103541025169998612872011430437867953261729272174064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rom_ctrl_kmac_err_chk.56534613107955738652041580103541025169998612872011430437867953261729272174064
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.41159401433570963339736974888406594036464123648012559613761329096203010999486
Short name T272
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Oct 25 01:51:44 PM PDT 23
Finished Oct 25 01:51:58 PM PDT 23
Peak memory 211084 kb
Host smart-04a82a12-52dd-4a71-a533-bc6642733061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41159401433570963339736974888406594036464123648012559613761329096203010999486 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.41159401433570963339736974888406594036464123648012559613761329096203010999486
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.94150078992633959466945506527455512310962966758331285589193719892672695014951
Short name T101
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.91 seconds
Started Oct 25 01:51:55 PM PDT 23
Finished Oct 25 01:52:24 PM PDT 23
Peak memory 212676 kb
Host smart-7c407740-ec95-48bc-b5a9-0db658b5acdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94150078992633959466945506527455512310962966758331285589193719892672695014951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.94150078992633959466945506527455512310962966758331285589193719892672695014951
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.56670136160539353936154405278512616268258041456074308581921443559803817946356
Short name T223
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.29 seconds
Started Oct 25 01:51:54 PM PDT 23
Finished Oct 25 01:52:37 PM PDT 23
Peak memory 212776 kb
Host smart-be9e1632-8340-45e6-9b42-85c11b7291be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566701361605393539361544052785126162682580414560743085819214435
59803817946356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.56670136160539353936154405278512616268258041456074
308581921443559803817946356
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.9999635883864010695488152932134727432318961423509215516189277537717373461600
Short name T219
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.07 seconds
Started Oct 25 01:52:56 PM PDT 23
Finished Oct 25 01:53:09 PM PDT 23
Peak memory 211028 kb
Host smart-90623a89-dea6-40f2-8a92-091eedfc2231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9999635883864010695488152932134727432318961423509215516189277537717373461600 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.9999635883864010695488152932134727432318961423509215516189277537717373461600
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.100043281091613023265014981587368704408237830057622899948912134338906705409668
Short name T206
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.9 seconds
Started Oct 25 01:51:56 PM PDT 23
Finished Oct 25 01:57:35 PM PDT 23
Peak memory 237648 kb
Host smart-a9a6b513-bb12-41ac-b33d-295b1e714448
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100043281091613023265014981587368704408237830057622899948912134338906705409668 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.10004328109161302326501498158736870440823783005762289994
8912134338906705409668
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.12851808635975588868058705860932179336798189633068357862455626242280266816340
Short name T164
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.67 seconds
Started Oct 25 01:51:49 PM PDT 23
Finished Oct 25 01:52:15 PM PDT 23
Peak memory 211592 kb
Host smart-c1170eca-3736-4788-be88-b4f03d529d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12851808635975588868058705860932179336798189633068357862455626242280266816340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rom_ctrl_kmac_err_chk.12851808635975588868058705860932179336798189633068357862455626242280266816340
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.115423397481446149308616683293765857507983827046244646175205517552030170818705
Short name T211
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.41 seconds
Started Oct 25 01:52:40 PM PDT 23
Finished Oct 25 01:52:54 PM PDT 23
Peak memory 208904 kb
Host smart-89047f34-a6ef-4e3b-b237-0961d46ecc9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115423397481446149308616683293765857507983827046244646175205517552030170818705 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.115423397481446149308616683293765857507983827046244646175205517552030170818705
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.73483456556540705631352078899372544568022384021559146756602313645680975236114
Short name T151
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.95 seconds
Started Oct 25 01:51:52 PM PDT 23
Finished Oct 25 01:52:20 PM PDT 23
Peak memory 212748 kb
Host smart-bbfed4cf-02b7-45ec-a675-2798e2a750e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73483456556540705631352078899372544568022384021559146756602313645680975236114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.73483456556540705631352078899372544568022384021559146756602313645680975236114
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.72151006196578261192966027104527976067110328087366437004699695979249813419762
Short name T104
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.17 seconds
Started Oct 25 01:51:55 PM PDT 23
Finished Oct 25 01:52:38 PM PDT 23
Peak memory 212788 kb
Host smart-b3415b56-f42b-47a6-92ab-de8f16a19f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721510061965782611929660271045279760671103280873664370046996959
79249813419762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.72151006196578261192966027104527976067110328087366
437004699695979249813419762
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.56026981432214793510185452117353614500435695239434376998207743559568046708413
Short name T131
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:10 PM PDT 23
Peak memory 211196 kb
Host smart-8c9bb9dd-ba4b-4f1f-8280-d32bea6da34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56026981432214793510185452117353614500435695239434376998207743559568046708413 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.56026981432214793510185452117353614500435695239434376998207743559568046708413
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.59323329983652751143789419572735246295252176514661505573590799686002534111515
Short name T141
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.75 seconds
Started Oct 25 01:51:54 PM PDT 23
Finished Oct 25 01:57:35 PM PDT 23
Peak memory 237672 kb
Host smart-31ee3517-68b6-41da-8a3d-c1f2a20d4778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59323329983652751143789419572735246295252176514661505573590799686002534111515 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.593233299836527511437894195727352462952521765146615055735
90799686002534111515
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.4588337934942629032703737582383272743628365700905244292249585135237418830431
Short name T179
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:50:54 PM PDT 23
Finished Oct 25 01:51:20 PM PDT 23
Peak memory 211752 kb
Host smart-fba549d8-7685-439b-8e56-0a50a5423070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4588337934942629032703737582383272743628365700905244292249585135237418830431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.rom_ctrl_kmac_err_chk.4588337934942629032703737582383272743628365700905244292249585135237418830431
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.44686282498600432837988570848567846545694389790502300038780100361575146324147
Short name T357
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.14 seconds
Started Oct 25 01:52:40 PM PDT 23
Finished Oct 25 01:52:54 PM PDT 23
Peak memory 209304 kb
Host smart-27354116-fdab-4100-94f9-1168d4ccf886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44686282498600432837988570848567846545694389790502300038780100361575146324147 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.44686282498600432837988570848567846545694389790502300038780100361575146324147
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.26160357703721006472027543064061128824967302130414325705714517219996920697182
Short name T121
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.8 seconds
Started Oct 25 01:51:47 PM PDT 23
Finished Oct 25 01:52:15 PM PDT 23
Peak memory 212676 kb
Host smart-b701c772-61a9-4883-bfc1-1140d66e1caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26160357703721006472027543064061128824967302130414325705714517219996920697182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.rom_ctrl_smoke.26160357703721006472027543064061128824967302130414325705714517219996920697182
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.97508069719171235274725196853860467046299177805501825184797063684360645014152
Short name T99
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.53 seconds
Started Oct 25 01:51:51 PM PDT 23
Finished Oct 25 01:52:34 PM PDT 23
Peak memory 212856 kb
Host smart-523dee91-c7e5-46b6-8e2f-37c209bfe078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975080697191712352747251968538604670462991778055018251847970636
84360645014152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.97508069719171235274725196853860467046299177805501
825184797063684360645014152
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.63292086507979692709109199344663387353778422785510477060903482788573092870514
Short name T29
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Oct 25 01:50:19 PM PDT 23
Finished Oct 25 01:50:32 PM PDT 23
Peak memory 211236 kb
Host smart-19a8e760-21b1-403f-97e4-d856684210dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63292086507979692709109199344663387353778422785510477060903482788573092870514 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.63292086507979692709109199344663387353778422785510477060903482788573092870514
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.18730310428059470889917242453430368966930759746274249636137543700426492502195
Short name T265
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.53 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:50:48 PM PDT 23
Peak memory 211580 kb
Host smart-83facaf6-7464-4725-93ee-46f1bc0bfb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18730310428059470889917242453430368966930759746274249636137543700426492502195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rom_ctrl_kmac_err_chk.18730310428059470889917242453430368966930759746274249636137543700426492502195
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.107460538984233669379849052559517732635984366181434094634502922003638910085435
Short name T120
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 25 01:50:55 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 211124 kb
Host smart-61803196-4723-4d34-a13c-1df00ba47d6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107460538984233669379849052559517732635984366181434094634502922003638910085435 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.107460538984233669379849052559517732635984366181434094634502922003638910085435
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.63942563724520040826089672952551467422527671684006186640160756981000545780860
Short name T28
Test name
Test status
Simulation time 3444857586 ps
CPU time 115.17 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:52:17 PM PDT 23
Peak memory 236812 kb
Host smart-0062a584-fa14-4394-908d-7dbc7f07f7d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63942563724520040826089672952551467422527671684006186640160756981000545780860 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.63942563724520040826089672952551467422527671684006186640160756981000545780860
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.24475211325984562897841771820404425777967895225877003342622861822360535961367
Short name T215
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.46 seconds
Started Oct 25 01:50:48 PM PDT 23
Finished Oct 25 01:51:17 PM PDT 23
Peak memory 212840 kb
Host smart-9599fa58-cc6c-4025-9474-b9ac11e365b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24475211325984562897841771820404425777967895225877003342622861822360535961367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.rom_ctrl_smoke.24475211325984562897841771820404425777967895225877003342622861822360535961367
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.26906984201486195767590566455592948962878238042362452373500918716336223036363
Short name T224
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.55 seconds
Started Oct 25 01:50:47 PM PDT 23
Finished Oct 25 01:51:30 PM PDT 23
Peak memory 212784 kb
Host smart-9694bf0a-d480-49da-b9ba-9cb32253e0dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269069842014861957675905664555929489628782380423624523735009187
16336223036363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.269069842014861957675905664555929489628782380423624
52373500918716336223036363
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.37158042955134838124186164317901626593503187608967296843546772149572107086210
Short name T187
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Oct 25 01:51:13 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 211152 kb
Host smart-47da151f-67d8-4945-b6e8-9204bbb18c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37158042955134838124186164317901626593503187608967296843546772149572107086210 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.37158042955134838124186164317901626593503187608967296843546772149572107086210
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.88154206387201476112688042999355307694276500274519502226041574451571215146653
Short name T267
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.46 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:57:10 PM PDT 23
Peak memory 237696 kb
Host smart-b0ae9cf4-2eba-41fc-bfaf-07dfce0dc3aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88154206387201476112688042999355307694276500274519502226041574451571215146653 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.881542063872014761126880429993553076942765002745195022260
41574451571215146653
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.98439406222991499777497598681107125408461369657681032813114742702955479020530
Short name T262
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.09 seconds
Started Oct 25 01:51:08 PM PDT 23
Finished Oct 25 01:51:34 PM PDT 23
Peak memory 211436 kb
Host smart-be301620-81e9-432b-8b78-7a874566a900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98439406222991499777497598681107125408461369657681032813114742702955479020530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rom_ctrl_kmac_err_chk.98439406222991499777497598681107125408461369657681032813114742702955479020530
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.91673046129464985904573047524024264572285987143601639905607942117835105237277
Short name T302
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.18 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:10 PM PDT 23
Peak memory 211084 kb
Host smart-28e59cbf-c565-4b7d-b7ec-33ce1573e73b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91673046129464985904573047524024264572285987143601639905607942117835105237277 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.91673046129464985904573047524024264572285987143601639905607942117835105237277
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.46784278142847055233365974571312048031917326293259039466244663450185045286918
Short name T210
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.29 seconds
Started Oct 25 01:51:12 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 212848 kb
Host smart-2152888f-ddf9-4de8-a756-3d1850973723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46784278142847055233365974571312048031917326293259039466244663450185045286918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_smoke.46784278142847055233365974571312048031917326293259039466244663450185045286918
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.114135298173855904244627755513784139599060593231957847327509235929807770069918
Short name T229
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.05 seconds
Started Oct 25 01:51:16 PM PDT 23
Finished Oct 25 01:51:59 PM PDT 23
Peak memory 212852 kb
Host smart-6101fbaf-a918-478a-8526-c0ee6e26c762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114135298173855904244627755513784139599060593231957847327509235
929807770069918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.1141352981738559042446277555137841395990605932319
57847327509235929807770069918
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.64479784201662158440237308363272486020896700253189994662744771179685831116053
Short name T294
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 25 01:51:46 PM PDT 23
Finished Oct 25 01:51:59 PM PDT 23
Peak memory 211228 kb
Host smart-a3a7382e-d563-4132-9b6f-6c63933333d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64479784201662158440237308363272486020896700253189994662744771179685831116053 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.64479784201662158440237308363272486020896700253189994662744771179685831116053
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.14150120653661899054334097394604784484880214542768660885319633807907739413705
Short name T152
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.8 seconds
Started Oct 25 01:51:23 PM PDT 23
Finished Oct 25 01:57:08 PM PDT 23
Peak memory 237664 kb
Host smart-6b4d21e7-3d73-4567-bfd7-e10f9b64fb98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150120653661899054334097394604784484880214542768660885319633807907739413705 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.141501206536618990543340973946047844848802145427686608853
19633807907739413705
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.21405805242040844935805152668897570718778913104930080360404850855457338812574
Short name T166
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:51:31 PM PDT 23
Finished Oct 25 01:51:58 PM PDT 23
Peak memory 211624 kb
Host smart-69b8fde3-8ac9-4a7a-ad6e-bcce439b62f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21405805242040844935805152668897570718778913104930080360404850855457338812574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.rom_ctrl_kmac_err_chk.21405805242040844935805152668897570718778913104930080360404850855457338812574
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.106948800727821556419885161970865454554962896595278564743702804870904994612821
Short name T130
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.13 seconds
Started Oct 25 01:51:20 PM PDT 23
Finished Oct 25 01:51:33 PM PDT 23
Peak memory 211264 kb
Host smart-ec445c5d-437d-439f-8eb4-6f000749f617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106948800727821556419885161970865454554962896595278564743702804870904994612821 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.106948800727821556419885161970865454554962896595278564743702804870904994612821
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.75910057186160308235226408097474453548204271207871129790509000775533143095444
Short name T269
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.58 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:51:53 PM PDT 23
Peak memory 212932 kb
Host smart-82355aee-3580-4506-8884-f038e5899dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75910057186160308235226408097474453548204271207871129790509000775533143095444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.rom_ctrl_smoke.75910057186160308235226408097474453548204271207871129790509000775533143095444
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.112344532681046166303360062203489453305291591948582484163192902761198741510898
Short name T214
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.97 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:40 PM PDT 23
Peak memory 212984 kb
Host smart-b3879f0b-40fc-4fb4-9725-88e08c8cb14b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112344532681046166303360062203489453305291591948582484163192902
761198741510898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.1123445326810461663033600622034894533052915919485
82484163192902761198741510898
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.106674625879119593918498454556267748542601381805643937087934290368654112911397
Short name T280
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.01 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:51:58 PM PDT 23
Peak memory 211020 kb
Host smart-7764188c-58a7-4a33-8a6b-39a5cdaf534c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106674625879119593918498454556267748542601381805643937087934290368654112911397 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.106674625879119593918498454556267748542601381805643937087934290368654112911397
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.72784814663772109180069799592557523630541135513309905109164354682808940022499
Short name T321
Test name
Test status
Simulation time 69854280986 ps
CPU time 347 seconds
Started Oct 25 01:51:38 PM PDT 23
Finished Oct 25 01:57:26 PM PDT 23
Peak memory 237472 kb
Host smart-c5246070-c87d-4dbb-b0dc-6c2fd33a0933
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72784814663772109180069799592557523630541135513309905109164354682808940022499 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.727848146637721091800697995925575236305411355133099051091
64354682808940022499
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.67330475314277210816940250310677440755075653333920422686680410211431820246361
Short name T228
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.83 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:52:09 PM PDT 23
Peak memory 211584 kb
Host smart-4e555c0d-a79f-4984-aae3-193b10226c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67330475314277210816940250310677440755075653333920422686680410211431820246361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.rom_ctrl_kmac_err_chk.67330475314277210816940250310677440755075653333920422686680410211431820246361
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.41852183044252327100329907960152021443081904570654160373230278881099319101287
Short name T74
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.46 seconds
Started Oct 25 01:51:27 PM PDT 23
Finished Oct 25 01:51:41 PM PDT 23
Peak memory 211024 kb
Host smart-4818a687-7b40-4232-8812-051d4d54f5db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41852183044252327100329907960152021443081904570654160373230278881099319101287 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.41852183044252327100329907960152021443081904570654160373230278881099319101287
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.7491678184895086404836404245450614907942390033009683679345333465148390590461
Short name T312
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Oct 25 01:51:31 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 212836 kb
Host smart-959156ca-a496-4294-bc7f-9577eb58ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7491678184895086404836404245450614907942390033009683679345333465148390590461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.rom_ctrl_smoke.7491678184895086404836404245450614907942390033009683679345333465148390590461
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2591256430438153934581805063006831913875347191793726282653175837911028878851
Short name T281
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.74 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:52:24 PM PDT 23
Peak memory 212940 kb
Host smart-0dc39720-12d5-4e88-8a0e-8b152455239d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259125643043815393458180506300683191387534719179372628265317583
7911028878851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.259125643043815393458180506300683191387534719179372
6282653175837911028878851
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.33740355496831770200614469617368576139398204137995538242999219978253454653000
Short name T194
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Oct 25 01:51:47 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211200 kb
Host smart-cb7a4eb7-dc72-44a5-8744-f922232cfb95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33740355496831770200614469617368576139398204137995538242999219978253454653000 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.33740355496831770200614469617368576139398204137995538242999219978253454653000
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.112576740425798989488650343277070923971461083470686477147690675028157030356019
Short name T127
Test name
Test status
Simulation time 69854280986 ps
CPU time 325.65 seconds
Started Oct 25 01:51:40 PM PDT 23
Finished Oct 25 01:57:07 PM PDT 23
Peak memory 237432 kb
Host smart-fda4a4c0-8e0e-4f2f-a802-1e47c8e0ab1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112576740425798989488650343277070923971461083470686477147690675028157030356019 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.11257674042579898948865034327707092397146108347068647714
7690675028157030356019
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.13825765439329901214992244743805399175531409119393822573386675080263126782234
Short name T313
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:52:11 PM PDT 23
Peak memory 211504 kb
Host smart-34e1f14d-c4f7-42c1-9101-eec02928ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13825765439329901214992244743805399175531409119393822573386675080263126782234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.13825765439329901214992244743805399175531409119393822573386675080263126782234
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.70928662011783340614130103990624815311870916446644977536215738221376447308240
Short name T133
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.57 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:51:56 PM PDT 23
Peak memory 211212 kb
Host smart-6132e331-69c3-4f52-a7ab-760074dab360
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=70928662011783340614130103990624815311870916446644977536215738221376447308240 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.70928662011783340614130103990624815311870916446644977536215738221376447308240
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.104023232910459049559596369840165293146888694135928729181739951026427013102570
Short name T145
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.94 seconds
Started Oct 25 01:51:42 PM PDT 23
Finished Oct 25 01:52:11 PM PDT 23
Peak memory 212756 kb
Host smart-a946fc09-e97c-4af4-8a46-dd595cf075eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104023232910459049559596369840165293146888694135928729181739951026427013102570 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.rom_ctrl_smoke.104023232910459049559596369840165293146888694135928729181739951026427013102570
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.71120706910535472878152454037831300426892354034816257112283107658134634371151
Short name T241
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.03 seconds
Started Oct 25 01:51:41 PM PDT 23
Finished Oct 25 01:52:25 PM PDT 23
Peak memory 212916 kb
Host smart-4a43a2cd-589e-4f8c-a3d7-e877ad2c84ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711207069105354728781524540378313004268923540348162571122831076
58134634371151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.71120706910535472878152454037831300426892354034816
257112283107658134634371151
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.63560171142528705803541845768372990045609764045312545776117201961384058866751
Short name T227
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.37 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:52:01 PM PDT 23
Peak memory 211000 kb
Host smart-20ab4faf-7a87-44c4-a211-c41030329dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63560171142528705803541845768372990045609764045312545776117201961384058866751 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.63560171142528705803541845768372990045609764045312545776117201961384058866751
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.44956400113598618904170452707504959488378326920073024994047781312671088944210
Short name T173
Test name
Test status
Simulation time 69854280986 ps
CPU time 327.4 seconds
Started Oct 25 01:51:48 PM PDT 23
Finished Oct 25 01:57:16 PM PDT 23
Peak memory 237560 kb
Host smart-50274795-32ce-498c-9308-5f1448d504a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44956400113598618904170452707504959488378326920073024994047781312671088944210 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.449564001135986189041704527075049594883783269200730249940
47781312671088944210
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.55023511958357416762469391341356421242775455853766814930781549247544600773413
Short name T343
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Oct 25 01:51:47 PM PDT 23
Finished Oct 25 01:52:13 PM PDT 23
Peak memory 211452 kb
Host smart-edf4cb3c-b017-4b67-a17d-72917d7611f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55023511958357416762469391341356421242775455853766814930781549247544600773413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rom_ctrl_kmac_err_chk.55023511958357416762469391341356421242775455853766814930781549247544600773413
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3638698177435783339319235215120796049204201231542278596257426959916253627743
Short name T158
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.05 seconds
Started Oct 25 01:51:44 PM PDT 23
Finished Oct 25 01:51:57 PM PDT 23
Peak memory 211084 kb
Host smart-ac1e067b-49ac-40ba-a618-9cc23f93e986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3638698177435783339319235215120796049204201231542278596257426959916253627743 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3638698177435783339319235215120796049204201231542278596257426959916253627743
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.42836777582473870772706966975953533677418688925600969011705648579198922856238
Short name T73
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.86 seconds
Started Oct 25 01:51:47 PM PDT 23
Finished Oct 25 01:52:17 PM PDT 23
Peak memory 212836 kb
Host smart-1ed46218-dc99-4678-ad92-d5c9ce3410b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42836777582473870772706966975953533677418688925600969011705648579198922856238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.rom_ctrl_smoke.42836777582473870772706966975953533677418688925600969011705648579198922856238
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.38210686523852179226203772703057606724223690101628934537108961972096652276376
Short name T232
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.87 seconds
Started Oct 25 01:51:51 PM PDT 23
Finished Oct 25 01:52:35 PM PDT 23
Peak memory 212740 kb
Host smart-fcecc384-280a-4895-b1f1-794fd4b11af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382106865238521792262037727030576067242236901016289345371089619
72096652276376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.38210686523852179226203772703057606724223690101628
934537108961972096652276376
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.49135192142813418228511174903443069348965897216031672465658587956682376673011
Short name T347
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.67 seconds
Started Oct 25 01:51:52 PM PDT 23
Finished Oct 25 01:52:05 PM PDT 23
Peak memory 211096 kb
Host smart-cc0deaec-b307-4314-ae6b-8f589222a135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49135192142813418228511174903443069348965897216031672465658587956682376673011 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.49135192142813418228511174903443069348965897216031672465658587956682376673011
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.87237950261150232056304665944155190611183568943224778154587796556734354202504
Short name T41
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.16 seconds
Started Oct 25 01:51:52 PM PDT 23
Finished Oct 25 01:57:26 PM PDT 23
Peak memory 237580 kb
Host smart-c32eb6e5-5fc1-468e-8988-bbbd3f08d42e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87237950261150232056304665944155190611183568943224778154587796556734354202504 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.872379502611502320563046659441551906111835689432247781545
87796556734354202504
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.45419952464987630309392180929751625628838982392157992957990572482619409127390
Short name T195
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.61 seconds
Started Oct 25 01:51:55 PM PDT 23
Finished Oct 25 01:52:21 PM PDT 23
Peak memory 211332 kb
Host smart-de8fbff0-cb00-481b-9c41-0e167056076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45419952464987630309392180929751625628838982392157992957990572482619409127390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rom_ctrl_kmac_err_chk.45419952464987630309392180929751625628838982392157992957990572482619409127390
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.71551135054728754911777903060845727253004884497095871438221753189232802104997
Short name T79
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 25 01:51:55 PM PDT 23
Finished Oct 25 01:52:09 PM PDT 23
Peak memory 211004 kb
Host smart-91e39e1b-50b6-4382-be8e-1bf44626b58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71551135054728754911777903060845727253004884497095871438221753189232802104997 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.71551135054728754911777903060845727253004884497095871438221753189232802104997
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.72627389979393219812665314848985325441698885108523076429399442138515134199914
Short name T216
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Oct 25 01:51:49 PM PDT 23
Finished Oct 25 01:52:18 PM PDT 23
Peak memory 212840 kb
Host smart-0ac05d18-2e24-4612-b0a3-9f05224c8b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72627389979393219812665314848985325441698885108523076429399442138515134199914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.72627389979393219812665314848985325441698885108523076429399442138515134199914
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.5547339059325445318213609304364526509885501975686308920128771305057780165355
Short name T2
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.44 seconds
Started Oct 25 01:51:55 PM PDT 23
Finished Oct 25 01:52:37 PM PDT 23
Peak memory 212736 kb
Host smart-6c3e20aa-f868-474c-965c-9077c23da649
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554733905932544531821360930436452650988550197568630892012877130
5057780165355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.554733905932544531821360930436452650988550197568630
8920128771305057780165355
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.82131926670691535814666308308326971516390755031606184634302023955481203347079
Short name T344
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.62 seconds
Started Oct 25 01:50:56 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 211316 kb
Host smart-66ad1662-1b84-42b5-b1ca-8e9e848f0929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82131926670691535814666308308326971516390755031606184634302023955481203347079 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.82131926670691535814666308308326971516390755031606184634302023955481203347079
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.93392769013924619712722627304827901939253224114063714258638768002138408174992
Short name T174
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.05 seconds
Started Oct 25 01:52:40 PM PDT 23
Finished Oct 25 01:58:12 PM PDT 23
Peak memory 235944 kb
Host smart-f7b8d78f-14e9-464c-a962-8423ce8b97ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93392769013924619712722627304827901939253224114063714258638768002138408174992 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.933927690139246197127226273048279019392532241140637142586
38768002138408174992
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.83702548070830791850988412360116818498173717348674249398468275451221132580867
Short name T291
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 25 01:51:53 PM PDT 23
Finished Oct 25 01:52:21 PM PDT 23
Peak memory 211524 kb
Host smart-78146682-034a-4b9c-8543-50fd93c2be28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83702548070830791850988412360116818498173717348674249398468275451221132580867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rom_ctrl_kmac_err_chk.83702548070830791850988412360116818498173717348674249398468275451221132580867
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.28187474508612251868779949410510123376080903826672323528706991794602582474355
Short name T159
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 25 01:52:40 PM PDT 23
Finished Oct 25 01:52:54 PM PDT 23
Peak memory 209048 kb
Host smart-2a95e34d-7a27-4028-9977-8740aca341d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28187474508612251868779949410510123376080903826672323528706991794602582474355 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.28187474508612251868779949410510123376080903826672323528706991794602582474355
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.84624156404161748887407614111180488369043912044280484947726842357179869812364
Short name T310
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.28 seconds
Started Oct 25 01:51:52 PM PDT 23
Finished Oct 25 01:52:20 PM PDT 23
Peak memory 212820 kb
Host smart-f747a760-afe7-4145-8a61-4e7bf7819238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84624156404161748887407614111180488369043912044280484947726842357179869812364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_smoke.84624156404161748887407614111180488369043912044280484947726842357179869812364
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.81081392934620608960177772226930666065185248664146206825944801194767067576917
Short name T331
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.87 seconds
Started Oct 25 01:51:52 PM PDT 23
Finished Oct 25 01:52:36 PM PDT 23
Peak memory 212856 kb
Host smart-52430900-10ea-4ff3-8f57-bcea0d609720
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810813929346206089601777722269306660651852486641462068259448011
94767067576917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.81081392934620608960177772226930666065185248664146
206825944801194767067576917
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.43394549795112930829440534378082796472329872573797835696134907463650544862477
Short name T253
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 25 01:51:08 PM PDT 23
Finished Oct 25 01:51:21 PM PDT 23
Peak memory 210904 kb
Host smart-592652f5-a6a1-47b0-a03c-92cf3d74d2b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43394549795112930829440534378082796472329872573797835696134907463650544862477 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.43394549795112930829440534378082796472329872573797835696134907463650544862477
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.74154160383439238366445679466676014782442875033397243473600501524216351024081
Short name T352
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.11 seconds
Started Oct 25 01:51:12 PM PDT 23
Finished Oct 25 01:56:56 PM PDT 23
Peak memory 237700 kb
Host smart-720fa9eb-a892-46d0-b336-f1681adbfa1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74154160383439238366445679466676014782442875033397243473600501524216351024081 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.741541603834392383664456794666760147824428750333972434736
00501524216351024081
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.109381942560824735157860987062892162405387851223929717008052599516265142987127
Short name T282
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.87 seconds
Started Oct 25 01:51:00 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 211508 kb
Host smart-670e71aa-d0b3-4630-b33c-3ebb45ac7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109381942560824735157860987062892162405387851223929717008052599516265142987127 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.rom_ctrl_kmac_err_chk.109381942560824735157860987062892162405387851223929717008052599516265142987127
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.94243774245578651752355745629782695804584436177059990224715021969835394623848
Short name T203
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.16 seconds
Started Oct 25 01:51:15 PM PDT 23
Finished Oct 25 01:51:29 PM PDT 23
Peak memory 211052 kb
Host smart-9bc8af32-f209-4adf-ab57-6d92b9fda304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94243774245578651752355745629782695804584436177059990224715021969835394623848 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.94243774245578651752355745629782695804584436177059990224715021969835394623848
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.4478726993762203813989832877544789122369081726189175384516885107308970753423
Short name T125
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.99 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:26 PM PDT 23
Peak memory 212836 kb
Host smart-01dd8a52-14af-49d4-9655-fd035731a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4478726993762203813989832877544789122369081726189175384516885107308970753423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.rom_ctrl_smoke.4478726993762203813989832877544789122369081726189175384516885107308970753423
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.64959111839931508700586959220987599230339755080451057567219471124470306588391
Short name T274
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.05 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:52:09 PM PDT 23
Peak memory 212952 kb
Host smart-cafd0d64-64cb-49a3-9933-ef71aa7bff02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649591118399315087005869592209875992303397550804510575672194711
24470306588391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.64959111839931508700586959220987599230339755080451
057567219471124470306588391
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.112847608987635943994058454484891456239330005535347774394424710573780060246630
Short name T38
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:51:38 PM PDT 23
Peak memory 211108 kb
Host smart-b23f00dc-1f9a-43ca-82f2-6caa94f5ecd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112847608987635943994058454484891456239330005535347774394424710573780060246630 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.112847608987635943994058454484891456239330005535347774394424710573780060246630
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.56291985260356648693384351087876412343450022743405173268019283817997419803441
Short name T135
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.01 seconds
Started Oct 25 01:51:21 PM PDT 23
Finished Oct 25 01:57:03 PM PDT 23
Peak memory 237756 kb
Host smart-af524372-afad-4bd4-b30f-04b29d789ac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56291985260356648693384351087876412343450022743405173268019283817997419803441 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.562919852603566486933843510878764123434500227434051732680
19283817997419803441
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.61463797421317799855906190868583804879728818097650865541101359202956007122922
Short name T139
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.28 seconds
Started Oct 25 01:51:25 PM PDT 23
Finished Oct 25 01:51:50 PM PDT 23
Peak memory 211528 kb
Host smart-7a9b4bb9-4744-48cf-8d5f-b58788376a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61463797421317799855906190868583804879728818097650865541101359202956007122922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.61463797421317799855906190868583804879728818097650865541101359202956007122922
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.115697888519955528321490460135215541491569994851420393446258710418634485160325
Short name T350
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.49 seconds
Started Oct 25 01:51:28 PM PDT 23
Finished Oct 25 01:51:42 PM PDT 23
Peak memory 211292 kb
Host smart-06d1e264-2d97-4a3d-a407-6412e3b9bb9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115697888519955528321490460135215541491569994851420393446258710418634485160325 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.115697888519955528321490460135215541491569994851420393446258710418634485160325
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.69535351291618070966652986343207943067309166555700178596770026322908452961647
Short name T77
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.83 seconds
Started Oct 25 01:50:57 PM PDT 23
Finished Oct 25 01:51:25 PM PDT 23
Peak memory 212840 kb
Host smart-c1d464fa-ed4c-49df-8eb5-2d1eeecfe106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69535351291618070966652986343207943067309166555700178596770026322908452961647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.69535351291618070966652986343207943067309166555700178596770026322908452961647
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.18017080676880097917372923379904976918643284910553443799958441005370587025005
Short name T201
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.8 seconds
Started Oct 25 01:51:08 PM PDT 23
Finished Oct 25 01:51:52 PM PDT 23
Peak memory 212652 kb
Host smart-8289b68c-b711-4991-9938-71d11764c840
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180170806768800979173729233799049769186432849105534437999584410
05370587025005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.18017080676880097917372923379904976918643284910553
443799958441005370587025005
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.10686243240482238408824326483936960802127386321579351385548899877994354820831
Short name T30
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 25 01:51:30 PM PDT 23
Finished Oct 25 01:51:42 PM PDT 23
Peak memory 211024 kb
Host smart-ea38f002-e5cf-4fd0-8363-ba75aa54db95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686243240482238408824326483936960802127386321579351385548899877994354820831 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.10686243240482238408824326483936960802127386321579351385548899877994354820831
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.18681495690304220901172155258012004073863741852332627868426250651558010118990
Short name T198
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.75 seconds
Started Oct 25 01:51:03 PM PDT 23
Finished Oct 25 01:56:43 PM PDT 23
Peak memory 237692 kb
Host smart-c8a977c0-f3e9-400d-8d96-5109e60eea74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18681495690304220901172155258012004073863741852332627868426250651558010118990 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.186814956903042209011721552580120040738637418523326278684
26250651558010118990
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.69681044230927635623846089131886143582484802450287391984052849504486865158094
Short name T6
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.85 seconds
Started Oct 25 01:51:45 PM PDT 23
Finished Oct 25 01:52:12 PM PDT 23
Peak memory 211520 kb
Host smart-2c702d06-1131-4365-ae9a-ead7edc3c02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69681044230927635623846089131886143582484802450287391984052849504486865158094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.rom_ctrl_kmac_err_chk.69681044230927635623846089131886143582484802450287391984052849504486865158094
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.39146776310723939150102288309153411934943411962634363395426355136268797065042
Short name T314
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Oct 25 01:51:38 PM PDT 23
Finished Oct 25 01:51:52 PM PDT 23
Peak memory 211212 kb
Host smart-91f582ef-fbb3-4dcc-87fd-b60b3720212e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39146776310723939150102288309153411934943411962634363395426355136268797065042 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.39146776310723939150102288309153411934943411962634363395426355136268797065042
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.6629690280231634162646351451872138855269194714877922757207113623023825107622
Short name T116
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.13 seconds
Started Oct 25 01:51:24 PM PDT 23
Finished Oct 25 01:51:53 PM PDT 23
Peak memory 212752 kb
Host smart-65724efc-8519-44f4-a7fa-c69cfa40cc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6629690280231634162646351451872138855269194714877922757207113623023825107622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.rom_ctrl_smoke.6629690280231634162646351451872138855269194714877922757207113623023825107622
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.57387158713420160619643765255879691028827040363232148716827035552927550237131
Short name T39
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.47 seconds
Started Oct 25 01:51:19 PM PDT 23
Finished Oct 25 01:52:03 PM PDT 23
Peak memory 212920 kb
Host smart-9c005117-10ef-4c2d-833b-70ea107aa19b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573871587134201606196437652558796910288270403632321487168270355
52927550237131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.57387158713420160619643765255879691028827040363232
148716827035552927550237131
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.101676887876504693477955853829986992865126548948973598243123265518915279985947
Short name T353
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.53 seconds
Started Oct 25 01:50:17 PM PDT 23
Finished Oct 25 01:50:30 PM PDT 23
Peak memory 211080 kb
Host smart-a8e1215b-e247-416a-b43c-83e383014c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101676887876504693477955853829986992865126548948973598243123265518915279985947 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.101676887876504693477955853829986992865126548948973598243123265518915279985947
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.25435520629886520626196196878423333755584562243643681648669847322287137682957
Short name T301
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.08 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:56:05 PM PDT 23
Peak memory 237828 kb
Host smart-38a29e4d-d566-40e2-a325-cd6a9c922698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25435520629886520626196196878423333755584562243643681648669847322287137682957 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.2543552062988652062619619687842333375558456224364368164866
9847322287137682957
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.96047967401340523606771056628705402091876641001623423715079502247796428057678
Short name T284
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.72 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:50:47 PM PDT 23
Peak memory 211516 kb
Host smart-14f0ac81-e50c-4929-afb9-e66ba47dc65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96047967401340523606771056628705402091876641001623423715079502247796428057678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.rom_ctrl_kmac_err_chk.96047967401340523606771056628705402091876641001623423715079502247796428057678
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.112581381028142442577289294789193032981653742516079675515652459690362363471732
Short name T263
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.63 seconds
Started Oct 25 01:50:18 PM PDT 23
Finished Oct 25 01:50:32 PM PDT 23
Peak memory 211164 kb
Host smart-75750c33-66ad-42c6-83d1-4e6cfea6f261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112581381028142442577289294789193032981653742516079675515652459690362363471732 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.112581381028142442577289294789193032981653742516079675515652459690362363471732
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.90798489905397548069075095939318637353689397726729741465189547965385831985983
Short name T204
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.8 seconds
Started Oct 25 01:50:22 PM PDT 23
Finished Oct 25 01:50:51 PM PDT 23
Peak memory 212836 kb
Host smart-5d1d55b4-e7ee-4077-8c78-4ecd31884aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90798489905397548069075095939318637353689397726729741465189547965385831985983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_smoke.90798489905397548069075095939318637353689397726729741465189547965385831985983
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.40660284649736338066453469246809537564567817996529642533607164086033541302841
Short name T218
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.91 seconds
Started Oct 25 01:50:18 PM PDT 23
Finished Oct 25 01:51:01 PM PDT 23
Peak memory 212864 kb
Host smart-a7a47709-4d95-4649-886f-f84c656420cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406602846497363380664534692468095375645678179965296425336071640
86033541302841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.406602846497363380664534692468095375645678179965296
42533607164086033541302841
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.87830252237529712023512694242054162292046727788597523193721684813038403090896
Short name T196
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.7 seconds
Started Oct 25 01:50:38 PM PDT 23
Finished Oct 25 01:50:51 PM PDT 23
Peak memory 211144 kb
Host smart-5ed4d5ef-6341-4ac4-a994-1d2788739a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87830252237529712023512694242054162292046727788597523193721684813038403090896 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.87830252237529712023512694242054162292046727788597523193721684813038403090896
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.80374349210003994999805166967873175906521842811684388506546570964530085866118
Short name T304
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.41 seconds
Started Oct 25 01:50:23 PM PDT 23
Finished Oct 25 01:56:09 PM PDT 23
Peak memory 237708 kb
Host smart-ad50b8d6-b5d7-4b1a-a0b4-dce772b9b75c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80374349210003994999805166967873175906521842811684388506546570964530085866118 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.8037434921000399499980516696787317590652184281168438850654
6570964530085866118
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.70159154820759520841230607254852895346054359056022658220288892472061015014391
Short name T182
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.63 seconds
Started Oct 25 01:50:22 PM PDT 23
Finished Oct 25 01:50:48 PM PDT 23
Peak memory 211632 kb
Host smart-2a44bd30-6a50-4221-bfbe-c5fe606d9adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70159154820759520841230607254852895346054359056022658220288892472061015014391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.rom_ctrl_kmac_err_chk.70159154820759520841230607254852895346054359056022658220288892472061015014391
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.14020198836874579354020117286801213497694311940205057260033972900096968747872
Short name T335
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.62 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:50:35 PM PDT 23
Peak memory 211328 kb
Host smart-f3ad9d70-9d7e-49b1-a912-dfefe0576a32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14020198836874579354020117286801213497694311940205057260033972900096968747872 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.14020198836874579354020117286801213497694311940205057260033972900096968747872
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.79251803801235228013817843661684135115496614164508651067912861280715003250776
Short name T305
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.01 seconds
Started Oct 25 01:50:20 PM PDT 23
Finished Oct 25 01:50:50 PM PDT 23
Peak memory 212844 kb
Host smart-92438c5b-52d5-4208-8f1a-b2188e9e586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79251803801235228013817843661684135115496614164508651067912861280715003250776 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_smoke.79251803801235228013817843661684135115496614164508651067912861280715003250776
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.44118078033437469947609431589917956943447276952686252401562694853142755161251
Short name T110
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.4 seconds
Started Oct 25 01:50:23 PM PDT 23
Finished Oct 25 01:51:07 PM PDT 23
Peak memory 213040 kb
Host smart-197eb52e-cbcb-4003-ae12-e115c7436b1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441180780334374699476094315899179569434472769526862524015626948
53142755161251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.441180780334374699476094315899179569434472769526862
52401562694853142755161251
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.54161823283329701393108836351598717094508330548684767905323405585038302763485
Short name T277
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:50:56 PM PDT 23
Peak memory 211096 kb
Host smart-48c05f51-b6a3-4492-9de2-fafbe9f0bfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54161823283329701393108836351598717094508330548684767905323405585038302763485 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.54161823283329701393108836351598717094508330548684767905323405585038302763485
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.45432419271704332994401262155117116919146093835432865636065182279304063244571
Short name T226
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.79 seconds
Started Oct 25 01:50:20 PM PDT 23
Finished Oct 25 01:55:57 PM PDT 23
Peak memory 237576 kb
Host smart-945508e2-825f-4846-a8ec-057265bfa92f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45432419271704332994401262155117116919146093835432865636065182279304063244571 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.4543241927170433299440126215511711691914609383543286563606
5182279304063244571
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.112085921513153749569304280095811123387857081107524843257003267247992236739509
Short name T278
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Oct 25 01:50:21 PM PDT 23
Finished Oct 25 01:50:47 PM PDT 23
Peak memory 211632 kb
Host smart-ad506488-ec1e-4f4e-bf60-7893341c59ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112085921513153749569304280095811123387857081107524843257003267247992236739509 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.rom_ctrl_kmac_err_chk.112085921513153749569304280095811123387857081107524843257003267247992236739509
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.5968301445629736159520894868438034126577561526439048592215687010808873369039
Short name T78
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Oct 25 01:50:24 PM PDT 23
Finished Oct 25 01:50:38 PM PDT 23
Peak memory 211288 kb
Host smart-9919847c-1c78-4199-a31c-9bc8458fc455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5968301445629736159520894868438034126577561526439048592215687010808873369039 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.5968301445629736159520894868438034126577561526439048592215687010808873369039
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.102082890950273823933029455424411952930413630639627707699314101243291954098594
Short name T124
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.8 seconds
Started Oct 25 01:50:24 PM PDT 23
Finished Oct 25 01:50:53 PM PDT 23
Peak memory 212824 kb
Host smart-c47f54ec-af8f-43ae-b2e6-cc36d3f2712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102082890950273823933029455424411952930413630639627707699314101243291954098594 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.rom_ctrl_smoke.102082890950273823933029455424411952930413630639627707699314101243291954098594
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.34874118263332846408896042770419171471801620293753508100038307568432251978868
Short name T303
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.94 seconds
Started Oct 25 01:50:23 PM PDT 23
Finished Oct 25 01:51:06 PM PDT 23
Peak memory 212964 kb
Host smart-31d87f5a-992c-4608-9846-978f9b7a40d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348741182633328464088960427704191714718016202937535081000383075
68432251978868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.348741182633328464088960427704191714718016202937535
08100038307568432251978868
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.14160606253921437256628817485323272474016990850256853862780703586958951703936
Short name T261
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.67 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:55 PM PDT 23
Peak memory 211180 kb
Host smart-0bdf359c-ac89-4c33-8f16-06b09fbf40f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14160606253921437256628817485323272474016990850256853862780703586958951703936 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.14160606253921437256628817485323272474016990850256853862780703586958951703936
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.17526989140273973796596978093640367849639938148364074718466734634238019102702
Short name T181
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.37 seconds
Started Oct 25 01:50:38 PM PDT 23
Finished Oct 25 01:56:25 PM PDT 23
Peak memory 237720 kb
Host smart-a10c27ad-6c6b-4ebf-ba6a-e158f9d86884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17526989140273973796596978093640367849639938148364074718466734634238019102702 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.1752698914027397379659697809364036784963993814836407471846
6734634238019102702
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.88750376292431747727625037228595006538581485633650194494503719710264602369003
Short name T363
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.73 seconds
Started Oct 25 01:50:51 PM PDT 23
Finished Oct 25 01:51:17 PM PDT 23
Peak memory 211588 kb
Host smart-ea520aa6-c660-41aa-899d-14e63e5fc885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88750376292431747727625037228595006538581485633650194494503719710264602369003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.88750376292431747727625037228595006538581485633650194494503719710264602369003
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.84530242814620214009779221119286736178135435571124032205548934382062684951896
Short name T156
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.48 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:50:56 PM PDT 23
Peak memory 211176 kb
Host smart-14df6840-6f75-47de-82a7-4a9be95b15e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84530242814620214009779221119286736178135435571124032205548934382062684951896 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.84530242814620214009779221119286736178135435571124032205548934382062684951896
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.33193503699368623818491969748661342158356951783105973118580746346236839389131
Short name T359
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.96 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 212732 kb
Host smart-7d3a1c10-3718-405d-a53d-5c21a8c45c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33193503699368623818491969748661342158356951783105973118580746346236839389131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.33193503699368623818491969748661342158356951783105973118580746346236839389131
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.45025724631984730630376171189935231927440517290047276584141354047541466884057
Short name T8
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.75 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:51:23 PM PDT 23
Peak memory 212988 kb
Host smart-0e5454a7-8ce6-4833-8b9e-cf5f565019e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450257246319847306303761711899352319274405172900472765841413540
47541466884057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.450257246319847306303761711899352319274405172900472
76584141354047541466884057
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.38581550320408188999448193161441109109135960861780638307920381525177510926359
Short name T184
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.74 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:50:58 PM PDT 23
Peak memory 211148 kb
Host smart-1f304f03-cead-4270-ba02-3a0069829a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38581550320408188999448193161441109109135960861780638307920381525177510926359 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.38581550320408188999448193161441109109135960861780638307920381525177510926359
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.42860798954422817550846239159586937587303895726109943945374031602225940227706
Short name T37
Test name
Test status
Simulation time 69854280986 ps
CPU time 332 seconds
Started Oct 25 01:50:40 PM PDT 23
Finished Oct 25 01:56:13 PM PDT 23
Peak memory 237460 kb
Host smart-78e7835b-e2b4-41e7-adfa-0b242fc1ab8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860798954422817550846239159586937587303895726109943945374031602225940227706 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.4286079895442281755084623915958693758730389572610994394537
4031602225940227706
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.60222639026101593952093102875582288790077630262496152500228928784111779550217
Short name T300
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.49 seconds
Started Oct 25 01:50:43 PM PDT 23
Finished Oct 25 01:51:09 PM PDT 23
Peak memory 211736 kb
Host smart-d0fabb21-f94e-4ddf-8985-8ee6f43ba0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60222639026101593952093102875582288790077630262496152500228928784111779550217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rom_ctrl_kmac_err_chk.60222639026101593952093102875582288790077630262496152500228928784111779550217
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.25005879884391215509976412331433716010429227088280896153091103491728933972931
Short name T355
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.31 seconds
Started Oct 25 01:50:44 PM PDT 23
Finished Oct 25 01:50:58 PM PDT 23
Peak memory 211128 kb
Host smart-4c67025c-5824-4179-ad60-1e2be84e0dbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25005879884391215509976412331433716010429227088280896153091103491728933972931 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.25005879884391215509976412331433716010429227088280896153091103491728933972931
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.31099596698831567585177566048996483576164424398414188963514558540705295997576
Short name T242
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.51 seconds
Started Oct 25 01:50:42 PM PDT 23
Finished Oct 25 01:51:11 PM PDT 23
Peak memory 212728 kb
Host smart-a6fa1423-5124-4007-bd99-215acc019ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31099596698831567585177566048996483576164424398414188963514558540705295997576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.31099596698831567585177566048996483576164424398414188963514558540705295997576
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.66262569916677710926110621747105768361290169759725309503449273234362984033139
Short name T345
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.62 seconds
Started Oct 25 01:50:45 PM PDT 23
Finished Oct 25 01:51:28 PM PDT 23
Peak memory 212968 kb
Host smart-d6f2397e-08a4-46ab-9a4a-d4b8844eb3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662625699166777109261106217471057683612901697597253095034492732
34362984033139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.662625699166777109261106217471057683612901697597253
09503449273234362984033139
Directory /workspace/9.rom_ctrl_stress_all/latest
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