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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T261 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.15852252553501061183865393739612693265874314691022538547945976035235345191274 Oct 29 02:05:51 PM PDT 23 Oct 29 02:06:17 PM PDT 23 6233818126 ps
T262 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.113984762044802624370874905415941364259048565900823467950307001510286287234841 Oct 29 02:04:28 PM PDT 23 Oct 29 02:09:55 PM PDT 23 69854280986 ps
T263 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.79964270294093701236828673187170217687888307615524120112231617260407585386976 Oct 29 02:05:37 PM PDT 23 Oct 29 02:11:16 PM PDT 23 69854280986 ps
T264 /workspace/coverage/default/43.rom_ctrl_smoke.8856275277127954625145228759141338550954440602207015875560614778354758843146 Oct 29 02:05:38 PM PDT 23 Oct 29 02:06:06 PM PDT 23 6265461576 ps
T265 /workspace/coverage/default/16.rom_ctrl_alert_test.60482771167559885392351596240392612025737386368735453036244929957376821740806 Oct 29 02:04:41 PM PDT 23 Oct 29 02:04:54 PM PDT 23 3124113076 ps
T266 /workspace/coverage/default/44.rom_ctrl_alert_test.33018172348224450200070236518807736183856563178175992596871351282705944173911 Oct 29 02:05:53 PM PDT 23 Oct 29 02:06:05 PM PDT 23 3124113076 ps
T267 /workspace/coverage/default/11.rom_ctrl_stress_all.18816238411337789091367976523066902302670220118358301547157885087138383315355 Oct 29 02:04:29 PM PDT 23 Oct 29 02:05:13 PM PDT 23 9415977006 ps
T268 /workspace/coverage/default/46.rom_ctrl_smoke.24633191021675886980179398009933984053235803732976950100966472713122638112320 Oct 29 02:05:38 PM PDT 23 Oct 29 02:06:07 PM PDT 23 6265461576 ps
T269 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.44889386124274692668219398365450282757826788415146959911814429989459318015100 Oct 29 02:04:15 PM PDT 23 Oct 29 02:09:58 PM PDT 23 69854280986 ps
T270 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.108120519301491613721943913383619217293247267624321922395199755331154949458157 Oct 29 02:04:45 PM PDT 23 Oct 29 02:10:15 PM PDT 23 69854280986 ps
T271 /workspace/coverage/default/49.rom_ctrl_smoke.75829237322391156637903058566756172913897554766786077561715934989756675185332 Oct 29 02:05:48 PM PDT 23 Oct 29 02:06:16 PM PDT 23 6265461576 ps
T272 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3030247697274987617661685844847145370815104831060189027250377972160305483755 Oct 29 02:04:45 PM PDT 23 Oct 29 02:10:12 PM PDT 23 69854280986 ps
T273 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.64097251783170198211492497921389249558005700273129644798034583154458231137950 Oct 29 02:04:30 PM PDT 23 Oct 29 02:10:14 PM PDT 23 69854280986 ps
T274 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.13417675433315956207548914320611503747091585730817928029689588149840868057127 Oct 29 02:05:24 PM PDT 23 Oct 29 02:05:42 PM PDT 23 3151732636 ps
T275 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.104998042514097948694407290710020129236707302467172241317116220344737672593450 Oct 29 02:04:12 PM PDT 23 Oct 29 02:04:38 PM PDT 23 6233818126 ps
T276 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.73906844413515869500742699683210650883979568333217121973611982442792636040130 Oct 29 02:05:27 PM PDT 23 Oct 29 02:05:56 PM PDT 23 6233818126 ps
T277 /workspace/coverage/default/6.rom_ctrl_alert_test.15580095324769826611442016036011659233464662536871052513760421067119261197829 Oct 29 02:04:29 PM PDT 23 Oct 29 02:04:43 PM PDT 23 3124113076 ps
T278 /workspace/coverage/default/16.rom_ctrl_stress_all.53188700252420614604798496522137668525806922584224619095154877617128643187723 Oct 29 02:04:45 PM PDT 23 Oct 29 02:05:26 PM PDT 23 9415977006 ps
T279 /workspace/coverage/default/14.rom_ctrl_alert_test.110847527998371448626109481632328042711203613510499052462377140668253142921108 Oct 29 02:04:31 PM PDT 23 Oct 29 02:04:44 PM PDT 23 3124113076 ps
T280 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.43552123430100293672058944007921063865797615088621225865751459804512339869442 Oct 29 02:04:48 PM PDT 23 Oct 29 02:05:14 PM PDT 23 6233818126 ps
T281 /workspace/coverage/default/40.rom_ctrl_stress_all.10039622398538958433069141586668104901783975209885861774969826311953582731743 Oct 29 02:05:32 PM PDT 23 Oct 29 02:06:17 PM PDT 23 9415977006 ps
T282 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.58558177117927494825463238207537056023884717280176637018973548012430873780690 Oct 29 02:04:08 PM PDT 23 Oct 29 02:09:48 PM PDT 23 69854280986 ps
T283 /workspace/coverage/default/32.rom_ctrl_stress_all.60554510123980777928766432373332824804859571910470242469521161119826433250658 Oct 29 02:05:26 PM PDT 23 Oct 29 02:06:12 PM PDT 23 9415977006 ps
T284 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.16172760488202010371638247122081356103027724667385335794328505126798476181224 Oct 29 02:05:26 PM PDT 23 Oct 29 02:05:55 PM PDT 23 6233818126 ps
T285 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.103341783734449458989622577985172538575406124421557205547844967006470375572449 Oct 29 02:05:26 PM PDT 23 Oct 29 02:05:43 PM PDT 23 3151732636 ps
T286 /workspace/coverage/default/40.rom_ctrl_smoke.109320858407144505495110127856306521689896402711136325259117764152759201842042 Oct 29 02:05:33 PM PDT 23 Oct 29 02:06:03 PM PDT 23 6265461576 ps
T287 /workspace/coverage/default/36.rom_ctrl_alert_test.65659871424303254214642062343605307164398214141911777598936701392671230465218 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:43 PM PDT 23 3124113076 ps
T288 /workspace/coverage/default/44.rom_ctrl_smoke.414757835767555345052708922014620091980199940509176123795418180991276129392 Oct 29 02:05:37 PM PDT 23 Oct 29 02:06:06 PM PDT 23 6265461576 ps
T289 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.67815848693620086064664082237180062574570847030930158491250533956908541426301 Oct 29 02:04:43 PM PDT 23 Oct 29 02:10:30 PM PDT 23 69854280986 ps
T290 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.65755160040770005630538359022900334205989654244078008142597444421352501365516 Oct 29 02:04:23 PM PDT 23 Oct 29 02:04:37 PM PDT 23 3151732636 ps
T291 /workspace/coverage/default/8.rom_ctrl_alert_test.8102539074563061390631642985104084770003847440736872934951969195582567308952 Oct 29 02:04:25 PM PDT 23 Oct 29 02:04:37 PM PDT 23 3124113076 ps
T292 /workspace/coverage/default/31.rom_ctrl_stress_all.73053226518967302831355379830218834683822877433680249713546559171930641019587 Oct 29 02:05:25 PM PDT 23 Oct 29 02:06:11 PM PDT 23 9415977006 ps
T293 /workspace/coverage/default/46.rom_ctrl_alert_test.1492738558812694504687564580356956010231604361565832248844508206726078164271 Oct 29 02:05:36 PM PDT 23 Oct 29 02:05:49 PM PDT 23 3124113076 ps
T294 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.39769783862138260243193107422921529323004961879129841195206873718615747377394 Oct 29 02:04:55 PM PDT 23 Oct 29 02:05:20 PM PDT 23 6233818126 ps
T295 /workspace/coverage/default/19.rom_ctrl_stress_all.50126441939910685633723777078385350516949641327467919085567632601785797631497 Oct 29 02:04:42 PM PDT 23 Oct 29 02:05:24 PM PDT 23 9415977006 ps
T296 /workspace/coverage/default/6.rom_ctrl_stress_all.82436690042755843659471340817792311759617175676010714945225234130299634699843 Oct 29 02:04:25 PM PDT 23 Oct 29 02:05:08 PM PDT 23 9415977006 ps
T297 /workspace/coverage/default/15.rom_ctrl_alert_test.25552808626943763879692460328132378907460597467567222578202107704785220363839 Oct 29 02:04:30 PM PDT 23 Oct 29 02:04:43 PM PDT 23 3124113076 ps
T298 /workspace/coverage/default/1.rom_ctrl_stress_all.45657204660343397237935303761369285241770173497775399122499867852595675088324 Oct 29 02:04:09 PM PDT 23 Oct 29 02:04:52 PM PDT 23 9415977006 ps
T299 /workspace/coverage/default/22.rom_ctrl_smoke.80457920250926989290445514716365713559623762551427392372116283410450297292027 Oct 29 02:04:59 PM PDT 23 Oct 29 02:05:28 PM PDT 23 6265461576 ps
T300 /workspace/coverage/default/48.rom_ctrl_smoke.61829523489598549431010132469848166510835038284735545622883185909633670647092 Oct 29 02:05:45 PM PDT 23 Oct 29 02:06:14 PM PDT 23 6265461576 ps
T301 /workspace/coverage/default/38.rom_ctrl_smoke.28961347198814775567237041720247887419779985886296139297062208852890579000604 Oct 29 02:05:25 PM PDT 23 Oct 29 02:05:57 PM PDT 23 6265461576 ps
T302 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.51525530740882632173472615733530254840767001288199456603509731711119465334988 Oct 29 02:05:29 PM PDT 23 Oct 29 02:11:12 PM PDT 23 69854280986 ps
T303 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.81987707163114619109310696977996999877118906386564590388432130798961131864021 Oct 29 02:05:00 PM PDT 23 Oct 29 02:10:37 PM PDT 23 69854280986 ps
T304 /workspace/coverage/default/11.rom_ctrl_smoke.114875511829158270405163899185105883147372085069735035156485512820434746404780 Oct 29 02:04:27 PM PDT 23 Oct 29 02:04:56 PM PDT 23 6265461576 ps
T305 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.83260993784361476404969495651254926494495391769075896673103704791209382745248 Oct 29 02:04:58 PM PDT 23 Oct 29 02:05:24 PM PDT 23 6233818126 ps
T306 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.86597212121584362710401117443343935667016671749727264336551435520899180524114 Oct 29 02:03:55 PM PDT 23 Oct 29 02:04:21 PM PDT 23 6233818126 ps
T307 /workspace/coverage/default/33.rom_ctrl_smoke.110440085801824196792964698805175447262206727427731986885050167037241020974800 Oct 29 02:05:26 PM PDT 23 Oct 29 02:05:58 PM PDT 23 6265461576 ps
T308 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.15355229749104623079966866276128122113732180156869771282670707956447428811029 Oct 29 02:04:58 PM PDT 23 Oct 29 02:05:12 PM PDT 23 3151732636 ps
T309 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.72645206843040158862034261089074036148900137661198380370566413837544124308193 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:29 PM PDT 23 3151732636 ps
T310 /workspace/coverage/default/25.rom_ctrl_smoke.25980955858833606128728796823428575851353869133736115949188136748709863504696 Oct 29 02:05:20 PM PDT 23 Oct 29 02:05:49 PM PDT 23 6265461576 ps
T311 /workspace/coverage/default/27.rom_ctrl_alert_test.45676218176041844449105450123191319251748407128823075026902847882913814491018 Oct 29 02:05:23 PM PDT 23 Oct 29 02:05:41 PM PDT 23 3124113076 ps
T312 /workspace/coverage/default/26.rom_ctrl_smoke.84831309914562724083327449820272337994703454993150667914863900460536222527758 Oct 29 02:05:24 PM PDT 23 Oct 29 02:05:56 PM PDT 23 6265461576 ps
T313 /workspace/coverage/default/21.rom_ctrl_smoke.50240121021508500180154129089117805725863635395797716786184395306544002330649 Oct 29 02:05:00 PM PDT 23 Oct 29 02:05:28 PM PDT 23 6265461576 ps
T314 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.7548791251137188553725942692001561889808579423026731667066063086210348412515 Oct 29 02:04:59 PM PDT 23 Oct 29 02:10:35 PM PDT 23 69854280986 ps
T315 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.92458219486935107587643032409807833329648748467769312304481983851671308008615 Oct 29 02:05:39 PM PDT 23 Oct 29 02:11:24 PM PDT 23 69854280986 ps
T316 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.24765303406474696333438239534462178064725750909083108524504933384843058067434 Oct 29 02:04:57 PM PDT 23 Oct 29 02:05:23 PM PDT 23 6233818126 ps
T317 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.23539787763789274193673790588832226302078158649319361030582296425692262710465 Oct 29 02:04:17 PM PDT 23 Oct 29 02:09:52 PM PDT 23 69854280986 ps
T318 /workspace/coverage/default/42.rom_ctrl_stress_all.50447048364489518653095414407989126337341828504376931273635306899485811746184 Oct 29 02:05:37 PM PDT 23 Oct 29 02:06:20 PM PDT 23 9415977006 ps
T319 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.65270352464645700037217041163598198802827522712493365701609188448454207799367 Oct 29 02:05:22 PM PDT 23 Oct 29 02:11:09 PM PDT 23 69854280986 ps
T320 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.110423668964365728092011638983514423410976741218908068059042449918515381233722 Oct 29 02:05:36 PM PDT 23 Oct 29 02:06:01 PM PDT 23 6233818126 ps
T321 /workspace/coverage/default/38.rom_ctrl_alert_test.59014407033699726689439003247442779480453012456060562166824959320184773325946 Oct 29 02:05:27 PM PDT 23 Oct 29 02:05:43 PM PDT 23 3124113076 ps
T322 /workspace/coverage/default/29.rom_ctrl_smoke.82394368972788753027581991769847969955575286789659738896133254226767392666084 Oct 29 02:05:27 PM PDT 23 Oct 29 02:05:58 PM PDT 23 6265461576 ps
T323 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.69926801886150037956459336980461387207178790378067003963276562623085177181838 Oct 29 02:05:27 PM PDT 23 Oct 29 02:05:55 PM PDT 23 6233818126 ps
T324 /workspace/coverage/default/10.rom_ctrl_smoke.1996344000340321934616359208311951973608888499863270133977852582181647693946 Oct 29 02:04:24 PM PDT 23 Oct 29 02:04:53 PM PDT 23 6265461576 ps
T325 /workspace/coverage/default/44.rom_ctrl_stress_all.30940240517827691235707599853737957174429011033749185728091149627464493758981 Oct 29 02:05:34 PM PDT 23 Oct 29 02:06:17 PM PDT 23 9415977006 ps
T326 /workspace/coverage/default/41.rom_ctrl_smoke.14328234924767103175025816515716663080487739431693478765376345136368002677039 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:59 PM PDT 23 6265461576 ps
T327 /workspace/coverage/default/39.rom_ctrl_alert_test.53774381050597538041370908822688535777680534670963635781012379675261708966362 Oct 29 02:05:29 PM PDT 23 Oct 29 02:05:43 PM PDT 23 3124113076 ps
T328 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.30513628330787906009320761508384368513613087007688608000339245630026141976809 Oct 29 02:05:24 PM PDT 23 Oct 29 02:11:12 PM PDT 23 69854280986 ps
T329 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.94573893185991477022713086401813079217216133983840011290907612852038539606952 Oct 29 02:04:29 PM PDT 23 Oct 29 02:04:55 PM PDT 23 6233818126 ps
T330 /workspace/coverage/default/37.rom_ctrl_stress_all.104940107923388335184284528826160641315852324877678922618777310141510602106851 Oct 29 02:05:27 PM PDT 23 Oct 29 02:06:12 PM PDT 23 9415977006 ps
T331 /workspace/coverage/default/5.rom_ctrl_stress_all.73522083419953761040644852268948496472929263078223554826874817007787037835028 Oct 29 02:04:21 PM PDT 23 Oct 29 02:05:03 PM PDT 23 9415977006 ps
T332 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.84724556550298783835070323719114802870515200009535748342641787722285380133544 Oct 29 02:04:49 PM PDT 23 Oct 29 02:05:03 PM PDT 23 3151732636 ps
T333 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.88674635743587014142387067985713872476966670270330145556492690310297101941358 Oct 29 02:04:45 PM PDT 23 Oct 29 02:05:10 PM PDT 23 6233818126 ps
T334 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.71374532426529574709996341926843478095925333136037054156314063615599283912072 Oct 29 02:04:21 PM PDT 23 Oct 29 02:04:35 PM PDT 23 3151732636 ps
T335 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.60322695885062929857994319145397344223030236851043882727935175418094844756752 Oct 29 02:05:44 PM PDT 23 Oct 29 02:05:57 PM PDT 23 3151732636 ps
T336 /workspace/coverage/default/15.rom_ctrl_stress_all.31839344800431026995883969407044809566420222608616996138486443513281882871680 Oct 29 02:04:45 PM PDT 23 Oct 29 02:05:27 PM PDT 23 9415977006 ps
T337 /workspace/coverage/default/4.rom_ctrl_stress_all.9325281998393196701382164530282957935881602739301485874188988924503823077831 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:59 PM PDT 23 9415977006 ps
T338 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.74062229767333430191896742134939951828090083863982316049094197101199299560646 Oct 29 02:05:24 PM PDT 23 Oct 29 02:11:11 PM PDT 23 69854280986 ps
T339 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.24973230101859184363427735588179338173152480415530049156765186253507300791599 Oct 29 02:05:22 PM PDT 23 Oct 29 02:05:54 PM PDT 23 6233818126 ps
T340 /workspace/coverage/default/38.rom_ctrl_stress_all.53207768162586442670588877461544192899207876400693695365156039340496637576139 Oct 29 02:05:25 PM PDT 23 Oct 29 02:06:13 PM PDT 23 9415977006 ps
T341 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.55336931501010413943048251353343510617274642115401375895872662825715082998473 Oct 29 02:05:29 PM PDT 23 Oct 29 02:05:45 PM PDT 23 3151732636 ps
T342 /workspace/coverage/default/7.rom_ctrl_alert_test.8193342529444430242646288453068533093558457595172318131124825791310250308998 Oct 29 02:04:28 PM PDT 23 Oct 29 02:04:40 PM PDT 23 3124113076 ps
T343 /workspace/coverage/default/17.rom_ctrl_smoke.21025221863130564889946820959397276983511807629189757725111035048440434766455 Oct 29 02:04:56 PM PDT 23 Oct 29 02:05:25 PM PDT 23 6265461576 ps
T344 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.14395664142934048560922650677882961239885107063411069014661110329357109238548 Oct 29 02:05:24 PM PDT 23 Oct 29 02:05:42 PM PDT 23 3151732636 ps
T345 /workspace/coverage/default/35.rom_ctrl_smoke.80745088848277460063242721810975756802270602859568318207726332624248838544399 Oct 29 02:05:26 PM PDT 23 Oct 29 02:05:59 PM PDT 23 6265461576 ps
T346 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.72272125467632313567077836838941877202069151291336683018450877832220165635270 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:44 PM PDT 23 3151732636 ps
T347 /workspace/coverage/default/29.rom_ctrl_stress_all.6669813125432762283402765927315108923360625991666361569066403383187423130521 Oct 29 02:05:20 PM PDT 23 Oct 29 02:06:04 PM PDT 23 9415977006 ps
T348 /workspace/coverage/default/2.rom_ctrl_stress_all.70746878437835179311457739191566472604860067283902672673695585630418835432748 Oct 29 02:04:16 PM PDT 23 Oct 29 02:05:00 PM PDT 23 9415977006 ps
T349 /workspace/coverage/default/7.rom_ctrl_smoke.84902224290480190415207218378292653369126428167656399578668815112353754370859 Oct 29 02:04:29 PM PDT 23 Oct 29 02:04:59 PM PDT 23 6265461576 ps
T350 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.90310878835271663952150667966714082421247361556381698598380149310322114099010 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:44 PM PDT 23 3151732636 ps
T351 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.104969486543748170698760475714217510703333599246371885376250650205552080196193 Oct 29 02:05:30 PM PDT 23 Oct 29 02:06:00 PM PDT 23 6233818126 ps
T352 /workspace/coverage/default/20.rom_ctrl_alert_test.51353678816729261992912331276024245859859050397386366234227926117452242433883 Oct 29 02:05:00 PM PDT 23 Oct 29 02:05:13 PM PDT 23 3124113076 ps
T353 /workspace/coverage/default/5.rom_ctrl_smoke.99987455855282811236955258544558386661883849299392679047401042951553590156163 Oct 29 02:04:21 PM PDT 23 Oct 29 02:04:50 PM PDT 23 6265461576 ps
T354 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.22645119828010870554776572641354713035926431870294210834045630908968232859360 Oct 29 02:04:48 PM PDT 23 Oct 29 02:05:02 PM PDT 23 3151732636 ps
T355 /workspace/coverage/default/43.rom_ctrl_alert_test.66112997669983939536996180007451612741716263140590508583482303573635115611395 Oct 29 02:05:36 PM PDT 23 Oct 29 02:05:49 PM PDT 23 3124113076 ps
T356 /workspace/coverage/default/18.rom_ctrl_stress_all.61631216081344804159239610533500254873958119854174894120719183442899291753474 Oct 29 02:04:39 PM PDT 23 Oct 29 02:05:21 PM PDT 23 9415977006 ps
T357 /workspace/coverage/default/12.rom_ctrl_stress_all.73497091532924735019140653816687992473868054078448604538024883078708157237470 Oct 29 02:04:23 PM PDT 23 Oct 29 02:05:05 PM PDT 23 9415977006 ps
T358 /workspace/coverage/default/23.rom_ctrl_stress_all.24725647656848578921099420386929475814834109967818705450631065764602988763951 Oct 29 02:05:03 PM PDT 23 Oct 29 02:05:46 PM PDT 23 9415977006 ps
T359 /workspace/coverage/default/1.rom_ctrl_smoke.75815744218678480894757017828488245095912166247560875079123655058852831589378 Oct 29 02:04:14 PM PDT 23 Oct 29 02:04:42 PM PDT 23 6265461576 ps
T360 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.97376536133847440619412229300064415737883303427863855183481454520303715991294 Oct 29 02:05:22 PM PDT 23 Oct 29 02:05:54 PM PDT 23 6233818126 ps
T361 /workspace/coverage/default/30.rom_ctrl_smoke.63599889046651724151720175650805724173934966294117916079111422811857611557193 Oct 29 02:05:26 PM PDT 23 Oct 29 02:05:59 PM PDT 23 6265461576 ps
T362 /workspace/coverage/default/15.rom_ctrl_smoke.65644258935379341245933796955058079355649891361516225621685998704876643465580 Oct 29 02:04:30 PM PDT 23 Oct 29 02:04:59 PM PDT 23 6265461576 ps
T363 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.11513423584384225226270730536047032233874134375176821568826353121085801834808 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:44 PM PDT 23 3151732636 ps
T364 /workspace/coverage/default/2.rom_ctrl_smoke.97984520157205110920199397890889736805349298604533258086882946123923892039534 Oct 29 02:04:20 PM PDT 23 Oct 29 02:04:49 PM PDT 23 6265461576 ps
T365 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.12510750467242902805213318702863421703054405816718032279775206279226736122867 Oct 29 02:05:28 PM PDT 23 Oct 29 02:05:43 PM PDT 23 3151732636 ps
T366 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.78000734984215580240434003770716504862589994501128976777756844909635050202538 Oct 29 02:02:17 PM PDT 23 Oct 29 02:03:41 PM PDT 23 3476453456 ps
T367 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.53954643051898773048842579164635233963518293392746537134673647778300934663122 Oct 29 02:03:12 PM PDT 23 Oct 29 02:04:33 PM PDT 23 3476453456 ps
T73 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.56439258487600122657860676678135630499432446683162573609180854356648822572839 Oct 29 02:02:48 PM PDT 23 Oct 29 02:07:30 PM PDT 23 65914678386 ps
T74 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.92978114980336818541074859823267873991576336458302517909781821489701144611268 Oct 29 02:03:46 PM PDT 23 Oct 29 02:08:27 PM PDT 23 65914678386 ps
T368 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.8588729335563964125013165863586777222210849564540445469374338559727543185516 Oct 29 02:03:19 PM PDT 23 Oct 29 02:04:40 PM PDT 23 3476453456 ps
T56 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.50326402849032622185900761262825428135729802650717053774243074033645282800577 Oct 29 02:03:16 PM PDT 23 Oct 29 02:03:28 PM PDT 23 3135422826 ps
T369 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.44017907700028540002313282518931077874185933420337868200121649375949972498099 Oct 29 02:02:37 PM PDT 23 Oct 29 02:02:52 PM PDT 23 3142303916 ps
T370 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.11303116990233268180858276826861478287208196505616982537352217837040387928193 Oct 29 02:03:07 PM PDT 23 Oct 29 02:03:19 PM PDT 23 3124113076 ps
T87 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.94119285997259428807621874244483710716410075515409984970192213062398122114396 Oct 29 02:02:54 PM PDT 23 Oct 29 02:03:07 PM PDT 23 3124113076 ps
T65 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.89722159661954500532526429348076674214443489569097666964312411099627138198685 Oct 29 02:02:33 PM PDT 23 Oct 29 02:02:50 PM PDT 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.107498511205812958699080020128752480148128428281895247232287925107944121516121 Oct 29 02:01:54 PM PDT 23 Oct 29 02:03:13 PM PDT 23 3476453456 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.66944925064546921463026720926770258149994810748066256546298724263298077515038 Oct 29 02:02:07 PM PDT 23 Oct 29 02:02:20 PM PDT 23 3124113076 ps
T373 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.12403655271533794982050428838143954528398825305324727580174349572772683142689 Oct 29 02:02:39 PM PDT 23 Oct 29 02:02:52 PM PDT 23 3135422826 ps
T374 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.97494673570737237942925900504305036833150093751191072644096516678824577245507 Oct 29 02:02:28 PM PDT 23 Oct 29 02:02:40 PM PDT 23 3124113076 ps
T375 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.81007122028718293604578462077108224560516914799195601580556768443887909092085 Oct 29 02:04:11 PM PDT 23 Oct 29 02:05:32 PM PDT 23 3476453456 ps
T376 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.46067593189851119341896473401530582475842656967276656685333098676573732010936 Oct 29 02:03:17 PM PDT 23 Oct 29 02:03:29 PM PDT 23 3124113076 ps
T377 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2421468646542004285654216304636400287168421866022681660543165754989242824895 Oct 29 02:02:46 PM PDT 23 Oct 29 02:02:59 PM PDT 23 3124113076 ps
T378 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.34604943101264693886450172796121135283081538767128824821221428508598815864185 Oct 29 02:04:13 PM PDT 23 Oct 29 02:04:26 PM PDT 23 3135422826 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.105559222722974690110641494244071343181796872748097953927915970850005132446914 Oct 29 02:04:15 PM PDT 23 Oct 29 02:09:00 PM PDT 23 65914678386 ps
T379 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.82733834093849686241176534848661792404126123617062920800106724622556191639593 Oct 29 02:04:13 PM PDT 23 Oct 29 02:04:28 PM PDT 23 3142303916 ps
T380 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.24090427042249705338046820833931241747799334556020467077238524110060306344977 Oct 29 02:03:08 PM PDT 23 Oct 29 02:03:20 PM PDT 23 3135422826 ps
T381 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.9463633830527763768003770324252143173768833434421745641675678936629522700824 Oct 29 02:04:07 PM PDT 23 Oct 29 02:04:21 PM PDT 23 3142303916 ps
T382 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.67075440662057639224995583618849700732154364279747840772050709814060072978760 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:30 PM PDT 23 3142303916 ps
T383 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.7448996425929933826803553810795754120173004582313247559951549457384129317619 Oct 29 02:01:55 PM PDT 23 Oct 29 02:02:11 PM PDT 23 3138518126 ps
T66 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.73068684985974557336652438146974926334239074022368438593353267971497084862417 Oct 29 02:02:50 PM PDT 23 Oct 29 02:03:06 PM PDT 23 3124113076 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.38867848312102511799682024514469750872529579752493111602814771353008166825558 Oct 29 02:01:45 PM PDT 23 Oct 29 02:01:59 PM PDT 23 3142303916 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.34368628501903461385273181900398497280120506661197670601356576578584306196613 Oct 29 02:03:51 PM PDT 23 Oct 29 02:04:07 PM PDT 23 3124113076 ps
T386 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.85374713643586314766426596146441190538802186491403135764162736648560558301728 Oct 29 02:04:01 PM PDT 23 Oct 29 02:04:16 PM PDT 23 3135422826 ps
T387 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.16181595757635621086011713435363774916391082441684254889085653557837781566796 Oct 29 02:03:56 PM PDT 23 Oct 29 02:04:10 PM PDT 23 3124113076 ps
T388 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.53300837113127509722998182596916535908987387808273667907895397135073058482747 Oct 29 02:03:47 PM PDT 23 Oct 29 02:05:07 PM PDT 23 3476453456 ps
T67 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.9589043635125884721814662159489608942236238054378032158197103646101649363743 Oct 29 02:02:31 PM PDT 23 Oct 29 02:02:48 PM PDT 23 3124113076 ps
T389 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.50926655144534785557735427739185292188578043392012800876527119489533067915800 Oct 29 02:02:36 PM PDT 23 Oct 29 02:02:49 PM PDT 23 3124113076 ps
T390 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.103771024513817910077149189165109031942152674354627723620124139027411984786835 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:28 PM PDT 23 3135422826 ps
T68 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.92024012968085217250186041978207659135088739505347508196889605506327410951267 Oct 29 02:02:40 PM PDT 23 Oct 29 02:02:57 PM PDT 23 3124113076 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.48391297095603995744272961116994744703848935125521121890065406319303491077236 Oct 29 02:04:12 PM PDT 23 Oct 29 02:08:46 PM PDT 23 65914678386 ps
T391 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.89053673358725471586057407924032340772236290076267423676540774647219464520407 Oct 29 02:04:15 PM PDT 23 Oct 29 02:04:32 PM PDT 23 3124113076 ps
T392 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.53263856639947210230050320660917122295220822218265746542593085897141055104131 Oct 29 02:01:55 PM PDT 23 Oct 29 02:02:08 PM PDT 23 3124113076 ps
T393 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.428937652394319752042428909577481622618065320667673581833352120992686992793 Oct 29 02:03:49 PM PDT 23 Oct 29 02:08:37 PM PDT 23 65914678386 ps
T394 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.107626810993846450521991696035813113035116370189152346878448483284825884641353 Oct 29 02:03:18 PM PDT 23 Oct 29 02:03:32 PM PDT 23 3142303916 ps
T395 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.36764279872509158877031790963423626663368684418027591940135953080898673555479 Oct 29 02:02:53 PM PDT 23 Oct 29 02:03:05 PM PDT 23 3124113076 ps
T396 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.50933833995878137865078675908633310664816871062248876350664682098615926183254 Oct 29 02:02:26 PM PDT 23 Oct 29 02:02:39 PM PDT 23 3124113076 ps
T397 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.8651621080207347757170032404202901644688744959952731759454225047593305389894 Oct 29 02:02:52 PM PDT 23 Oct 29 02:03:08 PM PDT 23 3124113076 ps
T398 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.75292895360046972349835111780802650419750998724578099792003355935798922243698 Oct 29 02:02:16 PM PDT 23 Oct 29 02:07:00 PM PDT 23 65914678386 ps
T399 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.82085610991422449580722981327915912559567467892986136898135343089101976141714 Oct 29 02:02:48 PM PDT 23 Oct 29 02:03:02 PM PDT 23 3142303916 ps
T400 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.22450170171182464176021608445779509695472988919849352468076697872502136436022 Oct 29 02:02:19 PM PDT 23 Oct 29 02:07:06 PM PDT 23 65914678386 ps
T401 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.10242723134466482316593342481050920566050966867908362127390979397662095839302 Oct 29 02:04:09 PM PDT 23 Oct 29 02:04:23 PM PDT 23 3142303916 ps
T402 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.23315533427485387768525737135115607829772990426294250801435430492640644397283 Oct 29 02:03:12 PM PDT 23 Oct 29 02:03:26 PM PDT 23 3142303916 ps
T403 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.60150267360525505833110162283147739249598134246890954016509633873989606433100 Oct 29 02:04:14 PM PDT 23 Oct 29 02:04:31 PM PDT 23 3124113076 ps
T404 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.14088485862920191533903259818447667837688491915307948905779093835719540521410 Oct 29 02:04:14 PM PDT 23 Oct 29 02:04:26 PM PDT 23 3124113076 ps
T405 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.6337000538954355426778038739797485250281736541420429460420046345850462191917 Oct 29 02:02:27 PM PDT 23 Oct 29 02:07:08 PM PDT 23 65914678386 ps
T406 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.109881184530546973795041026832928649665564291087426975926799576508942405755356 Oct 29 02:02:37 PM PDT 23 Oct 29 02:03:58 PM PDT 23 3476453456 ps
T407 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.76123429741380886313502289162856712330550725581795398879206547736382896163918 Oct 29 02:03:12 PM PDT 23 Oct 29 02:07:56 PM PDT 23 65914678386 ps
T408 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.8798051480119820616676255573143196902554264676364155304897709604203274993295 Oct 29 02:03:50 PM PDT 23 Oct 29 02:04:03 PM PDT 23 3124113076 ps
T409 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.64136898163044112401372134202120833665345579134118583140316361326776714234338 Oct 29 02:04:18 PM PDT 23 Oct 29 02:04:31 PM PDT 23 3135422826 ps
T410 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.110856408479514654057545460726970415779926388344722736734292986261833389661115 Oct 29 02:02:17 PM PDT 23 Oct 29 02:02:33 PM PDT 23 3135422826 ps
T411 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.101061199860511493636244670134700515084421142593836451993129724362081138208227 Oct 29 02:04:13 PM PDT 23 Oct 29 02:04:30 PM PDT 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.112889731104869389043458603954694317535614902949286904972128787542046048370624 Oct 29 02:02:16 PM PDT 23 Oct 29 02:02:29 PM PDT 23 3124113076 ps
T413 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.42228617007302717646364197662704123963724873093332722715958400114163965724863 Oct 29 02:03:18 PM PDT 23 Oct 29 02:03:31 PM PDT 23 3124113076 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.87124182943000664525178997522187280646688545746765244224738849222159360926653 Oct 29 02:02:17 PM PDT 23 Oct 29 02:02:37 PM PDT 23 3124113076 ps
T415 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.89473596112542090329482199456128778076229407752648739933417675950234387753005 Oct 29 02:04:09 PM PDT 23 Oct 29 02:04:26 PM PDT 23 3124113076 ps
T416 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3423649495725483716709595248479590870246088856662925296940221493596136706030 Oct 29 02:02:51 PM PDT 23 Oct 29 02:03:03 PM PDT 23 3135422826 ps
T417 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.91378522442546096857060365295955860032772384716593877500856971884280891342025 Oct 29 02:02:52 PM PDT 23 Oct 29 02:03:08 PM PDT 23 3124113076 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.24286768231033703619712527236545361049027089169521357162679444027015046286824 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:28 PM PDT 23 3135422826 ps
T419 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.62727829670036357006880077688125619012296725259803109084718294193931514366748 Oct 29 02:02:51 PM PDT 23 Oct 29 02:07:30 PM PDT 23 65914678386 ps
T420 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.23565888398043006095078472479170054729522896640289318683347819821855873390989 Oct 29 02:03:19 PM PDT 23 Oct 29 02:03:32 PM PDT 23 3135422826 ps
T421 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.9695167525615472426766298859993836128792256888824257108215414970132660998069 Oct 29 02:03:21 PM PDT 23 Oct 29 02:04:42 PM PDT 23 3476453456 ps
T422 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.9195032643240486932623578652307755665838003128828848639460719485270125562557 Oct 29 02:04:08 PM PDT 23 Oct 29 02:05:31 PM PDT 23 3476453456 ps
T423 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.10224082418134995269861623813797109304448084889203439315542979544262716677029 Oct 29 02:03:50 PM PDT 23 Oct 29 02:04:02 PM PDT 23 3135422826 ps
T424 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.104527490148476064235235153743533810798606568283843717479195025077662935977171 Oct 29 02:03:41 PM PDT 23 Oct 29 02:03:58 PM PDT 23 3124113076 ps
T425 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.27583405385079130414212184317570074699055555196465250133871547950792717541841 Oct 29 02:02:18 PM PDT 23 Oct 29 02:02:33 PM PDT 23 3124113076 ps
T426 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.109707761713161358646595242434436341122564071160173625544063864625948721593217 Oct 29 02:02:16 PM PDT 23 Oct 29 02:06:55 PM PDT 23 65914678386 ps
T427 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.83621780337574843954109258139848641756490727126398652011849417543420165565697 Oct 29 02:04:15 PM PDT 23 Oct 29 02:04:30 PM PDT 23 3142303916 ps
T428 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.49525158664353928523508126520256874058266934649607533046984223235522821855934 Oct 29 02:04:09 PM PDT 23 Oct 29 02:05:29 PM PDT 23 3476453456 ps
T429 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.104000043978229463222431307274025976887747303689698140091368252765182401217375 Oct 29 02:02:20 PM PDT 23 Oct 29 02:02:33 PM PDT 23 3124113076 ps
T430 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.114833698691322788471604720375355364173148907005268216656812297510473290322520 Oct 29 02:03:07 PM PDT 23 Oct 29 02:07:46 PM PDT 23 65914678386 ps
T431 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.79557012120528818501001804340636077025935777810335726725280340624443798388192 Oct 29 02:04:18 PM PDT 23 Oct 29 02:05:39 PM PDT 23 3476453456 ps
T432 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.70897933877118032435744843030992876470447795148700516012695423489760303697465 Oct 29 02:04:14 PM PDT 23 Oct 29 02:04:31 PM PDT 23 3124113076 ps
T433 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.366572469660754675796554553502245223289761090793814125156513667727488236000 Oct 29 02:03:16 PM PDT 23 Oct 29 02:07:53 PM PDT 23 65914678386 ps
T434 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.43950929160195904007588854562095350049597475249668661894468533838933530647591 Oct 29 02:03:12 PM PDT 23 Oct 29 02:03:24 PM PDT 23 3135422826 ps
T435 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.79046954937437329057410213120669441003068483679693780571761199719768760213812 Oct 29 02:04:17 PM PDT 23 Oct 29 02:04:33 PM PDT 23 3124113076 ps
T436 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.74189774768434800251566424282165262813821995561967818302611390997986885416060 Oct 29 02:03:07 PM PDT 23 Oct 29 02:04:28 PM PDT 23 3476453456 ps
T437 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.89099478502311101718202201800208362617902028234843654787399060824359174133216 Oct 29 02:03:44 PM PDT 23 Oct 29 02:03:58 PM PDT 23 3135422826 ps
T438 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.8617859139916828366555483823445291144703636946923573986244156213998830730476 Oct 29 02:02:37 PM PDT 23 Oct 29 02:02:50 PM PDT 23 3124113076 ps
T439 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.109907154046658960318422584105740244001425057966152204171480765677933848001485 Oct 29 02:02:53 PM PDT 23 Oct 29 02:03:09 PM PDT 23 3138518126 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.97509508243883565619101123884173335550656487830649463684475054991508178467027 Oct 29 02:03:25 PM PDT 23 Oct 29 02:03:37 PM PDT 23 3124113076 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.11071840895161970507086815529733375719414045399304380555299109519365156818564 Oct 29 02:02:48 PM PDT 23 Oct 29 02:03:01 PM PDT 23 3124113076 ps
T442 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.114665355552489325815578425274477582568943672908277560319604829338361818280047 Oct 29 02:02:53 PM PDT 23 Oct 29 02:04:11 PM PDT 23 3476453456 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.55206039587374313131881756185367833197592453525065292136678911825983421418400 Oct 29 02:04:16 PM PDT 23 Oct 29 02:04:29 PM PDT 23 3124113076 ps
T444 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.96175590860584779517338254556836297949492662147281301379836988387410245386289 Oct 29 02:02:56 PM PDT 23 Oct 29 02:04:17 PM PDT 23 3476453456 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.101479762199464294439634027586191682815213218182783726977665824499903779228378 Oct 29 02:02:33 PM PDT 23 Oct 29 02:02:46 PM PDT 23 3135422826 ps
T446 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.111806786310469773176244331043844469594952695666651778579387562457496439200850 Oct 29 02:02:22 PM PDT 23 Oct 29 02:02:35 PM PDT 23 3124113076 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.27911262963090507219380569449564681954992045477704020166023118238265402428851 Oct 29 02:02:30 PM PDT 23 Oct 29 02:02:45 PM PDT 23 3135422826 ps
T448 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.79676438505128335207421770676764848651369501022045133637493534906428958952580 Oct 29 02:02:54 PM PDT 23 Oct 29 02:03:08 PM PDT 23 3142303916 ps
T449 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.73179379817784153038969122150283305429875498310334898943784544400445831092197 Oct 29 02:04:08 PM PDT 23 Oct 29 02:04:20 PM PDT 23 3135422826 ps
T450 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.83566540228039107997822026069748104357904029731481108686655151614358371726462 Oct 29 02:03:19 PM PDT 23 Oct 29 02:08:03 PM PDT 23 65914678386 ps

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.31194441352799043208478280227209872633952241206221678911471072326289693714632
Short name T15
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.94 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:03:26 PM PDT 23
Peak memory 210836 kb
Host smart-923cc30b-d62e-4a36-82e4-e37e2dfeaf16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31194441352799043208478280227209872633952241206221678911471072326289693714632
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.311944413527990432084782802272098726339522412062216789
11471072326289693714632
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.58645776556199828086807401559430750629305516274072717424469569927166725223984
Short name T5
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.72 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:11:15 PM PDT 23
Peak memory 237740 kb
Host smart-d20a8435-5ea4-4f1e-9283-8dcadc43c6f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58645776556199828086807401559430750629305516274072717424469569927166725223984 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.586457765561998280868074015594307506293055162740727174244
69569927166725223984
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.94737718404574293148418722677812554265411733856026055093334537534214327370875
Short name T23
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.5 seconds
Started Oct 29 02:03:42 PM PDT 23
Finished Oct 29 02:03:59 PM PDT 23
Peak memory 219036 kb
Host smart-46fdb4ef-fd5e-45be-bfc6-0857e1864beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94737718404574293148418722677812554265411733856026055093334537534214327370875 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.94737718404574293148418722677812554265411733856026055093334537534214327370875
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.53015407354874012434246529499805293501851881984013383692908766589839818568911
Short name T17
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.68 seconds
Started Oct 29 02:03:19 PM PDT 23
Finished Oct 29 02:04:40 PM PDT 23
Peak memory 210940 kb
Host smart-6da73aff-1822-4ee2-83be-673a240f52c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53015407354874012434246529499805293501851881984013383692908766589839818568911 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.53015407354874012434246529499805293501851881984013383692908766589839818568911
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.23126763017371927851655721797919200604366897459123598849745459361821756155426
Short name T2
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.64 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:06:13 PM PDT 23
Peak memory 212904 kb
Host smart-95c6d5fb-5d54-4537-bb68-5696eb171e7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231267630173719278516557217979192006043668974591235988497454593
61821756155426 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.23126763017371927851655721797919200604366897459123
598849745459361821756155426
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.105559222722974690110641494244071343181796872748097953927915970850005132446914
Short name T75
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.21 seconds
Started Oct 29 02:04:15 PM PDT 23
Finished Oct 29 02:09:00 PM PDT 23
Peak memory 218848 kb
Host smart-10be945d-ecbd-4189-8e2c-e497a4447459
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105559222722974690110641494244071343181796872748097953927915970850005132446914 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.105559222722974690110641494244071343181796872748097953
927915970850005132446914
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.112681642580602192077549618037370656866035884147659760586055226183757668965678
Short name T86
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 29 02:01:56 PM PDT 23
Finished Oct 29 02:02:08 PM PDT 23
Peak memory 210700 kb
Host smart-1ed717e8-4671-4440-ac91-251bab82a4a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112681642580602192077549618037370656866035884147659760586055226183757668965678 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.112681642580602192077549618037370656866035884147659760586055226183757668965678
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.8839267740152612541602880429592888038581776891498443579475825563188758780504
Short name T27
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.12 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:06:14 PM PDT 23
Peak memory 236700 kb
Host smart-41d4f2b7-bf13-40a9-8498-7a3860876702
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8839267740152612541602880429592888038581776891498443579475825563188758780504 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.8839267740152612541602880429592888038581776891498443579475825563188758780504
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.66479402309098564943864050877088267970049000799941832894543502503864415037559
Short name T16
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Oct 29 02:02:34 PM PDT 23
Finished Oct 29 02:02:48 PM PDT 23
Peak memory 210764 kb
Host smart-e08829f3-d810-4b45-8744-b5b171e1f696
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66479402309098564943864050877088267970049000799941832894543502503864415037559 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.66479402309098564943864050877088267970049000799941832894543502503864415037559
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.11304491769817673510040906440515769570065923514299128484598708473938784070010
Short name T24
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.27 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:03:01 PM PDT 23
Peak memory 213428 kb
Host smart-63591e12-9a45-433b-b052-fe202b1f82a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130449176981767351004090644051576957006592
3514299128484598708473938784070010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1130449176981
7673510040906440515769570065923514299128484598708473938784070010
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.5126642494909950513652678445636501468871944363347906876271115843249959193201
Short name T81
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.19 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:43 PM PDT 23
Peak memory 211168 kb
Host smart-204b9e99-8745-4f3a-91b8-0429c2cf85a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5126642494909950513652678445636501468871944363347906876271115843249959193201 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.5126642494909950513652678445636501468871944363347906876271115843249959193201
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2915659721071938076549433166984725266450096018142339345539039095701353316582
Short name T102
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.97 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:55 PM PDT 23
Peak memory 211616 kb
Host smart-9a0b9c57-8c51-4d77-b1c5-9b7751c907f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915659721071938076549433166984725266450096018142339345539039095701353316582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.rom_ctrl_kmac_err_chk.2915659721071938076549433166984725266450096018142339345539039095701353316582
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.104933746831065894798103968321714428294949923480239713664055366954752952361946
Short name T116
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 211220 kb
Host smart-59bb23bb-4b8f-4763-af41-d2ff31c2e88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104933746831065894798103968321714428294949923480239713664055366954752952361946 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.104933746831065894798103968321714428294949923480239713664055366954752952361946
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.46067593189851119341896473401530582475842656967276656685333098676573732010936
Short name T376
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 29 02:03:17 PM PDT 23
Finished Oct 29 02:03:29 PM PDT 23
Peak memory 210808 kb
Host smart-bbc56ff3-1fc7-4652-a931-9f27b22c2934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46067593189851119341896473401530582475842656967276656685333098676573732010936 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.46067593189851119341896473401530582475842656967276656685333098676573732010936
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.66881193836246437502001520236438421794518022148419905883086796957596780367720
Short name T140
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.21 seconds
Started Oct 29 02:04:31 PM PDT 23
Finished Oct 29 02:05:00 PM PDT 23
Peak memory 212800 kb
Host smart-0db8932c-510f-4b12-8e6f-3ae1bd5296a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66881193836246437502001520236438421794518022148419905883086796957596780367720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.rom_ctrl_smoke.66881193836246437502001520236438421794518022148419905883086796957596780367720
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.7448996425929933826803553810795754120173004582313247559951549457384129317619
Short name T383
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.17 seconds
Started Oct 29 02:01:55 PM PDT 23
Finished Oct 29 02:02:11 PM PDT 23
Peak memory 210700 kb
Host smart-b994d60f-b43f-4331-a684-e1eeb20d9f33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7448996425929933826803553810795754120173004582313247559951549457384129317619 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.7448996425929933826803553810795754120173004582313247559951549457384129317619
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.53263856639947210230050320660917122295220822218265746542593085897141055104131
Short name T392
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 29 02:01:55 PM PDT 23
Finished Oct 29 02:02:08 PM PDT 23
Peak memory 210712 kb
Host smart-e05696f0-4f28-472d-b0ff-4da689e2c41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53263856639947210230050320660917122295220822218265746542593085897141055104131 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.53263856639947210230050320660917122295220822218265746542593085897141055104131
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.98230836444604657897623942073361897044758864061111482840775613375653876124579
Short name T22
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.94 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:03:00 PM PDT 23
Peak memory 210820 kb
Host smart-345af70a-4695-45cf-8f11-661e1bbb694b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98230836444604657897623942073361897044758864061111482840775613375653876124579 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.9823083644460465789762394207336189704475886406111148284077
5613375653876124579
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.66944925064546921463026720926770258149994810748066256546298724263298077515038
Short name T372
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 29 02:02:07 PM PDT 23
Finished Oct 29 02:02:20 PM PDT 23
Peak memory 210740 kb
Host smart-78814a1d-4176-48ca-a74f-c80dba49a0ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66944925064546921463026720926770258149994810748066256546298724263298077515038 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.66944925064546921463026720926770258149994810748066256546298724263298077515038
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.109707761713161358646595242434436341122564071160173625544063864625948721593217
Short name T426
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.61 seconds
Started Oct 29 02:02:16 PM PDT 23
Finished Oct 29 02:06:55 PM PDT 23
Peak memory 218956 kb
Host smart-aa491c4a-90f8-415b-931c-3c40dd10feda
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109707761713161358646595242434436341122564071160173625544063864625948721593217 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.1097077617131613586465952424344363411225640711601736255
44063864625948721593217
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.38867848312102511799682024514469750872529579752493111602814771353008166825558
Short name T384
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.75 seconds
Started Oct 29 02:01:45 PM PDT 23
Finished Oct 29 02:01:59 PM PDT 23
Peak memory 210824 kb
Host smart-b66ce630-b777-4fe4-ae37-d01f79aae7fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38867848312102511799682024514469750872529579752493111602814771353008166825558
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.388678483121025117996820245144697508725295797524931116
02814771353008166825558
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.87124182943000664525178997522187280646688545746765244224738849222159360926653
Short name T414
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.25 seconds
Started Oct 29 02:02:17 PM PDT 23
Finished Oct 29 02:02:37 PM PDT 23
Peak memory 218964 kb
Host smart-3d50022f-8edf-49bb-a216-1d15fae0bb2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87124182943000664525178997522187280646688545746765244224738849222159360926653 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.87124182943000664525178997522187280646688545746765244224738849222159360926653
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.107498511205812958699080020128752480148128428281895247232287925107944121516121
Short name T371
Test name
Test status
Simulation time 3476453456 ps
CPU time 78.19 seconds
Started Oct 29 02:01:54 PM PDT 23
Finished Oct 29 02:03:13 PM PDT 23
Peak memory 210924 kb
Host smart-58c4701f-6d93-4a1d-9932-6bf83e2713d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107498511205812958699080020128752480148128428281895247232287925107944121516121 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.107498511205812958699080020128752480148128428281895247232287925107944121516121
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.81031008011397387749821369379508801973187150015462244412079859408546447101021
Short name T61
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.71 seconds
Started Oct 29 02:02:22 PM PDT 23
Finished Oct 29 02:02:35 PM PDT 23
Peak memory 210640 kb
Host smart-380affcf-2498-461d-97a1-93f7341cbf33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81031008011397387749821369379508801973187150015462244412079859408546447101021 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.81031008011397387749821369379508801973187150015462244412079859408546447101021
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.112889731104869389043458603954694317535614902949286904972128787542046048370624
Short name T412
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.61 seconds
Started Oct 29 02:02:16 PM PDT 23
Finished Oct 29 02:02:29 PM PDT 23
Peak memory 210840 kb
Host smart-e02e8273-5680-4b7b-a75a-89267975ce22
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112889731104869389043458603954694317535614902949286904972128787542046048370624 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.112889731104869389043458603954694317535614902949286904972128787542046048370624
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.95500676125703653576072155968627508757642446716136951553246384699702331823226
Short name T96
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.06 seconds
Started Oct 29 02:02:30 PM PDT 23
Finished Oct 29 02:02:47 PM PDT 23
Peak memory 210688 kb
Host smart-57a50d41-e803-42dc-9e43-f2080e93d9e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95500676125703653576072155968627508757642446716136951553246384699702331823226 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.95500676125703653576072155968627508757642446716136951553246384699702331823226
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.101479762199464294439634027586191682815213218182783726977665824499903779228378
Short name T445
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.05 seconds
Started Oct 29 02:02:33 PM PDT 23
Finished Oct 29 02:02:46 PM PDT 23
Peak memory 213388 kb
Host smart-a8d77cc6-3c73-4d33-b844-cddabace5e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014797621994642944396340275861916828152132
18182783726977665824499903779228378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.101479762199
464294439634027586191682815213218182783726977665824499903779228378
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.8617859139916828366555483823445291144703636946923573986244156213998830730476
Short name T438
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 29 02:02:37 PM PDT 23
Finished Oct 29 02:02:50 PM PDT 23
Peak memory 210792 kb
Host smart-5bc617d4-b952-48b7-866e-60aa49605268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8617859139916828366555483823445291144703636946923573986244156213998830730476 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.8617859139916828366555483823445291144703636946923573986244156213998830730476
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.104000043978229463222431307274025976887747303689698140091368252765182401217375
Short name T429
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 29 02:02:20 PM PDT 23
Finished Oct 29 02:02:33 PM PDT 23
Peak memory 210752 kb
Host smart-f9b102bc-147e-435c-ac0a-c808f26f2b75
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104000043978229463222431307274025976887747303689698140091368252765182401217375 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.104000043978229463222431307274025976887747303689698140091
368252765182401217375
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.27583405385079130414212184317570074699055555196465250133871547950792717541841
Short name T425
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 29 02:02:18 PM PDT 23
Finished Oct 29 02:02:33 PM PDT 23
Peak memory 210824 kb
Host smart-a5add256-4c2d-4bd4-9fd8-6dbe1218002b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583405385079130414212184317570074699055555196465250133871547950792717541841 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.27583405385079130414212184317570074699055555196465250133871547950792717541841
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.8840997432225144985764751914744932607667698136409931872538721145791764125173
Short name T64
Test name
Test status
Simulation time 65914678386 ps
CPU time 271.66 seconds
Started Oct 29 02:02:22 PM PDT 23
Finished Oct 29 02:06:55 PM PDT 23
Peak memory 218780 kb
Host smart-7cdec6cf-be38-4eb9-9691-c3ae710d5c3e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8840997432225144985764751914744932607667698136409931872538721145791764125173 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.884099743222514498576475191474493260766769813640993187253
8721145791764125173
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.16140939767256603881315002453258658997749624655433138555891737752548225165687
Short name T49
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.02 seconds
Started Oct 29 02:02:31 PM PDT 23
Finished Oct 29 02:02:46 PM PDT 23
Peak memory 210844 kb
Host smart-7975bc38-3541-4523-b2db-1fa3a8da7294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16140939767256603881315002453258658997749624655433138555891737752548225165687
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.161409397672566038813150024532586589977496246554331385
55891737752548225165687
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.92024012968085217250186041978207659135088739505347508196889605506327410951267
Short name T68
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.36 seconds
Started Oct 29 02:02:40 PM PDT 23
Finished Oct 29 02:02:57 PM PDT 23
Peak memory 219052 kb
Host smart-f6e6ff89-b5f7-4559-a8b9-db4472dbc3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92024012968085217250186041978207659135088739505347508196889605506327410951267 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.92024012968085217250186041978207659135088739505347508196889605506327410951267
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.109881184530546973795041026832928649665564291087426975926799576508942405755356
Short name T406
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.13 seconds
Started Oct 29 02:02:37 PM PDT 23
Finished Oct 29 02:03:58 PM PDT 23
Peak memory 211004 kb
Host smart-80057cdf-d032-479e-8049-87a24279719e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109881184530546973795041026832928649665564291087426975926799576508942405755356 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.109881184530546973795041026832928649665564291087426975926799576508942405755356
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.23565888398043006095078472479170054729522896640289318683347819821855873390989
Short name T420
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.26 seconds
Started Oct 29 02:03:19 PM PDT 23
Finished Oct 29 02:03:32 PM PDT 23
Peak memory 213368 kb
Host smart-4be1e327-3399-4093-b599-f59d09097603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356588839804300609507847247917005472952289
6640289318683347819821855873390989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.235658883980
43006095078472479170054729522896640289318683347819821855873390989
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.76123429741380886313502289162856712330550725581795398879206547736382896163918
Short name T407
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.3 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:07:56 PM PDT 23
Peak memory 218984 kb
Host smart-42f310c9-770a-44e4-9827-1b72bd8fcf45
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76123429741380886313502289162856712330550725581795398879206547736382896163918 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.7612342974138088631350228916285671233055072558179539887
9206547736382896163918
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.93571538489022473199845661297336474501504208012771625284972466400163337262251
Short name T60
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.51 seconds
Started Oct 29 02:03:18 PM PDT 23
Finished Oct 29 02:03:32 PM PDT 23
Peak memory 210652 kb
Host smart-2975e459-206f-477f-b9a8-27b796b115a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93571538489022473199845661297336474501504208012771625284972466400163337262251
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.93571538489022473199845661297336474501504208012771625
284972466400163337262251
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.60434290205315280733360996492800286475147662043520955412227181684622492969115
Short name T53
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.94 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:03:28 PM PDT 23
Peak memory 219040 kb
Host smart-3c1d2f84-0d0d-4283-a618-5363d38d7fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60434290205315280733360996492800286475147662043520955412227181684622492969115 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.60434290205315280733360996492800286475147662043520955412227181684622492969115
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.9695167525615472426766298859993836128792256888824257108215414970132660998069
Short name T421
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.41 seconds
Started Oct 29 02:03:21 PM PDT 23
Finished Oct 29 02:04:42 PM PDT 23
Peak memory 210932 kb
Host smart-c7850df3-7149-4562-ade3-6cf3e4784f89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9695167525615472426766298859993836128792256888824257108215414970132660998069 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.9695167525615472426766298859993836128792256888824257108215414970132660998069
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.9844203050266575353059863429517458605001967510658409853453970631567363855011
Short name T51
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.2 seconds
Started Oct 29 02:03:20 PM PDT 23
Finished Oct 29 02:03:33 PM PDT 23
Peak memory 213412 kb
Host smart-69e4fd6d-3a68-427c-aa7d-44198286fa13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9844203050266575353059863429517458605001967
510658409853453970631567363855011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.9844203050266
575353059863429517458605001967510658409853453970631567363855011
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.85301788106868035239883046206783798420870873063721443219890897370273096469200
Short name T91
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 29 02:03:17 PM PDT 23
Finished Oct 29 02:03:30 PM PDT 23
Peak memory 210788 kb
Host smart-a8f5c898-61b9-40a8-acd4-b718ef9793f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85301788106868035239883046206783798420870873063721443219890897370273096469200 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.85301788106868035239883046206783798420870873063721443219890897370273096469200
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.83566540228039107997822026069748104357904029731481108686655151614358371726462
Short name T450
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.63 seconds
Started Oct 29 02:03:19 PM PDT 23
Finished Oct 29 02:08:03 PM PDT 23
Peak memory 218876 kb
Host smart-a4f2b1d7-422b-49b6-a874-d10112caaee1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83566540228039107997822026069748104357904029731481108686655151614358371726462 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.8356654022803910799782202606974810435790402973148110868
6655151614358371726462
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.107626810993846450521991696035813113035116370189152346878448483284825884641353
Short name T394
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.65 seconds
Started Oct 29 02:03:18 PM PDT 23
Finished Oct 29 02:03:32 PM PDT 23
Peak memory 210724 kb
Host smart-4ee1574d-5d14-483f-a8b2-f19cb1022ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107626810993846450521991696035813113035116370189152346878448483284825884641353
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.1076268109938464505219916960358131130351163701891523
46878448483284825884641353
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.47563582934235308249607703415214364186972620961642972532714480003449249693119
Short name T48
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.3 seconds
Started Oct 29 02:03:16 PM PDT 23
Finished Oct 29 02:03:33 PM PDT 23
Peak memory 218948 kb
Host smart-13ccbc5b-e8ef-455a-8225-dc9549ddd8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47563582934235308249607703415214364186972620961642972532714480003449249693119 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.47563582934235308249607703415214364186972620961642972532714480003449249693119
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.8588729335563964125013165863586777222210849564540445469374338559727543185516
Short name T368
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.33 seconds
Started Oct 29 02:03:19 PM PDT 23
Finished Oct 29 02:04:40 PM PDT 23
Peak memory 210960 kb
Host smart-503f7a06-9d9d-4c9a-adb6-2f16d7112ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8588729335563964125013165863586777222210849564540445469374338559727543185516 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.8588729335563964125013165863586777222210849564540445469374338559727543185516
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.89099478502311101718202201800208362617902028234843654787399060824359174133216
Short name T437
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.6 seconds
Started Oct 29 02:03:44 PM PDT 23
Finished Oct 29 02:03:58 PM PDT 23
Peak memory 213380 kb
Host smart-0ebce7b9-ed35-42d4-a824-124234703ab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8909947850231110171820220180020836261790202
8234843654787399060824359174133216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.890994785023
11101718202201800208362617902028234843654787399060824359174133216
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.97509508243883565619101123884173335550656487830649463684475054991508178467027
Short name T440
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Oct 29 02:03:25 PM PDT 23
Finished Oct 29 02:03:37 PM PDT 23
Peak memory 210808 kb
Host smart-d8fea69c-dd5a-46ac-8868-58e007fefd70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97509508243883565619101123884173335550656487830649463684475054991508178467027 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.97509508243883565619101123884173335550656487830649463684475054991508178467027
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.366572469660754675796554553502245223289761090793814125156513667727488236000
Short name T433
Test name
Test status
Simulation time 65914678386 ps
CPU time 276.62 seconds
Started Oct 29 02:03:16 PM PDT 23
Finished Oct 29 02:07:53 PM PDT 23
Peak memory 218776 kb
Host smart-9ca1302b-908b-40c0-8819-1d1652caeb44
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366572469660754675796554553502245223289761090793814125156513667727488236000 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.366572469660754675796554553502245223289761090793814125156
513667727488236000
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.26173825951791851549766193164355212582018910544505618568054611793666781860070
Short name T77
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.1 seconds
Started Oct 29 02:03:48 PM PDT 23
Finished Oct 29 02:04:03 PM PDT 23
Peak memory 210796 kb
Host smart-9bab582c-584d-49b0-90dd-e641f7627ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26173825951791851549766193164355212582018910544505618568054611793666781860070
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.26173825951791851549766193164355212582018910544505618
568054611793666781860070
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.104527490148476064235235153743533810798606568283843717479195025077662935977171
Short name T424
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.32 seconds
Started Oct 29 02:03:41 PM PDT 23
Finished Oct 29 02:03:58 PM PDT 23
Peak memory 219044 kb
Host smart-3b040d23-4096-4835-b28b-6a09ba3d7b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104527490148476064235235153743533810798606568283843717479195025077662935977171 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.104527490148476064235235153743533810798606568283843717479195025077662935977171
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.85374713643586314766426596146441190538802186491403135764162736648560558301728
Short name T386
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.31 seconds
Started Oct 29 02:04:01 PM PDT 23
Finished Oct 29 02:04:16 PM PDT 23
Peak memory 213452 kb
Host smart-f4f964fb-661e-4e28-90d0-9d9779b41e35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8537471364358631476642659614644119053880218
6491403135764162736648560558301728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.853747136435
86314766426596146441190538802186491403135764162736648560558301728
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.23545502389583814693408778766361616939991161736333249090857039189175721340791
Short name T58
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:29 PM PDT 23
Peak memory 210792 kb
Host smart-27a59981-e980-40ee-839c-308603ea652d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23545502389583814693408778766361616939991161736333249090857039189175721340791 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.23545502389583814693408778766361616939991161736333249090857039189175721340791
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.109435931074812809890236889274577579175099618117790239773615139508701852150775
Short name T20
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.88 seconds
Started Oct 29 02:03:23 PM PDT 23
Finished Oct 29 02:08:13 PM PDT 23
Peak memory 218932 kb
Host smart-193547d0-690a-4916-874a-de3624c897fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109435931074812809890236889274577579175099618117790239773615139508701852150775 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.109435931074812809890236889274577579175099618117790239
773615139508701852150775
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.9463633830527763768003770324252143173768833434421745641675678936629522700824
Short name T381
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.82 seconds
Started Oct 29 02:04:07 PM PDT 23
Finished Oct 29 02:04:21 PM PDT 23
Peak memory 210804 kb
Host smart-0627ae99-efb1-4b77-bad9-a0a2f5d1622b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9463633830527763768003770324252143173768833434421745641675678936629522700824 -
assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.946363383052776376800377032425214317376883343442174564
1675678936629522700824
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.49525158664353928523508126520256874058266934649607533046984223235522821855934
Short name T428
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.61 seconds
Started Oct 29 02:04:09 PM PDT 23
Finished Oct 29 02:05:29 PM PDT 23
Peak memory 210876 kb
Host smart-967c87c9-c8ea-4b32-8938-cc27918ba350
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49525158664353928523508126520256874058266934649607533046984223235522821855934 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.49525158664353928523508126520256874058266934649607533046984223235522821855934
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.10224082418134995269861623813797109304448084889203439315542979544262716677029
Short name T423
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.2 seconds
Started Oct 29 02:03:50 PM PDT 23
Finished Oct 29 02:04:02 PM PDT 23
Peak memory 213440 kb
Host smart-8004a19c-8e3c-4bce-968b-98dbc75591dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022408241813499526986162381379710930444808
4889203439315542979544262716677029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.102240824181
34995269861623813797109304448084889203439315542979544262716677029
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.34368628501903461385273181900398497280120506661197670601356576578584306196613
Short name T385
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Oct 29 02:03:51 PM PDT 23
Finished Oct 29 02:04:07 PM PDT 23
Peak memory 210832 kb
Host smart-4705780b-4862-4eb6-b234-f1841b3f681b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34368628501903461385273181900398497280120506661197670601356576578584306196613 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.34368628501903461385273181900398497280120506661197670601356576578584306196613
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.48391297095603995744272961116994744703848935125521121890065406319303491077236
Short name T76
Test name
Test status
Simulation time 65914678386 ps
CPU time 274.33 seconds
Started Oct 29 02:04:12 PM PDT 23
Finished Oct 29 02:08:46 PM PDT 23
Peak memory 218820 kb
Host smart-029cf4d9-d308-4132-8d3b-33ade5b0bd95
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48391297095603995744272961116994744703848935125521121890065406319303491077236 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.4839129709560399574427296111699474470384893512552112189
0065406319303491077236
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.67075440662057639224995583618849700732154364279747840772050709814060072978760
Short name T382
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.96 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 210676 kb
Host smart-daff5ac1-0d2f-4403-abbb-009ba682d70b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67075440662057639224995583618849700732154364279747840772050709814060072978760
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.67075440662057639224995583618849700732154364279747840
772050709814060072978760
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.89053673358725471586057407924032340772236290076267423676540774647219464520407
Short name T391
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.32 seconds
Started Oct 29 02:04:15 PM PDT 23
Finished Oct 29 02:04:32 PM PDT 23
Peak memory 219044 kb
Host smart-c95da6ea-a018-4934-85a2-e02388b03136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89053673358725471586057407924032340772236290076267423676540774647219464520407 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.89053673358725471586057407924032340772236290076267423676540774647219464520407
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.20129519944955642161578143200394859961414699252031722541631231626478591547118
Short name T47
Test name
Test status
Simulation time 3476453456 ps
CPU time 81 seconds
Started Oct 29 02:04:12 PM PDT 23
Finished Oct 29 02:05:33 PM PDT 23
Peak memory 210980 kb
Host smart-ba457ed0-9817-427e-a489-c4509cb71c46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129519944955642161578143200394859961414699252031722541631231626478591547118 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.20129519944955642161578143200394859961414699252031722541631231626478591547118
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.34604943101264693886450172796121135283081538767128824821221428508598815864185
Short name T378
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.54 seconds
Started Oct 29 02:04:13 PM PDT 23
Finished Oct 29 02:04:26 PM PDT 23
Peak memory 213364 kb
Host smart-764fc7d0-67f3-42db-bdba-3a70cb261a63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460494310126469388645017279612113528308153
8767128824821221428508598815864185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.346049431012
64693886450172796121135283081538767128824821221428508598815864185
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.55206039587374313131881756185367833197592453525065292136678911825983421418400
Short name T443
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:29 PM PDT 23
Peak memory 210712 kb
Host smart-604b5644-0476-4a24-b9fc-096884795e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55206039587374313131881756185367833197592453525065292136678911825983421418400 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.55206039587374313131881756185367833197592453525065292136678911825983421418400
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.428937652394319752042428909577481622618065320667673581833352120992686992793
Short name T393
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.53 seconds
Started Oct 29 02:03:49 PM PDT 23
Finished Oct 29 02:08:37 PM PDT 23
Peak memory 218920 kb
Host smart-fc619541-c84e-4fb9-a9f0-58cab0d25ec8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428937652394319752042428909577481622618065320667673581833352120992686992793 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.428937652394319752042428909577481622618065320667673581833
352120992686992793
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.10242723134466482316593342481050920566050966867908362127390979397662095839302
Short name T401
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.98 seconds
Started Oct 29 02:04:09 PM PDT 23
Finished Oct 29 02:04:23 PM PDT 23
Peak memory 210808 kb
Host smart-19b3e0cd-70e1-4562-b926-43023f03851e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242723134466482316593342481050920566050966867908362127390979397662095839302
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.10242723134466482316593342481050920566050966867908362
127390979397662095839302
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.79046954937437329057410213120669441003068483679693780571761199719768760213812
Short name T435
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.08 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:33 PM PDT 23
Peak memory 218912 kb
Host smart-7371fd60-ce88-46cd-bbaf-ca529423229f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79046954937437329057410213120669441003068483679693780571761199719768760213812 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.79046954937437329057410213120669441003068483679693780571761199719768760213812
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.9195032643240486932623578652307755665838003128828848639460719485270125562557
Short name T422
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.13 seconds
Started Oct 29 02:04:08 PM PDT 23
Finished Oct 29 02:05:31 PM PDT 23
Peak memory 211012 kb
Host smart-509ab01e-f8d3-4412-8dd7-2496ee15807b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9195032643240486932623578652307755665838003128828848639460719485270125562557 -assert no
postproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.9195032643240486932623578652307755665838003128828848639460719485270125562557
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.64136898163044112401372134202120833665345579134118583140316361326776714234338
Short name T409
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.48 seconds
Started Oct 29 02:04:18 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 213432 kb
Host smart-c3f1cd4a-f67b-436b-b925-bc66c5349432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6413689816304411240137213420212083366534557
9134118583140316361326776714234338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.641368981630
44112401372134202120833665345579134118583140316361326776714234338
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.16181595757635621086011713435363774916391082441684254889085653557837781566796
Short name T387
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 29 02:03:56 PM PDT 23
Finished Oct 29 02:04:10 PM PDT 23
Peak memory 210728 kb
Host smart-8e2da9e5-427b-4e9f-b9ba-2b5d0aa001c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16181595757635621086011713435363774916391082441684254889085653557837781566796 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.16181595757635621086011713435363774916391082441684254889085653557837781566796
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.83621780337574843954109258139848641756490727126398652011849417543420165565697
Short name T427
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.01 seconds
Started Oct 29 02:04:15 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 210828 kb
Host smart-8c56bc9c-d624-4570-9ee9-fc2a1be25ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83621780337574843954109258139848641756490727126398652011849417543420165565697
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.83621780337574843954109258139848641756490727126398652
011849417543420165565697
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.60150267360525505833110162283147739249598134246890954016509633873989606433100
Short name T403
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.42 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 218968 kb
Host smart-391cf7e7-f42e-46bc-a062-893d69587307
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60150267360525505833110162283147739249598134246890954016509633873989606433100 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.60150267360525505833110162283147739249598134246890954016509633873989606433100
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.30857063549774014562064024390607929916610077454073097085992299303306399149761
Short name T21
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.56 seconds
Started Oct 29 02:03:48 PM PDT 23
Finished Oct 29 02:05:10 PM PDT 23
Peak memory 211056 kb
Host smart-818d3735-8072-4c52-aa9e-63c12d45644a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857063549774014562064024390607929916610077454073097085992299303306399149761 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.30857063549774014562064024390607929916610077454073097085992299303306399149761
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.24286768231033703619712527236545361049027089169521357162679444027015046286824
Short name T418
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.16 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:28 PM PDT 23
Peak memory 213432 kb
Host smart-0bc6a9b5-ec8d-48d2-a3ab-3be669e0dff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428676823103370361971252723654536104902708
9169521357162679444027015046286824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.242867682310
33703619712527236545361049027089169521357162679444027015046286824
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.8798051480119820616676255573143196902554264676364155304897709604203274993295
Short name T408
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Oct 29 02:03:50 PM PDT 23
Finished Oct 29 02:04:03 PM PDT 23
Peak memory 210808 kb
Host smart-1d2256ec-16bf-479f-9b73-2a50f273f0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8798051480119820616676255573143196902554264676364155304897709604203274993295 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.8798051480119820616676255573143196902554264676364155304897709604203274993295
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.70985269171356808239081686214975436357845395787180377191835698221100666191641
Short name T62
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.07 seconds
Started Oct 29 02:04:22 PM PDT 23
Finished Oct 29 02:09:04 PM PDT 23
Peak memory 218944 kb
Host smart-88ee78c0-38b8-4997-ac1e-d0b588a71cf8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70985269171356808239081686214975436357845395787180377191835698221100666191641 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.7098526917135680823908168621497543635784539578718037719
1835698221100666191641
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.82733834093849686241176534848661792404126123617062920800106724622556191639593
Short name T379
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.97 seconds
Started Oct 29 02:04:13 PM PDT 23
Finished Oct 29 02:04:28 PM PDT 23
Peak memory 210744 kb
Host smart-53764739-5aec-4726-8eab-e953f3d0b509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82733834093849686241176534848661792404126123617062920800106724622556191639593
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.82733834093849686241176534848661792404126123617062920
800106724622556191639593
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.70897933877118032435744843030992876470447795148700516012695423489760303697465
Short name T432
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.66 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 218908 kb
Host smart-0d6376f1-b2e0-49c0-befc-1acbc3655278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70897933877118032435744843030992876470447795148700516012695423489760303697465 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.70897933877118032435744843030992876470447795148700516012695423489760303697465
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.53300837113127509722998182596916535908987387808273667907895397135073058482747
Short name T388
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.41 seconds
Started Oct 29 02:03:47 PM PDT 23
Finished Oct 29 02:05:07 PM PDT 23
Peak memory 211032 kb
Host smart-84352c02-fe0a-421c-aded-00467a1a5ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53300837113127509722998182596916535908987387808273667907895397135073058482747 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.53300837113127509722998182596916535908987387808273667907895397135073058482747
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.73179379817784153038969122150283305429875498310334898943784544400445831092197
Short name T449
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.24 seconds
Started Oct 29 02:04:08 PM PDT 23
Finished Oct 29 02:04:20 PM PDT 23
Peak memory 213432 kb
Host smart-51742496-3267-46a7-a326-f3d62406569f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7317937981778415303896912215028330542987549
8310334898943784544400445831092197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.731793798177
84153038969122150283305429875498310334898943784544400445831092197
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.32167512821558588861693167628630827198639758431414825326321281110504180501972
Short name T59
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.91 seconds
Started Oct 29 02:04:13 PM PDT 23
Finished Oct 29 02:04:25 PM PDT 23
Peak memory 210820 kb
Host smart-c1b377e5-4158-41b5-9a4b-76d645c0abe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167512821558588861693167628630827198639758431414825326321281110504180501972 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.32167512821558588861693167628630827198639758431414825326321281110504180501972
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.64693353199984457127962803190747983137414423028144084245977878102082249311517
Short name T18
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.67 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:09:02 PM PDT 23
Peak memory 218924 kb
Host smart-00ef94d8-e023-4f33-b585-90f6e369ad91
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64693353199984457127962803190747983137414423028144084245977878102082249311517 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.6469335319998445712796280319074798313741442302814408424
5977878102082249311517
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.83852521564393530877311028012878318713295912357756128093580285322167630858292
Short name T99
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.19 seconds
Started Oct 29 02:04:21 PM PDT 23
Finished Oct 29 02:04:36 PM PDT 23
Peak memory 210800 kb
Host smart-e19e2861-63d2-4ca2-9560-a5188efaa9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83852521564393530877311028012878318713295912357756128093580285322167630858292
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.83852521564393530877311028012878318713295912357756128
093580285322167630858292
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.89473596112542090329482199456128778076229407752648739933417675950234387753005
Short name T415
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Oct 29 02:04:09 PM PDT 23
Finished Oct 29 02:04:26 PM PDT 23
Peak memory 219044 kb
Host smart-ca136163-8d2d-4d9f-be1e-6387f68e5398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89473596112542090329482199456128778076229407752648739933417675950234387753005 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.89473596112542090329482199456128778076229407752648739933417675950234387753005
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.79557012120528818501001804340636077025935777810335726725280340624443798388192
Short name T431
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.27 seconds
Started Oct 29 02:04:18 PM PDT 23
Finished Oct 29 02:05:39 PM PDT 23
Peak memory 211056 kb
Host smart-54d15829-0bf7-4de5-98e1-16dcfbb08053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79557012120528818501001804340636077025935777810335726725280340624443798388192 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.79557012120528818501001804340636077025935777810335726725280340624443798388192
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.103771024513817910077149189165109031942152674354627723620124139027411984786835
Short name T390
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.37 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:28 PM PDT 23
Peak memory 213392 kb
Host smart-28980ba1-d33d-4d89-bfa9-c3d3bcb5bdea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037710245138179100771491891651090319421526
74354627723620124139027411984786835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.10377102451
3817910077149189165109031942152674354627723620124139027411984786835
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.14088485862920191533903259818447667837688491915307948905779093835719540521410
Short name T404
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:04:26 PM PDT 23
Peak memory 210728 kb
Host smart-d514b525-5b04-47d7-896e-1e6a2008b587
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088485862920191533903259818447667837688491915307948905779093835719540521410 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.14088485862920191533903259818447667837688491915307948905779093835719540521410
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.92978114980336818541074859823267873991576336458302517909781821489701144611268
Short name T74
Test name
Test status
Simulation time 65914678386 ps
CPU time 280.69 seconds
Started Oct 29 02:03:46 PM PDT 23
Finished Oct 29 02:08:27 PM PDT 23
Peak memory 218808 kb
Host smart-fb43ed1e-883e-4e2a-a310-b9d180c61b99
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92978114980336818541074859823267873991576336458302517909781821489701144611268 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.9297811498033681854107485982326787399157633645830251790
9781821489701144611268
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.100414088975280047595521906057474434535677281100852275426176287578473888724457
Short name T101
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.04 seconds
Started Oct 29 02:03:48 PM PDT 23
Finished Oct 29 02:04:03 PM PDT 23
Peak memory 210820 kb
Host smart-942dac6d-2940-46e3-8b46-7510f12cd1d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100414088975280047595521906057474434535677281100852275426176287578473888724457
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.1004140889752800475955219060574744345356772811008522
75426176287578473888724457
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.101061199860511493636244670134700515084421142593836451993129724362081138208227
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.49 seconds
Started Oct 29 02:04:13 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 219048 kb
Host smart-143236cf-cb95-4afc-9e4d-be9b7db8ecde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101061199860511493636244670134700515084421142593836451993129724362081138208227 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.101061199860511493636244670134700515084421142593836451993129724362081138208227
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.81007122028718293604578462077108224560516914799195601580556768443887909092085
Short name T375
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.66 seconds
Started Oct 29 02:04:11 PM PDT 23
Finished Oct 29 02:05:32 PM PDT 23
Peak memory 211028 kb
Host smart-105b0ae0-696a-4ca1-a095-af1bdaac87ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81007122028718293604578462077108224560516914799195601580556768443887909092085 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.81007122028718293604578462077108224560516914799195601580556768443887909092085
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.104785045853864592680015976364492799019808222414994144766596359056640519271043
Short name T88
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.13 seconds
Started Oct 29 02:02:15 PM PDT 23
Finished Oct 29 02:02:28 PM PDT 23
Peak memory 210844 kb
Host smart-d3cd57c9-6fe1-4f00-bcf9-1c8640347a62
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104785045853864592680015976364492799019808222414994144766596359056640519271043 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.104785045853864592680015976364492799019808222414994144766596359056640519271043
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.94987523182675054414868066657768706889536926870818028182341946316784853370302
Short name T19
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Oct 29 02:02:33 PM PDT 23
Finished Oct 29 02:02:46 PM PDT 23
Peak memory 210844 kb
Host smart-84b60131-e374-4aee-b7bd-80ed59306001
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94987523182675054414868066657768706889536926870818028182341946316784853370302 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.94987523182675054414868066657768706889536926870818028182341946316784853370302
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.58721915034690537679912447062246341652785969121017061511622705960301151063826
Short name T95
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.63 seconds
Started Oct 29 02:02:15 PM PDT 23
Finished Oct 29 02:02:31 PM PDT 23
Peak memory 210796 kb
Host smart-9ecf73cb-5739-4ea4-b9be-653ae282d650
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58721915034690537679912447062246341652785969121017061511622705960301151063826 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.58721915034690537679912447062246341652785969121017061511622705960301151063826
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.110856408479514654057545460726970415779926388344722736734292986261833389661115
Short name T410
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.19 seconds
Started Oct 29 02:02:17 PM PDT 23
Finished Oct 29 02:02:33 PM PDT 23
Peak memory 213452 kb
Host smart-b5a67bb2-4134-40d0-8e21-e86ae19b30df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108564084795146540575454607269704157799263
88344722736734292986261833389661115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.110856408479
514654057545460726970415779926388344722736734292986261833389661115
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.32784275285555572491479428043081547934559503653584248965532335572505008349074
Short name T70
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Oct 29 02:02:11 PM PDT 23
Finished Oct 29 02:02:24 PM PDT 23
Peak memory 210816 kb
Host smart-be0ad842-7111-47a1-a3fb-f709a596048e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32784275285555572491479428043081547934559503653584248965532335572505008349074 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.32784275285555572491479428043081547934559503653584248965532335572505008349074
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.50926655144534785557735427739185292188578043392012800876527119489533067915800
Short name T389
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Oct 29 02:02:36 PM PDT 23
Finished Oct 29 02:02:49 PM PDT 23
Peak memory 210776 kb
Host smart-c2634783-1cbb-4c08-acea-ea4c592c5ab9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50926655144534785557735427739185292188578043392012800876527119489533067915800 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.5092665514453478555773542773918529218857804339201280087652
7119489533067915800
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.56590309045418419728061909570379036949763870050849877569100666915722319595687
Short name T90
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 29 02:02:15 PM PDT 23
Finished Oct 29 02:02:27 PM PDT 23
Peak memory 210820 kb
Host smart-794b718e-d4d3-4402-801d-307e92b56541
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56590309045418419728061909570379036949763870050849877569100666915722319595687 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.56590309045418419728061909570379036949763870050849877569100666915722319595687
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.75292895360046972349835111780802650419750998724578099792003355935798922243698
Short name T398
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.72 seconds
Started Oct 29 02:02:16 PM PDT 23
Finished Oct 29 02:07:00 PM PDT 23
Peak memory 218964 kb
Host smart-a471f737-fc4f-4cad-90cb-c90ce386b043
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75292895360046972349835111780802650419750998724578099792003355935798922243698 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.75292895360046972349835111780802650419750998724578099792
003355935798922243698
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.44017907700028540002313282518931077874185933420337868200121649375949972498099
Short name T369
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.9 seconds
Started Oct 29 02:02:37 PM PDT 23
Finished Oct 29 02:02:52 PM PDT 23
Peak memory 210720 kb
Host smart-b7d7acdd-8934-4b8c-996f-f8942aee28a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44017907700028540002313282518931077874185933420337868200121649375949972498099
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.440179077000285400023132825189310778741859334203378682
00121649375949972498099
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.9589043635125884721814662159489608942236238054378032158197103646101649363743
Short name T67
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.91 seconds
Started Oct 29 02:02:31 PM PDT 23
Finished Oct 29 02:02:48 PM PDT 23
Peak memory 218984 kb
Host smart-6c2e30e0-5ac2-4821-bbb1-3a2c03f4552e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9589043635125884721814662159489608942236238054378032158197103646101649363743 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.9589043635125884721814662159489608942236238054378032158197103646101649363743
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.78000734984215580240434003770716504862589994501128976777756844909635050202538
Short name T366
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.3 seconds
Started Oct 29 02:02:17 PM PDT 23
Finished Oct 29 02:03:41 PM PDT 23
Peak memory 211048 kb
Host smart-adf9b887-1cf5-4a4b-9fa9-5a54189ddff8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78000734984215580240434003770716504862589994501128976777756844909635050202538 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.78000734984215580240434003770716504862589994501128976777756844909635050202538
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.50933833995878137865078675908633310664816871062248876350664682098615926183254
Short name T396
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Oct 29 02:02:26 PM PDT 23
Finished Oct 29 02:02:39 PM PDT 23
Peak memory 210808 kb
Host smart-70a66bf8-ae3b-4266-b611-f59ae33272bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50933833995878137865078675908633310664816871062248876350664682098615926183254 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.50933833995878137865078675908633310664816871062248876350664682098615926183254
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.111806786310469773176244331043844469594952695666651778579387562457496439200850
Short name T446
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.99 seconds
Started Oct 29 02:02:22 PM PDT 23
Finished Oct 29 02:02:35 PM PDT 23
Peak memory 210640 kb
Host smart-3106fbfb-fa96-42fd-8c8f-a50f823df30e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111806786310469773176244331043844469594952695666651778579387562457496439200850 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.111806786310469773176244331043844469594952695666651778579387562457496439200850
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.62102342676475131400424698624671560848691437481179611760954651991561246353394
Short name T69
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.51 seconds
Started Oct 29 02:02:22 PM PDT 23
Finished Oct 29 02:02:39 PM PDT 23
Peak memory 210796 kb
Host smart-ac0bb36a-26ba-4887-83e2-5a825572ae0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62102342676475131400424698624671560848691437481179611760954651991561246353394 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.62102342676475131400424698624671560848691437481179611760954651991561246353394
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.12403655271533794982050428838143954528398825305324727580174349572772683142689
Short name T373
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.19 seconds
Started Oct 29 02:02:39 PM PDT 23
Finished Oct 29 02:02:52 PM PDT 23
Peak memory 213300 kb
Host smart-37829ef4-c917-4cf5-8b33-4bf854c0404f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240365527153379498205042883814395452839882
5305324727580174349572772683142689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1240365527153
3794982050428838143954528398825305324727580174349572772683142689
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.77152294951964002043833378080520349683698736340341758624682542442816889433356
Short name T94
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Oct 29 02:02:29 PM PDT 23
Finished Oct 29 02:02:44 PM PDT 23
Peak memory 210828 kb
Host smart-a9f4612f-0bdc-4a36-a21b-9cb588da4905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77152294951964002043833378080520349683698736340341758624682542442816889433356 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.77152294951964002043833378080520349683698736340341758624682542442816889433356
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.97494673570737237942925900504305036833150093751191072644096516678824577245507
Short name T374
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.84 seconds
Started Oct 29 02:02:28 PM PDT 23
Finished Oct 29 02:02:40 PM PDT 23
Peak memory 210804 kb
Host smart-fee4199f-9326-4a11-bf92-237dd0060bee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97494673570737237942925900504305036833150093751191072644096516678824577245507 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.9749467357073723794292590050430503683315009375119107264409
6516678824577245507
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.38842537195860590936472983795464873396525348952177682807869110875664521663170
Short name T97
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.06 seconds
Started Oct 29 02:02:34 PM PDT 23
Finished Oct 29 02:02:47 PM PDT 23
Peak memory 210796 kb
Host smart-32accfb7-9e03-4b49-8b9e-b76f920395f9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842537195860590936472983795464873396525348952177682807869110875664521663170 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.38842537195860590936472983795464873396525348952177682807869110875664521663170
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.6337000538954355426778038739797485250281736541420429460420046345850462191917
Short name T405
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.06 seconds
Started Oct 29 02:02:27 PM PDT 23
Finished Oct 29 02:07:08 PM PDT 23
Peak memory 218924 kb
Host smart-93d1f07a-3bfd-4fce-9ad4-6636c4be7a21
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6337000538954355426778038739797485250281736541420429460420046345850462191917 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.633700053895435542677803873979748525028173654142042946042
0046345850462191917
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.82085610991422449580722981327915912559567467892986136898135343089101976141714
Short name T399
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.01 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:03:02 PM PDT 23
Peak memory 210824 kb
Host smart-1ea209ae-2400-47cb-a24c-865722b460be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82085610991422449580722981327915912559567467892986136898135343089101976141714
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.820856109914224495807229813279159125595674678929861368
98135343089101976141714
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.74016565329566030731769397818849932156548052248800428433185200795995987972882
Short name T54
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.01 seconds
Started Oct 29 02:02:16 PM PDT 23
Finished Oct 29 02:02:33 PM PDT 23
Peak memory 219060 kb
Host smart-f849a156-a128-47ed-bbd3-10fb3fb4f62f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74016565329566030731769397818849932156548052248800428433185200795995987972882 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.74016565329566030731769397818849932156548052248800428433185200795995987972882
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.103418460019693450724549328152880888569431544517046557461272771908490087829041
Short name T50
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.49 seconds
Started Oct 29 02:02:17 PM PDT 23
Finished Oct 29 02:03:41 PM PDT 23
Peak memory 211040 kb
Host smart-83db5da3-a54a-4ff8-b5d4-8a461356b468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103418460019693450724549328152880888569431544517046557461272771908490087829041 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.103418460019693450724549328152880888569431544517046557461272771908490087829041
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2421468646542004285654216304636400287168421866022681660543165754989242824895
Short name T377
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.28 seconds
Started Oct 29 02:02:46 PM PDT 23
Finished Oct 29 02:02:59 PM PDT 23
Peak memory 210808 kb
Host smart-26bf6f7a-5aad-4e67-8da6-1d83f037482e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421468646542004285654216304636400287168421866022681660543165754989242824895 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.2421468646542004285654216304636400287168421866022681660543165754989242824895
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.94119285997259428807621874244483710716410075515409984970192213062398122114396
Short name T87
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Oct 29 02:02:54 PM PDT 23
Finished Oct 29 02:03:07 PM PDT 23
Peak memory 210796 kb
Host smart-c308351f-6868-4c4d-a87a-545427f29ed1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94119285997259428807621874244483710716410075515409984970192213062398122114396 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.94119285997259428807621874244483710716410075515409984970192213062398122114396
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.109907154046658960318422584105740244001425057966152204171480765677933848001485
Short name T439
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.35 seconds
Started Oct 29 02:02:53 PM PDT 23
Finished Oct 29 02:03:09 PM PDT 23
Peak memory 210796 kb
Host smart-74277dc3-0bba-49a1-bb52-289857cb5ec1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109907154046658960318422584105740244001425057966152204171480765677933848001485 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.109907154046658960318422584105740244001425057966152204171480765677933848001485
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.27911262963090507219380569449564681954992045477704020166023118238265402428851
Short name T447
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.51 seconds
Started Oct 29 02:02:30 PM PDT 23
Finished Oct 29 02:02:45 PM PDT 23
Peak memory 213448 kb
Host smart-07d4ceb0-67b7-4fcf-9ce6-df977e34f06c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791126296309050721938056944956468195499204
5477704020166023118238265402428851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2791126296309
0507219380569449564681954992045477704020166023118238265402428851
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.36764279872509158877031790963423626663368684418027591940135953080898673555479
Short name T395
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.87 seconds
Started Oct 29 02:02:53 PM PDT 23
Finished Oct 29 02:03:05 PM PDT 23
Peak memory 210808 kb
Host smart-d31b1fd7-d054-45d8-84ef-e12fa11e9c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36764279872509158877031790963423626663368684418027591940135953080898673555479 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.36764279872509158877031790963423626663368684418027591940135953080898673555479
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.44288774113817887469615281170845303587370195594576648210818766990565556446162
Short name T92
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.88 seconds
Started Oct 29 02:02:53 PM PDT 23
Finished Oct 29 02:03:05 PM PDT 23
Peak memory 210808 kb
Host smart-7836edf3-ea07-4b27-9c55-a65f71b376a2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44288774113817887469615281170845303587370195594576648210818766990565556446162 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.4428877411381788746961528117084530358737019559457664821081
8766990565556446162
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.11071840895161970507086815529733375719414045399304380555299109519365156818564
Short name T441
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.94 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:03:01 PM PDT 23
Peak memory 210816 kb
Host smart-c3875862-6d2a-4e14-bdcd-41ec93de6ddb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071840895161970507086815529733375719414045399304380555299109519365156818564 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.11071840895161970507086815529733375719414045399304380555299109519365156818564
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.22450170171182464176021608445779509695472988919849352468076697872502136436022
Short name T400
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.58 seconds
Started Oct 29 02:02:19 PM PDT 23
Finished Oct 29 02:07:06 PM PDT 23
Peak memory 218880 kb
Host smart-49225f39-b7ee-4d02-a94e-c860eb3d284f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22450170171182464176021608445779509695472988919849352468076697872502136436022 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.22450170171182464176021608445779509695472988919849352468
076697872502136436022
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.109033585553737585355215869752397915464230222281823726356584619646410238640016
Short name T79
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.24 seconds
Started Oct 29 02:02:46 PM PDT 23
Finished Oct 29 02:03:00 PM PDT 23
Peak memory 210808 kb
Host smart-899c865b-518b-4af3-810b-10aa849e796d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109033585553737585355215869752397915464230222281823726356584619646410238640016
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.10903358555373758535521586975239791546423022228182372
6356584619646410238640016
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.89722159661954500532526429348076674214443489569097666964312411099627138198685
Short name T65
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.17 seconds
Started Oct 29 02:02:33 PM PDT 23
Finished Oct 29 02:02:50 PM PDT 23
Peak memory 219044 kb
Host smart-bd48514b-99cf-4dd4-b3a8-23b5ee062f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89722159661954500532526429348076674214443489569097666964312411099627138198685 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.89722159661954500532526429348076674214443489569097666964312411099627138198685
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.96707140618277682799229956274988816152355536889304183785405263818198896924900
Short name T98
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.11 seconds
Started Oct 29 02:02:54 PM PDT 23
Finished Oct 29 02:04:14 PM PDT 23
Peak memory 211020 kb
Host smart-27555f0e-ccd4-48e0-b502-8a3e35b0d905
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96707140618277682799229956274988816152355536889304183785405263818198896924900 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.96707140618277682799229956274988816152355536889304183785405263818198896924900
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.113432107113556072782728242613234462111309999938007564247194454333553491450659
Short name T55
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.31 seconds
Started Oct 29 02:02:51 PM PDT 23
Finished Oct 29 02:03:04 PM PDT 23
Peak memory 213444 kb
Host smart-52175203-ea54-4d5e-95f6-2974fec4b515
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134321071135560727827282426132344621113099
99938007564247194454333553491450659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.113432107113
556072782728242613234462111309999938007564247194454333553491450659
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.107442163673518449342156720585905683750092490311099300951395909212650770809483
Short name T71
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Oct 29 02:02:58 PM PDT 23
Finished Oct 29 02:03:10 PM PDT 23
Peak memory 210808 kb
Host smart-cdfa5b23-982d-47f4-ac8c-affffa8e77fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107442163673518449342156720585905683750092490311099300951395909212650770809483 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.107442163673518449342156720585905683750092490311099300951395909212650770809483
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.56439258487600122657860676678135630499432446683162573609180854356648822572839
Short name T73
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.3 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 218956 kb
Host smart-2d01f02f-1654-4930-aa10-0a84048da249
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56439258487600122657860676678135630499432446683162573609180854356648822572839 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.56439258487600122657860676678135630499432446683162573609
180854356648822572839
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.16755845583729822971417817106754705203312099749150699325824329621684898334667
Short name T78
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.37 seconds
Started Oct 29 02:02:51 PM PDT 23
Finished Oct 29 02:03:06 PM PDT 23
Peak memory 210788 kb
Host smart-51fcdf06-ec01-4a06-925d-63837bafc407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16755845583729822971417817106754705203312099749150699325824329621684898334667
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.167558455837298229714178171067547052033120997491506993
25824329621684898334667
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.28319566291712513602182413309619794776882020950664221496233499333816690118642
Short name T30
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.93 seconds
Started Oct 29 02:02:50 PM PDT 23
Finished Oct 29 02:03:06 PM PDT 23
Peak memory 219032 kb
Host smart-a787697a-a9eb-451d-b8f2-6b957909b53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28319566291712513602182413309619794776882020950664221496233499333816690118642 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.28319566291712513602182413309619794776882020950664221496233499333816690118642
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.74189774768434800251566424282165262813821995561967818302611390997986885416060
Short name T436
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.7 seconds
Started Oct 29 02:03:07 PM PDT 23
Finished Oct 29 02:04:28 PM PDT 23
Peak memory 211000 kb
Host smart-04b9b85e-fb3d-495f-bca2-b5a57629ae4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74189774768434800251566424282165262813821995561967818302611390997986885416060 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.74189774768434800251566424282165262813821995561967818302611390997986885416060
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.43950929160195904007588854562095350049597475249668661894468533838933530647591
Short name T434
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.02 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:03:24 PM PDT 23
Peak memory 213456 kb
Host smart-3ca6b313-068b-47d0-b5e7-de73326ba4b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4395092916019590400758885456209535004959747
5249668661894468533838933530647591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.4395092916019
5904007588854562095350049597475249668661894468533838933530647591
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.11303116990233268180858276826861478287208196505616982537352217837040387928193
Short name T370
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.86 seconds
Started Oct 29 02:03:07 PM PDT 23
Finished Oct 29 02:03:19 PM PDT 23
Peak memory 210788 kb
Host smart-ac49feb0-51f3-4116-91e5-d1d709a67b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11303116990233268180858276826861478287208196505616982537352217837040387928193 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.11303116990233268180858276826861478287208196505616982537352217837040387928193
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.113463812315664786365174395957989065030114130894671669101749527103730926019676
Short name T63
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.32 seconds
Started Oct 29 02:02:53 PM PDT 23
Finished Oct 29 02:07:36 PM PDT 23
Peak memory 218924 kb
Host smart-c990bd3b-5353-4e9b-86dc-92a3451f9c6a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113463812315664786365174395957989065030114130894671669101749527103730926019676 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.1134638123156647863651743959579890650301141308946716691
01749527103730926019676
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.91378522442546096857060365295955860032772384716593877500856971884280891342025
Short name T417
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.16 seconds
Started Oct 29 02:02:52 PM PDT 23
Finished Oct 29 02:03:08 PM PDT 23
Peak memory 219044 kb
Host smart-ec2b4421-3c4d-433c-bbc4-83c159088c8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91378522442546096857060365295955860032772384716593877500856971884280891342025 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.91378522442546096857060365295955860032772384716593877500856971884280891342025
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.114665355552489325815578425274477582568943672908277560319604829338361818280047
Short name T442
Test name
Test status
Simulation time 3476453456 ps
CPU time 77.85 seconds
Started Oct 29 02:02:53 PM PDT 23
Finished Oct 29 02:04:11 PM PDT 23
Peak memory 210924 kb
Host smart-5aafa65d-5c29-4e6e-bb95-4358ff0543a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114665355552489325815578425274477582568943672908277560319604829338361818280047 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.114665355552489325815578425274477582568943672908277560319604829338361818280047
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.24090427042249705338046820833931241747799334556020467077238524110060306344977
Short name T380
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.15 seconds
Started Oct 29 02:03:08 PM PDT 23
Finished Oct 29 02:03:20 PM PDT 23
Peak memory 213368 kb
Host smart-2dc37e08-0dfd-430f-a722-8b4e1d74b70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409042704224970533804682083393124174779933
4556020467077238524110060306344977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2409042704224
9705338046820833931241747799334556020467077238524110060306344977
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.108398667887631686761800977393040493433432686952887018964261935398771732242107
Short name T72
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Oct 29 02:02:57 PM PDT 23
Finished Oct 29 02:03:09 PM PDT 23
Peak memory 210808 kb
Host smart-0e04a028-6d4d-4072-aa3b-8313d9530aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108398667887631686761800977393040493433432686952887018964261935398771732242107 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.108398667887631686761800977393040493433432686952887018964261935398771732242107
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.114833698691322788471604720375355364173148907005268216656812297510473290322520
Short name T430
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.47 seconds
Started Oct 29 02:03:07 PM PDT 23
Finished Oct 29 02:07:46 PM PDT 23
Peak memory 218924 kb
Host smart-e4dd7997-c000-4112-9277-0d7237fbceca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114833698691322788471604720375355364173148907005268216656812297510473290322520 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.1148336986913227884716047203753553641731489070052682166
56812297510473290322520
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.113609375227308553209197765969838092403783059534296051052602840441043778869853
Short name T57
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.15 seconds
Started Oct 29 02:02:56 PM PDT 23
Finished Oct 29 02:03:10 PM PDT 23
Peak memory 210808 kb
Host smart-2bd210b2-3dfe-4a64-afc7-8901c9340b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113609375227308553209197765969838092403783059534296051052602840441043778869853
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.11360937522730855320919776596983809240378305953429605
1052602840441043778869853
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.66976676865024765781676032629351841935356053216183756234914664364809185088472
Short name T52
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.78 seconds
Started Oct 29 02:03:07 PM PDT 23
Finished Oct 29 02:03:23 PM PDT 23
Peak memory 218996 kb
Host smart-0a6bab3a-32e9-42e9-8aac-02f68bb73142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66976676865024765781676032629351841935356053216183756234914664364809185088472 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.66976676865024765781676032629351841935356053216183756234914664364809185088472
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.96175590860584779517338254556836297949492662147281301379836988387410245386289
Short name T444
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.19 seconds
Started Oct 29 02:02:56 PM PDT 23
Finished Oct 29 02:04:17 PM PDT 23
Peak memory 211032 kb
Host smart-27422762-b2c8-48f5-8953-e6849b602892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96175590860584779517338254556836297949492662147281301379836988387410245386289 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.96175590860584779517338254556836297949492662147281301379836988387410245386289
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3423649495725483716709595248479590870246088856662925296940221493596136706030
Short name T416
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.29 seconds
Started Oct 29 02:02:51 PM PDT 23
Finished Oct 29 02:03:03 PM PDT 23
Peak memory 213400 kb
Host smart-abb4a4bf-0c6a-4bcc-86f4-59f30cc812e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423649495725483716709595248479590870246088
856662925296940221493596136706030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.34236494957254
83716709595248479590870246088856662925296940221493596136706030
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.45542482054735821664328529563414532521011183570762992077800541350804826987299
Short name T100
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.8 seconds
Started Oct 29 02:02:48 PM PDT 23
Finished Oct 29 02:03:00 PM PDT 23
Peak memory 210820 kb
Host smart-4723ad7b-5144-425c-b065-9f2dce8d7d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45542482054735821664328529563414532521011183570762992077800541350804826987299 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.45542482054735821664328529563414532521011183570762992077800541350804826987299
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.60108246521504946577003925604351984224850363071673255812985949805095029555281
Short name T31
Test name
Test status
Simulation time 65914678386 ps
CPU time 278.18 seconds
Started Oct 29 02:02:52 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 218956 kb
Host smart-732b0c3f-4ac6-4df8-a6a9-df6f0945ae10
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60108246521504946577003925604351984224850363071673255812985949805095029555281 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.60108246521504946577003925604351984224850363071673255812
985949805095029555281
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.79676438505128335207421770676764848651369501022045133637493534906428958952580
Short name T448
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.21 seconds
Started Oct 29 02:02:54 PM PDT 23
Finished Oct 29 02:03:08 PM PDT 23
Peak memory 210712 kb
Host smart-3dcae6d5-6d85-4755-a2ef-a36f4d4821fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79676438505128335207421770676764848651369501022045133637493534906428958952580
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.796764385051283352074217706767648486513695010220451336
37493534906428958952580
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.8651621080207347757170032404202901644688744959952731759454225047593305389894
Short name T397
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.57 seconds
Started Oct 29 02:02:52 PM PDT 23
Finished Oct 29 02:03:08 PM PDT 23
Peak memory 218948 kb
Host smart-45290e92-b7b9-4c35-b59d-2ae0c1b28625
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8651621080207347757170032404202901644688744959952731759454225047593305389894 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.8651621080207347757170032404202901644688744959952731759454225047593305389894
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.90976512729028112140015059072952806622735287999920227215234539860403673130467
Short name T93
Test name
Test status
Simulation time 3476453456 ps
CPU time 79.42 seconds
Started Oct 29 02:02:52 PM PDT 23
Finished Oct 29 02:04:11 PM PDT 23
Peak memory 210968 kb
Host smart-9ad87d24-683a-475b-b8b1-e07035cdb35d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90976512729028112140015059072952806622735287999920227215234539860403673130467 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.90976512729028112140015059072952806622735287999920227215234539860403673130467
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.50326402849032622185900761262825428135729802650717053774243074033645282800577
Short name T56
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.26 seconds
Started Oct 29 02:03:16 PM PDT 23
Finished Oct 29 02:03:28 PM PDT 23
Peak memory 213360 kb
Host smart-4f85c54a-ec74-4e52-9542-d086d9dcaf48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5032640284903262218590076126282542813572980
2650717053774243074033645282800577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.5032640284903
2622185900761262825428135729802650717053774243074033645282800577
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.42228617007302717646364197662704123963724873093332722715958400114163965724863
Short name T413
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.3 seconds
Started Oct 29 02:03:18 PM PDT 23
Finished Oct 29 02:03:31 PM PDT 23
Peak memory 210808 kb
Host smart-3b0e2e52-737b-4125-a810-a1168fc58470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42228617007302717646364197662704123963724873093332722715958400114163965724863 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.42228617007302717646364197662704123963724873093332722715958400114163965724863
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.62727829670036357006880077688125619012296725259803109084718294193931514366748
Short name T419
Test name
Test status
Simulation time 65914678386 ps
CPU time 277.88 seconds
Started Oct 29 02:02:51 PM PDT 23
Finished Oct 29 02:07:30 PM PDT 23
Peak memory 218968 kb
Host smart-4d17b37c-c0bf-448f-ad6d-b28bb99b1023
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62727829670036357006880077688125619012296725259803109084718294193931514366748 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.62727829670036357006880077688125619012296725259803109084
718294193931514366748
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.23315533427485387768525737135115607829772990426294250801435430492640644397283
Short name T402
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.96 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:03:26 PM PDT 23
Peak memory 210852 kb
Host smart-2cffbbcd-813c-42a7-b97d-d0777b8dd3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23315533427485387768525737135115607829772990426294250801435430492640644397283
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.233155334274853877685257371351156078297729904262942508
01435430492640644397283
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.73068684985974557336652438146974926334239074022368438593353267971497084862417
Short name T66
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.75 seconds
Started Oct 29 02:02:50 PM PDT 23
Finished Oct 29 02:03:06 PM PDT 23
Peak memory 219032 kb
Host smart-136ceffb-6fc9-4cdd-8cd6-af9adc5c9e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73068684985974557336652438146974926334239074022368438593353267971497084862417 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.73068684985974557336652438146974926334239074022368438593353267971497084862417
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.53954643051898773048842579164635233963518293392746537134673647778300934663122
Short name T367
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.05 seconds
Started Oct 29 02:03:12 PM PDT 23
Finished Oct 29 02:04:33 PM PDT 23
Peak memory 211036 kb
Host smart-df1637a6-355c-4517-bbe4-fb407181d763
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53954643051898773048842579164635233963518293392746537134673647778300934663122 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.53954643051898773048842579164635233963518293392746537134673647778300934663122
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.44889386124274692668219398365450282757826788415146959911814429989459318015100
Short name T269
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.94 seconds
Started Oct 29 02:04:15 PM PDT 23
Finished Oct 29 02:09:58 PM PDT 23
Peak memory 237756 kb
Host smart-279b1255-7279-4cfa-ad1f-8a340eb4d336
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44889386124274692668219398365450282757826788415146959911814429989459318015100 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.4488938612427469266821939836545028275782678841514695991181
4429989459318015100
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.104998042514097948694407290710020129236707302467172241317116220344737672593450
Short name T275
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.34 seconds
Started Oct 29 02:04:12 PM PDT 23
Finished Oct 29 02:04:38 PM PDT 23
Peak memory 211552 kb
Host smart-36aee0c0-8369-4e33-a519-9d86a73d1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104998042514097948694407290710020129236707302467172241317116220344737672593450 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.rom_ctrl_kmac_err_chk.104998042514097948694407290710020129236707302467172241317116220344737672593450
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.21348512584830430126112600710846317398664189420115737979639911213092981454852
Short name T181
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.02 seconds
Started Oct 29 02:04:09 PM PDT 23
Finished Oct 29 02:04:22 PM PDT 23
Peak memory 211164 kb
Host smart-be12f029-1909-40f9-bfab-094df79c386a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21348512584830430126112600710846317398664189420115737979639911213092981454852 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.21348512584830430126112600710846317398664189420115737979639911213092981454852
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.44840342167678936972058573446207227738624496536565722889439379142545635585385
Short name T149
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.7 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:45 PM PDT 23
Peak memory 212696 kb
Host smart-77d8ef29-3a78-4780-a91e-c04e165f2684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44840342167678936972058573446207227738624496536565722889439379142545635585385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.rom_ctrl_smoke.44840342167678936972058573446207227738624496536565722889439379142545635585385
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.66560511072914439651519536304560428581021822714195493148296019925059261743703
Short name T112
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.6 seconds
Started Oct 29 02:03:56 PM PDT 23
Finished Oct 29 02:04:39 PM PDT 23
Peak memory 212872 kb
Host smart-0e36f56f-d6b3-4733-99cb-b62ea434967b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665605110729144396515195363045604285810218227141954931482960199
25059261743703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.665605110729144396515195363045604285810218227141954
93148296019925059261743703
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.95725686736617808537901518393906103355753190646720755334328386040503966977000
Short name T128
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 29 02:04:18 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 211124 kb
Host smart-3440cfd5-fd3a-48bc-aec3-2ad289e7de74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95725686736617808537901518393906103355753190646720755334328386040503966977000 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.95725686736617808537901518393906103355753190646720755334328386040503966977000
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.58558177117927494825463238207537056023884717280176637018973548012430873780690
Short name T282
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.01 seconds
Started Oct 29 02:04:08 PM PDT 23
Finished Oct 29 02:09:48 PM PDT 23
Peak memory 237652 kb
Host smart-094d0c70-8542-47ff-a63d-0d39d3b64d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58558177117927494825463238207537056023884717280176637018973548012430873780690 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.5855817711792749482546323820753705602388471728017663701897
3548012430873780690
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.86597212121584362710401117443343935667016671749727264336551435520899180524114
Short name T306
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.77 seconds
Started Oct 29 02:03:55 PM PDT 23
Finished Oct 29 02:04:21 PM PDT 23
Peak memory 211608 kb
Host smart-6615342c-0693-4800-ac32-de81af7bef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86597212121584362710401117443343935667016671749727264336551435520899180524114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rom_ctrl_kmac_err_chk.86597212121584362710401117443343935667016671749727264336551435520899180524114
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.14621598410172038334808185114681222818557638768553667997323321547541245559130
Short name T254
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 29 02:03:52 PM PDT 23
Finished Oct 29 02:04:08 PM PDT 23
Peak memory 211244 kb
Host smart-402f2180-a463-4050-9a82-be5b9aa3d557
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14621598410172038334808185114681222818557638768553667997323321547541245559130 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.14621598410172038334808185114681222818557638768553667997323321547541245559130
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.13717533346023517919725254951608303624391321083068544157228671157920463569325
Short name T33
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.82 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:06:10 PM PDT 23
Peak memory 236716 kb
Host smart-0918e233-983e-4547-b21f-b9dc8e219601
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717533346023517919725254951608303624391321083068544157228671157920463569325 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.13717533346023517919725254951608303624391321083068544157228671157920463569325
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.75815744218678480894757017828488245095912166247560875079123655058852831589378
Short name T359
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.26 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:04:42 PM PDT 23
Peak memory 212832 kb
Host smart-6efd050e-43db-4a05-8887-2babc0f83dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75815744218678480894757017828488245095912166247560875079123655058852831589378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_smoke.75815744218678480894757017828488245095912166247560875079123655058852831589378
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.45657204660343397237935303761369285241770173497775399122499867852595675088324
Short name T298
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.91 seconds
Started Oct 29 02:04:09 PM PDT 23
Finished Oct 29 02:04:52 PM PDT 23
Peak memory 212936 kb
Host smart-b8bd88e9-04d3-42a9-9e36-0d0da26f8371
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456572046603433972379353037613692852417701734977753991224998678
52595675088324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.456572046603433972379353037613692852417701734977753
99122499867852595675088324
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.74435155771540071665052953865937360729229843825811732098696606976107703700844
Short name T204
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 29 02:04:27 PM PDT 23
Finished Oct 29 02:04:39 PM PDT 23
Peak memory 211148 kb
Host smart-26fe77e1-a5ab-48a9-8cba-d8d91bc97b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74435155771540071665052953865937360729229843825811732098696606976107703700844 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.74435155771540071665052953865937360729229843825811732098696606976107703700844
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.96565704707640258587483271864335780347585280794297561111225607402540660142489
Short name T143
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.88 seconds
Started Oct 29 02:04:21 PM PDT 23
Finished Oct 29 02:10:02 PM PDT 23
Peak memory 237692 kb
Host smart-e9f42b00-dfa4-438a-b7e4-7dfe054970a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96565704707640258587483271864335780347585280794297561111225607402540660142489 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.965657047076402585874832718643357803475852807942975611112
25607402540660142489
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.5033984252082392527017766149824129687206272841228050336551054977313804315504
Short name T152
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.28 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:48 PM PDT 23
Peak memory 211616 kb
Host smart-e44c875b-f6c4-4c17-ae52-40191935f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5033984252082392527017766149824129687206272841228050336551054977313804315504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.rom_ctrl_kmac_err_chk.5033984252082392527017766149824129687206272841228050336551054977313804315504
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.65755160040770005630538359022900334205989654244078008142597444421352501365516
Short name T290
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:37 PM PDT 23
Peak memory 210168 kb
Host smart-9e17691b-3a0f-46ed-bbe6-013fb983d5e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65755160040770005630538359022900334205989654244078008142597444421352501365516 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.65755160040770005630538359022900334205989654244078008142597444421352501365516
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1996344000340321934616359208311951973608888499863270133977852582181647693946
Short name T324
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.36 seconds
Started Oct 29 02:04:24 PM PDT 23
Finished Oct 29 02:04:53 PM PDT 23
Peak memory 212776 kb
Host smart-1825d006-97a1-4d40-b70c-33aac8296517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996344000340321934616359208311951973608888499863270133977852582181647693946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.rom_ctrl_smoke.1996344000340321934616359208311951973608888499863270133977852582181647693946
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.15332675415630215435236911139110749309876422650748953228192712296399756251129
Short name T137
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.4 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:05:02 PM PDT 23
Peak memory 212828 kb
Host smart-fa317329-b641-4cfa-b44a-e96850a7dd25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153326754156302154352369111391107493098764226507489532281927122
96399756251129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.15332675415630215435236911139110749309876422650748
953228192712296399756251129
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.24402719812936698362973376566216509968459253990938564315753137241072451616521
Short name T41
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:36 PM PDT 23
Peak memory 210188 kb
Host smart-07e9f508-44b7-49ff-8380-6b9a539613e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24402719812936698362973376566216509968459253990938564315753137241072451616521 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.24402719812936698362973376566216509968459253990938564315753137241072451616521
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.39740062152602952331482114532929109362613627006638262523326867703120844368559
Short name T37
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.61 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:09:54 PM PDT 23
Peak memory 237664 kb
Host smart-69b59665-1232-4766-bc85-79c5ca47dc4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740062152602952331482114532929109362613627006638262523326867703120844368559 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.397400621526029523314821145329291093626136270066382625233
26867703120844368559
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.47691423957444670883045160751635847060183424024510683094056209303543587453583
Short name T197
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.99 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:48 PM PDT 23
Peak memory 211620 kb
Host smart-431f23c5-18dd-439d-a9b6-c88411ea1416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47691423957444670883045160751635847060183424024510683094056209303543587453583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.rom_ctrl_kmac_err_chk.47691423957444670883045160751635847060183424024510683094056209303543587453583
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.102104885049239500814694298431801088906189500885656299220232971275662277141019
Short name T85
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 211164 kb
Host smart-050a8642-9627-4452-ae1e-c764af8377be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102104885049239500814694298431801088906189500885656299220232971275662277141019 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.102104885049239500814694298431801088906189500885656299220232971275662277141019
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.114875511829158270405163899185105883147372085069735035156485512820434746404780
Short name T304
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.2 seconds
Started Oct 29 02:04:27 PM PDT 23
Finished Oct 29 02:04:56 PM PDT 23
Peak memory 212812 kb
Host smart-20ed732e-bae7-4f6a-904e-d6a96ae7a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114875511829158270405163899185105883147372085069735035156485512820434746404780 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.rom_ctrl_smoke.114875511829158270405163899185105883147372085069735035156485512820434746404780
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.18816238411337789091367976523066902302670220118358301547157885087138383315355
Short name T267
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.87 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:05:13 PM PDT 23
Peak memory 212900 kb
Host smart-009e4745-cf8f-4121-863f-dc9aeb93d63d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188162384113377890913679765230669023026702201183583015471578850
87138383315355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.18816238411337789091367976523066902302670220118358
301547157885087138383315355
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.50434303358163460590661293096441451346980444377785079765534309448862574221391
Short name T135
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:43 PM PDT 23
Peak memory 211088 kb
Host smart-b22a7c98-a1a6-4153-adac-f62ae340fe00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50434303358163460590661293096441451346980444377785079765534309448862574221391 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.50434303358163460590661293096441451346980444377785079765534309448862574221391
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.88454050754359488720307620048577623690215523718723739309414120285294437509888
Short name T224
Test name
Test status
Simulation time 69854280986 ps
CPU time 332.5 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:09:56 PM PDT 23
Peak memory 237284 kb
Host smart-ea94ef36-daa8-4a6e-afdd-6e8e6d867614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88454050754359488720307620048577623690215523718723739309414120285294437509888 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.884540507543594887203076200485776236902155237187237393094
14120285294437509888
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.70603515426510545469730364352145115465491000667502532715576806050269793583687
Short name T42
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.36 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:48 PM PDT 23
Peak memory 211620 kb
Host smart-c87aac84-a447-456a-acbb-82bdb541f410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70603515426510545469730364352145115465491000667502532715576806050269793583687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rom_ctrl_kmac_err_chk.70603515426510545469730364352145115465491000667502532715576806050269793583687
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.9115093092819834277836418660058260186553065489686602391003251750869668831304
Short name T118
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:31 PM PDT 23
Peak memory 211160 kb
Host smart-e4d48b08-0cf0-4d87-bfdd-ebe4605afa52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9115093092819834277836418660058260186553065489686602391003251750869668831304 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.9115093092819834277836418660058260186553065489686602391003251750869668831304
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.30198105510285402075892913945739503256293594795741599226407906139049449248533
Short name T163
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.22 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:04:51 PM PDT 23
Peak memory 212820 kb
Host smart-2d430d07-9142-4bc1-a199-3ad3c355fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30198105510285402075892913945739503256293594795741599226407906139049449248533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.rom_ctrl_smoke.30198105510285402075892913945739503256293594795741599226407906139049449248533
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.73497091532924735019140653816687992473868054078448604538024883078708157237470
Short name T357
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.94 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:05:05 PM PDT 23
Peak memory 212552 kb
Host smart-236f2eeb-f59d-466f-b173-77cc01b38f28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734970915329247350191406538166879924738680540784486045380248830
78708157237470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.73497091532924735019140653816687992473868054078448
604538024883078708157237470
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.100409259855133302567188458946712305580353926426440180011549534975786908075469
Short name T111
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.97 seconds
Started Oct 29 02:04:27 PM PDT 23
Finished Oct 29 02:04:39 PM PDT 23
Peak memory 211180 kb
Host smart-a572f3fd-eb3a-41e8-b20e-2e9db392e2df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100409259855133302567188458946712305580353926426440180011549534975786908075469 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.100409259855133302567188458946712305580353926426440180011549534975786908075469
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.108120519301491613721943913383619217293247267624321922395199755331154949458157
Short name T270
Test name
Test status
Simulation time 69854280986 ps
CPU time 329.4 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:10:15 PM PDT 23
Peak memory 237604 kb
Host smart-ab41bcc5-bc04-457d-8abb-0e320bd25ced
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108120519301491613721943913383619217293247267624321922395199755331154949458157 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.10812051930149161372194391338361921729324726762432192239
5199755331154949458157
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.72109536342225043271193256310325913708004312791330920204277754596978479612765
Short name T233
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.35 seconds
Started Oct 29 02:04:30 PM PDT 23
Finished Oct 29 02:04:44 PM PDT 23
Peak memory 211184 kb
Host smart-392afed4-5dd7-4a2c-93cc-e97c2c6208b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72109536342225043271193256310325913708004312791330920204277754596978479612765 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.72109536342225043271193256310325913708004312791330920204277754596978479612765
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.101341332207179200760183187166596659350783743027399420848139045012966481629110
Short name T133
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.16 seconds
Started Oct 29 02:04:32 PM PDT 23
Finished Oct 29 02:05:15 PM PDT 23
Peak memory 212852 kb
Host smart-cba510a8-e62a-423c-ac94-231bf07daba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101341332207179200760183187166596659350783743027399420848139045
012966481629110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.1013413322071792007601831871665966593507837430273
99420848139045012966481629110
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.110847527998371448626109481632328042711203613510499052462377140668253142921108
Short name T279
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.55 seconds
Started Oct 29 02:04:31 PM PDT 23
Finished Oct 29 02:04:44 PM PDT 23
Peak memory 211172 kb
Host smart-a9a0c6eb-70cd-4187-b77c-e81918a4c704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110847527998371448626109481632328042711203613510499052462377140668253142921108 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.110847527998371448626109481632328042711203613510499052462377140668253142921108
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3030247697274987617661685844847145370815104831060189027250377972160305483755
Short name T272
Test name
Test status
Simulation time 69854280986 ps
CPU time 326.47 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:10:12 PM PDT 23
Peak memory 237608 kb
Host smart-7df6235e-1baf-4302-ab6f-d3eeb1be3c2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030247697274987617661685844847145370815104831060189027250377972160305483755 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.3030247697274987617661685844847145370815104831060189027250
377972160305483755
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.88674635743587014142387067985713872476966670270330145556492690310297101941358
Short name T333
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.68 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:05:10 PM PDT 23
Peak memory 211500 kb
Host smart-fb8204a6-8b9e-4a10-993d-5c6892759a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88674635743587014142387067985713872476966670270330145556492690310297101941358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.88674635743587014142387067985713872476966670270330145556492690310297101941358
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.50545880853899467470237009127826327627274994081928175336023904124120789176608
Short name T207
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 29 02:04:32 PM PDT 23
Finished Oct 29 02:05:00 PM PDT 23
Peak memory 212744 kb
Host smart-9918d585-300f-4079-826e-3de017ae71c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50545880853899467470237009127826327627274994081928175336023904124120789176608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_smoke.50545880853899467470237009127826327627274994081928175336023904124120789176608
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.14750504392232631979309427521195286769597672056956940626125320331353194947333
Short name T200
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.5 seconds
Started Oct 29 02:04:32 PM PDT 23
Finished Oct 29 02:05:15 PM PDT 23
Peak memory 212952 kb
Host smart-1fc74e26-5c81-46fc-bd9e-77c79b2f5404
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147505043922326319793094275211952867695976720569569406261253203
31353194947333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.14750504392232631979309427521195286769597672056956
940626125320331353194947333
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.25552808626943763879692460328132378907460597467567222578202107704785220363839
Short name T297
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Oct 29 02:04:30 PM PDT 23
Finished Oct 29 02:04:43 PM PDT 23
Peak memory 211192 kb
Host smart-c99eb84f-c866-471f-8939-a1ad97c75084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25552808626943763879692460328132378907460597467567222578202107704785220363839 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.25552808626943763879692460328132378907460597467567222578202107704785220363839
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.76805145530114670826688285455860968985827325243175064341244632454894053793255
Short name T199
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.14 seconds
Started Oct 29 02:04:31 PM PDT 23
Finished Oct 29 02:10:14 PM PDT 23
Peak memory 237640 kb
Host smart-e822ff5c-aa0a-440a-b561-76a894031517
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76805145530114670826688285455860968985827325243175064341244632454894053793255 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.768051455301146708266882854558609689858273252431750643412
44632454894053793255
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.94573893185991477022713086401813079217216133983840011290907612852038539606952
Short name T329
Test name
Test status
Simulation time 6233818126 ps
CPU time 25 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:55 PM PDT 23
Peak memory 211544 kb
Host smart-8b836a89-e49e-4b6c-bf8f-ee9fcde864fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94573893185991477022713086401813079217216133983840011290907612852038539606952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.94573893185991477022713086401813079217216133983840011290907612852038539606952
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.26330464477679820468935753046848614220018802731892842430991162319209747847909
Short name T109
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.83 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:42 PM PDT 23
Peak memory 211032 kb
Host smart-1bf4651f-4096-4af5-8795-ecd4126f0110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26330464477679820468935753046848614220018802731892842430991162319209747847909 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.26330464477679820468935753046848614220018802731892842430991162319209747847909
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.65644258935379341245933796955058079355649891361516225621685998704876643465580
Short name T362
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.34 seconds
Started Oct 29 02:04:30 PM PDT 23
Finished Oct 29 02:04:59 PM PDT 23
Peak memory 212764 kb
Host smart-3210ccbc-4e15-41ec-8b2a-30a11874ff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65644258935379341245933796955058079355649891361516225621685998704876643465580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.65644258935379341245933796955058079355649891361516225621685998704876643465580
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.31839344800431026995883969407044809566420222608616996138486443513281882871680
Short name T336
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.68 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:05:27 PM PDT 23
Peak memory 212812 kb
Host smart-3ab98d11-2b8e-47f0-8cc2-4acd934a5d39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318393448004310269958839694070448095664202226086169961384864435
13281882871680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.31839344800431026995883969407044809566420222608616
996138486443513281882871680
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.60482771167559885392351596240392612025737386368735453036244929957376821740806
Short name T265
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Oct 29 02:04:41 PM PDT 23
Finished Oct 29 02:04:54 PM PDT 23
Peak memory 211176 kb
Host smart-e0b7dd64-b301-48dd-8431-f9cafd71614e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60482771167559885392351596240392612025737386368735453036244929957376821740806 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.60482771167559885392351596240392612025737386368735453036244929957376821740806
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.64097251783170198211492497921389249558005700273129644798034583154458231137950
Short name T273
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.45 seconds
Started Oct 29 02:04:30 PM PDT 23
Finished Oct 29 02:10:14 PM PDT 23
Peak memory 237720 kb
Host smart-fcf60564-40fb-4bfb-bc50-ad4857ce471e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64097251783170198211492497921389249558005700273129644798034583154458231137950 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.640972517831701982114924979213892495580057002731296447980
34583154458231137950
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.24765303406474696333438239534462178064725750909083108524504933384843058067434
Short name T316
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.36 seconds
Started Oct 29 02:04:57 PM PDT 23
Finished Oct 29 02:05:23 PM PDT 23
Peak memory 211608 kb
Host smart-762f5ee3-6087-47ed-9072-0a69b1b0b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24765303406474696333438239534462178064725750909083108524504933384843058067434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.rom_ctrl_kmac_err_chk.24765303406474696333438239534462178064725750909083108524504933384843058067434
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.36949768476942060539601389132222473607640654099750147255935648209994178479831
Short name T9
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:43 PM PDT 23
Peak memory 211088 kb
Host smart-df0d3d63-3752-4f36-b670-0eff8575fb20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=36949768476942060539601389132222473607640654099750147255935648209994178479831 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.36949768476942060539601389132222473607640654099750147255935648209994178479831
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.75790476171782487141997721643556307297858057715194603087102107082509050294016
Short name T132
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.83 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:05:14 PM PDT 23
Peak memory 212708 kb
Host smart-e7c5c602-fe24-4f8f-9583-8b193075a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75790476171782487141997721643556307297858057715194603087102107082509050294016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_smoke.75790476171782487141997721643556307297858057715194603087102107082509050294016
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.53188700252420614604798496522137668525806922584224619095154877617128643187723
Short name T278
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.04 seconds
Started Oct 29 02:04:45 PM PDT 23
Finished Oct 29 02:05:26 PM PDT 23
Peak memory 212812 kb
Host smart-145674c6-1734-499e-94fc-fe4c745c3a65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531887002524206146047984965221376685258069225842246190951548776
17128643187723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.53188700252420614604798496522137668525806922584224
619095154877617128643187723
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.76750086847211373418221021261858118088954217447768690779673046894424744309161
Short name T108
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.32 seconds
Started Oct 29 02:04:38 PM PDT 23
Finished Oct 29 02:04:51 PM PDT 23
Peak memory 211176 kb
Host smart-8f6e7982-1d17-4fba-801c-226ea500146c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76750086847211373418221021261858118088954217447768690779673046894424744309161 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.76750086847211373418221021261858118088954217447768690779673046894424744309161
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.115507586714581860639320167410222482046462393507455884558878176123297780086527
Short name T195
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.21 seconds
Started Oct 29 02:04:38 PM PDT 23
Finished Oct 29 02:10:23 PM PDT 23
Peak memory 237796 kb
Host smart-8a90a7b5-7a76-44ee-86d1-31fe740cd7d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115507586714581860639320167410222482046462393507455884558878176123297780086527 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.11550758671458186063932016741022248204646239350745588455
8878176123297780086527
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.35750791719567563757871916690185642947202431931761837492454538640494556886374
Short name T177
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.38 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:05:25 PM PDT 23
Peak memory 211716 kb
Host smart-07137a2f-b0c5-4e50-b72b-7c8959250cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35750791719567563757871916690185642947202431931761837492454538640494556886374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rom_ctrl_kmac_err_chk.35750791719567563757871916690185642947202431931761837492454538640494556886374
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.30740147998010466947070984878994541193893988960821941118295338474075872172324
Short name T245
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.37 seconds
Started Oct 29 02:04:37 PM PDT 23
Finished Oct 29 02:04:50 PM PDT 23
Peak memory 211104 kb
Host smart-44117ac2-2c6b-4d70-9310-c5593646eb63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30740147998010466947070984878994541193893988960821941118295338474075872172324 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.30740147998010466947070984878994541193893988960821941118295338474075872172324
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.21025221863130564889946820959397276983511807629189757725111035048440434766455
Short name T343
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.8 seconds
Started Oct 29 02:04:56 PM PDT 23
Finished Oct 29 02:05:25 PM PDT 23
Peak memory 212748 kb
Host smart-dd126ea7-07d4-4eb2-aa11-491cdfbc82b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21025221863130564889946820959397276983511807629189757725111035048440434766455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.rom_ctrl_smoke.21025221863130564889946820959397276983511807629189757725111035048440434766455
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.47244096853638101060993581623336000747097891801532121567560784934176862291739
Short name T169
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.55 seconds
Started Oct 29 02:04:57 PM PDT 23
Finished Oct 29 02:05:40 PM PDT 23
Peak memory 212844 kb
Host smart-9a4fb110-ec08-4b99-a9b2-7e4a4ba30acf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472440968536381010609935816233360007470978918015321215675607849
34176862291739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.47244096853638101060993581623336000747097891801532
121567560784934176862291739
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.93538878849194514753511098867151637755201498746499933456947940481147482496495
Short name T219
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 29 02:04:37 PM PDT 23
Finished Oct 29 02:04:49 PM PDT 23
Peak memory 211184 kb
Host smart-acd8a14c-5a43-4417-b14c-1cdc78307a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93538878849194514753511098867151637755201498746499933456947940481147482496495 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.93538878849194514753511098867151637755201498746499933456947940481147482496495
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.60501214124742797316648826809206910469654327484253219463372502670003135591003
Short name T251
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.56 seconds
Started Oct 29 02:04:57 PM PDT 23
Finished Oct 29 02:10:43 PM PDT 23
Peak memory 237620 kb
Host smart-92d117e3-c16c-4a1b-8411-35d12bf754b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60501214124742797316648826809206910469654327484253219463372502670003135591003 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.605012141247427973166488268092069104696543274842532194633
72502670003135591003
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.39769783862138260243193107422921529323004961879129841195206873718615747377394
Short name T294
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.02 seconds
Started Oct 29 02:04:55 PM PDT 23
Finished Oct 29 02:05:20 PM PDT 23
Peak memory 211616 kb
Host smart-aae01432-9c8d-40fe-be0a-0d02b60a15d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39769783862138260243193107422921529323004961879129841195206873718615747377394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.39769783862138260243193107422921529323004961879129841195206873718615747377394
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.84724556550298783835070323719114802870515200009535748342641787722285380133544
Short name T332
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 29 02:04:49 PM PDT 23
Finished Oct 29 02:05:03 PM PDT 23
Peak memory 211152 kb
Host smart-ce6270fc-828f-4c85-9d28-b74d527e9786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84724556550298783835070323719114802870515200009535748342641787722285380133544 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.84724556550298783835070323719114802870515200009535748342641787722285380133544
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.77877548451132998955901209564412612335012379570100410481239205978972159249609
Short name T84
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.1 seconds
Started Oct 29 02:04:38 PM PDT 23
Finished Oct 29 02:05:07 PM PDT 23
Peak memory 212728 kb
Host smart-c3316fb5-5039-43ab-89a2-74189c636e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77877548451132998955901209564412612335012379570100410481239205978972159249609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.77877548451132998955901209564412612335012379570100410481239205978972159249609
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.61631216081344804159239610533500254873958119854174894120719183442899291753474
Short name T356
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.35 seconds
Started Oct 29 02:04:39 PM PDT 23
Finished Oct 29 02:05:21 PM PDT 23
Peak memory 212864 kb
Host smart-e18f1d14-18a6-4ae9-88ef-f4207c44a1a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616312160813448041592396105335002548739581198541748941207191834
42899291753474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.61631216081344804159239610533500254873958119854174
894120719183442899291753474
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.67846262973787506176922965999306008029008465033643169241503840254823904054322
Short name T119
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 29 02:04:39 PM PDT 23
Finished Oct 29 02:04:52 PM PDT 23
Peak memory 211188 kb
Host smart-4e05c6dd-1130-4545-8f29-8ba26e5c01fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67846262973787506176922965999306008029008465033643169241503840254823904054322 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.67846262973787506176922965999306008029008465033643169241503840254823904054322
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.67815848693620086064664082237180062574570847030930158491250533956908541426301
Short name T289
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.35 seconds
Started Oct 29 02:04:43 PM PDT 23
Finished Oct 29 02:10:30 PM PDT 23
Peak memory 237688 kb
Host smart-dd211026-c7d3-4c42-b48a-60c0edc62610
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67815848693620086064664082237180062574570847030930158491250533956908541426301 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.678158486936200860646640822371800625745708470309301584912
50533956908541426301
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.43552123430100293672058944007921063865797615088621225865751459804512339869442
Short name T280
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.34 seconds
Started Oct 29 02:04:48 PM PDT 23
Finished Oct 29 02:05:14 PM PDT 23
Peak memory 211608 kb
Host smart-d9cbd20a-3aac-4ad3-9e28-25eb171362c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43552123430100293672058944007921063865797615088621225865751459804512339869442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.rom_ctrl_kmac_err_chk.43552123430100293672058944007921063865797615088621225865751459804512339869442
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.22645119828010870554776572641354713035926431870294210834045630908968232859360
Short name T354
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 29 02:04:48 PM PDT 23
Finished Oct 29 02:05:02 PM PDT 23
Peak memory 211176 kb
Host smart-fcaffeb3-1f25-46eb-8fd8-294653d0ca05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22645119828010870554776572641354713035926431870294210834045630908968232859360 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.22645119828010870554776572641354713035926431870294210834045630908968232859360
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.94196453547929134492086132491000662824116207774996438117806448463633888714456
Short name T257
Test name
Test status
Simulation time 6265461576 ps
CPU time 29 seconds
Started Oct 29 02:04:38 PM PDT 23
Finished Oct 29 02:05:07 PM PDT 23
Peak memory 212800 kb
Host smart-ca6d47e4-d894-45aa-b516-783a4914ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94196453547929134492086132491000662824116207774996438117806448463633888714456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_smoke.94196453547929134492086132491000662824116207774996438117806448463633888714456
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.50126441939910685633723777078385350516949641327467919085567632601785797631497
Short name T295
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.57 seconds
Started Oct 29 02:04:42 PM PDT 23
Finished Oct 29 02:05:24 PM PDT 23
Peak memory 212916 kb
Host smart-8ff0356f-ada3-415e-be0c-a833842ebf6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501264419399106856337237770783853505169496413274679190855676326
01785797631497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.50126441939910685633723777078385350516949641327467
919085567632601785797631497
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.42484356803164826328551866148558681323353474594611782288251897078563546016825
Short name T136
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.31 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:33 PM PDT 23
Peak memory 211168 kb
Host smart-1ca5f096-707c-418e-93b7-572017b733c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42484356803164826328551866148558681323353474594611782288251897078563546016825 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.42484356803164826328551866148558681323353474594611782288251897078563546016825
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.23539787763789274193673790588832226302078158649319361030582296425692262710465
Short name T317
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.33 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:09:52 PM PDT 23
Peak memory 237732 kb
Host smart-f1db927e-ee8a-4c48-ab27-c22a708e2d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539787763789274193673790588832226302078158649319361030582296425692262710465 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.2353978776378927419367379058883222630207815864931936103058
2296425692262710465
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.34559174100972339911318082912368769810510852632535761372589707659075812070565
Short name T115
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.86 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:42 PM PDT 23
Peak memory 211536 kb
Host smart-fab7daba-2684-4a46-8eff-cd61bdc575f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34559174100972339911318082912368769810510852632535761372589707659075812070565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.rom_ctrl_kmac_err_chk.34559174100972339911318082912368769810510852632535761372589707659075812070565
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.71374532426529574709996341926843478095925333136037054156314063615599283912072
Short name T334
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.83 seconds
Started Oct 29 02:04:21 PM PDT 23
Finished Oct 29 02:04:35 PM PDT 23
Peak memory 211116 kb
Host smart-90a7eea2-317b-467c-8038-046467cee0af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71374532426529574709996341926843478095925333136037054156314063615599283912072 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.71374532426529574709996341926843478095925333136037054156314063615599283912072
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.53920990333731068258085957049391732558527979115442194631786637280133272782850
Short name T32
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.94 seconds
Started Oct 29 02:04:24 PM PDT 23
Finished Oct 29 02:06:21 PM PDT 23
Peak memory 236840 kb
Host smart-7878948a-c9d0-419c-8a28-b81b2725decb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53920990333731068258085957049391732558527979115442194631786637280133272782850 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.53920990333731068258085957049391732558527979115442194631786637280133272782850
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.97984520157205110920199397890889736805349298604533258086882946123923892039534
Short name T364
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.33 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:49 PM PDT 23
Peak memory 212724 kb
Host smart-226ec463-d803-47bc-b3b3-72a0ad2bc479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97984520157205110920199397890889736805349298604533258086882946123923892039534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.97984520157205110920199397890889736805349298604533258086882946123923892039534
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.70746878437835179311457739191566472604860067283902672673695585630418835432748
Short name T348
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.49 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:05:00 PM PDT 23
Peak memory 212848 kb
Host smart-93db7f0e-8ef3-4975-8f45-b2d1255cf664
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707468784378351793114577391915664726048600672839026726736955856
30418835432748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.707468784378351793114577391915664726048600672839026
72673695585630418835432748
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.51353678816729261992912331276024245859859050397386366234227926117452242433883
Short name T352
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.5 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:13 PM PDT 23
Peak memory 211164 kb
Host smart-4e9156eb-ef49-4923-a465-ee3aa803c1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51353678816729261992912331276024245859859050397386366234227926117452242433883 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.51353678816729261992912331276024245859859050397386366234227926117452242433883
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.7548791251137188553725942692001561889808579423026731667066063086210348412515
Short name T314
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.27 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:10:35 PM PDT 23
Peak memory 237712 kb
Host smart-c48fd6dd-af8a-4233-be58-33c42d2865d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7548791251137188553725942692001561889808579423026731667066063086210348412515 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.7548791251137188553725942692001561889808579423026731667066
063086210348412515
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.83260993784361476404969495651254926494495391769075896673103704791209382745248
Short name T305
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.49 seconds
Started Oct 29 02:04:58 PM PDT 23
Finished Oct 29 02:05:24 PM PDT 23
Peak memory 211692 kb
Host smart-ba97f013-4ab6-43e0-b081-c27a8cda6a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83260993784361476404969495651254926494495391769075896673103704791209382745248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.rom_ctrl_kmac_err_chk.83260993784361476404969495651254926494495391769075896673103704791209382745248
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.14947478497464331621529045360697123522042639696697062375404759181641469392886
Short name T217
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.41 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:13 PM PDT 23
Peak memory 211152 kb
Host smart-5557ace6-102e-4a70-aa43-6e7af8e1b80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14947478497464331621529045360697123522042639696697062375404759181641469392886 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.14947478497464331621529045360697123522042639696697062375404759181641469392886
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.52398117145750224042860448023760444543105194407940948739544559295271939799193
Short name T83
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.64 seconds
Started Oct 29 02:04:37 PM PDT 23
Finished Oct 29 02:05:06 PM PDT 23
Peak memory 212756 kb
Host smart-cfcb591b-53e5-4664-b7de-5bbf4480f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52398117145750224042860448023760444543105194407940948739544559295271939799193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.rom_ctrl_smoke.52398117145750224042860448023760444543105194407940948739544559295271939799193
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.19058117338086769674185419765412566976898492022356675291018854538498800538517
Short name T250
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.38 seconds
Started Oct 29 02:04:55 PM PDT 23
Finished Oct 29 02:05:39 PM PDT 23
Peak memory 212932 kb
Host smart-25f7e2cc-ccbe-47b8-adc0-37fcaff243e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190581173380867696741854197654125669768984920223566752910188545
38498800538517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.19058117338086769674185419765412566976898492022356
675291018854538498800538517
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.68817346216228861373676897807025724401512147686332571745637156597725995660483
Short name T238
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:12 PM PDT 23
Peak memory 211184 kb
Host smart-3199f2d2-fcf0-42e0-9ff2-388e0a1f57ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68817346216228861373676897807025724401512147686332571745637156597725995660483 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.68817346216228861373676897807025724401512147686332571745637156597725995660483
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.81987707163114619109310696977996999877118906386564590388432130798961131864021
Short name T303
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.84 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:10:37 PM PDT 23
Peak memory 237740 kb
Host smart-1edb9755-f298-4088-b5f9-9fe6a0f57aa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81987707163114619109310696977996999877118906386564590388432130798961131864021 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.819877071631146191093106969779969998771189063865645903884
32130798961131864021
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.23745713642103486441210115921107487878554695695947276428434317666431725713245
Short name T206
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.21 seconds
Started Oct 29 02:05:05 PM PDT 23
Finished Oct 29 02:05:31 PM PDT 23
Peak memory 211604 kb
Host smart-65e7b457-b0ba-409f-9ce3-c1bfab2f4456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23745713642103486441210115921107487878554695695947276428434317666431725713245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rom_ctrl_kmac_err_chk.23745713642103486441210115921107487878554695695947276428434317666431725713245
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.3787921489495657451983407624844638177492853722296002923631658486079780139211
Short name T125
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:14 PM PDT 23
Peak memory 211164 kb
Host smart-1fa5fc1e-d8e2-467d-960c-5cc98fd5aa95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3787921489495657451983407624844638177492853722296002923631658486079780139211 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.3787921489495657451983407624844638177492853722296002923631658486079780139211
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.50240121021508500180154129089117805725863635395797716786184395306544002330649
Short name T313
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.18 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:28 PM PDT 23
Peak memory 212852 kb
Host smart-bde472f8-0370-4959-9d0e-06b4da619ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50240121021508500180154129089117805725863635395797716786184395306544002330649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.rom_ctrl_smoke.50240121021508500180154129089117805725863635395797716786184395306544002330649
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.18827189971616635460824103562023498299173096294882411635565101177805533457232
Short name T122
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.49 seconds
Started Oct 29 02:04:57 PM PDT 23
Finished Oct 29 02:05:40 PM PDT 23
Peak memory 212940 kb
Host smart-a8b11744-c8e2-40c8-b5ed-550a5dec42a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188271899716166354608241035620234982991730962948824116355651011
77805533457232 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.18827189971616635460824103562023498299173096294882
411635565101177805533457232
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.104495804510576344719666880203617008332527805957936670329708297053523340868678
Short name T161
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:13 PM PDT 23
Peak memory 211096 kb
Host smart-c73eb988-7ea2-4929-ba96-4a5e10365ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104495804510576344719666880203617008332527805957936670329708297053523340868678 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.104495804510576344719666880203617008332527805957936670329708297053523340868678
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.104402685981507354681938015137341764263200181399910345376303268247501187544531
Short name T255
Test name
Test status
Simulation time 69854280986 ps
CPU time 329.81 seconds
Started Oct 29 02:04:57 PM PDT 23
Finished Oct 29 02:10:27 PM PDT 23
Peak memory 237592 kb
Host smart-3a1b61ac-3427-4c45-8b00-fa1bb9f8fc36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104402685981507354681938015137341764263200181399910345376303268247501187544531 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.10440268598150735468193801513734176426320018139991034537
6303268247501187544531
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.108255642495640362604717300362015985834262992524855228955454013914311884541714
Short name T10
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.9 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:27 PM PDT 23
Peak memory 211608 kb
Host smart-fe81285b-3405-43bc-9853-c049efc5b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108255642495640362604717300362015985834262992524855228955454013914311884541714 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.rom_ctrl_kmac_err_chk.108255642495640362604717300362015985834262992524855228955454013914311884541714
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.15355229749104623079966866276128122113732180156869771282670707956447428811029
Short name T308
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.06 seconds
Started Oct 29 02:04:58 PM PDT 23
Finished Oct 29 02:05:12 PM PDT 23
Peak memory 211180 kb
Host smart-875316e3-ede5-4a5a-8a68-1848cc5732e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15355229749104623079966866276128122113732180156869771282670707956447428811029 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.15355229749104623079966866276128122113732180156869771282670707956447428811029
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.80457920250926989290445514716365713559623762551427392372116283410450297292027
Short name T299
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.46 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:05:28 PM PDT 23
Peak memory 212780 kb
Host smart-dfecde06-ea3e-4f8a-a270-7f17d8dca427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80457920250926989290445514716365713559623762551427392372116283410450297292027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.rom_ctrl_smoke.80457920250926989290445514716365713559623762551427392372116283410450297292027
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.37940956346344846263181679654440039454349972260190823848584860558853238309090
Short name T180
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.93 seconds
Started Oct 29 02:05:00 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 212900 kb
Host smart-c6ae5c12-622b-4b49-96f6-75561b8034d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379409563463448462631816796544400394543499722601908238485848605
58853238309090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.37940956346344846263181679654440039454349972260190
823848584860558853238309090
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.21201106212172923473656429524687915457007190504103768106579151637392159690567
Short name T185
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.4 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:05:12 PM PDT 23
Peak memory 211156 kb
Host smart-079f8403-1e45-4484-9ad6-d0dfbaa533b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201106212172923473656429524687915457007190504103768106579151637392159690567 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.21201106212172923473656429524687915457007190504103768106579151637392159690567
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.60826424351014269385141072305340579152615717790123103636389319454429345898091
Short name T247
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.48 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:10:39 PM PDT 23
Peak memory 237800 kb
Host smart-e20b8c1b-3a96-443f-8567-408696d0e5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60826424351014269385141072305340579152615717790123103636389319454429345898091 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.608264243510142693851410723053405791526157177901231036363
89319454429345898091
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.65632369932885619499818312021866790180071051266774338931336928333351941494934
Short name T7
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.75 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:05:25 PM PDT 23
Peak memory 211556 kb
Host smart-6d4f4332-584c-4249-83ae-160fe683d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65632369932885619499818312021866790180071051266774338931336928333351941494934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.rom_ctrl_kmac_err_chk.65632369932885619499818312021866790180071051266774338931336928333351941494934
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.82146723367005438534133101856610052675343589047192492390644859431442672934735
Short name T192
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.46 seconds
Started Oct 29 02:04:59 PM PDT 23
Finished Oct 29 02:05:13 PM PDT 23
Peak memory 211164 kb
Host smart-caf4e6ee-8880-45b6-a310-ccbf1fa5fd28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82146723367005438534133101856610052675343589047192492390644859431442672934735 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.82146723367005438534133101856610052675343589047192492390644859431442672934735
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.45390973133630925836948920788435564078308294810419071135951639378147842331116
Short name T145
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.11 seconds
Started Oct 29 02:05:02 PM PDT 23
Finished Oct 29 02:05:31 PM PDT 23
Peak memory 212772 kb
Host smart-ac6ac7dc-fd84-48b1-9590-8200bc8f94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45390973133630925836948920788435564078308294810419071135951639378147842331116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.45390973133630925836948920788435564078308294810419071135951639378147842331116
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.24725647656848578921099420386929475814834109967818705450631065764602988763951
Short name T358
Test name
Test status
Simulation time 9415977006 ps
CPU time 43 seconds
Started Oct 29 02:05:03 PM PDT 23
Finished Oct 29 02:05:46 PM PDT 23
Peak memory 212844 kb
Host smart-4c363f73-49bc-4816-954f-826b573d6099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247256476568485789210994203869294758148341099678187054506310657
64602988763951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.24725647656848578921099420386929475814834109967818
705450631065764602988763951
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.32232139401480531882175944062564656277822113258078600306670002673446393987176
Short name T121
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211020 kb
Host smart-397334af-dcbd-40b7-9a48-541ab3050d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32232139401480531882175944062564656277822113258078600306670002673446393987176 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.32232139401480531882175944062564656277822113258078600306670002673446393987176
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.16022633198807907905587872672677712220117599990583320875834317885445957073993
Short name T45
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.67 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:11:10 PM PDT 23
Peak memory 237672 kb
Host smart-ea3ad3dc-86e3-4b05-ab50-924bd98e5f8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022633198807907905587872672677712220117599990583320875834317885445957073993 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.160226331988079079055878726726777122201175999905833208758
34317885445957073993
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.84195662012751696110299972092790290860782008052110810398890193583563822486408
Short name T39
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.57 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211604 kb
Host smart-5497a300-8d30-4d7d-8999-9e0964fd78dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84195662012751696110299972092790290860782008052110810398890193583563822486408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rom_ctrl_kmac_err_chk.84195662012751696110299972092790290860782008052110810398890193583563822486408
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.65294938807104947279992860148287279804395081545642444236615278319392949441008
Short name T167
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.29 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:05:42 PM PDT 23
Peak memory 211116 kb
Host smart-e9854bf7-3953-4d31-9082-6fbbdedd03d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65294938807104947279992860148287279804395081545642444236615278319392949441008 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.65294938807104947279992860148287279804395081545642444236615278319392949441008
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.24925270964863571537008523271214130585982777111645612635440997758507142677185
Short name T259
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.69 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 212836 kb
Host smart-200fd900-1843-4058-8277-e801fbf3c0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24925270964863571537008523271214130585982777111645612635440997758507142677185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.rom_ctrl_smoke.24925270964863571537008523271214130585982777111645612635440997758507142677185
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.51713645978360989381700284694725403390127022838046290448014831919700668253170
Short name T105
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.13 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:06:12 PM PDT 23
Peak memory 212876 kb
Host smart-49e75dab-a487-4ccd-b7e1-031f1a1a304c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517136459783609893817002846947254033901270228380462904480148319
19700668253170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.51713645978360989381700284694725403390127022838046
290448014831919700668253170
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.46251478980341559275396430443422784128751768087640496395542780020375095447391
Short name T29
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.99 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211156 kb
Host smart-c32cc25b-ce46-4cbe-8d17-694f1a947de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46251478980341559275396430443422784128751768087640496395542780020375095447391 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.46251478980341559275396430443422784128751768087640496395542780020375095447391
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.55109132811522158435902852218712371357459972537710067580456335989951662563434
Short name T151
Test name
Test status
Simulation time 69854280986 ps
CPU time 347.4 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:11:16 PM PDT 23
Peak memory 237652 kb
Host smart-7960d857-e02c-4f44-8803-dbd40e7287b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55109132811522158435902852218712371357459972537710067580456335989951662563434 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.551091328115221584359028522187123713574599725377100675804
56335989951662563434
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.30768347747110111645455160967554996246910602844074335421857281929472986482123
Short name T248
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.2 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:54 PM PDT 23
Peak memory 211608 kb
Host smart-12daef35-04bf-4980-b1e8-015060d2ce40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30768347747110111645455160967554996246910602844074335421857281929472986482123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.rom_ctrl_kmac_err_chk.30768347747110111645455160967554996246910602844074335421857281929472986482123
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.15105336142281019345898497375994370809237413435686206737937548689648223699451
Short name T148
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.97 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211192 kb
Host smart-f2da7834-080a-4b7b-8e2c-a41e1138bf09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15105336142281019345898497375994370809237413435686206737937548689648223699451 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.15105336142281019345898497375994370809237413435686206737937548689648223699451
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.25980955858833606128728796823428575851353869133736115949188136748709863504696
Short name T310
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.13 seconds
Started Oct 29 02:05:20 PM PDT 23
Finished Oct 29 02:05:49 PM PDT 23
Peak memory 212816 kb
Host smart-8bbd849a-3af3-45e7-9af3-dcdc2d7846f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25980955858833606128728796823428575851353869133736115949188136748709863504696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.rom_ctrl_smoke.25980955858833606128728796823428575851353869133736115949188136748709863504696
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1199900442636071235108041440964226524870254818985752307697855803400077668452
Short name T211
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.08 seconds
Started Oct 29 02:05:20 PM PDT 23
Finished Oct 29 02:06:03 PM PDT 23
Peak memory 212836 kb
Host smart-4aa6737a-df3c-47e1-b1da-558534ae58b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119990044263607123510804144096422652487025481898575230769785580
3400077668452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.119990044263607123510804144096422652487025481898575
2307697855803400077668452
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.39767537001325549867449422874041360937042173560388259160112932466127049322879
Short name T117
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211124 kb
Host smart-311b52f9-83f7-41ef-ac26-097e9ab95031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767537001325549867449422874041360937042173560388259160112932466127049322879 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.39767537001325549867449422874041360937042173560388259160112932466127049322879
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.30513628330787906009320761508384368513613087007688608000339245630026141976809
Short name T328
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.44 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:11:12 PM PDT 23
Peak memory 237732 kb
Host smart-0ab088c4-e0c9-485c-bf6e-53365c34b3b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30513628330787906009320761508384368513613087007688608000339245630026141976809 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.305136283307879060093207615083843685136130870076886080003
39245630026141976809
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.34773991160873727134950246533092999210942941768976286461526908339952799696162
Short name T244
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.54 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211660 kb
Host smart-ed79c4c1-529e-4df1-ae54-0054350a541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34773991160873727134950246533092999210942941768976286461526908339952799696162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.34773991160873727134950246533092999210942941768976286461526908339952799696162
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.21758722576278464401522244803685665656492991036565148030772173321112728355132
Short name T189
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.48 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211164 kb
Host smart-87fd068e-eeb4-4d47-8072-e05d1b7eb9a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21758722576278464401522244803685665656492991036565148030772173321112728355132 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.21758722576278464401522244803685665656492991036565148030772173321112728355132
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.84831309914562724083327449820272337994703454993150667914863900460536222527758
Short name T312
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.26 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 212708 kb
Host smart-4268e0bd-5762-43da-b7ef-f22e98b9f270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84831309914562724083327449820272337994703454993150667914863900460536222527758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.84831309914562724083327449820272337994703454993150667914863900460536222527758
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.67331084331310471450404025243223147529028880904510074050876460055235737521429
Short name T231
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.68 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:06:13 PM PDT 23
Peak memory 212912 kb
Host smart-cc443533-866d-46d7-99f2-03dd88afa051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673310843313104714504040252432231475290288809045100740508764600
55235737521429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.67331084331310471450404025243223147529028880904510
074050876460055235737521429
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.45676218176041844449105450123191319251748407128823075026902847882913814491018
Short name T311
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 29 02:05:23 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211184 kb
Host smart-85fb613f-2255-40ef-8bdc-2cdb73d057f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45676218176041844449105450123191319251748407128823075026902847882913814491018 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.45676218176041844449105450123191319251748407128823075026902847882913814491018
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.11539210986999615535657533612629789217381201128690753684932225375687813500237
Short name T160
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.56 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:11:03 PM PDT 23
Peak memory 237696 kb
Host smart-5d1e4cee-62a3-4709-a991-f9efaba0f5e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11539210986999615535657533612629789217381201128690753684932225375687813500237 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.115392109869996155356575336126297892173812011286907536849
32225375687813500237
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.84673827309136890451171469924809690067328256602156420024697306760370401528916
Short name T203
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.53 seconds
Started Oct 29 02:05:21 PM PDT 23
Finished Oct 29 02:05:51 PM PDT 23
Peak memory 211600 kb
Host smart-723c3040-2a22-41d9-9876-cf6bd3435285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84673827309136890451171469924809690067328256602156420024697306760370401528916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rom_ctrl_kmac_err_chk.84673827309136890451171469924809690067328256602156420024697306760370401528916
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.55009260687591264973262217243651814261008004605579271457214492215568588243226
Short name T154
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.31 seconds
Started Oct 29 02:05:21 PM PDT 23
Finished Oct 29 02:05:38 PM PDT 23
Peak memory 211196 kb
Host smart-144004ea-705d-400e-b54b-fc2d92966c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55009260687591264973262217243651814261008004605579271457214492215568588243226 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.55009260687591264973262217243651814261008004605579271457214492215568588243226
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.51484831602224073636570716342780427202309338626251932593283311816371453713094
Short name T227
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.16 seconds
Started Oct 29 02:05:21 PM PDT 23
Finished Oct 29 02:05:50 PM PDT 23
Peak memory 212804 kb
Host smart-2da12eca-5212-45d6-bbb5-ee04856bb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51484831602224073636570716342780427202309338626251932593283311816371453713094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_smoke.51484831602224073636570716342780427202309338626251932593283311816371453713094
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.12636568463082073946772730884741716642390557119562707101279777845035575533762
Short name T252
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.46 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:06:11 PM PDT 23
Peak memory 212856 kb
Host smart-e180e3e6-1fe9-4259-b606-0d049e7eee4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126365684630820739467727308847417166423905571195627071012797778
45035575533762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.12636568463082073946772730884741716642390557119562
707101279777845035575533762
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.11248520288782018779697626010284839519474649042314404230730263227127808150483
Short name T191
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.13 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:42 PM PDT 23
Peak memory 211180 kb
Host smart-3e75f16c-5fc3-4c8e-87e2-32a5553e0dfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248520288782018779697626010284839519474649042314404230730263227127808150483 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.11248520288782018779697626010284839519474649042314404230730263227127808150483
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.65270352464645700037217041163598198802827522712493365701609188448454207799367
Short name T319
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.06 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:11:09 PM PDT 23
Peak memory 237716 kb
Host smart-e2ce80ec-19bd-48b0-aa7b-b2c56f28f9f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65270352464645700037217041163598198802827522712493365701609188448454207799367 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.652703524646457000372170411635981988028275227124933657016
09188448454207799367
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.24973230101859184363427735588179338173152480415530049156765186253507300791599
Short name T339
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.17 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:05:54 PM PDT 23
Peak memory 211496 kb
Host smart-e9749190-0785-43c3-8e74-e0775c34be27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24973230101859184363427735588179338173152480415530049156765186253507300791599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.rom_ctrl_kmac_err_chk.24973230101859184363427735588179338173152480415530049156765186253507300791599
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.14395664142934048560922650677882961239885107063411069014661110329357109238548
Short name T344
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.32 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:42 PM PDT 23
Peak memory 211196 kb
Host smart-eda4bb42-d507-4214-acca-4a10fbf6aadf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14395664142934048560922650677882961239885107063411069014661110329357109238548 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.14395664142934048560922650677882961239885107063411069014661110329357109238548
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.35646116889159573424481106360350426972393132171752318160445105214398217321032
Short name T1
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.06 seconds
Started Oct 29 02:05:23 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 212852 kb
Host smart-1a81ee5f-85da-4fdf-9867-8ce59554afad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35646116889159573424481106360350426972393132171752318160445105214398217321032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.35646116889159573424481106360350426972393132171752318160445105214398217321032
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.79130460465015056558286384154098001229546388581168781376267971473698793360191
Short name T129
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.53 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:06:10 PM PDT 23
Peak memory 212840 kb
Host smart-6031b7d0-d4ee-4b93-a8d8-61df85a87765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791304604650150565582863841540980012295463885811687813762679714
73698793360191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.79130460465015056558286384154098001229546388581168
781376267971473698793360191
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4159685661189974075104643854347241625137398379172216850913818046273161077581
Short name T8
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Oct 29 02:05:23 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211136 kb
Host smart-66670b7e-4ac1-4148-95bd-571903c2bf1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159685661189974075104643854347241625137398379172216850913818046273161077581 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4159685661189974075104643854347241625137398379172216850913818046273161077581
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.20903777946434332037740345700183723748155876448235046025572617328385397493721
Short name T212
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.33 seconds
Started Oct 29 02:05:23 PM PDT 23
Finished Oct 29 02:11:11 PM PDT 23
Peak memory 237672 kb
Host smart-50d0b122-3eb4-47aa-bf0d-e78c05af65df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903777946434332037740345700183723748155876448235046025572617328385397493721 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.209037779464343320377403457001837237481558764482350460255
72617328385397493721
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.88659606198857789208207730297109306025659462854540453611702484548198740678095
Short name T225
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.54 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211528 kb
Host smart-3e010a24-004d-4cc8-b3fe-32eba4bb78de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88659606198857789208207730297109306025659462854540453611702484548198740678095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.88659606198857789208207730297109306025659462854540453611702484548198740678095
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.103341783734449458989622577985172538575406124421557205547844967006470375572449
Short name T285
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.03 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211172 kb
Host smart-67c5589e-a7d9-4e57-9a00-14302da68452
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103341783734449458989622577985172538575406124421557205547844967006470375572449 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.103341783734449458989622577985172538575406124421557205547844967006470375572449
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.82394368972788753027581991769847969955575286789659738896133254226767392666084
Short name T322
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.24 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:58 PM PDT 23
Peak memory 212828 kb
Host smart-782c89d0-eaea-4979-a745-ef7376a064b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82394368972788753027581991769847969955575286789659738896133254226767392666084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.rom_ctrl_smoke.82394368972788753027581991769847969955575286789659738896133254226767392666084
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.6669813125432762283402765927315108923360625991666361569066403383187423130521
Short name T347
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.8 seconds
Started Oct 29 02:05:20 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 212868 kb
Host smart-ad898457-7125-4e2b-8e83-c9d543129228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666981312543276228340276592731510892336062599166636156906640338
3187423130521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.666981312543276228340276592731510892336062599166636
1569066403383187423130521
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.45946963922889088001401460071994341279623493176601748892320019451555885040349
Short name T183
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 211100 kb
Host smart-cecdb006-2a7d-4b44-85af-05862e68af08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45946963922889088001401460071994341279623493176601748892320019451555885040349 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.45946963922889088001401460071994341279623493176601748892320019451555885040349
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.15545220851920400872668423792841541941076063669482686572758862405423369480216
Short name T11
Test name
Test status
Simulation time 69854280986 ps
CPU time 324.81 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:09:41 PM PDT 23
Peak memory 237688 kb
Host smart-d793c149-973b-48f9-b276-4763f06fe544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15545220851920400872668423792841541941076063669482686572758862405423369480216 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.1554522085192040087266842379284154194107606366948268657275
8862405423369480216
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.98795322056943891010719069909070648047064459535275635530007616630030425274693
Short name T130
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.54 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:42 PM PDT 23
Peak memory 211600 kb
Host smart-f5871297-8ac0-4bf8-a5da-063c0d986090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98795322056943891010719069909070648047064459535275635530007616630030425274693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.98795322056943891010719069909070648047064459535275635530007616630030425274693
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.72645206843040158862034261089074036148900137661198380370566413837544124308193
Short name T309
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.25 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:29 PM PDT 23
Peak memory 211220 kb
Host smart-95272274-c988-492f-b39e-ec96358a3de7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72645206843040158862034261089074036148900137661198380370566413837544124308193 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.72645206843040158862034261089074036148900137661198380370566413837544124308193
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.74984101332333023077959813642138391612628473769655327669517990912417901499764
Short name T26
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.17 seconds
Started Oct 29 02:04:15 PM PDT 23
Finished Oct 29 02:06:10 PM PDT 23
Peak memory 236836 kb
Host smart-1372a431-2f25-47aa-8c2e-0cb02228e864
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74984101332333023077959813642138391612628473769655327669517990912417901499764 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.74984101332333023077959813642138391612628473769655327669517990912417901499764
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.51061115756395224355228066028671166766428433781651220824663665762863110589151
Short name T80
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.11 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:48 PM PDT 23
Peak memory 212840 kb
Host smart-b597a285-49d0-43cd-9ec1-2978acfad388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51061115756395224355228066028671166766428433781651220824663665762863110589151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_smoke.51061115756395224355228066028671166766428433781651220824663665762863110589151
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.61038315944550321250859995725148084945090331741951437700896958974479858514492
Short name T202
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.13 seconds
Started Oct 29 02:04:26 PM PDT 23
Finished Oct 29 02:05:09 PM PDT 23
Peak memory 212916 kb
Host smart-4fedb65a-2e06-43ba-83b6-b3f6204e597f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610383159445503212508599957251480849450903317419514377008969589
74479858514492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.610383159445503212508599957251480849450903317419514
37700896958974479858514492
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.80068873748854508530050704077164145858843637153531947078205239983538449492060
Short name T35
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Oct 29 02:05:23 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211192 kb
Host smart-0937a9d7-8ac4-45f1-8366-41b8d796895d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80068873748854508530050704077164145858843637153531947078205239983538449492060 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.80068873748854508530050704077164145858843637153531947078205239983538449492060
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.60915439667541239963442874745469379369349364803984029801691178609057262354424
Short name T194
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.37 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:11:14 PM PDT 23
Peak memory 237632 kb
Host smart-d6792b79-40b1-47a6-98e5-d7865ec6e411
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60915439667541239963442874745469379369349364803984029801691178609057262354424 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.609154396675412399634428747454693793693493648039840298016
91178609057262354424
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.97376536133847440619412229300064415737883303427863855183481454520303715991294
Short name T360
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.09 seconds
Started Oct 29 02:05:22 PM PDT 23
Finished Oct 29 02:05:54 PM PDT 23
Peak memory 211560 kb
Host smart-e0dd583d-c6f7-4da7-b8aa-a2f73d73d46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97376536133847440619412229300064415737883303427863855183481454520303715991294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.rom_ctrl_kmac_err_chk.97376536133847440619412229300064415737883303427863855183481454520303715991294
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.4742195882856314764505105968169358053861648304992209370884577240315609929677
Short name T82
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.14 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211176 kb
Host smart-57d14271-ac08-40b7-9124-be2f96b87cb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4742195882856314764505105968169358053861648304992209370884577240315609929677 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.4742195882856314764505105968169358053861648304992209370884577240315609929677
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.63599889046651724151720175650805724173934966294117916079111422811857611557193
Short name T361
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.43 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:59 PM PDT 23
Peak memory 212860 kb
Host smart-8633e72a-7ec3-4345-919b-b281e64d7418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63599889046651724151720175650805724173934966294117916079111422811857611557193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.rom_ctrl_smoke.63599889046651724151720175650805724173934966294117916079111422811857611557193
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.18592519323963024271562433498915833139958306573634874343659530823061385838350
Short name T173
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.69 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:06:13 PM PDT 23
Peak memory 212844 kb
Host smart-332a6ff3-5999-4f51-9a7b-e7da6f913681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185925193239630242715624334989158331399583065736348743436595308
23061385838350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.18592519323963024271562433498915833139958306573634
874343659530823061385838350
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2995302495000268607132159836698094164777067126152678752058173910347952621545
Short name T134
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211144 kb
Host smart-8052790d-45f8-42bc-b04b-6bcb856f25d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995302495000268607132159836698094164777067126152678752058173910347952621545 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2995302495000268607132159836698094164777067126152678752058173910347952621545
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.74062229767333430191896742134939951828090083863982316049094197101199299560646
Short name T338
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.57 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:11:11 PM PDT 23
Peak memory 237612 kb
Host smart-7e25bc00-9388-4690-b55a-1d92ad0e8f3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74062229767333430191896742134939951828090083863982316049094197101199299560646 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.740622297673334301918967421349399518280900838639823160490
94197101199299560646
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.90319249226961682728988823747015807736003218241713389709198901074930449319147
Short name T218
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.99 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:54 PM PDT 23
Peak memory 211628 kb
Host smart-96413d23-4510-49d2-b202-15d25dbf848b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90319249226961682728988823747015807736003218241713389709198901074930449319147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.rom_ctrl_kmac_err_chk.90319249226961682728988823747015807736003218241713389709198901074930449319147
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.83699441116259055981188328617318524794971176687090678547334923361285438409576
Short name T164
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.98 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211184 kb
Host smart-3db8c74e-2fae-461a-91cd-e90027377aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83699441116259055981188328617318524794971176687090678547334923361285438409576 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.83699441116259055981188328617318524794971176687090678547334923361285438409576
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.42109313382793704743379525084856156194229107426938657476101202150468669855563
Short name T216
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.15 seconds
Started Oct 29 02:05:21 PM PDT 23
Finished Oct 29 02:05:53 PM PDT 23
Peak memory 212844 kb
Host smart-795f05af-0c8b-4e58-ac3c-642fa00e4e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42109313382793704743379525084856156194229107426938657476101202150468669855563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.42109313382793704743379525084856156194229107426938657476101202150468669855563
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.73053226518967302831355379830218834683822877433680249713546559171930641019587
Short name T292
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.96 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:06:11 PM PDT 23
Peak memory 212932 kb
Host smart-3ab08ec1-515b-43b9-9fd1-8c20a0368d0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730532265189673028313553798302188346838228774336802497135465591
71930641019587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.73053226518967302831355379830218834683822877433680
249713546559171930641019587
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.8414140503897298139085043906717626803610019949759628536892222385907801174033
Short name T235
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.25 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211192 kb
Host smart-d58fdc71-0d81-45f3-bf51-80ee6fa54066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8414140503897298139085043906717626803610019949759628536892222385907801174033 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.8414140503897298139085043906717626803610019949759628536892222385907801174033
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.69926801886150037956459336980461387207178790378067003963276562623085177181838
Short name T323
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.06 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 211560 kb
Host smart-543d0de2-183b-48c4-8359-d424cc6554de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69926801886150037956459336980461387207178790378067003963276562623085177181838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.rom_ctrl_kmac_err_chk.69926801886150037956459336980461387207178790378067003963276562623085177181838
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.13417675433315956207548914320611503747091585730817928029689588149840868057127
Short name T274
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.22 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:42 PM PDT 23
Peak memory 211156 kb
Host smart-c17a4405-2042-4189-9b57-0eefa4f4bbe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=13417675433315956207548914320611503747091585730817928029689588149840868057127 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.13417675433315956207548914320611503747091585730817928029689588149840868057127
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.59351542187636576981226507723819980070125430664886297732252058120071437960754
Short name T146
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.5 seconds
Started Oct 29 02:05:21 PM PDT 23
Finished Oct 29 02:05:54 PM PDT 23
Peak memory 212760 kb
Host smart-5d14eee3-9551-4826-af04-db948db138d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59351542187636576981226507723819980070125430664886297732252058120071437960754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.59351542187636576981226507723819980070125430664886297732252058120071437960754
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.60554510123980777928766432373332824804859571910470242469521161119826433250658
Short name T283
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.12 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:06:12 PM PDT 23
Peak memory 212940 kb
Host smart-c5fda441-460a-4212-a94d-6b518a24bd99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605545101239807779287664323733328248048595719104702424695211611
19826433250658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.60554510123980777928766432373332824804859571910470
242469521161119826433250658
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.49072291989376638707364780185261698830524176088482046205902297920094855563801
Short name T139
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211084 kb
Host smart-cbea40b4-a8d6-4824-ab13-78f1f20339f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49072291989376638707364780185261698830524176088482046205902297920094855563801 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.49072291989376638707364780185261698830524176088482046205902297920094855563801
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.22665953630059896569414052384232817174893348470334184406637552900605843844882
Short name T176
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.28 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:11:14 PM PDT 23
Peak memory 237680 kb
Host smart-2c6d3add-97c4-49b2-aaa6-53626d076ccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665953630059896569414052384232817174893348470334184406637552900605843844882 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.226659536300598965694140523842328171748933484703341844066
37552900605843844882
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.73906844413515869500742699683210650883979568333217121973611982442792636040130
Short name T276
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.6 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211516 kb
Host smart-8a7d8da2-67a9-4d87-8bf5-b289c2d7a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73906844413515869500742699683210650883979568333217121973611982442792636040130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rom_ctrl_kmac_err_chk.73906844413515869500742699683210650883979568333217121973611982442792636040130
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.26900322786936176936614103009089484177727715524968295702786785136177785698515
Short name T166
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211180 kb
Host smart-c09cd8e5-5590-4f3a-a236-43d8c9a8c1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=26900322786936176936614103009089484177727715524968295702786785136177785698515 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.26900322786936176936614103009089484177727715524968295702786785136177785698515
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.110440085801824196792964698805175447262206727427731986885050167037241020974800
Short name T307
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.95 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:58 PM PDT 23
Peak memory 212832 kb
Host smart-48278d4f-5ea5-478d-aa38-5b678232adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110440085801824196792964698805175447262206727427731986885050167037241020974800 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.rom_ctrl_smoke.110440085801824196792964698805175447262206727427731986885050167037241020974800
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.79364703762868618949603551633239414810387973440745365809372070928994219088573
Short name T89
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.81 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:06:12 PM PDT 23
Peak memory 212932 kb
Host smart-f20c7140-a177-476d-b89d-6a96080abd31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793647037628686189496035516332394148103879734407453658093720709
28994219088573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.79364703762868618949603551633239414810387973440745
365809372070928994219088573
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.92710114174780350890787262346596439536787806135279066822397953431198708065510
Short name T28
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.97 seconds
Started Oct 29 02:05:31 PM PDT 23
Finished Oct 29 02:05:46 PM PDT 23
Peak memory 211148 kb
Host smart-e871439b-971f-4dd8-a4b6-cda3df84f35c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92710114174780350890787262346596439536787806135279066822397953431198708065510 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.92710114174780350890787262346596439536787806135279066822397953431198708065510
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.72926515062276431370710444686529874530545415129939571423866740553698473493385
Short name T46
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.17 seconds
Started Oct 29 02:05:33 PM PDT 23
Finished Oct 29 02:11:13 PM PDT 23
Peak memory 237628 kb
Host smart-e073c5a5-5ccd-4406-b478-20ddc8e48105
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72926515062276431370710444686529874530545415129939571423866740553698473493385 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.729265150622764313707104446865298745305454151299395714238
66740553698473493385
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.101011114169234377375907456747776784975814896604861814884559712193368477881221
Short name T110
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.07 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 211668 kb
Host smart-e257f277-a6a0-4152-994b-a9b06629fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101011114169234377375907456747776784975814896604861814884559712193368477881221 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.rom_ctrl_kmac_err_chk.101011114169234377375907456747776784975814896604861814884559712193368477881221
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.12510750467242902805213318702863421703054405816718032279775206279226736122867
Short name T365
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.04 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211244 kb
Host smart-3bf54193-0acb-4363-a713-eef337e3f7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12510750467242902805213318702863421703054405816718032279775206279226736122867 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.12510750467242902805213318702863421703054405816718032279775206279226736122867
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.77933194397578303727933414141372994716334004301983300985408272593897282601729
Short name T237
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.25 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 212860 kb
Host smart-2d1edd72-4149-475e-9414-2bd42028ff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77933194397578303727933414141372994716334004301983300985408272593897282601729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_smoke.77933194397578303727933414141372994716334004301983300985408272593897282601729
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.66216922883194426686464811478715126213438272892763956620950869386066946458976
Short name T144
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.51 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211060 kb
Host smart-a98d4236-7c0c-4381-9811-a35639856ad3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66216922883194426686464811478715126213438272892763956620950869386066946458976 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.66216922883194426686464811478715126213438272892763956620950869386066946458976
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.100627429311970108481219135339280753850318660836310188905744555520454446433614
Short name T182
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.3 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:11:10 PM PDT 23
Peak memory 237780 kb
Host smart-e3d05e5a-98d7-499a-8a9a-33ff4e3d511c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100627429311970108481219135339280753850318660836310188905744555520454446433614 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.10062742931197010848121913533928075385031866083631018890
5744555520454446433614
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.53009041515162975415087042853594853828544050290779783492373491708013476276741
Short name T196
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.99 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211628 kb
Host smart-1b430f2a-a44b-437c-bca2-892b8251bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53009041515162975415087042853594853828544050290779783492373491708013476276741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.rom_ctrl_kmac_err_chk.53009041515162975415087042853594853828544050290779783492373491708013476276741
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.55336931501010413943048251353343510617274642115401375895872662825715082998473
Short name T341
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:05:45 PM PDT 23
Peak memory 211140 kb
Host smart-f76e5807-de3f-4fe6-9078-8930615ffcdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55336931501010413943048251353343510617274642115401375895872662825715082998473 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.55336931501010413943048251353343510617274642115401375895872662825715082998473
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.80745088848277460063242721810975756802270602859568318207726332624248838544399
Short name T345
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.29 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:59 PM PDT 23
Peak memory 212764 kb
Host smart-75ef25c5-0c87-4a40-aa46-8dc082ca0c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80745088848277460063242721810975756802270602859568318207726332624248838544399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_smoke.80745088848277460063242721810975756802270602859568318207726332624248838544399
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.50094306947873283927102417986735288721361375272097609238569581693677705439071
Short name T172
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.52 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:06:14 PM PDT 23
Peak memory 212916 kb
Host smart-9225571e-d0fa-44f5-a396-a6cc8522685f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500943069478732839271024179867352887213613752720976092385695816
93677705439071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.50094306947873283927102417986735288721361375272097
609238569581693677705439071
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.65659871424303254214642062343605307164398214141911777598936701392671230465218
Short name T287
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211212 kb
Host smart-42f34b31-dd57-4c9e-a5ae-e97c80f54849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65659871424303254214642062343605307164398214141911777598936701392671230465218 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.65659871424303254214642062343605307164398214141911777598936701392671230465218
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.49692933974445971647857172045233338014232393302647715735800274413719566398224
Short name T243
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.46 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:11:07 PM PDT 23
Peak memory 237676 kb
Host smart-6a44e74b-11ca-42e8-984e-d8b7036ad4dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49692933974445971647857172045233338014232393302647715735800274413719566398224 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.496929339744459716478571720452333380142323933026477157358
00274413719566398224
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.16172760488202010371638247122081356103027724667385335794328505126798476181224
Short name T284
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.02 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 211608 kb
Host smart-3ac59a13-d65a-4629-b1b4-64dc31c3956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16172760488202010371638247122081356103027724667385335794328505126798476181224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rom_ctrl_kmac_err_chk.16172760488202010371638247122081356103027724667385335794328505126798476181224
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.52375081562042067047125237811362320487048207952935827593388445699018103980177
Short name T127
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.03 seconds
Started Oct 29 02:05:30 PM PDT 23
Finished Oct 29 02:05:46 PM PDT 23
Peak memory 211140 kb
Host smart-21e194ee-401b-47ce-ad69-f8409020b7dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52375081562042067047125237811362320487048207952935827593388445699018103980177 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.52375081562042067047125237811362320487048207952935827593388445699018103980177
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.106446959948243196600564570903820506455978780197136797322765962694289845427407
Short name T213
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.46 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:59 PM PDT 23
Peak memory 212776 kb
Host smart-e25f72f5-fe74-4d26-ae20-5d098a84124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106446959948243196600564570903820506455978780197136797322765962694289845427407 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.rom_ctrl_smoke.106446959948243196600564570903820506455978780197136797322765962694289845427407
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.103455292391592055126996838241336624770466138518230645233238090555904389874425
Short name T157
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.95 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:06:13 PM PDT 23
Peak memory 212844 kb
Host smart-f728ead1-c687-40ff-8b92-9e2c11c81084
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103455292391592055126996838241336624770466138518230645233238090
555904389874425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.1034552923915920551269968382413366247704661385182
30645233238090555904389874425
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.96777522156424697632877580133878397963928822898378190124844338788306720154428
Short name T187
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Oct 29 02:05:24 PM PDT 23
Finished Oct 29 02:05:41 PM PDT 23
Peak memory 211184 kb
Host smart-8cec8096-1a12-4ed5-9ffe-4b897c985896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96777522156424697632877580133878397963928822898378190124844338788306720154428 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.96777522156424697632877580133878397963928822898378190124844338788306720154428
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.25698045191945751270775568159561779091842706924152031601725682856369307551477
Short name T36
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.62 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:11:04 PM PDT 23
Peak memory 237676 kb
Host smart-12a6dbac-9d1b-4bf9-bb0f-f7df6702f2c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25698045191945751270775568159561779091842706924152031601725682856369307551477 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.256980451919457512707755681595617790918427069241520316017
25682856369307551477
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.47084397247749076829275960241394970812383538007902287977387886422699317065638
Short name T106
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.4 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:55 PM PDT 23
Peak memory 211512 kb
Host smart-405964aa-71f1-4b02-b07a-07fc99b4aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47084397247749076829275960241394970812383538007902287977387886422699317065638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rom_ctrl_kmac_err_chk.47084397247749076829275960241394970812383538007902287977387886422699317065638
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.113204428499676367275606466166572131179022703856259053470508709611499662864114
Short name T232
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211096 kb
Host smart-9aef242a-29c6-4a0a-aff6-a9d8f7016c76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113204428499676367275606466166572131179022703856259053470508709611499662864114 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.113204428499676367275606466166572131179022703856259053470508709611499662864114
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.57072200542084567835112071528692069497440699847964762779962377194620298715694
Short name T209
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.23 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 212812 kb
Host smart-0813102a-d7e8-4da4-9a74-b87e6b01a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57072200542084567835112071528692069497440699847964762779962377194620298715694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.57072200542084567835112071528692069497440699847964762779962377194620298715694
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.104940107923388335184284528826160641315852324877678922618777310141510602106851
Short name T330
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.31 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:06:12 PM PDT 23
Peak memory 212968 kb
Host smart-826c1193-4150-447b-97e1-209abc52e64a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104940107923388335184284528826160641315852324877678922618777310
141510602106851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.1049401079233883351842845288261606413158523248776
78922618777310141510602106851
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.59014407033699726689439003247442779480453012456060562166824959320184773325946
Short name T321
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211188 kb
Host smart-490604e4-1f8a-4ba7-894d-7f5c5ad2e674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59014407033699726689439003247442779480453012456060562166824959320184773325946 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.59014407033699726689439003247442779480453012456060562166824959320184773325946
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.37631316688318777114070927472768704293278831418949763625439967732844407541368
Short name T186
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.01 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:11:06 PM PDT 23
Peak memory 237752 kb
Host smart-12fa4390-b05e-4fb1-9a86-7aa828dd8783
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631316688318777114070927472768704293278831418949763625439967732844407541368 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.376313166883187771140709274727687042932788314189497636254
39967732844407541368
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.100558936326169881752101327775521108810144187746797110982734768475567217608816
Short name T188
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.58 seconds
Started Oct 29 02:05:26 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211632 kb
Host smart-f754b1cf-cfd7-45e5-b99b-497361fbed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100558936326169881752101327775521108810144187746797110982734768475567217608816 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.rom_ctrl_kmac_err_chk.100558936326169881752101327775521108810144187746797110982734768475567217608816
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.90310878835271663952150667966714082421247361556381698598380149310322114099010
Short name T350
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.36 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211120 kb
Host smart-94c7f5fb-c6f4-4343-a01a-ecdc1c73adbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=90310878835271663952150667966714082421247361556381698598380149310322114099010 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.90310878835271663952150667966714082421247361556381698598380149310322114099010
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.28961347198814775567237041720247887419779985886296139297062208852890579000604
Short name T301
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.97 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 212760 kb
Host smart-04c9506d-efc7-4cae-9924-e5d1906abdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28961347198814775567237041720247887419779985886296139297062208852890579000604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.28961347198814775567237041720247887419779985886296139297062208852890579000604
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.53207768162586442670588877461544192899207876400693695365156039340496637576139
Short name T340
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.19 seconds
Started Oct 29 02:05:25 PM PDT 23
Finished Oct 29 02:06:13 PM PDT 23
Peak memory 212860 kb
Host smart-804cb767-cb30-4c23-9743-ca30703ee6bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532077681625864426705888774615441928992078764006936953651560393
40496637576139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.53207768162586442670588877461544192899207876400693
695365156039340496637576139
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.53774381050597538041370908822688535777680534670963635781012379675261708966362
Short name T327
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:05:43 PM PDT 23
Peak memory 211184 kb
Host smart-a32b9039-71e5-48c3-9381-5c1b6b415460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53774381050597538041370908822688535777680534670963635781012379675261708966362 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.53774381050597538041370908822688535777680534670963635781012379675261708966362
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.68402793876814715176385926298032558861116616050652800888189520819380010401472
Short name T226
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.99 seconds
Started Oct 29 02:05:32 PM PDT 23
Finished Oct 29 02:11:11 PM PDT 23
Peak memory 237652 kb
Host smart-d8c99e5c-9407-4603-a8a6-66f5a1906d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68402793876814715176385926298032558861116616050652800888189520819380010401472 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.684027938768147151763859262980325588611166160506528008881
89520819380010401472
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.104969486543748170698760475714217510703333599246371885376250650205552080196193
Short name T351
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.88 seconds
Started Oct 29 02:05:30 PM PDT 23
Finished Oct 29 02:06:00 PM PDT 23
Peak memory 211520 kb
Host smart-7403bdf2-be84-4c85-92bf-df3ceb9b0235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104969486543748170698760475714217510703333599246371885376250650205552080196193 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.rom_ctrl_kmac_err_chk.104969486543748170698760475714217510703333599246371885376250650205552080196193
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.72272125467632313567077836838941877202069151291336683018450877832220165635270
Short name T346
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211176 kb
Host smart-2dd7229c-6ad3-4650-9b8f-9fde34437e4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72272125467632313567077836838941877202069151291336683018450877832220165635270 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.72272125467632313567077836838941877202069151291336683018450877832220165635270
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.39022608613289380233016426381329778556034794491875945950517834701938196260241
Short name T230
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 29 02:05:31 PM PDT 23
Finished Oct 29 02:06:03 PM PDT 23
Peak memory 212728 kb
Host smart-460a227b-424f-4ea8-81a8-2c018e28a8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39022608613289380233016426381329778556034794491875945950517834701938196260241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.rom_ctrl_smoke.39022608613289380233016426381329778556034794491875945950517834701938196260241
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.52061814044746354736389591489404850783735199254826622892838270551948629970602
Short name T138
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.26 seconds
Started Oct 29 02:05:31 PM PDT 23
Finished Oct 29 02:06:17 PM PDT 23
Peak memory 212828 kb
Host smart-2b5c5ec0-5314-4736-bee9-38efee71a9a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520618140447463547363895914894048507837351992548266228928382705
51948629970602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.52061814044746354736389591489404850783735199254826
622892838270551948629970602
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.61835238800168044538196942570821706071849183871807943359678254382137833962165
Short name T249
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:04:32 PM PDT 23
Peak memory 211212 kb
Host smart-e351380e-c848-48fc-89ce-e9ef8d9d8cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61835238800168044538196942570821706071849183871807943359678254382137833962165 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.61835238800168044538196942570821706071849183871807943359678254382137833962165
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.112675523724696786798055270036998766332469094986866012647625774877539523999421
Short name T258
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.53 seconds
Started Oct 29 02:04:26 PM PDT 23
Finished Oct 29 02:10:03 PM PDT 23
Peak memory 237084 kb
Host smart-9d177d31-0351-476b-9b4f-99715e3085d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112675523724696786798055270036998766332469094986866012647625774877539523999421 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.112675523724696786798055270036998766332469094986866012647
625774877539523999421
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.15104727825112806321375833721817619172942353907415802903190760315624754565020
Short name T104
Test name
Test status
Simulation time 6233818126 ps
CPU time 26 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:46 PM PDT 23
Peak memory 211624 kb
Host smart-c3b861d2-7720-435e-a485-c37f4bcbb0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15104727825112806321375833721817619172942353907415802903190760315624754565020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rom_ctrl_kmac_err_chk.15104727825112806321375833721817619172942353907415802903190760315624754565020
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.33340348471798373113327625431596298850311300878776437227327279929850146149644
Short name T178
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:04:32 PM PDT 23
Peak memory 211180 kb
Host smart-034e2ac5-78ba-4d71-8f2d-47900797198b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33340348471798373113327625431596298850311300878776437227327279929850146149644 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.33340348471798373113327625431596298850311300878776437227327279929850146149644
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.15155971646583567808972317696569989483463340921830650593901628801602850138613
Short name T25
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.7 seconds
Started Oct 29 02:04:28 PM PDT 23
Finished Oct 29 02:06:24 PM PDT 23
Peak memory 236752 kb
Host smart-89b4e178-9352-4869-8a8f-ab1e002c5b99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155971646583567808972317696569989483463340921830650593901628801602850138613 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.15155971646583567808972317696569989483463340921830650593901628801602850138613
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.55037241208119855163806439068808904228051810312292898880930037358139875949907
Short name T131
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.36 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:04:48 PM PDT 23
Peak memory 212816 kb
Host smart-ae3e6960-93b7-4817-bca9-adcc864338f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55037241208119855163806439068808904228051810312292898880930037358139875949907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.rom_ctrl_smoke.55037241208119855163806439068808904228051810312292898880930037358139875949907
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.9325281998393196701382164530282957935881602739301485874188988924503823077831
Short name T337
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.56 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:59 PM PDT 23
Peak memory 212984 kb
Host smart-928593fd-9bd6-481d-a011-d9a3242ae94d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932528199839319670138216453028295793588160273930148587418898892
4503823077831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.9325281998393196701382164530282957935881602739301485
874188988924503823077831
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1321584667527657726196359949530817639413078162708290014419668806730663133299
Short name T107
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211128 kb
Host smart-1ecad7da-5ba4-4a7d-bde8-ec0749d030d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321584667527657726196359949530817639413078162708290014419668806730663133299 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1321584667527657726196359949530817639413078162708290014419668806730663133299
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.51525530740882632173472615733530254840767001288199456603509731711119465334988
Short name T302
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.48 seconds
Started Oct 29 02:05:29 PM PDT 23
Finished Oct 29 02:11:12 PM PDT 23
Peak memory 237736 kb
Host smart-56f8c1c2-d1f9-410c-8965-d5879e1b2760
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51525530740882632173472615733530254840767001288199456603509731711119465334988 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.515255307408826321734726157335302548407670012881994566035
09731711119465334988
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.12290588879916725377116666302489963985403856910400616634017229019594976643955
Short name T214
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.69 seconds
Started Oct 29 02:05:27 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211784 kb
Host smart-02357add-c202-4331-b6ff-f27fae2765a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12290588879916725377116666302489963985403856910400616634017229019594976643955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rom_ctrl_kmac_err_chk.12290588879916725377116666302489963985403856910400616634017229019594976643955
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.24147391953167514122484952527411625608440871899573701613766920164862129357267
Short name T150
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 29 02:05:32 PM PDT 23
Finished Oct 29 02:05:48 PM PDT 23
Peak memory 211164 kb
Host smart-b52a0d8e-6332-4f9e-a22d-af449b236ece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24147391953167514122484952527411625608440871899573701613766920164862129357267 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.24147391953167514122484952527411625608440871899573701613766920164862129357267
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.109320858407144505495110127856306521689896402711136325259117764152759201842042
Short name T286
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.09 seconds
Started Oct 29 02:05:33 PM PDT 23
Finished Oct 29 02:06:03 PM PDT 23
Peak memory 212812 kb
Host smart-d19d8a16-3415-4756-a6a1-5bc35ee58424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109320858407144505495110127856306521689896402711136325259117764152759201842042 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.rom_ctrl_smoke.109320858407144505495110127856306521689896402711136325259117764152759201842042
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.10039622398538958433069141586668104901783975209885861774969826311953582731743
Short name T281
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.32 seconds
Started Oct 29 02:05:32 PM PDT 23
Finished Oct 29 02:06:17 PM PDT 23
Peak memory 212912 kb
Host smart-c43aaa0e-6418-4df4-aa25-6a371533e2d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100396223985389584330691415866681049017839752098858617749698263
11953582731743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.10039622398538958433069141586668104901783975209885
861774969826311953582731743
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.87095770421553552970537735225826110361438087653814377569371646967721582199844
Short name T201
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:05:50 PM PDT 23
Peak memory 211160 kb
Host smart-eccc6dff-caf4-4dec-b218-b6b0f620fe8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87095770421553552970537735225826110361438087653814377569371646967721582199844 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.87095770421553552970537735225826110361438087653814377569371646967721582199844
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.63381644824984414952480179843686789421234862650600480728717716890577142971825
Short name T234
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.56 seconds
Started Oct 29 02:05:35 PM PDT 23
Finished Oct 29 02:11:15 PM PDT 23
Peak memory 237656 kb
Host smart-661550cc-3c09-48c1-be0a-b934d23ad5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63381644824984414952480179843686789421234862650600480728717716890577142971825 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.633816448249844149524801798436867894212348626506004807287
17716890577142971825
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.44653300623158346192244929685949791194126090317249256083263199543690539517260
Short name T165
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.87 seconds
Started Oct 29 02:05:35 PM PDT 23
Finished Oct 29 02:06:01 PM PDT 23
Peak memory 211544 kb
Host smart-5000f46d-708f-41da-8928-66939e1e29e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44653300623158346192244929685949791194126090317249256083263199543690539517260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.rom_ctrl_kmac_err_chk.44653300623158346192244929685949791194126090317249256083263199543690539517260
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.11513423584384225226270730536047032233874134375176821568826353121085801834808
Short name T363
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:44 PM PDT 23
Peak memory 211104 kb
Host smart-7b7e3b3d-ff9e-44f2-aebd-68d40c65da2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11513423584384225226270730536047032233874134375176821568826353121085801834808 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.11513423584384225226270730536047032233874134375176821568826353121085801834808
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.14328234924767103175025816515716663080487739431693478765376345136368002677039
Short name T326
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.3 seconds
Started Oct 29 02:05:28 PM PDT 23
Finished Oct 29 02:05:59 PM PDT 23
Peak memory 212760 kb
Host smart-de34ef5f-b922-42a4-9427-a3573111cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14328234924767103175025816515716663080487739431693478765376345136368002677039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.rom_ctrl_smoke.14328234924767103175025816515716663080487739431693478765376345136368002677039
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.55965483122521199246893863584586125243684143287989072979494428084956125904008
Short name T13
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.43 seconds
Started Oct 29 02:05:32 PM PDT 23
Finished Oct 29 02:06:17 PM PDT 23
Peak memory 212912 kb
Host smart-c48c30b9-15af-4a9c-9b51-440c5a20b6c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559654831225211992468938635845861252436841432879890729794944280
84956125904008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.55965483122521199246893863584586125243684143287989
072979494428084956125904008
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.104187058210192491590613546423579637936579170688576080316516271995212278709095
Short name T171
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.02 seconds
Started Oct 29 02:05:51 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 211164 kb
Host smart-455492f9-3b6c-41d9-ae52-11c94c66337b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104187058210192491590613546423579637936579170688576080316516271995212278709095 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.104187058210192491590613546423579637936579170688576080316516271995212278709095
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.18567723464200615915332015080051602346868198295024875712035415381726528910932
Short name T215
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.21 seconds
Started Oct 29 02:05:41 PM PDT 23
Finished Oct 29 02:11:23 PM PDT 23
Peak memory 237812 kb
Host smart-73e3dbe1-e834-4e5b-97a4-c1d4ee274862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567723464200615915332015080051602346868198295024875712035415381726528910932 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.185677234642006159153320150800516023468681982950248757120
35415381726528910932
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1223002022351429160655186736529206380589702977148242798483913407687354526234
Short name T260
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.76 seconds
Started Oct 29 02:05:40 PM PDT 23
Finished Oct 29 02:06:09 PM PDT 23
Peak memory 211604 kb
Host smart-eb8f87a2-057d-4204-b46c-dd70e64ba898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223002022351429160655186736529206380589702977148242798483913407687354526234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.rom_ctrl_kmac_err_chk.1223002022351429160655186736529206380589702977148242798483913407687354526234
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.102811049653649018632413143873122966173980504244144705730737657353815230076917
Short name T223
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:05:49 PM PDT 23
Peak memory 211140 kb
Host smart-705d0a78-4393-4b8e-a411-d7d2f9385222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=102811049653649018632413143873122966173980504244144705730737657353815230076917 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.102811049653649018632413143873122966173980504244144705730737657353815230076917
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.6262205728994228622017888455596488234477932556092291103721920025174946535878
Short name T156
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.01 seconds
Started Oct 29 02:05:35 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 212824 kb
Host smart-bd5e9b61-30b3-49ea-8a3d-3adc7267a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6262205728994228622017888455596488234477932556092291103721920025174946535878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.rom_ctrl_smoke.6262205728994228622017888455596488234477932556092291103721920025174946535878
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.50447048364489518653095414407989126337341828504376931273635306899485811746184
Short name T318
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.64 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:06:20 PM PDT 23
Peak memory 212908 kb
Host smart-0804ed1f-5524-4d21-8aa5-a5a8bd5bb060
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504470483644895186530954144079891263373418285043769312736353068
99485811746184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.50447048364489518653095414407989126337341828504376
931273635306899485811746184
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.66112997669983939536996180007451612741716263140590508583482303573635115611395
Short name T355
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:05:49 PM PDT 23
Peak memory 211172 kb
Host smart-2805cc4d-4393-4782-b339-a5be68f974fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66112997669983939536996180007451612741716263140590508583482303573635115611395 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.66112997669983939536996180007451612741716263140590508583482303573635115611395
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.64689147955382745922926411983921349565219693634891090631107019172556186599310
Short name T241
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.62 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:11:21 PM PDT 23
Peak memory 237664 kb
Host smart-30b01a0a-0ea2-4bd9-86d2-032e1ca55bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64689147955382745922926411983921349565219693634891090631107019172556186599310 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.646891479553827459229264119839213495652196936348910906311
07019172556186599310
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.74661322520430034441002561617835524915952370038330152640469695232954153063762
Short name T153
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.03 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 211608 kb
Host smart-b1fe5807-6205-4fe3-b6ed-5c12f0120a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74661322520430034441002561617835524915952370038330152640469695232954153063762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.74661322520430034441002561617835524915952370038330152640469695232954153063762
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.14246874848246447648498204844340496753101696449327450227207503807224725641006
Short name T205
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.02 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:05:51 PM PDT 23
Peak memory 211228 kb
Host smart-3d42e91a-200f-44cf-b01f-95c93048303b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=14246874848246447648498204844340496753101696449327450227207503807224725641006 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.14246874848246447648498204844340496753101696449327450227207503807224725641006
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.8856275277127954625145228759141338550954440602207015875560614778354758843146
Short name T264
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.75 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:06:06 PM PDT 23
Peak memory 212808 kb
Host smart-f6b04141-491e-4a1b-8244-3854fa5ccf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8856275277127954625145228759141338550954440602207015875560614778354758843146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.rom_ctrl_smoke.8856275277127954625145228759141338550954440602207015875560614778354758843146
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.74929184208804066675998675531633999749191435332442989955768048109427633098293
Short name T236
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.68 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 212920 kb
Host smart-c5129b60-311a-4b7b-8cda-d5430e25bcc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749291842088040666759986755316339997491914353324429899557680481
09427633098293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.74929184208804066675998675531633999749191435332442
989955768048109427633098293
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.33018172348224450200070236518807736183856563178175992596871351282705944173911
Short name T266
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:05 PM PDT 23
Peak memory 211036 kb
Host smart-44310dd7-ed23-4792-84fd-3c2045ed15ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018172348224450200070236518807736183856563178175992596871351282705944173911 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.33018172348224450200070236518807736183856563178175992596871351282705944173911
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.79964270294093701236828673187170217687888307615524120112231617260407585386976
Short name T263
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.37 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:11:16 PM PDT 23
Peak memory 237672 kb
Host smart-eeeb4581-e5a6-4a9d-ac2f-4a47a7bd8abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79964270294093701236828673187170217687888307615524120112231617260407585386976 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.799642702940937012368286731871702176878883076155241201122
31617260407585386976
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.74911513102100873048420598469121200887102686678152729077275163822963603630353
Short name T174
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.06 seconds
Started Oct 29 02:05:33 PM PDT 23
Finished Oct 29 02:06:00 PM PDT 23
Peak memory 211612 kb
Host smart-1ee3fa8f-5fea-420d-88c2-9822d504ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74911513102100873048420598469121200887102686678152729077275163822963603630353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.rom_ctrl_kmac_err_chk.74911513102100873048420598469121200887102686678152729077275163822963603630353
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.66599845000449669603562826849542136542915526325950163984386275010564415852870
Short name T3
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:05:50 PM PDT 23
Peak memory 211100 kb
Host smart-262ba5cf-f330-4bbf-b5d4-99638bd2cd78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66599845000449669603562826849542136542915526325950163984386275010564415852870 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.66599845000449669603562826849542136542915526325950163984386275010564415852870
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.414757835767555345052708922014620091980199940509176123795418180991276129392
Short name T288
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.89 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:06:06 PM PDT 23
Peak memory 212836 kb
Host smart-9f7c6419-a6b8-4784-b870-ab6afeb95939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414757835767555345052708922014620091980199940509176123795418180991276129392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_ba
se_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.rom_ctrl_smoke.414757835767555345052708922014620091980199940509176123795418180991276129392
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.30940240517827691235707599853737957174429011033749185728091149627464493758981
Short name T325
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.51 seconds
Started Oct 29 02:05:34 PM PDT 23
Finished Oct 29 02:06:17 PM PDT 23
Peak memory 212908 kb
Host smart-6bda1ca4-6f8a-4a25-9c36-d113b6f41667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309402405178276912357075998537379571744290110337491857280911496
27464493758981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.30940240517827691235707599853737957174429011033749
185728091149627464493758981
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.87693059995904573868274716685367437079348099685133428186274831805209519564987
Short name T229
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:05:51 PM PDT 23
Peak memory 211208 kb
Host smart-2fa15103-78dd-431d-95f3-b7e12c775b55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87693059995904573868274716685367437079348099685133428186274831805209519564987 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.87693059995904573868274716685367437079348099685133428186274831805209519564987
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.107854743566069258202094707137849291183263343342592348553096247349501150533104
Short name T38
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.82 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:11:28 PM PDT 23
Peak memory 237636 kb
Host smart-092c10ed-3456-4e7c-aedf-d9c8e8e81209
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107854743566069258202094707137849291183263343342592348553096247349501150533104 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.10785474356606925820209470713784929118326334334259234855
3096247349501150533104
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.51528795704950525215721783067841812468914936179041313004745721528489995905639
Short name T14
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.23 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:06:04 PM PDT 23
Peak memory 211608 kb
Host smart-11ebc2c3-f595-45a1-9357-3aa360b11318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51528795704950525215721783067841812468914936179041313004745721528489995905639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rom_ctrl_kmac_err_chk.51528795704950525215721783067841812468914936179041313004745721528489995905639
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.42932290389288213389728306770333935351588951624120462337104383534179746672609
Short name T222
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.41 seconds
Started Oct 29 02:05:42 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211176 kb
Host smart-d7da5b14-48d5-490c-a55b-beba4aaf7985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42932290389288213389728306770333935351588951624120462337104383534179746672609 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.42932290389288213389728306770333935351588951624120462337104383534179746672609
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.95235844725706350700358336416339789782577984026979898510141560644003374073601
Short name T228
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.52 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:22 PM PDT 23
Peak memory 212816 kb
Host smart-7e1da068-96b1-4e47-981e-8aefbfb294ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95235844725706350700358336416339789782577984026979898510141560644003374073601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.95235844725706350700358336416339789782577984026979898510141560644003374073601
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.18659499227099239231023156433456913887237797980334071251475903462650144337117
Short name T168
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.55 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:06:23 PM PDT 23
Peak memory 212904 kb
Host smart-d29dc48e-e11a-4045-af06-5157e2766c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186594992270992392310231564334569138872377979803340712514759034
62650144337117 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.18659499227099239231023156433456913887237797980334
071251475903462650144337117
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1492738558812694504687564580356956010231604361565832248844508206726078164271
Short name T293
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:05:49 PM PDT 23
Peak memory 211208 kb
Host smart-f6e2afcb-5f5a-401d-b18f-e23346aa8e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492738558812694504687564580356956010231604361565832248844508206726078164271 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1492738558812694504687564580356956010231604361565832248844508206726078164271
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.92458219486935107587643032409807833329648748467769312304481983851671308008615
Short name T315
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.74 seconds
Started Oct 29 02:05:39 PM PDT 23
Finished Oct 29 02:11:24 PM PDT 23
Peak memory 237636 kb
Host smart-237f64ef-4f29-4a8a-844f-cb3888370fec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92458219486935107587643032409807833329648748467769312304481983851671308008615 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.924582194869351075876430324098078333296487484677693123044
81983851671308008615
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.6549735724057617045162955587617243326572900189245611515822613515045928554318
Short name T220
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.55 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:06:02 PM PDT 23
Peak memory 211604 kb
Host smart-bddc2c10-f31e-48af-8a14-30a55c984748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6549735724057617045162955587617243326572900189245611515822613515045928554318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.rom_ctrl_kmac_err_chk.6549735724057617045162955587617243326572900189245611515822613515045928554318
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.62672850058794477782218640570345466230824467267623434177843246346573632940210
Short name T170
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.33 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:05:51 PM PDT 23
Peak memory 211156 kb
Host smart-b2e46216-13e4-41ce-96db-e7cf672229c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62672850058794477782218640570345466230824467267623434177843246346573632940210 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.62672850058794477782218640570345466230824467267623434177843246346573632940210
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.24633191021675886980179398009933984053235803732976950100966472713122638112320
Short name T268
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Oct 29 02:05:38 PM PDT 23
Finished Oct 29 02:06:07 PM PDT 23
Peak memory 212820 kb
Host smart-4ec6e69f-dfef-4cbb-8667-c7e83702f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24633191021675886980179398009933984053235803732976950100966472713122638112320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_smoke.24633191021675886980179398009933984053235803732976950100966472713122638112320
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.101197580786221529258091930206107791602928528155030503923837075785140953057887
Short name T120
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.08 seconds
Started Oct 29 02:05:35 PM PDT 23
Finished Oct 29 02:06:18 PM PDT 23
Peak memory 212872 kb
Host smart-826d15d7-e615-4e97-894b-f7b6e3b03477
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101197580786221529258091930206107791602928528155030503923837075
785140953057887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.1011975807862215292580919302061077916029285281550
30503923837075785140953057887
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.24636125997343664177480520503598932075776759016076070900351957844587426604808
Short name T126
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:05:49 PM PDT 23
Peak memory 211188 kb
Host smart-b923225b-b632-4c0f-b6f7-6c9d792b713a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24636125997343664177480520503598932075776759016076070900351957844587426604808 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.24636125997343664177480520503598932075776759016076070900351957844587426604808
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.67394378400942058421151750165078003053738771787697473150925321404947586255853
Short name T43
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.79 seconds
Started Oct 29 02:05:37 PM PDT 23
Finished Oct 29 02:11:20 PM PDT 23
Peak memory 237744 kb
Host smart-e3028223-adec-49c3-bff7-f35904e65570
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67394378400942058421151750165078003053738771787697473150925321404947586255853 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.673943784009420584211517501650780030537387717876974731509
25321404947586255853
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.110423668964365728092011638983514423410976741218908068059042449918515381233722
Short name T320
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.81 seconds
Started Oct 29 02:05:36 PM PDT 23
Finished Oct 29 02:06:01 PM PDT 23
Peak memory 211580 kb
Host smart-94f86dc3-4e4d-494a-95e5-15305dc8e76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110423668964365728092011638983514423410976741218908068059042449918515381233722 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.rom_ctrl_kmac_err_chk.110423668964365728092011638983514423410976741218908068059042449918515381233722
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.84224043603165321810244099753207432376071854251812178770979235772649266965685
Short name T184
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:07 PM PDT 23
Peak memory 211172 kb
Host smart-5c38f915-144e-4957-a834-1645985fa4c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84224043603165321810244099753207432376071854251812178770979235772649266965685 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.84224043603165321810244099753207432376071854251812178770979235772649266965685
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.83619508981713809936154529632396350551799902738198972847569104418906194796649
Short name T221
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.37 seconds
Started Oct 29 02:05:52 PM PDT 23
Finished Oct 29 02:06:21 PM PDT 23
Peak memory 212816 kb
Host smart-221b2be7-db04-4f3c-a41d-de9ea70526e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83619508981713809936154529632396350551799902738198972847569104418906194796649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.rom_ctrl_smoke.83619508981713809936154529632396350551799902738198972847569104418906194796649
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.95189303823784043227482482490798149106308361269960923171619523825003256847333
Short name T198
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.2 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:37 PM PDT 23
Peak memory 212920 kb
Host smart-81f1ae9c-0246-436f-8bdf-fd98e316cb64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951893038237840432274824824907981491063083612699609231716195238
25003256847333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.95189303823784043227482482490798149106308361269960
923171619523825003256847333
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.92117717530147611599575774307851159000964959618440524278753033169681515008476
Short name T103
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Oct 29 02:05:47 PM PDT 23
Finished Oct 29 02:06:00 PM PDT 23
Peak memory 211168 kb
Host smart-271238ad-1ba6-4856-a88f-5c36cdb1abfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92117717530147611599575774307851159000964959618440524278753033169681515008476 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.92117717530147611599575774307851159000964959618440524278753033169681515008476
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.47921212378104115829880099622997732908796628063970077764508798244401442163629
Short name T12
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.31 seconds
Started Oct 29 02:05:43 PM PDT 23
Finished Oct 29 02:11:27 PM PDT 23
Peak memory 237696 kb
Host smart-d411b343-ea8e-4518-8861-25a8f6be0d3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47921212378104115829880099622997732908796628063970077764508798244401442163629 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.479212123781041158298800996229977329087966280639700777645
08798244401442163629
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.15852252553501061183865393739612693265874314691022538547945976035235345191274
Short name T261
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.9 seconds
Started Oct 29 02:05:51 PM PDT 23
Finished Oct 29 02:06:17 PM PDT 23
Peak memory 211540 kb
Host smart-114bc233-2265-4bcf-931b-b16263121735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15852252553501061183865393739612693265874314691022538547945976035235345191274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.15852252553501061183865393739612693265874314691022538547945976035235345191274
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.60322695885062929857994319145397344223030236851043882727935175418094844756752
Short name T335
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.19 seconds
Started Oct 29 02:05:44 PM PDT 23
Finished Oct 29 02:05:57 PM PDT 23
Peak memory 211172 kb
Host smart-4a15fd29-40bd-4cbb-ae6f-962fcca55b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60322695885062929857994319145397344223030236851043882727935175418094844756752 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.60322695885062929857994319145397344223030236851043882727935175418094844756752
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.61829523489598549431010132469848166510835038284735545622883185909633670647092
Short name T300
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.25 seconds
Started Oct 29 02:05:45 PM PDT 23
Finished Oct 29 02:06:14 PM PDT 23
Peak memory 212824 kb
Host smart-c504eccb-9353-4cd0-b5a5-c169a4347e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61829523489598549431010132469848166510835038284735545622883185909633670647092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.61829523489598549431010132469848166510835038284735545622883185909633670647092
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4544339092037038259559708290172814277183134081234570190158326222288669670968
Short name T34
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.67 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 212836 kb
Host smart-7f216d95-268c-4b15-9253-c87ee6de3327
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454433909203703825955970829017281427718313408123457019015832622
2288669670968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.454433909203703825955970829017281427718313408123457
0190158326222288669670968
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.108096242144198103292583786537777133059183795834324103173826648029100808851388
Short name T193
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Oct 29 02:05:48 PM PDT 23
Finished Oct 29 02:06:00 PM PDT 23
Peak memory 211088 kb
Host smart-e892a683-92e1-43e3-96ce-212d2b9f55cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108096242144198103292583786537777133059183795834324103173826648029100808851388 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.108096242144198103292583786537777133059183795834324103173826648029100808851388
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.89091214784569526275471248019960270403931621375362580950421905092499271994014
Short name T239
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.58 seconds
Started Oct 29 02:05:43 PM PDT 23
Finished Oct 29 02:11:26 PM PDT 23
Peak memory 237716 kb
Host smart-40160718-cb7b-4009-8572-971c6f4e9247
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89091214784569526275471248019960270403931621375362580950421905092499271994014 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.890912147845695262754712480199602704039316213753625809504
21905092499271994014
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.7623992943171922199493459538592223095053280107959019812766411570272338672693
Short name T141
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.62 seconds
Started Oct 29 02:05:44 PM PDT 23
Finished Oct 29 02:06:10 PM PDT 23
Peak memory 211548 kb
Host smart-fe445cc6-834e-4f0b-8a55-852bf7115563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7623992943171922199493459538592223095053280107959019812766411570272338672693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.rom_ctrl_kmac_err_chk.7623992943171922199493459538592223095053280107959019812766411570272338672693
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.71537771131478792683281415004754664409558851808177235450456492356731585150395
Short name T114
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.14 seconds
Started Oct 29 02:05:41 PM PDT 23
Finished Oct 29 02:05:56 PM PDT 23
Peak memory 211180 kb
Host smart-662bd6ed-37df-4855-b0b8-2a8f8dd9c5a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71537771131478792683281415004754664409558851808177235450456492356731585150395 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.71537771131478792683281415004754664409558851808177235450456492356731585150395
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.75829237322391156637903058566756172913897554766786077561715934989756675185332
Short name T271
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.1 seconds
Started Oct 29 02:05:48 PM PDT 23
Finished Oct 29 02:06:16 PM PDT 23
Peak memory 212740 kb
Host smart-d75ed982-b008-4fe3-aaf4-9527e23e67c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75829237322391156637903058566756172913897554766786077561715934989756675185332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.rom_ctrl_smoke.75829237322391156637903058566756172913897554766786077561715934989756675185332
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.1204152328975983510820484562058248360502563974898527113509155672888970456420
Short name T175
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.43 seconds
Started Oct 29 02:05:53 PM PDT 23
Finished Oct 29 02:06:36 PM PDT 23
Peak memory 212924 kb
Host smart-a00dae0e-8e7d-4857-97a0-d62634aac45d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120415232897598351082048456205824836050256397489852711350915567
2888970456420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.120415232897598351082048456205824836050256397489852
7113509155672888970456420
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.10997028903562226812844393248420766800488948938862670339148578081441082776435
Short name T123
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:33 PM PDT 23
Peak memory 211180 kb
Host smart-745b150b-372a-461d-8728-0185eea039de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10997028903562226812844393248420766800488948938862670339148578081441082776435 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.10997028903562226812844393248420766800488948938862670339148578081441082776435
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.101756588545955391496222377705666408084805927956573428673475809166546048840729
Short name T246
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.56 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:09:57 PM PDT 23
Peak memory 237096 kb
Host smart-e65d6f83-3b8b-4993-8788-96c8bd9cb291
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101756588545955391496222377705666408084805927956573428673475809166546048840729 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.101756588545955391496222377705666408084805927956573428673
475809166546048840729
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.66501580729433599863537117394562566495560668696192502948722712570389445257421
Short name T190
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.95 seconds
Started Oct 29 02:04:26 PM PDT 23
Finished Oct 29 02:04:51 PM PDT 23
Peak memory 211604 kb
Host smart-ff887414-4777-4125-a7ff-5db41b63791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66501580729433599863537117394562566495560668696192502948722712570389445257421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.rom_ctrl_kmac_err_chk.66501580729433599863537117394562566495560668696192502948722712570389445257421
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.82494243336061824991078770961944179452764854505479331749144836235418090160242
Short name T155
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.32 seconds
Started Oct 29 02:04:14 PM PDT 23
Finished Oct 29 02:04:27 PM PDT 23
Peak memory 211192 kb
Host smart-1d003be0-d059-4c8a-99da-87fc1f241157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82494243336061824991078770961944179452764854505479331749144836235418090160242 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.82494243336061824991078770961944179452764854505479331749144836235418090160242
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.99987455855282811236955258544558386661883849299392679047401042951553590156163
Short name T353
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.03 seconds
Started Oct 29 02:04:21 PM PDT 23
Finished Oct 29 02:04:50 PM PDT 23
Peak memory 212760 kb
Host smart-a72a7f48-9beb-4421-a939-cc30211f9700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99987455855282811236955258544558386661883849299392679047401042951553590156163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_smoke.99987455855282811236955258544558386661883849299392679047401042951553590156163
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.73522083419953761040644852268948496472929263078223554826874817007787037835028
Short name T331
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.41 seconds
Started Oct 29 02:04:21 PM PDT 23
Finished Oct 29 02:05:03 PM PDT 23
Peak memory 212968 kb
Host smart-6b3fb66a-e245-4025-8a09-c1ce34d7e357
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735220834199537610406448522689484964729292630782235548268748170
07787037835028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.735220834199537610406448522689484964729292630782235
54826874817007787037835028
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.15580095324769826611442016036011659233464662536871052513760421067119261197829
Short name T277
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.62 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:43 PM PDT 23
Peak memory 211180 kb
Host smart-bf3857f6-4cf9-4caf-8609-c7442630e49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580095324769826611442016036011659233464662536871052513760421067119261197829 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.15580095324769826611442016036011659233464662536871052513760421067119261197829
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.110424831861613416136989785418609147564354032777653023988402370037262275606924
Short name T147
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.65 seconds
Started Oct 29 02:04:18 PM PDT 23
Finished Oct 29 02:09:53 PM PDT 23
Peak memory 237096 kb
Host smart-78ce5b80-980c-4c72-a540-81b9f56d50ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110424831861613416136989785418609147564354032777653023988402370037262275606924 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.110424831861613416136989785418609147564354032777653023988
402370037262275606924
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.107590559817952529320001730590137614933867848171997482795277213418280328063622
Short name T242
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.43 seconds
Started Oct 29 02:04:26 PM PDT 23
Finished Oct 29 02:04:52 PM PDT 23
Peak memory 211580 kb
Host smart-9dcfcbf9-1323-4750-b0fb-7fb6cce88bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107590559817952529320001730590137614933867848171997482795277213418280328063622 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.rom_ctrl_kmac_err_chk.107590559817952529320001730590137614933867848171997482795277213418280328063622
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.105020779989920919125534011220320944419702357938556106173209313101548873862218
Short name T256
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.81 seconds
Started Oct 29 02:04:17 PM PDT 23
Finished Oct 29 02:04:30 PM PDT 23
Peak memory 211116 kb
Host smart-5355ed7d-ee09-43d0-aef8-15174fbeda29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105020779989920919125534011220320944419702357938556106173209313101548873862218 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.105020779989920919125534011220320944419702357938556106173209313101548873862218
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.70010812185907095935502355379759353318148566273651453925650710455184743746422
Short name T4
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.68 seconds
Started Oct 29 02:04:22 PM PDT 23
Finished Oct 29 02:04:50 PM PDT 23
Peak memory 212820 kb
Host smart-19c1ab22-a7c4-4268-ad3b-d1d72d9bd9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70010812185907095935502355379759353318148566273651453925650710455184743746422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_smoke.70010812185907095935502355379759353318148566273651453925650710455184743746422
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.82436690042755843659471340817792311759617175676010714945225234130299634699843
Short name T296
Test name
Test status
Simulation time 9415977006 ps
CPU time 43 seconds
Started Oct 29 02:04:25 PM PDT 23
Finished Oct 29 02:05:08 PM PDT 23
Peak memory 212968 kb
Host smart-7cf5b00b-3fd7-43ba-babf-557fc36e0982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824366900427558436594713408177923117596171756760107149452252341
30299634699843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.824366900427558436594713408177923117596171756760107
14945225234130299634699843
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.8193342529444430242646288453068533093558457595172318131124825791310250308998
Short name T342
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.04 seconds
Started Oct 29 02:04:28 PM PDT 23
Finished Oct 29 02:04:40 PM PDT 23
Peak memory 211152 kb
Host smart-e1eb8a27-8295-4f91-b663-fa170b62480d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8193342529444430242646288453068533093558457595172318131124825791310250308998 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.8193342529444430242646288453068533093558457595172318131124825791310250308998
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.113984762044802624370874905415941364259048565900823467950307001510286287234841
Short name T262
Test name
Test status
Simulation time 69854280986 ps
CPU time 326.77 seconds
Started Oct 29 02:04:28 PM PDT 23
Finished Oct 29 02:09:55 PM PDT 23
Peak memory 237084 kb
Host smart-c1a74477-bbac-4961-8f4f-c9077300dd5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113984762044802624370874905415941364259048565900823467950307001510286287234841 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.113984762044802624370874905415941364259048565900823467950
307001510286287234841
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.23979219287366214261373244388798104256646475499724069751274208322782512597730
Short name T40
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.44 seconds
Started Oct 29 02:04:28 PM PDT 23
Finished Oct 29 02:04:54 PM PDT 23
Peak memory 211596 kb
Host smart-b155bc9d-69ff-45cd-a6ed-af1fcb643332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23979219287366214261373244388798104256646475499724069751274208322782512597730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.rom_ctrl_kmac_err_chk.23979219287366214261373244388798104256646475499724069751274208322782512597730
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.85418691302460816161259126194995138418094023958906684238847397078210429666981
Short name T6
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:04:33 PM PDT 23
Peak memory 211216 kb
Host smart-edbdb456-82b8-4934-8e50-96d84c3bb662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85418691302460816161259126194995138418094023958906684238847397078210429666981 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.85418691302460816161259126194995138418094023958906684238847397078210429666981
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.84902224290480190415207218378292653369126428167656399578668815112353754370859
Short name T349
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.65 seconds
Started Oct 29 02:04:29 PM PDT 23
Finished Oct 29 02:04:59 PM PDT 23
Peak memory 212360 kb
Host smart-4ea6d8b2-19d4-4817-98fa-181219d50a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84902224290480190415207218378292653369126428167656399578668815112353754370859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.rom_ctrl_smoke.84902224290480190415207218378292653369126428167656399578668815112353754370859
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.19219808530851869011792947144377232699364791254810163526892084417759227294116
Short name T240
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.41 seconds
Started Oct 29 02:04:16 PM PDT 23
Finished Oct 29 02:04:59 PM PDT 23
Peak memory 212932 kb
Host smart-6c7ca90a-8c5a-4460-95a1-c5ec9d757f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192198085308518690117929471443772326993647912548101635268920844
17759227294116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.192198085308518690117929471443772326993647912548101
63526892084417759227294116
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.8102539074563061390631642985104084770003847440736872934951969195582567308952
Short name T291
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Oct 29 02:04:25 PM PDT 23
Finished Oct 29 02:04:37 PM PDT 23
Peak memory 211188 kb
Host smart-500ffbe0-5cda-4736-969a-0dd6dd687edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8102539074563061390631642985104084770003847440736872934951969195582567308952 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.8102539074563061390631642985104084770003847440736872934951969195582567308952
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.302288392650711248040715260129059301580638124711443237911886255143948186138
Short name T142
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.44 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:10:03 PM PDT 23
Peak memory 237560 kb
Host smart-c49e08af-cf99-4caf-9077-3af48d6afeaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302288392650711248040715260129059301580638124711443237911886255143948186138 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.302288392650711248040715260129059301580638124711443237911886
255143948186138
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.88284656327900178394891678915821480597571925406361761690189586584494220456062
Short name T208
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.64 seconds
Started Oct 29 02:04:25 PM PDT 23
Finished Oct 29 02:04:50 PM PDT 23
Peak memory 211604 kb
Host smart-5b2f8c2b-bb7f-4802-95b7-8aa2f483dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88284656327900178394891678915821480597571925406361761690189586584494220456062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.88284656327900178394891678915821480597571925406361761690189586584494220456062
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.31271097118768403685246198820309265388719953473836812853477936541776511746320
Short name T159
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.81 seconds
Started Oct 29 02:04:27 PM PDT 23
Finished Oct 29 02:04:40 PM PDT 23
Peak memory 211156 kb
Host smart-4672c84e-7cdf-4620-b022-03e1b410c251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31271097118768403685246198820309265388719953473836812853477936541776511746320 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.31271097118768403685246198820309265388719953473836812853477936541776511746320
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.73758117707798213297348762452650584065686569736995035489595259629492258216401
Short name T210
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.04 seconds
Started Oct 29 02:04:27 PM PDT 23
Finished Oct 29 02:04:55 PM PDT 23
Peak memory 212812 kb
Host smart-5a4f5b8a-fe7d-4593-b76a-894d748bac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73758117707798213297348762452650584065686569736995035489595259629492258216401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.73758117707798213297348762452650584065686569736995035489595259629492258216401
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.23502286335951585398153082812963453535013922055459319726484172245769404178874
Short name T124
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.96 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:05:02 PM PDT 23
Peak memory 212952 kb
Host smart-5d17c273-c118-4882-9932-4dfab7cdb090
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235022863359515853981530828129634535350139220554593197264841722
45769404178874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.235022863359515853981530828129634535350139220554593
19726484172245769404178874
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.34428607532891943744301893682332205383892375887382957099722280977704177768591
Short name T253
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Oct 29 02:04:20 PM PDT 23
Finished Oct 29 02:04:32 PM PDT 23
Peak memory 211076 kb
Host smart-796976cb-8c94-487d-9ed7-f6277584e99d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34428607532891943744301893682332205383892375887382957099722280977704177768591 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.34428607532891943744301893682332205383892375887382957099722280977704177768591
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.112069978421941111124987580457462403760382462593040660231244371823016680592941
Short name T44
Test name
Test status
Simulation time 69854280986 ps
CPU time 332.45 seconds
Started Oct 29 02:04:19 PM PDT 23
Finished Oct 29 02:09:52 PM PDT 23
Peak memory 237152 kb
Host smart-36fe98ae-9956-4b48-8eb1-f40b9d0f5e1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112069978421941111124987580457462403760382462593040660231244371823016680592941 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.112069978421941111124987580457462403760382462593040660231
244371823016680592941
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.53993597590797266562184304570516265485191551154612833664013427942957113257356
Short name T113
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.76 seconds
Started Oct 29 02:04:22 PM PDT 23
Finished Oct 29 02:04:47 PM PDT 23
Peak memory 211560 kb
Host smart-37c60b94-74e4-4ea6-b4b8-d0ed9f4c5682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53993597590797266562184304570516265485191551154612833664013427942957113257356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rom_ctrl_kmac_err_chk.53993597590797266562184304570516265485191551154612833664013427942957113257356
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.84628692307118724281227013670337043830539773419890877487361886798356679118836
Short name T158
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.99 seconds
Started Oct 29 02:04:28 PM PDT 23
Finished Oct 29 02:04:41 PM PDT 23
Peak memory 211156 kb
Host smart-1a04c850-de97-4c1b-bc44-6eb895954ba9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84628692307118724281227013670337043830539773419890877487361886798356679118836 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.84628692307118724281227013670337043830539773419890877487361886798356679118836
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.49173389074977108597746822585046347033905719655519247773957051392931897179756
Short name T162
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.09 seconds
Started Oct 29 02:04:22 PM PDT 23
Finished Oct 29 02:04:50 PM PDT 23
Peak memory 212760 kb
Host smart-444fc5df-e8f8-4e27-a689-d45004c8bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49173389074977108597746822585046347033905719655519247773957051392931897179756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.49173389074977108597746822585046347033905719655519247773957051392931897179756
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.54150913128088564200319477513145253028943350721170046778318292216676926084405
Short name T179
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.19 seconds
Started Oct 29 02:04:23 PM PDT 23
Finished Oct 29 02:05:07 PM PDT 23
Peak memory 212944 kb
Host smart-932b85af-9af0-4ff9-bb0f-8b2de8a8c7d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541509131280885642003194775131452530289433507211700467783182922
16676926084405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.541509131280885642003194775131452530289433507211700
46778318292216676926084405
Directory /workspace/9.rom_ctrl_stress_all/latest
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