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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.27 96.89 84.90 97.17 93.33 96.41 97.89 86.31


Total test records in report: 450
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T260 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.55822451898983278693392549483973797307422951836627866331349219147244053666711 Nov 01 02:44:17 PM PDT 23 Nov 01 02:49:46 PM PDT 23 69854280986 ps
T261 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.48580379961373252330908636037229930133139697313129829016024827999134648911535 Nov 01 02:43:28 PM PDT 23 Nov 01 02:43:54 PM PDT 23 6233818126 ps
T262 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.29714168015349808413830579036350575939844223417557370839664780979743778521339 Nov 01 02:44:29 PM PDT 23 Nov 01 02:44:47 PM PDT 23 3151732636 ps
T263 /workspace/coverage/default/23.rom_ctrl_smoke.63516595274066345941279478935961977386043493265333647269446216673599404204901 Nov 01 02:44:23 PM PDT 23 Nov 01 02:44:53 PM PDT 23 6265461576 ps
T264 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.71508912272355264260631328942248993557326090113235597555390771671267825304896 Nov 01 02:44:18 PM PDT 23 Nov 01 02:44:44 PM PDT 23 6233818126 ps
T265 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.97378511510134877455875921418433136559842308330248479857533822254530158521264 Nov 01 02:43:30 PM PDT 23 Nov 01 02:43:44 PM PDT 23 3151732636 ps
T266 /workspace/coverage/default/21.rom_ctrl_alert_test.99548214417683229409698605500012815927466619912408213455347894793635814369139 Nov 01 02:44:17 PM PDT 23 Nov 01 02:44:30 PM PDT 23 3124113076 ps
T267 /workspace/coverage/default/27.rom_ctrl_alert_test.44650662574436616490153697455824514169214769385724790892357843229181277574855 Nov 01 02:44:22 PM PDT 23 Nov 01 02:44:36 PM PDT 23 3124113076 ps
T268 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.96517954178171776932594635140229120821961152886983357902095440934399062627433 Nov 01 02:44:00 PM PDT 23 Nov 01 02:49:44 PM PDT 23 69854280986 ps
T269 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.16765086517311890256724522269726994230542680781530994425149481356331851745632 Nov 01 02:45:04 PM PDT 23 Nov 01 02:45:23 PM PDT 23 3151732636 ps
T270 /workspace/coverage/default/47.rom_ctrl_stress_all.12372632059718855426828186827618989691474250393404614617240397488608199041265 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:58 PM PDT 23 9415977006 ps
T271 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.89412680257902793926277620957025110839327244265190110946473709752160384363405 Nov 01 02:43:30 PM PDT 23 Nov 01 02:43:44 PM PDT 23 3151732636 ps
T272 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.6462865557430647191458948358204766496576232666148584703298290698521601299164 Nov 01 02:44:05 PM PDT 23 Nov 01 02:44:22 PM PDT 23 3151732636 ps
T273 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.71802403956863352943669039806931969003548446891604976389035606848321530195900 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:16 PM PDT 23 3151732636 ps
T274 /workspace/coverage/default/43.rom_ctrl_stress_all.74538516467979123063506000033625571975907186354841010662761951745119733417184 Nov 01 02:44:20 PM PDT 23 Nov 01 02:45:04 PM PDT 23 9415977006 ps
T275 /workspace/coverage/default/2.rom_ctrl_stress_all.114442573628748523913653417277808199370812122680133883074786183528266205228388 Nov 01 02:43:53 PM PDT 23 Nov 01 02:44:39 PM PDT 23 9415977006 ps
T276 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.21620868389155132703232798844541378304745702265241369588895891484519548252170 Nov 01 02:44:28 PM PDT 23 Nov 01 02:44:59 PM PDT 23 6233818126 ps
T277 /workspace/coverage/default/44.rom_ctrl_alert_test.86491375684174915005429775596282199918910902607485180254414565288205742615618 Nov 01 02:45:16 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3124113076 ps
T278 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.115546660895331448070617519929276852110855731895429082851021809297752835130570 Nov 01 02:44:32 PM PDT 23 Nov 01 02:44:48 PM PDT 23 3151732636 ps
T279 /workspace/coverage/default/47.rom_ctrl_alert_test.79318607917378454548559993917466096845559483988162388973901158909687714754771 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:28 PM PDT 23 3124113076 ps
T280 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.105414235734852075504344264013270784168481684775458066445602063630946937370116 Nov 01 02:44:20 PM PDT 23 Nov 01 02:44:48 PM PDT 23 6233818126 ps
T281 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.76951445081447376548954776621362056473130879318980610215210409907063589341756 Nov 01 02:44:06 PM PDT 23 Nov 01 02:44:35 PM PDT 23 6233818126 ps
T282 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1593879122860935070305043223754313984788395405982799003112717318786519456462 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3151732636 ps
T283 /workspace/coverage/default/38.rom_ctrl_smoke.55810012205136694669533460903368686602166934521621833102275825953842633750360 Nov 01 02:44:26 PM PDT 23 Nov 01 02:44:56 PM PDT 23 6265461576 ps
T284 /workspace/coverage/default/36.rom_ctrl_stress_all.50325881836855987635243349404831776941684566924640334520781213744861186462836 Nov 01 02:44:29 PM PDT 23 Nov 01 02:45:16 PM PDT 23 9415977006 ps
T285 /workspace/coverage/default/16.rom_ctrl_alert_test.89193509783646906580147374731038999643313706597824540978957759799180739636624 Nov 01 02:44:00 PM PDT 23 Nov 01 02:44:13 PM PDT 23 3124113076 ps
T286 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.59203287133424844275262822827733757357889799784283339682394532866779489736443 Nov 01 02:44:31 PM PDT 23 Nov 01 02:50:17 PM PDT 23 69854280986 ps
T287 /workspace/coverage/default/46.rom_ctrl_stress_all.27341643149338069623058269368639259906773905014667524702198449780970078831466 Nov 01 02:45:13 PM PDT 23 Nov 01 02:45:57 PM PDT 23 9415977006 ps
T288 /workspace/coverage/default/20.rom_ctrl_smoke.55314866182253026665761170344990818769135061514991949986296278177824343750691 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:32 PM PDT 23 6265461576 ps
T289 /workspace/coverage/default/22.rom_ctrl_stress_all.51510450355919467816197371327406987059988070055197115651706893791048111767159 Nov 01 02:44:17 PM PDT 23 Nov 01 02:45:02 PM PDT 23 9415977006 ps
T34 /workspace/coverage/default/0.rom_ctrl_sec_cm.95778758854887871130838838349023527172374492092006135077719576635133806622056 Nov 01 02:44:05 PM PDT 23 Nov 01 02:46:05 PM PDT 23 3444857586 ps
T290 /workspace/coverage/default/34.rom_ctrl_stress_all.113892450103332689099304870863193198841615303207183192224727632786132224847225 Nov 01 02:44:42 PM PDT 23 Nov 01 02:45:26 PM PDT 23 9415977006 ps
T291 /workspace/coverage/default/21.rom_ctrl_stress_all.32541218436079803395172737705079156655451949808183870845882233999419545057741 Nov 01 02:44:03 PM PDT 23 Nov 01 02:44:50 PM PDT 23 9415977006 ps
T292 /workspace/coverage/default/31.rom_ctrl_smoke.34649500667675335321494583704338282116312380872434277542031330391611496653907 Nov 01 02:44:30 PM PDT 23 Nov 01 02:45:02 PM PDT 23 6265461576 ps
T293 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.22884910852325720804690850821843311667646605383680696281916767840209164718811 Nov 01 02:45:13 PM PDT 23 Nov 01 02:50:52 PM PDT 23 69854280986 ps
T294 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.113195195242120031789796675233548760548073120633230426801341936489045884212753 Nov 01 02:44:26 PM PDT 23 Nov 01 02:44:53 PM PDT 23 6233818126 ps
T295 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.31541746687543020924780939994955675496715118222842496589264555473370112397963 Nov 01 02:44:17 PM PDT 23 Nov 01 02:44:44 PM PDT 23 6233818126 ps
T296 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.112007601999615680417521371354717564114485101348684044455786153985927065325998 Nov 01 02:44:29 PM PDT 23 Nov 01 02:44:47 PM PDT 23 3151732636 ps
T297 /workspace/coverage/default/41.rom_ctrl_alert_test.14628020774625324826300258072130024953557470294595225563235084751778322957517 Nov 01 02:44:37 PM PDT 23 Nov 01 02:44:50 PM PDT 23 3124113076 ps
T298 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.66060537205795089976171894149075091975378385875404438546815352718936228188666 Nov 01 02:45:17 PM PDT 23 Nov 01 02:50:57 PM PDT 23 69854280986 ps
T299 /workspace/coverage/default/9.rom_ctrl_alert_test.89722078382903256319863277044586270710522153913002765431040067327832130512903 Nov 01 02:43:27 PM PDT 23 Nov 01 02:43:41 PM PDT 23 3124113076 ps
T300 /workspace/coverage/default/10.rom_ctrl_smoke.53845557442213781099242278708429257572728166154994364627919416185024200144919 Nov 01 02:43:55 PM PDT 23 Nov 01 02:44:25 PM PDT 23 6265461576 ps
T301 /workspace/coverage/default/20.rom_ctrl_stress_all.104745817434178514786504517212159596530510866977421502895153930825021355004016 Nov 01 02:44:09 PM PDT 23 Nov 01 02:44:55 PM PDT 23 9415977006 ps
T302 /workspace/coverage/default/29.rom_ctrl_smoke.50903464158339964834267807004817525526663454477498443289386916822581790906256 Nov 01 02:44:25 PM PDT 23 Nov 01 02:44:55 PM PDT 23 6265461576 ps
T303 /workspace/coverage/default/16.rom_ctrl_stress_all.109644435389034114507940825108551414403894234100172644157463273765599920078474 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:45 PM PDT 23 9415977006 ps
T304 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.88082768357284024495165285383737268274893749307936851406691675641363574498159 Nov 01 02:43:55 PM PDT 23 Nov 01 02:49:39 PM PDT 23 69854280986 ps
T35 /workspace/coverage/default/1.rom_ctrl_sec_cm.22010205351892414029043856788198464964266229369478782426418211077216268451800 Nov 01 02:44:08 PM PDT 23 Nov 01 02:46:09 PM PDT 23 3444857586 ps
T305 /workspace/coverage/default/14.rom_ctrl_alert_test.113275345108333315912338818074021150906724201123145750691559473315740118638842 Nov 01 02:44:02 PM PDT 23 Nov 01 02:44:18 PM PDT 23 3124113076 ps
T306 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.83969698892464536463244534945786341967168641539127087876765055190804553678842 Nov 01 02:44:00 PM PDT 23 Nov 01 02:44:16 PM PDT 23 3151732636 ps
T307 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.93491103694961150180171967017366378506089324835889024002155338778512322331473 Nov 01 02:44:26 PM PDT 23 Nov 01 02:50:11 PM PDT 23 69854280986 ps
T308 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.67229432056158988685148666644617725506358910146112494175834393891757250374437 Nov 01 02:44:39 PM PDT 23 Nov 01 02:50:20 PM PDT 23 69854280986 ps
T309 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.78366441396646914113941283779116361315020461420897488699634976951211972234495 Nov 01 02:44:19 PM PDT 23 Nov 01 02:44:33 PM PDT 23 3151732636 ps
T310 /workspace/coverage/default/48.rom_ctrl_smoke.52377427605673602436377425479169534781758739196574857695786629984137920606731 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:48 PM PDT 23 6265461576 ps
T311 /workspace/coverage/default/42.rom_ctrl_stress_all.16919117017448123639569546950750904443211900866092697105248512161494123196579 Nov 01 02:44:54 PM PDT 23 Nov 01 02:45:39 PM PDT 23 9415977006 ps
T312 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.59545872813359582974308264229953934531539408692325059234001169065409531322312 Nov 01 02:44:03 PM PDT 23 Nov 01 02:44:20 PM PDT 23 3151732636 ps
T313 /workspace/coverage/default/47.rom_ctrl_smoke.24204382418127145539941128583526334419072241042012679465954100757293985090008 Nov 01 02:45:06 PM PDT 23 Nov 01 02:45:40 PM PDT 23 6265461576 ps
T314 /workspace/coverage/default/14.rom_ctrl_stress_all.53934693118524843681764317503830571454163222809558718084845666480223963459282 Nov 01 02:44:04 PM PDT 23 Nov 01 02:44:49 PM PDT 23 9415977006 ps
T315 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.10273669927087052005753349080352152250991768135135255553807379233685887642304 Nov 01 02:44:18 PM PDT 23 Nov 01 02:44:33 PM PDT 23 3151732636 ps
T316 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.92649839271616304666469352313235665883914536164419504239898262297467512648189 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:17 PM PDT 23 3151732636 ps
T317 /workspace/coverage/default/18.rom_ctrl_alert_test.83525647000146627770009996572600370625820114062247650622651723186771851301954 Nov 01 02:44:06 PM PDT 23 Nov 01 02:44:22 PM PDT 23 3124113076 ps
T318 /workspace/coverage/default/42.rom_ctrl_alert_test.25430285190945237821148244938343881506402266306906463148309343259273445017816 Nov 01 02:44:30 PM PDT 23 Nov 01 02:44:46 PM PDT 23 3124113076 ps
T319 /workspace/coverage/default/8.rom_ctrl_alert_test.76273607528652917450619392631986098937614401119943884081405031267261718057829 Nov 01 02:43:29 PM PDT 23 Nov 01 02:43:43 PM PDT 23 3124113076 ps
T320 /workspace/coverage/default/39.rom_ctrl_smoke.45796129749020316708993815638557660124492436539841555201324887463562895641371 Nov 01 02:44:30 PM PDT 23 Nov 01 02:45:03 PM PDT 23 6265461576 ps
T321 /workspace/coverage/default/6.rom_ctrl_alert_test.54619130300120525645062621849475183494756739895881650843923231872017606143329 Nov 01 02:44:06 PM PDT 23 Nov 01 02:44:22 PM PDT 23 3124113076 ps
T322 /workspace/coverage/default/23.rom_ctrl_stress_all.13133191397880474500629840076594905434977857548096517592886348754055354410189 Nov 01 02:44:23 PM PDT 23 Nov 01 02:45:07 PM PDT 23 9415977006 ps
T323 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.94497737059088383841775192432567891646254495715080819295982942703993052080561 Nov 01 02:43:49 PM PDT 23 Nov 01 02:44:02 PM PDT 23 3151732636 ps
T324 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.112497040259173599232229840708334500533504824586336146999957815057655324893495 Nov 01 02:44:19 PM PDT 23 Nov 01 02:44:46 PM PDT 23 6233818126 ps
T325 /workspace/coverage/default/28.rom_ctrl_stress_all.48979407306527244001951656304231474919860020604841872416540493996177119577037 Nov 01 02:44:25 PM PDT 23 Nov 01 02:45:09 PM PDT 23 9415977006 ps
T326 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.72813129069300254934465935871108538479594230258743780331214067966723769403351 Nov 01 02:45:04 PM PDT 23 Nov 01 02:45:36 PM PDT 23 6233818126 ps
T327 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.104329726916311309625154515575959910147083875650850276829694363771541462288625 Nov 01 02:44:40 PM PDT 23 Nov 01 02:44:55 PM PDT 23 3151732636 ps
T328 /workspace/coverage/default/12.rom_ctrl_smoke.24287675139471224378946952969225349024919280275547355400881496909922450275103 Nov 01 02:44:04 PM PDT 23 Nov 01 02:44:35 PM PDT 23 6265461576 ps
T329 /workspace/coverage/default/10.rom_ctrl_alert_test.110085552223563964637852991391324883826566363854487483565266235723278723186405 Nov 01 02:43:59 PM PDT 23 Nov 01 02:44:12 PM PDT 23 3124113076 ps
T330 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.71502316053159528653977723501730352683624643286972673304580144567471843547927 Nov 01 02:44:22 PM PDT 23 Nov 01 02:44:48 PM PDT 23 6233818126 ps
T331 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.100461663017083911425971554673210345571547932273440056291208654548679306280849 Nov 01 02:44:31 PM PDT 23 Nov 01 02:44:59 PM PDT 23 6233818126 ps
T332 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.77105824260461542611017585036510585282611594324255526096452000098528597902331 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3151732636 ps
T333 /workspace/coverage/default/46.rom_ctrl_alert_test.18284564491354607319867825187015814934293764228110843807899285327839422466905 Nov 01 02:45:04 PM PDT 23 Nov 01 02:45:21 PM PDT 23 3124113076 ps
T334 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.79164723655229908649949114716533470724561479176122571051589343813787072871263 Nov 01 02:44:29 PM PDT 23 Nov 01 02:44:59 PM PDT 23 6233818126 ps
T335 /workspace/coverage/default/45.rom_ctrl_alert_test.114542344532918758313704600365718931489436187035719364144227740185754049419722 Nov 01 02:45:20 PM PDT 23 Nov 01 02:45:34 PM PDT 23 3124113076 ps
T336 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.85370790905627452168842238059310999259966178997736565611103494316271883524187 Nov 01 02:44:19 PM PDT 23 Nov 01 02:44:34 PM PDT 23 3151732636 ps
T337 /workspace/coverage/default/8.rom_ctrl_smoke.18931409539191219638946429259403298570841084867437402054939438650558830670200 Nov 01 02:44:09 PM PDT 23 Nov 01 02:44:41 PM PDT 23 6265461576 ps
T338 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.20595372219573062493956022769285045970834313856124598182815343415819743788291 Nov 01 02:44:25 PM PDT 23 Nov 01 02:50:03 PM PDT 23 69854280986 ps
T339 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.75647141616806247854628415037722380660876186394550641506872665097969076136913 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:42 PM PDT 23 6233818126 ps
T340 /workspace/coverage/default/20.rom_ctrl_alert_test.77516559375849901929740562222846668153849771264543234999370933191870765398196 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:16 PM PDT 23 3124113076 ps
T341 /workspace/coverage/default/5.rom_ctrl_smoke.29229585861579370164501036635469253428927178506870885841122553370139399712207 Nov 01 02:44:04 PM PDT 23 Nov 01 02:44:37 PM PDT 23 6265461576 ps
T342 /workspace/coverage/default/6.rom_ctrl_smoke.92531857258963773647641675329073884194863622959033437523325392209862226587679 Nov 01 02:44:04 PM PDT 23 Nov 01 02:44:36 PM PDT 23 6265461576 ps
T343 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.47262213085731787954059806437626283731165178224038497246771097927732431341181 Nov 01 02:44:25 PM PDT 23 Nov 01 02:44:52 PM PDT 23 6233818126 ps
T344 /workspace/coverage/default/41.rom_ctrl_smoke.22030736003638157736303513274609311712914624369475850757959990181462892464153 Nov 01 02:44:30 PM PDT 23 Nov 01 02:45:02 PM PDT 23 6265461576 ps
T345 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.28786100043663037110016291759902076550173554489773554441210256095942066838104 Nov 01 02:44:00 PM PDT 23 Nov 01 02:44:15 PM PDT 23 3151732636 ps
T346 /workspace/coverage/default/33.rom_ctrl_alert_test.96319045606279295258736930715263932823473806273998614093578269631542928917218 Nov 01 02:44:53 PM PDT 23 Nov 01 02:45:08 PM PDT 23 3124113076 ps
T347 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.72095154983095458724314194737977861671272603161509541654453629179798083128507 Nov 01 02:44:25 PM PDT 23 Nov 01 02:44:39 PM PDT 23 3151732636 ps
T348 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.108810996956932621908543477285115261566944549260424146272546276542541502347193 Nov 01 02:44:30 PM PDT 23 Nov 01 02:44:59 PM PDT 23 6233818126 ps
T349 /workspace/coverage/default/10.rom_ctrl_stress_all.30818997941044461313223228242154839800684730776178845194168797294779972943311 Nov 01 02:43:26 PM PDT 23 Nov 01 02:44:10 PM PDT 23 9415977006 ps
T350 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1819694916560135435612751951447969868997118717422882024504445788888706784902 Nov 01 02:44:04 PM PDT 23 Nov 01 02:44:20 PM PDT 23 3151732636 ps
T351 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.23037595165864250010220378718072329195192658673965296446862073140356017410273 Nov 01 02:43:25 PM PDT 23 Nov 01 02:49:06 PM PDT 23 69854280986 ps
T352 /workspace/coverage/default/37.rom_ctrl_alert_test.70002208892850467051669503100060126296299161141122975566334079705627652276830 Nov 01 02:44:26 PM PDT 23 Nov 01 02:44:39 PM PDT 23 3124113076 ps
T353 /workspace/coverage/default/9.rom_ctrl_smoke.12188906441310597406142902399216123340867527969509217726467373375819418522711 Nov 01 02:43:53 PM PDT 23 Nov 01 02:44:22 PM PDT 23 6265461576 ps
T354 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.8401324667225705704191512053584209053739074442166575906489745283022146769203 Nov 01 02:44:03 PM PDT 23 Nov 01 02:49:50 PM PDT 23 69854280986 ps
T355 /workspace/coverage/default/0.rom_ctrl_smoke.103998292331800016988822040071346872200772040531274220148974159381945755844122 Nov 01 02:43:53 PM PDT 23 Nov 01 02:44:22 PM PDT 23 6265461576 ps
T356 /workspace/coverage/default/5.rom_ctrl_stress_all.72398967831591768787563029685925496026106968041143429450302736828948225362523 Nov 01 02:44:01 PM PDT 23 Nov 01 02:44:46 PM PDT 23 9415977006 ps
T357 /workspace/coverage/default/35.rom_ctrl_stress_all.114919682065143360533123802416015304376825301115014665939572283183842244946946 Nov 01 02:44:19 PM PDT 23 Nov 01 02:45:03 PM PDT 23 9415977006 ps
T358 /workspace/coverage/default/25.rom_ctrl_stress_all.23706429434351453300920564940382683367257470211734527538853374067225789624417 Nov 01 02:44:17 PM PDT 23 Nov 01 02:45:01 PM PDT 23 9415977006 ps
T359 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.57873562520193599265346365322629850917762241014040405708627433318207154919663 Nov 01 02:44:08 PM PDT 23 Nov 01 02:44:25 PM PDT 23 3151732636 ps
T360 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.46746174878338314344144222722682620648639567149003021026630924638844595244269 Nov 01 02:44:05 PM PDT 23 Nov 01 02:49:50 PM PDT 23 69854280986 ps
T361 /workspace/coverage/default/4.rom_ctrl_alert_test.85777572411346836303612299301515130796479111224927964386659623173193313508237 Nov 01 02:44:03 PM PDT 23 Nov 01 02:44:19 PM PDT 23 3124113076 ps
T362 /workspace/coverage/default/30.rom_ctrl_alert_test.27294888962563515065086422177120362701695205302410021336914181943552600937959 Nov 01 02:44:25 PM PDT 23 Nov 01 02:44:39 PM PDT 23 3124113076 ps
T363 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.113640642979266834985345431531427779649297534353752367232383496965029875553081 Nov 01 02:45:44 PM PDT 23 Nov 01 02:45:59 PM PDT 23 3142303916 ps
T364 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.18817878756523990551395128656463157089186824435911582690880421463004868703416 Nov 01 02:45:43 PM PDT 23 Nov 01 02:45:57 PM PDT 23 3124113076 ps
T365 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.86298553249835049335263496661331014482025577739653438543052543750824137404469 Nov 01 02:45:20 PM PDT 23 Nov 01 02:45:34 PM PDT 23 3124113076 ps
T366 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3701849486665999946279275651402649475053508124504613147609653229364806461097 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3135422826 ps
T367 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.85638006728989641060518717514491822079710099257653156749069621912913487788813 Nov 01 02:45:18 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3124113076 ps
T74 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.32452850888251959898516933350916692239876358962714293349985049128471158396502 Nov 01 02:45:05 PM PDT 23 Nov 01 02:49:53 PM PDT 23 65914678386 ps
T368 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.39291867846937006217033955115475265136861583293196426796176755128159729501116 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3135422826 ps
T87 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.113183218775121148911983682375883971579768192305897692503639520762261598594329 Nov 01 02:45:20 PM PDT 23 Nov 01 02:45:33 PM PDT 23 3124113076 ps
T369 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.30424586328173104230870129420135440812648745461744698291069597075022324855403 Nov 01 02:45:41 PM PDT 23 Nov 01 02:47:02 PM PDT 23 3476453456 ps
T75 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.27835452819599541747630726988254182216189428636622539634402239211475858349204 Nov 01 02:45:37 PM PDT 23 Nov 01 02:50:19 PM PDT 23 65914678386 ps
T370 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.25132406085136698675926581009389631062683844645479303829766729062007676605698 Nov 01 02:45:16 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3124113076 ps
T371 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.67595216658747131969189935688764782799906452802154804258250927992457677872092 Nov 01 02:45:42 PM PDT 23 Nov 01 02:47:04 PM PDT 23 3476453456 ps
T372 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.110700208443488000345696976267207001824544937741116119513700581233094409561907 Nov 01 02:45:06 PM PDT 23 Nov 01 02:46:34 PM PDT 23 3476453456 ps
T373 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.102220494233325257053491621929602514085497695471491429045173221471704785534091 Nov 01 02:45:18 PM PDT 23 Nov 01 02:45:33 PM PDT 23 3124113076 ps
T374 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.29338675132018360169595660787215250209141921709837987072996075756882821233741 Nov 01 02:45:39 PM PDT 23 Nov 01 02:45:53 PM PDT 23 3124113076 ps
T375 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.108360376808454282864809274484059861071072907476170083830087251139240628164811 Nov 01 02:45:41 PM PDT 23 Nov 01 02:47:03 PM PDT 23 3476453456 ps
T376 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.54314322646933043614273084616890000244024535642873274373347749528031446547788 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3124113076 ps
T377 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.85764133347067998124122821665163383549145510703477552525827432290981311420534 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3124113076 ps
T378 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.27742178268768923933294621864803399817599894277600256347440752099154985500553 Nov 01 02:45:43 PM PDT 23 Nov 01 02:47:06 PM PDT 23 3476453456 ps
T69 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.58264542138523125252754217971102344549371982187463478870777268409338194462875 Nov 01 02:45:39 PM PDT 23 Nov 01 02:45:56 PM PDT 23 3124113076 ps
T379 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.56636168722861759129254733225210437951353890437929119278675874018331633561777 Nov 01 02:45:22 PM PDT 23 Nov 01 02:45:38 PM PDT 23 3142303916 ps
T380 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.47996796401483396299617654846318204375278189521451002717298275759258815362323 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:55 PM PDT 23 3142303916 ps
T381 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.103733885836204022262763814838887492954624215762916826019355245465200971126609 Nov 01 02:45:18 PM PDT 23 Nov 01 02:46:41 PM PDT 23 3476453456 ps
T382 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.30500218747885048547902015783578001514674475056451395385813346557308082191156 Nov 01 02:45:19 PM PDT 23 Nov 01 02:45:36 PM PDT 23 3138518126 ps
T383 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.30903403612597271159413821330394220124069613075154129784830069124009390313966 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:53 PM PDT 23 3124113076 ps
T384 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.55782973021276061682163069283775498747709703184321575942158044542707228943704 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3124113076 ps
T385 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.26329655286914779338907318245536388392244530626397585274819226352569867179978 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3124113076 ps
T386 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.53467605513803333671712979628487640088566111841166770058696206143860059940878 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:35 PM PDT 23 3138518126 ps
T387 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.64402859696796713685425386700638732921082350261729862995718735212857517578340 Nov 01 02:45:54 PM PDT 23 Nov 01 02:46:09 PM PDT 23 3142303916 ps
T76 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.83483572745294168686803534342248401362921034314060649523103821309303040179951 Nov 01 02:45:39 PM PDT 23 Nov 01 02:50:32 PM PDT 23 65914678386 ps
T388 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.82709977561231077599321987875249275807598012884317659463583673133515125988495 Nov 01 02:45:18 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3124113076 ps
T389 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.92913238950324495127198408978496332178458013281356530950842632873149717389075 Nov 01 02:45:22 PM PDT 23 Nov 01 02:46:45 PM PDT 23 3476453456 ps
T390 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.86304052924465255002536133899509357439161758719197416130752388572580440744248 Nov 01 02:45:04 PM PDT 23 Nov 01 02:45:21 PM PDT 23 3124113076 ps
T391 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.66827399531771138710512862967947890297404025226716152556521664952015923450936 Nov 01 02:45:22 PM PDT 23 Nov 01 02:50:10 PM PDT 23 65914678386 ps
T392 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.98879551090595749041178191150393424232394888600337609637580305216167128855907 Nov 01 02:45:43 PM PDT 23 Nov 01 02:45:56 PM PDT 23 3124113076 ps
T393 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.19422404549092564561570622475366139570804760185949788309368681145128385587984 Nov 01 02:45:14 PM PDT 23 Nov 01 02:50:02 PM PDT 23 65914678386 ps
T394 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.87970461305232891204429067659874910128659755401329028927829152497656032754587 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3142303916 ps
T395 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.28934034356943312315565930557421832031756615162055933028007779653958258809201 Nov 01 02:45:17 PM PDT 23 Nov 01 02:46:38 PM PDT 23 3476453456 ps
T396 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.21918453253491568615808223149624593105679526928388607007675955418777799740245 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3124113076 ps
T397 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.92229197310189434506822514398182994757710056909015496438144530917187001358245 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3135422826 ps
T70 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.111315060850450136975482481936344105020084312599937588157562637904111488473034 Nov 01 02:45:43 PM PDT 23 Nov 01 02:46:01 PM PDT 23 3124113076 ps
T398 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.54013529360248477327780989520020086584972276874189421690699573475286953956257 Nov 01 02:45:24 PM PDT 23 Nov 01 02:45:37 PM PDT 23 3135422826 ps
T399 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.94437263684378314065239804360541676755190697999790332944047983067503646069806 Nov 01 02:45:42 PM PDT 23 Nov 01 02:45:56 PM PDT 23 3135422826 ps
T400 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.100586735283959211515985432358941745584991757100196617111933846934761268554702 Nov 01 02:45:25 PM PDT 23 Nov 01 02:46:47 PM PDT 23 3476453456 ps
T401 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.29522361355272681191648678951406462433578424757752289050982019176467019330946 Nov 01 02:45:41 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3124113076 ps
T89 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.95031648908237966132365694811660197444826080458916725676844669950089324234405 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3124113076 ps
T402 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.26119102682742286183337932523701908386971670693357970419559793924400300763956 Nov 01 02:45:22 PM PDT 23 Nov 01 02:45:40 PM PDT 23 3124113076 ps
T403 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.16140393563855621190256944718537380764836998987816318850370386938713324912753 Nov 01 02:45:20 PM PDT 23 Nov 01 02:45:33 PM PDT 23 3124113076 ps
T404 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.70466438374975648340970519330854146061432314469292784394738756896229908370267 Nov 01 02:45:40 PM PDT 23 Nov 01 02:47:04 PM PDT 23 3476453456 ps
T405 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.102795913847217983959779125275883453869722530161962397667769790631241235989256 Nov 01 02:45:19 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3124113076 ps
T406 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.42650343941465103392824344123675742791360410295974877753819662998615401359480 Nov 01 02:45:04 PM PDT 23 Nov 01 02:45:25 PM PDT 23 3138518126 ps
T407 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2309246537150925394283305256837576878182403530415553476639790814568702575111 Nov 01 02:45:42 PM PDT 23 Nov 01 02:46:00 PM PDT 23 3124113076 ps
T408 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.91175983580613122981017573963915473550759580534540753217745270200402372896306 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:35 PM PDT 23 3124113076 ps
T409 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.67072451907975680993766544568591656609672521990529499434309336938334144780265 Nov 01 02:45:39 PM PDT 23 Nov 01 02:50:28 PM PDT 23 65914678386 ps
T410 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.10660469061710632816185029420143302588846806745067318141992678262282538788844 Nov 01 02:45:41 PM PDT 23 Nov 01 02:50:31 PM PDT 23 65914678386 ps
T411 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.8233801163154242478890172671040940224513401537909837660232189799703870053999 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3124113076 ps
T412 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.94836578604211600423464713232265602838560784193766288685127894386605461058510 Nov 01 02:45:21 PM PDT 23 Nov 01 02:45:39 PM PDT 23 3124113076 ps
T413 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.26329241524458827069477949707385590768924023599609416446972780502771790354328 Nov 01 02:45:18 PM PDT 23 Nov 01 02:45:35 PM PDT 23 3142303916 ps
T414 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.97298927418108197113570960514475474672197005586627578118945356592074432813032 Nov 01 02:45:16 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3135422826 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.47592567224045587673642080800138047418220557345516404914782237972367346435276 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:35 PM PDT 23 3124113076 ps
T416 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.92396888892276826505955356656097974140006139914329481569690683736311119920340 Nov 01 02:45:16 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3124113076 ps
T417 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.61611199449313028709822559179727570511009980012348602982707354826905178970512 Nov 01 02:45:13 PM PDT 23 Nov 01 02:45:28 PM PDT 23 3142303916 ps
T418 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.58726062909804126423298387772290180434817341003187506396746262546361548892466 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:58 PM PDT 23 3124113076 ps
T419 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.51934066352610064529310663212582230193909199273562138359537703098801547115149 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3124113076 ps
T420 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.98592412991551728236731971373495038599122440875147705189658164833314043084225 Nov 01 02:45:21 PM PDT 23 Nov 01 02:45:35 PM PDT 23 3124113076 ps
T421 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.50834242630904760438843899165880650250543659912496135295813029765599368034517 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:34 PM PDT 23 3124113076 ps
T422 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.63165925316227747197386657477778757936136748069013258438246359200325118983557 Nov 01 02:45:17 PM PDT 23 Nov 01 02:45:31 PM PDT 23 3135422826 ps
T423 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.69438159241447253860104670495213431138152424033719710814690513498249519469758 Nov 01 02:45:41 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3135422826 ps
T424 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.81099569696483442789149029260436107983796760294021664532864550874617458009101 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3142303916 ps
T425 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.94515817195496354813873768616466338069199764020977629820753433803463226175856 Nov 01 02:45:39 PM PDT 23 Nov 01 02:50:26 PM PDT 23 65914678386 ps
T426 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.84910500029223368493637609846112198077728618216528389342998768259614505997984 Nov 01 02:45:16 PM PDT 23 Nov 01 02:50:09 PM PDT 23 65914678386 ps
T427 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.43277515217077275327874480828747182298118696891272135091916894785601265460463 Nov 01 02:45:42 PM PDT 23 Nov 01 02:45:55 PM PDT 23 3124113076 ps
T428 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.88410438101730290150516346870073794441676097377103394116396748817587152877856 Nov 01 02:45:15 PM PDT 23 Nov 01 02:50:01 PM PDT 23 65914678386 ps
T429 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.34638888573074184005295829764925391305720868325488324306803886997266633763163 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3135422826 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.33569995624494190018748970588782264625663869060666611393659063410027358974003 Nov 01 02:45:25 PM PDT 23 Nov 01 02:45:38 PM PDT 23 3135422826 ps
T431 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.41443293737171536774001406538632672202734655939550361509758498665380060879495 Nov 01 02:45:15 PM PDT 23 Nov 01 02:50:04 PM PDT 23 65914678386 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.101408497199691334736963264913107184290587340354190636126998960418564435117549 Nov 01 02:45:21 PM PDT 23 Nov 01 02:50:06 PM PDT 23 65914678386 ps
T433 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.49137872153111746581956488181351801813940066272208199263830376544128608804400 Nov 01 02:45:40 PM PDT 23 Nov 01 02:45:54 PM PDT 23 3135422826 ps
T434 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.98479593378018244216864819571060951773198304239624483778926364566514648049885 Nov 01 02:45:22 PM PDT 23 Nov 01 02:45:40 PM PDT 23 3124113076 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.114810934336126630277930415888868580579921659018188998931714275824873867766093 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:32 PM PDT 23 3138518126 ps
T436 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.100886771293450263681394523065237421237268757615053075094750859591659032136433 Nov 01 02:45:42 PM PDT 23 Nov 01 02:47:04 PM PDT 23 3476453456 ps
T437 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.48469486254961473853856824145678206913135238519816636130391729392974142067707 Nov 01 02:45:41 PM PDT 23 Nov 01 02:47:03 PM PDT 23 3476453456 ps
T438 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.87206476352428333664830913516532998092007152042319107472697919869760062971824 Nov 01 02:45:22 PM PDT 23 Nov 01 02:45:38 PM PDT 23 3142303916 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.32378841835940201953995719920528439540496541147079438724909269935818362577718 Nov 01 02:45:06 PM PDT 23 Nov 01 02:45:28 PM PDT 23 3124113076 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.84014334592753358027831370296049031372027530049484734127038218020798899231791 Nov 01 02:45:04 PM PDT 23 Nov 01 02:46:31 PM PDT 23 3476453456 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.56492549815137628372554455296732766855354010218375499538935137177331590449582 Nov 01 02:45:24 PM PDT 23 Nov 01 02:45:41 PM PDT 23 3124113076 ps
T442 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.102885986762709235314921834692622484911792167814268535186862254498753153574606 Nov 01 02:45:43 PM PDT 23 Nov 01 02:45:56 PM PDT 23 3124113076 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.33513228866284443115529902035902154797195528889683137359405408725405165675143 Nov 01 02:45:24 PM PDT 23 Nov 01 02:45:37 PM PDT 23 3135422826 ps
T444 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.88570323061444825189820240925938267017884380885930345026061016702512244199333 Nov 01 02:45:21 PM PDT 23 Nov 01 02:46:44 PM PDT 23 3476453456 ps
T445 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.86165118299453949365033565369518782626682602615508207938028489130989324999019 Nov 01 02:45:05 PM PDT 23 Nov 01 02:45:24 PM PDT 23 3124113076 ps
T446 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.31235241294564232160533243305190757269564112132540954357505881296592801407591 Nov 01 02:45:44 PM PDT 23 Nov 01 02:45:59 PM PDT 23 3142303916 ps
T447 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.73055440226640047738719577938750346336421825608632601397844875347397471076420 Nov 01 02:45:15 PM PDT 23 Nov 01 02:45:30 PM PDT 23 3135422826 ps
T448 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.66423219786380580268690026085722360678687036350062153110711832897363283640303 Nov 01 02:45:39 PM PDT 23 Nov 01 02:50:23 PM PDT 23 65914678386 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.59576375029268380096189457387965255284320954517982783767735241970057252928007 Nov 01 02:45:14 PM PDT 23 Nov 01 02:45:28 PM PDT 23 3124113076 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.47868904273722472153812939082684191974798362218760696181447324048207154434452 Nov 01 02:45:20 PM PDT 23 Nov 01 02:45:34 PM PDT 23 3124113076 ps

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.24166454369778460815441819386255431162705984750006328584529702210525006225651
Short name T16
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.79 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:39 PM PDT 23
Peak memory 210896 kb
Host smart-66b5f0de-2f61-45bb-af9b-972327bbaeb5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24166454369778460815441819386255431162705984750006328584529702210525006225651 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_reset.24166454369778460815441819386255431162705984750006328584529702210525006225651
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.112343289043687450553390846594092348200354398295144146360285537975688454027219
Short name T5
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.16 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:49:54 PM PDT 23
Peak memory 237748 kb
Host smart-4ce617fc-1e83-4c81-8e66-6b8b3f5bd5c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112343289043687450553390846594092348200354398295144146360285537975688454027219 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_corrupt_sig_fatal_chk.11234328904368745055339084659409234820035439829514414636
0285537975688454027219
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.19341196784619537623818953403822576991954881045221231825047740490793968607956
Short name T20
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.03 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 219104 kb
Host smart-12051f45-97f1-4bc0-9f4d-12847b4102e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19341196784619537623818953403822576991954881045221231825047740490793968607956 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.19341196784619537623818953403822576991954881045221231825047740490793968607956
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.59491886498656693617244004950686863629188996537274577716810357652596733689244
Short name T21
Test name
Test status
Simulation time 3476453456 ps
CPU time 83.69 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:47:06 PM PDT 23
Peak memory 211084 kb
Host smart-6f4cab8b-750a-47cd-944c-ad2484a9a706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59491886498656693617244004950686863629188996537274577716810357652596733689244 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_intg_err.59491886498656693617244004950686863629188996537274577716810357652596733689244
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.12117621930378655377346811858572833300455003335497952387239191181972466080366
Short name T3
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.3 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 212792 kb
Host smart-2a5acfac-c641-44b3-9ac3-714a8bdbc108
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121176219303786553773468118585728333004550033354979523872391911
81972466080366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all.12117621930378655377346811858572833300455003335497
952387239191181972466080366
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.78921803824174660937048263709240258068408170134499616496409611396907923111614
Short name T24
Test name
Test status
Simulation time 65914678386 ps
CPU time 284.89 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:49:59 PM PDT 23
Peak memory 218916 kb
Host smart-78819c70-ce5d-43b4-aafa-a8e7548cc50c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78921803824174660937048263709240258068408170134499616496409611396907923111614 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_passthru_mem_tl_intg_err.78921803824174660937048263709240258068408170134499616496
409611396907923111614
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.30903403612597271159413821330394220124069613075154129784830069124009390313966
Short name T383
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:53 PM PDT 23
Peak memory 210940 kb
Host smart-b9bb4370-6fcb-4a4f-9fd9-16c3df758dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30903403612597271159413821330394220124069613075154129784830069124009390313966 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.30903403612597271159413821330394220124069613075154129784830069124009390313966
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.95778758854887871130838838349023527172374492092006135077719576635133806622056
Short name T34
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.4 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:46:05 PM PDT 23
Peak memory 236820 kb
Host smart-242b35aa-8137-4cc1-a170-48ae834c6e77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95778758854887871130838838349023527172374492092006135077719576635133806622056 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.95778758854887871130838838349023527172374492092006135077719576635133806622056
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.53498417692876380287763426468073596707939691860556826271504745363015272744818
Short name T79
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 209828 kb
Host smart-4517b7af-0a0b-4b38-ab0d-329a1faf7393
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53498417692876380287763426468073596707939691860556826271504745363015272744818 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_bash.53498417692876380287763426468073596707939691860556826271504745363015272744818
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.102068231113681113333894555091675705406621285954770775479689398166145029560011
Short name T81
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.86 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:29 PM PDT 23
Peak memory 210892 kb
Host smart-0c54dc09-cef2-4c1a-8fdc-bf9614b18980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102068231113681113333894555091675705406621285954770775479689398166145029560011
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_same_csr_outstanding.10206823111368111333389455509167570540662128595477077
5479689398166145029560011
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.82245727995366215972993686649944913981070002941576417944183998233971501446796
Short name T57
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.23 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:52 PM PDT 23
Peak memory 213300 kb
Host smart-194b22b4-d985-4b02-ae74-22a15d4f1207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8224572799536621597299368664994491398107000
2941576417944183998233971501446796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.822457279953
66215972993686649944913981070002941576417944183998233971501446796
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.14599711781660553114801961756206353852117682054544623535319736653130226413740
Short name T13
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.26 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:37 PM PDT 23
Peak memory 211612 kb
Host smart-ad189891-3567-4443-b2f2-13d28a8e8422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14599711781660553114801961756206353852117682054544623535319736653130226413740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.rom_ctrl_kmac_err_chk.14599711781660553114801961756206353852117682054544623535319736653130226413740
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.95031648908237966132365694811660197444826080458916725676844669950089324234405
Short name T89
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210960 kb
Host smart-ff4941c0-5796-4d05-bf59-daf6000ed48c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95031648908237966132365694811660197444826080458916725676844669950089324234405 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_aliasing.95031648908237966132365694811660197444826080458916725676844669950089324234405
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.94637499570007045647886875132669331868250656479265661781763850042082998937382
Short name T53
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:44:07 PM PDT 23
Peak memory 211176 kb
Host smart-8dd781e6-b07d-4034-9c3f-8385d527cd03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94637499570007045647886875132669331868250656479265661781763850042082998937382 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.94637499570007045647886875132669331868250656479265661781763850042082998937382
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.83112151309140459148014790470078981832527554824280390947500083464932916305227
Short name T102
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211180 kb
Host smart-3aec9e09-0456-4427-a0d3-a9f1b555cd35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83112151309140459148014790470078981832527554824280390947500083464932916305227 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.83112151309140459148014790470078981832527554824280390947500083464932916305227
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.81512997179198230239564878223739271701212020096014197729402177072298131412847
Short name T85
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:32 PM PDT 23
Peak memory 212868 kb
Host smart-887767e5-1805-4ee7-996d-c8d3540d8597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81512997179198230239564878223739271701212020096014197729402177072298131412847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.rom_ctrl_smoke.81512997179198230239564878223739271701212020096014197729402177072298131412847
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.114810934336126630277930415888868580579921659018188998931714275824873867766093
Short name T435
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.64 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210820 kb
Host smart-d5661dba-b851-4507-9a05-e658d3ceb862
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114810934336126630277930415888868580579921659018188998931714275824873867766093 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_reset.114810934336126630277930415888868580579921659018188998931714275824873867766093
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.97298927418108197113570960514475474672197005586627578118945356592074432813032
Short name T414
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.27 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 213524 kb
Host smart-cdf53b0c-e1af-4cb6-af91-accc81a21403
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9729892741810819711357096051447547467219700
5586627578118945356592074432813032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.9729892741810
8197113570960514475474672197005586627578118945356592074432813032
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.59576375029268380096189457387965255284320954517982783767735241970057252928007
Short name T449
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:28 PM PDT 23
Peak memory 210888 kb
Host smart-c03a2d42-7b30-4bec-96cd-53f3f68c0120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59576375029268380096189457387965255284320954517982783767735241970057252928007 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.59576375029268380096189457387965255284320954517982783767735241970057252928007
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.55782973021276061682163069283775498747709703184321575942158044542707228943704
Short name T384
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 210876 kb
Host smart-843caf0f-3338-4bf0-8f11-24d0c27eda8e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55782973021276061682163069283775498747709703184321575942158044542707228943704 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_partial_access.5578297302127606168216306928377549874770970318432157594215
8044542707228943704
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.85764133347067998124122821665163383549145510703477552525827432290981311420534
Short name T377
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.09 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 210764 kb
Host smart-834217bf-e981-4d39-970f-cd6fc9d7c0a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85764133347067998124122821665163383549145510703477552525827432290981311420534 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.85764133347067998124122821665163383549145510703477552525827432290981311420534
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.50834242630904760438843899165880650250543659912496135295813029765599368034517
Short name T421
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.52 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 219064 kb
Host smart-828b3b39-12f5-4ff0-9c05-4f38f80613c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50834242630904760438843899165880650250543659912496135295813029765599368034517 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.50834242630904760438843899165880650250543659912496135295813029765599368034517
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.110700208443488000345696976267207001824544937741116119513700581233094409561907
Short name T372
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.02 seconds
Started Nov 01 02:45:06 PM PDT 23
Finished Nov 01 02:46:34 PM PDT 23
Peak memory 211104 kb
Host smart-aa7786ea-49da-4c37-b446-592726c48151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110700208443488000345696976267207001824544937741116119513700581233094409561907 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_intg_err.110700208443488000345696976267207001824544937741116119513700581233094409561907
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.102795913847217983959779125275883453869722530161962397667769790631241235989256
Short name T405
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Nov 01 02:45:19 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210952 kb
Host smart-0d9206a6-657f-4911-a2d3-40b83479b996
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102795913847217983959779125275883453869722530161962397667769790631241235989256 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_aliasing.102795913847217983959779125275883453869722530161962397667769790631241235989256
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.102220494233325257053491621929602514085497695471491429045173221471704785534091
Short name T373
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:45:33 PM PDT 23
Peak memory 210860 kb
Host smart-b2427d9a-1d1f-4e32-a308-cdcf816ed8ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102220494233325257053491621929602514085497695471491429045173221471704785534091 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_bash.102220494233325257053491621929602514085497695471491429045173221471704785534091
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.53467605513803333671712979628487640088566111841166770058696206143860059940878
Short name T386
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.8 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 210884 kb
Host smart-16ef3bae-ecec-41dc-87a0-04b363ffdd91
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53467605513803333671712979628487640088566111841166770058696206143860059940878 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_reset.53467605513803333671712979628487640088566111841166770058696206143860059940878
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.63165925316227747197386657477778757936136748069013258438246359200325118983557
Short name T422
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.21 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 213404 kb
Host smart-412c788f-d9bf-46b6-924d-d29d128f6960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6316592531622774719738665747777875793613674
8069013258438246359200325118983557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.6316592531622
7747197386657477778757936136748069013258438246359200325118983557
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.98592412991551728236731971373495038599122440875147705189658164833314043084225
Short name T420
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.17 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 210884 kb
Host smart-7f9cd50e-aa6f-4ad3-9c97-1c32e8ff09e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98592412991551728236731971373495038599122440875147705189658164833314043084225 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.98592412991551728236731971373495038599122440875147705189658164833314043084225
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.66131845117498008514231827764662545420480853175648424066912986246312281192288
Short name T91
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.98 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 210816 kb
Host smart-3779f7bc-f83f-46d5-8cc0-c1168d3a82a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66131845117498008514231827764662545420480853175648424066912986246312281192288 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_partial_access.6613184511749800851423182776466254542048085317564842406691
2986246312281192288
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.8233801163154242478890172671040940224513401537909837660232189799703870053999
Short name T411
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210860 kb
Host smart-9b2477f6-9d98-438d-8283-872ac9afcc22
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8233801163154242478890172671040940224513401537909837660232189799703870053999 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.8233801163154242478890172671040940224513401537909837660232189799703870053999
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.19422404549092564561570622475366139570804760185949788309368681145128385587984
Short name T393
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.41 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:50:02 PM PDT 23
Peak memory 219076 kb
Host smart-f8e690af-c22e-4ee1-ae0f-0f8804fc6355
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19422404549092564561570622475366139570804760185949788309368681145128385587984 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_passthru_mem_tl_intg_err.19422404549092564561570622475366139570804760185949788309
368681145128385587984
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.67892956190855290451130440910470077985933167391897144233839271058808647940546
Short name T22
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.25 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:33 PM PDT 23
Peak memory 210788 kb
Host smart-eec5ae46-089b-484b-84bc-3f22633f4799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67892956190855290451130440910470077985933167391897144233839271058808647940546
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_same_csr_outstanding.678929561908552904511304409104700779859331673918971442
33839271058808647940546
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.47592567224045587673642080800138047418220557345516404914782237972367346435276
Short name T415
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.17 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 219056 kb
Host smart-09cd8949-d1fa-414e-8cf2-56bdec180ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47592567224045587673642080800138047418220557345516404914782237972367346435276 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.47592567224045587673642080800138047418220557345516404914782237972367346435276
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.105753767383454261031379192507240064264411658379906254712376121762396650102255
Short name T61
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.51 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:46:40 PM PDT 23
Peak memory 211044 kb
Host smart-ef5af477-432e-4e6f-8e45-bbfb232a9232
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105753767383454261031379192507240064264411658379906254712376121762396650102255 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_intg_err.105753767383454261031379192507240064264411658379906254712376121762396650102255
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.54013529360248477327780989520020086584972276874189421690699573475286953956257
Short name T398
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.53 seconds
Started Nov 01 02:45:24 PM PDT 23
Finished Nov 01 02:45:37 PM PDT 23
Peak memory 213416 kb
Host smart-1d3bc5c2-ef23-477a-bf7e-370dceed6b2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5401352936024847732778098952002008658497227
6874189421690699573475286953956257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.540135293602
48477327780989520020086584972276874189421690699573475286953956257
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.79646278045836138190929870272290733406274508184080622095681918744738541260829
Short name T71
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Nov 01 02:45:25 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 210872 kb
Host smart-5c1fee79-2957-42b3-b20c-ebfaef9cc706
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79646278045836138190929870272290733406274508184080622095681918744738541260829 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.79646278045836138190929870272290733406274508184080622095681918744738541260829
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.66827399531771138710512862967947890297404025226716152556521664952015923450936
Short name T391
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.4 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:50:10 PM PDT 23
Peak memory 219004 kb
Host smart-0205e367-5889-4ce2-ad50-52b8b25df19c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66827399531771138710512862967947890297404025226716152556521664952015923450936 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_passthru_mem_tl_intg_err.6682739953177113871051286296794789029740402522671615255
6521664952015923450936
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.59959866706134752633988533742368097307413214823817419734891269927015740876585
Short name T78
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.35 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 210892 kb
Host smart-8243dd54-ed23-4013-a546-1eaa3c9d3a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59959866706134752633988533742368097307413214823817419734891269927015740876585
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_same_csr_outstanding.59959866706134752633988533742368097307413214823817419
734891269927015740876585
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.56492549815137628372554455296732766855354010218375499538935137177331590449582
Short name T441
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.31 seconds
Started Nov 01 02:45:24 PM PDT 23
Finished Nov 01 02:45:41 PM PDT 23
Peak memory 219104 kb
Host smart-62435607-1152-420f-81e8-8b4b563458cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56492549815137628372554455296732766855354010218375499538935137177331590449582 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.56492549815137628372554455296732766855354010218375499538935137177331590449582
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.92913238950324495127198408978496332178458013281356530950842632873149717389075
Short name T389
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.36 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:46:45 PM PDT 23
Peak memory 211096 kb
Host smart-50c4c2ca-f1ea-496f-a793-10a6ec2d9861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92913238950324495127198408978496332178458013281356530950842632873149717389075 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_intg_err.92913238950324495127198408978496332178458013281356530950842632873149717389075
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.49137872153111746581956488181351801813940066272208199263830376544128608804400
Short name T433
Test name
Test status
Simulation time 3135422826 ps
CPU time 11.96 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 213440 kb
Host smart-de718631-a3d9-4f5d-8def-23c8f8555346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4913787215311174658195648818135180181394006
6272208199263830376544128608804400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.491378721531
11746581956488181351801813940066272208199263830376544128608804400
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.98879551090595749041178191150393424232394888600337609637580305216167128855907
Short name T392
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.12 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:45:56 PM PDT 23
Peak memory 210832 kb
Host smart-56eef920-e2aa-4be2-9153-1ec48886da8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98879551090595749041178191150393424232394888600337609637580305216167128855907 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.98879551090595749041178191150393424232394888600337609637580305216167128855907
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.50091774412022081908201375491216080707287810796929820636450377159882106158115
Short name T17
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.82 seconds
Started Nov 01 02:45:24 PM PDT 23
Finished Nov 01 02:50:11 PM PDT 23
Peak memory 218924 kb
Host smart-ed44125c-ec37-4b30-9ebe-2f23e7215fe1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50091774412022081908201375491216080707287810796929820636450377159882106158115 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_passthru_mem_tl_intg_err.5009177441202208190820137549121608070728781079692982063
6450377159882106158115
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.69036318764957344136492650045033222651986693284732601401208243917025490609303
Short name T93
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.14 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 210884 kb
Host smart-7e3ae0dc-82e2-42a8-8310-677bacfbd1cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69036318764957344136492650045033222651986693284732601401208243917025490609303
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_same_csr_outstanding.69036318764957344136492650045033222651986693284732601
401208243917025490609303
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.53541531577396698415783295737521984131008848088173309872474645027208213405420
Short name T67
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.24 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 219080 kb
Host smart-a8f2b944-a96c-4b00-a82a-546fd819a8f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53541531577396698415783295737521984131008848088173309872474645027208213405420 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.53541531577396698415783295737521984131008848088173309872474645027208213405420
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.92229197310189434506822514398182994757710056909015496438144530917187001358245
Short name T397
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.43 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 213480 kb
Host smart-da9acf58-1822-41b8-ae52-d0b2a92bfa1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9222919731018943450682251439818299475771005
6909015496438144530917187001358245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.922291973101
89434506822514398182994757710056909015496438144530917187001358245
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.29522361355272681191648678951406462433578424757752289050982019176467019330946
Short name T401
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 210888 kb
Host smart-a560da3e-4c10-4515-966a-f167f2193b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522361355272681191648678951406462433578424757752289050982019176467019330946 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.29522361355272681191648678951406462433578424757752289050982019176467019330946
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.94515817195496354813873768616466338069199764020977629820753433803463226175856
Short name T425
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.74 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:50:26 PM PDT 23
Peak memory 219052 kb
Host smart-40cc652f-d6c4-410f-bf37-f4bf49657594
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94515817195496354813873768616466338069199764020977629820753433803463226175856 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_passthru_mem_tl_intg_err.9451581719549635481387376861646633806919976402097762982
0753433803463226175856
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.47996796401483396299617654846318204375278189521451002717298275759258815362323
Short name T380
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.1 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:55 PM PDT 23
Peak memory 210884 kb
Host smart-fee7edfb-3554-4d74-9adc-0016d3f1026e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47996796401483396299617654846318204375278189521451002717298275759258815362323
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_same_csr_outstanding.47996796401483396299617654846318204375278189521451002
717298275759258815362323
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.58264542138523125252754217971102344549371982187463478870777268409338194462875
Short name T69
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.95 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:56 PM PDT 23
Peak memory 219176 kb
Host smart-f71d6bc9-90ef-4730-9641-a35d23dea3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58264542138523125252754217971102344549371982187463478870777268409338194462875 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.58264542138523125252754217971102344549371982187463478870777268409338194462875
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.30424586328173104230870129420135440812648745461744698291069597075022324855403
Short name T369
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.06 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:47:02 PM PDT 23
Peak memory 210896 kb
Host smart-f7619877-6abd-4bcc-9938-c4b2b965efa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30424586328173104230870129420135440812648745461744698291069597075022324855403 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_intg_err.30424586328173104230870129420135440812648745461744698291069597075022324855403
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.39291867846937006217033955115475265136861583293196426796176755128159729501116
Short name T368
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.63 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 213476 kb
Host smart-99681acb-d592-4536-ae83-3c052daa2950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929186784693700621703395511547526513686158
3293196426796176755128159729501116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.392918678469
37006217033955115475265136861583293196426796176755128159729501116
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.43277515217077275327874480828747182298118696891272135091916894785601265460463
Short name T427
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.23 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:45:55 PM PDT 23
Peak memory 210884 kb
Host smart-6c665134-7179-4896-b90f-c6d2bbbaf2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43277515217077275327874480828747182298118696891272135091916894785601265460463 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.43277515217077275327874480828747182298118696891272135091916894785601265460463
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.67072451907975680993766544568591656609672521990529499434309336938334144780265
Short name T409
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.26 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:50:28 PM PDT 23
Peak memory 219020 kb
Host smart-fc8c6adc-c510-4e1f-ab38-76ece870255c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67072451907975680993766544568591656609672521990529499434309336938334144780265 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_passthru_mem_tl_intg_err.6707245190797568099376654456859165660967252199052949943
4309336938334144780265
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.39137298071567116586797181288508806334071583760226699836114996143395637724494
Short name T63
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.95 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:45:57 PM PDT 23
Peak memory 210944 kb
Host smart-382d6047-7a21-4bfe-b56f-5b96f86d6243
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39137298071567116586797181288508806334071583760226699836114996143395637724494
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_same_csr_outstanding.39137298071567116586797181288508806334071583760226699
836114996143395637724494
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.62949432819983588776342294605716815564738395945242689323677143576210843892480
Short name T31
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.18 seconds
Started Nov 01 02:45:46 PM PDT 23
Finished Nov 01 02:46:03 PM PDT 23
Peak memory 219104 kb
Host smart-4f831544-5345-4b59-ba77-ac9df419e58f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62949432819983588776342294605716815564738395945242689323677143576210843892480 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.62949432819983588776342294605716815564738395945242689323677143576210843892480
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.67595216658747131969189935688764782799906452802154804258250927992457677872092
Short name T371
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.2 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:47:04 PM PDT 23
Peak memory 211176 kb
Host smart-d0243373-5097-405c-b51c-172e4b3d82b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67595216658747131969189935688764782799906452802154804258250927992457677872092 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_intg_err.67595216658747131969189935688764782799906452802154804258250927992457677872092
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.94437263684378314065239804360541676755190697999790332944047983067503646069806
Short name T399
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.26 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:45:56 PM PDT 23
Peak memory 213276 kb
Host smart-0f5dbebf-b24e-49bc-bc55-9d6c55eb9131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9443726368437831406523980436054167675519069
7999790332944047983067503646069806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.944372636843
78314065239804360541676755190697999790332944047983067503646069806
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.26329655286914779338907318245536388392244530626397585274819226352569867179978
Short name T385
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.39 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 210852 kb
Host smart-553d394f-3584-4fa8-9656-be91ccb3b7a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26329655286914779338907318245536388392244530626397585274819226352569867179978 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.26329655286914779338907318245536388392244530626397585274819226352569867179978
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.8322535166488999808439675613695718069501137500978539031575626269837229429694
Short name T32
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.7 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:50:25 PM PDT 23
Peak memory 218956 kb
Host smart-1af10a6b-6da6-4ba9-acbc-8821ae43f27a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8322535166488999808439675613695718069501137500978539031575626269837229429694 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_passthru_mem_tl_intg_err.83225351664889998084396756136957180695011375009785390315
75626269837229429694
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.64402859696796713685425386700638732921082350261729862995718735212857517578340
Short name T387
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.85 seconds
Started Nov 01 02:45:54 PM PDT 23
Finished Nov 01 02:46:09 PM PDT 23
Peak memory 210828 kb
Host smart-b4c1f87f-43c2-43fd-aecb-7351746f7e12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64402859696796713685425386700638732921082350261729862995718735212857517578340
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_same_csr_outstanding.64402859696796713685425386700638732921082350261729862
995718735212857517578340
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.35427634667580580452479084867342441786023271058720037419731559643747506033659
Short name T30
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.14 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 219124 kb
Host smart-41b247c2-beda-4d21-98ae-8c613eaf8a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35427634667580580452479084867342441786023271058720037419731559643747506033659 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.35427634667580580452479084867342441786023271058720037419731559643747506033659
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.27742178268768923933294621864803399817599894277600256347440752099154985500553
Short name T378
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.54 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:47:06 PM PDT 23
Peak memory 211116 kb
Host smart-701a4722-150f-489e-a47e-956f396a0172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742178268768923933294621864803399817599894277600256347440752099154985500553 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_intg_err.27742178268768923933294621864803399817599894277600256347440752099154985500553
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.59620487861202142902060821803983291548810973625497513923979413135175427236239
Short name T101
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.21 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:45:55 PM PDT 23
Peak memory 213256 kb
Host smart-15985b7f-a197-4b31-8f69-6707e767323b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5962048786120214290206082180398329154881097
3625497513923979413135175427236239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.596204878612
02142902060821803983291548810973625497513923979413135175427236239
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.10660469061710632816185029420143302588846806745067318141992678262282538788844
Short name T410
Test name
Test status
Simulation time 65914678386 ps
CPU time 288.41 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:50:31 PM PDT 23
Peak memory 218992 kb
Host smart-0fcebab3-2170-4b64-811d-7da2d6808b0b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10660469061710632816185029420143302588846806745067318141992678262282538788844 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_passthru_mem_tl_intg_err.1066046906171063281618502942014330258884680674506731814
1992678262282538788844
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.78755613863092330563196624192302801814483914398590762619605754822473404826601
Short name T19
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.09 seconds
Started Nov 01 02:45:38 PM PDT 23
Finished Nov 01 02:45:53 PM PDT 23
Peak memory 210792 kb
Host smart-ca338f8c-694d-49d1-a95c-40a8ee207d2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78755613863092330563196624192302801814483914398590762619605754822473404826601
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_same_csr_outstanding.78755613863092330563196624192302801814483914398590762
619605754822473404826601
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.111315060850450136975482481936344105020084312599937588157562637904111488473034
Short name T70
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.17 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 219024 kb
Host smart-af190d0d-8b52-473d-8343-bc0b3ab83830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111315060850450136975482481936344105020084312599937588157562637904111488473034 -assert nopostproc +
UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover
_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.111315060850450136975482481936344105020084312599937588157562637904111488473034
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.100886771293450263681394523065237421237268757615053075094750859591659032136433
Short name T436
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.44 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:47:04 PM PDT 23
Peak memory 211060 kb
Host smart-ceabdf3a-c6fb-40a8-a00b-5f9a66daa14b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100886771293450263681394523065237421237268757615053075094750859591659032136433 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_intg_err.100886771293450263681394523065237421237268757615053075094750859591659032136433
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.102885986762709235314921834692622484911792167814268535186862254498753153574606
Short name T442
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.16 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:45:56 PM PDT 23
Peak memory 210904 kb
Host smart-094eb36b-c4b5-426b-866d-27b8eecbae76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102885986762709235314921834692622484911792167814268535186862254498753153574606 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.102885986762709235314921834692622484911792167814268535186862254498753153574606
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.27835452819599541747630726988254182216189428636622539634402239211475858349204
Short name T75
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.55 seconds
Started Nov 01 02:45:37 PM PDT 23
Finished Nov 01 02:50:19 PM PDT 23
Peak memory 219044 kb
Host smart-5841f07d-8818-41d7-b1b1-2179de60353d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27835452819599541747630726988254182216189428636622539634402239211475858349204 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_passthru_mem_tl_intg_err.2783545281959954174763072698825418221618942863662253963
4402239211475858349204
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.31235241294564232160533243305190757269564112132540954357505881296592801407591
Short name T446
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.17 seconds
Started Nov 01 02:45:44 PM PDT 23
Finished Nov 01 02:45:59 PM PDT 23
Peak memory 210512 kb
Host smart-ee85d492-9cc9-4463-b3aa-303814a89d04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31235241294564232160533243305190757269564112132540954357505881296592801407591
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_same_csr_outstanding.31235241294564232160533243305190757269564112132540954
357505881296592801407591
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.99021232743476782893239247589651633605186553021560996915687658448081304447468
Short name T68
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.12 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:46:00 PM PDT 23
Peak memory 219104 kb
Host smart-63d0a4a1-793a-451d-9508-14cebaf03964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99021232743476782893239247589651633605186553021560996915687658448081304447468 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.99021232743476782893239247589651633605186553021560996915687658448081304447468
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.70466438374975648340970519330854146061432314469292784394738756896229908370267
Short name T404
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.74 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:47:04 PM PDT 23
Peak memory 211124 kb
Host smart-0878ce5c-46dd-4dc9-979a-e5fc45f26932
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70466438374975648340970519330854146061432314469292784394738756896229908370267 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg_err.70466438374975648340970519330854146061432314469292784394738756896229908370267
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.34638888573074184005295829764925391305720868325488324306803886997266633763163
Short name T429
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.29 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 213508 kb
Host smart-e0a2d8c3-3b68-4abd-be53-f1b85ba7c5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463888857307418400529582976492539130572086
8325488324306803886997266633763163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.346388885730
74184005295829764925391305720868325488324306803886997266633763163
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.18817878756523990551395128656463157089186824435911582690880421463004868703416
Short name T364
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Nov 01 02:45:43 PM PDT 23
Finished Nov 01 02:45:57 PM PDT 23
Peak memory 210876 kb
Host smart-e2dfef6c-a24b-4aa0-9e4b-282c5dd47c5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18817878756523990551395128656463157089186824435911582690880421463004868703416 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.18817878756523990551395128656463157089186824435911582690880421463004868703416
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.66423219786380580268690026085722360678687036350062153110711832897363283640303
Short name T448
Test name
Test status
Simulation time 65914678386 ps
CPU time 282.93 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:50:23 PM PDT 23
Peak memory 218936 kb
Host smart-467efe00-8cae-4994-a36b-391c2a9d2606
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66423219786380580268690026085722360678687036350062153110711832897363283640303 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_passthru_mem_tl_intg_err.6642321978638058026869002608572236067868703635006215311
0711832897363283640303
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.113640642979266834985345431531427779649297534353752367232383496965029875553081
Short name T363
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.16 seconds
Started Nov 01 02:45:44 PM PDT 23
Finished Nov 01 02:45:59 PM PDT 23
Peak memory 210876 kb
Host smart-2535fb27-c4e2-4d74-85b4-fae67f1eab07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113640642979266834985345431531427779649297534353752367232383496965029875553081
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_same_csr_outstanding.1136406429792668349853454315314277796492975343537523
67232383496965029875553081
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.58726062909804126423298387772290180434817341003187506396746262546361548892466
Short name T418
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.29 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:58 PM PDT 23
Peak memory 219000 kb
Host smart-3544a451-76fa-4d92-a478-1898e91efb40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58726062909804126423298387772290180434817341003187506396746262546361548892466 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.58726062909804126423298387772290180434817341003187506396746262546361548892466
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.108360376808454282864809274484059861071072907476170083830087251139240628164811
Short name T375
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.14 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:47:03 PM PDT 23
Peak memory 210996 kb
Host smart-f4392ecc-6410-4577-948f-353e23f9fade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108360376808454282864809274484059861071072907476170083830087251139240628164811 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_intg_err.108360376808454282864809274484059861071072907476170083830087251139240628164811
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.49497627751122738520363450552633352174693728800770846582687483292321761270514
Short name T59
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.18 seconds
Started Nov 01 02:45:38 PM PDT 23
Finished Nov 01 02:45:51 PM PDT 23
Peak memory 213364 kb
Host smart-7d88c959-26a0-404a-b520-ebc44ce13412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4949762775112273852036345055263335217469372
8800770846582687483292321761270514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.494976277511
22738520363450552633352174693728800770846582687483292321761270514
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.29338675132018360169595660787215250209141921709837987072996075756882821233741
Short name T374
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.2 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:53 PM PDT 23
Peak memory 210876 kb
Host smart-cebef06d-6166-45b8-b7f2-06f1bea38976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29338675132018360169595660787215250209141921709837987072996075756882821233741 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.29338675132018360169595660787215250209141921709837987072996075756882821233741
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.94841332430132578985980236017286881377886032393150425759801237378296565068851
Short name T66
Test name
Test status
Simulation time 65914678386 ps
CPU time 285.12 seconds
Started Nov 01 02:45:44 PM PDT 23
Finished Nov 01 02:50:30 PM PDT 23
Peak memory 218568 kb
Host smart-f8cbda49-2a5b-4b14-815a-c723de5078ac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94841332430132578985980236017286881377886032393150425759801237378296565068851 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_passthru_mem_tl_intg_err.9484133243013257898598023601728688137788603239315042575
9801237378296565068851
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.113006664475907341476846843326078228012468003864670076573424480461200634496179
Short name T97
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.81 seconds
Started Nov 01 02:45:40 PM PDT 23
Finished Nov 01 02:45:55 PM PDT 23
Peak memory 210916 kb
Host smart-bbec43fa-018a-4743-b7b8-fa80b185dce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113006664475907341476846843326078228012468003864670076573424480461200634496179
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_same_csr_outstanding.1130066644759073414768468433260782280124680038646700
76573424480461200634496179
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2309246537150925394283305256837576878182403530415553476639790814568702575111
Short name T407
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.19 seconds
Started Nov 01 02:45:42 PM PDT 23
Finished Nov 01 02:46:00 PM PDT 23
Peak memory 219092 kb
Host smart-48aca424-1afa-4ec1-a095-9bca642955ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309246537150925394283305256837576878182403530415553476639790814568702575111 -assert nopostproc +UV
M_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.2309246537150925394283305256837576878182403530415553476639790814568702575111
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.48469486254961473853856824145678206913135238519816636130391729392974142067707
Short name T437
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.07 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:47:03 PM PDT 23
Peak memory 211056 kb
Host smart-89f830af-fe68-47c5-9f04-8324878f43a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48469486254961473853856824145678206913135238519816636130391729392974142067707 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_intg_err.48469486254961473853856824145678206913135238519816636130391729392974142067707
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.69438159241447253860104670495213431138152424033719710814690513498249519469758
Short name T423
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.26 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 213492 kb
Host smart-06909d54-87ea-43e8-9cdf-f042cb35d86d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6943815924144725386010467049521343113815242
4033719710814690513498249519469758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.694381592414
47253860104670495213431138152424033719710814690513498249519469758
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.71751380493909767809041054129808123636522671077916608305649023171191307103324
Short name T73
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:53 PM PDT 23
Peak memory 210868 kb
Host smart-8cca2807-6964-40b9-b848-2b0a50bac44e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71751380493909767809041054129808123636522671077916608305649023171191307103324 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.71751380493909767809041054129808123636522671077916608305649023171191307103324
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.83483572745294168686803534342248401362921034314060649523103821309303040179951
Short name T76
Test name
Test status
Simulation time 65914678386 ps
CPU time 291.26 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:50:32 PM PDT 23
Peak memory 219012 kb
Host smart-37de10c4-0a60-4b68-8f38-a24d07dd8554
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83483572745294168686803534342248401362921034314060649523103821309303040179951 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_passthru_mem_tl_intg_err.8348357274529416868680353434224840136292103431406064952
3103821309303040179951
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.68730964728416486129176802673269054101802793506164170694025701515400445105164
Short name T25
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.98 seconds
Started Nov 01 02:45:39 PM PDT 23
Finished Nov 01 02:45:54 PM PDT 23
Peak memory 210864 kb
Host smart-5e912c5b-8251-4dba-b515-fc3090f2ac3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68730964728416486129176802673269054101802793506164170694025701515400445105164
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_same_csr_outstanding.68730964728416486129176802673269054101802793506164170
694025701515400445105164
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.88891371514962402225382130054601553802076311710528585540203909779381120497144
Short name T60
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.48 seconds
Started Nov 01 02:45:44 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 219108 kb
Host smart-611adeab-cad1-42f4-a977-a2ca7e4b0982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88891371514962402225382130054601553802076311710528585540203909779381120497144 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.88891371514962402225382130054601553802076311710528585540203909779381120497144
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.22542654126927992810940064874499807845789099083137563499049611981775643579961
Short name T95
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.98 seconds
Started Nov 01 02:45:41 PM PDT 23
Finished Nov 01 02:47:05 PM PDT 23
Peak memory 211052 kb
Host smart-3492a8fa-2d69-4c45-92ba-6c50e36c6149
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542654126927992810940064874499807845789099083137563499049611981775643579961 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_intg_err.22542654126927992810940064874499807845789099083137563499049611981775643579961
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.97373203058262387479902266936229669103516901102300825434101904345881372327875
Short name T88
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 210904 kb
Host smart-b5fdb4a4-7765-46d6-80a6-77461e5a13da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97373203058262387479902266936229669103516901102300825434101904345881372327875 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasing.97373203058262387479902266936229669103516901102300825434101904345881372327875
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.113183218775121148911983682375883971579768192305897692503639520762261598594329
Short name T87
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.63 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:33 PM PDT 23
Peak memory 210888 kb
Host smart-5ba7f518-4661-4915-8ee3-4af880b8fcd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113183218775121148911983682375883971579768192305897692503639520762261598594329 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_bash.113183218775121148911983682375883971579768192305897692503639520762261598594329
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.36202644591522869128856904871922292116959899803194159051866723596339678161106
Short name T100
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.34 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 213040 kb
Host smart-cf496728-33ee-4df6-ad6a-70a2557a88ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620264459152286912885690487192229211695989
9803194159051866723596339678161106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3620264459152
2869128856904871922292116959899803194159051866723596339678161106
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.51934066352610064529310663212582230193909199273562138359537703098801547115149
Short name T419
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.98 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210888 kb
Host smart-64b942f9-ac0d-46a9-a292-90c754c24514
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51934066352610064529310663212582230193909199273562138359537703098801547115149 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.51934066352610064529310663212582230193909199273562138359537703098801547115149
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.54314322646933043614273084616890000244024535642873274373347749528031446547788
Short name T376
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.98 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210868 kb
Host smart-97df900f-782f-49fa-8fac-6773b00652bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54314322646933043614273084616890000244024535642873274373347749528031446547788 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_partial_access.5431432264693304361427308461689000024402453564287327437334
7749528031446547788
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.82709977561231077599321987875249275807598012884317659463583673133515125988495
Short name T388
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.03 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210964 kb
Host smart-c33228ee-a9a4-42d7-b11a-6579032fc899
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82709977561231077599321987875249275807598012884317659463583673133515125988495 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.82709977561231077599321987875249275807598012884317659463583673133515125988495
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.110690679373477531129353139960557980863654021108438270299437939589192335535945
Short name T64
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.81 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:50:03 PM PDT 23
Peak memory 218972 kb
Host smart-aac90d68-8261-402e-a4c2-7178f2dfda9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110690679373477531129353139960557980863654021108438270299437939589192335535945 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_passthru_mem_tl_intg_err.1106906793734775311293531399605579808636540211084382702
99437939589192335535945
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.91086827159193137947407053227663125622289353552822234975237387921107734293946
Short name T98
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.92 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:37 PM PDT 23
Peak memory 209868 kb
Host smart-dacb11e0-65f6-4f98-9adc-0f1d5c03a4de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91086827159193137947407053227663125622289353552822234975237387921107734293946
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_same_csr_outstanding.910868271591931379474070532276631256222893535528222349
75237387921107734293946
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.61937533123964061195166101723667532292032539633040069158433273817708623439123
Short name T55
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.23 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 219112 kb
Host smart-d8e0a073-b1b6-432e-85de-11e4c1a6511d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61937533123964061195166101723667532292032539633040069158433273817708623439123 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.61937533123964061195166101723667532292032539633040069158433273817708623439123
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.103733885836204022262763814838887492954624215762916826019355245465200971126609
Short name T381
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.42 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:46:41 PM PDT 23
Peak memory 211208 kb
Host smart-7b5d5768-5586-4d10-b965-d72357b801da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103733885836204022262763814838887492954624215762916826019355245465200971126609 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg_err.103733885836204022262763814838887492954624215762916826019355245465200971126609
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.93093880995131692787591071697741036835054565273470839056801123613054666960461
Short name T86
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Nov 01 02:45:24 PM PDT 23
Finished Nov 01 02:45:37 PM PDT 23
Peak memory 210808 kb
Host smart-a42bccf7-a8ae-41d4-b724-99a5fe154f6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93093880995131692787591071697741036835054565273470839056801123613054666960461 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_aliasing.93093880995131692787591071697741036835054565273470839056801123613054666960461
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.47868904273722472153812939082684191974798362218760696181447324048207154434452
Short name T450
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.61 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 210896 kb
Host smart-36f7eeaf-6ae3-404f-992b-a213540c55c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47868904273722472153812939082684191974798362218760696181447324048207154434452 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_bash.47868904273722472153812939082684191974798362218760696181447324048207154434452
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.30500218747885048547902015783578001514674475056451395385813346557308082191156
Short name T382
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.6 seconds
Started Nov 01 02:45:19 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 210960 kb
Host smart-96a947ca-b190-4ee4-9129-3da861b05f7b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30500218747885048547902015783578001514674475056451395385813346557308082191156 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_reset.30500218747885048547902015783578001514674475056451395385813346557308082191156
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.33513228866284443115529902035902154797195528889683137359405408725405165675143
Short name T443
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.71 seconds
Started Nov 01 02:45:24 PM PDT 23
Finished Nov 01 02:45:37 PM PDT 23
Peak memory 213412 kb
Host smart-2983ee42-3313-40fd-ade7-719d571eaf21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351322886628444311552990203590215479719552
8889683137359405408725405165675143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3351322886628
4443115529902035902154797195528889683137359405408725405165675143
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.84788629686169822187556169868695150265853170926091125523611868501657527003405
Short name T99
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 210860 kb
Host smart-c7fd1fe5-c4c1-463a-8c75-e100574a7302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84788629686169822187556169868695150265853170926091125523611868501657527003405 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.84788629686169822187556169868695150265853170926091125523611868501657527003405
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.86298553249835049335263496661331014482025577739653438543052543750824137404469
Short name T365
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.8 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 210844 kb
Host smart-06f28081-6135-4c18-becd-aba6dcfd9f48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86298553249835049335263496661331014482025577739653438543052543750824137404469 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_partial_access.8629855324983504933526349666133101448202557773965343854305
2543750824137404469
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.34962826015450726292690565179633828039364624551650941709899478432223286249520
Short name T90
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.05 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 210732 kb
Host smart-0bb7c530-b54b-4204-a1bf-619f7b243ee7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34962826015450726292690565179633828039364624551650941709899478432223286249520 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.34962826015450726292690565179633828039364624551650941709899478432223286249520
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.13784709837187966814485654809885533790133759628583298806976096616644342396517
Short name T65
Test name
Test status
Simulation time 65914678386 ps
CPU time 277.55 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:49:59 PM PDT 23
Peak memory 218972 kb
Host smart-8a420483-c95f-4fde-b55a-b44eb93d3b04
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784709837187966814485654809885533790133759628583298806976096616644342396517 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_passthru_mem_tl_intg_err.13784709837187966814485654809885533790133759628583298806
976096616644342396517
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.87206476352428333664830913516532998092007152042319107472697919869760062971824
Short name T438
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.1 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 210844 kb
Host smart-a80ddd75-1bf7-47fd-b984-073a8b352b82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87206476352428333664830913516532998092007152042319107472697919869760062971824
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_same_csr_outstanding.872064763524283336648309135165329980920071520423191074
72697919869760062971824
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.98479593378018244216864819571060951773198304239624483778926364566514648049885
Short name T434
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.43 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 219028 kb
Host smart-2f40ed31-0e67-4fde-b75a-29e9fee18872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98479593378018244216864819571060951773198304239624483778926364566514648049885 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.98479593378018244216864819571060951773198304239624483778926364566514648049885
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.100586735283959211515985432358941745584991757100196617111933846934761268554702
Short name T400
Test name
Test status
Simulation time 3476453456 ps
CPU time 82.14 seconds
Started Nov 01 02:45:25 PM PDT 23
Finished Nov 01 02:46:47 PM PDT 23
Peak memory 211096 kb
Host smart-67bfecfa-be95-4382-b2e5-36a8c29d8c57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100586735283959211515985432358941745584991757100196617111933846934761268554702 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_intg_err.100586735283959211515985432358941745584991757100196617111933846934761268554702
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.92396888892276826505955356656097974140006139914329481569690683736311119920340
Short name T416
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.32 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210856 kb
Host smart-a831d4bc-03e2-4ad3-90a7-db88e36eec92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92396888892276826505955356656097974140006139914329481569690683736311119920340 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_aliasing.92396888892276826505955356656097974140006139914329481569690683736311119920340
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.97552820641909787452995259895608369841987286319486582961887147150644100979743
Short name T80
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.5 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210920 kb
Host smart-c209a010-16e0-46dd-b067-6269c3b421c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97552820641909787452995259895608369841987286319486582961887147150644100979743 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_bash.97552820641909787452995259895608369841987286319486582961887147150644100979743
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.42650343941465103392824344123675742791360410295974877753819662998615401359480
Short name T406
Test name
Test status
Simulation time 3138518126 ps
CPU time 15.73 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:25 PM PDT 23
Peak memory 210888 kb
Host smart-34b61433-7d9c-4224-b65f-df288bb30294
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42650343941465103392824344123675742791360410295974877753819662998615401359480 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_reset.42650343941465103392824344123675742791360410295974877753819662998615401359480
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.73055440226640047738719577938750346336421825608632601397844875347397471076420
Short name T447
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.3 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 213480 kb
Host smart-e09817e1-11a5-448d-8495-50ea1ced4eb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7305544022664004773871957793875034633642182
5608632601397844875347397471076420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.7305544022664
0047738719577938750346336421825608632601397844875347397471076420
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2537390815299998821744874935018358401646522031471705945102097844556200430449
Short name T72
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.46 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:28 PM PDT 23
Peak memory 210852 kb
Host smart-e0961ae6-12a8-4834-b7e6-54bd3862e04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537390815299998821744874935018358401646522031471705945102097844556200430449 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cove
r_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2537390815299998821744874935018358401646522031471705945102097844556200430449
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.86165118299453949365033565369518782626682602615508207938028489130989324999019
Short name T445
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.1 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:45:24 PM PDT 23
Peak memory 210872 kb
Host smart-30e3598b-24fb-41ab-9718-1655f4b4d6e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86165118299453949365033565369518782626682602615508207938028489130989324999019 -a
ssert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_partial_access.8616511829945394936503356536951878262668260261550820793802
8489130989324999019
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.86304052924465255002536133899509357439161758719197416130752388572580440744248
Short name T390
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.87 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:21 PM PDT 23
Peak memory 210884 kb
Host smart-85113e3a-58b5-4267-a5da-eb9c1b4db2f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86304052924465255002536133899509357439161758719197416130752388572580440744248 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.86304052924465255002536133899509357439161758719197416130752388572580440744248
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.101408497199691334736963264913107184290587340354190636126998960418564435117549
Short name T432
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.17 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:50:06 PM PDT 23
Peak memory 218992 kb
Host smart-892e451d-f626-47e3-825d-904479418bac
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101408497199691334736963264913107184290587340354190636126998960418564435117549 -asse
rt nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_passthru_mem_tl_intg_err.1014084971996913347369632649131071842905873403541906361
26998960418564435117549
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.61611199449313028709822559179727570511009980012348602982707354826905178970512
Short name T417
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.7 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:45:28 PM PDT 23
Peak memory 210956 kb
Host smart-a963e850-08ef-49b4-82f4-6a7443e4c537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61611199449313028709822559179727570511009980012348602982707354826905178970512
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_same_csr_outstanding.616111994493130287098225591797275705110099800123486029
82707354826905178970512
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.94836578604211600423464713232265602838560784193766288685127894386605461058510
Short name T412
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.34 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:39 PM PDT 23
Peak memory 219108 kb
Host smart-8c105480-565b-452f-9d09-e09e5fdc4898
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94836578604211600423464713232265602838560784193766288685127894386605461058510 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.94836578604211600423464713232265602838560784193766288685127894386605461058510
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.17694233449433019781135458179016262136810784508036633212767183056465225952332
Short name T54
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.84 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:46:36 PM PDT 23
Peak memory 210984 kb
Host smart-5854c7b6-cde1-4de1-947c-34a274053147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17694233449433019781135458179016262136810784508036633212767183056465225952332 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_intg_err.17694233449433019781135458179016262136810784508036633212767183056465225952332
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.57955526434664130641300848800529623309538549487933697765786586476898969009636
Short name T33
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.44 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:29 PM PDT 23
Peak memory 213456 kb
Host smart-f2e9f87f-a000-4b1e-a814-87cdf0faadb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5795552643466413064130084880052962330953854
9487933697765786586476898969009636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.5795552643466
4130641300848800529623309538549487933697765786586476898969009636
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.43919625784695503570465063229054961674714697979677908825319341764147599445296
Short name T92
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.64 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:45:22 PM PDT 23
Peak memory 210820 kb
Host smart-582a243a-6dce-43ae-94ea-f2964ee2722d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43919625784695503570465063229054961674714697979677908825319341764147599445296 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.43919625784695503570465063229054961674714697979677908825319341764147599445296
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.32452850888251959898516933350916692239876358962714293349985049128471158396502
Short name T74
Test name
Test status
Simulation time 65914678386 ps
CPU time 281.35 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:49:53 PM PDT 23
Peak memory 218952 kb
Host smart-8d3f061b-1452-4945-84e2-f95e0ca36ba5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452850888251959898516933350916692239876358962714293349985049128471158396502 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_passthru_mem_tl_intg_err.32452850888251959898516933350916692239876358962714293349
985049128471158396502
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.87970461305232891204429067659874910128659755401329028927829152497656032754587
Short name T394
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.96 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 210816 kb
Host smart-43ae0902-7445-4856-a771-cdf5ee2dfbde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87970461305232891204429067659874910128659755401329028927829152497656032754587
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_same_csr_outstanding.879704613052328912044290676598749101286597554013290289
27829152497656032754587
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.32378841835940201953995719920528439540496541147079438724909269935818362577718
Short name T439
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.01 seconds
Started Nov 01 02:45:06 PM PDT 23
Finished Nov 01 02:45:28 PM PDT 23
Peak memory 219048 kb
Host smart-7cc4ce59-20c5-4f9a-a458-e2c14e32949c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378841835940201953995719920528439540496541147079438724909269935818362577718 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.32378841835940201953995719920528439540496541147079438724909269935818362577718
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.84014334592753358027831370296049031372027530049484734127038218020798899231791
Short name T440
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.53 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:46:31 PM PDT 23
Peak memory 211044 kb
Host smart-13d76bc2-ea2c-4ae4-b3a9-d75e7e0a04f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84014334592753358027831370296049031372027530049484734127038218020798899231791 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg_err.84014334592753358027831370296049031372027530049484734127038218020798899231791
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3701849486665999946279275651402649475053508124504613147609653229364806461097
Short name T366
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.32 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 213492 kb
Host smart-0518cb1e-586e-4d42-97bb-42166a348ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701849486665999946279275651402649475053508
124504613147609653229364806461097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.37018494866659
99946279275651402649475053508124504613147609653229364806461097
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.21918453253491568615808223149624593105679526928388607007675955418777799740245
Short name T396
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210868 kb
Host smart-1fb3c557-a4c6-4c11-af9d-e21a4586f2d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21918453253491568615808223149624593105679526928388607007675955418777799740245 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.21918453253491568615808223149624593105679526928388607007675955418777799740245
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.41443293737171536774001406538632672202734655939550361509758498665380060879495
Short name T431
Test name
Test status
Simulation time 65914678386 ps
CPU time 287.05 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:50:04 PM PDT 23
Peak memory 219016 kb
Host smart-7b5a0912-b831-4c2b-aa3e-a24f58ab8a3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41443293737171536774001406538632672202734655939550361509758498665380060879495 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_passthru_mem_tl_intg_err.41443293737171536774001406538632672202734655939550361509
758498665380060879495
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.26329241524458827069477949707385590768924023599609416446972780502771790354328
Short name T413
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.58 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 210868 kb
Host smart-6c990578-30f7-4e2a-97a6-2dd24181bc8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26329241524458827069477949707385590768924023599609416446972780502771790354328
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_same_csr_outstanding.263292415244588270694779497073855907689240235996094164
46972780502771790354328
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.91175983580613122981017573963915473550759580534540753217745270200402372896306
Short name T408
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.37 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 219076 kb
Host smart-a7d4e890-adf3-4aa8-aad1-f92b28deb258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91175983580613122981017573963915473550759580534540753217745270200402372896306 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.91175983580613122981017573963915473550759580534540753217745270200402372896306
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.88570323061444825189820240925938267017884380885930345026061016702512244199333
Short name T444
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.81 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:46:44 PM PDT 23
Peak memory 210760 kb
Host smart-07ce9c83-d6f9-45be-a979-e9e687915227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88570323061444825189820240925938267017884380885930345026061016702512244199333 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_intg_err.88570323061444825189820240925938267017884380885930345026061016702512244199333
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.16312581640069724709278833797187137235501630452858515479619294690595717194370
Short name T56
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.09 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 213460 kb
Host smart-39494a4f-7926-40ce-a2c7-1fa75a7ad6a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631258164006972470927883379718713723550163
0452858515479619294690595717194370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1631258164006
9724709278833797187137235501630452858515479619294690595717194370
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.25132406085136698675926581009389631062683844645479303829766729062007676605698
Short name T370
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.15 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 210840 kb
Host smart-835b05fb-db73-4c87-bff3-1c82c8ff2b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25132406085136698675926581009389631062683844645479303829766729062007676605698 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.25132406085136698675926581009389631062683844645479303829766729062007676605698
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.84910500029223368493637609846112198077728618216528389342998768259614505997984
Short name T426
Test name
Test status
Simulation time 65914678386 ps
CPU time 291.01 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:50:09 PM PDT 23
Peak memory 219016 kb
Host smart-ba20a9dd-c31a-4cad-89f4-80dacec1ef77
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84910500029223368493637609846112198077728618216528389342998768259614505997984 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_passthru_mem_tl_intg_err.84910500029223368493637609846112198077728618216528389342
998768259614505997984
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.81099569696483442789149029260436107983796760294021664532864550874617458009101
Short name T424
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.47 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210816 kb
Host smart-77e4e2e1-4896-4a2f-be03-1ac20bcdb2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81099569696483442789149029260436107983796760294021664532864550874617458009101
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_same_csr_outstanding.810995696964834427891490292604361079837967602940216645
32864550874617458009101
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.74986354328925342774079875650532611983776911432494961531457824965360372987703
Short name T62
Test name
Test status
Simulation time 3124113076 ps
CPU time 16.39 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 219116 kb
Host smart-2d2f5a35-1649-4251-afc0-6bf6de248c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74986354328925342774079875650532611983776911432494961531457824965360372987703 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.74986354328925342774079875650532611983776911432494961531457824965360372987703
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.28934034356943312315565930557421832031756615162055933028007779653958258809201
Short name T395
Test name
Test status
Simulation time 3476453456 ps
CPU time 78.89 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:46:38 PM PDT 23
Peak memory 211032 kb
Host smart-c813e5b5-a970-4f0a-a913-0b7b44cb2da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28934034356943312315565930557421832031756615162055933028007779653958258809201 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_intg_err.28934034356943312315565930557421832031756615162055933028007779653958258809201
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.114520372871677518096365642959869769858787775336713158520671843988058603931614
Short name T96
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.24 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 213496 kb
Host smart-0e699d93-d2cb-4335-9493-d29e667052a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145203728716775180963656429598697698587877
75336713158520671843988058603931614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.114520372871
677518096365642959869769858787775336713158520671843988058603931614
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.85638006728989641060518717514491822079710099257653156749069621912913487788813
Short name T367
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Nov 01 02:45:18 PM PDT 23
Finished Nov 01 02:45:32 PM PDT 23
Peak memory 210972 kb
Host smart-1d483220-6a9b-4b43-8fa2-df94ea2f4c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85638006728989641060518717514491822079710099257653156749069621912913487788813 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.85638006728989641060518717514491822079710099257653156749069621912913487788813
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.88410438101730290150516346870073794441676097377103394116396748817587152877856
Short name T428
Test name
Test status
Simulation time 65914678386 ps
CPU time 283.36 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:50:01 PM PDT 23
Peak memory 218952 kb
Host smart-b91e8849-ca51-4a87-a060-6bad584c4d1d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88410438101730290150516346870073794441676097377103394116396748817587152877856 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_passthru_mem_tl_intg_err.88410438101730290150516346870073794441676097377103394116
396748817587152877856
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.56636168722861759129254733225210437951353890437929119278675874018331633561777
Short name T379
Test name
Test status
Simulation time 3142303916 ps
CPU time 14.11 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 210868 kb
Host smart-2f404831-8394-440c-99fb-1b2f91841afd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56636168722861759129254733225210437951353890437929119278675874018331633561777
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_same_csr_outstanding.566361687228617591292547332252104379513538904379291192
78675874018331633561777
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.26119102682742286183337932523701908386971670693357970419559793924400300763956
Short name T402
Test name
Test status
Simulation time 3124113076 ps
CPU time 15.88 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 219104 kb
Host smart-92c17ca4-a795-469f-8502-3d157ab078aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26119102682742286183337932523701908386971670693357970419559793924400300763956 -assert nopostproc +U
VM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.26119102682742286183337932523701908386971670693357970419559793924400300763956
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.28719608806361528756589130645537217596457549274226123998566339219088765831285
Short name T94
Test name
Test status
Simulation time 3476453456 ps
CPU time 81.41 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:46:41 PM PDT 23
Peak memory 211112 kb
Host smart-b746d784-f369-4a2c-9813-e16d1f35383d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719608806361528756589130645537217596457549274226123998566339219088765831285 -assert n
opostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_intg_err.28719608806361528756589130645537217596457549274226123998566339219088765831285
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.33569995624494190018748970588782264625663869060666611393659063410027358974003
Short name T430
Test name
Test status
Simulation time 3135422826 ps
CPU time 12.36 seconds
Started Nov 01 02:45:25 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 213476 kb
Host smart-2fa50319-9485-4930-a9ed-7bcb0eb3c78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356999562449419001874897058878226462566386
9060666611393659063410027358974003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3356999562449
4190018748970588782264625663869060666611393659063410027358974003
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.16140393563855621190256944718537380764836998987816318850370386938713324912753
Short name T403
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.06 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:33 PM PDT 23
Peak memory 210832 kb
Host smart-e468b502-1ff7-4689-85b6-4c4972afb340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16140393563855621190256944718537380764836998987816318850370386938713324912753 -assert nopostproc
+UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cov
er_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.16140393563855621190256944718537380764836998987816318850370386938713324912753
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.33367532956105479065227306783159759668318676093915044505493713183102949121254
Short name T58
Test name
Test status
Simulation time 65914678386 ps
CPU time 286.12 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:50:10 PM PDT 23
Peak memory 218976 kb
Host smart-9d33eb05-938a-4b2e-abf6-c0ce9544c2a4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33367532956105479065227306783159759668318676093915044505493713183102949121254 -asser
t nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_passthru_mem_tl_intg_err.33367532956105479065227306783159759668318676093915044505
493713183102949121254
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.23071559098961680421973021207996360635037517009871947550608914215804665955980
Short name T23
Test name
Test status
Simulation time 3142303916 ps
CPU time 13.84 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:37 PM PDT 23
Peak memory 210832 kb
Host smart-ad7e721b-00ba-4281-bb35-f6a28f5c4201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23071559098961680421973021207996360635037517009871947550608914215804665955980
-assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_same_csr_outstanding.230715590989616804219730212079963606350375170098719475
50608914215804665955980
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.115046118592460155192062989829177412560337158454247229088968122676701437437222
Short name T18
Test name
Test status
Simulation time 3476453456 ps
CPU time 80.41 seconds
Started Nov 01 02:45:22 PM PDT 23
Finished Nov 01 02:46:44 PM PDT 23
Peak memory 210640 kb
Host smart-1cd7576e-a937-49c8-a659-dac21940e210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115046118592460155192062989829177412560337158454247229088968122676701437437222 -assert
nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_intg_err.115046118592460155192062989829177412560337158454247229088968122676701437437222
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.54859781021848953950095560786153928464694679523292880039696812372472288588475
Short name T204
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.02 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:49:53 PM PDT 23
Peak memory 237752 kb
Host smart-f73628b6-9223-4c24-a80f-994f4bf986aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54859781021848953950095560786153928464694679523292880039696812372472288588475 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_corrupt_sig_fatal_chk.5485978102184895395009556078615392846469467952329288003969
6812372472288588475
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.28402338693418751908067745277440232787738176263435560094855995001935640784721
Short name T243
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.65 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 211616 kb
Host smart-568ceacb-7edd-421b-8aab-c7a1817e01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28402338693418751908067745277440232787738176263435560094855995001935640784721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.rom_ctrl_kmac_err_chk.28402338693418751908067745277440232787738176263435560094855995001935640784721
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.16344453525176503974981793934201484746705570118116605146376838503536709272796
Short name T44
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:20 PM PDT 23
Peak memory 211116 kb
Host smart-3c1e51f4-1d70-45e0-9b5a-8058016f5e86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16344453525176503974981793934201484746705570118116605146376838503536709272796 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.16344453525176503974981793934201484746705570118116605146376838503536709272796
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.103998292331800016988822040071346872200772040531274220148974159381945755844122
Short name T355
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.39 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 212804 kb
Host smart-37a4b70a-f251-4371-b516-88541c59c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103998292331800016988822040071346872200772040531274220148974159381945755844122 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.rom_ctrl_smoke.103998292331800016988822040071346872200772040531274220148974159381945755844122
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.77670893794621551063042978626166343749435027063882716076472264213515975702871
Short name T244
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.17 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:51 PM PDT 23
Peak memory 212884 kb
Host smart-881b8e88-0024-48c3-85c0-7cabb5dd91c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776708937946215510630429786261663437494350270638827160764722642
13515975702871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all.776708937946215510630429786261663437494350270638827
16076472264213515975702871
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.24607776537780068814113723267780267550035493674701328224123819959396066025071
Short name T147
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.56 seconds
Started Nov 01 02:43:24 PM PDT 23
Finished Nov 01 02:43:38 PM PDT 23
Peak memory 211224 kb
Host smart-36be1fa2-a6b2-4b10-82b6-731e68f23925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24607776537780068814113723267780267550035493674701328224123819959396066025071 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.24607776537780068814113723267780267550035493674701328224123819959396066025071
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.71569228149177800938745260912024128843524417827373907563245258154073628063689
Short name T208
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.71 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:49:54 PM PDT 23
Peak memory 237748 kb
Host smart-49b50637-568e-454c-bd8f-1387e45e6a03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71569228149177800938745260912024128843524417827373907563245258154073628063689 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_corrupt_sig_fatal_chk.7156922814917780093874526091202412884352441782737390756324
5258154073628063689
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.78797386839123366495652058273488002788761331825025243656845487563879952812291
Short name T151
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:17 PM PDT 23
Peak memory 211232 kb
Host smart-a11573e9-3845-4709-845d-cf5ec92bd8cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78797386839123366495652058273488002788761331825025243656845487563879952812291 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.78797386839123366495652058273488002788761331825025243656845487563879952812291
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.22010205351892414029043856788198464964266229369478782426418211077216268451800
Short name T35
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.68 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:46:09 PM PDT 23
Peak memory 236760 kb
Host smart-5f908786-7abd-4c26-8a05-09600f394006
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010205351892414029043856788198464964266229369478782426418211077216268451800 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.22010205351892414029043856788198464964266229369478782426418211077216268451800
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.64894486772469562892749758695199200975993912577616459322846539986174009428064
Short name T166
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.18 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 212672 kb
Host smart-aaf52893-4c13-4031-9a13-2ad05c39f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64894486772469562892749758695199200975993912577616459322846539986174009428064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.rom_ctrl_smoke.64894486772469562892749758695199200975993912577616459322846539986174009428064
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.96325262211960026569561285861883502488335078159811637223148723821805466736593
Short name T119
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.66 seconds
Started Nov 01 02:44:10 PM PDT 23
Finished Nov 01 02:44:57 PM PDT 23
Peak memory 212976 kb
Host smart-a4e9a984-7de2-470c-aec7-6398665eba1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963252622119600265695612858618835024883350781598116372231487238
21805466736593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all.963252622119600265695612858618835024883350781598116
37223148723821805466736593
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.110085552223563964637852991391324883826566363854487483565266235723278723186405
Short name T329
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Nov 01 02:43:59 PM PDT 23
Finished Nov 01 02:44:12 PM PDT 23
Peak memory 211224 kb
Host smart-330560d6-0740-4e0a-9e96-f1d021b1f3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110085552223563964637852991391324883826566363854487483565266235723278723186405 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.110085552223563964637852991391324883826566363854487483565266235723278723186405
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.88082768357284024495165285383737268274893749307936851406691675641363574498159
Short name T304
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.08 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:49:39 PM PDT 23
Peak memory 237664 kb
Host smart-8c503a19-ecdf-41ff-bf11-1f2364e32d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88082768357284024495165285383737268274893749307936851406691675641363574498159 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_corrupt_sig_fatal_chk.880827683572840244951652853837372682748937493079368514066
91675641363574498159
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.33938944774251021720749636991568398804590654832859658470220580457842371378314
Short name T41
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.55 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211728 kb
Host smart-27d235fb-8c0d-4c3c-a717-8341f1ff91b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33938944774251021720749636991568398804590654832859658470220580457842371378314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.rom_ctrl_kmac_err_chk.33938944774251021720749636991568398804590654832859658470220580457842371378314
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.53845557442213781099242278708429257572728166154994364627919416185024200144919
Short name T300
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.75 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 212836 kb
Host smart-17a9bb07-960f-4fed-9c32-66167565804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53845557442213781099242278708429257572728166154994364627919416185024200144919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.rom_ctrl_smoke.53845557442213781099242278708429257572728166154994364627919416185024200144919
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.30818997941044461313223228242154839800684730776178845194168797294779972943311
Short name T349
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.54 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:44:10 PM PDT 23
Peak memory 212984 kb
Host smart-35f63a6d-b1c8-422a-bae3-ce9d21ba4fbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308189979410444613132232282421548398006847307761788451941687972
94779972943311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all.30818997941044461313223228242154839800684730776178
845194168797294779972943311
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.21791986484440241336987749375561493166427292440172239176423244476412283504542
Short name T133
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.38 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:20 PM PDT 23
Peak memory 211164 kb
Host smart-77282dad-941c-4c78-96cd-4580e905587d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21791986484440241336987749375561493166427292440172239176423244476412283504542 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.21791986484440241336987749375561493166427292440172239176423244476412283504542
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.78623762743740515240959783950427216238285285114712765752194665929014672685978
Short name T148
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.18 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:49:41 PM PDT 23
Peak memory 237616 kb
Host smart-12870551-69c3-4c76-8e96-2ab321c60a59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78623762743740515240959783950427216238285285114712765752194665929014672685978 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_corrupt_sig_fatal_chk.786237627437405152409597839504272162382852851147127657521
94665929014672685978
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.114269152009983949009469023187034463728789176463278029691093518109705145042947
Short name T130
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.37 seconds
Started Nov 01 02:43:48 PM PDT 23
Finished Nov 01 02:44:14 PM PDT 23
Peak memory 211640 kb
Host smart-3b856688-d012-4305-bd36-2be7d5860814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114269152009983949009469023187034463728789176463278029691093518109705145042947 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.rom_ctrl_kmac_err_chk.114269152009983949009469023187034463728789176463278029691093518109705145042947
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.71802403956863352943669039806931969003548446891604976389035606848321530195900
Short name T273
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.21 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 211276 kb
Host smart-3e5aa578-de6b-4333-915e-cfdd3a38a9cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71802403956863352943669039806931969003548446891604976389035606848321530195900 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.71802403956863352943669039806931969003548446891604976389035606848321530195900
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.46099434073010137098049480050707014786254259384623176988494987176125794294643
Short name T239
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.46 seconds
Started Nov 01 02:43:32 PM PDT 23
Finished Nov 01 02:44:01 PM PDT 23
Peak memory 212828 kb
Host smart-ce6763b5-c8bf-417b-b3d3-ef42b81ab2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46099434073010137098049480050707014786254259384623176988494987176125794294643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.rom_ctrl_smoke.46099434073010137098049480050707014786254259384623176988494987176125794294643
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.13343166496831774497950117767133711971266911020360341656087577469216418502822
Short name T104
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.56 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 212976 kb
Host smart-7061fb6e-1801-438e-9e92-af523c8e3698
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133431664968317744979501177671337119712669110203603416560875774
69216418502822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all.13343166496831774497950117767133711971266911020360
341656087577469216418502822
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.100154418526659829750714985433848752318014600795559464216762240018938366505343
Short name T9
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.41 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 211188 kb
Host smart-5e086cf5-ae04-4c3d-b025-1f9bc4b35ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100154418526659829750714985433848752318014600795559464216762240018938366505343 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.100154418526659829750714985433848752318014600795559464216762240018938366505343
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.96517954178171776932594635140229120821961152886983357902095440934399062627433
Short name T268
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.59 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:49:44 PM PDT 23
Peak memory 237788 kb
Host smart-bc638b18-b899-4bf3-9185-5b8993fc9a5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96517954178171776932594635140229120821961152886983357902095440934399062627433 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_corrupt_sig_fatal_chk.965179541781717769325946351402291208219611528869833579020
95440934399062627433
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.50266322712268114456059334247663731717853192579885119764862084905425257227015
Short name T191
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.65 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:36 PM PDT 23
Peak memory 211592 kb
Host smart-a7edde20-46aa-4072-834a-169a4c398dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50266322712268114456059334247663731717853192579885119764862084905425257227015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.rom_ctrl_kmac_err_chk.50266322712268114456059334247663731717853192579885119764862084905425257227015
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.28786100043663037110016291759902076550173554489773554441210256095942066838104
Short name T345
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:15 PM PDT 23
Peak memory 211224 kb
Host smart-33eae6e5-0247-4852-9f05-49f820564463
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28786100043663037110016291759902076550173554489773554441210256095942066838104 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.28786100043663037110016291759902076550173554489773554441210256095942066838104
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.24287675139471224378946952969225349024919280275547355400881496909922450275103
Short name T328
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.41 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 212828 kb
Host smart-9e26a857-16b8-44f3-8b94-bfb5fbabd750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24287675139471224378946952969225349024919280275547355400881496909922450275103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.rom_ctrl_smoke.24287675139471224378946952969225349024919280275547355400881496909922450275103
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.38150660616013246190325659442181415923735923352025902092780309748335423785176
Short name T108
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.72 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 212868 kb
Host smart-a3eedcf8-7201-488e-8011-0c48aec42df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381506606160132461903256594421814159237359233520259020927803097
48335423785176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all.38150660616013246190325659442181415923735923352025
902092780309748335423785176
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.67862057292961148659730294159960017169270600101165130913101455680105795871289
Short name T212
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Nov 01 02:43:59 PM PDT 23
Finished Nov 01 02:44:12 PM PDT 23
Peak memory 211240 kb
Host smart-d83c3021-0f76-4ce2-922c-3ff4bc4b7b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67862057292961148659730294159960017169270600101165130913101455680105795871289 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.67862057292961148659730294159960017169270600101165130913101455680105795871289
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.30049837868050918682693909576424891041814338377295096619551108805712327371086
Short name T8
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.92 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:49:49 PM PDT 23
Peak memory 237692 kb
Host smart-12938cd8-8567-405a-b928-28b6df45237e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30049837868050918682693909576424891041814338377295096619551108805712327371086 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_corrupt_sig_fatal_chk.300498378680509186826939095764248910418143383772950966195
51108805712327371086
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.16851653227136669857789170935296594143281566439464356917088232787716540989282
Short name T167
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.54 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:30 PM PDT 23
Peak memory 211632 kb
Host smart-39bf5438-d241-4373-8eeb-f5158229875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16851653227136669857789170935296594143281566439464356917088232787716540989282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.rom_ctrl_kmac_err_chk.16851653227136669857789170935296594143281566439464356917088232787716540989282
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.92649839271616304666469352313235665883914536164419504239898262297467512648189
Short name T316
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:17 PM PDT 23
Peak memory 211160 kb
Host smart-fe137476-cf78-4368-b37f-4230cca34611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92649839271616304666469352313235665883914536164419504239898262297467512648189 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.92649839271616304666469352313235665883914536164419504239898262297467512648189
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.25320321900011030891964363296347432974048121344668728851479300579058731085225
Short name T182
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.31 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 212896 kb
Host smart-e033cfa9-d456-4e1e-8510-e3d656054cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25320321900011030891964363296347432974048121344668728851479300579058731085225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.rom_ctrl_smoke.25320321900011030891964363296347432974048121344668728851479300579058731085225
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.80596898926852944639270868777718379764754435731623301161253608909105548572415
Short name T140
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.59 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 212972 kb
Host smart-5e5e789b-fa8b-4257-8bb7-27e64003c522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805968989268529446392708687777183797647544357316233011612536089
09105548572415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all.80596898926852944639270868777718379764754435731623
301161253608909105548572415
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.113275345108333315912338818074021150906724201123145750691559473315740118638842
Short name T305
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:18 PM PDT 23
Peak memory 211236 kb
Host smart-9a09f206-c0e9-471e-9c2d-bc535c0e58ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113275345108333315912338818074021150906724201123145750691559473315740118638842 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.113275345108333315912338818074021150906724201123145750691559473315740118638842
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.67734198836101090127753573861017330393227609485025504232276938876325181025654
Short name T48
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.75 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:49:51 PM PDT 23
Peak memory 237744 kb
Host smart-138392a1-859c-4cd3-bf64-60115330a187
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67734198836101090127753573861017330393227609485025504232276938876325181025654 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_corrupt_sig_fatal_chk.677341988361010901277535738610173303932276094850255042322
76938876325181025654
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.72210059906799389056266426160597644001587178795321996794679329962516773698392
Short name T240
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.74 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:29 PM PDT 23
Peak memory 211648 kb
Host smart-aeea5e10-230b-4375-93bb-9bc92a0682c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72210059906799389056266426160597644001587178795321996794679329962516773698392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.rom_ctrl_kmac_err_chk.72210059906799389056266426160597644001587178795321996794679329962516773698392
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.49534033636946633607815751068845370769819706788359656278134708243742096570122
Short name T12
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.22 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:19 PM PDT 23
Peak memory 211232 kb
Host smart-ce2cec64-fd5e-499f-b40d-b787e41fe3f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=49534033636946633607815751068845370769819706788359656278134708243742096570122 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.49534033636946633607815751068845370769819706788359656278134708243742096570122
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.65425406751891619312674563382074409327223577976550700184282232845468174576506
Short name T234
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.72 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 212940 kb
Host smart-be6dde29-1627-4747-95bc-3ef3ffe86471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65425406751891619312674563382074409327223577976550700184282232845468174576506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.rom_ctrl_smoke.65425406751891619312674563382074409327223577976550700184282232845468174576506
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.53934693118524843681764317503830571454163222809558718084845666480223963459282
Short name T314
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.38 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 213012 kb
Host smart-cd8bfb2c-1c99-4b4c-aa41-46207fdd66ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539346931185248436817643175038305714541632228095587180848456664
80223963459282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all.53934693118524843681764317503830571454163222809558
718084845666480223963459282
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.34972695080827878605366628424463374896646872214397837761845248686079878925839
Short name T112
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:15 PM PDT 23
Peak memory 211212 kb
Host smart-df0aa364-e59e-4a5a-b5d4-fb7935ddf36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34972695080827878605366628424463374896646872214397837761845248686079878925839 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.34972695080827878605366628424463374896646872214397837761845248686079878925839
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.98834624886929191905385259551068976681734655467236552011168449704812050154138
Short name T253
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.09 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211684 kb
Host smart-6cd28eef-52b9-43d0-b653-a5702f190898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98834624886929191905385259551068976681734655467236552011168449704812050154138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.rom_ctrl_kmac_err_chk.98834624886929191905385259551068976681734655467236552011168449704812050154138
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.59545872813359582974308264229953934531539408692325059234001169065409531322312
Short name T312
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.46 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:20 PM PDT 23
Peak memory 211240 kb
Host smart-d0ff2fe4-c487-4f91-a177-1f2bdac94b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=59545872813359582974308264229953934531539408692325059234001169065409531322312 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.59545872813359582974308264229953934531539408692325059234001169065409531322312
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.78623022876190131313440393467799263613540309364401097323742664017875257105357
Short name T237
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.29 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:45 PM PDT 23
Peak memory 212996 kb
Host smart-3f9790ee-30e4-4107-9854-e111522b55fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786230228761901313134403934677992636135403093644010973237426640
17875257105357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all.78623022876190131313440393467799263613540309364401
097323742664017875257105357
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.89193509783646906580147374731038999643313706597824540978957759799180739636624
Short name T285
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.34 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:13 PM PDT 23
Peak memory 211256 kb
Host smart-eae8383a-ad36-4891-882d-d55b89dc1fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89193509783646906580147374731038999643313706597824540978957759799180739636624 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.89193509783646906580147374731038999643313706597824540978957759799180739636624
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.77217773291856385183571768360119322496872009167818396631844384056315079216338
Short name T49
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.06 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:49:52 PM PDT 23
Peak memory 237756 kb
Host smart-0ba89a30-2c7c-4503-84b2-18c37b0a5e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77217773291856385183571768360119322496872009167818396631844384056315079216338 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_corrupt_sig_fatal_chk.772177732918563851835717683601193224968720091678183966318
44384056315079216338
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.103490724959518153742547032464380698129278079194832298915169506169278758130802
Short name T258
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.54 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:31 PM PDT 23
Peak memory 211788 kb
Host smart-8dbc8b7c-1a08-4458-8e62-0a6e1cc2477d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103490724959518153742547032464380698129278079194832298915169506169278758130802 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.rom_ctrl_kmac_err_chk.103490724959518153742547032464380698129278079194832298915169506169278758130802
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.94497737059088383841775192432567891646254495715080819295982942703993052080561
Short name T323
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.34 seconds
Started Nov 01 02:43:49 PM PDT 23
Finished Nov 01 02:44:02 PM PDT 23
Peak memory 211220 kb
Host smart-deeea161-1a9b-47cb-9b2e-700db3cf65cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94497737059088383841775192432567891646254495715080819295982942703993052080561 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.94497737059088383841775192432567891646254495715080819295982942703993052080561
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.93208764303654596797471754493437711663585752556768106546293710871535199467052
Short name T235
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.21 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 212800 kb
Host smart-1a878d39-51aa-422e-82a1-1627b6954516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93208764303654596797471754493437711663585752556768106546293710871535199467052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.rom_ctrl_smoke.93208764303654596797471754493437711663585752556768106546293710871535199467052
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.109644435389034114507940825108551414403894234100172644157463273765599920078474
Short name T303
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.49 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:45 PM PDT 23
Peak memory 212920 kb
Host smart-f3f1fed7-1674-46fc-8280-1d4416757a35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109644435389034114507940825108551414403894234100172644157463273
765599920078474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all.1096444353890341145079408251085514144038942341001
72644157463273765599920078474
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.95085879184743243941152471069596495027888232662783277248533855242515745229632
Short name T259
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:19 PM PDT 23
Peak memory 211232 kb
Host smart-3e315233-55ad-4563-aa56-e98643a5e6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95085879184743243941152471069596495027888232662783277248533855242515745229632 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.95085879184743243941152471069596495027888232662783277248533855242515745229632
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.5250854274748130078774253256966761334862150151967061601115877709035360238141
Short name T159
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.84 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:49:44 PM PDT 23
Peak memory 237608 kb
Host smart-a3ec9fe8-05c1-492f-9b08-0b520ec4d6fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5250854274748130078774253256966761334862150151967061601115877709035360238141 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_corrupt_sig_fatal_chk.5250854274748130078774253256966761334862150151967061601115
877709035360238141
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.98256295598260734695788351395540571521512532033776481698586717575134883800450
Short name T202
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.79 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:31 PM PDT 23
Peak memory 211540 kb
Host smart-adcbac80-02d6-4537-a4d6-3c32fd2e8665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98256295598260734695788351395540571521512532033776481698586717575134883800450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.rom_ctrl_kmac_err_chk.98256295598260734695788351395540571521512532033776481698586717575134883800450
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.76956511081819912812223786716901706888548656537613826262261376781110595347434
Short name T11
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.16 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:21 PM PDT 23
Peak memory 211188 kb
Host smart-ba830e91-5fb2-450e-abf3-c37a947aca38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76956511081819912812223786716901706888548656537613826262261376781110595347434 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.76956511081819912812223786716901706888548656537613826262261376781110595347434
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.58366490507519861187680783467151463780004290565040247539059377537084349029971
Short name T115
Test name
Test status
Simulation time 6265461576 ps
CPU time 29.02 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 212868 kb
Host smart-dd57475e-4581-478e-9086-68bc26a282b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58366490507519861187680783467151463780004290565040247539059377537084349029971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.rom_ctrl_smoke.58366490507519861187680783467151463780004290565040247539059377537084349029971
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.41189211784213933355104619233807642930447723958814621619115650036296032332666
Short name T254
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.23 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:43 PM PDT 23
Peak memory 212996 kb
Host smart-87e16704-2497-4edd-9ce9-1ea7a59c46fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411892117842139333551046192338076429304477239588146216191156500
36296032332666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all.41189211784213933355104619233807642930447723958814
621619115650036296032332666
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.83525647000146627770009996572600370625820114062247650622651723186771851301954
Short name T317
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.29 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211212 kb
Host smart-6f945801-9ef5-4c31-a18c-acdc234b8992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83525647000146627770009996572600370625820114062247650622651723186771851301954 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.83525647000146627770009996572600370625820114062247650622651723186771851301954
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.46746174878338314344144222722682620648639567149003021026630924638844595244269
Short name T360
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.27 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:49:50 PM PDT 23
Peak memory 237644 kb
Host smart-4230f408-a9db-4414-867e-e4c4df036e4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46746174878338314344144222722682620648639567149003021026630924638844595244269 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_corrupt_sig_fatal_chk.467461748783383143441442227226826206486395671490030210266
30924638844595244269
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.69327391057620375852701907408273697548323295745271454132392659345825527135374
Short name T14
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.87 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211668 kb
Host smart-193b20aa-01c6-4cad-8460-05c7fe0e74e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69327391057620375852701907408273697548323295745271454132392659345825527135374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.rom_ctrl_kmac_err_chk.69327391057620375852701907408273697548323295745271454132392659345825527135374
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.22993947367515034337598415818285497586700878184090759048560257529641519107636
Short name T125
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.53 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 211228 kb
Host smart-d8e0938d-fd26-4032-aba0-1c1e85cea6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22993947367515034337598415818285497586700878184090759048560257529641519107636 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.22993947367515034337598415818285497586700878184090759048560257529641519107636
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.78780839416615471443560638642926801629535563324608172055460700081266509820697
Short name T156
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.55 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 212824 kb
Host smart-b5788ca2-961f-4a6e-b6ca-9b966b021a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78780839416615471443560638642926801629535563324608172055460700081266509820697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.rom_ctrl_smoke.78780839416615471443560638642926801629535563324608172055460700081266509820697
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.61318815890262664708921332535649650926370766516814556785634848421764202702254
Short name T197
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.33 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 212896 kb
Host smart-124fcd24-ae26-4163-a9b6-c5659ff4e7bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613188158902626647089213325356496509263707665168145567856348484
21764202702254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all.61318815890262664708921332535649650926370766516814
556785634848421764202702254
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.113570080929328761520292145273897542172962462923767973091422843581123047537041
Short name T219
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.18 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:24 PM PDT 23
Peak memory 211152 kb
Host smart-f68c0e75-9024-4e51-b21d-5167a66c80e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113570080929328761520292145273897542172962462923767973091422843581123047537041 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.113570080929328761520292145273897542172962462923767973091422843581123047537041
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.99711405050477381357129720835191096449535173143354229737692696289083413001288
Short name T205
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.24 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:49:52 PM PDT 23
Peak memory 237864 kb
Host smart-31ed5c58-a17c-4e17-a213-a6a4ecb9ac20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99711405050477381357129720835191096449535173143354229737692696289083413001288 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_corrupt_sig_fatal_chk.997114050504773813571297208351910964495351731433542297376
92696289083413001288
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.88947450468630483698913423214265591993951401245824459170979916942824200584111
Short name T109
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.65 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:44:37 PM PDT 23
Peak memory 211456 kb
Host smart-21ac1a80-1766-4034-9956-f9fcf0c090b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88947450468630483698913423214265591993951401245824459170979916942824200584111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.rom_ctrl_kmac_err_chk.88947450468630483698913423214265591993951401245824459170979916942824200584111
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.37535630756375591438316574807253980566471406661367965629522435654338825750004
Short name T207
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.1 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211224 kb
Host smart-9aed415d-0f22-4883-9992-5b200e6ef71f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37535630756375591438316574807253980566471406661367965629522435654338825750004 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.37535630756375591438316574807253980566471406661367965629522435654338825750004
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.19211166398618408046344498422682229201045651071186661267942866129724269603365
Short name T1
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.15 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:38 PM PDT 23
Peak memory 212992 kb
Host smart-1996141e-11d5-4cd5-9e5f-9add85a9610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19211166398618408046344498422682229201045651071186661267942866129724269603365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.rom_ctrl_smoke.19211166398618408046344498422682229201045651071186661267942866129724269603365
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.93144019394666969986821410023771090185042206587645007014550784835668253188362
Short name T192
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.5 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 212972 kb
Host smart-49f53bf7-9a5e-47c7-b8bb-23c552728a14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931440193946669699868214100237710901850422065876450070145507848
35668253188362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all.93144019394666969986821410023771090185042206587645
007014550784835668253188362
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.104324156079923713812698115711032294156149989792093183332621315309897614641672
Short name T135
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.54 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:42 PM PDT 23
Peak memory 211224 kb
Host smart-36dec3d0-4615-4543-a68d-2aecbbeb64b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104324156079923713812698115711032294156149989792093183332621315309897614641672 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.104324156079923713812698115711032294156149989792093183332621315309897614641672
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.6502490693126597610457433509643088950284814791714533147674692123913156937900
Short name T183
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.43 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:49:29 PM PDT 23
Peak memory 237672 kb
Host smart-1ba4f799-b517-4656-b5ab-1056daf4d35f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6502490693126597610457433509643088950284814791714533147674692123913156937900 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_corrupt_sig_fatal_chk.65024906931265976104574335096430889502848147917145331476746
92123913156937900
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.106313338505507684109712409252411879031858139317923332310227760220030657795179
Short name T153
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.73 seconds
Started Nov 01 02:43:27 PM PDT 23
Finished Nov 01 02:43:55 PM PDT 23
Peak memory 211640 kb
Host smart-dbbb01d9-0c27-4b93-bbc1-7edfb07e16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106313338505507684109712409252411879031858139317923332310227760220030657795179 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.rom_ctrl_kmac_err_chk.106313338505507684109712409252411879031858139317923332310227760220030657795179
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.83969698892464536463244534945786341967168641539127087876765055190804553678842
Short name T306
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.55 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 211268 kb
Host smart-db46d0b5-9810-445b-859c-8ae26f478758
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83969698892464536463244534945786341967168641539127087876765055190804553678842 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.83969698892464536463244534945786341967168641539127087876765055190804553678842
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.95446133573986668346260569540737830594962251244203814549174437111405390231308
Short name T27
Test name
Test status
Simulation time 3444857586 ps
CPU time 117.75 seconds
Started Nov 01 02:44:00 PM PDT 23
Finished Nov 01 02:46:00 PM PDT 23
Peak memory 236876 kb
Host smart-69662e33-b5fc-481b-b8f4-0c52cc1f4e94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95446133573986668346260569540737830594962251244203814549174437111405390231308 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.95446133573986668346260569540737830594962251244203814549174437111405390231308
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.73015267059657391127358334368872115853703425491651965178984996441266368613345
Short name T113
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.95 seconds
Started Nov 01 02:43:54 PM PDT 23
Finished Nov 01 02:44:24 PM PDT 23
Peak memory 212832 kb
Host smart-d12c5b49-2567-4c94-8fd9-402d8bb239d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73015267059657391127358334368872115853703425491651965178984996441266368613345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.rom_ctrl_smoke.73015267059657391127358334368872115853703425491651965178984996441266368613345
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.114442573628748523913653417277808199370812122680133883074786183528266205228388
Short name T275
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.16 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 212924 kb
Host smart-7cd67d02-3a0e-492d-ac6f-5b18526494d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114442573628748523913653417277808199370812122680133883074786183
528266205228388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all.11444257362874852391365341727780819937081212268013
3883074786183528266205228388
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.77516559375849901929740562222846668153849771264543234999370933191870765398196
Short name T340
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.44 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:16 PM PDT 23
Peak memory 211324 kb
Host smart-4c55ce0d-97d6-498e-9e81-03a4ab695e72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77516559375849901929740562222846668153849771264543234999370933191870765398196 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.77516559375849901929740562222846668153849771264543234999370933191870765398196
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.49138316516096233541869154275897350914322229571151267332080422572379515713982
Short name T188
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.96 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:49:47 PM PDT 23
Peak memory 237712 kb
Host smart-b1d37f39-4ee2-424f-b86b-76e26c1bb04b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49138316516096233541869154275897350914322229571151267332080422572379515713982 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_corrupt_sig_fatal_chk.491383165160962335418691542758973509143222295711512673320
80422572379515713982
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.110156224424814665172476761857467878217341260820606677679612828204216771187177
Short name T122
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.52 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:30 PM PDT 23
Peak memory 211680 kb
Host smart-119038df-7753-4154-9198-07a945dfdba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110156224424814665172476761857467878217341260820606677679612828204216771187177 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.rom_ctrl_kmac_err_chk.110156224424814665172476761857467878217341260820606677679612828204216771187177
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.57873562520193599265346365322629850917762241014040405708627433318207154919663
Short name T359
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.06 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 211200 kb
Host smart-9ffc0e14-f3d0-413f-92e4-f0892102848a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57873562520193599265346365322629850917762241014040405708627433318207154919663 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.57873562520193599265346365322629850917762241014040405708627433318207154919663
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.55314866182253026665761170344990818769135061514991949986296278177824343750691
Short name T288
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.19 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:32 PM PDT 23
Peak memory 212904 kb
Host smart-280fc76f-82a8-4ede-8eaa-3693a663d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55314866182253026665761170344990818769135061514991949986296278177824343750691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.rom_ctrl_smoke.55314866182253026665761170344990818769135061514991949986296278177824343750691
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.104745817434178514786504517212159596530510866977421502895153930825021355004016
Short name T301
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.61 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:55 PM PDT 23
Peak memory 212928 kb
Host smart-85f96722-c377-4468-b5bb-913335a2d0e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104745817434178514786504517212159596530510866977421502895153930
825021355004016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all.1047458174341785147865045172121595965305108669774
21502895153930825021355004016
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.99548214417683229409698605500012815927466619912408213455347894793635814369139
Short name T266
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.26 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:30 PM PDT 23
Peak memory 211148 kb
Host smart-a5f2d49a-e352-48ac-a5b5-e8ed9d273f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99548214417683229409698605500012815927466619912408213455347894793635814369139 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.99548214417683229409698605500012815927466619912408213455347894793635814369139
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.8401324667225705704191512053584209053739074442166575906489745283022146769203
Short name T354
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.17 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:49:50 PM PDT 23
Peak memory 237748 kb
Host smart-0fbc44b5-40c6-4f17-94a6-3bf1d5ceb28f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8401324667225705704191512053584209053739074442166575906489745283022146769203 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_corrupt_sig_fatal_chk.8401324667225705704191512053584209053739074442166575906489
745283022146769203
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.47671997408207817484805788912062784066558855692868343025177601069567851904698
Short name T132
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.42 seconds
Started Nov 01 02:44:23 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 211672 kb
Host smart-53155af7-aeb0-45ad-a906-3fa5c403d0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47671997408207817484805788912062784066558855692868343025177601069567851904698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.rom_ctrl_kmac_err_chk.47671997408207817484805788912062784066558855692868343025177601069567851904698
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.45281746882948312065287668838156959177138410672705983630020853080441770062357
Short name T225
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:26 PM PDT 23
Peak memory 211200 kb
Host smart-bcad99df-4da8-40e8-80b5-2287cdabb698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45281746882948312065287668838156959177138410672705983630020853080441770062357 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.45281746882948312065287668838156959177138410672705983630020853080441770062357
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.12624823545985943601518555767874866970567678522244082704046729768440918363379
Short name T203
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.1 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:40 PM PDT 23
Peak memory 212844 kb
Host smart-75df7de4-39df-4b5a-9aed-41dd41a049b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12624823545985943601518555767874866970567678522244082704046729768440918363379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.rom_ctrl_smoke.12624823545985943601518555767874866970567678522244082704046729768440918363379
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.32541218436079803395172737705079156655451949808183870845882233999419545057741
Short name T291
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.47 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 212972 kb
Host smart-1aa82e34-90a2-4da0-8f00-aa6fbe919c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325412184360798033951727377050791566554519498081838708458822339
99419545057741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all.32541218436079803395172737705079156655451949808183
870845882233999419545057741
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.67387118510343773443221434231182515154976722522970480826759250479263002576156
Short name T37
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:31 PM PDT 23
Peak memory 211312 kb
Host smart-a15bc5f9-3613-4fc1-b880-03bd7dd1bf9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67387118510343773443221434231182515154976722522970480826759250479263002576156 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.67387118510343773443221434231182515154976722522970480826759250479263002576156
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.55822451898983278693392549483973797307422951836627866331349219147244053666711
Short name T260
Test name
Test status
Simulation time 69854280986 ps
CPU time 328.76 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:49:46 PM PDT 23
Peak memory 237616 kb
Host smart-18f3f48d-522d-4ccd-81f4-a12961f46a09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55822451898983278693392549483973797307422951836627866331349219147244053666711 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_corrupt_sig_fatal_chk.558224518989832786933925494839737973074229518366278663313
49219147244053666711
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.71508912272355264260631328942248993557326090113235597555390771671267825304896
Short name T264
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.5 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:44:44 PM PDT 23
Peak memory 211640 kb
Host smart-72b1b634-8832-4f91-bddf-ffabb195efee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71508912272355264260631328942248993557326090113235597555390771671267825304896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.rom_ctrl_kmac_err_chk.71508912272355264260631328942248993557326090113235597555390771671267825304896
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.85370790905627452168842238059310999259966178997736565611103494316271883524187
Short name T336
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.28 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 211172 kb
Host smart-74c10065-1961-4d8b-a6ca-ce4adab12c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=85370790905627452168842238059310999259966178997736565611103494316271883524187 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.85370790905627452168842238059310999259966178997736565611103494316271883524187
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.112917371748443915755200275559476629522285798683590433683011586727698846405470
Short name T138
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.69 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:44:51 PM PDT 23
Peak memory 212888 kb
Host smart-73fcd1f6-039f-42b9-894f-8a1d63c319dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112917371748443915755200275559476629522285798683590433683011586727698846405470 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.rom_ctrl_smoke.112917371748443915755200275559476629522285798683590433683011586727698846405470
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.51510450355919467816197371327406987059988070055197115651706893791048111767159
Short name T289
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.48 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212980 kb
Host smart-32b6f8c3-f01f-417b-bdb4-1ea44ed5bdc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515104503559194678161973713274069870599880700551971156517068937
91048111767159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all.51510450355919467816197371327406987059988070055197
115651706893791048111767159
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.24945851785235745344767134272839708638128869491053410001528895319848021513022
Short name T249
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.42 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:30 PM PDT 23
Peak memory 211232 kb
Host smart-587be796-51eb-4c5b-89fe-69833f0e7390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945851785235745344767134272839708638128869491053410001528895319848021513022 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.24945851785235745344767134272839708638128869491053410001528895319848021513022
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.66784561779181395036626520413721157071733901425458196474862183532872863253352
Short name T51
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.88 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:49:51 PM PDT 23
Peak memory 237704 kb
Host smart-476caf21-70b5-483a-8040-762fee3c3d74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66784561779181395036626520413721157071733901425458196474862183532872863253352 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_corrupt_sig_fatal_chk.667845617791813950366265204137211570717339014254581964748
62183532872863253352
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.31541746687543020924780939994955675496715118222842496589264555473370112397963
Short name T295
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.4 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:44 PM PDT 23
Peak memory 211768 kb
Host smart-3a09311b-4291-482b-a3aa-a912aeed332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31541746687543020924780939994955675496715118222842496589264555473370112397963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.rom_ctrl_kmac_err_chk.31541746687543020924780939994955675496715118222842496589264555473370112397963
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.54174049267624135847443170690453251728732262313351396813936422355487103655807
Short name T158
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:32 PM PDT 23
Peak memory 211220 kb
Host smart-9d39f709-ec55-4c8c-8e5a-6d3b0a46568b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54174049267624135847443170690453251728732262313351396813936422355487103655807 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.54174049267624135847443170690453251728732262313351396813936422355487103655807
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.63516595274066345941279478935961977386043493265333647269446216673599404204901
Short name T263
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.87 seconds
Started Nov 01 02:44:23 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 212940 kb
Host smart-5e651240-ef65-4663-a6d7-916922e839e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63516595274066345941279478935961977386043493265333647269446216673599404204901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.rom_ctrl_smoke.63516595274066345941279478935961977386043493265333647269446216673599404204901
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.13133191397880474500629840076594905434977857548096517592886348754055354410189
Short name T322
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.38 seconds
Started Nov 01 02:44:23 PM PDT 23
Finished Nov 01 02:45:07 PM PDT 23
Peak memory 212896 kb
Host smart-4e12e3de-15b5-40e8-9af8-b79ed8f37265
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131331913978804745006298400765949054349778575480965175928863487
54055354410189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all.13133191397880474500629840076594905434977857548096
517592886348754055354410189
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.106046659942920885324464923829798563502896481068012399275919299083842066077864
Short name T127
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.58 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:44:32 PM PDT 23
Peak memory 211172 kb
Host smart-464d54b0-e65d-4e7d-b2dc-af64e851e1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106046659942920885324464923829798563502896481068012399275919299083842066077864 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.106046659942920885324464923829798563502896481068012399275919299083842066077864
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.11670770331592773767363183051958876052711027185037600040164093966637379172332
Short name T36
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.15 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:50:01 PM PDT 23
Peak memory 237744 kb
Host smart-ac0116f8-4181-491c-953d-24590897e162
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670770331592773767363183051958876052711027185037600040164093966637379172332 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_corrupt_sig_fatal_chk.116707703315927737673631830519588760527110271850376000401
64093966637379172332
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.35845546910492744244517937135514100566780759265687874305784818004462762794977
Short name T131
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.42 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 211612 kb
Host smart-834ec2fa-084a-4521-ae04-2f96d9102465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35845546910492744244517937135514100566780759265687874305784818004462762794977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.rom_ctrl_kmac_err_chk.35845546910492744244517937135514100566780759265687874305784818004462762794977
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.10273669927087052005753349080352152250991768135135255553807379233685887642304
Short name T315
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.6 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211192 kb
Host smart-2ad10176-ed69-46e2-89c4-bf21f8683e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10273669927087052005753349080352152250991768135135255553807379233685887642304 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.10273669927087052005753349080352152250991768135135255553807379233685887642304
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.37700882697798541195493413502643374139338400181440959669993134549950077267824
Short name T184
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.67 seconds
Started Nov 01 02:44:21 PM PDT 23
Finished Nov 01 02:44:52 PM PDT 23
Peak memory 212948 kb
Host smart-f46fdfdd-2bbb-4ce7-a137-315a07131c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37700882697798541195493413502643374139338400181440959669993134549950077267824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.rom_ctrl_smoke.37700882697798541195493413502643374139338400181440959669993134549950077267824
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.20528356567323161822316288447700249102857388822907333909406338708410709231638
Short name T155
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.79 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212804 kb
Host smart-a9876430-6ab2-436f-9ee6-c286052eebf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205283565673231618223162884477002491028573888229073339094063387
08410709231638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all.20528356567323161822316288447700249102857388822907
333909406338708410709231638
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.35583383829082560400097453799438058759689850103738102293293127245842219649724
Short name T255
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:44:31 PM PDT 23
Peak memory 211212 kb
Host smart-faceb7e9-9ee2-4158-9933-69d3144c3bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35583383829082560400097453799438058759689850103738102293293127245842219649724 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.35583383829082560400097453799438058759689850103738102293293127245842219649724
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.63852755329587355941154855061514294259012936673955944437671738186227620226501
Short name T248
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.52 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:50:06 PM PDT 23
Peak memory 237724 kb
Host smart-d6525978-5b85-402c-8dc4-d0caf1812c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63852755329587355941154855061514294259012936673955944437671738186227620226501 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_corrupt_sig_fatal_chk.638527553295873559411548550615142942590129366739559444376
71738186227620226501
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.105414235734852075504344264013270784168481684775458066445602063630946937370116
Short name T280
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.42 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:44:48 PM PDT 23
Peak memory 211660 kb
Host smart-953b47a2-00c4-4fd4-a637-b7c2ce5b54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105414235734852075504344264013270784168481684775458066445602063630946937370116 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.rom_ctrl_kmac_err_chk.105414235734852075504344264013270784168481684775458066445602063630946937370116
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.78366441396646914113941283779116361315020461420897488699634976951211972234495
Short name T309
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.24 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211184 kb
Host smart-7b00f618-0613-4a24-b610-d8d540254f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78366441396646914113941283779116361315020461420897488699634976951211972234495 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.78366441396646914113941283779116361315020461420897488699634976951211972234495
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.104590575406255125637832768210416691700884017728276811527232270333771519875770
Short name T177
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.51 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 212920 kb
Host smart-322e8f61-e1a2-44fd-a1cf-70c7b3437b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104590575406255125637832768210416691700884017728276811527232270333771519875770 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.rom_ctrl_smoke.104590575406255125637832768210416691700884017728276811527232270333771519875770
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.23706429434351453300920564940382683367257470211734527538853374067225789624417
Short name T358
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.73 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:45:01 PM PDT 23
Peak memory 212928 kb
Host smart-c1743c29-b296-4ddf-a84d-9b97e8d4e195
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237064294343514533009205649403826833672574702117345275388533740
67225789624417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all.23706429434351453300920564940382683367257470211734
527538853374067225789624417
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.43964377951345735598154204808821248296641105639917647279871429294740019163839
Short name T238
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.22 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:32 PM PDT 23
Peak memory 211220 kb
Host smart-ac7138ed-3caa-40a1-a5a1-52e7f064bc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43964377951345735598154204808821248296641105639917647279871429294740019163839 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.43964377951345735598154204808821248296641105639917647279871429294740019163839
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.55967778037842754126331026308249498322690446832667625152755710996582516002412
Short name T10
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.08 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:49:53 PM PDT 23
Peak memory 237852 kb
Host smart-0988e178-9907-4467-84e4-91057b7e10f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55967778037842754126331026308249498322690446832667625152755710996582516002412 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_corrupt_sig_fatal_chk.559677780378427541263310263082494983226904468326676251527
55710996582516002412
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.47262213085731787954059806437626283731165178224038497246771097927732431341181
Short name T343
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.47 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:44:52 PM PDT 23
Peak memory 211472 kb
Host smart-c9cca6c8-5f82-4eef-858a-c25e3df82c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47262213085731787954059806437626283731165178224038497246771097927732431341181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.rom_ctrl_kmac_err_chk.47262213085731787954059806437626283731165178224038497246771097927732431341181
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.72095154983095458724314194737977861671272603161509541654453629179798083128507
Short name T347
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.17 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 211236 kb
Host smart-59f14aaa-a2ce-47eb-8c42-b87dd2848875
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72095154983095458724314194737977861671272603161509541654453629179798083128507 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.72095154983095458724314194737977861671272603161509541654453629179798083128507
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.68671233214634112902950364372248370187648260991852680497601772948982789560296
Short name T121
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.68 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 212872 kb
Host smart-74d04a74-b561-48e1-98e4-d9318c5846d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68671233214634112902950364372248370187648260991852680497601772948982789560296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.rom_ctrl_smoke.68671233214634112902950364372248370187648260991852680497601772948982789560296
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4176251179171034098079291902466265909031635972247012412401247965787815865563
Short name T174
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.74 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:45:01 PM PDT 23
Peak memory 212980 kb
Host smart-bdc1a6e4-e0ee-4fe3-9b17-0857fb54ffca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417625117917103409807929190246626590903163597224701241240124796
5787815865563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all.417625117917103409807929190246626590903163597224701
2412401247965787815865563
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.44650662574436616490153697455824514169214769385724790892357843229181277574855
Short name T267
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.46 seconds
Started Nov 01 02:44:22 PM PDT 23
Finished Nov 01 02:44:36 PM PDT 23
Peak memory 211292 kb
Host smart-955ad8a8-e5aa-47be-85ba-ab2c94eeffb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44650662574436616490153697455824514169214769385724790892357843229181277574855 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.44650662574436616490153697455824514169214769385724790892357843229181277574855
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.20595372219573062493956022769285045970834313856124598182815343415819743788291
Short name T338
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.79 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:50:03 PM PDT 23
Peak memory 237704 kb
Host smart-d98fcdc6-93b7-403d-8a70-39eec3d3127e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20595372219573062493956022769285045970834313856124598182815343415819743788291 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_corrupt_sig_fatal_chk.205953722195730624939560227692850459708343138561245981828
15343415819743788291
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.26809838880868461651569488028500395356388044570530945175931784581095301791758
Short name T185
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.94 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 211448 kb
Host smart-9250cd1c-6903-4233-b091-589e664dc964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26809838880868461651569488028500395356388044570530945175931784581095301791758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.rom_ctrl_kmac_err_chk.26809838880868461651569488028500395356388044570530945175931784581095301791758
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.20863108522001642966165919011763008660163057858173983885729940359541241059018
Short name T178
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.51 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 211360 kb
Host smart-b92f1ecc-81a8-4028-be8d-2e415ae191af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20863108522001642966165919011763008660163057858173983885729940359541241059018 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.20863108522001642966165919011763008660163057858173983885729940359541241059018
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.38287098643577074081408292094997075227763774197179319395773948583951119317766
Short name T199
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.68 seconds
Started Nov 01 02:44:17 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 212760 kb
Host smart-47fee10a-e949-4ef8-bad4-aab19a7db998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38287098643577074081408292094997075227763774197179319395773948583951119317766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.rom_ctrl_smoke.38287098643577074081408292094997075227763774197179319395773948583951119317766
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.68327715291618295466029425656384587377495050511107152734805436995113734665321
Short name T227
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.65 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 212900 kb
Host smart-56f37ad5-f176-49cc-aa91-36a0f4930630
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683277152916182954660294256563845873774950505111071527348054369
95113734665321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all.68327715291618295466029425656384587377495050511107
152734805436995113734665321
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.31563752661767111821683526426503763248594846902532588875274012203918253302022
Short name T144
Test name
Test status
Simulation time 3124113076 ps
CPU time 12 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 210868 kb
Host smart-d8bf8ee0-1e43-4c7a-80bb-43cfd2f6239d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31563752661767111821683526426503763248594846902532588875274012203918253302022 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.31563752661767111821683526426503763248594846902532588875274012203918253302022
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.12075016882412204757282718235954076956629055117542262219119603541410132204792
Short name T216
Test name
Test status
Simulation time 69854280986 ps
CPU time 339.62 seconds
Started Nov 01 02:44:18 PM PDT 23
Finished Nov 01 02:49:58 PM PDT 23
Peak memory 237660 kb
Host smart-1e66c4fb-a0b0-4dca-a564-0203ebba7fdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12075016882412204757282718235954076956629055117542262219119603541410132204792 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_corrupt_sig_fatal_chk.120750168824122047572827182359540769566290551175422622191
19603541410132204792
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.7467828216070189118630362306094091847197538289877743305301391032736585260903
Short name T145
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.91 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:00 PM PDT 23
Peak memory 211444 kb
Host smart-8c636d71-d524-4594-97da-6ca4d844d1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7467828216070189118630362306094091847197538289877743305301391032736585260903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.rom_ctrl_kmac_err_chk.7467828216070189118630362306094091847197538289877743305301391032736585260903
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.75603109252723167047841571233268226224552542375138352283959384048962869647907
Short name T105
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.11 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211360 kb
Host smart-fc886806-2996-4cd7-ad17-d5ea30674d7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75603109252723167047841571233268226224552542375138352283959384048962869647907 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.75603109252723167047841571233268226224552542375138352283959384048962869647907
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.68982520741070345433291431028903851009355413552357113011725192914610569059398
Short name T165
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.49 seconds
Started Nov 01 02:44:24 PM PDT 23
Finished Nov 01 02:44:54 PM PDT 23
Peak memory 212880 kb
Host smart-d6552cda-09f3-41b1-b911-8a7a2f6dae4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68982520741070345433291431028903851009355413552357113011725192914610569059398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.rom_ctrl_smoke.68982520741070345433291431028903851009355413552357113011725192914610569059398
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.48979407306527244001951656304231474919860020604841872416540493996177119577037
Short name T325
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.2 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:45:09 PM PDT 23
Peak memory 212988 kb
Host smart-63333673-25ff-4c71-aaeb-c5f856e54c14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489794073065272440019516563042314749198600206048418724165404939
96177119577037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all.48979407306527244001951656304231474919860020604841
872416540493996177119577037
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.37997944629231430317811595046934037269293413682743920356341606420703859256303
Short name T189
Test name
Test status
Simulation time 3124113076 ps
CPU time 11.88 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 211032 kb
Host smart-11d63e0e-4bc2-4ca2-8add-a3b5f6b27882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37997944629231430317811595046934037269293413682743920356341606420703859256303 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.37997944629231430317811595046934037269293413682743920356341606420703859256303
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.4857792600513910162328186332675548057268462208635480249158886197097574115471
Short name T172
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.07 seconds
Started Nov 01 02:44:21 PM PDT 23
Finished Nov 01 02:50:01 PM PDT 23
Peak memory 237776 kb
Host smart-2de06322-76e9-4d82-a5c9-28e93fbccdfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4857792600513910162328186332675548057268462208635480249158886197097574115471 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_corrupt_sig_fatal_chk.4857792600513910162328186332675548057268462208635480249158
886197097574115471
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.86459426947214584181875433432067292797400091036609058638739158945171136587465
Short name T195
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.65 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 211620 kb
Host smart-57f5a2ed-f3bb-4082-97e0-f1707c60643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86459426947214584181875433432067292797400091036609058638739158945171136587465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.rom_ctrl_kmac_err_chk.86459426947214584181875433432067292797400091036609058638739158945171136587465
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.44817757842443471359879200129756784619721060490674967107179243346407466163023
Short name T6
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.37 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 211156 kb
Host smart-6e052abf-2255-4d21-85a6-fda55b405ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44817757842443471359879200129756784619721060490674967107179243346407466163023 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.44817757842443471359879200129756784619721060490674967107179243346407466163023
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.50903464158339964834267807004817525526663454477498443289386916822581790906256
Short name T302
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.34 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:44:55 PM PDT 23
Peak memory 212856 kb
Host smart-aa4acc86-884c-44a7-9c57-f4ffcf8e39ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50903464158339964834267807004817525526663454477498443289386916822581790906256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.rom_ctrl_smoke.50903464158339964834267807004817525526663454477498443289386916822581790906256
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.60581448731033604380219199550027359270423656526715584789655143273064665998227
Short name T252
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.72 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:17 PM PDT 23
Peak memory 212912 kb
Host smart-28b93bc5-9d80-4edb-ac80-4f1c06db1d6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605814487310336043802191995500273592704236565267155847896551432
73064665998227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all.60581448731033604380219199550027359270423656526715
584789655143273064665998227
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.36868042369229763436340412496415744531715790500532629344236397340183965093355
Short name T128
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.47 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:44 PM PDT 23
Peak memory 211224 kb
Host smart-41518679-f5ab-4455-b6ca-0958874c31ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36868042369229763436340412496415744531715790500532629344236397340183965093355 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.36868042369229763436340412496415744531715790500532629344236397340183965093355
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.49954041675428078148333588340573463294836350127170748248487077069463031550552
Short name T232
Test name
Test status
Simulation time 69854280986 ps
CPU time 345.9 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:49:17 PM PDT 23
Peak memory 237584 kb
Host smart-b3f4f9fd-e8ac-4fb5-b9fe-c8079131a119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49954041675428078148333588340573463294836350127170748248487077069463031550552 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_corrupt_sig_fatal_chk.4995404167542807814833358834057346329483635012717074824848
7077069463031550552
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.10909185267669976800330415312720377310578481736705160338814346251780863154216
Short name T175
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:57 PM PDT 23
Peak memory 211616 kb
Host smart-3f6ead91-c068-4059-a58e-027efd400b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10909185267669976800330415312720377310578481736705160338814346251780863154216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.rom_ctrl_kmac_err_chk.10909185267669976800330415312720377310578481736705160338814346251780863154216
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3488233217031849173092780929191487024805816035587686396937375169136537938867
Short name T257
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.57 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:45 PM PDT 23
Peak memory 211052 kb
Host smart-441bed53-d83c-41e2-8ad2-240d9116fe1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3488233217031849173092780929191487024805816035587686396937375169136537938867 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3488233217031849173092780929191487024805816035587686396937375169136537938867
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.76660816477164977717053433682607972111227117395891593109194481980834615552046
Short name T26
Test name
Test status
Simulation time 3444857586 ps
CPU time 114.26 seconds
Started Nov 01 02:43:31 PM PDT 23
Finished Nov 01 02:45:26 PM PDT 23
Peak memory 236756 kb
Host smart-f9ba9311-c5bf-4f58-922d-19bf538d6dbd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76660816477164977717053433682607972111227117395891593109194481980834615552046 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.76660816477164977717053433682607972111227117395891593109194481980834615552046
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.24366932643868289618803053331742204160527532162994790022871472730464849243198
Short name T206
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.61 seconds
Started Nov 01 02:43:26 PM PDT 23
Finished Nov 01 02:43:56 PM PDT 23
Peak memory 212884 kb
Host smart-89e49722-1a4f-4f34-92e7-e8c998bb9604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24366932643868289618803053331742204160527532162994790022871472730464849243198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.rom_ctrl_smoke.24366932643868289618803053331742204160527532162994790022871472730464849243198
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.73494883917354836530153320804895033994552711868674826889172349491692351679125
Short name T210
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.41 seconds
Started Nov 01 02:43:55 PM PDT 23
Finished Nov 01 02:44:38 PM PDT 23
Peak memory 213044 kb
Host smart-654c5a13-29ee-4bcb-bb9a-4ec453359979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734948839173548365301533208048950339945527118686748268891723494
91692351679125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all.734948839173548365301533208048950339945527118686748
26889172349491692351679125
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.27294888962563515065086422177120362701695205302410021336914181943552600937959
Short name T362
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.59 seconds
Started Nov 01 02:44:25 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 211220 kb
Host smart-3104efd3-e678-4126-b3ca-a2ed035a4f3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27294888962563515065086422177120362701695205302410021336914181943552600937959 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.27294888962563515065086422177120362701695205302410021336914181943552600937959
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.71311564832941373464714687976143072462928557015457935523012053317749185265272
Short name T143
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.15 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:50:08 PM PDT 23
Peak memory 237744 kb
Host smart-792062ec-20ed-425f-8d6b-ba4d798a7c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71311564832941373464714687976143072462928557015457935523012053317749185265272 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_corrupt_sig_fatal_chk.713115648329413734647146879761430724629285570154579355230
12053317749185265272
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.113195195242120031789796675233548760548073120633230426801341936489045884212753
Short name T294
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.66 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:44:53 PM PDT 23
Peak memory 211676 kb
Host smart-0b0108be-0b90-481c-961a-4a65c4811f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113195195242120031789796675233548760548073120633230426801341936489045884212753 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.rom_ctrl_kmac_err_chk.113195195242120031789796675233548760548073120633230426801341936489045884212753
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.115546660895331448070617519929276852110855731895429082851021809297752835130570
Short name T278
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.84 seconds
Started Nov 01 02:44:32 PM PDT 23
Finished Nov 01 02:44:48 PM PDT 23
Peak memory 211028 kb
Host smart-05ce7a6b-72b6-4e6d-b60e-893c9786dd7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115546660895331448070617519929276852110855731895429082851021809297752835130570 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.115546660895331448070617519929276852110855731895429082851021809297752835130570
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.106303677871630240433834933384469184606730586211768544656489978229500697029834
Short name T173
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.29 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 212900 kb
Host smart-13cac786-3f3c-448f-8232-88e02c8f2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106303677871630240433834933384469184606730586211768544656489978229500697029834 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.rom_ctrl_smoke.106303677871630240433834933384469184606730586211768544656489978229500697029834
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.99459685513006733491679242904726231634402013341873482664811445993888105626985
Short name T186
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.87 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 212792 kb
Host smart-d20ed255-946d-4bdc-bdb5-dd36883e801a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994596855130067334916792429047262316344020133418734826648114459
93888105626985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all.99459685513006733491679242904726231634402013341873
482664811445993888105626985
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.72984606703798692320168357278827138234180738359793875030232435533524403511278
Short name T250
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.35 seconds
Started Nov 01 02:44:27 PM PDT 23
Finished Nov 01 02:44:43 PM PDT 23
Peak memory 211248 kb
Host smart-2a3e1d04-d06e-49c1-8537-fbc60ea42553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72984606703798692320168357278827138234180738359793875030232435533524403511278 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.72984606703798692320168357278827138234180738359793875030232435533524403511278
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.42655089770748771531881308900042712933845584328582944186957903243854091281406
Short name T141
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.86 seconds
Started Nov 01 02:44:27 PM PDT 23
Finished Nov 01 02:50:16 PM PDT 23
Peak memory 237780 kb
Host smart-eefb8bbe-6c2a-472a-a88b-5b3a44d553c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655089770748771531881308900042712933845584328582944186957903243854091281406 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_corrupt_sig_fatal_chk.426550897707487715318813089000427129338455843285829441869
57903243854091281406
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.108810996956932621908543477285115261566944549260424146272546276542541502347193
Short name T348
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.6 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 211624 kb
Host smart-bd07b9a8-b8ee-4732-9700-6cfc0529e1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108810996956932621908543477285115261566944549260424146272546276542541502347193 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.rom_ctrl_kmac_err_chk.108810996956932621908543477285115261566944549260424146272546276542541502347193
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.57819085868600550322585716985140904074744950108247772488305014121793855691728
Short name T201
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 211240 kb
Host smart-00513304-4b06-4481-a787-e1ee96d231d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57819085868600550322585716985140904074744950108247772488305014121793855691728 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.57819085868600550322585716985140904074744950108247772488305014121793855691728
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.34649500667675335321494583704338282116312380872434277542031330391611496653907
Short name T292
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.48 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212816 kb
Host smart-6afa783e-8504-42c2-9d08-f476f8e82a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34649500667675335321494583704338282116312380872434277542031330391611496653907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.rom_ctrl_smoke.34649500667675335321494583704338282116312380872434277542031330391611496653907
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.66837335008979187126278558988463788101545983031751355775933918720394859745036
Short name T162
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.72 seconds
Started Nov 01 02:44:27 PM PDT 23
Finished Nov 01 02:45:15 PM PDT 23
Peak memory 213000 kb
Host smart-1cc0a5a0-ff26-4f49-98c3-7347974da428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668373350089791871262785589884637881015459830317513557759339187
20394859745036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all.66837335008979187126278558988463788101545983031751
355775933918720394859745036
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.49489532894302190381651203464130880750500322970879144653100377478986739099561
Short name T168
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Nov 01 02:44:22 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 211248 kb
Host smart-622f6698-ab27-4d2c-b744-7bfb4f03225b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49489532894302190381651203464130880750500322970879144653100377478986739099561 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.49489532894302190381651203464130880750500322970879144653100377478986739099561
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.59203287133424844275262822827733757357889799784283339682394532866779489736443
Short name T286
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.74 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:50:17 PM PDT 23
Peak memory 237744 kb
Host smart-ae803403-cea7-4cb8-9029-f9995c6b6248
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59203287133424844275262822827733757357889799784283339682394532866779489736443 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_corrupt_sig_fatal_chk.592032871334248442752628228277337573578897997842833396823
94532866779489736443
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.100461663017083911425971554673210345571547932273440056291208654548679306280849
Short name T331
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 211660 kb
Host smart-ade85678-828b-4f0e-9199-185cddb5edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100461663017083911425971554673210345571547932273440056291208654548679306280849 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.rom_ctrl_kmac_err_chk.100461663017083911425971554673210345571547932273440056291208654548679306280849
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.95194726630700836432917212109392626730095756865455899509723841959967267717820
Short name T40
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:44:48 PM PDT 23
Peak memory 211232 kb
Host smart-4f4a54aa-4b65-4e7b-bfda-7d6421c727c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=95194726630700836432917212109392626730095756865455899509723841959967267717820 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.95194726630700836432917212109392626730095756865455899509723841959967267717820
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.65062257914800938661875034909400797203697241003837134038746544394429522763703
Short name T218
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.18 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212628 kb
Host smart-74e868db-94fc-41dd-9290-3a786a06020a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65062257914800938661875034909400797203697241003837134038746544394429522763703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.rom_ctrl_smoke.65062257914800938661875034909400797203697241003837134038746544394429522763703
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.28584551731457473065031097531527764353203361302684698111223743770822343956239
Short name T226
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.39 seconds
Started Nov 01 02:44:28 PM PDT 23
Finished Nov 01 02:45:17 PM PDT 23
Peak memory 213012 kb
Host smart-018d6ef7-6bd0-4d18-b3d4-6f43dd824d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285845517314574730650310975315277643532033613026846981112237437
70822343956239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all.28584551731457473065031097531527764353203361302684
698111223743770822343956239
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.96319045606279295258736930715263932823473806273998614093578269631542928917218
Short name T346
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.52 seconds
Started Nov 01 02:44:53 PM PDT 23
Finished Nov 01 02:45:08 PM PDT 23
Peak memory 211212 kb
Host smart-4d175514-dbf3-4413-9817-6e15590ba0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96319045606279295258736930715263932823473806273998614093578269631542928917218 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.96319045606279295258736930715263932823473806273998614093578269631542928917218
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.72412663063280452774470604419002772159174977530768546657711817662515706298710
Short name T190
Test name
Test status
Simulation time 69854280986 ps
CPU time 331.35 seconds
Started Nov 01 02:44:42 PM PDT 23
Finished Nov 01 02:50:14 PM PDT 23
Peak memory 237804 kb
Host smart-f693d5be-daeb-4b34-a289-5dc18f845c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72412663063280452774470604419002772159174977530768546657711817662515706298710 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_corrupt_sig_fatal_chk.724126630632804527744706044190027721591749775307685466577
11817662515706298710
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.71502316053159528653977723501730352683624643286972673304580144567471843547927
Short name T330
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.27 seconds
Started Nov 01 02:44:22 PM PDT 23
Finished Nov 01 02:44:48 PM PDT 23
Peak memory 211476 kb
Host smart-2048cdbf-3b82-475b-bae9-2ba79fe238aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71502316053159528653977723501730352683624643286972673304580144567471843547927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.rom_ctrl_kmac_err_chk.71502316053159528653977723501730352683624643286972673304580144567471843547927
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.107643161031881852207110914797344318411463774881987590861168319898650429734733
Short name T150
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.45 seconds
Started Nov 01 02:44:40 PM PDT 23
Finished Nov 01 02:44:54 PM PDT 23
Peak memory 211104 kb
Host smart-a3992ae9-179c-49c2-9466-f392cbc5a7ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107643161031881852207110914797344318411463774881987590861168319898650429734733 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.107643161031881852207110914797344318411463774881987590861168319898650429734733
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.28830718678597746956781800640644123500091590922027070678634841415819143469770
Short name T224
Test name
Test status
Simulation time 6265461576 ps
CPU time 27.82 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212516 kb
Host smart-331151a4-c718-4000-ab5d-50d853f422e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28830718678597746956781800640644123500091590922027070678634841415819143469770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.rom_ctrl_smoke.28830718678597746956781800640644123500091590922027070678634841415819143469770
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.61487777251829070984800151928225980703946231316022874908152100713936368013814
Short name T4
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.51 seconds
Started Nov 01 02:44:21 PM PDT 23
Finished Nov 01 02:45:05 PM PDT 23
Peak memory 212996 kb
Host smart-41cb059c-3ead-444f-8249-5b4571fa34e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614877772518290709848001519282259807039462313160228749081521007
13936368013814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all.61487777251829070984800151928225980703946231316022
874908152100713936368013814
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.97441002972683321121426824905653744504135131825507699801454820405931249475315
Short name T29
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.64 seconds
Started Nov 01 02:44:38 PM PDT 23
Finished Nov 01 02:44:52 PM PDT 23
Peak memory 211176 kb
Host smart-1c8d8df3-877b-429f-92d6-e65627b0cf17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97441002972683321121426824905653744504135131825507699801454820405931249475315 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.97441002972683321121426824905653744504135131825507699801454820405931249475315
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.67229432056158988685148666644617725506358910146112494175834393891757250374437
Short name T308
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.33 seconds
Started Nov 01 02:44:39 PM PDT 23
Finished Nov 01 02:50:20 PM PDT 23
Peak memory 237852 kb
Host smart-52b4a998-cbee-4cfb-8248-7a9345ef0162
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67229432056158988685148666644617725506358910146112494175834393891757250374437 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_corrupt_sig_fatal_chk.672294320561589886851486666446177255063589101461124941758
34393891757250374437
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.47968530912583509983750182969072341137853597068808153823170123974326398461436
Short name T176
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.35 seconds
Started Nov 01 02:44:22 PM PDT 23
Finished Nov 01 02:44:49 PM PDT 23
Peak memory 211684 kb
Host smart-8085cf04-d6bf-4325-87cb-fb638512dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47968530912583509983750182969072341137853597068808153823170123974326398461436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.rom_ctrl_kmac_err_chk.47968530912583509983750182969072341137853597068808153823170123974326398461436
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.104329726916311309625154515575959910147083875650850276829694363771541462288625
Short name T327
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.16 seconds
Started Nov 01 02:44:40 PM PDT 23
Finished Nov 01 02:44:55 PM PDT 23
Peak memory 211188 kb
Host smart-b8639710-4bd9-4cca-b7fd-b30a97b38a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104329726916311309625154515575959910147083875650850276829694363771541462288625 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.104329726916311309625154515575959910147083875650850276829694363771541462288625
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.25735228222384623189779464769031311407855860462607984152281256967468480927917
Short name T117
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.44 seconds
Started Nov 01 02:44:40 PM PDT 23
Finished Nov 01 02:45:09 PM PDT 23
Peak memory 212828 kb
Host smart-85a1d8b9-bb3d-4a64-953c-305ef41f7467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25735228222384623189779464769031311407855860462607984152281256967468480927917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.rom_ctrl_smoke.25735228222384623189779464769031311407855860462607984152281256967468480927917
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.113892450103332689099304870863193198841615303207183192224727632786132224847225
Short name T290
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.27 seconds
Started Nov 01 02:44:42 PM PDT 23
Finished Nov 01 02:45:26 PM PDT 23
Peak memory 212876 kb
Host smart-3121c6fa-d6b6-4401-8182-0d24e454dcb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113892450103332689099304870863193198841615303207183192224727632
786132224847225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all.1138924501033326890993048708631931988416153032071
83192224727632786132224847225
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.84945040193838064354765652957611642075534276341561190414820965112109298516394
Short name T220
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.19 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:33 PM PDT 23
Peak memory 211200 kb
Host smart-c43fd47f-7a03-4b04-892c-99244e34ee16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84945040193838064354765652957611642075534276341561190414820965112109298516394 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.84945040193838064354765652957611642075534276341561190414820965112109298516394
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.97984643762096499212907970471902780601933583759268811552301337317501346847032
Short name T52
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.93 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:50:15 PM PDT 23
Peak memory 237680 kb
Host smart-61ab78da-cb4d-4418-8e6e-615b88a73930
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97984643762096499212907970471902780601933583759268811552301337317501346847032 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_corrupt_sig_fatal_chk.979846437620964992129079704719027806019335837592688115523
01337317501346847032
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.112497040259173599232229840708334500533504824586336146999957815057655324893495
Short name T324
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.02 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 211672 kb
Host smart-a1a4eadc-3b85-448a-847e-9a19779b2579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112497040259173599232229840708334500533504824586336146999957815057655324893495 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.rom_ctrl_kmac_err_chk.112497040259173599232229840708334500533504824586336146999957815057655324893495
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.111465167916559694146470356893275438981305429606142617361668252273257619981205
Short name T83
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.95 seconds
Started Nov 01 02:44:28 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 210996 kb
Host smart-07f13173-803a-4fc4-830a-aa3bc6fa0565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=111465167916559694146470356893275438981305429606142617361668252273257619981205 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.111465167916559694146470356893275438981305429606142617361668252273257619981205
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.49926492525285881662287104431187943368373960321232571636712176158533767822671
Short name T221
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.61 seconds
Started Nov 01 02:44:39 PM PDT 23
Finished Nov 01 02:45:08 PM PDT 23
Peak memory 212680 kb
Host smart-cc69f3bc-1436-47b4-9a77-25b04c3daf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49926492525285881662287104431187943368373960321232571636712176158533767822671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.rom_ctrl_smoke.49926492525285881662287104431187943368373960321232571636712176158533767822671
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.114919682065143360533123802416015304376825301115014665939572283183842244946946
Short name T357
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.82 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:45:03 PM PDT 23
Peak memory 212892 kb
Host smart-14ba87ad-2e2b-4c44-abaa-ba3f3805c543
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114919682065143360533123802416015304376825301115014665939572283
183842244946946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all.1149196820651433605331238024160153043768253011150
14665939572283183842244946946
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.97928025795221100914620857480156037935267653146770180752882009740737777069024
Short name T233
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.57 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:44:40 PM PDT 23
Peak memory 211220 kb
Host smart-7e0b1b88-bffc-4b13-aa9c-18d3d2415fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97928025795221100914620857480156037935267653146770180752882009740737777069024 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.97928025795221100914620857480156037935267653146770180752882009740737777069024
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.91562784713690105958899147816179488532812725669493246675137039244156501063530
Short name T247
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.27 seconds
Started Nov 01 02:44:19 PM PDT 23
Finished Nov 01 02:50:01 PM PDT 23
Peak memory 237708 kb
Host smart-7da50215-954c-4cb0-bbee-db1e34f0b194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91562784713690105958899147816179488532812725669493246675137039244156501063530 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_corrupt_sig_fatal_chk.915627847136901059588991478161794885328127256694932466751
37039244156501063530
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.21620868389155132703232798844541378304745702265241369588895891484519548252170
Short name T276
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.08 seconds
Started Nov 01 02:44:28 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 211372 kb
Host smart-3cc7160e-bc16-43ee-a64e-f30f90a77f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21620868389155132703232798844541378304745702265241369588895891484519548252170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.rom_ctrl_kmac_err_chk.21620868389155132703232798844541378304745702265241369588895891484519548252170
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.29714168015349808413830579036350575939844223417557370839664780979743778521339
Short name T262
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.16 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 211164 kb
Host smart-eac72939-f1f4-4871-8fd1-d17a4587e418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29714168015349808413830579036350575939844223417557370839664780979743778521339 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.29714168015349808413830579036350575939844223417557370839664780979743778521339
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.80262117439798463967518248753859061094480541636000477048742971615299865847138
Short name T217
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.49 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 212788 kb
Host smart-b1e1a405-ab3c-49ef-99c2-d66d638847e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80262117439798463967518248753859061094480541636000477048742971615299865847138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.rom_ctrl_smoke.80262117439798463967518248753859061094480541636000477048742971615299865847138
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.50325881836855987635243349404831776941684566924640334520781213744861186462836
Short name T284
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.92 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 212324 kb
Host smart-4a8657f4-2c57-4311-9f2f-8b7b440441b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503258818368559876352433494048317769416845669246403345207812137
44861186462836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all.50325881836855987635243349404831776941684566924640
334520781213744861186462836
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.70002208892850467051669503100060126296299161141122975566334079705627652276830
Short name T352
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:44:39 PM PDT 23
Peak memory 211236 kb
Host smart-6ddc32b6-fb09-4f82-8012-7413fd7238ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70002208892850467051669503100060126296299161141122975566334079705627652276830 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.70002208892850467051669503100060126296299161141122975566334079705627652276830
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2604499470371133332188233433215056997777896744535634782426591040224754482277
Short name T223
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.96 seconds
Started Nov 01 02:44:21 PM PDT 23
Finished Nov 01 02:50:00 PM PDT 23
Peak memory 237736 kb
Host smart-5ffbbd31-e5e9-421e-b960-14907000ee9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604499470371133332188233433215056997777896744535634782426591040224754482277 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_corrupt_sig_fatal_chk.2604499470371133332188233433215056997777896744535634782426
591040224754482277
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.19962568013165728809796866228663465182386770245455948082999067705214331207899
Short name T152
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.28 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:45:00 PM PDT 23
Peak memory 211480 kb
Host smart-734de62c-5d52-41c3-8091-cd007c8eb362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19962568013165728809796866228663465182386770245455948082999067705214331207899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.rom_ctrl_kmac_err_chk.19962568013165728809796866228663465182386770245455948082999067705214331207899
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.40415381804251280305826309351825537224196067822823742329337550511942780768916
Short name T77
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.83 seconds
Started Nov 01 02:44:32 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 211044 kb
Host smart-351ea9a6-7105-4cf1-9742-545857d7eb0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40415381804251280305826309351825537224196067822823742329337550511942780768916 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.40415381804251280305826309351825537224196067822823742329337550511942780768916
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.41337757134230804416177917792105699736369143208060220280473952698220866976196
Short name T241
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.08 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:45:03 PM PDT 23
Peak memory 212688 kb
Host smart-e1180f11-48f1-43a5-a5a8-7240919a8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41337757134230804416177917792105699736369143208060220280473952698220866976196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.rom_ctrl_smoke.41337757134230804416177917792105699736369143208060220280473952698220866976196
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.41072305952848678520587267739559389727851617301324413000010492481779660128851
Short name T187
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Nov 01 02:44:28 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 211188 kb
Host smart-5864ceea-e8f4-4772-8871-f8de2fcb0a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072305952848678520587267739559389727851617301324413000010492481779660128851 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.41072305952848678520587267739559389727851617301324413000010492481779660128851
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.93491103694961150180171967017366378506089324835889024002155338778512322331473
Short name T307
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.43 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:50:11 PM PDT 23
Peak memory 237732 kb
Host smart-77f6e905-5680-46fd-ac6b-806cc7529efc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93491103694961150180171967017366378506089324835889024002155338778512322331473 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_corrupt_sig_fatal_chk.934911036949611501801719670173663785060893248358890240021
55338778512322331473
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.61855364465126907087337408278349496809491839057468636969342008748272912845863
Short name T123
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.31 seconds
Started Nov 01 02:44:27 PM PDT 23
Finished Nov 01 02:44:57 PM PDT 23
Peak memory 211684 kb
Host smart-01079f49-fddb-4d49-bd9b-54d59ecf2cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61855364465126907087337408278349496809491839057468636969342008748272912845863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.rom_ctrl_kmac_err_chk.61855364465126907087337408278349496809491839057468636969342008748272912845863
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.75852626031103884932866759460332299041506236493655269331296975448031684206476
Short name T179
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 211196 kb
Host smart-3cf9bc98-d231-42c9-a83a-5044918e459d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75852626031103884932866759460332299041506236493655269331296975448031684206476 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.75852626031103884932866759460332299041506236493655269331296975448031684206476
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.55810012205136694669533460903368686602166934521621833102275825953842633750360
Short name T283
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.97 seconds
Started Nov 01 02:44:26 PM PDT 23
Finished Nov 01 02:44:56 PM PDT 23
Peak memory 212896 kb
Host smart-80ef372f-b165-4d76-96d9-e9f421f4df8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55810012205136694669533460903368686602166934521621833102275825953842633750360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.rom_ctrl_smoke.55810012205136694669533460903368686602166934521621833102275825953842633750360
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.23533822524314868223926392748024991085732137142977617162648433251085019480521
Short name T38
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.89 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:17 PM PDT 23
Peak memory 212948 kb
Host smart-6b820c21-db57-4b0c-9c81-13c0e067cf16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235338225243148682239263927480249910857321371429776171626484332
51085019480521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all.23533822524314868223926392748024991085732137142977
617162648433251085019480521
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.41428873741801552028830557133284312862162637657292789878226245995118886055865
Short name T139
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 211220 kb
Host smart-d5a98f32-3796-4e15-aa23-47f5e8430a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428873741801552028830557133284312862162637657292789878226245995118886055865 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.41428873741801552028830557133284312862162637657292789878226245995118886055865
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.105040032647937292644880009398658143607275505332864916465308537590628870638983
Short name T213
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.31 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:50:19 PM PDT 23
Peak memory 237736 kb
Host smart-21f335ca-fa2e-48e2-ba1d-d65f4ba57cab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105040032647937292644880009398658143607275505332864916465308537590628870638983 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_corrupt_sig_fatal_chk.10504003264793729264488000939865814360727550533286491646
5308537590628870638983
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.24894458635000628857767044529815025601244085557610605662989954764141682506217
Short name T106
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.74 seconds
Started Nov 01 02:44:33 PM PDT 23
Finished Nov 01 02:45:03 PM PDT 23
Peak memory 211600 kb
Host smart-b6407dac-b104-463c-a5db-7e1f3071031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24894458635000628857767044529815025601244085557610605662989954764141682506217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.rom_ctrl_kmac_err_chk.24894458635000628857767044529815025601244085557610605662989954764141682506217
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.112007601999615680417521371354717564114485101348684044455786153985927065325998
Short name T296
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.18 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 211192 kb
Host smart-a2633d1e-025d-49c5-ad58-3f80917bd8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112007601999615680417521371354717564114485101348684044455786153985927065325998 -assert nopostproc +UVM_TE
STNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.112007601999615680417521371354717564114485101348684044455786153985927065325998
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.45796129749020316708993815638557660124492436539841555201324887463562895641371
Short name T320
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.69 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:03 PM PDT 23
Peak memory 212628 kb
Host smart-7f897c51-4829-42e4-9f9b-1f2935362be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45796129749020316708993815638557660124492436539841555201324887463562895641371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.rom_ctrl_smoke.45796129749020316708993815638557660124492436539841555201324887463562895641371
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.56645838762642228792117899580804868522965994321798263788154014230649943654771
Short name T246
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.07 seconds
Started Nov 01 02:44:31 PM PDT 23
Finished Nov 01 02:45:18 PM PDT 23
Peak memory 212976 kb
Host smart-0568ce2d-33f3-49e7-9e68-af780c5b4ce6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566458387626422287921178995808048685229659943217982637881540142
30649943654771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all.56645838762642228792117899580804868522965994321798
263788154014230649943654771
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.85777572411346836303612299301515130796479111224927964386659623173193313508237
Short name T361
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.24 seconds
Started Nov 01 02:44:03 PM PDT 23
Finished Nov 01 02:44:19 PM PDT 23
Peak memory 211236 kb
Host smart-eba1cd8f-4df1-4905-b6db-60535eb0cc48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85777572411346836303612299301515130796479111224927964386659623173193313508237 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.85777572411346836303612299301515130796479111224927964386659623173193313508237
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.44625999181502461848750626881883147506791838095924501948778219522656522650147
Short name T180
Test name
Test status
Simulation time 69854280986 ps
CPU time 340.65 seconds
Started Nov 01 02:43:31 PM PDT 23
Finished Nov 01 02:49:13 PM PDT 23
Peak memory 237724 kb
Host smart-2fbc5fc2-efe3-4e33-a1b5-9ab1a8ad6ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44625999181502461848750626881883147506791838095924501948778219522656522650147 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_corrupt_sig_fatal_chk.4462599918150246184875062688188314750679183809592450194877
8219522656522650147
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.28521286794443468473604662859722008395208963307752836684639242729314992144837
Short name T126
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.93 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:31 PM PDT 23
Peak memory 211636 kb
Host smart-688ec616-eaba-41d9-98f8-a698a7a6ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28521286794443468473604662859722008395208963307752836684639242729314992144837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.rom_ctrl_kmac_err_chk.28521286794443468473604662859722008395208963307752836684639242729314992144837
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.89412680257902793926277620957025110839327244265190110946473709752160384363405
Short name T271
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.2 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:44 PM PDT 23
Peak memory 211240 kb
Host smart-2def0a0c-7e6a-4aab-98ba-a9401801978e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89412680257902793926277620957025110839327244265190110946473709752160384363405 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.89412680257902793926277620957025110839327244265190110946473709752160384363405
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.21771140787766933760624633774590163153903663859379833962048910951526347030086
Short name T28
Test name
Test status
Simulation time 3444857586 ps
CPU time 116.57 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:46:02 PM PDT 23
Peak memory 236844 kb
Host smart-997243c8-7a3f-41d3-98da-6e7286c64640
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21771140787766933760624633774590163153903663859379833962048910951526347030086 -assert nopostpro
c +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.21771140787766933760624633774590163153903663859379833962048910951526347030086
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.36867932968658726672771048633102932162561222576242307343900667567012946053559
Short name T118
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.7 seconds
Started Nov 01 02:44:02 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 212868 kb
Host smart-877cd2a6-b0cb-4e49-bc8a-91acc43f56aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36867932968658726672771048633102932162561222576242307343900667567012946053559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.rom_ctrl_smoke.36867932968658726672771048633102932162561222576242307343900667567012946053559
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.54390876368118636574908003044468766017639264825771623579025769306771244672198
Short name T124
Test name
Test status
Simulation time 9415977006 ps
CPU time 44.1 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:44:15 PM PDT 23
Peak memory 212984 kb
Host smart-7d400984-b5f6-42b1-84a1-2a1699335ea6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543908763681186365749080030444687660176392648257716235790257693
06771244672198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all.543908763681186365749080030444687660176392648257716
23579025769306771244672198
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.45810494730511333977957813784141927919532545991399093160335958972197011743087
Short name T7
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.72 seconds
Started Nov 01 02:44:43 PM PDT 23
Finished Nov 01 02:44:57 PM PDT 23
Peak memory 211220 kb
Host smart-16c182fb-8fc4-4ce3-975b-21125b8c9f83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45810494730511333977957813784141927919532545991399093160335958972197011743087 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.45810494730511333977957813784141927919532545991399093160335958972197011743087
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.87165207712469988294405004159198183967832920856490394084479444156671910588258
Short name T170
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.82 seconds
Started Nov 01 02:44:40 PM PDT 23
Finished Nov 01 02:50:20 PM PDT 23
Peak memory 237676 kb
Host smart-5f37d29b-55d5-49ed-9445-70864da99ae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87165207712469988294405004159198183967832920856490394084479444156671910588258 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_corrupt_sig_fatal_chk.871652077124699882944050041591981839678329208564903940844
79444156671910588258
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.79164723655229908649949114716533470724561479176122571051589343813787072871263
Short name T334
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.15 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:44:59 PM PDT 23
Peak memory 210608 kb
Host smart-3f53090d-c2f5-4aa5-a25f-0877c42936c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79164723655229908649949114716533470724561479176122571051589343813787072871263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.rom_ctrl_kmac_err_chk.79164723655229908649949114716533470724561479176122571051589343813787072871263
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.84287648111735791593691485798522446308797699268812739791227720390608281857861
Short name T114
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.28 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 210148 kb
Host smart-9006f468-9308-4010-a6c8-04b570115c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=84287648111735791593691485798522446308797699268812739791227720390608281857861 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.84287648111735791593691485798522446308797699268812739791227720390608281857861
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.16813744706240504170825580373326605163140276298558959625124448405281080312901
Short name T171
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.28 seconds
Started Nov 01 02:44:32 PM PDT 23
Finished Nov 01 02:45:05 PM PDT 23
Peak memory 212876 kb
Host smart-40222907-b13b-46c8-96a4-10125d155d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16813744706240504170825580373326605163140276298558959625124448405281080312901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.rom_ctrl_smoke.16813744706240504170825580373326605163140276298558959625124448405281080312901
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.33970646522255165365519398651364525035022475257345428536495314960994111296374
Short name T136
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.29 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:45:16 PM PDT 23
Peak memory 212808 kb
Host smart-2f1cef87-6d6c-46d4-820e-bf259910bbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339706465222551653655193986513645250350224752573454285364953149
60994111296374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all.33970646522255165365519398651364525035022475257345
428536495314960994111296374
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.14628020774625324826300258072130024953557470294595225563235084751778322957517
Short name T297
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.53 seconds
Started Nov 01 02:44:37 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 211196 kb
Host smart-b7579391-9050-4612-8fb6-2f129090aa27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14628020774625324826300258072130024953557470294595225563235084751778322957517 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.14628020774625324826300258072130024953557470294595225563235084751778322957517
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.33001080076966469612621918611975777082949381307365817856656852388976726744778
Short name T222
Test name
Test status
Simulation time 69854280986 ps
CPU time 344.69 seconds
Started Nov 01 02:44:38 PM PDT 23
Finished Nov 01 02:50:24 PM PDT 23
Peak memory 237724 kb
Host smart-d9129718-498b-41d6-bd6c-225230972581
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001080076966469612621918611975777082949381307365817856656852388976726744778 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_corrupt_sig_fatal_chk.330010800769664696126219186119757770829493813073658178566
56852388976726744778
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.113537395503263747025422208704020356962335478403790485555652265090380318219297
Short name T129
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.59 seconds
Started Nov 01 02:44:37 PM PDT 23
Finished Nov 01 02:45:04 PM PDT 23
Peak memory 211468 kb
Host smart-b24c7ae3-6ebb-4dba-adbf-a549e8d745f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113537395503263747025422208704020356962335478403790485555652265090380318219297 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.rom_ctrl_kmac_err_chk.113537395503263747025422208704020356962335478403790485555652265090380318219297
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.37088704598596098576423237785804190830787588715079414383550383476039851361915
Short name T242
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.3 seconds
Started Nov 01 02:44:38 PM PDT 23
Finished Nov 01 02:44:52 PM PDT 23
Peak memory 211240 kb
Host smart-1b0c3846-af80-428d-aee3-8e3cfa43a63d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37088704598596098576423237785804190830787588715079414383550383476039851361915 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.37088704598596098576423237785804190830787588715079414383550383476039851361915
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.22030736003638157736303513274609311712914624369475850757959990181462892464153
Short name T344
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.09 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:45:02 PM PDT 23
Peak memory 212704 kb
Host smart-cdabbf1f-4123-4437-b096-62f7ecfb6dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22030736003638157736303513274609311712914624369475850757959990181462892464153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.rom_ctrl_smoke.22030736003638157736303513274609311712914624369475850757959990181462892464153
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.52977303686722319220344885318202052678181703788124646435863178712800459439688
Short name T107
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.92 seconds
Started Nov 01 02:44:35 PM PDT 23
Finished Nov 01 02:45:21 PM PDT 23
Peak memory 213024 kb
Host smart-bd55fdcf-c25b-4952-afb5-07aa817f2b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529773036867223192203448853182020526781817037881246464358631787
12800459439688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all.52977303686722319220344885318202052678181703788124
646435863178712800459439688
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.25430285190945237821148244938343881506402266306906463148309343259273445017816
Short name T318
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.21 seconds
Started Nov 01 02:44:30 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 211028 kb
Host smart-c252cfff-fbdd-42f4-8da4-0455cfcba5d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25430285190945237821148244938343881506402266306906463148309343259273445017816 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.25430285190945237821148244938343881506402266306906463148309343259273445017816
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.22259764452846718685730655999438926813385091072724234849426473872860007495508
Short name T256
Test name
Test status
Simulation time 69854280986 ps
CPU time 333.4 seconds
Started Nov 01 02:44:29 PM PDT 23
Finished Nov 01 02:50:07 PM PDT 23
Peak memory 237340 kb
Host smart-a34903ea-306e-44fb-bfee-2a3070162d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259764452846718685730655999438926813385091072724234849426473872860007495508 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_corrupt_sig_fatal_chk.222597644528467186857306559994389268133850910727242348494
26473872860007495508
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.23148712462208018719679689610513229857621339344696610521803927486061866773211
Short name T231
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.72 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 211676 kb
Host smart-94d6fc24-1bf7-40e0-a82b-8c8f8ec837d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23148712462208018719679689610513229857621339344696610521803927486061866773211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.rom_ctrl_kmac_err_chk.23148712462208018719679689610513229857621339344696610521803927486061866773211
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.42279280030031333076567133012828962645947739547136044455018426301405598537812
Short name T161
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.12 seconds
Started Nov 01 02:44:28 PM PDT 23
Finished Nov 01 02:44:47 PM PDT 23
Peak memory 211164 kb
Host smart-acc16289-275f-42c4-aa2f-d451056c7dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=42279280030031333076567133012828962645947739547136044455018426301405598537812 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.42279280030031333076567133012828962645947739547136044455018426301405598537812
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.26983613420319076591367574868799320081074453858485141306825653865699359127157
Short name T84
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.53 seconds
Started Nov 01 02:44:52 PM PDT 23
Finished Nov 01 02:45:23 PM PDT 23
Peak memory 212764 kb
Host smart-99a360ba-537c-42bc-aaa7-a3fd24d5a351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26983613420319076591367574868799320081074453858485141306825653865699359127157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.rom_ctrl_smoke.26983613420319076591367574868799320081074453858485141306825653865699359127157
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.16919117017448123639569546950750904443211900866092697105248512161494123196579
Short name T311
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.4 seconds
Started Nov 01 02:44:54 PM PDT 23
Finished Nov 01 02:45:39 PM PDT 23
Peak memory 212972 kb
Host smart-970cdf70-7d1d-431f-9e8d-4cb359345c7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169191170174481236395695469507509044432119008660926971052485121
61494123196579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all.16919117017448123639569546950750904443211900866092
697105248512161494123196579
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.33297753928308071121436932710187007520274835517707333209489831487762032650573
Short name T120
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.69 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:45:24 PM PDT 23
Peak memory 211184 kb
Host smart-2517e27a-5e64-463e-b861-ffc345c9ddd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297753928308071121436932710187007520274835517707333209489831487762032650573 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.33297753928308071121436932710187007520274835517707333209489831487762032650573
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.63560184255731090909886243868742344048973961077325757639112507510905851968335
Short name T163
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.37 seconds
Started Nov 01 02:45:12 PM PDT 23
Finished Nov 01 02:50:49 PM PDT 23
Peak memory 237680 kb
Host smart-6ab8a5db-7dd9-432e-8f7c-4fbcca73d1dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63560184255731090909886243868742344048973961077325757639112507510905851968335 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_corrupt_sig_fatal_chk.635601842557310909098862438687423440489739610773257576391
12507510905851968335
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.72813129069300254934465935871108538479594230258743780331214067966723769403351
Short name T326
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.62 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:36 PM PDT 23
Peak memory 211672 kb
Host smart-fd22a48b-c397-4f74-9170-69e1d71b844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72813129069300254934465935871108538479594230258743780331214067966723769403351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.rom_ctrl_kmac_err_chk.72813129069300254934465935871108538479594230258743780331214067966723769403351
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.16765086517311890256724522269726994230542680781530994425149481356331851745632
Short name T269
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.63 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:23 PM PDT 23
Peak memory 211220 kb
Host smart-71708801-9370-4292-8bac-872d4108cb2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16765086517311890256724522269726994230542680781530994425149481356331851745632 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.16765086517311890256724522269726994230542680781530994425149481356331851745632
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.63501065635267096471369031328069078388636166727848147556327798928925135176839
Short name T146
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.26 seconds
Started Nov 01 02:44:21 PM PDT 23
Finished Nov 01 02:44:51 PM PDT 23
Peak memory 212888 kb
Host smart-cf92fa6e-dbd3-4bd8-aa69-b28eb6f61cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63501065635267096471369031328069078388636166727848147556327798928925135176839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.rom_ctrl_smoke.63501065635267096471369031328069078388636166727848147556327798928925135176839
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.74538516467979123063506000033625571975907186354841010662761951745119733417184
Short name T274
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.5 seconds
Started Nov 01 02:44:20 PM PDT 23
Finished Nov 01 02:45:04 PM PDT 23
Peak memory 212996 kb
Host smart-67c4a965-0a85-485b-bb20-397ad0f9aca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745385164679791230635060000336255719759071863548410106627619517
45119733417184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all.74538516467979123063506000033625571975907186354841
010662761951745119733417184
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.86491375684174915005429775596282199918910902607485180254414565288205742615618
Short name T277
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.08 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 211136 kb
Host smart-3df8f79b-48ee-4135-9a62-53c4b256d817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86491375684174915005429775596282199918910902607485180254414565288205742615618 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.86491375684174915005429775596282199918910902607485180254414565288205742615618
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3986009605996144174148437398810291575458064198544973787000221794911148691544
Short name T200
Test name
Test status
Simulation time 69854280986 ps
CPU time 343.27 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:51:06 PM PDT 23
Peak memory 237816 kb
Host smart-b2b7cb4c-1f46-4811-a444-4aa493e67cad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986009605996144174148437398810291575458064198544973787000221794911148691544 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_corrupt_sig_fatal_chk.3986009605996144174148437398810291575458064198544973787000
221794911148691544
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.5816046602944961505242044399809588653076159953167889681145961663177965503879
Short name T251
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.21 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:45:43 PM PDT 23
Peak memory 211680 kb
Host smart-4bd8141a-9faf-4f39-b24d-6e68aa5282c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5816046602944961505242044399809588653076159953167889681145961663177965503879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_b
ase_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.rom_ctrl_kmac_err_chk.5816046602944961505242044399809588653076159953167889681145961663177965503879
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1593879122860935070305043223754313984788395405982799003112717318786519456462
Short name T282
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.48 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:30 PM PDT 23
Peak memory 211220 kb
Host smart-bbb56072-14e2-438b-b92d-ebdd5ec3a80e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1593879122860935070305043223754313984788395405982799003112717318786519456462 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1593879122860935070305043223754313984788395405982799003112717318786519456462
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.62782403539641844614380579916778575677217594715028883308429312779588277762348
Short name T134
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.73 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 212896 kb
Host smart-19c10039-d328-4315-a038-ffb170ddee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62782403539641844614380579916778575677217594715028883308429312779588277762348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.rom_ctrl_smoke.62782403539641844614380579916778575677217594715028883308429312779588277762348
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.25385663698903304608138872098081938911912624767057517160829463112668363751458
Short name T137
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.19 seconds
Started Nov 01 02:45:12 PM PDT 23
Finished Nov 01 02:45:56 PM PDT 23
Peak memory 212976 kb
Host smart-5c51492a-f779-4dcf-b0a0-5a1249e89f55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253856636989033046081388720980819389119126247670575171608294631
12668363751458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all.25385663698903304608138872098081938911912624767057
517160829463112668363751458
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.114542344532918758313704600365718931489436187035719364144227740185754049419722
Short name T335
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.27 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:34 PM PDT 23
Peak memory 211332 kb
Host smart-b4960b1f-91ec-4b87-b509-3c91478fd14a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114542344532918758313704600365718931489436187035719364144227740185754049419722 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.114542344532918758313704600365718931489436187035719364144227740185754049419722
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.22884910852325720804690850821843311667646605383680696281916767840209164718811
Short name T293
Test name
Test status
Simulation time 69854280986 ps
CPU time 337.26 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:50:52 PM PDT 23
Peak memory 237728 kb
Host smart-b00e0518-b9a8-4014-b162-87c1aa303aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884910852325720804690850821843311667646605383680696281916767840209164718811 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_corrupt_sig_fatal_chk.228849108523257208046908508218433116676466053836806962819
16767840209164718811
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.86400149885266333220455091248037727802164653820737257497356657599091076515320
Short name T42
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.19 seconds
Started Nov 01 02:45:12 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 211636 kb
Host smart-5e6d937d-afc7-4e8c-8ca3-fc8629b7791d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86400149885266333220455091248037727802164653820737257497356657599091076515320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.rom_ctrl_kmac_err_chk.86400149885266333220455091248037727802164653820737257497356657599091076515320
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.77105824260461542611017585036510585282611594324255526096452000098528597902331
Short name T332
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.27 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 211120 kb
Host smart-745298b2-3b3c-4ea9-9be9-6fa9e0ad3573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77105824260461542611017585036510585282611594324255526096452000098528597902331 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.77105824260461542611017585036510585282611594324255526096452000098528597902331
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.79232415425907742571438626905994955989300271552125749486002118872211992695596
Short name T111
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.99 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:45:47 PM PDT 23
Peak memory 212856 kb
Host smart-548ba087-7219-4cd2-a5c4-335262763f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79232415425907742571438626905994955989300271552125749486002118872211992695596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.rom_ctrl_smoke.79232415425907742571438626905994955989300271552125749486002118872211992695596
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.47304726312764892034134327473538464441082260831411866086093515078956780058801
Short name T110
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.04 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 212984 kb
Host smart-3b410be3-c315-41a8-8e93-3eb47a2873a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473047263127648920341343274735384644410822608314118660860935150
78956780058801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all.47304726312764892034134327473538464441082260831411
866086093515078956780058801
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.18284564491354607319867825187015814934293764228110843807899285327839422466905
Short name T333
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.48 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:21 PM PDT 23
Peak memory 211204 kb
Host smart-63d1f567-783e-4f2f-9786-edbe7ca2e478
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284564491354607319867825187015814934293764228110843807899285327839422466905 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.18284564491354607319867825187015814934293764228110843807899285327839422466905
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.66060537205795089976171894149075091975378385875404438546815352718936228188666
Short name T298
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.12 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:50:57 PM PDT 23
Peak memory 237764 kb
Host smart-c5225f01-d27f-48c9-adbe-8b40db5b0438
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66060537205795089976171894149075091975378385875404438546815352718936228188666 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_corrupt_sig_fatal_chk.660605372057950899761718941490750919753783858754044385468
15352718936228188666
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.63368234241386360036234633416543759006942441839019782221022216921327685503438
Short name T229
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.07 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:45:38 PM PDT 23
Peak memory 211656 kb
Host smart-0a11a16e-5e9f-4d7a-b7b0-fa8c7714a97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63368234241386360036234633416543759006942441839019782221022216921327685503438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.rom_ctrl_kmac_err_chk.63368234241386360036234633416543759006942441839019782221022216921327685503438
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.52345848201898253463429974905795573951576201367694888929983291679798920445298
Short name T160
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.23 seconds
Started Nov 01 02:45:21 PM PDT 23
Finished Nov 01 02:45:35 PM PDT 23
Peak memory 211300 kb
Host smart-e60dfbcd-8f12-4838-a983-937c2c11e81c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52345848201898253463429974905795573951576201367694888929983291679798920445298 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.52345848201898253463429974905795573951576201367694888929983291679798920445298
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.76740620160541569262913870856225226978133489599838569085579308314578503742928
Short name T169
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.67 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:45:43 PM PDT 23
Peak memory 212864 kb
Host smart-16249458-2cd9-412c-bc5c-4794a562351c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76740620160541569262913870856225226978133489599838569085579308314578503742928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.rom_ctrl_smoke.76740620160541569262913870856225226978133489599838569085579308314578503742928
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.27341643149338069623058269368639259906773905014667524702198449780970078831466
Short name T287
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.16 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:45:57 PM PDT 23
Peak memory 213076 kb
Host smart-a44a9a7d-e1c5-4acf-9493-c95d2e78078d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273416431493380696230582693686392599067739050146675247021984497
80970078831466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all.27341643149338069623058269368639259906773905014667
524702198449780970078831466
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.79318607917378454548559993917466096845559483988162388973901158909687714754771
Short name T279
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.61 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:28 PM PDT 23
Peak memory 211220 kb
Host smart-8774df42-2f5e-40b9-893c-b94633c4f9bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79318607917378454548559993917466096845559483988162388973901158909687714754771 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.79318607917378454548559993917466096845559483988162388973901158909687714754771
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.6399998254701884211369446844816740376985145136180495833438125017490860710632
Short name T47
Test name
Test status
Simulation time 69854280986 ps
CPU time 341.39 seconds
Started Nov 01 02:45:16 PM PDT 23
Finished Nov 01 02:51:00 PM PDT 23
Peak memory 237904 kb
Host smart-042ddccf-8ddb-4b8e-ab07-f3eb0041bbaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6399998254701884211369446844816740376985145136180495833438125017490860710632 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_corrupt_sig_fatal_chk.6399998254701884211369446844816740376985145136180495833438
125017490860710632
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.79593959685708187800710120133660724941032301805118420148327778736255794293685
Short name T149
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.6 seconds
Started Nov 01 02:45:13 PM PDT 23
Finished Nov 01 02:45:41 PM PDT 23
Peak memory 211684 kb
Host smart-c1f3e879-8dcc-4934-b96d-61454f046ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79593959685708187800710120133660724941032301805118420148327778736255794293685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.rom_ctrl_kmac_err_chk.79593959685708187800710120133660724941032301805118420148327778736255794293685
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.30922988915904340146018040095734995513096218229860904917026238814046588364724
Short name T230
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.88 seconds
Started Nov 01 02:47:58 PM PDT 23
Finished Nov 01 02:48:18 PM PDT 23
Peak memory 211300 kb
Host smart-30980abb-e0f8-46d0-861a-5b1ed0add494
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30922988915904340146018040095734995513096218229860904917026238814046588364724 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.30922988915904340146018040095734995513096218229860904917026238814046588364724
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.24204382418127145539941128583526334419072241042012679465954100757293985090008
Short name T313
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.27 seconds
Started Nov 01 02:45:06 PM PDT 23
Finished Nov 01 02:45:40 PM PDT 23
Peak memory 212860 kb
Host smart-01ad43d1-8b09-409c-aaa9-ecd997115d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24204382418127145539941128583526334419072241042012679465954100757293985090008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.rom_ctrl_smoke.24204382418127145539941128583526334419072241042012679465954100757293985090008
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.12372632059718855426828186827618989691474250393404614617240397488608199041265
Short name T270
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.51 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:58 PM PDT 23
Peak memory 212972 kb
Host smart-980d76eb-1d6b-4e21-8155-b06bdc7754de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123726320597188554268281868276189896914742503934046146172403974
88608199041265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all.12372632059718855426828186827618989691474250393404
614617240397488608199041265
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.100752419617867774580342593907595704026173780918784025846209008677459847841127
Short name T193
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Nov 01 02:45:05 PM PDT 23
Finished Nov 01 02:45:24 PM PDT 23
Peak memory 211160 kb
Host smart-3973ecb1-aa2d-456e-a1e9-c1cbca0c986f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100752419617867774580342593907595704026173780918784025846209008677459847841127 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.100752419617867774580342593907595704026173780918784025846209008677459847841127
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.40195127006396548838482488184228987920244982277055585083341533340614090509744
Short name T209
Test name
Test status
Simulation time 69854280986 ps
CPU time 335.39 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:50:53 PM PDT 23
Peak memory 237684 kb
Host smart-5b81d284-10cb-48ce-9c68-11c185b58157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195127006396548838482488184228987920244982277055585083341533340614090509744 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_corrupt_sig_fatal_chk.401951270063965488384824881842289879202449822770555850833
41533340614090509744
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.75647141616806247854628415037722380660876186394550641506872665097969076136913
Short name T339
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.83 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:42 PM PDT 23
Peak memory 211684 kb
Host smart-b2c982cf-553c-41a7-837b-d01afdb0fbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75647141616806247854628415037722380660876186394550641506872665097969076136913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.rom_ctrl_kmac_err_chk.75647141616806247854628415037722380660876186394550641506872665097969076136913
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.39945278113933305076140312293653591588978454118453824037498731748384770750920
Short name T82
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.42 seconds
Started Nov 01 02:45:03 PM PDT 23
Finished Nov 01 02:45:22 PM PDT 23
Peak memory 211144 kb
Host smart-1397f9cb-d7e9-4b91-848b-a3c2d45c97a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39945278113933305076140312293653591588978454118453824037498731748384770750920 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.39945278113933305076140312293653591588978454118453824037498731748384770750920
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.52377427605673602436377425479169534781758739196574857695786629984137920606731
Short name T310
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.52 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:48 PM PDT 23
Peak memory 212836 kb
Host smart-90a9673e-8032-496c-81f5-b1394a69114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52377427605673602436377425479169534781758739196574857695786629984137920606731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.rom_ctrl_smoke.52377427605673602436377425479169534781758739196574857695786629984137920606731
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.15592998596982904293601410420815974080742668166502755493806351822141729929665
Short name T103
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.66 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:58 PM PDT 23
Peak memory 213016 kb
Host smart-be7c9b32-8d07-4af4-b7dc-3a3bc2711976
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155929985969829042936014104208159740807426681665027554938063518
22141729929665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all.15592998596982904293601410420815974080742668166502
755493806351822141729929665
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.72682823191468095535939773156907484162091268683438614622466409901548146761987
Short name T181
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.43 seconds
Started Nov 01 02:45:17 PM PDT 23
Finished Nov 01 02:45:31 PM PDT 23
Peak memory 211196 kb
Host smart-f44a72f8-7763-4048-9afe-07d071574244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72682823191468095535939773156907484162091268683438614622466409901548146761987 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.72682823191468095535939773156907484162091268683438614622466409901548146761987
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.79740661662849669512762257671487196189633784923410011799063225298396258215650
Short name T46
Test name
Test status
Simulation time 69854280986 ps
CPU time 334.07 seconds
Started Nov 01 02:45:03 PM PDT 23
Finished Nov 01 02:50:43 PM PDT 23
Peak memory 237756 kb
Host smart-fac982f7-cfa2-42b0-a7f7-bd206ed5a93e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79740661662849669512762257671487196189633784923410011799063225298396258215650 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_corrupt_sig_fatal_chk.797406616628496695127622576714871961896337849234100117990
63225298396258215650
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.39637512459661032907541844456028352421531060685555824765594959729768378592960
Short name T228
Test name
Test status
Simulation time 6233818126 ps
CPU time 26.05 seconds
Started Nov 01 02:45:14 PM PDT 23
Finished Nov 01 02:45:41 PM PDT 23
Peak memory 211676 kb
Host smart-4af17a71-46a4-4b37-a198-907b420eb8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39637512459661032907541844456028352421531060685555824765594959729768378592960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.rom_ctrl_kmac_err_chk.39637512459661032907541844456028352421531060685555824765594959729768378592960
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.60914283915553368176663577282286529510457268816734490975587683161057025217113
Short name T2
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.28 seconds
Started Nov 01 02:45:04 PM PDT 23
Finished Nov 01 02:45:22 PM PDT 23
Peak memory 211156 kb
Host smart-448063ea-8118-4cd1-b306-fd6dfb72d274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=60914283915553368176663577282286529510457268816734490975587683161057025217113 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.60914283915553368176663577282286529510457268816734490975587683161057025217113
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.50611297017322906615099971436507824433980514492620178608307135049131651679393
Short name T215
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.49 seconds
Started Nov 01 02:45:20 PM PDT 23
Finished Nov 01 02:45:50 PM PDT 23
Peak memory 212940 kb
Host smart-ca5134eb-89f0-4414-9591-cda81de64b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50611297017322906615099971436507824433980514492620178608307135049131651679393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.rom_ctrl_smoke.50611297017322906615099971436507824433980514492620178608307135049131651679393
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.109867251948110331149778973109633455304983437274740468357571722651816152087569
Short name T154
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.2 seconds
Started Nov 01 02:45:15 PM PDT 23
Finished Nov 01 02:46:01 PM PDT 23
Peak memory 213036 kb
Host smart-df90d5d9-c35e-41f4-9945-a8c28bbaf48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109867251948110331149778973109633455304983437274740468357571722
651816152087569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all.1098672519481103311497789731096334553049834372747
40468357571722651816152087569
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.105746416321844458152003576978798309655035903104800327403840222635822215433685
Short name T245
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.36 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:21 PM PDT 23
Peak memory 211220 kb
Host smart-a67a06f1-6d51-4e5e-9a2f-cd708e7199e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105746416321844458152003576978798309655035903104800327403840222635822215433685 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.105746416321844458152003576978798309655035903104800327403840222635822215433685
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.9139277435148426273050860110096401746388689295545314995384799023220221766984
Short name T194
Test name
Test status
Simulation time 69854280986 ps
CPU time 342.39 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:49:52 PM PDT 23
Peak memory 237780 kb
Host smart-8f905c39-a2ec-4f17-81e3-bd7b31a755fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9139277435148426273050860110096401746388689295545314995384799023220221766984 -assert nopostp
roc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_corrupt_sig_fatal_chk.91392774351484262730508601100964017463886892955453149953847
99023220221766984
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.95347436461469846929680614223295203296421613013201579028764575629027241671203
Short name T39
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.62 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:34 PM PDT 23
Peak memory 211676 kb
Host smart-c453c996-51c9-48c2-b19b-818ba906e84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95347436461469846929680614223295203296421613013201579028764575629027241671203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.rom_ctrl_kmac_err_chk.95347436461469846929680614223295203296421613013201579028764575629027241671203
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1819694916560135435612751951447969868997118717422882024504445788888706784902
Short name T350
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.25 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:20 PM PDT 23
Peak memory 211228 kb
Host smart-41ca8c63-aa79-4b7b-83e1-6deab1348310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1819694916560135435612751951447969868997118717422882024504445788888706784902 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1819694916560135435612751951447969868997118717422882024504445788888706784902
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.29229585861579370164501036635469253428927178506870885841122553370139399712207
Short name T341
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.77 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:37 PM PDT 23
Peak memory 212944 kb
Host smart-21b12039-2944-4750-81e7-60dc1a6aa443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29229585861579370164501036635469253428927178506870885841122553370139399712207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.rom_ctrl_smoke.29229585861579370164501036635469253428927178506870885841122553370139399712207
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.72398967831591768787563029685925496026106968041143429450302736828948225362523
Short name T356
Test name
Test status
Simulation time 9415977006 ps
CPU time 41.71 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:46 PM PDT 23
Peak memory 212896 kb
Host smart-ae296b85-4e01-4e0a-addf-723559221078
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723989678315917687875630296859254960261069680411434294503027368
28948225362523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all.723989678315917687875630296859254960261069680411434
29450302736828948225362523
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.54619130300120525645062621849475183494756739895881650843923231872017606143329
Short name T321
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.49 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211232 kb
Host smart-e5675e95-b7d4-4abc-afeb-bc497e021ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54619130300120525645062621849475183494756739895881650843923231872017606143329 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.54619130300120525645062621849475183494756739895881650843923231872017606143329
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.42381949133488808836155279434631151198086618255431806715407187337837494815426
Short name T50
Test name
Test status
Simulation time 69854280986 ps
CPU time 346.76 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:49:58 PM PDT 23
Peak memory 237616 kb
Host smart-6477a1f2-18fe-4616-846f-698d28889a4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42381949133488808836155279434631151198086618255431806715407187337837494815426 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_corrupt_sig_fatal_chk.4238194913348880883615527943463115119808661825543180671540
7187337837494815426
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.76951445081447376548954776621362056473130879318980610215210409907063589341756
Short name T281
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.91 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:35 PM PDT 23
Peak memory 211648 kb
Host smart-e2369a81-9487-42ae-aa7d-ecc33fcfa984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76951445081447376548954776621362056473130879318980610215210409907063589341756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.rom_ctrl_kmac_err_chk.76951445081447376548954776621362056473130879318980610215210409907063589341756
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.7367454700798720928357540322537127644442341113621346512520667971736842216605
Short name T236
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.35 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211224 kb
Host smart-ce354028-7c3e-499e-aa11-8de79e29905c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=7367454700798720928357540322537127644442341113621346512520667971736842216605 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.7367454700798720928357540322537127644442341113621346512520667971736842216605
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.92531857258963773647641675329073884194863622959033437523325392209862226587679
Short name T342
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.8 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:36 PM PDT 23
Peak memory 212764 kb
Host smart-9bced148-16e5-4390-a10b-bc24e110fe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92531857258963773647641675329073884194863622959033437523325392209862226587679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.rom_ctrl_smoke.92531857258963773647641675329073884194863622959033437523325392209862226587679
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.13868960852933288124151062622102665746413191383255435534056591149805856868592
Short name T43
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.65 seconds
Started Nov 01 02:44:04 PM PDT 23
Finished Nov 01 02:44:50 PM PDT 23
Peak memory 212932 kb
Host smart-a9b9158f-5f7e-4650-ace8-45f9f22d30a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138689608529332881241510626221026657464131913832554355340565911
49805856868592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all.138689608529332881241510626221026657464131913832554
35534056591149805856868592
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.36649446992499071856263169596224332315918539403740871505056043004623117088336
Short name T214
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.73 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 211236 kb
Host smart-8cd72c67-3f45-4d85-8236-5dd76ad10860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649446992499071856263169596224332315918539403740871505056043004623117088336 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.36649446992499071856263169596224332315918539403740871505056043004623117088336
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.33903107160288046744900151113039557541094259880911545337305307288582918568672
Short name T164
Test name
Test status
Simulation time 69854280986 ps
CPU time 336.85 seconds
Started Nov 01 02:44:07 PM PDT 23
Finished Nov 01 02:49:48 PM PDT 23
Peak memory 237524 kb
Host smart-ce42a820-9853-496d-8930-b5fe6a62ed97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33903107160288046744900151113039557541094259880911545337305307288582918568672 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_corrupt_sig_fatal_chk.3390310716028804674490015111303955754109425988091154533730
5307288582918568672
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.115506173056842505542580644876163245302395690118606237325171104964756254390618
Short name T211
Test name
Test status
Simulation time 6233818126 ps
CPU time 24.76 seconds
Started Nov 01 02:43:59 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 211672 kb
Host smart-54f4d2d1-f25a-4809-bc54-df5245bd87e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115506173056842505542580644876163245302395690118606237325171104964756254390618 -assert nopostproc +UVM_TESTNAME=rom_ctrl
_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.rom_ctrl_kmac_err_chk.115506173056842505542580644876163245302395690118606237325171104964756254390618
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.6462865557430647191458948358204766496576232666148584703298290698521601299164
Short name T272
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.09 seconds
Started Nov 01 02:44:05 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 211244 kb
Host smart-ef90397d-26e4-4e7d-9311-da4fd7fda657
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=6462865557430647191458948358204766496576232666148584703298290698521601299164 -assert nopostproc +UVM_TEST
NAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.6462865557430647191458948358204766496576232666148584703298290698521601299164
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.49691269210154274265849020809592618506617940580080254912206190458199736191185
Short name T142
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.74 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:38 PM PDT 23
Peak memory 212840 kb
Host smart-3e54cc6e-ebaf-407b-84a6-0e2e56d79863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49691269210154274265849020809592618506617940580080254912206190458199736191185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.rom_ctrl_smoke.49691269210154274265849020809592618506617940580080254912206190458199736191185
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.112003116483267668795948380421573784412812537521131783289138192351821870345199
Short name T116
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.9 seconds
Started Nov 01 02:44:06 PM PDT 23
Finished Nov 01 02:44:52 PM PDT 23
Peak memory 213092 kb
Host smart-5f8344ee-2078-402e-b070-efa6f76b0755
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112003116483267668795948380421573784412812537521131783289138192
351821870345199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all.11200311648326766879594838042157378441281253752113
1783289138192351821870345199
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.76273607528652917450619392631986098937614401119943884081405031267261718057829
Short name T319
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.33 seconds
Started Nov 01 02:43:29 PM PDT 23
Finished Nov 01 02:43:43 PM PDT 23
Peak memory 211252 kb
Host smart-99870648-6468-4763-b36c-cfca1e5a0135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76273607528652917450619392631986098937614401119943884081405031267261718057829 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.76273607528652917450619392631986098937614401119943884081405031267261718057829
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.106739731452309942822178013911877739688346371495708082269240221105515991637897
Short name T157
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.88 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:49:10 PM PDT 23
Peak memory 237164 kb
Host smart-addf6b58-5151-41d1-a07d-0ccbfe945cc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106739731452309942822178013911877739688346371495708082269240221105515991637897 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_corrupt_sig_fatal_chk.106739731452309942822178013911877739688346371495708082269
240221105515991637897
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.72950137471451985100219367920909090144037770329439290474859100121474411899455
Short name T15
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.65 seconds
Started Nov 01 02:44:01 PM PDT 23
Finished Nov 01 02:44:30 PM PDT 23
Peak memory 211636 kb
Host smart-07e020b3-9caa-4b5a-9e94-31026e4bb8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72950137471451985100219367920909090144037770329439290474859100121474411899455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.rom_ctrl_kmac_err_chk.72950137471451985100219367920909090144037770329439290474859100121474411899455
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.46450439720058437806639599227784584614354532252493891372013412943900856890673
Short name T198
Test name
Test status
Simulation time 3151732636 ps
CPU time 12.95 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:25 PM PDT 23
Peak memory 211200 kb
Host smart-2b9a423d-43d3-4cbd-8f3a-bac2752467c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46450439720058437806639599227784584614354532252493891372013412943900856890673 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.46450439720058437806639599227784584614354532252493891372013412943900856890673
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.18931409539191219638946429259403298570841084867437402054939438650558830670200
Short name T337
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.29 seconds
Started Nov 01 02:44:09 PM PDT 23
Finished Nov 01 02:44:41 PM PDT 23
Peak memory 212824 kb
Host smart-b05a676f-a7d0-4324-943d-3fa0285581eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18931409539191219638946429259403298570841084867437402054939438650558830670200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.rom_ctrl_smoke.18931409539191219638946429259403298570841084867437402054939438650558830670200
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.114182374667328276110860960360455536329754497597474121752767969988651860029185
Short name T196
Test name
Test status
Simulation time 9415977006 ps
CPU time 42.59 seconds
Started Nov 01 02:44:08 PM PDT 23
Finished Nov 01 02:44:54 PM PDT 23
Peak memory 212992 kb
Host smart-f332f9b7-b7f8-4610-9e52-7a7b97266367
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114182374667328276110860960360455536329754497597474121752767969
988651860029185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all.11418237466732827611086096036045553632975449759747
4121752767969988651860029185
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.89722078382903256319863277044586270710522153913002765431040067327832130512903
Short name T299
Test name
Test status
Simulation time 3124113076 ps
CPU time 12.45 seconds
Started Nov 01 02:43:27 PM PDT 23
Finished Nov 01 02:43:41 PM PDT 23
Peak memory 211216 kb
Host smart-af8b6d44-7cc8-4bf8-93b1-dcf5474c42e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89722078382903256319863277044586270710522153913002765431040067327832130512903 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.89722078382903256319863277044586270710522153913002765431040067327832130512903
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.23037595165864250010220378718072329195192658673965296446862073140356017410273
Short name T351
Test name
Test status
Simulation time 69854280986 ps
CPU time 338.18 seconds
Started Nov 01 02:43:25 PM PDT 23
Finished Nov 01 02:49:06 PM PDT 23
Peak memory 237732 kb
Host smart-6a8f37eb-2811-41c7-ba9e-383221c7a595
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037595165864250010220378718072329195192658673965296446862073140356017410273 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_corrupt_sig_fatal_chk.2303759516586425001022037871807232919519265867396529644686
2073140356017410273
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.48580379961373252330908636037229930133139697313129829016024827999134648911535
Short name T261
Test name
Test status
Simulation time 6233818126 ps
CPU time 25.12 seconds
Started Nov 01 02:43:28 PM PDT 23
Finished Nov 01 02:43:54 PM PDT 23
Peak memory 211660 kb
Host smart-e907f97b-d07a-4311-ab38-7171558f4b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48580379961373252330908636037229930133139697313129829016024827999134648911535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.rom_ctrl_kmac_err_chk.48580379961373252330908636037229930133139697313129829016024827999134648911535
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.97378511510134877455875921418433136559842308330248479857533822254530158521264
Short name T265
Test name
Test status
Simulation time 3151732636 ps
CPU time 13.26 seconds
Started Nov 01 02:43:30 PM PDT 23
Finished Nov 01 02:43:44 PM PDT 23
Peak memory 211256 kb
Host smart-c4e52219-c6f6-441e-a503-27a3db88fbd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97378511510134877455875921418433136559842308330248479857533822254530158521264 -assert nopostproc +UVM_TES
TNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.97378511510134877455875921418433136559842308330248479857533822254530158521264
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.12188906441310597406142902399216123340867527969509217726467373375819418522711
Short name T353
Test name
Test status
Simulation time 6265461576 ps
CPU time 28.2 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:44:22 PM PDT 23
Peak memory 212824 kb
Host smart-acea5394-c154-456c-ab4a-5d0036822c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12188906441310597406142902399216123340867527969509217726467373375819418522711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_
base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.rom_ctrl_smoke.12188906441310597406142902399216123340867527969509217726467373375819418522711
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.45062228074294327783164334538586369338467507217681419911853180884701358600032
Short name T45
Test name
Test status
Simulation time 9415977006 ps
CPU time 43.24 seconds
Started Nov 01 02:43:53 PM PDT 23
Finished Nov 01 02:44:37 PM PDT 23
Peak memory 212908 kb
Host smart-f5202400-0938-4f23-9933-f8529bb26b24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450622280742943277831643345385863693384675072176814199118531808
84701358600032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all.450622280742943277831643345385863693384675072176814
19911853180884701358600032
Directory /workspace/9.rom_ctrl_stress_all/latest
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