Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 97.11 93.27 97.88 100.00 99.02 97.89 99.07


Total test records in report: 483
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T265 /workspace/coverage/default/30.rom_ctrl_alert_test.1338808186 Dec 20 12:39:03 PM PST 23 Dec 20 12:40:24 PM PST 23 3403138458 ps
T266 /workspace/coverage/default/11.rom_ctrl_stress_all.2524127492 Dec 20 12:38:35 PM PST 23 Dec 20 12:40:59 PM PST 23 22210369404 ps
T267 /workspace/coverage/default/22.rom_ctrl_alert_test.3143434369 Dec 20 12:39:12 PM PST 23 Dec 20 12:40:48 PM PST 23 8456417279 ps
T268 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.981312132 Dec 20 12:39:02 PM PST 23 Dec 20 12:46:36 PM PST 23 146303844975 ps
T269 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.949405702 Dec 20 12:39:45 PM PST 23 Dec 20 12:45:38 PM PST 23 171869041103 ps
T270 /workspace/coverage/default/18.rom_ctrl_smoke.4138373033 Dec 20 12:39:27 PM PST 23 Dec 20 12:40:59 PM PST 23 9632542010 ps
T271 /workspace/coverage/default/38.rom_ctrl_alert_test.2280319914 Dec 20 12:39:21 PM PST 23 Dec 20 12:40:33 PM PST 23 333019620 ps
T272 /workspace/coverage/default/4.rom_ctrl_smoke.3687784558 Dec 20 12:39:05 PM PST 23 Dec 20 12:40:23 PM PST 23 184265915 ps
T273 /workspace/coverage/default/31.rom_ctrl_smoke.3858692181 Dec 20 12:39:07 PM PST 23 Dec 20 12:40:50 PM PST 23 17608521348 ps
T274 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2593429189 Dec 20 12:38:33 PM PST 23 Dec 20 12:40:03 PM PST 23 8237757109 ps
T275 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1858245393 Dec 20 12:38:39 PM PST 23 Dec 20 12:39:57 PM PST 23 2275464168 ps
T276 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3996034945 Dec 20 12:39:53 PM PST 23 Dec 20 12:41:09 PM PST 23 692174064 ps
T277 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.300058555 Dec 20 12:39:32 PM PST 23 Dec 20 12:41:13 PM PST 23 8343298440 ps
T278 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2376479980 Dec 20 12:38:57 PM PST 23 Dec 20 12:42:34 PM PST 23 13631984158 ps
T279 /workspace/coverage/default/17.rom_ctrl_alert_test.2791646795 Dec 20 12:39:02 PM PST 23 Dec 20 12:40:15 PM PST 23 1222047572 ps
T39 /workspace/coverage/default/3.rom_ctrl_sec_cm.336853151 Dec 20 12:38:27 PM PST 23 Dec 20 12:40:31 PM PST 23 878489962 ps
T280 /workspace/coverage/default/14.rom_ctrl_smoke.132770494 Dec 20 12:38:33 PM PST 23 Dec 20 12:40:13 PM PST 23 4930039028 ps
T281 /workspace/coverage/default/10.rom_ctrl_alert_test.270973006 Dec 20 12:38:57 PM PST 23 Dec 20 12:40:05 PM PST 23 2894275334 ps
T40 /workspace/coverage/default/2.rom_ctrl_sec_cm.2426235788 Dec 20 12:39:03 PM PST 23 Dec 20 12:41:58 PM PST 23 212197649 ps
T282 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4083115948 Dec 20 12:38:51 PM PST 23 Dec 20 12:46:07 PM PST 23 164564064554 ps
T283 /workspace/coverage/default/23.rom_ctrl_stress_all.1036210365 Dec 20 12:39:24 PM PST 23 Dec 20 12:40:50 PM PST 23 1369884541 ps
T284 /workspace/coverage/default/29.rom_ctrl_smoke.2708285696 Dec 20 12:38:53 PM PST 23 Dec 20 12:40:06 PM PST 23 262000178 ps
T285 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4154031065 Dec 20 12:39:49 PM PST 23 Dec 20 01:37:18 PM PST 23 149727010953 ps
T286 /workspace/coverage/default/37.rom_ctrl_smoke.1977505285 Dec 20 12:38:55 PM PST 23 Dec 20 12:40:32 PM PST 23 1208245695 ps
T287 /workspace/coverage/default/42.rom_ctrl_stress_all.460291269 Dec 20 12:39:21 PM PST 23 Dec 20 12:40:57 PM PST 23 3460084736 ps
T288 /workspace/coverage/default/33.rom_ctrl_stress_all.1113994970 Dec 20 12:39:01 PM PST 23 Dec 20 12:42:09 PM PST 23 133330072877 ps
T289 /workspace/coverage/default/7.rom_ctrl_smoke.2281865037 Dec 20 12:38:26 PM PST 23 Dec 20 12:39:56 PM PST 23 7619832112 ps
T290 /workspace/coverage/default/22.rom_ctrl_smoke.152792256 Dec 20 12:39:14 PM PST 23 Dec 20 12:40:33 PM PST 23 748630828 ps
T291 /workspace/coverage/default/8.rom_ctrl_smoke.101265364 Dec 20 12:38:42 PM PST 23 Dec 20 12:40:05 PM PST 23 2144653602 ps
T292 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.855354087 Dec 20 12:39:01 PM PST 23 Dec 20 12:40:20 PM PST 23 23359020371 ps
T293 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1070439159 Dec 20 12:40:44 PM PST 23 Dec 20 12:41:59 PM PST 23 463071080 ps
T294 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.195086195 Dec 20 12:38:41 PM PST 23 Dec 20 12:39:55 PM PST 23 1348361733 ps
T295 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3418902528 Dec 20 12:39:01 PM PST 23 Dec 20 12:57:29 PM PST 23 28732165345 ps
T296 /workspace/coverage/default/25.rom_ctrl_smoke.1909730432 Dec 20 12:38:48 PM PST 23 Dec 20 12:40:22 PM PST 23 5821408737 ps
T297 /workspace/coverage/default/41.rom_ctrl_alert_test.2157525951 Dec 20 12:38:55 PM PST 23 Dec 20 12:40:16 PM PST 23 2045975904 ps
T298 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.280987498 Dec 20 12:38:52 PM PST 23 Dec 20 12:42:09 PM PST 23 35769577056 ps
T299 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.946687500 Dec 20 12:38:41 PM PST 23 Dec 20 12:40:10 PM PST 23 5002643742 ps
T300 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1455675292 Dec 20 12:39:57 PM PST 23 Dec 20 12:41:23 PM PST 23 5912098775 ps
T301 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2802386186 Dec 20 12:39:00 PM PST 23 Dec 20 12:40:21 PM PST 23 4279783729 ps
T302 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2034591844 Dec 20 12:39:06 PM PST 23 Dec 20 12:40:20 PM PST 23 1394893458 ps
T32 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3630566625 Dec 20 12:39:45 PM PST 23 Dec 20 12:41:11 PM PST 23 3182095569 ps
T303 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2824029923 Dec 20 12:38:51 PM PST 23 Dec 20 01:22:59 PM PST 23 68835674663 ps
T304 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1845668972 Dec 20 12:38:30 PM PST 23 Dec 20 12:43:20 PM PST 23 4924921589 ps
T305 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1078398267 Dec 20 12:38:40 PM PST 23 Dec 20 12:40:07 PM PST 23 2257316064 ps
T306 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.749722313 Dec 20 12:39:16 PM PST 23 Dec 20 12:48:59 PM PST 23 986467223376 ps
T307 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3103201575 Dec 20 12:39:41 PM PST 23 Dec 20 12:41:07 PM PST 23 7458617444 ps
T308 /workspace/coverage/default/5.rom_ctrl_stress_all.2223316491 Dec 20 12:39:19 PM PST 23 Dec 20 12:41:08 PM PST 23 79666058569 ps
T309 /workspace/coverage/default/18.rom_ctrl_stress_all.3573013194 Dec 20 12:38:57 PM PST 23 Dec 20 12:40:52 PM PST 23 3350974836 ps
T310 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2290532189 Dec 20 12:38:39 PM PST 23 Dec 20 12:40:50 PM PST 23 10058381871 ps
T311 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.123619742 Dec 20 12:39:15 PM PST 23 Dec 20 12:40:35 PM PST 23 2502284370 ps
T312 /workspace/coverage/default/25.rom_ctrl_alert_test.2717351303 Dec 20 12:38:49 PM PST 23 Dec 20 12:40:11 PM PST 23 88357246 ps
T313 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1013423853 Dec 20 12:38:33 PM PST 23 Dec 20 12:59:49 PM PST 23 77666036942 ps
T314 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1094581344 Dec 20 12:38:58 PM PST 23 Dec 20 12:40:33 PM PST 23 14655286466 ps
T315 /workspace/coverage/default/49.rom_ctrl_alert_test.2498005290 Dec 20 12:39:25 PM PST 23 Dec 20 12:40:55 PM PST 23 1816737657 ps
T316 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3497546792 Dec 20 12:38:54 PM PST 23 Dec 20 12:40:08 PM PST 23 1181967151 ps
T317 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1687252040 Dec 20 12:38:41 PM PST 23 Dec 20 12:47:06 PM PST 23 45542409425 ps
T318 /workspace/coverage/default/7.rom_ctrl_stress_all.1302996415 Dec 20 12:38:51 PM PST 23 Dec 20 12:40:27 PM PST 23 2058392592 ps
T319 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4098812341 Dec 20 12:39:29 PM PST 23 Dec 20 12:41:02 PM PST 23 1540157639 ps
T320 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3223374429 Dec 20 12:39:30 PM PST 23 Dec 20 12:40:49 PM PST 23 1383994609 ps
T321 /workspace/coverage/default/2.rom_ctrl_smoke.3168455045 Dec 20 12:39:02 PM PST 23 Dec 20 12:40:19 PM PST 23 3131691505 ps
T322 /workspace/coverage/default/49.rom_ctrl_stress_all.3365285473 Dec 20 12:39:25 PM PST 23 Dec 20 12:40:53 PM PST 23 1593083411 ps
T323 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4211742585 Dec 20 12:39:29 PM PST 23 Dec 20 01:36:45 PM PST 23 99944002291 ps
T324 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1888508722 Dec 20 12:39:14 PM PST 23 Dec 20 12:40:36 PM PST 23 1465716836 ps
T325 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2904311571 Dec 20 12:39:34 PM PST 23 Dec 20 12:51:09 PM PST 23 67689754301 ps
T326 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3829729915 Dec 20 12:39:34 PM PST 23 Dec 20 12:40:56 PM PST 23 177207822 ps
T327 /workspace/coverage/default/2.rom_ctrl_alert_test.345373160 Dec 20 12:39:18 PM PST 23 Dec 20 12:40:38 PM PST 23 1627342983 ps
T328 /workspace/coverage/default/18.rom_ctrl_alert_test.1543108539 Dec 20 12:38:56 PM PST 23 Dec 20 12:40:14 PM PST 23 3034938461 ps
T329 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2548542727 Dec 20 12:38:53 PM PST 23 Dec 20 12:41:14 PM PST 23 4849471690 ps
T330 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2233789517 Dec 20 12:39:02 PM PST 23 Dec 20 12:40:21 PM PST 23 501830368 ps
T331 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.640725472 Dec 20 12:38:55 PM PST 23 Dec 20 12:45:12 PM PST 23 125475071781 ps
T332 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.793853465 Dec 20 12:39:32 PM PST 23 Dec 20 12:40:53 PM PST 23 1079526690 ps
T333 /workspace/coverage/default/49.rom_ctrl_smoke.2208924480 Dec 20 12:39:22 PM PST 23 Dec 20 12:41:08 PM PST 23 14516895484 ps
T334 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3507331037 Dec 20 12:39:14 PM PST 23 Dec 20 12:40:27 PM PST 23 1744140142 ps
T335 /workspace/coverage/default/23.rom_ctrl_smoke.319229477 Dec 20 12:38:41 PM PST 23 Dec 20 12:40:14 PM PST 23 3506594301 ps
T336 /workspace/coverage/default/36.rom_ctrl_smoke.2605481511 Dec 20 12:38:48 PM PST 23 Dec 20 12:40:10 PM PST 23 1379181680 ps
T337 /workspace/coverage/default/39.rom_ctrl_alert_test.2395256320 Dec 20 12:38:56 PM PST 23 Dec 20 12:40:11 PM PST 23 290165042 ps
T101 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3611502943 Dec 20 12:39:27 PM PST 23 Dec 20 01:44:51 PM PST 23 108029260687 ps
T338 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.164001823 Dec 20 12:38:55 PM PST 23 Dec 20 12:40:25 PM PST 23 2912407993 ps
T339 /workspace/coverage/default/27.rom_ctrl_stress_all.2384797805 Dec 20 12:39:07 PM PST 23 Dec 20 12:40:20 PM PST 23 154686467 ps
T340 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1859743169 Dec 20 12:38:44 PM PST 23 Dec 20 12:39:59 PM PST 23 192196509 ps
T341 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3856161763 Dec 20 12:38:33 PM PST 23 Dec 20 12:42:24 PM PST 23 10010455666 ps
T342 /workspace/coverage/default/39.rom_ctrl_stress_all.2746205182 Dec 20 12:39:47 PM PST 23 Dec 20 12:41:48 PM PST 23 24137580939 ps
T343 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.47936894 Dec 20 12:39:32 PM PST 23 Dec 20 12:46:57 PM PST 23 110429260132 ps
T344 /workspace/coverage/default/22.rom_ctrl_stress_all.1613175356 Dec 20 12:39:47 PM PST 23 Dec 20 12:41:09 PM PST 23 2640011554 ps
T345 /workspace/coverage/default/16.rom_ctrl_smoke.3921689772 Dec 20 12:38:29 PM PST 23 Dec 20 12:40:05 PM PST 23 3443940182 ps
T346 /workspace/coverage/default/32.rom_ctrl_alert_test.780659895 Dec 20 12:39:20 PM PST 23 Dec 20 12:40:39 PM PST 23 5282523436 ps
T347 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2167808682 Dec 20 12:38:54 PM PST 23 Dec 20 01:19:32 PM PST 23 206006439431 ps
T348 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1852449528 Dec 20 12:38:46 PM PST 23 Dec 20 12:42:45 PM PST 23 55811868566 ps
T349 /workspace/coverage/default/46.rom_ctrl_alert_test.1180267077 Dec 20 12:39:23 PM PST 23 Dec 20 12:40:44 PM PST 23 2130807768 ps
T350 /workspace/coverage/default/0.rom_ctrl_alert_test.1584405010 Dec 20 12:38:11 PM PST 23 Dec 20 12:39:19 PM PST 23 332733338 ps
T351 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4198952467 Dec 20 12:38:55 PM PST 23 Dec 20 12:40:19 PM PST 23 1733032052 ps
T352 /workspace/coverage/default/8.rom_ctrl_alert_test.1679194548 Dec 20 12:38:26 PM PST 23 Dec 20 12:39:35 PM PST 23 1488426430 ps
T353 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.186326689 Dec 20 12:38:46 PM PST 23 Dec 20 12:39:58 PM PST 23 7326590198 ps
T354 /workspace/coverage/default/33.rom_ctrl_smoke.437116409 Dec 20 12:39:19 PM PST 23 Dec 20 12:41:02 PM PST 23 7646251581 ps
T355 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3213486763 Dec 20 12:38:44 PM PST 23 Dec 20 12:41:22 PM PST 23 1740683511 ps
T356 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3658727272 Dec 20 12:38:47 PM PST 23 Dec 20 12:43:09 PM PST 23 47529409039 ps
T357 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1367735992 Dec 20 12:38:31 PM PST 23 Dec 20 12:49:54 PM PST 23 26489603676 ps
T358 /workspace/coverage/default/17.rom_ctrl_smoke.1207553868 Dec 20 12:39:42 PM PST 23 Dec 20 12:41:25 PM PST 23 15323569203 ps
T359 /workspace/coverage/default/41.rom_ctrl_stress_all.3619232646 Dec 20 12:39:24 PM PST 23 Dec 20 12:42:14 PM PST 23 34504108794 ps
T360 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2901269896 Dec 20 12:38:53 PM PST 23 Dec 20 01:21:36 PM PST 23 198202086830 ps
T361 /workspace/coverage/default/29.rom_ctrl_alert_test.4141889393 Dec 20 12:38:48 PM PST 23 Dec 20 12:39:55 PM PST 23 89000100 ps
T362 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2605877035 Dec 20 12:39:16 PM PST 23 Dec 20 12:40:35 PM PST 23 1338552264 ps
T363 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3760225970 Dec 20 12:39:22 PM PST 23 Dec 20 12:59:08 PM PST 23 357129095737 ps
T364 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1475403627 Dec 20 12:39:05 PM PST 23 Dec 20 12:43:21 PM PST 23 16210974140 ps
T365 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.987482991 Dec 20 12:38:43 PM PST 23 Dec 20 12:43:26 PM PST 23 42607271313 ps
T366 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.937176839 Dec 20 12:39:29 PM PST 23 Dec 20 12:40:57 PM PST 23 2354468314 ps
T367 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1803550237 Dec 20 12:39:25 PM PST 23 Dec 20 12:40:49 PM PST 23 1197371000 ps
T368 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4070415451 Dec 20 12:39:46 PM PST 23 Dec 20 12:41:00 PM PST 23 195763043 ps
T369 /workspace/coverage/default/28.rom_ctrl_stress_all.962940922 Dec 20 12:39:41 PM PST 23 Dec 20 12:41:41 PM PST 23 28054907465 ps
T102 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.857308867 Dec 20 12:38:56 PM PST 23 Dec 20 02:03:34 PM PST 23 502774578261 ps
T370 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1257686613 Dec 20 12:39:05 PM PST 23 Dec 20 12:43:15 PM PST 23 40173237590 ps
T371 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3696983700 Dec 20 12:39:22 PM PST 23 Dec 20 12:45:23 PM PST 23 88496933231 ps
T372 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2141955411 Dec 20 12:38:49 PM PST 23 Dec 20 12:40:22 PM PST 23 7229017565 ps
T373 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2996799775 Dec 20 12:38:43 PM PST 23 Dec 20 02:08:27 PM PST 23 67163412605 ps
T374 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.408378944 Dec 20 12:39:29 PM PST 23 Dec 20 12:40:46 PM PST 23 949520362 ps
T375 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2695500024 Dec 20 12:38:44 PM PST 23 Dec 20 12:41:46 PM PST 23 12283801926 ps
T376 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3699880049 Dec 20 12:38:30 PM PST 23 Dec 20 12:39:40 PM PST 23 1742770652 ps
T377 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.752209893 Dec 20 12:38:58 PM PST 23 Dec 20 12:40:06 PM PST 23 105822985 ps
T378 /workspace/coverage/default/20.rom_ctrl_stress_all.2552491860 Dec 20 12:38:35 PM PST 23 Dec 20 12:40:02 PM PST 23 1036613234 ps
T379 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3527989409 Dec 20 12:39:50 PM PST 23 Dec 20 12:54:05 PM PST 23 34853137280 ps
T380 /workspace/coverage/default/45.rom_ctrl_smoke.3974177144 Dec 20 12:39:48 PM PST 23 Dec 20 12:41:25 PM PST 23 18879340522 ps
T381 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3220565425 Dec 20 12:39:09 PM PST 23 Dec 20 12:40:35 PM PST 23 664508675 ps
T382 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2956891504 Dec 20 12:39:09 PM PST 23 Dec 20 12:40:35 PM PST 23 2041569582 ps
T383 /workspace/coverage/default/12.rom_ctrl_alert_test.3920711827 Dec 20 12:39:04 PM PST 23 Dec 20 12:40:26 PM PST 23 5115968278 ps
T384 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1789429276 Dec 20 12:38:55 PM PST 23 Dec 20 12:40:29 PM PST 23 3768079436 ps
T385 /workspace/coverage/default/34.rom_ctrl_smoke.1189403579 Dec 20 12:39:28 PM PST 23 Dec 20 12:40:59 PM PST 23 19779972759 ps
T386 /workspace/coverage/default/30.rom_ctrl_stress_all.1715998955 Dec 20 12:39:03 PM PST 23 Dec 20 12:40:30 PM PST 23 2486742160 ps
T387 /workspace/coverage/default/1.rom_ctrl_stress_all.3210351912 Dec 20 12:38:17 PM PST 23 Dec 20 12:39:27 PM PST 23 2357343041 ps
T388 /workspace/coverage/default/6.rom_ctrl_smoke.3435534637 Dec 20 12:38:23 PM PST 23 Dec 20 12:39:45 PM PST 23 1890153694 ps
T389 /workspace/coverage/default/40.rom_ctrl_smoke.28746792 Dec 20 12:39:46 PM PST 23 Dec 20 12:41:28 PM PST 23 16037681210 ps
T390 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4241971326 Dec 20 12:38:38 PM PST 23 Dec 20 12:40:01 PM PST 23 8594192830 ps
T391 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1649420444 Dec 20 12:39:36 PM PST 23 Dec 20 12:40:57 PM PST 23 1452069845 ps
T392 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.775942460 Dec 20 12:38:56 PM PST 23 Dec 20 12:44:37 PM PST 23 60682108656 ps
T393 /workspace/coverage/default/40.rom_ctrl_stress_all.21577145 Dec 20 12:39:01 PM PST 23 Dec 20 12:40:46 PM PST 23 3730901166 ps
T394 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2350240595 Dec 20 12:38:26 PM PST 23 Dec 20 12:39:37 PM PST 23 6767601980 ps
T395 /workspace/coverage/default/32.rom_ctrl_stress_all.361160198 Dec 20 12:39:47 PM PST 23 Dec 20 12:41:15 PM PST 23 5542398457 ps
T396 /workspace/coverage/default/35.rom_ctrl_smoke.2011064518 Dec 20 12:39:03 PM PST 23 Dec 20 12:40:21 PM PST 23 185452936 ps
T397 /workspace/coverage/default/40.rom_ctrl_alert_test.717592299 Dec 20 12:39:10 PM PST 23 Dec 20 12:40:21 PM PST 23 2334053613 ps
T398 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3662159727 Dec 20 12:38:31 PM PST 23 Dec 20 01:50:47 PM PST 23 51893023207 ps
T399 /workspace/coverage/default/3.rom_ctrl_alert_test.1313159203 Dec 20 12:38:57 PM PST 23 Dec 20 12:40:01 PM PST 23 462856113 ps
T400 /workspace/coverage/default/21.rom_ctrl_smoke.3838932924 Dec 20 12:39:14 PM PST 23 Dec 20 12:40:58 PM PST 23 21364459483 ps
T401 /workspace/coverage/default/8.rom_ctrl_stress_all.3202562916 Dec 20 12:38:29 PM PST 23 Dec 20 12:39:55 PM PST 23 1512045039 ps
T402 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2326588846 Dec 20 12:38:30 PM PST 23 Dec 20 01:37:17 PM PST 23 136642039226 ps
T403 /workspace/coverage/default/43.rom_ctrl_stress_all.1499850262 Dec 20 12:39:28 PM PST 23 Dec 20 12:43:02 PM PST 23 27146407968 ps
T404 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.36104129 Dec 20 12:39:23 PM PST 23 Dec 20 01:24:35 PM PST 23 41836821662 ps
T405 /workspace/coverage/default/12.rom_ctrl_smoke.1102870445 Dec 20 12:38:53 PM PST 23 Dec 20 12:40:20 PM PST 23 7989502614 ps
T406 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3190026325 Dec 20 12:39:18 PM PST 23 Dec 20 12:40:49 PM PST 23 7863442165 ps
T407 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1707004029 Dec 20 12:39:03 PM PST 23 Dec 20 12:40:33 PM PST 23 861470957 ps
T408 /workspace/coverage/default/4.rom_ctrl_alert_test.4151369221 Dec 20 12:38:34 PM PST 23 Dec 20 12:39:44 PM PST 23 1173343041 ps
T409 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.25429815 Dec 20 12:39:49 PM PST 23 Dec 20 12:41:20 PM PST 23 9224864244 ps
T410 /workspace/coverage/default/16.rom_ctrl_alert_test.2497598365 Dec 20 12:38:59 PM PST 23 Dec 20 12:40:13 PM PST 23 6593446941 ps
T411 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2088903652 Dec 20 12:39:32 PM PST 23 Dec 20 12:40:57 PM PST 23 3298350381 ps
T412 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1328463489 Dec 20 12:39:42 PM PST 23 Dec 20 12:48:08 PM PST 23 139796871621 ps
T413 /workspace/coverage/default/0.rom_ctrl_smoke.1641315834 Dec 20 12:38:14 PM PST 23 Dec 20 12:39:42 PM PST 23 2849158608 ps
T414 /workspace/coverage/default/46.rom_ctrl_smoke.652187121 Dec 20 12:38:58 PM PST 23 Dec 20 12:40:32 PM PST 23 6618778276 ps
T415 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1392242489 Dec 20 12:38:41 PM PST 23 Dec 20 01:44:00 PM PST 23 371456437439 ps
T416 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1690245989 Dec 20 12:39:04 PM PST 23 Dec 20 12:40:37 PM PST 23 2884474926 ps
T417 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2691597272 Dec 20 12:38:28 PM PST 23 Dec 20 12:39:36 PM PST 23 3289542431 ps
T418 /workspace/coverage/default/47.rom_ctrl_stress_all.2342004201 Dec 20 12:39:00 PM PST 23 Dec 20 12:40:48 PM PST 23 1099222472 ps
T419 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4130669103 Dec 20 12:39:18 PM PST 23 Dec 20 12:40:52 PM PST 23 2221432720 ps
T420 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.155951827 Dec 20 12:38:51 PM PST 23 Dec 20 03:36:36 PM PST 23 46419173246 ps
T421 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4138362674 Dec 20 12:38:33 PM PST 23 Dec 20 12:46:58 PM PST 23 42612473674 ps
T422 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1060814069 Dec 20 12:39:30 PM PST 23 Dec 20 12:40:51 PM PST 23 757160705 ps
T423 /workspace/coverage/default/3.rom_ctrl_smoke.1247597928 Dec 20 12:38:46 PM PST 23 Dec 20 12:40:07 PM PST 23 1544894899 ps
T424 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2564287992 Dec 20 12:39:54 PM PST 23 Dec 20 12:41:09 PM PST 23 924309272 ps
T425 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2894419685 Dec 20 12:39:02 PM PST 23 Dec 20 01:05:24 PM PST 23 41024908341 ps
T426 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1434773104 Dec 20 12:39:04 PM PST 23 Dec 20 12:40:35 PM PST 23 1209283442 ps
T427 /workspace/coverage/default/11.rom_ctrl_alert_test.1906418548 Dec 20 12:38:34 PM PST 23 Dec 20 12:39:39 PM PST 23 168452940 ps
T428 /workspace/coverage/default/38.rom_ctrl_stress_all.3351436789 Dec 20 12:38:47 PM PST 23 Dec 20 12:40:28 PM PST 23 2458359748 ps
T429 /workspace/coverage/default/21.rom_ctrl_alert_test.781703925 Dec 20 12:38:39 PM PST 23 Dec 20 12:39:51 PM PST 23 89061714 ps
T430 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2998664085 Dec 20 12:38:34 PM PST 23 Dec 20 12:42:26 PM PST 23 12680364781 ps
T431 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2011681098 Dec 20 12:39:07 PM PST 23 Dec 20 12:40:42 PM PST 23 13297473790 ps
T432 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1671611400 Dec 20 12:39:00 PM PST 23 Dec 20 12:42:32 PM PST 23 14689025107 ps
T433 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.885389851 Dec 20 12:27:24 PM PST 23 Dec 20 12:28:17 PM PST 23 7803738077 ps
T434 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1734207332 Dec 20 12:26:50 PM PST 23 Dec 20 12:27:33 PM PST 23 6683322121 ps
T435 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2523713293 Dec 20 12:26:59 PM PST 23 Dec 20 12:27:38 PM PST 23 3129327603 ps
T436 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.768510267 Dec 20 12:26:59 PM PST 23 Dec 20 12:27:36 PM PST 23 516998739 ps
T437 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.355045222 Dec 20 12:26:58 PM PST 23 Dec 20 12:27:48 PM PST 23 2121600453 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3985601185 Dec 20 12:29:08 PM PST 23 Dec 20 12:29:48 PM PST 23 659498963 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4180427898 Dec 20 12:27:07 PM PST 23 Dec 20 12:27:46 PM PST 23 1785058543 ps
T88 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.717094920 Dec 20 12:27:00 PM PST 23 Dec 20 12:27:44 PM PST 23 1486479750 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.927341446 Dec 20 12:29:14 PM PST 23 Dec 20 12:29:45 PM PST 23 421048125 ps
T441 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1484035459 Dec 20 12:27:04 PM PST 23 Dec 20 12:28:46 PM PST 23 1748985430 ps
T442 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3686381208 Dec 20 12:29:19 PM PST 23 Dec 20 12:29:59 PM PST 23 6411463991 ps
T443 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2787926198 Dec 20 12:27:07 PM PST 23 Dec 20 12:27:49 PM PST 23 3134767169 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1164157101 Dec 20 12:26:57 PM PST 23 Dec 20 12:27:44 PM PST 23 3979537641 ps
T445 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2392803049 Dec 20 12:27:05 PM PST 23 Dec 20 12:28:17 PM PST 23 2748024571 ps
T446 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2288412158 Dec 20 12:26:45 PM PST 23 Dec 20 12:27:33 PM PST 23 1493641045 ps
T447 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.917061289 Dec 20 12:27:01 PM PST 23 Dec 20 12:27:44 PM PST 23 7206779987 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3010883628 Dec 20 12:27:23 PM PST 23 Dec 20 12:28:08 PM PST 23 521360494 ps
T449 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1961923019 Dec 20 12:27:11 PM PST 23 Dec 20 12:28:29 PM PST 23 8798747781 ps
T450 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2212590633 Dec 20 12:27:00 PM PST 23 Dec 20 12:27:39 PM PST 23 820794930 ps
T451 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2320953150 Dec 20 12:26:53 PM PST 23 Dec 20 12:27:38 PM PST 23 2058081917 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3285590267 Dec 20 12:27:18 PM PST 23 Dec 20 12:28:03 PM PST 23 1629599967 ps
T453 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3539526913 Dec 20 12:29:04 PM PST 23 Dec 20 12:29:40 PM PST 23 1731347951 ps
T454 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2283397868 Dec 20 12:27:02 PM PST 23 Dec 20 12:27:47 PM PST 23 1691827368 ps
T455 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3947040708 Dec 20 12:27:00 PM PST 23 Dec 20 12:27:41 PM PST 23 1362558979 ps
T83 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2304908793 Dec 20 12:27:03 PM PST 23 Dec 20 12:31:33 PM PST 23 20487472935 ps
T456 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2151101535 Dec 20 12:27:34 PM PST 23 Dec 20 12:28:28 PM PST 23 1747568339 ps
T457 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2394153824 Dec 20 12:26:56 PM PST 23 Dec 20 12:28:18 PM PST 23 1020309213 ps
T458 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3414116233 Dec 20 12:26:54 PM PST 23 Dec 20 12:27:31 PM PST 23 93224378 ps
T459 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1750926221 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:51 PM PST 23 4571374221 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3035805269 Dec 20 12:26:53 PM PST 23 Dec 20 12:27:31 PM PST 23 212265977 ps
T460 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.18738320 Dec 20 12:26:57 PM PST 23 Dec 20 12:27:42 PM PST 23 3839536346 ps
T85 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2730287762 Dec 20 12:28:37 PM PST 23 Dec 20 12:31:01 PM PST 23 8992225945 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2697052729 Dec 20 12:27:28 PM PST 23 Dec 20 12:28:19 PM PST 23 2896347980 ps
T462 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1502263023 Dec 20 12:26:51 PM PST 23 Dec 20 12:29:03 PM PST 23 9536374444 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2995125562 Dec 20 12:26:54 PM PST 23 Dec 20 12:27:37 PM PST 23 1045645976 ps
T464 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3579038863 Dec 20 12:26:58 PM PST 23 Dec 20 12:27:48 PM PST 23 2891307231 ps
T465 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1113390951 Dec 20 12:27:09 PM PST 23 Dec 20 12:27:51 PM PST 23 1949135209 ps
T466 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2532145983 Dec 20 12:27:10 PM PST 23 Dec 20 12:27:51 PM PST 23 2044084184 ps
T105 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3066041997 Dec 20 12:27:02 PM PST 23 Dec 20 12:28:13 PM PST 23 1178002259 ps
T86 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1111581621 Dec 20 12:27:03 PM PST 23 Dec 20 12:27:43 PM PST 23 2467392874 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1560636569 Dec 20 12:26:50 PM PST 23 Dec 20 12:27:25 PM PST 23 332740710 ps
T468 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2711817985 Dec 20 12:26:46 PM PST 23 Dec 20 12:27:31 PM PST 23 1685444125 ps
T469 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1580762486 Dec 20 12:27:11 PM PST 23 Dec 20 12:27:57 PM PST 23 2217783018 ps
T87 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2454692642 Dec 20 12:27:02 PM PST 23 Dec 20 12:29:52 PM PST 23 56035561082 ps
T470 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3860929348 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:45 PM PST 23 1144603713 ps
T471 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2998447086 Dec 20 12:28:37 PM PST 23 Dec 20 12:29:13 PM PST 23 175518852 ps
T472 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3940726723 Dec 20 12:27:06 PM PST 23 Dec 20 12:27:43 PM PST 23 1439875671 ps
T473 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1461285550 Dec 20 12:26:58 PM PST 23 Dec 20 12:27:31 PM PST 23 175610867 ps
T474 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2157626491 Dec 20 12:29:14 PM PST 23 Dec 20 12:31:04 PM PST 23 21914963025 ps
T475 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1622997681 Dec 20 12:27:23 PM PST 23 Dec 20 12:28:15 PM PST 23 2441342400 ps
T476 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1705240561 Dec 20 12:27:09 PM PST 23 Dec 20 12:28:33 PM PST 23 979355723 ps
T477 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.985289271 Dec 20 12:26:52 PM PST 23 Dec 20 12:27:39 PM PST 23 8697386120 ps
T478 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.471432541 Dec 20 12:28:37 PM PST 23 Dec 20 12:29:26 PM PST 23 2188607184 ps
T479 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1500023357 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:49 PM PST 23 2572584303 ps
T480 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.16128698 Dec 20 12:27:24 PM PST 23 Dec 20 12:28:21 PM PST 23 1986759344 ps
T481 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1170099250 Dec 20 12:29:40 PM PST 23 Dec 20 12:30:14 PM PST 23 9006323042 ps
T109 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3605525740 Dec 20 12:27:36 PM PST 23 Dec 20 12:29:32 PM PST 23 3324924398 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2397283110 Dec 20 12:26:57 PM PST 23 Dec 20 12:28:50 PM PST 23 1841993061 ps
T482 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3222791860 Dec 20 12:27:15 PM PST 23 Dec 20 12:28:08 PM PST 23 4060511039 ps
T483 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3422922865 Dec 20 12:27:26 PM PST 23 Dec 20 12:28:21 PM PST 23 7041950895 ps

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.3827796698
Short name T20
Test name
Test status
Simulation time 3932729030 ps
CPU time 11.5 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:27:47 PM PST 23
Peak memory 219432 kb
Host smart-0c615eb5-2fd1-451b-a1dc-96cdb93518b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827796698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.3827796698
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1258817076
Short name T4
Test name
Test status
Simulation time 26181863897 ps
CPU time 260.02 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:44:04 PM PST 23
Peak memory 237428 kb
Host smart-8268ddf1-fd93-477e-9aae-bce5dfdc9a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258817076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1258817076
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.615745332
Short name T26
Test name
Test status
Simulation time 145068335736 ps
CPU time 318.17 seconds
Started Dec 20 12:27:03 PM PST 23
Finished Dec 20 12:32:50 PM PST 23
Peak memory 211320 kb
Host smart-1d3a4c99-6899-4706-83df-347df4134287
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615745332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.615745332
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.536342421
Short name T21
Test name
Test status
Simulation time 1785279832 ps
CPU time 78.86 seconds
Started Dec 20 12:27:26 PM PST 23
Finished Dec 20 12:29:24 PM PST 23
Peak memory 211612 kb
Host smart-8cb1d259-0ac7-4c58-92ff-ff4150898a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536342421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.536342421
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2903119490
Short name T12
Test name
Test status
Simulation time 42304019843 ps
CPU time 3210.95 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 01:33:50 PM PST 23
Peak memory 228296 kb
Host smart-7f616340-4026-4c4b-85e0-61728327a060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903119490 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2903119490
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3887696215
Short name T62
Test name
Test status
Simulation time 905289529 ps
CPU time 78.28 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 212752 kb
Host smart-607fee10-2b82-4994-960c-53f391610596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887696215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3887696215
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3044199793
Short name T35
Test name
Test status
Simulation time 334736448 ps
CPU time 56.42 seconds
Started Dec 20 12:38:27 PM PST 23
Finished Dec 20 12:40:26 PM PST 23
Peak memory 236448 kb
Host smart-cd57676b-d49a-43c2-b17b-1b6e826c13f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044199793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3044199793
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1463041196
Short name T24
Test name
Test status
Simulation time 66996023326 ps
CPU time 261.92 seconds
Started Dec 20 12:27:30 PM PST 23
Finished Dec 20 12:32:30 PM PST 23
Peak memory 211312 kb
Host smart-a8ad70ad-ec55-4049-b8c2-b6919240a6fd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463041196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1463041196
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.717094920
Short name T88
Test name
Test status
Simulation time 1486479750 ps
CPU time 14.86 seconds
Started Dec 20 12:27:00 PM PST 23
Finished Dec 20 12:27:44 PM PST 23
Peak memory 211284 kb
Host smart-6f8fa5c1-f52e-416e-b264-1f0d7909874f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717094920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.717094920
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3031263021
Short name T112
Test name
Test status
Simulation time 661012975 ps
CPU time 9.74 seconds
Started Dec 20 12:26:56 PM PST 23
Finished Dec 20 12:27:37 PM PST 23
Peak memory 215396 kb
Host smart-635914f2-0c1d-481b-8f06-3df4f1cac7c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031263021 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3031263021
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1756210826
Short name T18
Test name
Test status
Simulation time 844476701987 ps
CPU time 4240.25 seconds
Started Dec 20 12:39:37 PM PST 23
Finished Dec 20 01:51:26 PM PST 23
Peak memory 254380 kb
Host smart-37d6d501-4309-4c92-9726-390bf6de139a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756210826 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1756210826
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.756311256
Short name T110
Test name
Test status
Simulation time 6058885657 ps
CPU time 33.54 seconds
Started Dec 20 12:38:36 PM PST 23
Finished Dec 20 12:40:12 PM PST 23
Peak memory 215712 kb
Host smart-a50e362d-5c75-4be9-acb4-c6285f48cb39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756311256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.756311256
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3853665326
Short name T66
Test name
Test status
Simulation time 778355116 ps
CPU time 10.57 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:28:00 PM PST 23
Peak memory 211244 kb
Host smart-054d4981-ba9c-4a6e-8268-721f6a2f67dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853665326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3853665326
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2224591691
Short name T11
Test name
Test status
Simulation time 666032170 ps
CPU time 9.6 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:38 PM PST 23
Peak memory 211252 kb
Host smart-dcbda5ee-e562-48a4-be9c-33c10b9c13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224591691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2224591691
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2511548239
Short name T213
Test name
Test status
Simulation time 2298473008 ps
CPU time 22.94 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 12:40:09 PM PST 23
Peak memory 210972 kb
Host smart-bd8dddb3-1867-451c-aff8-36607db54471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511548239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2511548239
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3630566625
Short name T32
Test name
Test status
Simulation time 3182095569 ps
CPU time 22.53 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:41:11 PM PST 23
Peak memory 211128 kb
Host smart-d9f07a66-7f0e-4001-b5fa-11a6e5ef85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630566625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3630566625
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4080676648
Short name T107
Test name
Test status
Simulation time 548503329 ps
CPU time 40.91 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:30:18 PM PST 23
Peak memory 212000 kb
Host smart-0a8e43d0-87d3-4697-8d98-49f1b406b041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080676648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.4080676648
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3483538408
Short name T15
Test name
Test status
Simulation time 14385114226 ps
CPU time 30.34 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 12:40:10 PM PST 23
Peak memory 213380 kb
Host smart-4d21d4cc-2649-45ee-978c-d64368b631a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483538408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3483538408
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3133963717
Short name T47
Test name
Test status
Simulation time 4231781008 ps
CPU time 122.95 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 224676 kb
Host smart-c2c426f2-def7-4dfd-b475-9519a4707221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133963717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3133963717
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3865829773
Short name T151
Test name
Test status
Simulation time 2190600977 ps
CPU time 10.84 seconds
Started Dec 20 12:38:32 PM PST 23
Finished Dec 20 12:39:52 PM PST 23
Peak memory 211072 kb
Host smart-54504110-c4c5-49f1-8307-45894486e6ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865829773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3865829773
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2397283110
Short name T104
Test name
Test status
Simulation time 1841993061 ps
CPU time 83.15 seconds
Started Dec 20 12:26:57 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 211460 kb
Host smart-9f712f26-1b24-4a11-bfe6-a78798c836ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397283110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2397283110
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3605525740
Short name T109
Test name
Test status
Simulation time 3324924398 ps
CPU time 81.11 seconds
Started Dec 20 12:27:36 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 211532 kb
Host smart-d9babf0e-034f-4ae5-81b2-aaf0c88aa531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605525740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3605525740
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2426235788
Short name T40
Test name
Test status
Simulation time 212197649 ps
CPU time 107.29 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:41:58 PM PST 23
Peak memory 236548 kb
Host smart-2f56e8da-64eb-4988-8d90-5d6043a38755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426235788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2426235788
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.3611502943
Short name T101
Test name
Test status
Simulation time 108029260687 ps
CPU time 3854.76 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 01:44:51 PM PST 23
Peak memory 251924 kb
Host smart-ad2b5c40-89c7-46ca-b759-e94c52605e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611502943 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.3611502943
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3035805269
Short name T84
Test name
Test status
Simulation time 212265977 ps
CPU time 5.89 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 211332 kb
Host smart-9a0913dd-83bd-4900-9636-7ffa11d2e85a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035805269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3035805269
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1750926221
Short name T459
Test name
Test status
Simulation time 4571374221 ps
CPU time 11.7 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 211308 kb
Host smart-90b9a3df-aaf6-48b2-8ac3-e8eaf8ed65f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750926221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1750926221
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.3907692647
Short name T124
Test name
Test status
Simulation time 1184386588 ps
CPU time 11.1 seconds
Started Dec 20 12:26:56 PM PST 23
Finished Dec 20 12:27:37 PM PST 23
Peak memory 211276 kb
Host smart-d1c68beb-2b90-475a-b07a-0cf5004ddcfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907692647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.3907692647
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3947040708
Short name T455
Test name
Test status
Simulation time 1362558979 ps
CPU time 12.13 seconds
Started Dec 20 12:27:00 PM PST 23
Finished Dec 20 12:27:41 PM PST 23
Peak memory 211188 kb
Host smart-ecde27bb-ecd0-444b-b6f9-9944b39b5b00
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947040708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3947040708
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.263983461
Short name T121
Test name
Test status
Simulation time 15639453155 ps
CPU time 14.87 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:28:05 PM PST 23
Peak memory 211468 kb
Host smart-e6462e63-2a52-4e13-8769-50142810aa13
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263983461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
263983461
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1966066143
Short name T70
Test name
Test status
Simulation time 18962365949 ps
CPU time 206.8 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:31:02 PM PST 23
Peak memory 211328 kb
Host smart-20d4aad4-10f0-43ce-a4ad-4c7d8f570033
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966066143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1966066143
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2523713293
Short name T435
Test name
Test status
Simulation time 3129327603 ps
CPU time 9.37 seconds
Started Dec 20 12:26:59 PM PST 23
Finished Dec 20 12:27:38 PM PST 23
Peak memory 211428 kb
Host smart-8ac9f17d-3dc2-41ae-ae67-cd57161da8a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523713293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2523713293
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3414116233
Short name T458
Test name
Test status
Simulation time 93224378 ps
CPU time 7.14 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 219460 kb
Host smart-4e7bf1f9-2f96-4ce2-83b3-6c290dce4420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414116233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3414116233
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.3595180473
Short name T81
Test name
Test status
Simulation time 378642580 ps
CPU time 4.26 seconds
Started Dec 20 12:27:17 PM PST 23
Finished Dec 20 12:27:59 PM PST 23
Peak memory 211312 kb
Host smart-d925728c-f430-4b7c-b638-b81015b35187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595180473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.3595180473
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.993736077
Short name T82
Test name
Test status
Simulation time 614904251 ps
CPU time 5.91 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:27:55 PM PST 23
Peak memory 211376 kb
Host smart-223d37c4-1f9d-49d5-b842-f1a4c63c6107
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993736077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.993736077
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3514065064
Short name T79
Test name
Test status
Simulation time 881863569 ps
CPU time 12.6 seconds
Started Dec 20 12:26:55 PM PST 23
Finished Dec 20 12:27:37 PM PST 23
Peak memory 211300 kb
Host smart-f865ef33-d71b-4099-a102-e0e0b6cc7994
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514065064 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3514065064
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2697052729
Short name T461
Test name
Test status
Simulation time 2896347980 ps
CPU time 13.11 seconds
Started Dec 20 12:27:28 PM PST 23
Finished Dec 20 12:28:19 PM PST 23
Peak memory 213940 kb
Host smart-f5cf0936-41f5-4be2-ae04-c8f934aec7a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697052729 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2697052729
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1769821036
Short name T74
Test name
Test status
Simulation time 85608148 ps
CPU time 4.41 seconds
Started Dec 20 12:27:28 PM PST 23
Finished Dec 20 12:28:10 PM PST 23
Peak memory 211248 kb
Host smart-ba4e458a-4dd1-4ad0-accb-066c5e0bb54a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769821036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1769821036
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1920833993
Short name T89
Test name
Test status
Simulation time 88846287 ps
CPU time 4.35 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:43 PM PST 23
Peak memory 211252 kb
Host smart-b8b77189-2ef9-4b02-9aea-2dce4f3ef819
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920833993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1920833993
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.880801801
Short name T122
Test name
Test status
Simulation time 5841158608 ps
CPU time 11.8 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:49 PM PST 23
Peak memory 210884 kb
Host smart-a0026105-b2b1-417a-a49c-11717af41ace
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880801801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
880801801
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2730287762
Short name T85
Test name
Test status
Simulation time 8992225945 ps
CPU time 112.79 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:31:01 PM PST 23
Peak memory 209892 kb
Host smart-2069aab3-e99e-4397-b755-f3e544e46d3d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730287762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2730287762
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1911637339
Short name T136
Test name
Test status
Simulation time 253033386 ps
CPU time 6.23 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:27:30 PM PST 23
Peak memory 211372 kb
Host smart-7a8172c0-1ccf-4bd7-b706-117757be51df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911637339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1911637339
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1164157101
Short name T444
Test name
Test status
Simulation time 3979537641 ps
CPU time 17.64 seconds
Started Dec 20 12:26:57 PM PST 23
Finished Dec 20 12:27:44 PM PST 23
Peak memory 219520 kb
Host smart-48901fb6-0b28-42b3-9aff-c170354edb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164157101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1164157101
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.140761803
Short name T134
Test name
Test status
Simulation time 1003087841 ps
CPU time 76.67 seconds
Started Dec 20 12:27:00 PM PST 23
Finished Dec 20 12:28:46 PM PST 23
Peak memory 212684 kb
Host smart-f5939bc3-30c9-4c65-8910-e3d9e7cb9f72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140761803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.140761803
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.3095473837
Short name T117
Test name
Test status
Simulation time 2157526260 ps
CPU time 15.98 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 213568 kb
Host smart-11e46b68-b49d-42e6-93d0-ae5da689abfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095473837 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.3095473837
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2330624155
Short name T99
Test name
Test status
Simulation time 3738893042 ps
CPU time 9.51 seconds
Started Dec 20 12:29:32 PM PST 23
Finished Dec 20 12:30:02 PM PST 23
Peak memory 211168 kb
Host smart-7aa8fbd0-0ded-4b17-952d-9e2bdefa757f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330624155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2330624155
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2394153824
Short name T457
Test name
Test status
Simulation time 1020309213 ps
CPU time 52.25 seconds
Started Dec 20 12:26:56 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 211228 kb
Host smart-97358d66-d7ca-4f97-8d2d-dd844145f227
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394153824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2394153824
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.355045222
Short name T437
Test name
Test status
Simulation time 2121600453 ps
CPU time 16.98 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:48 PM PST 23
Peak memory 211264 kb
Host smart-aa170612-48db-4493-8cd2-7bb4190fe6f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355045222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.355045222
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2392803049
Short name T445
Test name
Test status
Simulation time 2748024571 ps
CPU time 42.36 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 212596 kb
Host smart-3f88f4ac-6855-4703-9cbd-3dcc59a22f6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392803049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2392803049
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3065212481
Short name T22
Test name
Test status
Simulation time 4549100096 ps
CPU time 11.21 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 211652 kb
Host smart-8a7dddc0-dcef-4c8d-a64c-b804f4892584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065212481 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3065212481
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.209246860
Short name T75
Test name
Test status
Simulation time 168420081 ps
CPU time 4.39 seconds
Started Dec 20 12:26:55 PM PST 23
Finished Dec 20 12:27:29 PM PST 23
Peak memory 211276 kb
Host smart-6614d12c-9cd6-48ed-b388-7ff6b211a42d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209246860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.209246860
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1705240561
Short name T476
Test name
Test status
Simulation time 979355723 ps
CPU time 52.4 seconds
Started Dec 20 12:27:09 PM PST 23
Finished Dec 20 12:28:33 PM PST 23
Peak memory 211216 kb
Host smart-8b7bbf11-ae18-4140-9652-79bab8cf1596
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705240561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1705240561
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3510831101
Short name T28
Test name
Test status
Simulation time 86336349 ps
CPU time 4.25 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 210868 kb
Host smart-346084bc-7e8b-4d8b-8271-4a7a2b0444ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510831101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3510831101
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.104232990
Short name T63
Test name
Test status
Simulation time 6372875749 ps
CPU time 17.01 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:28:05 PM PST 23
Peak memory 219548 kb
Host smart-5d5e5f41-dd04-4d6a-93ef-b616d68ffaad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104232990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.104232990
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1657636123
Short name T73
Test name
Test status
Simulation time 8046816620 ps
CPU time 50.02 seconds
Started Dec 20 12:26:56 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 212624 kb
Host smart-ae8e0392-21c9-4c96-ac1f-043cbce07cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657636123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1657636123
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3789315787
Short name T128
Test name
Test status
Simulation time 615599877 ps
CPU time 4.92 seconds
Started Dec 20 12:26:59 PM PST 23
Finished Dec 20 12:27:35 PM PST 23
Peak memory 214864 kb
Host smart-f51ab77c-a87a-449c-bf63-268f3a9189ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789315787 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3789315787
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1401764151
Short name T133
Test name
Test status
Simulation time 1196495505 ps
CPU time 11.58 seconds
Started Dec 20 12:27:21 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 211252 kb
Host smart-94f73e2d-8376-4fff-8e6e-70d55c836c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401764151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1401764151
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.154513904
Short name T52
Test name
Test status
Simulation time 6122825266 ps
CPU time 11.83 seconds
Started Dec 20 12:27:17 PM PST 23
Finished Dec 20 12:28:07 PM PST 23
Peak memory 219440 kb
Host smart-f96449a1-6a21-44a6-b93b-ff557cb7f2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154513904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.154513904
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1734207332
Short name T434
Test name
Test status
Simulation time 6683322121 ps
CPU time 13.34 seconds
Started Dec 20 12:26:50 PM PST 23
Finished Dec 20 12:27:33 PM PST 23
Peak memory 219548 kb
Host smart-48d9df23-760a-4ff9-b871-b3144cb2a021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734207332 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1734207332
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1678915852
Short name T80
Test name
Test status
Simulation time 20397875045 ps
CPU time 16.7 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:28:05 PM PST 23
Peak memory 211472 kb
Host smart-ccb18b53-bd16-4351-ba9b-00a226c3648a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678915852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1678915852
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3276959273
Short name T135
Test name
Test status
Simulation time 4802272722 ps
CPU time 11.5 seconds
Started Dec 20 12:27:37 PM PST 23
Finished Dec 20 12:28:23 PM PST 23
Peak memory 211344 kb
Host smart-e712f0b1-ff3b-46bd-9e3c-420a94ece549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276959273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3276959273
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.471432541
Short name T478
Test name
Test status
Simulation time 2188607184 ps
CPU time 18.26 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 218168 kb
Host smart-2a1de88c-282c-4ee3-8238-67af1c0743df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471432541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.471432541
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1484035459
Short name T441
Test name
Test status
Simulation time 1748985430 ps
CPU time 73.38 seconds
Started Dec 20 12:27:04 PM PST 23
Finished Dec 20 12:28:46 PM PST 23
Peak memory 211460 kb
Host smart-90141676-d112-4331-99d1-6b38ddf71210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484035459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1484035459
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.3422922865
Short name T483
Test name
Test status
Simulation time 7041950895 ps
CPU time 16.46 seconds
Started Dec 20 12:27:26 PM PST 23
Finished Dec 20 12:28:21 PM PST 23
Peak memory 216076 kb
Host smart-c7d8c5db-daab-4fe8-bf88-984f955a4d1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422922865 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.3422922865
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.3300899474
Short name T94
Test name
Test status
Simulation time 7754264107 ps
CPU time 15.73 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:53 PM PST 23
Peak memory 210900 kb
Host smart-b9b93f63-c4e0-4de4-9fc6-08a852ed7a42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300899474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.3300899474
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.735310566
Short name T72
Test name
Test status
Simulation time 4039474863 ps
CPU time 52.75 seconds
Started Dec 20 12:27:03 PM PST 23
Finished Dec 20 12:28:24 PM PST 23
Peak memory 211320 kb
Host smart-4ca18e7e-7a45-4a3f-8bae-d898b33a30fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735310566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.735310566
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3686381208
Short name T442
Test name
Test status
Simulation time 6411463991 ps
CPU time 15.57 seconds
Started Dec 20 12:29:19 PM PST 23
Finished Dec 20 12:29:59 PM PST 23
Peak memory 211064 kb
Host smart-e3e5dd97-186b-42e1-a245-2874552f1580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686381208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3686381208
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3985601185
Short name T438
Test name
Test status
Simulation time 659498963 ps
CPU time 10.24 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 219000 kb
Host smart-0128d2ed-346b-40cc-843b-aa7a4805c3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985601185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3985601185
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.4073994870
Short name T119
Test name
Test status
Simulation time 2139832188 ps
CPU time 84.22 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:28:47 PM PST 23
Peak memory 212196 kb
Host smart-511caa4f-5031-460c-9f95-3d9b4c869cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073994870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.4073994870
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.503610647
Short name T111
Test name
Test status
Simulation time 256976134 ps
CPU time 6.55 seconds
Started Dec 20 12:27:35 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 212996 kb
Host smart-60bd2696-4c36-487a-a998-30fb492f14fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503610647 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.503610647
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.927341446
Short name T440
Test name
Test status
Simulation time 421048125 ps
CPU time 5.51 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:29:45 PM PST 23
Peak memory 210852 kb
Host smart-b29b1ff8-66a2-4c39-b7f5-d595a3e9390b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927341446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.927341446
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.589372956
Short name T67
Test name
Test status
Simulation time 10414567833 ps
CPU time 120.19 seconds
Started Dec 20 12:27:02 PM PST 23
Finished Dec 20 12:29:31 PM PST 23
Peak memory 211332 kb
Host smart-cdde81fa-cb57-4354-b1eb-95162840b091
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589372956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.589372956
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.18738320
Short name T460
Test name
Test status
Simulation time 3839536346 ps
CPU time 15.44 seconds
Started Dec 20 12:26:57 PM PST 23
Finished Dec 20 12:27:42 PM PST 23
Peak memory 211468 kb
Host smart-b26b0016-850b-4faa-9062-eb3cf17f3d2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18738320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ct
rl_same_csr_outstanding.18738320
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3579038863
Short name T464
Test name
Test status
Simulation time 2891307231 ps
CPU time 19.98 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:48 PM PST 23
Peak memory 219624 kb
Host smart-35d3ecd1-ae5f-40df-b111-f9bbffe8d5c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579038863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3579038863
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1717676643
Short name T23
Test name
Test status
Simulation time 14485417911 ps
CPU time 82.8 seconds
Started Dec 20 12:27:34 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 211880 kb
Host smart-20e03541-162b-4eaa-b0a5-eb26f0a17bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717676643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1717676643
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.751088878
Short name T61
Test name
Test status
Simulation time 2755439222 ps
CPU time 12.31 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:29:52 PM PST 23
Peak memory 218944 kb
Host smart-71e0219b-254d-474f-ba69-a5d6705e278e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751088878 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.751088878
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3375967720
Short name T138
Test name
Test status
Simulation time 2442899712 ps
CPU time 10.33 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:50 PM PST 23
Peak memory 211340 kb
Host smart-c311b2d2-cbc5-4298-bcb8-5c31495de625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375967720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3375967720
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1359535216
Short name T69
Test name
Test status
Simulation time 62036730731 ps
CPU time 268.33 seconds
Started Dec 20 12:27:33 PM PST 23
Finished Dec 20 12:32:38 PM PST 23
Peak memory 211348 kb
Host smart-fa626aa7-4472-4ce5-b963-5e16d1d924fa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359535216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1359535216
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3405970949
Short name T98
Test name
Test status
Simulation time 85568650 ps
CPU time 4.16 seconds
Started Dec 20 12:29:06 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 210860 kb
Host smart-8eea775f-985f-4550-b4b8-6131b81e3cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405970949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3405970949
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2711817985
Short name T468
Test name
Test status
Simulation time 1685444125 ps
CPU time 14.66 seconds
Started Dec 20 12:26:46 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 219656 kb
Host smart-757acde6-cf09-4f88-80c5-387abdc776a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711817985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2711817985
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1961923019
Short name T449
Test name
Test status
Simulation time 8798747781 ps
CPU time 44.58 seconds
Started Dec 20 12:27:11 PM PST 23
Finished Dec 20 12:28:29 PM PST 23
Peak memory 212764 kb
Host smart-4ad400b7-f4a7-465d-82f8-26d9948e21f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961923019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1961923019
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3539526913
Short name T453
Test name
Test status
Simulation time 1731347951 ps
CPU time 4.36 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 212076 kb
Host smart-b400dc9e-b414-4660-af2c-51cc8e5dad86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539526913 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3539526913
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1113390951
Short name T465
Test name
Test status
Simulation time 1949135209 ps
CPU time 10.35 seconds
Started Dec 20 12:27:09 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 211272 kb
Host smart-729219dd-3474-4627-8890-f76c18aa0f7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113390951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1113390951
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.2157626491
Short name T474
Test name
Test status
Simulation time 21914963025 ps
CPU time 83.96 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 210748 kb
Host smart-49808b6e-bfba-4161-935e-845b039fe0ce
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157626491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.2157626491
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3222791860
Short name T482
Test name
Test status
Simulation time 4060511039 ps
CPU time 15.59 seconds
Started Dec 20 12:27:15 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 211356 kb
Host smart-859fa1b9-07ed-484b-b076-250d6554c915
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222791860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3222791860
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.674062852
Short name T53
Test name
Test status
Simulation time 1413534091 ps
CPU time 14.14 seconds
Started Dec 20 12:27:11 PM PST 23
Finished Dec 20 12:28:00 PM PST 23
Peak memory 219468 kb
Host smart-5aa6772f-7eec-4674-af04-010d5a8cf05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674062852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.674062852
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3055541618
Short name T132
Test name
Test status
Simulation time 8602750879 ps
CPU time 42.41 seconds
Started Dec 20 12:27:06 PM PST 23
Finished Dec 20 12:28:19 PM PST 23
Peak memory 212924 kb
Host smart-b3c778ee-1c7d-4c8d-83cb-0488c3f718bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055541618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3055541618
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.823481209
Short name T56
Test name
Test status
Simulation time 8343108247 ps
CPU time 15.72 seconds
Started Dec 20 12:27:06 PM PST 23
Finished Dec 20 12:27:52 PM PST 23
Peak memory 214444 kb
Host smart-d1810465-cbaf-4a90-a7e7-f430f9de28ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823481209 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.823481209
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2532145983
Short name T466
Test name
Test status
Simulation time 2044084184 ps
CPU time 7.81 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 211276 kb
Host smart-81b7c432-4653-4e5f-abaf-a3a7ef5e7505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532145983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2532145983
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3160590950
Short name T76
Test name
Test status
Simulation time 3900595807 ps
CPU time 53.52 seconds
Started Dec 20 12:27:14 PM PST 23
Finished Dec 20 12:28:44 PM PST 23
Peak memory 211296 kb
Host smart-b2365806-aed2-4bb4-a8ac-560dc33e807e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160590950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3160590950
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.153755474
Short name T131
Test name
Test status
Simulation time 361679465 ps
CPU time 4.56 seconds
Started Dec 20 12:27:38 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 211264 kb
Host smart-4395d956-7359-4f66-a315-7a33656ea321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153755474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_c
trl_same_csr_outstanding.153755474
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1580762486
Short name T469
Test name
Test status
Simulation time 2217783018 ps
CPU time 10.54 seconds
Started Dec 20 12:27:11 PM PST 23
Finished Dec 20 12:27:57 PM PST 23
Peak memory 219564 kb
Host smart-7305ee34-1cf4-43d1-a21f-aed613aca28e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580762486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1580762486
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3899746433
Short name T58
Test name
Test status
Simulation time 666831104 ps
CPU time 76.71 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:28:54 PM PST 23
Peak memory 212580 kb
Host smart-653bff31-063e-4021-9399-f45ec7740877
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899746433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3899746433
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.4180427898
Short name T439
Test name
Test status
Simulation time 1785058543 ps
CPU time 8.46 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:46 PM PST 23
Peak memory 214484 kb
Host smart-4a2e087e-1b77-4b0f-9b70-159307fdbf9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180427898 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.4180427898
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3074371281
Short name T123
Test name
Test status
Simulation time 2120376663 ps
CPU time 16.31 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:56 PM PST 23
Peak memory 209516 kb
Host smart-9638cd44-cf0d-4447-8ec2-6823bf2cd24f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074371281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3074371281
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.57387758
Short name T25
Test name
Test status
Simulation time 42292800009 ps
CPU time 391.62 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:34:19 PM PST 23
Peak memory 219500 kb
Host smart-f903fc09-55ce-4c9a-b8d6-eb709593ab11
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57387758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pas
sthru_mem_tl_intg_err.57387758
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.2035188893
Short name T91
Test name
Test status
Simulation time 4977746894 ps
CPU time 11.72 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:55 PM PST 23
Peak memory 211356 kb
Host smart-d53c3d1d-737b-4808-bd2c-ca077d80778d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035188893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.2035188893
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2151101535
Short name T456
Test name
Test status
Simulation time 1747568339 ps
CPU time 18.24 seconds
Started Dec 20 12:27:34 PM PST 23
Finished Dec 20 12:28:28 PM PST 23
Peak memory 219524 kb
Host smart-116d447d-de76-46b9-b199-657c82904477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151101535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2151101535
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3523027766
Short name T137
Test name
Test status
Simulation time 4813855708 ps
CPU time 48.7 seconds
Started Dec 20 12:27:28 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 212536 kb
Host smart-978005c2-3d5b-41a3-b6d9-ce4b8312c9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523027766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3523027766
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1584004912
Short name T95
Test name
Test status
Simulation time 4352167757 ps
CPU time 9.18 seconds
Started Dec 20 12:26:49 PM PST 23
Finished Dec 20 12:27:28 PM PST 23
Peak memory 211252 kb
Host smart-7b640b64-b451-425d-9045-40c67267932f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584004912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1584004912
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.768510267
Short name T436
Test name
Test status
Simulation time 516998739 ps
CPU time 7.69 seconds
Started Dec 20 12:26:59 PM PST 23
Finished Dec 20 12:27:36 PM PST 23
Peak memory 211120 kb
Host smart-13d21f1d-e439-485f-8669-589d58a918f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768510267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.768510267
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1111581621
Short name T86
Test name
Test status
Simulation time 2467392874 ps
CPU time 11.53 seconds
Started Dec 20 12:27:03 PM PST 23
Finished Dec 20 12:27:43 PM PST 23
Peak memory 211344 kb
Host smart-9f719e58-9467-41c4-aa32-ff2cf5881c8d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111581621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1111581621
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3757738954
Short name T57
Test name
Test status
Simulation time 2444628890 ps
CPU time 8.45 seconds
Started Dec 20 12:27:04 PM PST 23
Finished Dec 20 12:27:45 PM PST 23
Peak memory 214164 kb
Host smart-a872bd52-6310-4bd4-b80c-352c1dee90f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757738954 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3757738954
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2782171264
Short name T129
Test name
Test status
Simulation time 320302077 ps
CPU time 4.42 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:42 PM PST 23
Peak memory 211232 kb
Host smart-96ab3a42-6eee-4aaa-be62-2ce6c33540ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782171264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2782171264
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.985289271
Short name T477
Test name
Test status
Simulation time 8697386120 ps
CPU time 16.91 seconds
Started Dec 20 12:26:52 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 211372 kb
Host smart-7c111c79-c3e6-4564-95a5-7a4da218253a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985289271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.985289271
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3285590267
Short name T452
Test name
Test status
Simulation time 1629599967 ps
CPU time 6.89 seconds
Started Dec 20 12:27:18 PM PST 23
Finished Dec 20 12:28:03 PM PST 23
Peak memory 211380 kb
Host smart-c195e5ea-0b6f-4adf-ba83-7879758c5e7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285590267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3285590267
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2995125562
Short name T463
Test name
Test status
Simulation time 1045645976 ps
CPU time 12.56 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:27:37 PM PST 23
Peak memory 211276 kb
Host smart-ad67eaf2-ef71-47b8-8375-8dd777d5d801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995125562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.2995125562
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3536309529
Short name T64
Test name
Test status
Simulation time 1762675484 ps
CPU time 17.25 seconds
Started Dec 20 12:27:38 PM PST 23
Finished Dec 20 12:28:30 PM PST 23
Peak memory 219584 kb
Host smart-e78e3da5-eac1-48f1-8362-482338cd131e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536309529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3536309529
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1220647197
Short name T103
Test name
Test status
Simulation time 2310372331 ps
CPU time 85.65 seconds
Started Dec 20 12:26:54 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 211572 kb
Host smart-b2b89eab-e50e-4797-adf8-6ce01f9f0e33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220647197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1220647197
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1170099250
Short name T481
Test name
Test status
Simulation time 9006323042 ps
CPU time 15.29 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:14 PM PST 23
Peak memory 211152 kb
Host smart-468c62d7-c0be-4310-b9f9-d1c0e9b80a4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170099250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1170099250
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1936123897
Short name T97
Test name
Test status
Simulation time 14476421266 ps
CPU time 15.63 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:14 PM PST 23
Peak memory 211152 kb
Host smart-78942cd0-65d7-4b2a-80c9-0fd0424b5469
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936123897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1936123897
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.917061289
Short name T447
Test name
Test status
Simulation time 7206779987 ps
CPU time 14.09 seconds
Started Dec 20 12:27:01 PM PST 23
Finished Dec 20 12:27:44 PM PST 23
Peak memory 211328 kb
Host smart-442c2627-ef95-488c-b508-d72915d056ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917061289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re
set.917061289
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3009878772
Short name T125
Test name
Test status
Simulation time 88130832 ps
CPU time 4.58 seconds
Started Dec 20 12:26:59 PM PST 23
Finished Dec 20 12:27:33 PM PST 23
Peak memory 212148 kb
Host smart-b9243c26-c352-4104-adae-d662e20b4843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009878772 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3009878772
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3860929348
Short name T470
Test name
Test status
Simulation time 1144603713 ps
CPU time 6.21 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:45 PM PST 23
Peak memory 211224 kb
Host smart-06994f05-f66a-44da-8abc-2cf7803fd4b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860929348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.3860929348
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2316272619
Short name T120
Test name
Test status
Simulation time 997292685 ps
CPU time 7.34 seconds
Started Dec 20 12:27:32 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 211308 kb
Host smart-f2e48ae5-5a3d-4346-ba58-4b0607d0d5c1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316272619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2316272619
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2907807516
Short name T127
Test name
Test status
Simulation time 2775470926 ps
CPU time 6.65 seconds
Started Dec 20 12:27:01 PM PST 23
Finished Dec 20 12:27:36 PM PST 23
Peak memory 211204 kb
Host smart-80d6d634-14f8-4f94-b5d5-e6a3165a9f74
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907807516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2907807516
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2304908793
Short name T83
Test name
Test status
Simulation time 20487472935 ps
CPU time 241.16 seconds
Started Dec 20 12:27:03 PM PST 23
Finished Dec 20 12:31:33 PM PST 23
Peak memory 211336 kb
Host smart-7dcbdcfc-8fcf-469a-ac9f-cc569eba5c41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304908793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2304908793
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.376744973
Short name T59
Test name
Test status
Simulation time 1124294638 ps
CPU time 13.28 seconds
Started Dec 20 12:27:27 PM PST 23
Finished Dec 20 12:28:19 PM PST 23
Peak memory 211408 kb
Host smart-e63340fe-98fb-460c-a336-fab48497818e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376744973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.376744973
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1560636569
Short name T467
Test name
Test status
Simulation time 332740710 ps
CPU time 6.6 seconds
Started Dec 20 12:26:50 PM PST 23
Finished Dec 20 12:27:25 PM PST 23
Peak memory 214004 kb
Host smart-f6d28b81-3315-473e-b8f6-d6759d194e93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560636569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.1560636569
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1349402339
Short name T118
Test name
Test status
Simulation time 629566101 ps
CPU time 77.87 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:28:55 PM PST 23
Peak memory 211828 kb
Host smart-24c363f8-6afb-404a-9c41-002b8cd875c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349402339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1349402339
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.4020702979
Short name T96
Test name
Test status
Simulation time 330443277 ps
CPU time 6.56 seconds
Started Dec 20 12:27:02 PM PST 23
Finished Dec 20 12:27:38 PM PST 23
Peak memory 211244 kb
Host smart-3e80492d-711d-45db-8b7c-096351f2351b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020702979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.4020702979
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2787926198
Short name T443
Test name
Test status
Simulation time 3134767169 ps
CPU time 11.3 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:49 PM PST 23
Peak memory 211340 kb
Host smart-01a92cb9-07e7-4e8c-a23a-d58683c31118
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787926198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2787926198
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2055237247
Short name T29
Test name
Test status
Simulation time 94074354 ps
CPU time 7.83 seconds
Started Dec 20 12:27:03 PM PST 23
Finished Dec 20 12:27:40 PM PST 23
Peak memory 211232 kb
Host smart-d2da7d94-ac4f-4c41-a75f-be3b7daba04c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055237247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2055237247
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3731671594
Short name T55
Test name
Test status
Simulation time 5795452713 ps
CPU time 12.86 seconds
Started Dec 20 12:27:19 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 219356 kb
Host smart-64c3d18a-f6cd-48cf-9db2-cc255c17f4ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731671594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3731671594
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3010883628
Short name T448
Test name
Test status
Simulation time 521360494 ps
CPU time 5.86 seconds
Started Dec 20 12:27:23 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 211296 kb
Host smart-92a02df4-4d06-49ac-aac4-34aad9a15cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010883628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3010883628
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.4021221169
Short name T126
Test name
Test status
Simulation time 1376478857 ps
CPU time 6.19 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:28:00 PM PST 23
Peak memory 211172 kb
Host smart-b09bc2f4-6b2c-4180-b5f0-c6709cdc6310
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021221169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.4021221169
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1461285550
Short name T473
Test name
Test status
Simulation time 175610867 ps
CPU time 4.19 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:31 PM PST 23
Peak memory 211236 kb
Host smart-a8e2d4a9-1d58-4612-964c-d9bda3a471df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461285550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1461285550
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1327429026
Short name T71
Test name
Test status
Simulation time 30473624152 ps
CPU time 90.84 seconds
Started Dec 20 12:29:21 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 211000 kb
Host smart-8633f2eb-0886-4ff0-9b09-722de58abaf5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327429026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1327429026
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1841279853
Short name T139
Test name
Test status
Simulation time 3364586023 ps
CPU time 13.37 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:28:00 PM PST 23
Peak memory 211360 kb
Host smart-50162212-d66f-4490-9fe3-bf262924d68f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841279853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.1841279853
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2288412158
Short name T446
Test name
Test status
Simulation time 1493641045 ps
CPU time 16.95 seconds
Started Dec 20 12:26:45 PM PST 23
Finished Dec 20 12:27:33 PM PST 23
Peak memory 219528 kb
Host smart-a70f8056-c6d8-4a3a-90c1-0bbe4f746788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288412158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2288412158
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.881254109
Short name T108
Test name
Test status
Simulation time 9264057896 ps
CPU time 76.39 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:30:32 PM PST 23
Peak memory 210268 kb
Host smart-31fde502-aa15-4ba5-b09a-d5aae8d3a718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881254109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.881254109
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2400155631
Short name T115
Test name
Test status
Simulation time 32857572169 ps
CPU time 13.59 seconds
Started Dec 20 12:27:01 PM PST 23
Finished Dec 20 12:27:43 PM PST 23
Peak memory 213236 kb
Host smart-ce6ec7e8-2e82-493a-887d-b905225066b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400155631 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2400155631
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3616041011
Short name T27
Test name
Test status
Simulation time 3668858590 ps
CPU time 14.5 seconds
Started Dec 20 12:27:14 PM PST 23
Finished Dec 20 12:28:05 PM PST 23
Peak memory 211152 kb
Host smart-c3a5d312-0102-4b0d-bd0f-00a4f842c325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616041011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3616041011
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.264984774
Short name T60
Test name
Test status
Simulation time 32467047989 ps
CPU time 117.62 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 211376 kb
Host smart-5610f919-eec9-48c0-9279-0c8387a7ac61
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264984774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.264984774
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.459115129
Short name T92
Test name
Test status
Simulation time 223790679 ps
CPU time 5.94 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:34 PM PST 23
Peak memory 211352 kb
Host smart-5f10ef92-5882-4f3d-910c-47efba30b1d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459115129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.459115129
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2283397868
Short name T454
Test name
Test status
Simulation time 1691827368 ps
CPU time 15.94 seconds
Started Dec 20 12:27:02 PM PST 23
Finished Dec 20 12:27:47 PM PST 23
Peak memory 219536 kb
Host smart-8121ce05-66dc-481a-9c99-17c356ed5583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283397868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2283397868
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1500023357
Short name T479
Test name
Test status
Simulation time 2572584303 ps
CPU time 9.87 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:49 PM PST 23
Peak memory 214896 kb
Host smart-327a86f7-b86b-4ac2-8fc7-93cb58f5cfed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500023357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1500023357
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2320953150
Short name T451
Test name
Test status
Simulation time 2058081917 ps
CPU time 15.37 seconds
Started Dec 20 12:26:53 PM PST 23
Finished Dec 20 12:27:38 PM PST 23
Peak memory 211244 kb
Host smart-e2a294eb-8a05-4b5a-ad79-192bd6c3f46f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320953150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2320953150
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2454692642
Short name T87
Test name
Test status
Simulation time 56035561082 ps
CPU time 140.82 seconds
Started Dec 20 12:27:02 PM PST 23
Finished Dec 20 12:29:52 PM PST 23
Peak memory 211316 kb
Host smart-d2bf5e66-5c8b-403a-a5b7-1807023db130
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454692642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2454692642
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.885389851
Short name T433
Test name
Test status
Simulation time 7803738077 ps
CPU time 13.57 seconds
Started Dec 20 12:27:24 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 211332 kb
Host smart-1fc6cff4-ef7e-49f7-9718-ac50743d70a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885389851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.885389851
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2787503724
Short name T130
Test name
Test status
Simulation time 150317185 ps
CPU time 7.35 seconds
Started Dec 20 12:29:19 PM PST 23
Finished Dec 20 12:29:51 PM PST 23
Peak memory 219076 kb
Host smart-11c7c55a-ad25-480b-847c-835f7163a89e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787503724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2787503724
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3109067289
Short name T113
Test name
Test status
Simulation time 371446337 ps
CPU time 4.68 seconds
Started Dec 20 12:27:29 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 213980 kb
Host smart-9c90f24d-30e7-4ec9-b921-0b225dc40626
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109067289 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3109067289
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2998447086
Short name T471
Test name
Test status
Simulation time 175518852 ps
CPU time 4.13 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 209412 kb
Host smart-b3dac741-49cc-4e46-8e96-4708c7219129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998447086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2998447086
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3933036895
Short name T68
Test name
Test status
Simulation time 7459844070 ps
CPU time 100.63 seconds
Started Dec 20 12:26:50 PM PST 23
Finished Dec 20 12:28:59 PM PST 23
Peak memory 211332 kb
Host smart-3b4499c7-a13c-419e-b495-0434d29dd49b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933036895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3933036895
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3657864440
Short name T140
Test name
Test status
Simulation time 671283278 ps
CPU time 8.36 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:27:55 PM PST 23
Peak memory 211348 kb
Host smart-7f1b0d74-3006-406b-aa39-7ed61ffd2a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657864440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3657864440
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.565537166
Short name T54
Test name
Test status
Simulation time 293735804 ps
CPU time 8.32 seconds
Started Dec 20 12:26:57 PM PST 23
Finished Dec 20 12:27:35 PM PST 23
Peak memory 219536 kb
Host smart-841dab6c-ae5b-4ced-871a-b2247872f896
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565537166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.565537166
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3940726723
Short name T472
Test name
Test status
Simulation time 1439875671 ps
CPU time 7.6 seconds
Started Dec 20 12:27:06 PM PST 23
Finished Dec 20 12:27:43 PM PST 23
Peak memory 214608 kb
Host smart-85562477-285b-43ce-bc57-d9c2103717c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940726723 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3940726723
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1622997681
Short name T475
Test name
Test status
Simulation time 2441342400 ps
CPU time 12.62 seconds
Started Dec 20 12:27:23 PM PST 23
Finished Dec 20 12:28:15 PM PST 23
Peak memory 211384 kb
Host smart-fd6b62aa-9e4b-49e9-a0fe-e15b2206aaf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622997681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1622997681
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1012897848
Short name T90
Test name
Test status
Simulation time 4348802566 ps
CPU time 8.26 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:36 PM PST 23
Peak memory 211256 kb
Host smart-9d01a5bd-636e-4ca5-afc8-82d52558775f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012897848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1012897848
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3052006096
Short name T114
Test name
Test status
Simulation time 6705201024 ps
CPU time 18.37 seconds
Started Dec 20 12:26:58 PM PST 23
Finished Dec 20 12:27:46 PM PST 23
Peak memory 219504 kb
Host smart-81953e4c-439c-43df-bce6-bfb2a09ae038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052006096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3052006096
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3159132682
Short name T106
Test name
Test status
Simulation time 11824938714 ps
CPU time 43.36 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:53 PM PST 23
Peak memory 210656 kb
Host smart-ecbeac0c-ad70-4d1a-92dd-7ce5d513d992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159132682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3159132682
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2212590633
Short name T450
Test name
Test status
Simulation time 820794930 ps
CPU time 9.77 seconds
Started Dec 20 12:27:00 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 214588 kb
Host smart-918b81d3-0d6f-4258-996d-85db2b5f7815
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212590633 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2212590633
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1387501783
Short name T65
Test name
Test status
Simulation time 85560902 ps
CPU time 4.31 seconds
Started Dec 20 12:26:52 PM PST 23
Finished Dec 20 12:27:26 PM PST 23
Peak memory 211268 kb
Host smart-a40487dc-d37a-4452-aabb-38a6be3ecea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387501783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1387501783
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1502263023
Short name T462
Test name
Test status
Simulation time 9536374444 ps
CPU time 104.05 seconds
Started Dec 20 12:26:51 PM PST 23
Finished Dec 20 12:29:03 PM PST 23
Peak memory 211268 kb
Host smart-1c76d8a7-6c64-48e5-93fd-e69cd1d8c859
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502263023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1502263023
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.16128698
Short name T480
Test name
Test status
Simulation time 1986759344 ps
CPU time 17.39 seconds
Started Dec 20 12:27:24 PM PST 23
Finished Dec 20 12:28:21 PM PST 23
Peak memory 211276 kb
Host smart-01653616-86b4-4183-b30f-503cd3b78495
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.16128698
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.988684163
Short name T116
Test name
Test status
Simulation time 1341241725 ps
CPU time 14.69 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:52 PM PST 23
Peak memory 219472 kb
Host smart-fc228c7e-d237-437e-89b4-02d04a73873f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988684163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.988684163
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3066041997
Short name T105
Test name
Test status
Simulation time 1178002259 ps
CPU time 41.99 seconds
Started Dec 20 12:27:02 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 212588 kb
Host smart-818b9438-5f75-403d-a49b-5ea45c6f3648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066041997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3066041997
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1584405010
Short name T350
Test name
Test status
Simulation time 332733338 ps
CPU time 5.52 seconds
Started Dec 20 12:38:11 PM PST 23
Finished Dec 20 12:39:19 PM PST 23
Peak memory 211012 kb
Host smart-8293c878-4422-4d4e-b7fa-b8c7dafa364a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584405010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1584405010
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.873792919
Short name T225
Test name
Test status
Simulation time 13656178083 ps
CPU time 269.15 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:44:46 PM PST 23
Peak memory 237504 kb
Host smart-333acf90-1c85-4f61-8ec0-5d715a68208a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873792919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.873792919
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1434773104
Short name T426
Test name
Test status
Simulation time 1209283442 ps
CPU time 12 seconds
Started Dec 20 12:39:04 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 210796 kb
Host smart-72c876de-14dc-4ed3-8bb2-57b3bff6a263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1434773104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1434773104
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.603971004
Short name T37
Test name
Test status
Simulation time 12514547210 ps
CPU time 67.51 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:41:27 PM PST 23
Peak memory 229420 kb
Host smart-b877726d-9093-415b-8976-8b495edff824
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603971004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.603971004
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1641315834
Short name T413
Test name
Test status
Simulation time 2849158608 ps
CPU time 25.76 seconds
Started Dec 20 12:38:14 PM PST 23
Finished Dec 20 12:39:42 PM PST 23
Peak memory 212184 kb
Host smart-7d4b37b1-7be6-4f69-a2cb-0b4b549e8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641315834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1641315834
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2729652624
Short name T222
Test name
Test status
Simulation time 3324135889 ps
CPU time 35.53 seconds
Started Dec 20 12:39:13 PM PST 23
Finished Dec 20 12:40:58 PM PST 23
Peak memory 212140 kb
Host smart-cfcf6197-bf1b-46fd-aebf-b2091323812b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729652624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2729652624
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2996799775
Short name T373
Test name
Test status
Simulation time 67163412605 ps
CPU time 5307.8 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 02:08:27 PM PST 23
Peak memory 235524 kb
Host smart-de9bd610-2b1f-4d85-8e09-7a0bc6c35cef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996799775 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2996799775
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2838489510
Short name T244
Test name
Test status
Simulation time 337906708 ps
CPU time 5.56 seconds
Started Dec 20 12:38:32 PM PST 23
Finished Dec 20 12:39:47 PM PST 23
Peak memory 210796 kb
Host smart-5d4c9f35-fb81-480d-908c-2ebca1ab52aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838489510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2838489510
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2960280551
Short name T179
Test name
Test status
Simulation time 4491760943 ps
CPU time 12.49 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:39:55 PM PST 23
Peak memory 211028 kb
Host smart-55857b24-2489-45c2-848b-6b98c7faa45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2960280551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2960280551
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2575827317
Short name T36
Test name
Test status
Simulation time 256060123 ps
CPU time 108.91 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:42:48 PM PST 23
Peak memory 236316 kb
Host smart-435413bf-3ac9-41bc-b3c5-105647b06b12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575827317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2575827317
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.2835236524
Short name T252
Test name
Test status
Simulation time 15103593210 ps
CPU time 32.58 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 213228 kb
Host smart-aa5da98f-49b5-4b4b-a896-dc755b684804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835236524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2835236524
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.3210351912
Short name T387
Test name
Test status
Simulation time 2357343041 ps
CPU time 7.36 seconds
Started Dec 20 12:38:17 PM PST 23
Finished Dec 20 12:39:27 PM PST 23
Peak memory 211000 kb
Host smart-f532cf67-a659-4b71-a22a-b716eff16ef1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210351912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.3210351912
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3880606368
Short name T154
Test name
Test status
Simulation time 28808268048 ps
CPU time 935.75 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:56:05 PM PST 23
Peak memory 235680 kb
Host smart-c224827b-a87b-4b65-816a-e037cf12e034
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880606368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3880606368
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.270973006
Short name T281
Test name
Test status
Simulation time 2894275334 ps
CPU time 9.12 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:40:05 PM PST 23
Peak memory 211036 kb
Host smart-939d294d-a967-4adc-b4ad-7ccfe5a035e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270973006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.270973006
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1671611400
Short name T432
Test name
Test status
Simulation time 14689025107 ps
CPU time 150.47 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:42:32 PM PST 23
Peak memory 236528 kb
Host smart-9ad31128-a3aa-4ec2-8fb0-13bd244ee923
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671611400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1671611400
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2724710388
Short name T183
Test name
Test status
Simulation time 4022622007 ps
CPU time 31.86 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:40:16 PM PST 23
Peak memory 210976 kb
Host smart-aa8622d5-67ab-4677-b264-1666fd39ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724710388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2724710388
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2511965625
Short name T241
Test name
Test status
Simulation time 283131942 ps
CPU time 6.64 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:16 PM PST 23
Peak memory 211020 kb
Host smart-e1dfcb25-3f5f-40b3-918f-7571fbce66ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511965625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2511965625
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2717696293
Short name T256
Test name
Test status
Simulation time 3367957677 ps
CPU time 28.84 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:40:04 PM PST 23
Peak memory 212300 kb
Host smart-d150539a-084f-42ca-a73a-d1690a558135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717696293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2717696293
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.532545228
Short name T227
Test name
Test status
Simulation time 1181959960 ps
CPU time 21.44 seconds
Started Dec 20 12:38:36 PM PST 23
Finished Dec 20 12:39:53 PM PST 23
Peak memory 213112 kb
Host smart-dff124a2-6fcb-4d10-abce-6944baac41ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532545228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.532545228
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4154031065
Short name T285
Test name
Test status
Simulation time 149727010953 ps
CPU time 3380.45 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 01:37:18 PM PST 23
Peak memory 232968 kb
Host smart-b3faa17d-7f0e-490a-bc33-6ea15e742546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154031065 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4154031065
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1906418548
Short name T427
Test name
Test status
Simulation time 168452940 ps
CPU time 4.25 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:39:39 PM PST 23
Peak memory 210824 kb
Host smart-83ed5636-a003-42cf-a912-7508823211e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906418548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1906418548
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.4083115948
Short name T282
Test name
Test status
Simulation time 164564064554 ps
CPU time 375.95 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:46:07 PM PST 23
Peak memory 237228 kb
Host smart-9090fc36-8a3e-4849-923c-9fd536876d30
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083115948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.4083115948
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2593429189
Short name T274
Test name
Test status
Simulation time 8237757109 ps
CPU time 31.11 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:40:03 PM PST 23
Peak memory 211436 kb
Host smart-5c6c1645-19dd-48ab-b148-35f311d09413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593429189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2593429189
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1859743169
Short name T340
Test name
Test status
Simulation time 192196509 ps
CPU time 5.61 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:39:59 PM PST 23
Peak memory 210700 kb
Host smart-b69983b8-bcab-4d0a-951b-6739c8d543d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1859743169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1859743169
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.1094713809
Short name T205
Test name
Test status
Simulation time 180636505 ps
CPU time 10.43 seconds
Started Dec 20 12:38:50 PM PST 23
Finished Dec 20 12:40:03 PM PST 23
Peak memory 212192 kb
Host smart-0315690c-5cb7-4281-a792-aeafd2fc9c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094713809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.1094713809
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2524127492
Short name T266
Test name
Test status
Simulation time 22210369404 ps
CPU time 76.02 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:40:59 PM PST 23
Peak memory 219012 kb
Host smart-f48f1c15-4e03-4e94-9d6b-e68d1322763e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524127492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2524127492
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2326588846
Short name T402
Test name
Test status
Simulation time 136642039226 ps
CPU time 3447.38 seconds
Started Dec 20 12:38:30 PM PST 23
Finished Dec 20 01:37:17 PM PST 23
Peak memory 235608 kb
Host smart-9a8f69da-45c2-4cb5-8065-397b2217aed6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326588846 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2326588846
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3920711827
Short name T383
Test name
Test status
Simulation time 5115968278 ps
CPU time 16.12 seconds
Started Dec 20 12:39:04 PM PST 23
Finished Dec 20 12:40:26 PM PST 23
Peak memory 210996 kb
Host smart-b03ea14f-b957-4be9-b814-675a36098896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920711827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3920711827
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.949405702
Short name T269
Test name
Test status
Simulation time 171869041103 ps
CPU time 289.06 seconds
Started Dec 20 12:39:45 PM PST 23
Finished Dec 20 12:45:38 PM PST 23
Peak memory 235748 kb
Host smart-b344669e-300f-4351-bdf0-f4e3facd2681
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949405702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.949405702
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2359669058
Short name T198
Test name
Test status
Simulation time 755046845 ps
CPU time 9.76 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:40:31 PM PST 23
Peak memory 211020 kb
Host smart-0e47ad3d-f97d-4709-82ff-42fdd277d892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359669058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2359669058
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.123619742
Short name T311
Test name
Test status
Simulation time 2502284370 ps
CPU time 13.18 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 211016 kb
Host smart-a7d64214-6873-42b8-840c-d3f26bc44ed4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123619742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.123619742
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1102870445
Short name T405
Test name
Test status
Simulation time 7989502614 ps
CPU time 28.29 seconds
Started Dec 20 12:38:53 PM PST 23
Finished Dec 20 12:40:20 PM PST 23
Peak memory 213328 kb
Host smart-276a7dbb-9719-441c-8060-add6a68cb29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102870445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1102870445
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2662392083
Short name T147
Test name
Test status
Simulation time 10051716868 ps
CPU time 29.67 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:41:14 PM PST 23
Peak memory 212912 kb
Host smart-bb557dbe-e8d9-46a6-a049-a43f5b777f1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662392083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2662392083
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2522915565
Short name T232
Test name
Test status
Simulation time 1476727408 ps
CPU time 13.05 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:40:37 PM PST 23
Peak memory 211052 kb
Host smart-97bb847d-74e8-4be5-a807-aac3ae61f438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522915565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2522915565
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4138362674
Short name T421
Test name
Test status
Simulation time 42612473674 ps
CPU time 445.91 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:46:58 PM PST 23
Peak memory 237484 kb
Host smart-e1014bef-098b-4936-a903-52f2259d30ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138362674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4138362674
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3829729915
Short name T326
Test name
Test status
Simulation time 177207822 ps
CPU time 9.67 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:40:56 PM PST 23
Peak memory 211288 kb
Host smart-90bab1e9-87c7-43eb-b95f-4a6486993ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829729915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3829729915
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.4198952467
Short name T351
Test name
Test status
Simulation time 1733032052 ps
CPU time 10.57 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:19 PM PST 23
Peak memory 210896 kb
Host smart-adc7f49b-8012-4007-bc84-68e5ef92174d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4198952467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.4198952467
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3085838465
Short name T78
Test name
Test status
Simulation time 2678715379 ps
CPU time 31.33 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:40:01 PM PST 23
Peak memory 212624 kb
Host smart-a9b974ed-1758-4a2e-a4f8-3364611b808d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085838465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3085838465
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.504746193
Short name T44
Test name
Test status
Simulation time 283362656 ps
CPU time 15.63 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 12:40:45 PM PST 23
Peak memory 215192 kb
Host smart-43599e8b-75a9-464b-b8c8-6cd852abe24a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504746193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.504746193
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.988942504
Short name T160
Test name
Test status
Simulation time 37095933496 ps
CPU time 2372.09 seconds
Started Dec 20 12:38:36 PM PST 23
Finished Dec 20 01:19:10 PM PST 23
Peak memory 232412 kb
Host smart-d4d3ba73-9d32-4ffe-8e1a-9d8467296c80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988942504 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.988942504
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.86029651
Short name T257
Test name
Test status
Simulation time 332702759 ps
CPU time 4.33 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:39:46 PM PST 23
Peak memory 210888 kb
Host smart-5acdb140-cde4-4db9-aeba-19c3391335d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86029651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.86029651
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3696983700
Short name T371
Test name
Test status
Simulation time 88496933231 ps
CPU time 292.69 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:45:23 PM PST 23
Peak memory 233628 kb
Host smart-26d022c5-4e48-4978-b683-1d066d47412e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696983700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3696983700
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3190026325
Short name T406
Test name
Test status
Simulation time 7863442165 ps
CPU time 20.89 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:49 PM PST 23
Peak memory 211260 kb
Host smart-ceb73c3c-6a75-4157-a348-1bd3941f2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190026325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3190026325
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1078398267
Short name T305
Test name
Test status
Simulation time 2257316064 ps
CPU time 8.82 seconds
Started Dec 20 12:38:40 PM PST 23
Finished Dec 20 12:40:07 PM PST 23
Peak memory 210924 kb
Host smart-9824daed-41e0-4368-9cc8-83c301663f11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1078398267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1078398267
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.132770494
Short name T280
Test name
Test status
Simulation time 4930039028 ps
CPU time 29.33 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:40:13 PM PST 23
Peak memory 212912 kb
Host smart-faad9bde-5a38-48d9-bb6c-2340dcc5063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132770494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.132770494
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1373073032
Short name T212
Test name
Test status
Simulation time 3321362408 ps
CPU time 10.1 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 211068 kb
Host smart-a9bd65f0-8ecd-45e3-a4ca-64afb5a7efdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373073032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1373073032
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1367735992
Short name T357
Test name
Test status
Simulation time 26489603676 ps
CPU time 623.25 seconds
Started Dec 20 12:38:31 PM PST 23
Finished Dec 20 12:49:54 PM PST 23
Peak memory 230200 kb
Host smart-1a345246-43fc-4d73-928d-e905773e0841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367735992 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.1367735992
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.3856161763
Short name T341
Test name
Test status
Simulation time 10010455666 ps
CPU time 171.48 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:42:24 PM PST 23
Peak memory 228088 kb
Host smart-d429dc3a-1f6f-4a94-9a2b-ac1940eeb3f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856161763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.3856161763
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2728215506
Short name T223
Test name
Test status
Simulation time 7887064132 ps
CPU time 32.73 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:41:05 PM PST 23
Peak memory 211388 kb
Host smart-0dcb4ae2-f35b-4122-98f9-51de0c0cf8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728215506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2728215506
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1122658400
Short name T235
Test name
Test status
Simulation time 1322527440 ps
CPU time 12.56 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 210860 kb
Host smart-165a7dc2-eee7-492e-8204-d6fbffbfe1a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122658400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1122658400
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.567032370
Short name T242
Test name
Test status
Simulation time 941512936 ps
CPU time 9.95 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 212596 kb
Host smart-11629388-a6dd-4f13-8b47-ccc4cf263fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567032370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.567032370
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2929807220
Short name T261
Test name
Test status
Simulation time 8458417683 ps
CPU time 44.44 seconds
Started Dec 20 12:38:49 PM PST 23
Finished Dec 20 12:40:43 PM PST 23
Peak memory 216980 kb
Host smart-8e2a003c-9920-4053-8337-4b6bb52b3a26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929807220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2929807220
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2824029923
Short name T303
Test name
Test status
Simulation time 68835674663 ps
CPU time 2586.51 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 01:22:59 PM PST 23
Peak memory 243884 kb
Host smart-a1c7c6be-cbd2-4c63-ab3a-13fccb420076
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824029923 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2824029923
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2497598365
Short name T410
Test name
Test status
Simulation time 6593446941 ps
CPU time 14.04 seconds
Started Dec 20 12:38:59 PM PST 23
Finished Dec 20 12:40:13 PM PST 23
Peak memory 211076 kb
Host smart-ef51751f-77f4-4ad8-80e6-da0f0aecca46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497598365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2497598365
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.1210610499
Short name T199
Test name
Test status
Simulation time 15234874460 ps
CPU time 173.07 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:43:08 PM PST 23
Peak memory 237532 kb
Host smart-68f3826b-b971-44c3-b419-297d2fde7e4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210610499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.1210610499
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4241971326
Short name T390
Test name
Test status
Simulation time 8594192830 ps
CPU time 22.83 seconds
Started Dec 20 12:38:38 PM PST 23
Finished Dec 20 12:40:01 PM PST 23
Peak memory 211356 kb
Host smart-763a1fda-afc0-4b4f-a70e-73a2301ae4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241971326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4241971326
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.408378944
Short name T374
Test name
Test status
Simulation time 949520362 ps
CPU time 10.65 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:40:46 PM PST 23
Peak memory 210940 kb
Host smart-e5351c4e-30fa-4204-ba9d-8bbe95ca3a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408378944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.408378944
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3921689772
Short name T345
Test name
Test status
Simulation time 3443940182 ps
CPU time 37.12 seconds
Started Dec 20 12:38:29 PM PST 23
Finished Dec 20 12:40:05 PM PST 23
Peak memory 212052 kb
Host smart-31add6af-37c4-4bdb-9028-933769afdfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921689772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3921689772
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1013423853
Short name T313
Test name
Test status
Simulation time 77666036942 ps
CPU time 1202.37 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:59:49 PM PST 23
Peak memory 234356 kb
Host smart-7156aabc-f7e0-4290-a6c7-4d4ab3be5045
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013423853 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1013423853
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2791646795
Short name T279
Test name
Test status
Simulation time 1222047572 ps
CPU time 11.48 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:40:15 PM PST 23
Peak memory 210968 kb
Host smart-14b63e1b-0c18-416f-a04e-336e1fb72e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791646795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2791646795
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.47936894
Short name T343
Test name
Test status
Simulation time 110429260132 ps
CPU time 370.43 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:46:57 PM PST 23
Peak memory 237368 kb
Host smart-94156e30-907c-4a73-98cb-a104017bcc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47936894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_co
rrupt_sig_fatal_chk.47936894
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.195086195
Short name T294
Test name
Test status
Simulation time 1348361733 ps
CPU time 17.94 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 12:39:55 PM PST 23
Peak memory 211012 kb
Host smart-60beb7ec-6dfc-4eb9-83b4-aac6aad71ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195086195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.195086195
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2823370713
Short name T229
Test name
Test status
Simulation time 2870473163 ps
CPU time 10.94 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:41:00 PM PST 23
Peak memory 210876 kb
Host smart-b8a50b31-2aab-4d89-afea-6dabfcbc468d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2823370713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2823370713
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1207553868
Short name T358
Test name
Test status
Simulation time 15323569203 ps
CPU time 38.95 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 212956 kb
Host smart-c5868b7a-c69d-4a6c-b50f-4b2a122b614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207553868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1207553868
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1787209295
Short name T226
Test name
Test status
Simulation time 1668264746 ps
CPU time 22.18 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:40:04 PM PST 23
Peak memory 214116 kb
Host smart-62458eb4-d2ee-4e86-9a3c-83d4f902e5ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787209295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1787209295
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3662159727
Short name T398
Test name
Test status
Simulation time 51893023207 ps
CPU time 4265.32 seconds
Started Dec 20 12:38:31 PM PST 23
Finished Dec 20 01:50:47 PM PST 23
Peak memory 235556 kb
Host smart-4bffa889-55cc-4bcd-8c33-dec2789684e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662159727 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3662159727
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1543108539
Short name T328
Test name
Test status
Simulation time 3034938461 ps
CPU time 12.98 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:14 PM PST 23
Peak memory 211016 kb
Host smart-7deb3b9b-29ef-4ba1-8050-b0288ca11d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543108539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1543108539
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1813578886
Short name T192
Test name
Test status
Simulation time 2646348940 ps
CPU time 151.63 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:43:19 PM PST 23
Peak memory 237484 kb
Host smart-2ad5772c-d132-4a2e-bbda-727b93f1a0ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813578886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1813578886
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.372251861
Short name T214
Test name
Test status
Simulation time 14545899678 ps
CPU time 28.31 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 211404 kb
Host smart-4f747680-4e30-4259-a412-578257cbe1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372251861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.372251861
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.855354087
Short name T292
Test name
Test status
Simulation time 23359020371 ps
CPU time 16.94 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:40:20 PM PST 23
Peak memory 210908 kb
Host smart-4c45d05b-6f9b-4324-a094-068ace95dfce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855354087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.855354087
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.4138373033
Short name T270
Test name
Test status
Simulation time 9632542010 ps
CPU time 22.52 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:40:59 PM PST 23
Peak memory 213184 kb
Host smart-a54ab4a8-47b7-4641-ae61-b574c35983e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138373033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.4138373033
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3573013194
Short name T309
Test name
Test status
Simulation time 3350974836 ps
CPU time 46.32 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:40:52 PM PST 23
Peak memory 214960 kb
Host smart-7e4066e7-124f-4077-b929-378d00dd415a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573013194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3573013194
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.1382197251
Short name T1
Test name
Test status
Simulation time 361358910 ps
CPU time 4.34 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:39:51 PM PST 23
Peak memory 211000 kb
Host smart-698deec1-dee2-4ad7-837e-d8e21d8aedbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382197251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1382197251
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.127393925
Short name T180
Test name
Test status
Simulation time 2176501492 ps
CPU time 74.07 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:42:13 PM PST 23
Peak memory 236596 kb
Host smart-c9a47d1f-1421-4db9-80a2-249417a09560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127393925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.127393925
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2142802872
Short name T5
Test name
Test status
Simulation time 99764730 ps
CPU time 5.89 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 12:39:45 PM PST 23
Peak memory 210964 kb
Host smart-83704a22-0ce4-47aa-b3b7-2e0598d4de18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142802872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2142802872
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3713367758
Short name T175
Test name
Test status
Simulation time 2410287083 ps
CPU time 30.19 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:39:59 PM PST 23
Peak memory 212912 kb
Host smart-d663c4cb-a560-415d-9039-093ed1833991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713367758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3713367758
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.814216931
Short name T200
Test name
Test status
Simulation time 9442787470 ps
CPU time 24.69 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 12:40:08 PM PST 23
Peak memory 211476 kb
Host smart-666361ad-f8a2-40d5-833e-683c7b3013c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814216931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.814216931
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.363636022
Short name T236
Test name
Test status
Simulation time 64982181600 ps
CPU time 608.14 seconds
Started Dec 20 12:38:45 PM PST 23
Finished Dec 20 12:49:51 PM PST 23
Peak memory 227300 kb
Host smart-41b2a42b-03e5-4b0e-8e4b-dc9fd3d152f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363636022 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.363636022
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.345373160
Short name T327
Test name
Test status
Simulation time 1627342983 ps
CPU time 9.18 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:38 PM PST 23
Peak memory 210828 kb
Host smart-0cb7df86-ebb0-4c18-bd18-c0033fac6ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345373160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.345373160
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1845668972
Short name T304
Test name
Test status
Simulation time 4924921589 ps
CPU time 201.77 seconds
Started Dec 20 12:38:30 PM PST 23
Finished Dec 20 12:43:20 PM PST 23
Peak memory 233432 kb
Host smart-d5d7b211-884a-4e32-b0ce-d11ac718b859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845668972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1845668972
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1789429276
Short name T384
Test name
Test status
Simulation time 3768079436 ps
CPU time 31.07 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:29 PM PST 23
Peak memory 210984 kb
Host smart-93b894e1-9b46-4038-aa11-3181941be10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789429276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1789429276
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.1690245989
Short name T416
Test name
Test status
Simulation time 2884474926 ps
CPU time 13.8 seconds
Started Dec 20 12:39:04 PM PST 23
Finished Dec 20 12:40:37 PM PST 23
Peak memory 211060 kb
Host smart-caea8a55-9cbe-4bcb-9836-45d0ed464287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690245989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.1690245989
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3168455045
Short name T321
Test name
Test status
Simulation time 3131691505 ps
CPU time 15.76 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:40:19 PM PST 23
Peak memory 212656 kb
Host smart-786d65bf-ac94-40dd-acc0-0342e98d9231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168455045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3168455045
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.974049297
Short name T42
Test name
Test status
Simulation time 30743563090 ps
CPU time 83.97 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 216668 kb
Host smart-60c885e6-f465-4ff1-b219-c6a3937624e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974049297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.974049297
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.3159329631
Short name T6
Test name
Test status
Simulation time 361522229 ps
CPU time 4.32 seconds
Started Dec 20 12:38:40 PM PST 23
Finished Dec 20 12:39:45 PM PST 23
Peak memory 210968 kb
Host smart-0b1dec85-9d6c-4bc0-9038-178b9b10ac2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159329631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.3159329631
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3424383942
Short name T8
Test name
Test status
Simulation time 21244068072 ps
CPU time 131.64 seconds
Started Dec 20 12:38:37 PM PST 23
Finished Dec 20 12:42:02 PM PST 23
Peak memory 237464 kb
Host smart-dd5453a3-ebb9-4d5d-88ae-8eee27d0d107
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424383942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3424383942
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2743114296
Short name T148
Test name
Test status
Simulation time 9948036445 ps
CPU time 25.14 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:53 PM PST 23
Peak memory 211372 kb
Host smart-a3b2771a-0f14-4148-a578-62ff1b8c3d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743114296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2743114296
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1858245393
Short name T275
Test name
Test status
Simulation time 2275464168 ps
CPU time 15.51 seconds
Started Dec 20 12:38:39 PM PST 23
Finished Dec 20 12:39:57 PM PST 23
Peak memory 210992 kb
Host smart-a25dbe1a-745d-4260-8c5f-9ced7e6374f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1858245393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1858245393
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2552491860
Short name T378
Test name
Test status
Simulation time 1036613234 ps
CPU time 19.92 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:40:02 PM PST 23
Peak memory 212232 kb
Host smart-f431e2f8-973a-4ff6-8833-90cfc888b648
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552491860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2552491860
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.781703925
Short name T429
Test name
Test status
Simulation time 89061714 ps
CPU time 4.48 seconds
Started Dec 20 12:38:39 PM PST 23
Finished Dec 20 12:39:51 PM PST 23
Peak memory 210916 kb
Host smart-8765a4df-04f9-4415-a49e-73bf3d57a110
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781703925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.781703925
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1746330552
Short name T50
Test name
Test status
Simulation time 3402436829 ps
CPU time 111.13 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:42:16 PM PST 23
Peak memory 228040 kb
Host smart-0d6d26a1-8892-4c50-a26f-a8cfe5bca255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746330552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1746330552
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1070439159
Short name T293
Test name
Test status
Simulation time 463071080 ps
CPU time 12.48 seconds
Started Dec 20 12:40:44 PM PST 23
Finished Dec 20 12:41:59 PM PST 23
Peak memory 211004 kb
Host smart-3132219e-e130-48fb-bcaf-74ec5093d3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070439159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1070439159
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2605877035
Short name T362
Test name
Test status
Simulation time 1338552264 ps
CPU time 7.49 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 210920 kb
Host smart-0cd41e16-17cd-4ab9-b8a9-562aee56a768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605877035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2605877035
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3838932924
Short name T400
Test name
Test status
Simulation time 21364459483 ps
CPU time 31.21 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:58 PM PST 23
Peak memory 213316 kb
Host smart-e4e7b7a5-4974-4b28-bc89-1a3c1e1e4f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838932924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3838932924
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3965866407
Short name T77
Test name
Test status
Simulation time 313916337 ps
CPU time 8.71 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:31 PM PST 23
Peak memory 210896 kb
Host smart-d7c287c5-e3e0-4211-a977-aaf1020011a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965866407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3965866407
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.3143434369
Short name T267
Test name
Test status
Simulation time 8456417279 ps
CPU time 15.41 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:40:48 PM PST 23
Peak memory 211156 kb
Host smart-115a51f0-4893-459b-b684-ecb68ee338b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143434369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.3143434369
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.2290532189
Short name T310
Test name
Test status
Simulation time 10058381871 ps
CPU time 71.7 seconds
Started Dec 20 12:38:39 PM PST 23
Finished Dec 20 12:40:50 PM PST 23
Peak memory 236876 kb
Host smart-49060ffd-7c4a-49d7-8956-850dae95481e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290532189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.2290532189
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1546067490
Short name T2
Test name
Test status
Simulation time 1278783318 ps
CPU time 17.44 seconds
Started Dec 20 12:39:24 PM PST 23
Finished Dec 20 12:40:49 PM PST 23
Peak memory 211012 kb
Host smart-9e5063bb-3ed0-4643-bb35-29924da03069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546067490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1546067490
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1888508722
Short name T324
Test name
Test status
Simulation time 1465716836 ps
CPU time 13.73 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:36 PM PST 23
Peak memory 210916 kb
Host smart-9868fdc9-e3bf-4a36-a9e1-f7493d426bb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888508722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1888508722
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.152792256
Short name T290
Test name
Test status
Simulation time 748630828 ps
CPU time 10.03 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:33 PM PST 23
Peak memory 212100 kb
Host smart-6e2fba1c-768f-4028-a1a3-3802fd686e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152792256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.152792256
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1613175356
Short name T344
Test name
Test status
Simulation time 2640011554 ps
CPU time 15.63 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 211140 kb
Host smart-5726dde2-9d2c-4c68-9604-2f9ae876c9e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613175356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1613175356
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3093359266
Short name T152
Test name
Test status
Simulation time 176188592 ps
CPU time 5.49 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:40:45 PM PST 23
Peak memory 211052 kb
Host smart-356a1434-8aaf-4fef-9d5a-c52cad9c8a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093359266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3093359266
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2376479980
Short name T278
Test name
Test status
Simulation time 13631984158 ps
CPU time 156.9 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:42:34 PM PST 23
Peak memory 236292 kb
Host smart-88b80a8d-055a-406c-9ebe-e448515dc39f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376479980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2376479980
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.946687500
Short name T299
Test name
Test status
Simulation time 5002643742 ps
CPU time 17.3 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 12:40:10 PM PST 23
Peak memory 211372 kb
Host smart-a6214e2d-a3d1-4819-a76c-5dd7bab91255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946687500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.946687500
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2034591844
Short name T302
Test name
Test status
Simulation time 1394893458 ps
CPU time 7.81 seconds
Started Dec 20 12:39:06 PM PST 23
Finished Dec 20 12:40:20 PM PST 23
Peak memory 210744 kb
Host smart-2c695d42-2c47-40b4-88cd-da4c08257a27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2034591844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2034591844
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.319229477
Short name T335
Test name
Test status
Simulation time 3506594301 ps
CPU time 29.59 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 12:40:14 PM PST 23
Peak memory 212508 kb
Host smart-20f6fb27-b52b-4062-8195-2cd62602c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319229477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.319229477
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1036210365
Short name T283
Test name
Test status
Simulation time 1369884541 ps
CPU time 16.7 seconds
Started Dec 20 12:39:24 PM PST 23
Finished Dec 20 12:40:50 PM PST 23
Peak memory 210804 kb
Host smart-402c0fe3-4f31-4193-8098-b716e56428c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036210365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1036210365
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.704221420
Short name T161
Test name
Test status
Simulation time 9915304200 ps
CPU time 16.27 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:39 PM PST 23
Peak memory 210996 kb
Host smart-d6dd9898-ddee-4e44-aa1b-9a36ba4b85a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704221420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.704221420
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1938111166
Short name T254
Test name
Test status
Simulation time 15981770942 ps
CPU time 181.79 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 12:43:15 PM PST 23
Peak memory 212300 kb
Host smart-f4419788-49a6-4a6a-80ca-7864e54f7cac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938111166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1938111166
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.827432599
Short name T177
Test name
Test status
Simulation time 1717140580 ps
CPU time 15.35 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:40:30 PM PST 23
Peak memory 211128 kb
Host smart-ae514f03-8f63-4d15-9897-b1fdae597a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827432599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.827432599
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4070415451
Short name T368
Test name
Test status
Simulation time 195763043 ps
CPU time 5.5 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:41:00 PM PST 23
Peak memory 210728 kb
Host smart-1d098627-4afd-409e-9b90-0b6c79b909ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070415451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4070415451
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.4054727796
Short name T264
Test name
Test status
Simulation time 1931182762 ps
CPU time 21.35 seconds
Started Dec 20 12:38:45 PM PST 23
Finished Dec 20 12:40:05 PM PST 23
Peak memory 212088 kb
Host smart-930b3b9e-c0e5-488f-a809-d8c35b756d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054727796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.4054727796
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1585243616
Short name T233
Test name
Test status
Simulation time 2221824109 ps
CPU time 19.45 seconds
Started Dec 20 12:38:49 PM PST 23
Finished Dec 20 12:40:24 PM PST 23
Peak memory 210840 kb
Host smart-b6eb278f-d06e-4a74-89b8-c8121dae0506
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585243616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1585243616
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2717351303
Short name T312
Test name
Test status
Simulation time 88357246 ps
CPU time 4.48 seconds
Started Dec 20 12:38:49 PM PST 23
Finished Dec 20 12:40:11 PM PST 23
Peak memory 210940 kb
Host smart-331cbbfa-48dd-4702-8401-9bd671d46821
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717351303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2717351303
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4130669103
Short name T419
Test name
Test status
Simulation time 2221432720 ps
CPU time 22.71 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:52 PM PST 23
Peak memory 211140 kb
Host smart-3071a202-dac7-4083-88ec-9d6b5c9a5bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130669103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4130669103
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.186326689
Short name T353
Test name
Test status
Simulation time 7326590198 ps
CPU time 11.26 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:39:58 PM PST 23
Peak memory 210956 kb
Host smart-9896096d-8976-4c0b-9297-a0d4e5cf9e22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186326689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.186326689
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1909730432
Short name T296
Test name
Test status
Simulation time 5821408737 ps
CPU time 29.86 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:40:22 PM PST 23
Peak memory 212164 kb
Host smart-e6889bc8-4ec3-4ed2-86cf-1d55eb86a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909730432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1909730432
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2070664208
Short name T165
Test name
Test status
Simulation time 10099816843 ps
CPU time 59.58 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 215756 kb
Host smart-2afbb729-0f01-4a05-b7e1-9e5f5f3bfc3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070664208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2070664208
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3527989409
Short name T379
Test name
Test status
Simulation time 34853137280 ps
CPU time 779.24 seconds
Started Dec 20 12:39:50 PM PST 23
Finished Dec 20 12:54:05 PM PST 23
Peak memory 235108 kb
Host smart-cb3aaac0-f633-4bff-a619-efbf7de525c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527989409 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3527989409
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1616107400
Short name T143
Test name
Test status
Simulation time 132119701 ps
CPU time 5.23 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:39:45 PM PST 23
Peak memory 210836 kb
Host smart-5a4d0aa3-7e3b-4006-817b-0fa112bb764a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616107400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1616107400
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1687252040
Short name T317
Test name
Test status
Simulation time 45542409425 ps
CPU time 432.71 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 12:47:06 PM PST 23
Peak memory 236464 kb
Host smart-913b992c-0b94-4da9-aecb-4bff84eb473a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687252040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1687252040
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2443880239
Short name T221
Test name
Test status
Simulation time 13483067492 ps
CPU time 29.19 seconds
Started Dec 20 12:38:50 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 211372 kb
Host smart-46564e80-1d69-4f56-908f-d21874882de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443880239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2443880239
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1857968425
Short name T178
Test name
Test status
Simulation time 2135975439 ps
CPU time 12.08 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:41:06 PM PST 23
Peak memory 210840 kb
Host smart-4fa947ae-913e-4fa2-820f-cf779b64a10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857968425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1857968425
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.66568759
Short name T255
Test name
Test status
Simulation time 2389351272 ps
CPU time 29.21 seconds
Started Dec 20 12:39:35 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 212288 kb
Host smart-a4efde50-8531-4ca7-bb81-9c024e731746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66568759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.66568759
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4247238458
Short name T204
Test name
Test status
Simulation time 7448253395 ps
CPU time 76.4 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:41:07 PM PST 23
Peak memory 216096 kb
Host smart-85c11195-0f19-4c11-a38c-d5a1d4f4f3c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247238458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4247238458
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.1845043699
Short name T166
Test name
Test status
Simulation time 7622847610 ps
CPU time 15.38 seconds
Started Dec 20 12:39:51 PM PST 23
Finished Dec 20 12:41:17 PM PST 23
Peak memory 210912 kb
Host smart-a65adfa0-6743-44c8-b80f-bac11c6ddf2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845043699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1845043699
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1772613159
Short name T210
Test name
Test status
Simulation time 55378267687 ps
CPU time 283.2 seconds
Started Dec 20 12:40:12 PM PST 23
Finished Dec 20 12:46:01 PM PST 23
Peak memory 236436 kb
Host smart-a98525b7-14a3-4d47-80c8-2e93e1346e71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772613159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1772613159
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3996034945
Short name T276
Test name
Test status
Simulation time 692174064 ps
CPU time 9.6 seconds
Started Dec 20 12:39:53 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 210924 kb
Host smart-c8ad105a-cc45-4030-ae0a-eeb9938bb196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996034945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3996034945
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3500614741
Short name T3
Test name
Test status
Simulation time 217245355 ps
CPU time 5.63 seconds
Started Dec 20 12:38:37 PM PST 23
Finished Dec 20 12:39:51 PM PST 23
Peak memory 210948 kb
Host smart-6addcd78-c359-4567-97bf-3cbbfdb4ce6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3500614741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3500614741
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.32931674
Short name T159
Test name
Test status
Simulation time 6376202797 ps
CPU time 28.33 seconds
Started Dec 20 12:39:38 PM PST 23
Finished Dec 20 12:41:18 PM PST 23
Peak memory 213872 kb
Host smart-406b8cec-9ab2-43f5-95d2-1e7bb2d5a460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32931674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.32931674
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.2384797805
Short name T339
Test name
Test status
Simulation time 154686467 ps
CPU time 7.42 seconds
Started Dec 20 12:39:07 PM PST 23
Finished Dec 20 12:40:20 PM PST 23
Peak memory 210956 kb
Host smart-53a62f78-71de-4ed0-9a51-12b9babec0cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384797805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.2384797805
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.3695220071
Short name T145
Test name
Test status
Simulation time 121086817173 ps
CPU time 3927.84 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 01:45:19 PM PST 23
Peak memory 238344 kb
Host smart-28159ba9-d66e-40b6-98a8-b552c03f1eea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695220071 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.3695220071
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.834506564
Short name T240
Test name
Test status
Simulation time 1183425626 ps
CPU time 4.41 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:39:49 PM PST 23
Peak memory 210992 kb
Host smart-0db2fd74-6d58-417c-b158-63fb9e086e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834506564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.834506564
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2695500024
Short name T375
Test name
Test status
Simulation time 12283801926 ps
CPU time 120.22 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:41:46 PM PST 23
Peak memory 227748 kb
Host smart-9ed8fdbf-e353-4522-b6dc-e80aafc11d70
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695500024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2695500024
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2011681098
Short name T431
Test name
Test status
Simulation time 13297473790 ps
CPU time 29.93 seconds
Started Dec 20 12:39:07 PM PST 23
Finished Dec 20 12:40:42 PM PST 23
Peak memory 211320 kb
Host smart-318c1fbc-7f55-42d8-a780-96d7ceca8d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011681098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2011681098
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1880492286
Short name T93
Test name
Test status
Simulation time 1250104210 ps
CPU time 12.26 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:41:02 PM PST 23
Peak memory 210876 kb
Host smart-95b3eb5b-b62f-4a35-ac2f-bb3876a2ea51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1880492286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1880492286
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.429286894
Short name T206
Test name
Test status
Simulation time 2244939330 ps
CPU time 23.62 seconds
Started Dec 20 12:38:42 PM PST 23
Finished Dec 20 12:40:18 PM PST 23
Peak memory 212648 kb
Host smart-98041746-88d0-4587-82f3-df72049ebb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429286894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.429286894
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.962940922
Short name T369
Test name
Test status
Simulation time 28054907465 ps
CPU time 55.07 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:41:41 PM PST 23
Peak memory 215916 kb
Host smart-bcccd0f4-26f0-4f65-9497-1010d2203c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962940922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.rom_ctrl_stress_all.962940922
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.105609102
Short name T170
Test name
Test status
Simulation time 61463325178 ps
CPU time 1618.81 seconds
Started Dec 20 12:38:59 PM PST 23
Finished Dec 20 01:06:58 PM PST 23
Peak memory 235216 kb
Host smart-81b698a4-d870-4bae-8479-e23e3f5c7426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105609102 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.105609102
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.4141889393
Short name T361
Test name
Test status
Simulation time 89000100 ps
CPU time 4.44 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:39:55 PM PST 23
Peak memory 210940 kb
Host smart-05489829-83ed-4c29-a5f0-7a6f63905e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141889393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.4141889393
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3079339119
Short name T217
Test name
Test status
Simulation time 200442312327 ps
CPU time 565.17 seconds
Started Dec 20 12:38:52 PM PST 23
Finished Dec 20 12:49:21 PM PST 23
Peak memory 224308 kb
Host smart-3fe18abc-cc26-4ac9-91ef-cacc6b1e3a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079339119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3079339119
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1707004029
Short name T407
Test name
Test status
Simulation time 861470957 ps
CPU time 14.44 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:33 PM PST 23
Peak memory 211392 kb
Host smart-149a496d-8c5a-49d0-aee4-a2f3f05ab43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707004029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1707004029
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1612415455
Short name T193
Test name
Test status
Simulation time 3202218839 ps
CPU time 15.29 seconds
Started Dec 20 12:39:12 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 210952 kb
Host smart-70228940-99a4-469a-82ea-598769165670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1612415455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1612415455
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2708285696
Short name T284
Test name
Test status
Simulation time 262000178 ps
CPU time 12.18 seconds
Started Dec 20 12:38:53 PM PST 23
Finished Dec 20 12:40:06 PM PST 23
Peak memory 212612 kb
Host smart-c1bd61c1-bba3-4021-92f1-4c692cfa6b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708285696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2708285696
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.727969273
Short name T141
Test name
Test status
Simulation time 3796156726 ps
CPU time 14.45 seconds
Started Dec 20 12:39:11 PM PST 23
Finished Dec 20 12:40:31 PM PST 23
Peak memory 210836 kb
Host smart-490d149f-09ea-4cd0-99e8-353fdd3f4747
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727969273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.rom_ctrl_stress_all.727969273
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1313159203
Short name T399
Test name
Test status
Simulation time 462856113 ps
CPU time 4.38 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:40:01 PM PST 23
Peak memory 211004 kb
Host smart-0572ee9c-e377-4539-935f-ab2441ccea5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313159203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1313159203
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1328463489
Short name T412
Test name
Test status
Simulation time 139796871621 ps
CPU time 428.89 seconds
Started Dec 20 12:39:42 PM PST 23
Finished Dec 20 12:48:08 PM PST 23
Peak memory 237252 kb
Host smart-8218869e-fb79-4493-8e75-389ac2c250e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328463489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1328463489
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1280770640
Short name T186
Test name
Test status
Simulation time 2428782549 ps
CPU time 24.02 seconds
Started Dec 20 12:38:37 PM PST 23
Finished Dec 20 12:40:14 PM PST 23
Peak memory 211140 kb
Host smart-60b4c714-bb8f-41e2-9160-f79fe77b5029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280770640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1280770640
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2350240595
Short name T394
Test name
Test status
Simulation time 6767601980 ps
CPU time 14.56 seconds
Started Dec 20 12:38:26 PM PST 23
Finished Dec 20 12:39:37 PM PST 23
Peak memory 210980 kb
Host smart-8fd5b087-6e64-4d59-a563-70a4a2254bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350240595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2350240595
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.336853151
Short name T39
Test name
Test status
Simulation time 878489962 ps
CPU time 58.82 seconds
Started Dec 20 12:38:27 PM PST 23
Finished Dec 20 12:40:31 PM PST 23
Peak memory 234720 kb
Host smart-adc0355e-54b1-454b-b0cb-1dc1e30bdbfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336853151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.336853151
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1247597928
Short name T423
Test name
Test status
Simulation time 1544894899 ps
CPU time 19.54 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:40:07 PM PST 23
Peak memory 212644 kb
Host smart-4cc2cf4c-85aa-486a-a043-cfd1687c1846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247597928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1247597928
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.813875175
Short name T156
Test name
Test status
Simulation time 767086418 ps
CPU time 18.33 seconds
Started Dec 20 12:38:33 PM PST 23
Finished Dec 20 12:39:51 PM PST 23
Peak memory 212912 kb
Host smart-a3f8cf7b-5195-442c-900d-41477b60bb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813875175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.813875175
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2491218539
Short name T169
Test name
Test status
Simulation time 107637006133 ps
CPU time 10519.9 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 03:35:39 PM PST 23
Peak memory 236240 kb
Host smart-95ae68e5-8708-437a-b699-094a1f318eca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491218539 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.2491218539
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1338808186
Short name T265
Test name
Test status
Simulation time 3403138458 ps
CPU time 13.9 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:24 PM PST 23
Peak memory 211056 kb
Host smart-158ef288-3175-4f0a-b00c-ede52e6ddbc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338808186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1338808186
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.749722313
Short name T306
Test name
Test status
Simulation time 986467223376 ps
CPU time 508.2 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:48:59 PM PST 23
Peak memory 236504 kb
Host smart-ecaedcae-0a54-4e63-8a78-4400597c133d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749722313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_c
orrupt_sig_fatal_chk.749722313
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3355980506
Short name T33
Test name
Test status
Simulation time 1874010186 ps
CPU time 12.87 seconds
Started Dec 20 12:39:04 PM PST 23
Finished Dec 20 12:40:23 PM PST 23
Peak memory 211032 kb
Host smart-d445c4d5-2d98-4295-92b2-61bdfee1f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355980506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3355980506
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.354032099
Short name T262
Test name
Test status
Simulation time 2006580608 ps
CPU time 16.18 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:19 PM PST 23
Peak memory 210812 kb
Host smart-79d6291d-37d3-4837-911b-787942428459
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354032099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.354032099
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3187857503
Short name T41
Test name
Test status
Simulation time 8261431791 ps
CPU time 20.23 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:40:11 PM PST 23
Peak memory 213628 kb
Host smart-c14f21d1-4d11-402a-92a6-0880d7172bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187857503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3187857503
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1715998955
Short name T386
Test name
Test status
Simulation time 2486742160 ps
CPU time 24.56 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:30 PM PST 23
Peak memory 215376 kb
Host smart-5ca46ca1-4744-4e51-9357-2eb4d266341a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715998955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1715998955
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2894419685
Short name T425
Test name
Test status
Simulation time 41024908341 ps
CPU time 1519.27 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 01:05:24 PM PST 23
Peak memory 235188 kb
Host smart-7159f552-9e92-4738-a6df-d904f50ec7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894419685 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2894419685
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1940617949
Short name T224
Test name
Test status
Simulation time 1825046955 ps
CPU time 14.93 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:39:57 PM PST 23
Peak memory 210820 kb
Host smart-79b699ab-edd2-41ee-b69e-42c4c3af4b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940617949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1940617949
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1475403627
Short name T364
Test name
Test status
Simulation time 16210974140 ps
CPU time 188.34 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:43:21 PM PST 23
Peak memory 237540 kb
Host smart-fdc46156-3f9f-4b6f-b3a1-112bb31ac9bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475403627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1475403627
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3103201575
Short name T307
Test name
Test status
Simulation time 7458617444 ps
CPU time 20.83 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:41:07 PM PST 23
Peak memory 212616 kb
Host smart-56df1460-125b-4d66-89d3-189ac4a02833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103201575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3103201575
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2052825019
Short name T260
Test name
Test status
Simulation time 1168970394 ps
CPU time 11.9 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 210736 kb
Host smart-0c61bba3-aa85-4d95-815e-7cdc47635350
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052825019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2052825019
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3858692181
Short name T273
Test name
Test status
Simulation time 17608521348 ps
CPU time 39.52 seconds
Started Dec 20 12:39:07 PM PST 23
Finished Dec 20 12:40:50 PM PST 23
Peak memory 213288 kb
Host smart-32502923-01b8-4688-9d2f-8ff8a127d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858692181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3858692181
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2257933015
Short name T211
Test name
Test status
Simulation time 36486095504 ps
CPU time 51.88 seconds
Started Dec 20 12:38:59 PM PST 23
Finished Dec 20 12:40:55 PM PST 23
Peak memory 216732 kb
Host smart-41afd91c-4915-4cbf-9538-e7d9fc8ba3d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257933015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2257933015
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.3418902528
Short name T295
Test name
Test status
Simulation time 28732165345 ps
CPU time 1036.38 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:57:29 PM PST 23
Peak memory 235632 kb
Host smart-bbc51cd0-1166-42f7-a2f1-dd0ba20645e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418902528 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.3418902528
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.780659895
Short name T346
Test name
Test status
Simulation time 5282523436 ps
CPU time 7.96 seconds
Started Dec 20 12:39:20 PM PST 23
Finished Dec 20 12:40:39 PM PST 23
Peak memory 211036 kb
Host smart-ac14d85e-1bbe-4913-b34e-34c5e2a183aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780659895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.780659895
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.787216013
Short name T245
Test name
Test status
Simulation time 10026027799 ps
CPU time 195.61 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:43:26 PM PST 23
Peak memory 236372 kb
Host smart-5dce524e-2fe9-426b-81b8-26779f5234fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787216013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.787216013
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1674872264
Short name T234
Test name
Test status
Simulation time 1891495746 ps
CPU time 14.89 seconds
Started Dec 20 12:38:50 PM PST 23
Finished Dec 20 12:40:16 PM PST 23
Peak memory 211036 kb
Host smart-fe9ff369-9ae3-45c6-8735-c0db43d2860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674872264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1674872264
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1492642788
Short name T162
Test name
Test status
Simulation time 98801870 ps
CPU time 5.88 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:39:59 PM PST 23
Peak memory 210980 kb
Host smart-8c98f6f5-61a0-47e5-8e63-5160d5a65e20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492642788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1492642788
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3516187115
Short name T167
Test name
Test status
Simulation time 723369717 ps
CPU time 9.64 seconds
Started Dec 20 12:39:41 PM PST 23
Finished Dec 20 12:40:56 PM PST 23
Peak memory 211612 kb
Host smart-79573260-72a1-49f3-81e3-049112c14b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516187115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3516187115
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.361160198
Short name T395
Test name
Test status
Simulation time 5542398457 ps
CPU time 24.18 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 216276 kb
Host smart-f266b3f4-404a-41a1-9254-228764115fbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361160198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.rom_ctrl_stress_all.361160198
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3167022395
Short name T250
Test name
Test status
Simulation time 251626502383 ps
CPU time 8694.64 seconds
Started Dec 20 12:38:52 PM PST 23
Finished Dec 20 03:04:47 PM PST 23
Peak memory 243804 kb
Host smart-3e8f3fee-3d50-4b14-a2c7-5db7f3b3b3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167022395 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3167022395
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3738819623
Short name T149
Test name
Test status
Simulation time 5813694723 ps
CPU time 11.5 seconds
Started Dec 20 12:39:11 PM PST 23
Finished Dec 20 12:40:34 PM PST 23
Peak memory 211028 kb
Host smart-b8b36cbb-7c8d-4cf0-8b41-f41a0f2be23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738819623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3738819623
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1852449528
Short name T348
Test name
Test status
Simulation time 55811868566 ps
CPU time 182.32 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:42:45 PM PST 23
Peak memory 237368 kb
Host smart-6dabd5f8-b678-4d78-b87e-e515dcd6932a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852449528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1852449528
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2233789517
Short name T330
Test name
Test status
Simulation time 501830368 ps
CPU time 12.9 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 210968 kb
Host smart-7b883a78-0a6c-4a89-95f8-c5f02f1d49b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233789517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2233789517
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.846932461
Short name T187
Test name
Test status
Simulation time 6366941671 ps
CPU time 14.8 seconds
Started Dec 20 12:38:46 PM PST 23
Finished Dec 20 12:39:57 PM PST 23
Peak memory 210808 kb
Host smart-65734d85-f227-4226-8999-9f61c2b8ff59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846932461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.846932461
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.437116409
Short name T354
Test name
Test status
Simulation time 7646251581 ps
CPU time 28.26 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:41:02 PM PST 23
Peak memory 213680 kb
Host smart-41d95465-721e-4ed3-b0c3-ed360a36621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437116409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.437116409
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.1113994970
Short name T288
Test name
Test status
Simulation time 133330072877 ps
CPU time 125.6 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 215828 kb
Host smart-fc65fef3-352a-4661-a20a-3656c5323898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113994970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.1113994970
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1922702924
Short name T194
Test name
Test status
Simulation time 333540019 ps
CPU time 6.7 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 12:40:04 PM PST 23
Peak memory 211068 kb
Host smart-15153da9-31c0-4fb3-bb0a-8e1f8afc1d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922702924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1922702924
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.987482991
Short name T365
Test name
Test status
Simulation time 42607271313 ps
CPU time 226.76 seconds
Started Dec 20 12:38:43 PM PST 23
Finished Dec 20 12:43:26 PM PST 23
Peak memory 224260 kb
Host smart-89cd75cf-443b-4ce8-a8b2-9b6b68788bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987482991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.987482991
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.4098812341
Short name T319
Test name
Test status
Simulation time 1540157639 ps
CPU time 18.78 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:41:02 PM PST 23
Peak memory 210900 kb
Host smart-0fc16d6b-9f13-4d0b-8092-b7878f0a6968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098812341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.4098812341
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.752209893
Short name T377
Test name
Test status
Simulation time 105822985 ps
CPU time 5.77 seconds
Started Dec 20 12:38:58 PM PST 23
Finished Dec 20 12:40:06 PM PST 23
Peak memory 210772 kb
Host smart-20cb4244-3126-4e3a-ae34-c3006ff48a3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=752209893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.752209893
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1189403579
Short name T385
Test name
Test status
Simulation time 19779972759 ps
CPU time 21.54 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:40:59 PM PST 23
Peak memory 213380 kb
Host smart-db9a8167-4785-4f25-823e-99f6d8450fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189403579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1189403579
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3663631028
Short name T248
Test name
Test status
Simulation time 10145401995 ps
CPU time 56.91 seconds
Started Dec 20 12:39:31 PM PST 23
Finished Dec 20 12:41:37 PM PST 23
Peak memory 217220 kb
Host smart-e385d45c-f3f6-4a72-977c-907f52d6953e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663631028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3663631028
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1392242489
Short name T415
Test name
Test status
Simulation time 371456437439 ps
CPU time 3852.93 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 01:44:00 PM PST 23
Peak memory 231876 kb
Host smart-89f990dc-f590-4cae-b218-9ca77f56a28a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392242489 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1392242489
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2680736632
Short name T150
Test name
Test status
Simulation time 8399468816 ps
CPU time 16.27 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:22 PM PST 23
Peak memory 211100 kb
Host smart-6252c498-83f4-4b91-912e-b9a4200b9ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680736632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2680736632
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3922138908
Short name T45
Test name
Test status
Simulation time 23034866376 ps
CPU time 209.73 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 12:43:28 PM PST 23
Peak memory 236388 kb
Host smart-595b5e38-7f32-49cc-a33f-65c836ff4e84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922138908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3922138908
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2026029327
Short name T144
Test name
Test status
Simulation time 4231099782 ps
CPU time 31.79 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 211236 kb
Host smart-50e3104b-2e1f-47ab-b2a7-214dbe4d48c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026029327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2026029327
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.560165635
Short name T48
Test name
Test status
Simulation time 2052182154 ps
CPU time 16.08 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:40:36 PM PST 23
Peak memory 210744 kb
Host smart-94a7ef8a-d420-419e-8bab-0d5d5ceca7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=560165635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.560165635
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2011064518
Short name T396
Test name
Test status
Simulation time 185452936 ps
CPU time 11.01 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 212432 kb
Host smart-33050ee1-8624-4f6f-8cc0-02811c1b42ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011064518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2011064518
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1854356767
Short name T171
Test name
Test status
Simulation time 5105564649 ps
CPU time 19.48 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 213704 kb
Host smart-a8fb0c43-3028-4881-a657-90a4f0252ae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854356767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1854356767
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3780265646
Short name T189
Test name
Test status
Simulation time 1775072767 ps
CPU time 9.58 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 210920 kb
Host smart-34c43fd4-50b1-490b-bec2-2820cdca2a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780265646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3780265646
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3213486763
Short name T355
Test name
Test status
Simulation time 1740683511 ps
CPU time 98.7 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:41:22 PM PST 23
Peak memory 211080 kb
Host smart-4166660d-3eac-49bd-9218-7baa80272eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213486763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3213486763
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.4055356758
Short name T231
Test name
Test status
Simulation time 53764738279 ps
CPU time 32.66 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:40:40 PM PST 23
Peak memory 211524 kb
Host smart-416cdb2e-9723-41e6-b8a8-caf603ff3332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055356758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.4055356758
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2956891504
Short name T382
Test name
Test status
Simulation time 2041569582 ps
CPU time 17.1 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 210884 kb
Host smart-61964919-4711-4d66-af66-18eeaef66930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956891504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2956891504
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2605481511
Short name T336
Test name
Test status
Simulation time 1379181680 ps
CPU time 17.87 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:40:10 PM PST 23
Peak memory 212576 kb
Host smart-ca7a4f4e-d61e-4e80-8117-e347f124070d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605481511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2605481511
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.944535838
Short name T174
Test name
Test status
Simulation time 61986492009 ps
CPU time 50.35 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:41:27 PM PST 23
Peak memory 213084 kb
Host smart-f76d26e9-3877-45c4-97d2-7eac3185d591
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944535838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.944535838
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.36104129
Short name T404
Test name
Test status
Simulation time 41836821662 ps
CPU time 2638.36 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 01:24:35 PM PST 23
Peak memory 235544 kb
Host smart-793fc2da-b784-42e8-a0b0-a7089ce227fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36104129 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.36104129
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3125437337
Short name T243
Test name
Test status
Simulation time 832142847 ps
CPU time 9.52 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:40:34 PM PST 23
Peak memory 211020 kb
Host smart-01cbcfc5-1587-4888-a32b-2e71dfb81608
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125437337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3125437337
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.2904311571
Short name T325
Test name
Test status
Simulation time 67689754301 ps
CPU time 622.03 seconds
Started Dec 20 12:39:34 PM PST 23
Finished Dec 20 12:51:09 PM PST 23
Peak memory 233248 kb
Host smart-1f4a64fc-4795-4f8a-962c-7a4b3306cb00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904311571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.2904311571
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.164001823
Short name T338
Test name
Test status
Simulation time 2912407993 ps
CPU time 27.38 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:25 PM PST 23
Peak memory 211076 kb
Host smart-3b7585c2-7367-42ff-be9d-6e04bdc72c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164001823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.164001823
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2141955411
Short name T372
Test name
Test status
Simulation time 7229017565 ps
CPU time 15.09 seconds
Started Dec 20 12:38:49 PM PST 23
Finished Dec 20 12:40:22 PM PST 23
Peak memory 210832 kb
Host smart-72d139e0-51bc-4559-b8d8-ee05ff4db4b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141955411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2141955411
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1977505285
Short name T286
Test name
Test status
Simulation time 1208245695 ps
CPU time 14.09 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:32 PM PST 23
Peak memory 212740 kb
Host smart-16765255-cb3e-484b-b1b4-9a2c44992d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977505285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1977505285
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1471668375
Short name T230
Test name
Test status
Simulation time 471502621 ps
CPU time 14.54 seconds
Started Dec 20 12:39:39 PM PST 23
Finished Dec 20 12:41:02 PM PST 23
Peak memory 212856 kb
Host smart-76a07662-80fa-4239-844b-19a8e92a4712
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471668375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1471668375
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3760225970
Short name T363
Test name
Test status
Simulation time 357129095737 ps
CPU time 1116.63 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:59:08 PM PST 23
Peak memory 235660 kb
Host smart-29444af2-64f1-4bed-9286-f1dce7f55176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760225970 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3760225970
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2280319914
Short name T271
Test name
Test status
Simulation time 333019620 ps
CPU time 4.45 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:40:33 PM PST 23
Peak memory 210936 kb
Host smart-6d5ce1ca-b157-49ec-ae63-91b2d1aeb48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280319914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2280319914
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.712501355
Short name T181
Test name
Test status
Simulation time 35793248365 ps
CPU time 400.32 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:46:37 PM PST 23
Peak memory 237692 kb
Host smart-f1400cbc-cdeb-4f8c-b53a-1d9edddfea99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712501355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.712501355
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.2802386186
Short name T301
Test name
Test status
Simulation time 4279783729 ps
CPU time 17.07 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 211240 kb
Host smart-ab3ccfab-1a43-48c6-9253-a33b68b0fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802386186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.2802386186
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.376948600
Short name T246
Test name
Test status
Simulation time 4056713654 ps
CPU time 16.58 seconds
Started Dec 20 12:38:59 PM PST 23
Finished Dec 20 12:40:17 PM PST 23
Peak memory 211028 kb
Host smart-ee4e8270-c334-40bd-9b99-daf38363e05b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376948600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.376948600
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3987561667
Short name T247
Test name
Test status
Simulation time 759853519 ps
CPU time 10.23 seconds
Started Dec 20 12:39:07 PM PST 23
Finished Dec 20 12:40:22 PM PST 23
Peak memory 212740 kb
Host smart-65eccbe4-3a02-4ca4-b92f-e21cb755ec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987561667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3987561667
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3351436789
Short name T428
Test name
Test status
Simulation time 2458359748 ps
CPU time 39.07 seconds
Started Dec 20 12:38:47 PM PST 23
Finished Dec 20 12:40:28 PM PST 23
Peak memory 215256 kb
Host smart-024f372a-1a7e-4b1d-9b4e-50c3aa0d9eff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351436789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3351436789
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2395256320
Short name T337
Test name
Test status
Simulation time 290165042 ps
CPU time 6.37 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:11 PM PST 23
Peak memory 210864 kb
Host smart-4d9ad833-9b40-426d-9616-af869b7300b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395256320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2395256320
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2548542727
Short name T329
Test name
Test status
Simulation time 4849471690 ps
CPU time 82.47 seconds
Started Dec 20 12:38:53 PM PST 23
Finished Dec 20 12:41:14 PM PST 23
Peak memory 237468 kb
Host smart-a0f65a63-2ce4-4987-b3b6-56e54b007eab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548542727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2548542727
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.300058555
Short name T277
Test name
Test status
Simulation time 8343298440 ps
CPU time 33.13 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:41:13 PM PST 23
Peak memory 211436 kb
Host smart-f189cd55-7fbf-479b-80d9-1cf4418702a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300058555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.300058555
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1455675292
Short name T300
Test name
Test status
Simulation time 5912098775 ps
CPU time 14.44 seconds
Started Dec 20 12:39:57 PM PST 23
Finished Dec 20 12:41:23 PM PST 23
Peak memory 211064 kb
Host smart-a95fb1ef-19ed-4a83-a068-289f8341d6c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455675292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1455675292
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.34325694
Short name T228
Test name
Test status
Simulation time 4106276624 ps
CPU time 41.16 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:41:19 PM PST 23
Peak memory 212104 kb
Host smart-8b9745c2-bcd5-4f3f-b112-e07c8e9b8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34325694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.34325694
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2746205182
Short name T342
Test name
Test status
Simulation time 24137580939 ps
CPU time 57.73 seconds
Started Dec 20 12:39:47 PM PST 23
Finished Dec 20 12:41:48 PM PST 23
Peak memory 212972 kb
Host smart-7186ef43-aa01-44a5-87e2-ee8d9e1116fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746205182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2746205182
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2350365876
Short name T100
Test name
Test status
Simulation time 35941931750 ps
CPU time 696.4 seconds
Started Dec 20 12:40:02 PM PST 23
Finished Dec 20 12:52:39 PM PST 23
Peak memory 229720 kb
Host smart-ebdbc646-1bff-4066-a65b-500a5301e84e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350365876 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2350365876
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.4151369221
Short name T408
Test name
Test status
Simulation time 1173343041 ps
CPU time 11.35 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:39:44 PM PST 23
Peak memory 210964 kb
Host smart-4f6751ca-e02a-4942-a433-d22c751f8078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151369221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.4151369221
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3431003731
Short name T218
Test name
Test status
Simulation time 169223879 ps
CPU time 10.05 seconds
Started Dec 20 12:38:21 PM PST 23
Finished Dec 20 12:39:38 PM PST 23
Peak memory 211592 kb
Host smart-c801eef8-1317-4f92-8d1c-bdf3ffa2a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431003731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3431003731
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1770809947
Short name T201
Test name
Test status
Simulation time 1921599319 ps
CPU time 15.85 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:36 PM PST 23
Peak memory 210884 kb
Host smart-f5ae708d-6a19-4317-9ec8-0d3b6562fa30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770809947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1770809947
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.3687784558
Short name T272
Test name
Test status
Simulation time 184265915 ps
CPU time 10.47 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:23 PM PST 23
Peak memory 212708 kb
Host smart-bf74b7cd-43cf-4094-8050-6af32ff47efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687784558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.3687784558
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1517044264
Short name T263
Test name
Test status
Simulation time 13937484172 ps
CPU time 48.57 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 216224 kb
Host smart-101b88a0-6606-4e23-b214-4b133e7b3c28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517044264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1517044264
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2595503692
Short name T14
Test name
Test status
Simulation time 47270296815 ps
CPU time 838.87 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 12:53:57 PM PST 23
Peak memory 235200 kb
Host smart-b6bbc8db-d73a-43ff-87b9-3a2416d969dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595503692 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2595503692
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.717592299
Short name T397
Test name
Test status
Simulation time 2334053613 ps
CPU time 7.66 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 12:40:21 PM PST 23
Peak memory 211052 kb
Host smart-b5877801-0566-4851-979c-53170e0106b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717592299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.717592299
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.790436459
Short name T215
Test name
Test status
Simulation time 44986740331 ps
CPU time 204.32 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:43:35 PM PST 23
Peak memory 237324 kb
Host smart-7eb6a5a9-383c-4a5c-b020-305601ff2d8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790436459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.790436459
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1060814069
Short name T422
Test name
Test status
Simulation time 757160705 ps
CPU time 9.46 seconds
Started Dec 20 12:39:30 PM PST 23
Finished Dec 20 12:40:51 PM PST 23
Peak memory 211188 kb
Host smart-4ae8c3aa-8a7d-4ae9-abcb-adc3a22f5b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060814069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1060814069
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3497546792
Short name T316
Test name
Test status
Simulation time 1181967151 ps
CPU time 7.53 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 12:40:08 PM PST 23
Peak memory 210872 kb
Host smart-7d1fb843-6a16-4656-be5d-452aaa28d869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3497546792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3497546792
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.28746792
Short name T389
Test name
Test status
Simulation time 16037681210 ps
CPU time 32.69 seconds
Started Dec 20 12:39:46 PM PST 23
Finished Dec 20 12:41:28 PM PST 23
Peak memory 213360 kb
Host smart-a8da8142-c37d-4d04-a2f3-e47bd61bb476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28746792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.28746792
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.21577145
Short name T393
Test name
Test status
Simulation time 3730901166 ps
CPU time 36.49 seconds
Started Dec 20 12:39:01 PM PST 23
Finished Dec 20 12:40:46 PM PST 23
Peak memory 214248 kb
Host smart-0e67371d-13ea-4906-850c-a83fde8ac862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 40.rom_ctrl_stress_all.21577145
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.2569634625
Short name T184
Test name
Test status
Simulation time 162785761666 ps
CPU time 2630.98 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 01:24:16 PM PST 23
Peak memory 235512 kb
Host smart-322d4ea1-338b-4c27-ba8f-2a1ad140889a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569634625 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.2569634625
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2157525951
Short name T297
Test name
Test status
Simulation time 2045975904 ps
CPU time 15.31 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:16 PM PST 23
Peak memory 210916 kb
Host smart-6b0c1214-45ae-4224-bb5a-5553097f6bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157525951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2157525951
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3589613545
Short name T49
Test name
Test status
Simulation time 5384861644 ps
CPU time 162.89 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:43:19 PM PST 23
Peak memory 237616 kb
Host smart-a7704720-1fbe-4cb6-949a-c3aaa1c32ed8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589613545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3589613545
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.25429815
Short name T409
Test name
Test status
Simulation time 9224864244 ps
CPU time 22.61 seconds
Started Dec 20 12:39:49 PM PST 23
Finished Dec 20 12:41:20 PM PST 23
Peak memory 211228 kb
Host smart-572ca16e-81ac-4441-9e2e-b8d9ae07ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25429815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.25429815
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3507331037
Short name T334
Test name
Test status
Simulation time 1744140142 ps
CPU time 8.08 seconds
Started Dec 20 12:39:14 PM PST 23
Finished Dec 20 12:40:27 PM PST 23
Peak memory 210772 kb
Host smart-64f04641-66f6-4111-822d-6d6fe47aff52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507331037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3507331037
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2869100004
Short name T251
Test name
Test status
Simulation time 18347989767 ps
CPU time 39.18 seconds
Started Dec 20 12:38:59 PM PST 23
Finished Dec 20 12:40:40 PM PST 23
Peak memory 213128 kb
Host smart-61928a1d-38e1-4f0b-aed2-22cf574cfba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869100004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2869100004
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3619232646
Short name T359
Test name
Test status
Simulation time 34504108794 ps
CPU time 86.39 seconds
Started Dec 20 12:39:24 PM PST 23
Finished Dec 20 12:42:14 PM PST 23
Peak memory 218168 kb
Host smart-8616af9a-097c-4c74-b25d-1f2fd5798286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619232646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3619232646
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.155951827
Short name T420
Test name
Test status
Simulation time 46419173246 ps
CPU time 10601.8 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 03:36:36 PM PST 23
Peak memory 235612 kb
Host smart-f35df60a-4b37-4149-84c7-61f7e200d9fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155951827 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.155951827
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1381150277
Short name T172
Test name
Test status
Simulation time 7204772562 ps
CPU time 15.53 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:40:17 PM PST 23
Peak memory 210968 kb
Host smart-49b02a7b-bd6f-437d-9946-87223325fe8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381150277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1381150277
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1743820364
Short name T220
Test name
Test status
Simulation time 34265667827 ps
CPU time 228.64 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 12:44:02 PM PST 23
Peak memory 227816 kb
Host smart-ae03d0a2-9624-4889-8587-dc8eb7252a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743820364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1743820364
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1219461542
Short name T168
Test name
Test status
Simulation time 665953520 ps
CPU time 9.79 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:40:39 PM PST 23
Peak memory 211080 kb
Host smart-4738c193-c951-4edc-a27e-74d8c6a28280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219461542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1219461542
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2564287992
Short name T424
Test name
Test status
Simulation time 924309272 ps
CPU time 10.53 seconds
Started Dec 20 12:39:54 PM PST 23
Finished Dec 20 12:41:09 PM PST 23
Peak memory 210804 kb
Host smart-5177d42b-5eac-4717-9958-423ab86985f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2564287992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2564287992
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2127126567
Short name T202
Test name
Test status
Simulation time 3789638455 ps
CPU time 17.16 seconds
Started Dec 20 12:39:56 PM PST 23
Finished Dec 20 12:41:15 PM PST 23
Peak memory 212572 kb
Host smart-c9f80fcf-2097-4fce-9cbf-d31a077bf4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127126567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2127126567
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.460291269
Short name T287
Test name
Test status
Simulation time 3460084736 ps
CPU time 29.28 seconds
Started Dec 20 12:39:21 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 216124 kb
Host smart-643a6038-187a-44d6-b9fd-1fa91bb42df9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460291269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.460291269
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2092001433
Short name T142
Test name
Test status
Simulation time 446498907 ps
CPU time 7.03 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:10 PM PST 23
Peak memory 211044 kb
Host smart-031e9990-b2fe-4cfc-8545-9d785d0cd891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092001433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2092001433
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.981312132
Short name T268
Test name
Test status
Simulation time 146303844975 ps
CPU time 392.9 seconds
Started Dec 20 12:39:02 PM PST 23
Finished Dec 20 12:46:36 PM PST 23
Peak memory 236380 kb
Host smart-1a27d417-d8ec-4d53-88d7-ed44d9f4d5db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981312132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.981312132
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.937176839
Short name T366
Test name
Test status
Simulation time 2354468314 ps
CPU time 13.35 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 211200 kb
Host smart-f30825ab-a248-4d8d-a42c-6fe5f1706789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937176839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.937176839
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2088903652
Short name T411
Test name
Test status
Simulation time 3298350381 ps
CPU time 10 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 211064 kb
Host smart-e71f3597-1839-49d4-84f2-764a7c05d36e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088903652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2088903652
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2956888077
Short name T46
Test name
Test status
Simulation time 348403059 ps
CPU time 10.05 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:11 PM PST 23
Peak memory 211236 kb
Host smart-5d504c57-d412-4d2e-86fb-496b1c882d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956888077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2956888077
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1499850262
Short name T403
Test name
Test status
Simulation time 27146407968 ps
CPU time 145.89 seconds
Started Dec 20 12:39:28 PM PST 23
Finished Dec 20 12:43:02 PM PST 23
Peak memory 219052 kb
Host smart-c6e4b499-ae83-4922-8ed8-bd46ede39ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499850262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1499850262
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3846062449
Short name T191
Test name
Test status
Simulation time 173468969639 ps
CPU time 9795.45 seconds
Started Dec 20 12:40:10 PM PST 23
Finished Dec 20 03:24:29 PM PST 23
Peak memory 235632 kb
Host smart-9fb65620-bac7-4101-b98e-5f55d93c9795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846062449 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3846062449
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3772734216
Short name T173
Test name
Test status
Simulation time 89943911 ps
CPU time 4.42 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:02 PM PST 23
Peak memory 210948 kb
Host smart-b59b4cde-8377-4056-a48a-ee1a58eb3e7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772734216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3772734216
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3383438526
Short name T51
Test name
Test status
Simulation time 54189600233 ps
CPU time 490.86 seconds
Started Dec 20 12:39:11 PM PST 23
Finished Dec 20 12:48:31 PM PST 23
Peak memory 221116 kb
Host smart-68dd7edf-31ca-4268-b2b9-1aa3adc7d2e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383438526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3383438526
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1062249241
Short name T195
Test name
Test status
Simulation time 693193317 ps
CPU time 9.79 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:11 PM PST 23
Peak memory 210944 kb
Host smart-28c473f5-bb4a-47ed-b4b3-e34f260b4b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062249241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1062249241
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1649420444
Short name T391
Test name
Test status
Simulation time 1452069845 ps
CPU time 11.46 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:40:57 PM PST 23
Peak memory 210784 kb
Host smart-216f0151-a866-42be-bde7-18710c8542fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649420444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1649420444
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2480502366
Short name T185
Test name
Test status
Simulation time 358831719 ps
CPU time 10.14 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:25 PM PST 23
Peak memory 211820 kb
Host smart-3587c5dd-0509-4b26-a8ff-af9e0c717dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480502366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2480502366
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3766048412
Short name T253
Test name
Test status
Simulation time 5825648904 ps
CPU time 54.52 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:41:07 PM PST 23
Peak memory 215784 kb
Host smart-5d549c57-bddc-4751-97dd-d4b60febc659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766048412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3766048412
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.609995878
Short name T196
Test name
Test status
Simulation time 121547444173 ps
CPU time 6405.88 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 02:27:05 PM PST 23
Peak memory 237692 kb
Host smart-ff86c9d7-c59c-4f44-8da8-e67e72a4f52b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609995878 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.609995878
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2687914829
Short name T9
Test name
Test status
Simulation time 174023069 ps
CPU time 5.38 seconds
Started Dec 20 12:39:16 PM PST 23
Finished Dec 20 12:40:32 PM PST 23
Peak memory 210900 kb
Host smart-9fc3ae39-70cf-45bf-8a42-eb237a830caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687914829 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2687914829
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.280987498
Short name T298
Test name
Test status
Simulation time 35769577056 ps
CPU time 130.48 seconds
Started Dec 20 12:38:52 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 236212 kb
Host smart-21a5cb46-7a32-4ff4-b712-09cbe226ce62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280987498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.280987498
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1432034183
Short name T31
Test name
Test status
Simulation time 7037274532 ps
CPU time 29.09 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:41:02 PM PST 23
Peak memory 211228 kb
Host smart-0a8005c3-c51e-4aba-84e2-32dcbd84fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432034183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1432034183
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.541797483
Short name T164
Test name
Test status
Simulation time 553094897 ps
CPU time 8.84 seconds
Started Dec 20 12:39:08 PM PST 23
Finished Dec 20 12:40:20 PM PST 23
Peak memory 210780 kb
Host smart-4748199a-3386-4f10-a589-741c10faa088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541797483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.541797483
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3974177144
Short name T380
Test name
Test status
Simulation time 18879340522 ps
CPU time 22.18 seconds
Started Dec 20 12:39:48 PM PST 23
Finished Dec 20 12:41:25 PM PST 23
Peak memory 213168 kb
Host smart-df4322f2-9aed-4368-8f2d-00b4dd8ec323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974177144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3974177144
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1911748133
Short name T188
Test name
Test status
Simulation time 7697507674 ps
CPU time 59.43 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:41:01 PM PST 23
Peak memory 215236 kb
Host smart-ba33660a-04db-4622-bb96-4027d3d2c857
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911748133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1911748133
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.4211742585
Short name T323
Test name
Test status
Simulation time 99944002291 ps
CPU time 3359.63 seconds
Started Dec 20 12:39:29 PM PST 23
Finished Dec 20 01:36:45 PM PST 23
Peak memory 235516 kb
Host smart-7e88aea5-ccf3-402a-addd-72d79af39f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211742585 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.4211742585
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1180267077
Short name T349
Test name
Test status
Simulation time 2130807768 ps
CPU time 7.84 seconds
Started Dec 20 12:39:23 PM PST 23
Finished Dec 20 12:40:44 PM PST 23
Peak memory 210968 kb
Host smart-d9c8499b-d6e2-4bc9-a1fa-805e4a73dc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180267077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1180267077
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3216125088
Short name T209
Test name
Test status
Simulation time 37936406167 ps
CPU time 179.83 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:43:29 PM PST 23
Peak memory 234276 kb
Host smart-600d2908-7cd8-413b-a234-d9bfdde38b8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216125088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3216125088
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4044711999
Short name T216
Test name
Test status
Simulation time 348209274 ps
CPU time 10.18 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:25 PM PST 23
Peak memory 210960 kb
Host smart-fbe3e431-0e70-4ba3-89ec-27f15607c3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044711999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4044711999
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3223374429
Short name T320
Test name
Test status
Simulation time 1383994609 ps
CPU time 9.53 seconds
Started Dec 20 12:39:30 PM PST 23
Finished Dec 20 12:40:49 PM PST 23
Peak memory 210880 kb
Host smart-468c61f3-0753-4fe8-b0ea-3b2d4d90030f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223374429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3223374429
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.652187121
Short name T414
Test name
Test status
Simulation time 6618778276 ps
CPU time 20.8 seconds
Started Dec 20 12:38:58 PM PST 23
Finished Dec 20 12:40:32 PM PST 23
Peak memory 213420 kb
Host smart-d92fc836-912c-4660-8b0c-ec7e0df9963f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652187121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.652187121
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3354484863
Short name T239
Test name
Test status
Simulation time 1664801072 ps
CPU time 19.22 seconds
Started Dec 20 12:39:03 PM PST 23
Finished Dec 20 12:40:30 PM PST 23
Peak memory 210956 kb
Host smart-56155eda-a6a7-40de-99da-f6cfa9d54805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354484863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3354484863
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.836588510
Short name T153
Test name
Test status
Simulation time 2050007270 ps
CPU time 15.09 seconds
Started Dec 20 12:39:36 PM PST 23
Finished Dec 20 12:41:04 PM PST 23
Peak memory 210916 kb
Host smart-7d702dc6-d00d-4489-887f-c546311a9881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836588510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.836588510
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.775942460
Short name T392
Test name
Test status
Simulation time 60682108656 ps
CPU time 276.75 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:44:37 PM PST 23
Peak memory 236892 kb
Host smart-0dd845a8-82b5-44ef-9a67-78c9ae4592d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775942460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.775942460
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3220565425
Short name T381
Test name
Test status
Simulation time 664508675 ps
CPU time 9.74 seconds
Started Dec 20 12:39:09 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 211136 kb
Host smart-b19983c6-5c35-4684-81bd-26f73d92231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220565425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3220565425
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1803550237
Short name T367
Test name
Test status
Simulation time 1197371000 ps
CPU time 11.14 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:40:49 PM PST 23
Peak memory 210936 kb
Host smart-57f3b293-f3aa-454d-9ff5-c69773b60bdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1803550237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1803550237
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2658725742
Short name T190
Test name
Test status
Simulation time 1991594430 ps
CPU time 14.17 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:40:35 PM PST 23
Peak memory 212260 kb
Host smart-2da5f246-8123-40a1-aa52-931e84b6a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658725742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2658725742
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2342004201
Short name T418
Test name
Test status
Simulation time 1099222472 ps
CPU time 33.38 seconds
Started Dec 20 12:39:00 PM PST 23
Finished Dec 20 12:40:48 PM PST 23
Peak memory 216580 kb
Host smart-966e91d2-a5d4-40d4-86fd-0cd2ce032234
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342004201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2342004201
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.4043766059
Short name T13
Test name
Test status
Simulation time 67387854313 ps
CPU time 351.47 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:45:48 PM PST 23
Peak memory 235440 kb
Host smart-ff77b89f-3c67-41af-8788-760f20054d83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043766059 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.4043766059
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3715725469
Short name T237
Test name
Test status
Simulation time 6178526974 ps
CPU time 13.04 seconds
Started Dec 20 12:38:57 PM PST 23
Finished Dec 20 12:40:19 PM PST 23
Peak memory 210980 kb
Host smart-72ca63ef-1dbe-4c69-8aad-e44e7896cdc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715725469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3715725469
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.56659168
Short name T19
Test name
Test status
Simulation time 54756208958 ps
CPU time 251.85 seconds
Started Dec 20 12:39:27 PM PST 23
Finished Dec 20 12:44:45 PM PST 23
Peak memory 236352 kb
Host smart-66243ac2-54e2-459d-a5c4-89a44fa74c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56659168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_co
rrupt_sig_fatal_chk.56659168
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3193013089
Short name T259
Test name
Test status
Simulation time 9297412709 ps
CPU time 22.22 seconds
Started Dec 20 12:39:17 PM PST 23
Finished Dec 20 12:40:53 PM PST 23
Peak memory 211472 kb
Host smart-501a7b02-b63d-4b2d-b956-1b4e3c3deefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193013089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3193013089
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3139249717
Short name T207
Test name
Test status
Simulation time 1477963714 ps
CPU time 13.26 seconds
Started Dec 20 12:39:04 PM PST 23
Finished Dec 20 12:40:19 PM PST 23
Peak memory 210708 kb
Host smart-8d42a8ef-818f-4c8c-9a67-635c1a7274c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139249717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3139249717
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1764327246
Short name T203
Test name
Test status
Simulation time 2544705464 ps
CPU time 25.18 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:34 PM PST 23
Peak memory 212644 kb
Host smart-82589362-a3d2-48d3-a3b0-243a65f49f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764327246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1764327246
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3684215398
Short name T43
Test name
Test status
Simulation time 36130573667 ps
CPU time 51.07 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 12:40:52 PM PST 23
Peak memory 216564 kb
Host smart-0c944a3a-5782-4baa-845a-fd35d25a6c3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684215398 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3684215398
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.857308867
Short name T102
Test name
Test status
Simulation time 502774578261 ps
CPU time 5004.85 seconds
Started Dec 20 12:38:56 PM PST 23
Finished Dec 20 02:03:34 PM PST 23
Peak memory 276488 kb
Host smart-859845bc-403a-418b-856e-3bfc9863bd29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857308867 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.857308867
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2498005290
Short name T315
Test name
Test status
Simulation time 1816737657 ps
CPU time 15.07 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:40:55 PM PST 23
Peak memory 211000 kb
Host smart-74f7e5a9-d113-4fd8-91d6-5a29b6ab14e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498005290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2498005290
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.160051621
Short name T10
Test name
Test status
Simulation time 15438367365 ps
CPU time 198.18 seconds
Started Dec 20 12:38:58 PM PST 23
Finished Dec 20 12:43:19 PM PST 23
Peak memory 237400 kb
Host smart-564a7e13-0e12-4405-83c6-0f809b2afb4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160051621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.160051621
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.1094581344
Short name T314
Test name
Test status
Simulation time 14655286466 ps
CPU time 32.27 seconds
Started Dec 20 12:38:58 PM PST 23
Finished Dec 20 12:40:33 PM PST 23
Peak memory 211320 kb
Host smart-784a26e8-3358-42a0-a891-207ed9b7e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094581344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.1094581344
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.793853465
Short name T332
Test name
Test status
Simulation time 1079526690 ps
CPU time 11.72 seconds
Started Dec 20 12:39:32 PM PST 23
Finished Dec 20 12:40:53 PM PST 23
Peak memory 210940 kb
Host smart-808946de-884f-47d5-bf9d-e53a391acd26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793853465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.793853465
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2208924480
Short name T333
Test name
Test status
Simulation time 14516895484 ps
CPU time 37.35 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:41:08 PM PST 23
Peak memory 213188 kb
Host smart-a162e255-fd28-43ca-95d8-ab362916c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208924480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2208924480
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3365285473
Short name T322
Test name
Test status
Simulation time 1593083411 ps
CPU time 22.03 seconds
Started Dec 20 12:39:25 PM PST 23
Finished Dec 20 12:40:53 PM PST 23
Peak memory 215292 kb
Host smart-44512d29-7fd7-4033-acbb-e60440f43115
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365285473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3365285473
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2167808682
Short name T347
Test name
Test status
Simulation time 206006439431 ps
CPU time 2377.68 seconds
Started Dec 20 12:38:54 PM PST 23
Finished Dec 20 01:19:32 PM PST 23
Peak memory 238276 kb
Host smart-51fb2ae8-7852-4dd3-a71e-d69df6e2ba9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167808682 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2167808682
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3697242338
Short name T197
Test name
Test status
Simulation time 1618138594 ps
CPU time 13.94 seconds
Started Dec 20 12:39:22 PM PST 23
Finished Dec 20 12:40:47 PM PST 23
Peak memory 210776 kb
Host smart-65319a75-2348-44eb-92cb-d0923f4decab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697242338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3697242338
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.699503547
Short name T208
Test name
Test status
Simulation time 4215912189 ps
CPU time 139.98 seconds
Started Dec 20 12:38:40 PM PST 23
Finished Dec 20 12:42:09 PM PST 23
Peak memory 237496 kb
Host smart-1a5649b9-9d46-409b-8a55-fba75e09a72a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699503547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.699503547
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2961627067
Short name T7
Test name
Test status
Simulation time 693658964 ps
CPU time 9.73 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:39:54 PM PST 23
Peak memory 210908 kb
Host smart-29f90396-1e4f-458f-b18a-9feb0b472238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961627067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2961627067
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1796748493
Short name T219
Test name
Test status
Simulation time 1255594290 ps
CPU time 11.07 seconds
Started Dec 20 12:38:44 PM PST 23
Finished Dec 20 12:39:55 PM PST 23
Peak memory 210880 kb
Host smart-e6997d30-2f66-495c-8da9-aa09b3cb7985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796748493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1796748493
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.3082402169
Short name T157
Test name
Test status
Simulation time 2512163303 ps
CPU time 24.8 seconds
Started Dec 20 12:38:23 PM PST 23
Finished Dec 20 12:39:46 PM PST 23
Peak memory 212896 kb
Host smart-9bf449ec-0a7d-4851-891c-70074eed01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082402169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.3082402169
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2223316491
Short name T308
Test name
Test status
Simulation time 79666058569 ps
CPU time 39.26 seconds
Started Dec 20 12:39:19 PM PST 23
Finished Dec 20 12:41:08 PM PST 23
Peak memory 212820 kb
Host smart-1087759f-6716-41c3-88db-fe1815943286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223316491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2223316491
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.4016711020
Short name T176
Test name
Test status
Simulation time 55949890439 ps
CPU time 4084 seconds
Started Dec 20 12:39:10 PM PST 23
Finished Dec 20 01:48:19 PM PST 23
Peak memory 235424 kb
Host smart-c54b8ca2-1b6c-4b65-a7a6-e9dd4f6704f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016711020 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.4016711020
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.962844868
Short name T146
Test name
Test status
Simulation time 7118361797 ps
CPU time 14.5 seconds
Started Dec 20 12:38:25 PM PST 23
Finished Dec 20 12:39:45 PM PST 23
Peak memory 211144 kb
Host smart-03ac100c-741b-4dc2-ad45-962cbbb3a30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962844868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.962844868
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.640725472
Short name T331
Test name
Test status
Simulation time 125475071781 ps
CPU time 314.06 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:45:12 PM PST 23
Peak memory 212212 kb
Host smart-79f06703-78ac-4d79-aee4-df8192d65674
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640725472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_co
rrupt_sig_fatal_chk.640725472
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1221551567
Short name T249
Test name
Test status
Simulation time 260780623 ps
CPU time 11.28 seconds
Started Dec 20 12:38:29 PM PST 23
Finished Dec 20 12:39:42 PM PST 23
Peak memory 210960 kb
Host smart-2fc93a7e-8ae3-41b4-96a5-19162c0dec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221551567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1221551567
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1953307901
Short name T238
Test name
Test status
Simulation time 4495688997 ps
CPU time 12.21 seconds
Started Dec 20 12:39:18 PM PST 23
Finished Dec 20 12:40:41 PM PST 23
Peak memory 210996 kb
Host smart-124805cc-8d81-4ffd-8a75-5a029cbb1cb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1953307901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1953307901
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3435534637
Short name T388
Test name
Test status
Simulation time 1890153694 ps
CPU time 21.33 seconds
Started Dec 20 12:38:23 PM PST 23
Finished Dec 20 12:39:45 PM PST 23
Peak memory 212104 kb
Host smart-897af855-82bb-416a-bcbd-bd4f75d7085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435534637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3435534637
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.332051586
Short name T17
Test name
Test status
Simulation time 3207251426 ps
CPU time 10.65 seconds
Started Dec 20 12:38:41 PM PST 23
Finished Dec 20 12:39:57 PM PST 23
Peak memory 210980 kb
Host smart-6c5a6300-aa07-446b-bfba-a0ecda83c824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332051586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.332051586
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.618554978
Short name T163
Test name
Test status
Simulation time 66050048671 ps
CPU time 360.07 seconds
Started Dec 20 12:38:47 PM PST 23
Finished Dec 20 12:45:50 PM PST 23
Peak memory 229004 kb
Host smart-af6dde79-6e8d-4d8a-91af-3f295f707037
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618554978 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.618554978
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.714829917
Short name T158
Test name
Test status
Simulation time 85413542 ps
CPU time 4.39 seconds
Started Dec 20 12:38:48 PM PST 23
Finished Dec 20 12:39:54 PM PST 23
Peak memory 210996 kb
Host smart-bcc6655f-3b32-44f1-9043-483b1bdcb6a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714829917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.714829917
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2998664085
Short name T430
Test name
Test status
Simulation time 12680364781 ps
CPU time 162.29 seconds
Started Dec 20 12:38:34 PM PST 23
Finished Dec 20 12:42:26 PM PST 23
Peak memory 236592 kb
Host smart-11cc0d23-ec72-4a6b-a141-8d9964637713
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998664085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2998664085
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3833312059
Short name T34
Test name
Test status
Simulation time 1702105411 ps
CPU time 19.34 seconds
Started Dec 20 12:38:55 PM PST 23
Finished Dec 20 12:40:34 PM PST 23
Peak memory 211096 kb
Host smart-2592df91-6312-45e3-be33-803ff8b34296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833312059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3833312059
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3699880049
Short name T376
Test name
Test status
Simulation time 1742770652 ps
CPU time 8.09 seconds
Started Dec 20 12:38:30 PM PST 23
Finished Dec 20 12:39:40 PM PST 23
Peak memory 210944 kb
Host smart-866fb549-7fec-476b-b607-722258156ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699880049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3699880049
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2281865037
Short name T289
Test name
Test status
Simulation time 7619832112 ps
CPU time 21.69 seconds
Started Dec 20 12:38:26 PM PST 23
Finished Dec 20 12:39:56 PM PST 23
Peak memory 212992 kb
Host smart-1c6ae2aa-a7a0-4162-9115-75f995483218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281865037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2281865037
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1302996415
Short name T318
Test name
Test status
Simulation time 2058392592 ps
CPU time 34.94 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:40:27 PM PST 23
Peak memory 215760 kb
Host smart-97c200cb-94e0-4882-8201-2909ec3ae3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302996415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1302996415
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1679194548
Short name T352
Test name
Test status
Simulation time 1488426430 ps
CPU time 6.92 seconds
Started Dec 20 12:38:26 PM PST 23
Finished Dec 20 12:39:35 PM PST 23
Peak memory 211040 kb
Host smart-2b0939da-59c9-419a-86da-a57ed722b4e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679194548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1679194548
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3658727272
Short name T356
Test name
Test status
Simulation time 47529409039 ps
CPU time 201.83 seconds
Started Dec 20 12:38:47 PM PST 23
Finished Dec 20 12:43:09 PM PST 23
Peak memory 236548 kb
Host smart-599507bc-7765-43cc-95df-28fec8f21f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658727272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3658727272
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2239294150
Short name T30
Test name
Test status
Simulation time 1244619460 ps
CPU time 11.42 seconds
Started Dec 20 12:38:51 PM PST 23
Finished Dec 20 12:40:04 PM PST 23
Peak memory 211072 kb
Host smart-d93377fc-7f0b-4adc-8e3e-b2951b29c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239294150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2239294150
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2691597272
Short name T417
Test name
Test status
Simulation time 3289542431 ps
CPU time 8.55 seconds
Started Dec 20 12:38:28 PM PST 23
Finished Dec 20 12:39:36 PM PST 23
Peak memory 210856 kb
Host smart-daecfa84-882b-469f-92b9-81155e43a465
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2691597272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2691597272
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.101265364
Short name T291
Test name
Test status
Simulation time 2144653602 ps
CPU time 25.59 seconds
Started Dec 20 12:38:42 PM PST 23
Finished Dec 20 12:40:05 PM PST 23
Peak memory 212236 kb
Host smart-8d2cfc80-b5a4-4b7b-9f76-747a81ee0e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101265364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.101265364
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3202562916
Short name T401
Test name
Test status
Simulation time 1512045039 ps
CPU time 17.72 seconds
Started Dec 20 12:38:29 PM PST 23
Finished Dec 20 12:39:55 PM PST 23
Peak memory 211440 kb
Host smart-9ba3bedc-2255-41d3-84c0-63ee361523e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202562916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3202562916
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2901269896
Short name T360
Test name
Test status
Simulation time 198202086830 ps
CPU time 2477.3 seconds
Started Dec 20 12:38:53 PM PST 23
Finished Dec 20 01:21:36 PM PST 23
Peak memory 235604 kb
Host smart-373a920f-39d5-402e-8a7b-80c911d646be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901269896 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.2901269896
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.558157775
Short name T38
Test name
Test status
Simulation time 1905063740 ps
CPU time 9.1 seconds
Started Dec 20 12:38:42 PM PST 23
Finished Dec 20 12:39:51 PM PST 23
Peak memory 210944 kb
Host smart-a8cd9ec4-b384-4fea-8b64-9eaacdb8df6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558157775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.558157775
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1257686613
Short name T370
Test name
Test status
Simulation time 40173237590 ps
CPU time 187.12 seconds
Started Dec 20 12:39:05 PM PST 23
Finished Dec 20 12:43:15 PM PST 23
Peak memory 236568 kb
Host smart-dc82b8a1-b5e1-46dc-87d3-bd17d77031b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257686613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1257686613
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3017909522
Short name T258
Test name
Test status
Simulation time 16099386706 ps
CPU time 32.9 seconds
Started Dec 20 12:39:15 PM PST 23
Finished Dec 20 12:40:54 PM PST 23
Peak memory 211368 kb
Host smart-9190bf21-e768-4c7e-9ffc-47beec15ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017909522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3017909522
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.64010683
Short name T155
Test name
Test status
Simulation time 6579507520 ps
CPU time 14.55 seconds
Started Dec 20 12:38:35 PM PST 23
Finished Dec 20 12:40:12 PM PST 23
Peak memory 211004 kb
Host smart-3cd7d8a3-6b7b-4b3b-a6fb-054ced5b26c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64010683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.64010683
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1226899438
Short name T182
Test name
Test status
Simulation time 5527767497 ps
CPU time 18.58 seconds
Started Dec 20 12:39:40 PM PST 23
Finished Dec 20 12:41:06 PM PST 23
Peak memory 212628 kb
Host smart-07175029-0d21-4b27-9996-2ddfb62f0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226899438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1226899438
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2487573091
Short name T16
Test name
Test status
Simulation time 1917059480 ps
CPU time 33.5 seconds
Started Dec 20 12:38:32 PM PST 23
Finished Dec 20 12:40:04 PM PST 23
Peak memory 215560 kb
Host smart-55b66caf-7681-4900-a2f4-157ec2fbd535
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487573091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2487573091
Directory /workspace/9.rom_ctrl_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%