Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.58 97.11 92.53 97.88 100.00 98.37 97.89 99.30


Total test records in report: 485
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T269 /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2071858652 Dec 24 12:46:30 PM PST 23 Dec 24 01:42:18 PM PST 23 37545042151 ps
T270 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3542903129 Dec 24 12:47:10 PM PST 23 Dec 24 12:51:52 PM PST 23 24117520307 ps
T271 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.228619810 Dec 24 12:47:15 PM PST 23 Dec 24 12:52:12 PM PST 23 55524425172 ps
T272 /workspace/coverage/default/17.rom_ctrl_alert_test.1940395009 Dec 24 12:46:56 PM PST 23 Dec 24 12:47:16 PM PST 23 5507270511 ps
T273 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1001115244 Dec 24 12:47:31 PM PST 23 Dec 24 12:48:02 PM PST 23 14381918449 ps
T274 /workspace/coverage/default/31.rom_ctrl_smoke.713221205 Dec 24 12:47:14 PM PST 23 Dec 24 12:47:53 PM PST 23 3240252924 ps
T275 /workspace/coverage/default/4.rom_ctrl_alert_test.2814569654 Dec 24 12:46:28 PM PST 23 Dec 24 12:46:44 PM PST 23 23332078817 ps
T276 /workspace/coverage/default/18.rom_ctrl_smoke.1651891157 Dec 24 12:46:58 PM PST 23 Dec 24 12:47:31 PM PST 23 1729231042 ps
T277 /workspace/coverage/default/23.rom_ctrl_stress_all.4065893639 Dec 24 12:47:12 PM PST 23 Dec 24 12:48:21 PM PST 23 34622274955 ps
T278 /workspace/coverage/default/49.rom_ctrl_alert_test.2486378983 Dec 24 12:47:26 PM PST 23 Dec 24 12:47:42 PM PST 23 4614630978 ps
T279 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2542336938 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:28 PM PST 23 1403111686 ps
T280 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1566532357 Dec 24 12:47:01 PM PST 23 Dec 24 12:47:39 PM PST 23 6183995200 ps
T281 /workspace/coverage/default/38.rom_ctrl_alert_test.923692636 Dec 24 12:47:31 PM PST 23 Dec 24 12:47:39 PM PST 23 85648281 ps
T282 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.834263822 Dec 24 12:46:46 PM PST 23 Dec 24 12:46:58 PM PST 23 831966105 ps
T283 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3418304106 Dec 24 12:47:14 PM PST 23 Dec 24 12:52:22 PM PST 23 51025815690 ps
T284 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1274216402 Dec 24 12:47:22 PM PST 23 Dec 24 12:47:32 PM PST 23 93686455 ps
T285 /workspace/coverage/default/28.rom_ctrl_smoke.3386889171 Dec 24 12:47:07 PM PST 23 Dec 24 12:47:24 PM PST 23 2889230581 ps
T286 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.902675817 Dec 24 12:47:26 PM PST 23 Dec 24 01:13:13 PM PST 23 443075231299 ps
T287 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2162091376 Dec 24 12:46:55 PM PST 23 Dec 24 02:10:50 PM PST 23 254162747203 ps
T288 /workspace/coverage/default/37.rom_ctrl_stress_all.2371158825 Dec 24 12:47:28 PM PST 23 Dec 24 12:48:27 PM PST 23 4472333510 ps
T289 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.218348626 Dec 24 12:46:10 PM PST 23 Dec 24 12:46:51 PM PST 23 3715240666 ps
T290 /workspace/coverage/default/2.rom_ctrl_smoke.3693328743 Dec 24 12:46:26 PM PST 23 Dec 24 12:46:38 PM PST 23 753463263 ps
T291 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1738145521 Dec 24 12:47:31 PM PST 23 Dec 24 12:47:45 PM PST 23 6069644300 ps
T292 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.879310939 Dec 24 12:46:57 PM PST 23 Dec 24 12:52:45 PM PST 23 96770624025 ps
T293 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2409307935 Dec 24 12:47:31 PM PST 23 Dec 24 12:47:42 PM PST 23 739149505 ps
T294 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.382608054 Dec 24 12:47:13 PM PST 23 Dec 24 12:53:58 PM PST 23 41288710385 ps
T295 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3585446691 Dec 24 12:46:48 PM PST 23 Dec 24 12:48:14 PM PST 23 1996226214 ps
T296 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2713961406 Dec 24 12:46:46 PM PST 23 Dec 24 12:48:05 PM PST 23 1270302495 ps
T297 /workspace/coverage/default/23.rom_ctrl_smoke.644873696 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:41 PM PST 23 2431447893 ps
T298 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2058452664 Dec 24 12:47:26 PM PST 23 Dec 24 01:18:48 PM PST 23 24681188158 ps
T299 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4057561804 Dec 24 12:47:38 PM PST 23 Dec 24 12:49:27 PM PST 23 1714285310 ps
T300 /workspace/coverage/default/25.rom_ctrl_alert_test.4198370552 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:28 PM PST 23 14244503655 ps
T301 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1889897618 Dec 24 12:47:29 PM PST 23 Dec 24 12:47:46 PM PST 23 1241795248 ps
T302 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4264386189 Dec 24 12:46:53 PM PST 23 Dec 24 12:49:30 PM PST 23 19771679430 ps
T303 /workspace/coverage/default/39.rom_ctrl_alert_test.3835800433 Dec 24 12:47:30 PM PST 23 Dec 24 12:47:47 PM PST 23 5603768454 ps
T304 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2424394559 Dec 24 12:47:21 PM PST 23 Dec 24 12:50:09 PM PST 23 12495213395 ps
T305 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4019419631 Dec 24 12:47:33 PM PST 23 Dec 24 12:50:20 PM PST 23 49240280866 ps
T306 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.231858880 Dec 24 12:46:48 PM PST 23 Dec 24 12:47:00 PM PST 23 173486624 ps
T307 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.832161906 Dec 24 12:46:13 PM PST 23 Dec 24 12:46:39 PM PST 23 1998044692 ps
T308 /workspace/coverage/default/22.rom_ctrl_alert_test.1017740121 Dec 24 12:47:10 PM PST 23 Dec 24 12:47:31 PM PST 23 7934347245 ps
T309 /workspace/coverage/default/21.rom_ctrl_alert_test.3629754136 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:27 PM PST 23 3142036801 ps
T310 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1025375295 Dec 24 12:46:13 PM PST 23 Dec 24 12:46:34 PM PST 23 920975611 ps
T311 /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.318056159 Dec 24 12:47:13 PM PST 23 Dec 24 03:13:42 PM PST 23 89455023174 ps
T312 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3272113086 Dec 24 12:47:31 PM PST 23 Dec 24 12:48:04 PM PST 23 10869249694 ps
T313 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1902854685 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:21 PM PST 23 218258271 ps
T314 /workspace/coverage/default/39.rom_ctrl_stress_all.2963897510 Dec 24 12:47:30 PM PST 23 Dec 24 12:48:34 PM PST 23 10432285898 ps
T315 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4158205606 Dec 24 12:46:15 PM PST 23 Dec 24 12:50:57 PM PST 23 16125553099 ps
T316 /workspace/coverage/default/7.rom_ctrl_stress_all.1035334079 Dec 24 12:46:26 PM PST 23 Dec 24 12:46:53 PM PST 23 428912950 ps
T317 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1892887339 Dec 24 12:47:48 PM PST 23 Dec 24 12:47:59 PM PST 23 173780658 ps
T318 /workspace/coverage/default/40.rom_ctrl_stress_all.2803509818 Dec 24 12:47:25 PM PST 23 Dec 24 12:47:37 PM PST 23 111447691 ps
T319 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1539905599 Dec 24 12:46:55 PM PST 23 Dec 24 12:47:08 PM PST 23 388243076 ps
T320 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3369599800 Dec 24 12:47:11 PM PST 23 Dec 24 12:47:48 PM PST 23 70057597730 ps
T321 /workspace/coverage/default/15.rom_ctrl_smoke.1505002497 Dec 24 12:46:48 PM PST 23 Dec 24 12:47:17 PM PST 23 1549307083 ps
T322 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2320127885 Dec 24 12:47:31 PM PST 23 Dec 24 12:47:45 PM PST 23 666717509 ps
T323 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1561187300 Dec 24 12:46:11 PM PST 23 Dec 24 12:50:56 PM PST 23 105934893496 ps
T324 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2800982516 Dec 24 12:47:19 PM PST 23 Dec 24 12:50:42 PM PST 23 16533619419 ps
T325 /workspace/coverage/default/30.rom_ctrl_stress_all.634124997 Dec 24 12:47:11 PM PST 23 Dec 24 12:47:34 PM PST 23 9808319771 ps
T326 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.206667377 Dec 24 12:47:27 PM PST 23 Dec 24 12:47:41 PM PST 23 243581426 ps
T327 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2127667976 Dec 24 12:47:26 PM PST 23 Dec 24 12:47:38 PM PST 23 1654885541 ps
T328 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.982892693 Dec 24 12:46:24 PM PST 23 Dec 24 12:53:08 PM PST 23 20544912454 ps
T329 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2974134867 Dec 24 12:46:49 PM PST 23 Dec 24 12:47:07 PM PST 23 1864451426 ps
T330 /workspace/coverage/default/26.rom_ctrl_smoke.1525866070 Dec 24 12:47:07 PM PST 23 Dec 24 12:47:28 PM PST 23 4363118209 ps
T331 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2916567202 Dec 24 12:47:13 PM PST 23 Dec 24 02:03:42 PM PST 23 66580769565 ps
T332 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4054599974 Dec 24 12:46:26 PM PST 23 Dec 24 12:46:38 PM PST 23 334251975 ps
T333 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3686292186 Dec 24 12:47:42 PM PST 23 Dec 24 12:54:54 PM PST 23 285673155937 ps
T334 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.268833126 Dec 24 12:47:30 PM PST 23 Dec 24 12:47:57 PM PST 23 2122288738 ps
T335 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2609696371 Dec 24 12:47:00 PM PST 23 Dec 24 12:47:25 PM PST 23 1784506977 ps
T37 /workspace/coverage/default/0.rom_ctrl_sec_cm.2374450704 Dec 24 12:46:04 PM PST 23 Dec 24 12:48:03 PM PST 23 1359215474 ps
T49 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3779139202 Dec 24 12:47:29 PM PST 23 Dec 24 01:00:57 PM PST 23 38721311567 ps
T50 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2542233393 Dec 24 12:47:27 PM PST 23 Dec 24 01:18:18 PM PST 23 51503625408 ps
T336 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1493226774 Dec 24 12:46:47 PM PST 23 Dec 24 12:46:55 PM PST 23 102814886 ps
T337 /workspace/coverage/default/19.rom_ctrl_smoke.3648791058 Dec 24 12:46:51 PM PST 23 Dec 24 12:47:11 PM PST 23 750836271 ps
T338 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3961843370 Dec 24 12:47:28 PM PST 23 Dec 24 12:48:58 PM PST 23 3036129262 ps
T339 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.650491217 Dec 24 12:47:09 PM PST 23 Dec 24 01:15:15 PM PST 23 30587617884 ps
T340 /workspace/coverage/default/35.rom_ctrl_smoke.2718574241 Dec 24 12:47:15 PM PST 23 Dec 24 12:47:31 PM PST 23 380044719 ps
T341 /workspace/coverage/default/31.rom_ctrl_alert_test.2326853099 Dec 24 12:47:11 PM PST 23 Dec 24 12:47:21 PM PST 23 85578938 ps
T342 /workspace/coverage/default/38.rom_ctrl_stress_all.67477591 Dec 24 12:47:30 PM PST 23 Dec 24 12:48:10 PM PST 23 17948725494 ps
T343 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2319763503 Dec 24 12:47:15 PM PST 23 Dec 24 12:47:42 PM PST 23 1740492393 ps
T344 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.315580866 Dec 24 12:47:16 PM PST 23 Dec 24 12:51:17 PM PST 23 3571734723 ps
T345 /workspace/coverage/default/17.rom_ctrl_stress_all.265812159 Dec 24 12:47:01 PM PST 23 Dec 24 12:47:21 PM PST 23 181256816 ps
T346 /workspace/coverage/default/42.rom_ctrl_alert_test.3015419901 Dec 24 12:47:27 PM PST 23 Dec 24 12:47:46 PM PST 23 2932138414 ps
T347 /workspace/coverage/default/48.rom_ctrl_alert_test.1540055792 Dec 24 12:47:47 PM PST 23 Dec 24 12:47:54 PM PST 23 332741946 ps
T348 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3215350474 Dec 24 12:46:00 PM PST 23 Dec 24 12:49:32 PM PST 23 14464694478 ps
T349 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3218204298 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:26 PM PST 23 20623745113 ps
T350 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2642178053 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:49 PM PST 23 36428609846 ps
T351 /workspace/coverage/default/31.rom_ctrl_stress_all.466484767 Dec 24 12:47:15 PM PST 23 Dec 24 12:47:51 PM PST 23 695687162 ps
T352 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3324630238 Dec 24 12:47:28 PM PST 23 Dec 24 12:49:37 PM PST 23 48257423543 ps
T353 /workspace/coverage/default/33.rom_ctrl_smoke.2976974933 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:46 PM PST 23 3160301951 ps
T354 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2181567394 Dec 24 12:47:26 PM PST 23 Dec 24 12:48:50 PM PST 23 20587731374 ps
T355 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4026135844 Dec 24 12:46:56 PM PST 23 Dec 24 12:47:20 PM PST 23 5038160392 ps
T356 /workspace/coverage/default/4.rom_ctrl_smoke.1634932056 Dec 24 12:46:23 PM PST 23 Dec 24 12:46:56 PM PST 23 14320894939 ps
T357 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4037244857 Dec 24 12:47:25 PM PST 23 Dec 24 12:48:04 PM PST 23 3949827007 ps
T358 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3034919817 Dec 24 12:46:32 PM PST 23 Dec 24 01:20:38 PM PST 23 27439216072 ps
T359 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1692093330 Dec 24 12:47:14 PM PST 23 Dec 24 12:47:52 PM PST 23 3911835090 ps
T360 /workspace/coverage/default/10.rom_ctrl_stress_all.2956227642 Dec 24 12:46:16 PM PST 23 Dec 24 12:47:01 PM PST 23 4382000731 ps
T361 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3354746529 Dec 24 12:46:14 PM PST 23 Dec 24 12:46:37 PM PST 23 1017217316 ps
T362 /workspace/coverage/default/11.rom_ctrl_alert_test.360428585 Dec 24 12:46:42 PM PST 23 Dec 24 12:46:53 PM PST 23 1628876934 ps
T363 /workspace/coverage/default/6.rom_ctrl_stress_all.858649987 Dec 24 12:46:25 PM PST 23 Dec 24 12:46:53 PM PST 23 827285343 ps
T364 /workspace/coverage/default/13.rom_ctrl_stress_all.3919636673 Dec 24 12:46:53 PM PST 23 Dec 24 12:47:23 PM PST 23 13416842200 ps
T365 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.160790886 Dec 24 12:47:12 PM PST 23 Dec 24 12:51:33 PM PST 23 90249638347 ps
T366 /workspace/coverage/default/43.rom_ctrl_alert_test.3730039524 Dec 24 12:47:34 PM PST 23 Dec 24 12:47:42 PM PST 23 416555236 ps
T367 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.688327919 Dec 24 12:46:28 PM PST 23 Dec 24 12:46:55 PM PST 23 2540607021 ps
T368 /workspace/coverage/default/14.rom_ctrl_stress_all.613209305 Dec 24 12:46:46 PM PST 23 Dec 24 12:47:23 PM PST 23 18874740459 ps
T369 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3050520860 Dec 24 12:47:27 PM PST 23 Dec 24 12:51:12 PM PST 23 4270229148 ps
T370 /workspace/coverage/default/34.rom_ctrl_stress_all.49745250 Dec 24 12:47:13 PM PST 23 Dec 24 12:48:09 PM PST 23 16585395921 ps
T371 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2070334836 Dec 24 12:47:03 PM PST 23 Dec 24 12:47:20 PM PST 23 782685442 ps
T372 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3672580911 Dec 24 12:46:10 PM PST 23 Dec 24 12:46:39 PM PST 23 1971047291 ps
T373 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3991592673 Dec 24 12:47:31 PM PST 23 Dec 24 12:47:46 PM PST 23 168984669 ps
T374 /workspace/coverage/default/40.rom_ctrl_smoke.3956141564 Dec 24 12:47:30 PM PST 23 Dec 24 12:48:01 PM PST 23 10296266842 ps
T375 /workspace/coverage/default/34.rom_ctrl_smoke.2641178610 Dec 24 12:47:16 PM PST 23 Dec 24 12:47:47 PM PST 23 23804763227 ps
T376 /workspace/coverage/default/0.rom_ctrl_stress_all.4288528184 Dec 24 12:46:02 PM PST 23 Dec 24 12:46:43 PM PST 23 4640165085 ps
T377 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3610593761 Dec 24 12:46:44 PM PST 23 Dec 24 01:07:48 PM PST 23 27749856154 ps
T378 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.698434340 Dec 24 12:47:16 PM PST 23 Dec 24 12:47:56 PM PST 23 4265405507 ps
T379 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1009749446 Dec 24 12:46:16 PM PST 23 Dec 24 12:51:44 PM PST 23 76443840968 ps
T380 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.458614262 Dec 24 12:47:35 PM PST 23 Dec 24 12:47:51 PM PST 23 1970581953 ps
T381 /workspace/coverage/default/20.rom_ctrl_alert_test.565146147 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:27 PM PST 23 14006721443 ps
T382 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3389364190 Dec 24 12:47:12 PM PST 23 Dec 24 12:47:27 PM PST 23 794035782 ps
T383 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3436448812 Dec 24 12:47:27 PM PST 23 Dec 24 12:47:49 PM PST 23 14285519312 ps
T384 /workspace/coverage/default/24.rom_ctrl_stress_all.1479764190 Dec 24 12:47:13 PM PST 23 Dec 24 12:47:42 PM PST 23 6120856388 ps
T385 /workspace/coverage/default/41.rom_ctrl_smoke.3020715063 Dec 24 12:47:35 PM PST 23 Dec 24 12:48:05 PM PST 23 2151947299 ps
T386 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2052701753 Dec 24 12:47:01 PM PST 23 Dec 24 12:48:57 PM PST 23 1780047033 ps
T387 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3241184092 Dec 24 12:47:33 PM PST 23 Dec 24 12:47:52 PM PST 23 10138795653 ps
T388 /workspace/coverage/default/16.rom_ctrl_smoke.1631237931 Dec 24 12:46:48 PM PST 23 Dec 24 12:47:16 PM PST 23 2071266883 ps
T389 /workspace/coverage/default/47.rom_ctrl_alert_test.3976328651 Dec 24 12:47:33 PM PST 23 Dec 24 12:47:48 PM PST 23 5067522171 ps
T390 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2055638891 Dec 24 12:47:29 PM PST 23 Dec 24 12:47:51 PM PST 23 6956971186 ps
T391 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.186400983 Dec 24 12:46:22 PM PST 23 Dec 24 12:46:38 PM PST 23 1191958475 ps
T392 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1001371465 Dec 24 12:47:42 PM PST 23 Dec 24 12:48:15 PM PST 23 13602445749 ps
T393 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2033859228 Dec 24 12:46:51 PM PST 23 Dec 24 01:20:54 PM PST 23 37164323474 ps
T394 /workspace/coverage/default/13.rom_ctrl_alert_test.2597211435 Dec 24 12:46:46 PM PST 23 Dec 24 12:47:01 PM PST 23 1365601377 ps
T395 /workspace/coverage/default/9.rom_ctrl_stress_all.3513317395 Dec 24 12:46:12 PM PST 23 Dec 24 12:47:18 PM PST 23 8008497211 ps
T396 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2307928961 Dec 24 12:46:56 PM PST 23 Dec 24 12:47:35 PM PST 23 14567445073 ps
T397 /workspace/coverage/default/36.rom_ctrl_alert_test.1758542003 Dec 24 12:47:33 PM PST 23 Dec 24 12:47:50 PM PST 23 15613959442 ps
T398 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.707870152 Dec 24 12:46:33 PM PST 23 Dec 24 02:26:10 PM PST 23 208163455547 ps
T399 /workspace/coverage/default/9.rom_ctrl_alert_test.4103698136 Dec 24 12:46:23 PM PST 23 Dec 24 12:46:41 PM PST 23 1754751340 ps
T400 /workspace/coverage/default/15.rom_ctrl_stress_all.3317970904 Dec 24 12:46:48 PM PST 23 Dec 24 12:47:09 PM PST 23 230740319 ps
T401 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.104516762 Dec 24 12:47:30 PM PST 23 Dec 24 12:47:40 PM PST 23 376808716 ps
T402 /workspace/coverage/default/42.rom_ctrl_stress_all.63263242 Dec 24 12:47:26 PM PST 23 Dec 24 12:48:14 PM PST 23 4429561979 ps
T403 /workspace/coverage/default/8.rom_ctrl_alert_test.4130889808 Dec 24 12:46:12 PM PST 23 Dec 24 12:46:36 PM PST 23 7759615041 ps
T404 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3363934868 Dec 24 12:47:08 PM PST 23 Dec 24 01:09:26 PM PST 23 94837380303 ps
T405 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.364118953 Dec 24 12:46:49 PM PST 23 Dec 24 12:50:05 PM PST 23 84731044072 ps
T406 /workspace/coverage/default/27.rom_ctrl_smoke.2768500151 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:52 PM PST 23 4025536859 ps
T407 /workspace/coverage/default/43.rom_ctrl_stress_all.1965504908 Dec 24 12:47:27 PM PST 23 Dec 24 12:47:54 PM PST 23 1508586505 ps
T408 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3839213609 Dec 24 12:47:10 PM PST 23 Dec 24 12:47:24 PM PST 23 177103933 ps
T409 /workspace/coverage/default/49.rom_ctrl_smoke.340713042 Dec 24 12:47:47 PM PST 23 Dec 24 12:48:14 PM PST 23 2532581566 ps
T42 /workspace/coverage/default/3.rom_ctrl_sec_cm.3165843500 Dec 24 12:46:25 PM PST 23 Dec 24 12:48:22 PM PST 23 801964263 ps
T410 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.347565963 Dec 24 12:46:24 PM PST 23 Dec 24 12:46:33 PM PST 23 733156186 ps
T411 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1093155003 Dec 24 12:46:15 PM PST 23 Dec 24 12:49:01 PM PST 23 3311201109 ps
T412 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.483218654 Dec 24 12:47:27 PM PST 23 Dec 24 12:47:41 PM PST 23 347460123 ps
T413 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.759137836 Dec 24 12:47:07 PM PST 23 Dec 24 12:47:19 PM PST 23 707448428 ps
T414 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2311217354 Dec 24 12:46:12 PM PST 23 Dec 24 12:46:57 PM PST 23 5019638431 ps
T43 /workspace/coverage/default/1.rom_ctrl_sec_cm.5737432 Dec 24 12:46:20 PM PST 23 Dec 24 12:48:19 PM PST 23 2239295897 ps
T415 /workspace/coverage/default/3.rom_ctrl_smoke.3378184441 Dec 24 12:46:05 PM PST 23 Dec 24 12:46:25 PM PST 23 744193955 ps
T416 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1939875001 Dec 24 12:47:11 PM PST 23 Dec 24 12:47:22 PM PST 23 1307704767 ps
T417 /workspace/coverage/default/21.rom_ctrl_stress_all.1030387351 Dec 24 12:46:59 PM PST 23 Dec 24 12:48:14 PM PST 23 21852640664 ps
T418 /workspace/coverage/default/30.rom_ctrl_alert_test.746457948 Dec 24 12:47:19 PM PST 23 Dec 24 12:47:36 PM PST 23 4146362311 ps
T419 /workspace/coverage/default/14.rom_ctrl_smoke.2387913406 Dec 24 12:46:45 PM PST 23 Dec 24 12:47:20 PM PST 23 14852611900 ps
T420 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2348163831 Dec 24 12:46:54 PM PST 23 Dec 24 01:04:43 PM PST 23 24531573635 ps
T421 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1621751873 Dec 24 12:46:10 PM PST 23 Dec 24 12:46:30 PM PST 23 954230899 ps
T422 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.566201318 Dec 24 12:46:55 PM PST 23 Dec 24 12:47:36 PM PST 23 22294433742 ps
T122 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.727792925 Dec 24 12:47:37 PM PST 23 Dec 24 01:14:59 PM PST 23 44114331993 ps
T423 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1839138563 Dec 24 12:47:15 PM PST 23 Dec 24 12:56:05 PM PST 23 58198013629 ps
T424 /workspace/coverage/default/42.rom_ctrl_smoke.2630164653 Dec 24 12:47:24 PM PST 23 Dec 24 12:48:09 PM PST 23 15659415603 ps
T425 /workspace/coverage/default/44.rom_ctrl_alert_test.149950988 Dec 24 12:47:36 PM PST 23 Dec 24 12:47:49 PM PST 23 3774764281 ps
T426 /workspace/coverage/default/8.rom_ctrl_stress_all.2589862062 Dec 24 12:46:16 PM PST 23 Dec 24 12:46:53 PM PST 23 2288754461 ps
T427 /workspace/coverage/default/4.rom_ctrl_stress_all.3279605035 Dec 24 12:46:31 PM PST 23 Dec 24 12:47:47 PM PST 23 7714806931 ps
T428 /workspace/coverage/default/25.rom_ctrl_smoke.3673047960 Dec 24 12:47:09 PM PST 23 Dec 24 12:47:39 PM PST 23 9082755150 ps
T429 /workspace/coverage/default/18.rom_ctrl_alert_test.3950343304 Dec 24 12:46:46 PM PST 23 Dec 24 12:47:00 PM PST 23 1275959220 ps
T430 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2664684769 Dec 24 12:47:32 PM PST 23 Dec 24 12:53:24 PM PST 23 59466464735 ps
T431 /workspace/coverage/default/32.rom_ctrl_alert_test.2623182904 Dec 24 12:47:11 PM PST 23 Dec 24 12:47:29 PM PST 23 10248684236 ps
T432 /workspace/coverage/default/3.rom_ctrl_stress_all.3005640249 Dec 24 12:46:50 PM PST 23 Dec 24 12:47:46 PM PST 23 16633389956 ps
T433 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4155576438 Dec 24 12:46:06 PM PST 23 Dec 24 12:46:43 PM PST 23 5856712468 ps
T434 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1955565768 Dec 24 12:47:34 PM PST 23 Dec 24 12:48:00 PM PST 23 2233972662 ps
T435 /workspace/coverage/default/1.rom_ctrl_smoke.4290669729 Dec 24 12:45:58 PM PST 23 Dec 24 12:46:32 PM PST 23 10078979447 ps
T436 /workspace/coverage/default/12.rom_ctrl_smoke.205288774 Dec 24 12:46:32 PM PST 23 Dec 24 12:46:45 PM PST 23 183859693 ps
T437 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1693165533 Dec 24 12:47:21 PM PST 23 Dec 24 12:51:51 PM PST 23 23766192565 ps
T438 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1009529472 Dec 24 12:47:44 PM PST 23 Dec 24 01:18:49 PM PST 23 116057839565 ps
T439 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1251706902 Dec 24 12:30:49 PM PST 23 Dec 24 12:31:24 PM PST 23 2054548792 ps
T440 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1113861235 Dec 24 12:30:36 PM PST 23 Dec 24 12:31:14 PM PST 23 5834796732 ps
T441 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3696102248 Dec 24 12:30:45 PM PST 23 Dec 24 12:31:19 PM PST 23 722528059 ps
T95 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1487784008 Dec 24 12:30:21 PM PST 23 Dec 24 12:33:14 PM PST 23 8757962826 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2482804501 Dec 24 12:30:07 PM PST 23 Dec 24 12:30:38 PM PST 23 346816603 ps
T443 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.327251928 Dec 24 12:30:16 PM PST 23 Dec 24 12:30:48 PM PST 23 1505113548 ps
T112 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.141643302 Dec 24 12:30:18 PM PST 23 Dec 24 12:31:20 PM PST 23 157701441 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2573565583 Dec 24 12:31:04 PM PST 23 Dec 24 12:31:30 PM PST 23 1038294344 ps
T445 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.572671518 Dec 24 12:31:06 PM PST 23 Dec 24 12:31:38 PM PST 23 7796129214 ps
T117 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.718192296 Dec 24 12:30:24 PM PST 23 Dec 24 12:31:38 PM PST 23 3076665266 ps
T446 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1288037694 Dec 24 12:30:54 PM PST 23 Dec 24 12:31:28 PM PST 23 14399075526 ps
T447 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1501934724 Dec 24 12:30:33 PM PST 23 Dec 24 12:31:50 PM PST 23 1010540740 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3097677805 Dec 24 12:30:19 PM PST 23 Dec 24 12:30:48 PM PST 23 1627709105 ps
T114 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.613842051 Dec 24 12:30:38 PM PST 23 Dec 24 12:32:22 PM PST 23 5447499694 ps
T449 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4275220467 Dec 24 12:30:16 PM PST 23 Dec 24 12:30:52 PM PST 23 4919280064 ps
T100 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2969710923 Dec 24 12:30:15 PM PST 23 Dec 24 12:30:44 PM PST 23 378726210 ps
T450 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3065314761 Dec 24 12:30:22 PM PST 23 Dec 24 12:30:50 PM PST 23 658497997 ps
T96 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3197505116 Dec 24 12:31:11 PM PST 23 Dec 24 12:34:36 PM PST 23 39721311663 ps
T121 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.391297242 Dec 24 12:30:31 PM PST 23 Dec 24 12:31:46 PM PST 23 7213720440 ps
T99 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2162761773 Dec 24 12:30:05 PM PST 23 Dec 24 12:36:08 PM PST 23 35397304790 ps
T451 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3478264816 Dec 24 12:30:19 PM PST 23 Dec 24 12:30:54 PM PST 23 6318249048 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3863286501 Dec 24 12:30:28 PM PST 23 Dec 24 12:31:09 PM PST 23 5131532986 ps
T453 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3126939807 Dec 24 12:30:21 PM PST 23 Dec 24 12:30:54 PM PST 23 1122443278 ps
T454 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2870745382 Dec 24 12:30:24 PM PST 23 Dec 24 12:31:01 PM PST 23 6480829342 ps
T455 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2216127240 Dec 24 12:31:20 PM PST 23 Dec 24 12:34:44 PM PST 23 27158207526 ps
T456 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3877832444 Dec 24 12:30:24 PM PST 23 Dec 24 12:30:54 PM PST 23 1537811958 ps
T457 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.712288844 Dec 24 12:30:16 PM PST 23 Dec 24 12:30:53 PM PST 23 5326115620 ps
T458 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1940424014 Dec 24 12:31:15 PM PST 23 Dec 24 12:34:28 PM PST 23 20789277935 ps
T459 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.90854054 Dec 24 12:30:41 PM PST 23 Dec 24 12:31:13 PM PST 23 99112673 ps
T460 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.43468203 Dec 24 12:31:19 PM PST 23 Dec 24 12:31:50 PM PST 23 426509895 ps
T461 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3153911081 Dec 24 12:30:31 PM PST 23 Dec 24 12:31:07 PM PST 23 556810061 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.280863265 Dec 24 12:31:03 PM PST 23 Dec 24 12:31:32 PM PST 23 1870548146 ps
T463 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1040142268 Dec 24 12:30:14 PM PST 23 Dec 24 12:30:47 PM PST 23 1536204769 ps
T464 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2018808863 Dec 24 12:30:19 PM PST 23 Dec 24 12:31:03 PM PST 23 6785059906 ps
T465 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4101040984 Dec 24 12:31:09 PM PST 23 Dec 24 12:31:37 PM PST 23 624909558 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.111233300 Dec 24 12:30:07 PM PST 23 Dec 24 12:30:46 PM PST 23 7000813941 ps
T101 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2948826273 Dec 24 12:30:25 PM PST 23 Dec 24 12:31:04 PM PST 23 8012994666 ps
T115 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1770055882 Dec 24 12:30:52 PM PST 23 Dec 24 12:32:38 PM PST 23 1666848746 ps
T102 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2753640897 Dec 24 12:30:31 PM PST 23 Dec 24 12:32:27 PM PST 23 10928595974 ps
T467 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1357948887 Dec 24 12:30:47 PM PST 23 Dec 24 12:33:34 PM PST 23 58088883015 ps
T468 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2585215488 Dec 24 12:30:23 PM PST 23 Dec 24 12:31:02 PM PST 23 3067950053 ps
T469 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1473898545 Dec 24 12:30:37 PM PST 23 Dec 24 12:31:42 PM PST 23 299979760 ps
T470 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2764120809 Dec 24 12:30:53 PM PST 23 Dec 24 12:31:27 PM PST 23 1469202884 ps
T471 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3992258710 Dec 24 12:30:13 PM PST 23 Dec 24 12:30:46 PM PST 23 860706603 ps
T472 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3139582173 Dec 24 12:30:24 PM PST 23 Dec 24 12:31:00 PM PST 23 4993448367 ps
T473 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2057197609 Dec 24 12:30:52 PM PST 23 Dec 24 12:31:19 PM PST 23 87318481 ps
T474 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3517841401 Dec 24 12:30:21 PM PST 23 Dec 24 12:30:55 PM PST 23 378178830 ps
T475 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2153066690 Dec 24 12:31:11 PM PST 23 Dec 24 12:31:44 PM PST 23 3118220155 ps
T476 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1105436636 Dec 24 12:30:13 PM PST 23 Dec 24 12:33:29 PM PST 23 23099237586 ps
T477 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2974968269 Dec 24 12:30:22 PM PST 23 Dec 24 12:30:55 PM PST 23 1003529646 ps
T478 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4031814079 Dec 24 12:30:33 PM PST 23 Dec 24 12:33:09 PM PST 23 4454765431 ps
T103 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1691962639 Dec 24 12:30:24 PM PST 23 Dec 24 12:32:17 PM PST 23 6505541005 ps
T479 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2422520010 Dec 24 12:30:06 PM PST 23 Dec 24 12:30:40 PM PST 23 2777048062 ps
T480 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1997207244 Dec 24 12:29:55 PM PST 23 Dec 24 12:31:37 PM PST 23 542018037 ps
T481 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4032525483 Dec 24 12:30:19 PM PST 23 Dec 24 12:30:46 PM PST 23 378239294 ps
T482 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3077713609 Dec 24 12:30:06 PM PST 23 Dec 24 12:30:35 PM PST 23 377824753 ps
T483 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.913436841 Dec 24 12:30:17 PM PST 23 Dec 24 12:30:51 PM PST 23 1314021396 ps
T484 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3485103946 Dec 24 12:29:52 PM PST 23 Dec 24 12:30:29 PM PST 23 5124781115 ps
T485 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3844090819 Dec 24 12:30:46 PM PST 23 Dec 24 12:31:27 PM PST 23 8593189064 ps

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.959400440
Short name T25
Test name
Test status
Simulation time 754812461 ps
CPU time 4.31 seconds
Started Dec 24 12:31:12 PM PST 23
Finished Dec 24 12:31:39 PM PST 23
Peak memory 211116 kb
Host smart-7db3988c-1632-43b7-93f7-b28beb2870db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959400440 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.959400440
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3904885654
Short name T5
Test name
Test status
Simulation time 64547778034 ps
CPU time 335.14 seconds
Started Dec 24 12:47:24 PM PST 23
Finished Dec 24 12:53:04 PM PST 23
Peak memory 237288 kb
Host smart-decfc5da-1d31-4e91-97e4-dd43522fd31e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904885654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3904885654
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2037299483
Short name T30
Test name
Test status
Simulation time 6563880988 ps
CPU time 16.95 seconds
Started Dec 24 12:30:05 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 219328 kb
Host smart-5630bba4-57d8-44c5-8354-079d2bd7bca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037299483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2037299483
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.497581278
Short name T8
Test name
Test status
Simulation time 90371206503 ps
CPU time 1001.98 seconds
Started Dec 24 12:46:54 PM PST 23
Finished Dec 24 01:03:44 PM PST 23
Peak memory 228176 kb
Host smart-e6ae0239-660c-4f4f-93ce-2bcaa7fe9db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497581278 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.497581278
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2933514149
Short name T58
Test name
Test status
Simulation time 1197646559 ps
CPU time 76.82 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:31:57 PM PST 23
Peak memory 212552 kb
Host smart-af61efb0-3aaf-4e40-95cd-63661116e562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933514149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2933514149
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.334345912
Short name T31
Test name
Test status
Simulation time 48932217564 ps
CPU time 136.92 seconds
Started Dec 24 12:30:32 PM PST 23
Finished Dec 24 12:33:16 PM PST 23
Peak memory 211272 kb
Host smart-478b9f7b-a3e5-4ff3-9890-fd4833be77e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334345912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.334345912
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.991102972
Short name T124
Test name
Test status
Simulation time 2023036960 ps
CPU time 19.22 seconds
Started Dec 24 12:30:33 PM PST 23
Finished Dec 24 12:31:18 PM PST 23
Peak memory 219280 kb
Host smart-0ab9e2e7-3dfe-43da-8b7b-ca9a851145a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991102972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.991102972
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1226664632
Short name T14
Test name
Test status
Simulation time 842497852 ps
CPU time 15.35 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 212376 kb
Host smart-b995b6c4-a378-4ca8-bc62-68873ce7fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226664632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1226664632
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.949293484
Short name T35
Test name
Test status
Simulation time 7010629958 ps
CPU time 119.18 seconds
Started Dec 24 12:46:26 PM PST 23
Finished Dec 24 12:48:27 PM PST 23
Peak memory 236336 kb
Host smart-e7c0e4ff-dfe7-4188-be5e-f005904f3ada
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949293484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.949293484
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2162761773
Short name T99
Test name
Test status
Simulation time 35397304790 ps
CPU time 337.85 seconds
Started Dec 24 12:30:05 PM PST 23
Finished Dec 24 12:36:08 PM PST 23
Peak memory 211124 kb
Host smart-5be9be7e-f9e7-4ca2-b1f8-a39ec2ecb0d5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162761773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2162761773
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2102100039
Short name T57
Test name
Test status
Simulation time 617912591 ps
CPU time 39.21 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:31:22 PM PST 23
Peak memory 212300 kb
Host smart-acf425e8-f168-4a71-b143-f2fefac695ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102100039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2102100039
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.1043111909
Short name T72
Test name
Test status
Simulation time 37467383623 ps
CPU time 301.37 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:35:52 PM PST 23
Peak memory 211160 kb
Host smart-6fc3dfe3-8870-4554-b736-59ca0d2f9a1e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043111909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.1043111909
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.727792925
Short name T122
Test name
Test status
Simulation time 44114331993 ps
CPU time 1639.36 seconds
Started Dec 24 12:47:37 PM PST 23
Finished Dec 24 01:14:59 PM PST 23
Peak memory 233912 kb
Host smart-973e787e-a052-4d12-9597-99420f7c5d5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727792925 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.727792925
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.546559853
Short name T111
Test name
Test status
Simulation time 10017634900 ps
CPU time 47.07 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:31:41 PM PST 23
Peak memory 212284 kb
Host smart-0aa5c423-9e2f-4ccd-a699-bdaa4375c3f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546559853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.546559853
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1333543743
Short name T23
Test name
Test status
Simulation time 7818146999 ps
CPU time 33.67 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 211764 kb
Host smart-9f3777a2-ccc5-46b3-a129-c82929705ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333543743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1333543743
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.231858880
Short name T306
Test name
Test status
Simulation time 173486624 ps
CPU time 10.02 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:00 PM PST 23
Peak memory 210992 kb
Host smart-7d829724-c42d-42a3-8fe5-3db96df8e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231858880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.231858880
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.772889698
Short name T184
Test name
Test status
Simulation time 6627841188 ps
CPU time 14.07 seconds
Started Dec 24 12:46:23 PM PST 23
Finished Dec 24 12:46:41 PM PST 23
Peak memory 210964 kb
Host smart-26248729-d986-45f0-8caf-0473d8112a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772889698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.772889698
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.613842051
Short name T114
Test name
Test status
Simulation time 5447499694 ps
CPU time 77.46 seconds
Started Dec 24 12:30:38 PM PST 23
Finished Dec 24 12:32:22 PM PST 23
Peak memory 211636 kb
Host smart-c9aa59a6-6b73-40c1-a26b-cdc0dc5e037e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613842051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.613842051
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2103691069
Short name T11
Test name
Test status
Simulation time 352311249639 ps
CPU time 3436.77 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 01:44:11 PM PST 23
Peak memory 256064 kb
Host smart-26029e7a-3bf8-496c-895b-98157e339ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103691069 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2103691069
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.4119528265
Short name T110
Test name
Test status
Simulation time 46287879191 ps
CPU time 1763.15 seconds
Started Dec 24 12:46:18 PM PST 23
Finished Dec 24 01:15:48 PM PST 23
Peak memory 236516 kb
Host smart-95095eea-508a-425b-9f6f-303865c7dff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119528265 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.4119528265
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3787395555
Short name T84
Test name
Test status
Simulation time 1207788083 ps
CPU time 6.3 seconds
Started Dec 24 12:30:03 PM PST 23
Finished Dec 24 12:30:35 PM PST 23
Peak memory 211144 kb
Host smart-1bb2f661-b40c-4736-b938-9ed0de0f0c2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787395555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3787395555
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3485103946
Short name T484
Test name
Test status
Simulation time 5124781115 ps
CPU time 11.9 seconds
Started Dec 24 12:29:52 PM PST 23
Finished Dec 24 12:30:29 PM PST 23
Peak memory 211288 kb
Host smart-965e9e81-b226-4167-bd85-0bf078285777
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485103946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.3485103946
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.764192189
Short name T91
Test name
Test status
Simulation time 682873078 ps
CPU time 11.76 seconds
Started Dec 24 12:30:39 PM PST 23
Finished Dec 24 12:31:18 PM PST 23
Peak memory 211184 kb
Host smart-581b5385-6667-48f8-84b9-6ac0faebe283
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764192189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.764192189
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1637287491
Short name T67
Test name
Test status
Simulation time 2163825077 ps
CPU time 17.02 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:57 PM PST 23
Peak memory 215700 kb
Host smart-72d3b9af-75a0-4b6e-9f4e-b34eaad140fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637287491 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1637287491
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.890006865
Short name T98
Test name
Test status
Simulation time 347764478 ps
CPU time 4.3 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 211220 kb
Host smart-ad391463-901a-49f7-9bf2-0c04d13ae811
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890006865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.890006865
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3612553341
Short name T128
Test name
Test status
Simulation time 665481872 ps
CPU time 8.21 seconds
Started Dec 24 12:30:30 PM PST 23
Finished Dec 24 12:31:05 PM PST 23
Peak memory 211080 kb
Host smart-c9eddf3e-00dd-4209-b70f-6ab3de3b558a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612553341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3612553341
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2484750102
Short name T150
Test name
Test status
Simulation time 346453281 ps
CPU time 4.25 seconds
Started Dec 24 12:31:07 PM PST 23
Finished Dec 24 12:31:30 PM PST 23
Peak memory 211068 kb
Host smart-6503e557-ef2a-452c-875d-6ed8c5b5e806
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484750102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2484750102
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1696942135
Short name T144
Test name
Test status
Simulation time 89022250 ps
CPU time 4.36 seconds
Started Dec 24 12:30:12 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 211124 kb
Host smart-3571d274-36e8-47e6-8b27-9f78ffb3b110
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696942135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1696942135
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3517841401
Short name T474
Test name
Test status
Simulation time 378178830 ps
CPU time 12.05 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:30:55 PM PST 23
Peak memory 219516 kb
Host smart-4be84539-813e-4080-95d8-3cc60d87c8ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517841401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3517841401
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.141643302
Short name T112
Test name
Test status
Simulation time 157701441 ps
CPU time 39.6 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:31:20 PM PST 23
Peak memory 212128 kb
Host smart-92e46372-6be4-4ea2-a2b8-57855ec2c7a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141643302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.141643302
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2019880108
Short name T131
Test name
Test status
Simulation time 293760477 ps
CPU time 6.16 seconds
Started Dec 24 12:31:05 PM PST 23
Finished Dec 24 12:31:30 PM PST 23
Peak memory 211116 kb
Host smart-8bdfd785-0d6c-4ada-81f1-8923cc604d1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019880108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.2019880108
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.101613655
Short name T133
Test name
Test status
Simulation time 89147159 ps
CPU time 4.5 seconds
Started Dec 24 12:30:46 PM PST 23
Finished Dec 24 12:31:16 PM PST 23
Peak memory 211088 kb
Host smart-404deef5-ba6b-4cee-abe6-b044af264d69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101613655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_b
ash.101613655
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.312832851
Short name T97
Test name
Test status
Simulation time 872887774 ps
CPU time 11.22 seconds
Started Dec 24 12:30:11 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 211476 kb
Host smart-ea400e25-9f6e-47ea-80c9-21a86abcf93b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312832851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.312832851
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.4097085563
Short name T61
Test name
Test status
Simulation time 2026039051 ps
CPU time 12.27 seconds
Started Dec 24 12:30:39 PM PST 23
Finished Dec 24 12:31:17 PM PST 23
Peak memory 214928 kb
Host smart-f259ac88-ccfc-4d49-8a8c-221681ce844c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097085563 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.4097085563
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.43468203
Short name T460
Test name
Test status
Simulation time 426509895 ps
CPU time 5.89 seconds
Started Dec 24 12:31:19 PM PST 23
Finished Dec 24 12:31:50 PM PST 23
Peak memory 211132 kb
Host smart-1663ce04-893a-4321-a409-984a47b6f3a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43468203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.43468203
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3198618897
Short name T130
Test name
Test status
Simulation time 333596354 ps
CPU time 4.23 seconds
Started Dec 24 12:31:20 PM PST 23
Finished Dec 24 12:31:50 PM PST 23
Peak memory 211192 kb
Host smart-d5fb3d8e-1335-41a8-9d16-73751170719e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198618897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3198618897
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2153066690
Short name T475
Test name
Test status
Simulation time 3118220155 ps
CPU time 12.87 seconds
Started Dec 24 12:31:11 PM PST 23
Finished Dec 24 12:31:44 PM PST 23
Peak memory 211208 kb
Host smart-42008e16-7b83-498f-b402-8bc1022310cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153066690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2153066690
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2006254241
Short name T74
Test name
Test status
Simulation time 71457715993 ps
CPU time 151.56 seconds
Started Dec 24 12:30:08 PM PST 23
Finished Dec 24 12:33:05 PM PST 23
Peak memory 211188 kb
Host smart-df0f6140-14fe-40bb-b8bd-190868b8fdbf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006254241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.2006254241
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.18169531
Short name T104
Test name
Test status
Simulation time 6118877608 ps
CPU time 14.99 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:04 PM PST 23
Peak memory 211420 kb
Host smart-6edec85e-8dfc-42f9-bc74-5b6906410eb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_same_csr_outstanding.18169531
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3012738765
Short name T108
Test name
Test status
Simulation time 23692972334 ps
CPU time 14.76 seconds
Started Dec 24 12:31:03 PM PST 23
Finished Dec 24 12:31:38 PM PST 23
Peak memory 219420 kb
Host smart-0e7c2959-063e-4ceb-8e2f-d46ad1abcb6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012738765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3012738765
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.299845472
Short name T116
Test name
Test status
Simulation time 514536688 ps
CPU time 39.36 seconds
Started Dec 24 12:30:27 PM PST 23
Finished Dec 24 12:31:31 PM PST 23
Peak memory 212308 kb
Host smart-69a9af97-e584-4335-88fd-47ee360421ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299845472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_int
g_err.299845472
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2678594348
Short name T138
Test name
Test status
Simulation time 1325762676 ps
CPU time 11.98 seconds
Started Dec 24 12:30:30 PM PST 23
Finished Dec 24 12:31:08 PM PST 23
Peak memory 212304 kb
Host smart-8efb87ff-b805-4fa7-8434-f78e315d5ce1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678594348 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2678594348
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2974968269
Short name T477
Test name
Test status
Simulation time 1003529646 ps
CPU time 10.11 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:55 PM PST 23
Peak memory 211060 kb
Host smart-e4514db8-e036-4cda-a027-7202f5d9d18c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974968269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2974968269
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.804992048
Short name T76
Test name
Test status
Simulation time 15388576125 ps
CPU time 174.22 seconds
Started Dec 24 12:30:32 PM PST 23
Finished Dec 24 12:33:53 PM PST 23
Peak memory 211136 kb
Host smart-1fbddd6c-a730-4bf5-a016-6f423c4cb65c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804992048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.804992048
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.141126031
Short name T141
Test name
Test status
Simulation time 3395223066 ps
CPU time 14.74 seconds
Started Dec 24 12:30:23 PM PST 23
Finished Dec 24 12:31:00 PM PST 23
Peak memory 211260 kb
Host smart-69883faa-f10c-46f6-98f9-1e29f3f4ff05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141126031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.141126031
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.4275220467
Short name T449
Test name
Test status
Simulation time 4919280064 ps
CPU time 13.92 seconds
Started Dec 24 12:30:16 PM PST 23
Finished Dec 24 12:30:52 PM PST 23
Peak memory 219492 kb
Host smart-1a9b16f9-ea34-4636-97d2-48575d5e9a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275220467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.4275220467
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3455720734
Short name T118
Test name
Test status
Simulation time 17961015399 ps
CPU time 83.66 seconds
Started Dec 24 12:30:27 PM PST 23
Finished Dec 24 12:32:15 PM PST 23
Peak memory 211456 kb
Host smart-d8119b2c-8c4a-4072-83a5-b7bd82b2d84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455720734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3455720734
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.90854054
Short name T459
Test name
Test status
Simulation time 99112673 ps
CPU time 5.08 seconds
Started Dec 24 12:30:41 PM PST 23
Finished Dec 24 12:31:13 PM PST 23
Peak memory 214196 kb
Host smart-8d0e1126-a7aa-4bc4-9c57-b2ea803d30fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90854054 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.90854054
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2354858698
Short name T68
Test name
Test status
Simulation time 3832163395 ps
CPU time 12.31 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 211120 kb
Host smart-ce35ac8b-684b-401c-93ae-2db60a3adc0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354858698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2354858698
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1940424014
Short name T458
Test name
Test status
Simulation time 20789277935 ps
CPU time 170.13 seconds
Started Dec 24 12:31:15 PM PST 23
Finished Dec 24 12:34:28 PM PST 23
Peak memory 211168 kb
Host smart-650acd56-351d-4c8a-842f-721325131eb5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940424014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.1940424014
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.337209866
Short name T139
Test name
Test status
Simulation time 5749647514 ps
CPU time 12.39 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:31:03 PM PST 23
Peak memory 211240 kb
Host smart-2c17c2ec-4321-421d-862a-dedf47dbf6ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337209866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.337209866
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.4101040984
Short name T465
Test name
Test status
Simulation time 624909558 ps
CPU time 8.95 seconds
Started Dec 24 12:31:09 PM PST 23
Finished Dec 24 12:31:37 PM PST 23
Peak memory 214816 kb
Host smart-e83f370c-19be-4eff-ab67-a680977ef58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101040984 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.4101040984
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2057197609
Short name T473
Test name
Test status
Simulation time 87318481 ps
CPU time 4.38 seconds
Started Dec 24 12:30:52 PM PST 23
Finished Dec 24 12:31:19 PM PST 23
Peak memory 211200 kb
Host smart-270c51f5-33ef-4911-8bf5-824ed591720c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057197609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2057197609
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1691962639
Short name T103
Test name
Test status
Simulation time 6505541005 ps
CPU time 89.6 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:32:17 PM PST 23
Peak memory 211252 kb
Host smart-0d674c52-7c96-4625-874b-f79991c92242
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691962639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1691962639
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.1492843196
Short name T105
Test name
Test status
Simulation time 2362295564 ps
CPU time 17 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:31:04 PM PST 23
Peak memory 211256 kb
Host smart-3c40440b-a4db-42f5-84a9-7e313ab6abca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492843196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.1492843196
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.1251706902
Short name T439
Test name
Test status
Simulation time 2054548792 ps
CPU time 11.37 seconds
Started Dec 24 12:30:49 PM PST 23
Finished Dec 24 12:31:24 PM PST 23
Peak memory 219304 kb
Host smart-ec5d7fa0-89c0-49e2-aa42-ead718a7e3e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251706902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.1251706902
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.718192296
Short name T117
Test name
Test status
Simulation time 3076665266 ps
CPU time 49.93 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:31:38 PM PST 23
Peak memory 212448 kb
Host smart-22307c91-963c-410a-a0a4-7e05191f73f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718192296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.718192296
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1745274560
Short name T64
Test name
Test status
Simulation time 327513177 ps
CPU time 4.45 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:52 PM PST 23
Peak memory 213404 kb
Host smart-939cce14-fef7-45c7-8f57-fe994323d1a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745274560 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1745274560
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1357948887
Short name T467
Test name
Test status
Simulation time 58088883015 ps
CPU time 138.17 seconds
Started Dec 24 12:30:47 PM PST 23
Finished Dec 24 12:33:34 PM PST 23
Peak memory 211236 kb
Host smart-8a1cf9c7-3665-466b-89dd-dd0b13bf5a31
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357948887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1357948887
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3844090819
Short name T485
Test name
Test status
Simulation time 8593189064 ps
CPU time 15.98 seconds
Started Dec 24 12:30:46 PM PST 23
Finished Dec 24 12:31:27 PM PST 23
Peak memory 211240 kb
Host smart-f25211af-e78e-476e-99b4-88b5d10262c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844090819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3844090819
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1231537657
Short name T145
Test name
Test status
Simulation time 1932064919 ps
CPU time 17.15 seconds
Started Dec 24 12:30:31 PM PST 23
Finished Dec 24 12:31:14 PM PST 23
Peak memory 219356 kb
Host smart-fecd54f9-ccd4-4f68-97da-7be0c808556e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231537657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1231537657
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.44439782
Short name T148
Test name
Test status
Simulation time 7575851397 ps
CPU time 48.75 seconds
Started Dec 24 12:30:29 PM PST 23
Finished Dec 24 12:31:43 PM PST 23
Peak memory 212668 kb
Host smart-e087a1f4-1b46-4544-9722-82b5ab2068dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44439782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_int
g_err.44439782
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.572671518
Short name T445
Test name
Test status
Simulation time 7796129214 ps
CPU time 13.86 seconds
Started Dec 24 12:31:06 PM PST 23
Finished Dec 24 12:31:38 PM PST 23
Peak memory 214856 kb
Host smart-6ea78533-d5e9-4b8f-9361-db999cbde531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572671518 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.572671518
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2018808863
Short name T464
Test name
Test status
Simulation time 6785059906 ps
CPU time 16.16 seconds
Started Dec 24 12:30:19 PM PST 23
Finished Dec 24 12:31:03 PM PST 23
Peak memory 211288 kb
Host smart-f5710567-2752-41dc-a9b1-a95dfab862c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018808863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2018808863
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2753640897
Short name T102
Test name
Test status
Simulation time 10928595974 ps
CPU time 90.3 seconds
Started Dec 24 12:30:31 PM PST 23
Finished Dec 24 12:32:27 PM PST 23
Peak memory 219364 kb
Host smart-d6725891-2d46-4dcb-934c-cd377e4f7000
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753640897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2753640897
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.2974972945
Short name T33
Test name
Test status
Simulation time 4261372776 ps
CPU time 10.43 seconds
Started Dec 24 12:30:36 PM PST 23
Finished Dec 24 12:31:13 PM PST 23
Peak memory 211268 kb
Host smart-cd5428c5-5944-449b-ac65-f7d349983529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974972945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.2974972945
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2573565583
Short name T444
Test name
Test status
Simulation time 1038294344 ps
CPU time 6.35 seconds
Started Dec 24 12:31:04 PM PST 23
Finished Dec 24 12:31:30 PM PST 23
Peak memory 219316 kb
Host smart-2e60b5d5-fc68-4e1f-ac83-96ae2db99bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573565583 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2573565583
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1770055882
Short name T115
Test name
Test status
Simulation time 1666848746 ps
CPU time 82.59 seconds
Started Dec 24 12:30:52 PM PST 23
Finished Dec 24 12:32:38 PM PST 23
Peak memory 212156 kb
Host smart-279431bf-c07a-4f81-a131-4dad0016e286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770055882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1770055882
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3553565279
Short name T56
Test name
Test status
Simulation time 8411981958 ps
CPU time 17.85 seconds
Started Dec 24 12:30:34 PM PST 23
Finished Dec 24 12:31:18 PM PST 23
Peak memory 219464 kb
Host smart-36ed0d4c-ecf0-4a0e-a42a-6b1b8211dc6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553565279 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3553565279
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3079571480
Short name T132
Test name
Test status
Simulation time 1378228181 ps
CPU time 11.99 seconds
Started Dec 24 12:30:26 PM PST 23
Finished Dec 24 12:31:03 PM PST 23
Peak memory 211088 kb
Host smart-af1b989e-eb01-4d3f-8cc0-50a07739704e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079571480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3079571480
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3197505116
Short name T96
Test name
Test status
Simulation time 39721311663 ps
CPU time 184.67 seconds
Started Dec 24 12:31:11 PM PST 23
Finished Dec 24 12:34:36 PM PST 23
Peak memory 211244 kb
Host smart-1871457f-27d7-49a6-b333-d85893c34960
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197505116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3197505116
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2870745382
Short name T454
Test name
Test status
Simulation time 6480829342 ps
CPU time 14.12 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:31:01 PM PST 23
Peak memory 211120 kb
Host smart-80930854-66fe-4b20-a2a5-e05b7357b16a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870745382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2870745382
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3153911081
Short name T461
Test name
Test status
Simulation time 556810061 ps
CPU time 10.11 seconds
Started Dec 24 12:30:31 PM PST 23
Finished Dec 24 12:31:07 PM PST 23
Peak memory 219404 kb
Host smart-27d627e3-eb17-4328-8d2c-68766b874079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153911081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.3153911081
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1841946256
Short name T123
Test name
Test status
Simulation time 1665779476 ps
CPU time 9.88 seconds
Started Dec 24 12:30:54 PM PST 23
Finished Dec 24 12:31:27 PM PST 23
Peak memory 215616 kb
Host smart-6348753f-69f2-45df-80bb-1800defe83b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841946256 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1841946256
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2932588360
Short name T94
Test name
Test status
Simulation time 2895653092 ps
CPU time 10.26 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:31:04 PM PST 23
Peak memory 211160 kb
Host smart-1b0fdfbc-77e6-4836-a165-dad13ea09511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932588360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2932588360
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2440809122
Short name T151
Test name
Test status
Simulation time 2162669258 ps
CPU time 16.4 seconds
Started Dec 24 12:30:46 PM PST 23
Finished Dec 24 12:31:27 PM PST 23
Peak memory 211252 kb
Host smart-57538ef1-75c2-4176-b922-98e0b3cabdc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440809122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2440809122
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.429170099
Short name T65
Test name
Test status
Simulation time 2405765747 ps
CPU time 13.19 seconds
Started Dec 24 12:30:47 PM PST 23
Finished Dec 24 12:31:25 PM PST 23
Peak memory 219472 kb
Host smart-5303c52a-ae33-4d28-afc0-63f8720cc615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429170099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.429170099
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.391297242
Short name T121
Test name
Test status
Simulation time 7213720440 ps
CPU time 48.6 seconds
Started Dec 24 12:30:31 PM PST 23
Finished Dec 24 12:31:46 PM PST 23
Peak memory 212684 kb
Host smart-ff19cf8d-db3a-442b-b212-0c72aa823415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391297242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.391297242
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1113861235
Short name T440
Test name
Test status
Simulation time 5834796732 ps
CPU time 12.02 seconds
Started Dec 24 12:30:36 PM PST 23
Finished Dec 24 12:31:14 PM PST 23
Peak memory 213556 kb
Host smart-1f3fb901-094e-4dbb-bb4e-4d8efb468a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113861235 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1113861235
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3065314761
Short name T450
Test name
Test status
Simulation time 658497997 ps
CPU time 5.04 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:50 PM PST 23
Peak memory 211088 kb
Host smart-e3b429e0-5af0-4bec-a5b9-6381916b4aa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065314761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3065314761
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.325474198
Short name T41
Test name
Test status
Simulation time 22180912447 ps
CPU time 116.33 seconds
Started Dec 24 12:30:47 PM PST 23
Finished Dec 24 12:33:08 PM PST 23
Peak memory 211188 kb
Host smart-4337a520-4bc8-4bc2-8f1a-f2781d9340f6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325474198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.325474198
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1964394591
Short name T83
Test name
Test status
Simulation time 2578226775 ps
CPU time 11.84 seconds
Started Dec 24 12:30:41 PM PST 23
Finished Dec 24 12:31:20 PM PST 23
Peak memory 211192 kb
Host smart-dc7e03ea-d4c1-4505-b20b-2fe095ea1639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964394591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1964394591
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2030221996
Short name T146
Test name
Test status
Simulation time 916301374 ps
CPU time 12.42 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:53 PM PST 23
Peak memory 219384 kb
Host smart-9701e213-6a89-40d8-848e-b961c25e6899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030221996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2030221996
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.539491557
Short name T120
Test name
Test status
Simulation time 5624605189 ps
CPU time 81.08 seconds
Started Dec 24 12:31:06 PM PST 23
Finished Dec 24 12:32:46 PM PST 23
Peak memory 212876 kb
Host smart-e8e006a9-6a3a-486d-b606-53a246bc8b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539491557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.539491557
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2697509995
Short name T66
Test name
Test status
Simulation time 96746047 ps
CPU time 4.9 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:30:48 PM PST 23
Peak memory 213948 kb
Host smart-a3489056-016f-414d-8aaa-88a8c797b741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697509995 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2697509995
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.696180307
Short name T81
Test name
Test status
Simulation time 518949178 ps
CPU time 4.32 seconds
Started Dec 24 12:30:27 PM PST 23
Finished Dec 24 12:31:02 PM PST 23
Peak memory 211188 kb
Host smart-05b38159-05b7-44c6-a69c-c3fbe0cce7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696180307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.696180307
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3080139545
Short name T137
Test name
Test status
Simulation time 353146842 ps
CPU time 6.05 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 211200 kb
Host smart-ebdf9ecf-eba5-4383-8ee1-c606f19c17b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080139545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3080139545
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.874382481
Short name T109
Test name
Test status
Simulation time 2663567289 ps
CPU time 15.88 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:13 PM PST 23
Peak memory 219460 kb
Host smart-32416fad-6a59-4719-b202-8d25824b2780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874382481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.874382481
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2141195453
Short name T78
Test name
Test status
Simulation time 1355075353 ps
CPU time 46.03 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:31:26 PM PST 23
Peak memory 212004 kb
Host smart-85ee6d21-a2cf-40b3-aded-cbf2e20dd6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141195453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2141195453
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.393360415
Short name T127
Test name
Test status
Simulation time 1423427401 ps
CPU time 12.62 seconds
Started Dec 24 12:30:35 PM PST 23
Finished Dec 24 12:31:14 PM PST 23
Peak memory 215828 kb
Host smart-f49f1b53-e73b-4d88-a616-71e6eb9d4f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393360415 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.393360415
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.4032525483
Short name T481
Test name
Test status
Simulation time 378239294 ps
CPU time 4.7 seconds
Started Dec 24 12:30:19 PM PST 23
Finished Dec 24 12:30:46 PM PST 23
Peak memory 211212 kb
Host smart-fdcbc333-24c9-4e81-ab10-ecf25fff804a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032525483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.4032525483
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2216127240
Short name T455
Test name
Test status
Simulation time 27158207526 ps
CPU time 179.69 seconds
Started Dec 24 12:31:20 PM PST 23
Finished Dec 24 12:34:44 PM PST 23
Peak memory 211184 kb
Host smart-2939b14e-dbd3-4a83-835a-361df51d7a86
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216127240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2216127240
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3696102248
Short name T441
Test name
Test status
Simulation time 722528059 ps
CPU time 8.69 seconds
Started Dec 24 12:30:45 PM PST 23
Finished Dec 24 12:31:19 PM PST 23
Peak memory 211140 kb
Host smart-d2d98dbf-b176-414b-b80e-ff35a67be5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696102248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3696102248
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2585215488
Short name T468
Test name
Test status
Simulation time 3067950053 ps
CPU time 16.35 seconds
Started Dec 24 12:30:23 PM PST 23
Finished Dec 24 12:31:02 PM PST 23
Peak memory 219404 kb
Host smart-86c32e2f-5302-4c22-be82-f2acb5919a43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585215488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2585215488
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1473898545
Short name T469
Test name
Test status
Simulation time 299979760 ps
CPU time 39.23 seconds
Started Dec 24 12:30:37 PM PST 23
Finished Dec 24 12:31:42 PM PST 23
Peak memory 212344 kb
Host smart-311c9689-f8ee-40eb-b130-ae0efdfa7a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473898545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1473898545
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.280863265
Short name T462
Test name
Test status
Simulation time 1870548146 ps
CPU time 9.81 seconds
Started Dec 24 12:31:03 PM PST 23
Finished Dec 24 12:31:32 PM PST 23
Peak memory 211100 kb
Host smart-1de9ef4b-4e98-4c75-9970-fab40e5634aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280863265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.280863265
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.327251928
Short name T443
Test name
Test status
Simulation time 1505113548 ps
CPU time 10.05 seconds
Started Dec 24 12:30:16 PM PST 23
Finished Dec 24 12:30:48 PM PST 23
Peak memory 211140 kb
Host smart-ec756d2d-fa8e-4bad-9787-15ea8bea5e48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327251928 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.327251928
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1821715883
Short name T82
Test name
Test status
Simulation time 1744780606 ps
CPU time 15.81 seconds
Started Dec 24 12:31:22 PM PST 23
Finished Dec 24 12:32:03 PM PST 23
Peak memory 211172 kb
Host smart-3bd6a986-9557-48e8-bb71-d3dd9a74889c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821715883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1821715883
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.868628994
Short name T28
Test name
Test status
Simulation time 865582087 ps
CPU time 4.59 seconds
Started Dec 24 12:29:54 PM PST 23
Finished Dec 24 12:30:24 PM PST 23
Peak memory 212280 kb
Host smart-2c24e5a8-fecd-46c8-a68c-67c38be8e25e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868628994 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.868628994
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.111233300
Short name T466
Test name
Test status
Simulation time 7000813941 ps
CPU time 14.54 seconds
Started Dec 24 12:30:07 PM PST 23
Finished Dec 24 12:30:46 PM PST 23
Peak memory 211280 kb
Host smart-9b277e25-3070-4018-b65f-2ea3c22b220b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111233300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.111233300
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.487145290
Short name T143
Test name
Test status
Simulation time 1550288515 ps
CPU time 12.98 seconds
Started Dec 24 12:30:17 PM PST 23
Finished Dec 24 12:30:53 PM PST 23
Peak memory 211120 kb
Host smart-08b13138-3602-43da-99c3-13f0b65a2eb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487145290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.487145290
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.1288037694
Short name T446
Test name
Test status
Simulation time 14399075526 ps
CPU time 11.47 seconds
Started Dec 24 12:30:54 PM PST 23
Finished Dec 24 12:31:28 PM PST 23
Peak memory 211160 kb
Host smart-1abb12f2-569b-42a5-a28a-6896334f375a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288037694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.1288037694
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3405708342
Short name T73
Test name
Test status
Simulation time 8546533286 ps
CPU time 117.14 seconds
Started Dec 24 12:31:00 PM PST 23
Finished Dec 24 12:33:17 PM PST 23
Peak memory 211256 kb
Host smart-8f4b13e9-696b-4d47-ac06-83d26d707077
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405708342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3405708342
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3478264816
Short name T451
Test name
Test status
Simulation time 6318249048 ps
CPU time 13.83 seconds
Started Dec 24 12:30:19 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 211180 kb
Host smart-05cf5a5b-7a02-4816-a329-96746ee8117f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478264816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3478264816
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.606614188
Short name T62
Test name
Test status
Simulation time 12640325317 ps
CPU time 17.65 seconds
Started Dec 24 12:31:02 PM PST 23
Finished Dec 24 12:31:39 PM PST 23
Peak memory 219432 kb
Host smart-46f31bbe-dd36-4b71-93e1-c10a175b08e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606614188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.606614188
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1426954761
Short name T60
Test name
Test status
Simulation time 1237707308 ps
CPU time 40.81 seconds
Started Dec 24 12:30:17 PM PST 23
Finished Dec 24 12:31:20 PM PST 23
Peak memory 212476 kb
Host smart-c5756a4e-949a-42a4-9542-ff42766f7ddf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426954761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1426954761
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4129013444
Short name T69
Test name
Test status
Simulation time 2147597971 ps
CPU time 16.04 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:31:10 PM PST 23
Peak memory 211220 kb
Host smart-2e1d12f5-0128-464c-9bb7-4dcbd3bd9fd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129013444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.4129013444
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3077713609
Short name T482
Test name
Test status
Simulation time 377824753 ps
CPU time 4.55 seconds
Started Dec 24 12:30:06 PM PST 23
Finished Dec 24 12:30:35 PM PST 23
Peak memory 211212 kb
Host smart-ec7e318e-7c57-443b-bb92-2956ac6be3ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077713609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3077713609
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1429923520
Short name T149
Test name
Test status
Simulation time 2940198310 ps
CPU time 14.55 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:03 PM PST 23
Peak memory 211176 kb
Host smart-120ac20f-031c-4ddd-8378-5e4d08fa6bd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429923520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1429923520
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1265987707
Short name T134
Test name
Test status
Simulation time 3156232832 ps
CPU time 15.32 seconds
Started Dec 24 12:30:15 PM PST 23
Finished Dec 24 12:30:53 PM PST 23
Peak memory 212112 kb
Host smart-3f243285-f8a3-4377-9de8-79d22eb1370c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265987707 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1265987707
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2969710923
Short name T100
Test name
Test status
Simulation time 378726210 ps
CPU time 6.34 seconds
Started Dec 24 12:30:15 PM PST 23
Finished Dec 24 12:30:44 PM PST 23
Peak memory 211096 kb
Host smart-d0c29531-5668-4dcf-b166-cf70077af380
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969710923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2969710923
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2976414059
Short name T136
Test name
Test status
Simulation time 3482427505 ps
CPU time 11.08 seconds
Started Dec 24 12:30:58 PM PST 23
Finished Dec 24 12:31:30 PM PST 23
Peak memory 211140 kb
Host smart-d6c9fc0a-fba6-40ef-bf0d-29940c8ee4a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976414059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2976414059
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3877832444
Short name T456
Test name
Test status
Simulation time 1537811958 ps
CPU time 6.81 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 211096 kb
Host smart-5e0ff099-820b-4cf8-a71f-dfe6422f0d53
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877832444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3877832444
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2764120809
Short name T470
Test name
Test status
Simulation time 1469202884 ps
CPU time 10.64 seconds
Started Dec 24 12:30:53 PM PST 23
Finished Dec 24 12:31:27 PM PST 23
Peak memory 211180 kb
Host smart-8efa3c5f-0878-4a1f-b422-44f077f7743b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764120809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.2764120809
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.900420924
Short name T126
Test name
Test status
Simulation time 3767505998 ps
CPU time 12.41 seconds
Started Dec 24 12:30:08 PM PST 23
Finished Dec 24 12:30:45 PM PST 23
Peak memory 219464 kb
Host smart-53925628-dfd9-40df-a3bc-914714a09c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900420924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.900420924
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3252167069
Short name T119
Test name
Test status
Simulation time 1746731006 ps
CPU time 80.95 seconds
Started Dec 24 12:30:14 PM PST 23
Finished Dec 24 12:31:59 PM PST 23
Peak memory 213608 kb
Host smart-6c32f5e5-c272-4601-9de1-ce99a58b029a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252167069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3252167069
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2338904481
Short name T70
Test name
Test status
Simulation time 1603155968 ps
CPU time 13.33 seconds
Started Dec 24 12:30:41 PM PST 23
Finished Dec 24 12:31:21 PM PST 23
Peak memory 211128 kb
Host smart-43575318-74fb-425e-b613-cbcacbc48629
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338904481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2338904481
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.913436841
Short name T483
Test name
Test status
Simulation time 1314021396 ps
CPU time 12.09 seconds
Started Dec 24 12:30:17 PM PST 23
Finished Dec 24 12:30:51 PM PST 23
Peak memory 211124 kb
Host smart-07294114-6757-473c-ad1f-2393d224faa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913436841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.913436841
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3863286501
Short name T452
Test name
Test status
Simulation time 5131532986 ps
CPU time 14.94 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:31:09 PM PST 23
Peak memory 211160 kb
Host smart-72ba608a-1e54-4c9d-8924-ed027a9bad13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863286501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3863286501
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2422520010
Short name T479
Test name
Test status
Simulation time 2777048062 ps
CPU time 8.69 seconds
Started Dec 24 12:30:06 PM PST 23
Finished Dec 24 12:30:40 PM PST 23
Peak memory 214124 kb
Host smart-b86c2675-111e-4b3b-91c6-b524fba115c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422520010 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2422520010
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1274216212
Short name T92
Test name
Test status
Simulation time 216735054 ps
CPU time 5.51 seconds
Started Dec 24 12:31:07 PM PST 23
Finished Dec 24 12:31:31 PM PST 23
Peak memory 211172 kb
Host smart-350e3800-64bc-414f-8ac7-f9f0ed21341a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274216212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1274216212
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2002345109
Short name T80
Test name
Test status
Simulation time 1419974252 ps
CPU time 11.82 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:30:52 PM PST 23
Peak memory 211156 kb
Host smart-b39384cc-5325-4ba7-9734-db79861e1cc4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002345109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2002345109
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3097677805
Short name T448
Test name
Test status
Simulation time 1627709105 ps
CPU time 7.31 seconds
Started Dec 24 12:30:19 PM PST 23
Finished Dec 24 12:30:48 PM PST 23
Peak memory 211164 kb
Host smart-b5e6c7c9-8820-45fc-b868-b8d7e544e658
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097677805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3097677805
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.4031814079
Short name T478
Test name
Test status
Simulation time 4454765431 ps
CPU time 129.64 seconds
Started Dec 24 12:30:33 PM PST 23
Finished Dec 24 12:33:09 PM PST 23
Peak memory 211244 kb
Host smart-0715c16e-0409-4081-99b5-2edbb3b2cec2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031814079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.4031814079
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.101841018
Short name T129
Test name
Test status
Simulation time 1365888710 ps
CPU time 13.04 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:02 PM PST 23
Peak memory 211176 kb
Host smart-ca3eac0d-e684-4263-a9c2-abc913603911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101841018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.101841018
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2882339186
Short name T79
Test name
Test status
Simulation time 9224026679 ps
CPU time 44.46 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:31:29 PM PST 23
Peak memory 212500 kb
Host smart-13cbfe05-b115-4a7c-afdc-ca3b71b5fc0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882339186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2882339186
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1451593172
Short name T26
Test name
Test status
Simulation time 1195047709 ps
CPU time 7.94 seconds
Started Dec 24 12:31:05 PM PST 23
Finished Dec 24 12:31:32 PM PST 23
Peak memory 213148 kb
Host smart-ad3596b4-6b8e-4f43-b13f-2ecfdfeb77cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451593172 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1451593172
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.712288844
Short name T457
Test name
Test status
Simulation time 5326115620 ps
CPU time 14.93 seconds
Started Dec 24 12:30:16 PM PST 23
Finished Dec 24 12:30:53 PM PST 23
Peak memory 211280 kb
Host smart-ac97166c-0737-46e9-9b83-8287ee04587b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712288844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.712288844
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1487784008
Short name T95
Test name
Test status
Simulation time 8757962826 ps
CPU time 150.53 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:33:14 PM PST 23
Peak memory 211184 kb
Host smart-913bbabb-c91a-471e-892d-788e90e4de78
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487784008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1487784008
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.79975531
Short name T147
Test name
Test status
Simulation time 6786149101 ps
CPU time 14.32 seconds
Started Dec 24 12:30:15 PM PST 23
Finished Dec 24 12:30:51 PM PST 23
Peak memory 211192 kb
Host smart-c423d8ea-24ba-4b16-b657-29941fbec8f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79975531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctr
l_same_csr_outstanding.79975531
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2482804501
Short name T442
Test name
Test status
Simulation time 346816603 ps
CPU time 5.86 seconds
Started Dec 24 12:30:07 PM PST 23
Finished Dec 24 12:30:38 PM PST 23
Peak memory 219408 kb
Host smart-23b3d80b-643d-49da-8e4f-7b8d69d74c76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482804501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2482804501
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1997207244
Short name T480
Test name
Test status
Simulation time 542018037 ps
CPU time 76.45 seconds
Started Dec 24 12:29:55 PM PST 23
Finished Dec 24 12:31:37 PM PST 23
Peak memory 212600 kb
Host smart-cb22daac-b74e-4600-b595-a1ae5b13a000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997207244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1997207244
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3139582173
Short name T472
Test name
Test status
Simulation time 4993448367 ps
CPU time 11.92 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:31:00 PM PST 23
Peak memory 215024 kb
Host smart-99ecffe7-ae60-4ef1-8cf9-39de11ab4084
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139582173 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3139582173
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2948826273
Short name T101
Test name
Test status
Simulation time 8012994666 ps
CPU time 14.87 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:31:04 PM PST 23
Peak memory 211236 kb
Host smart-ef41d273-4d4d-4227-a06b-e20570cd47f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948826273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2948826273
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3652533084
Short name T34
Test name
Test status
Simulation time 8086488521 ps
CPU time 78.52 seconds
Started Dec 24 12:30:25 PM PST 23
Finished Dec 24 12:32:08 PM PST 23
Peak memory 211288 kb
Host smart-ebe2578b-4878-4874-8cc3-53b1ebc1419f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652533084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3652533084
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3713290083
Short name T85
Test name
Test status
Simulation time 88115945 ps
CPU time 4.42 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:52 PM PST 23
Peak memory 211176 kb
Host smart-fe32419c-7190-49fd-810e-d2b07e783d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713290083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3713290083
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1040142268
Short name T463
Test name
Test status
Simulation time 1536204769 ps
CPU time 10.37 seconds
Started Dec 24 12:30:14 PM PST 23
Finished Dec 24 12:30:47 PM PST 23
Peak memory 219400 kb
Host smart-2743096a-3542-481b-876e-91963612291b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040142268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1040142268
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.3198321264
Short name T113
Test name
Test status
Simulation time 4202155173 ps
CPU time 85.87 seconds
Started Dec 24 12:30:02 PM PST 23
Finished Dec 24 12:31:54 PM PST 23
Peak memory 211524 kb
Host smart-c00b78da-716b-4701-b28b-e778092c5608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198321264 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.3198321264
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2821350078
Short name T29
Test name
Test status
Simulation time 98774917 ps
CPU time 4.98 seconds
Started Dec 24 12:30:15 PM PST 23
Finished Dec 24 12:30:43 PM PST 23
Peak memory 214264 kb
Host smart-86e3b9d7-60ee-42cc-af64-627d1ce87c39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821350078 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2821350078
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2818295355
Short name T93
Test name
Test status
Simulation time 88857698 ps
CPU time 4.29 seconds
Started Dec 24 12:30:23 PM PST 23
Finished Dec 24 12:30:50 PM PST 23
Peak memory 211048 kb
Host smart-a2c612b1-a47b-481d-a811-5c567abc11c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818295355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2818295355
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2366862508
Short name T75
Test name
Test status
Simulation time 23291155690 ps
CPU time 181.4 seconds
Started Dec 24 12:30:10 PM PST 23
Finished Dec 24 12:33:36 PM PST 23
Peak memory 211140 kb
Host smart-ed7c9e6c-4424-4bf2-8eee-d4bfa10b22cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366862508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2366862508
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2836876980
Short name T140
Test name
Test status
Simulation time 333957141 ps
CPU time 4.46 seconds
Started Dec 24 12:30:31 PM PST 23
Finished Dec 24 12:31:02 PM PST 23
Peak memory 211176 kb
Host smart-1786747c-f8af-4f9b-a759-9c151f53cd2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836876980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.2836876980
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.541595297
Short name T125
Test name
Test status
Simulation time 1158958830 ps
CPU time 13.28 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:58 PM PST 23
Peak memory 219380 kb
Host smart-567e785e-afc3-4283-a0a0-d57563f40e2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541595297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.541595297
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.655135735
Short name T142
Test name
Test status
Simulation time 3938408644 ps
CPU time 17.19 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:31:02 PM PST 23
Peak memory 214760 kb
Host smart-246a21c3-55dd-4d3e-be14-878d037eb0b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655135735 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.655135735
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1430131697
Short name T71
Test name
Test status
Simulation time 945596601 ps
CPU time 10.3 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:55 PM PST 23
Peak memory 211080 kb
Host smart-6fae89fc-077f-4d3a-87dd-7421a226bd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430131697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1430131697
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1501934724
Short name T447
Test name
Test status
Simulation time 1010540740 ps
CPU time 51.35 seconds
Started Dec 24 12:30:33 PM PST 23
Finished Dec 24 12:31:50 PM PST 23
Peak memory 211176 kb
Host smart-1f5c8217-a87f-498f-ba19-1cd771af9a72
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501934724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1501934724
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2957598388
Short name T27
Test name
Test status
Simulation time 2138285920 ps
CPU time 16 seconds
Started Dec 24 12:30:28 PM PST 23
Finished Dec 24 12:31:10 PM PST 23
Peak memory 211184 kb
Host smart-f5d1317e-f30f-4d89-981e-a997e1e98fd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957598388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2957598388
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3126939807
Short name T453
Test name
Test status
Simulation time 1122443278 ps
CPU time 10.24 seconds
Started Dec 24 12:30:21 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 213904 kb
Host smart-aa14df15-7336-41f4-9a45-658a02181453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126939807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3126939807
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.430484973
Short name T77
Test name
Test status
Simulation time 1415403991 ps
CPU time 47.39 seconds
Started Dec 24 12:30:18 PM PST 23
Finished Dec 24 12:31:28 PM PST 23
Peak memory 212236 kb
Host smart-2f20911e-9032-46db-80a5-914e868cd2b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430484973 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.430484973
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3983724754
Short name T32
Test name
Test status
Simulation time 2961024863 ps
CPU time 9.19 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 213732 kb
Host smart-ebd52b4c-4d1b-4d89-9393-a117b2e335c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983724754 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3983724754
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3992258710
Short name T471
Test name
Test status
Simulation time 860706603 ps
CPU time 9.39 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:30:46 PM PST 23
Peak memory 211100 kb
Host smart-e1f8c639-5b14-4bb2-a111-5077f439f166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992258710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3992258710
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1105436636
Short name T476
Test name
Test status
Simulation time 23099237586 ps
CPU time 172.8 seconds
Started Dec 24 12:30:13 PM PST 23
Finished Dec 24 12:33:29 PM PST 23
Peak memory 211244 kb
Host smart-0e5c0f12-3e3b-45d3-921e-baea0e061ac5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105436636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1105436636
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.3582712902
Short name T135
Test name
Test status
Simulation time 6000348263 ps
CPU time 15.51 seconds
Started Dec 24 12:30:22 PM PST 23
Finished Dec 24 12:31:00 PM PST 23
Peak memory 211268 kb
Host smart-2ceaded5-5317-41b7-9817-f5ad36ca70cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582712902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.3582712902
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3501256394
Short name T63
Test name
Test status
Simulation time 85588888 ps
CPU time 6.07 seconds
Started Dec 24 12:30:24 PM PST 23
Finished Dec 24 12:30:54 PM PST 23
Peak memory 219376 kb
Host smart-8f7eaafd-7b05-49a7-a4e8-a77ea0b2344b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501256394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3501256394
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2622433249
Short name T253
Test name
Test status
Simulation time 6504458615 ps
CPU time 15.58 seconds
Started Dec 24 12:45:57 PM PST 23
Finished Dec 24 12:46:15 PM PST 23
Peak memory 210876 kb
Host smart-31b1f9d2-5bf6-4957-a240-fdbbb7e4a3d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622433249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2622433249
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2680419386
Short name T53
Test name
Test status
Simulation time 4927872271 ps
CPU time 73.76 seconds
Started Dec 24 12:46:16 PM PST 23
Finished Dec 24 12:47:38 PM PST 23
Peak memory 212192 kb
Host smart-493f94c7-0f5a-4f33-a890-9239d17bad22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680419386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2680419386
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2311217354
Short name T414
Test name
Test status
Simulation time 5019638431 ps
CPU time 35.11 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:57 PM PST 23
Peak memory 211868 kb
Host smart-be4d37f8-7f7d-4dfd-90e8-c95677f3af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311217354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2311217354
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.832161906
Short name T307
Test name
Test status
Simulation time 1998044692 ps
CPU time 16.72 seconds
Started Dec 24 12:46:13 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 210752 kb
Host smart-1bf6d655-60f7-4773-8b74-aefe12c32094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=832161906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.832161906
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2374450704
Short name T37
Test name
Test status
Simulation time 1359215474 ps
CPU time 108.59 seconds
Started Dec 24 12:46:04 PM PST 23
Finished Dec 24 12:48:03 PM PST 23
Peak memory 237372 kb
Host smart-16dec580-7bc6-4a71-88f5-b060b731da3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374450704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2374450704
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3365205759
Short name T12
Test name
Test status
Simulation time 3056213231 ps
CPU time 30.39 seconds
Started Dec 24 12:46:03 PM PST 23
Finished Dec 24 12:46:43 PM PST 23
Peak memory 212232 kb
Host smart-5598765a-6958-44c3-bac6-c0c21094a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365205759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3365205759
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.4288528184
Short name T376
Test name
Test status
Simulation time 4640165085 ps
CPU time 32.42 seconds
Started Dec 24 12:46:02 PM PST 23
Finished Dec 24 12:46:43 PM PST 23
Peak memory 214100 kb
Host smart-079a7e3d-1a17-4301-900c-0f795ca4b6e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288528184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.4288528184
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2874025094
Short name T244
Test name
Test status
Simulation time 561061096899 ps
CPU time 3535.21 seconds
Started Dec 24 12:45:59 PM PST 23
Finished Dec 24 01:44:58 PM PST 23
Peak memory 265160 kb
Host smart-d24c0479-ceb9-4250-b3f2-053e6efcdc01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874025094 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2874025094
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2800079260
Short name T264
Test name
Test status
Simulation time 5748680510 ps
CPU time 13.35 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 12:46:33 PM PST 23
Peak memory 211004 kb
Host smart-af35dd7c-408e-44d8-b7b9-38508610eac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800079260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2800079260
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3215350474
Short name T348
Test name
Test status
Simulation time 14464694478 ps
CPU time 209.28 seconds
Started Dec 24 12:46:00 PM PST 23
Finished Dec 24 12:49:32 PM PST 23
Peak memory 233556 kb
Host smart-9258ee39-6188-4e36-93ff-f619c91de324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215350474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3215350474
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.4155576438
Short name T433
Test name
Test status
Simulation time 5856712468 ps
CPU time 27.66 seconds
Started Dec 24 12:46:06 PM PST 23
Finished Dec 24 12:46:43 PM PST 23
Peak memory 211384 kb
Host smart-bbc6691b-5ee9-44f1-9727-959f194733b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155576438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.4155576438
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1219318428
Short name T165
Test name
Test status
Simulation time 888858206 ps
CPU time 8.27 seconds
Started Dec 24 12:46:06 PM PST 23
Finished Dec 24 12:46:24 PM PST 23
Peak memory 210776 kb
Host smart-4fcf9902-f889-491c-97e7-3c381ea8a690
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1219318428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1219318428
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.5737432
Short name T43
Test name
Test status
Simulation time 2239295897 ps
CPU time 114.14 seconds
Started Dec 24 12:46:20 PM PST 23
Finished Dec 24 12:48:19 PM PST 23
Peak memory 236336 kb
Host smart-181083f6-0677-4bc1-b38d-75cbbae241b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5737432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.5737432
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4290669729
Short name T435
Test name
Test status
Simulation time 10078979447 ps
CPU time 31.2 seconds
Started Dec 24 12:45:58 PM PST 23
Finished Dec 24 12:46:32 PM PST 23
Peak memory 210848 kb
Host smart-c57b0a68-1429-477b-aeeb-fef610ac3cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290669729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4290669729
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1075574801
Short name T181
Test name
Test status
Simulation time 6811744543 ps
CPU time 67.7 seconds
Started Dec 24 12:45:54 PM PST 23
Finished Dec 24 12:47:04 PM PST 23
Peak memory 216164 kb
Host smart-16d0254f-2b78-4a90-8368-317a7e760c77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075574801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1075574801
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.235494801
Short name T191
Test name
Test status
Simulation time 4327103524 ps
CPU time 17.26 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 210900 kb
Host smart-8c0faaeb-c549-4e7e-aed2-fd0abde74e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235494801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.235494801
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3428939515
Short name T24
Test name
Test status
Simulation time 37203939404 ps
CPU time 222.63 seconds
Started Dec 24 12:46:18 PM PST 23
Finished Dec 24 12:50:07 PM PST 23
Peak memory 224188 kb
Host smart-6d7a47f0-706a-411f-b341-f17a20a7ee35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428939515 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3428939515
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.1621751873
Short name T421
Test name
Test status
Simulation time 954230899 ps
CPU time 11.11 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 12:46:30 PM PST 23
Peak memory 210836 kb
Host smart-5f58b72f-9f3d-4969-9bcb-a66da3304e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1621751873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.1621751873
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.991267569
Short name T255
Test name
Test status
Simulation time 379217410 ps
CPU time 10.14 seconds
Started Dec 24 12:46:14 PM PST 23
Finished Dec 24 12:46:33 PM PST 23
Peak memory 212192 kb
Host smart-f5f29c15-f0b8-4b77-8abf-0b1bcc5268ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991267569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.991267569
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2956227642
Short name T360
Test name
Test status
Simulation time 4382000731 ps
CPU time 36.97 seconds
Started Dec 24 12:46:16 PM PST 23
Finished Dec 24 12:47:01 PM PST 23
Peak memory 214248 kb
Host smart-acf2c79a-0622-412f-abae-3632e25765f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956227642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2956227642
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.2071858652
Short name T269
Test name
Test status
Simulation time 37545042151 ps
CPU time 3345.68 seconds
Started Dec 24 12:46:30 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 235476 kb
Host smart-a982c50d-4fe1-4474-a1bd-49781ce419e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071858652 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.2071858652
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.360428585
Short name T362
Test name
Test status
Simulation time 1628876934 ps
CPU time 9.34 seconds
Started Dec 24 12:46:42 PM PST 23
Finished Dec 24 12:46:53 PM PST 23
Peak memory 210852 kb
Host smart-980fae4e-1713-439d-ab00-b9a74c63e976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360428585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.360428585
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.540904520
Short name T45
Test name
Test status
Simulation time 97704225474 ps
CPU time 282.79 seconds
Started Dec 24 12:46:20 PM PST 23
Finished Dec 24 12:51:08 PM PST 23
Peak memory 236216 kb
Host smart-1e7a7e8b-c708-4412-9ce5-1dc2aff73427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540904520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_c
orrupt_sig_fatal_chk.540904520
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3154060092
Short name T267
Test name
Test status
Simulation time 7167286840 ps
CPU time 14.69 seconds
Started Dec 24 12:46:41 PM PST 23
Finished Dec 24 12:46:57 PM PST 23
Peak memory 211528 kb
Host smart-337e716c-7593-4dc9-80c2-9f1e90e25b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154060092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3154060092
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2216208477
Short name T252
Test name
Test status
Simulation time 382068557 ps
CPU time 5.6 seconds
Started Dec 24 12:46:09 PM PST 23
Finished Dec 24 12:46:22 PM PST 23
Peak memory 210796 kb
Host smart-3a55fa3e-fd72-4d1a-b9f4-c31b53b032bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216208477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2216208477
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2490022133
Short name T89
Test name
Test status
Simulation time 36978150001 ps
CPU time 33.39 seconds
Started Dec 24 12:46:37 PM PST 23
Finished Dec 24 12:47:12 PM PST 23
Peak memory 213396 kb
Host smart-acb7b108-23f6-40b7-b5c2-51c6b9094ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490022133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2490022133
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.1511500325
Short name T1
Test name
Test status
Simulation time 2750331201 ps
CPU time 16.82 seconds
Started Dec 24 12:46:15 PM PST 23
Finished Dec 24 12:46:40 PM PST 23
Peak memory 211236 kb
Host smart-b05883be-a884-482a-a9cd-b8d9ec30bdcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511500325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.1511500325
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.304467403
Short name T263
Test name
Test status
Simulation time 89206798 ps
CPU time 4.4 seconds
Started Dec 24 12:46:53 PM PST 23
Finished Dec 24 12:47:06 PM PST 23
Peak memory 210884 kb
Host smart-e9c05bfd-f58f-4226-9312-4c3068236ab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304467403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.304467403
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.1861302475
Short name T262
Test name
Test status
Simulation time 128798026694 ps
CPU time 339.76 seconds
Started Dec 24 12:46:53 PM PST 23
Finished Dec 24 12:52:41 PM PST 23
Peak memory 233488 kb
Host smart-aa9a3138-3e6c-40a6-94ac-6b9efa45d8fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861302475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.1861302475
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1493226774
Short name T336
Test name
Test status
Simulation time 102814886 ps
CPU time 5.83 seconds
Started Dec 24 12:46:47 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 210780 kb
Host smart-16258e7a-5bc4-44e1-b301-acd2c51634ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493226774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1493226774
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.205288774
Short name T436
Test name
Test status
Simulation time 183859693 ps
CPU time 10.46 seconds
Started Dec 24 12:46:32 PM PST 23
Finished Dec 24 12:46:45 PM PST 23
Peak memory 212444 kb
Host smart-b687cb50-f50a-4826-bf1b-5012c93c1bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205288774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.205288774
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.797362864
Short name T158
Test name
Test status
Simulation time 8956754397 ps
CPU time 28.88 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:18 PM PST 23
Peak memory 216532 kb
Host smart-820055d6-df21-41d8-88bc-123fc98075cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797362864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.797362864
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2597211435
Short name T394
Test name
Test status
Simulation time 1365601377 ps
CPU time 12.36 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:01 PM PST 23
Peak memory 210812 kb
Host smart-b45ac44b-5a28-46a2-be96-2585782a4306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597211435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2597211435
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.4264386189
Short name T302
Test name
Test status
Simulation time 19771679430 ps
CPU time 148.16 seconds
Started Dec 24 12:46:53 PM PST 23
Finished Dec 24 12:49:30 PM PST 23
Peak memory 212188 kb
Host smart-33aa4869-b2e0-4ad6-88a2-31dd843168d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264386189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.4264386189
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1170018521
Short name T229
Test name
Test status
Simulation time 1775679287 ps
CPU time 13.41 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:02 PM PST 23
Peak memory 210976 kb
Host smart-3d67000d-7f7e-4004-a998-6ea58cf6ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170018521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1170018521
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.251464436
Short name T224
Test name
Test status
Simulation time 1521141812 ps
CPU time 5.72 seconds
Started Dec 24 12:46:56 PM PST 23
Finished Dec 24 12:47:09 PM PST 23
Peak memory 210888 kb
Host smart-4a11034c-8e8e-4244-807a-a6a9adc6bb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251464436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.251464436
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.964104231
Short name T256
Test name
Test status
Simulation time 4353552289 ps
CPU time 39.62 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:51 PM PST 23
Peak memory 212592 kb
Host smart-e9ed7754-136a-4707-bf09-88ae08c4ba09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964104231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.964104231
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3919636673
Short name T364
Test name
Test status
Simulation time 13416842200 ps
CPU time 21.25 seconds
Started Dec 24 12:46:53 PM PST 23
Finished Dec 24 12:47:23 PM PST 23
Peak memory 210820 kb
Host smart-9aeee975-b760-4b11-bc34-55dc3557509c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919636673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3919636673
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1330438302
Short name T250
Test name
Test status
Simulation time 950662770 ps
CPU time 10.05 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:06 PM PST 23
Peak memory 210860 kb
Host smart-b932bc3d-e7cb-45fa-ac6a-065924d0f77d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330438302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1330438302
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.879310939
Short name T292
Test name
Test status
Simulation time 96770624025 ps
CPU time 341.27 seconds
Started Dec 24 12:46:57 PM PST 23
Finished Dec 24 12:52:45 PM PST 23
Peak memory 237336 kb
Host smart-fb5f2488-4aa9-46c0-9928-375450ff83ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879310939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.879310939
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2307928961
Short name T396
Test name
Test status
Simulation time 14567445073 ps
CPU time 31.86 seconds
Started Dec 24 12:46:56 PM PST 23
Finished Dec 24 12:47:35 PM PST 23
Peak memory 211388 kb
Host smart-96c43480-af64-4db4-b0a9-9353adec636e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307928961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2307928961
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4026135844
Short name T355
Test name
Test status
Simulation time 5038160392 ps
CPU time 15.76 seconds
Started Dec 24 12:46:56 PM PST 23
Finished Dec 24 12:47:20 PM PST 23
Peak memory 210864 kb
Host smart-a70a30d2-7805-498d-9a64-910ade8f6897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026135844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4026135844
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2387913406
Short name T419
Test name
Test status
Simulation time 14852611900 ps
CPU time 32.76 seconds
Started Dec 24 12:46:45 PM PST 23
Finished Dec 24 12:47:20 PM PST 23
Peak memory 213140 kb
Host smart-0f744b74-29e1-426d-a3b3-c52fcdc5d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387913406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2387913406
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.613209305
Short name T368
Test name
Test status
Simulation time 18874740459 ps
CPU time 33.31 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:23 PM PST 23
Peak memory 213440 kb
Host smart-e8e96a1b-e8ee-4f6d-a0da-4bccf56e1196
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613209305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.613209305
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3585446691
Short name T295
Test name
Test status
Simulation time 1996226214 ps
CPU time 80.7 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:48:14 PM PST 23
Peak memory 219064 kb
Host smart-86716951-60c3-42b3-8359-ad8a80eb61d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585446691 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3585446691
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.503335085
Short name T208
Test name
Test status
Simulation time 3482390869 ps
CPU time 15.34 seconds
Started Dec 24 12:46:50 PM PST 23
Finished Dec 24 12:47:15 PM PST 23
Peak memory 210896 kb
Host smart-4783498b-34a3-4b30-89ae-b740a8a710fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503335085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.503335085
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2713961406
Short name T296
Test name
Test status
Simulation time 1270302495 ps
CPU time 75.69 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:48:05 PM PST 23
Peak memory 232224 kb
Host smart-7d33b9e1-a617-4e26-9240-78a88c38973c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713961406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2713961406
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1566532357
Short name T280
Test name
Test status
Simulation time 6183995200 ps
CPU time 29.33 seconds
Started Dec 24 12:47:01 PM PST 23
Finished Dec 24 12:47:39 PM PST 23
Peak memory 219560 kb
Host smart-a8b9c1f0-8da8-4dbc-9863-ba90f92fa640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566532357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1566532357
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.2070334836
Short name T371
Test name
Test status
Simulation time 782685442 ps
CPU time 10.11 seconds
Started Dec 24 12:47:03 PM PST 23
Finished Dec 24 12:47:20 PM PST 23
Peak memory 210844 kb
Host smart-01574a15-59d7-48e2-9b18-79ec2c51cc1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070334836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.2070334836
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1505002497
Short name T321
Test name
Test status
Simulation time 1549307083 ps
CPU time 21.06 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:17 PM PST 23
Peak memory 212460 kb
Host smart-5b370f1d-b2db-40b4-95ab-cf13e3fa038b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505002497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1505002497
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3317970904
Short name T400
Test name
Test status
Simulation time 230740319 ps
CPU time 15.2 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:09 PM PST 23
Peak memory 213904 kb
Host smart-cab43a25-71ec-484e-b5c1-f40d15c0d6ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317970904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3317970904
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2033859228
Short name T393
Test name
Test status
Simulation time 37164323474 ps
CPU time 2032.58 seconds
Started Dec 24 12:46:51 PM PST 23
Finished Dec 24 01:20:54 PM PST 23
Peak memory 229756 kb
Host smart-5a4e9e9f-45e0-4017-888f-e8b4b2244f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033859228 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2033859228
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1007045871
Short name T219
Test name
Test status
Simulation time 175453286 ps
CPU time 4.5 seconds
Started Dec 24 12:46:58 PM PST 23
Finished Dec 24 12:47:11 PM PST 23
Peak memory 210924 kb
Host smart-4370b409-2efd-4dd0-b95d-1b45695c5a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007045871 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1007045871
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.254971404
Short name T209
Test name
Test status
Simulation time 25556368859 ps
CPU time 244.95 seconds
Started Dec 24 12:46:45 PM PST 23
Finished Dec 24 12:50:53 PM PST 23
Peak memory 211096 kb
Host smart-11262471-7407-420f-8bc1-1ea3aa61f15c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254971404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_c
orrupt_sig_fatal_chk.254971404
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2625555408
Short name T192
Test name
Test status
Simulation time 6001868164 ps
CPU time 20.2 seconds
Started Dec 24 12:46:51 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 211432 kb
Host smart-95f2e28d-16e7-4c6a-b53e-979ee6c510e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625555408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2625555408
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1055658092
Short name T179
Test name
Test status
Simulation time 4775256135 ps
CPU time 15.57 seconds
Started Dec 24 12:46:55 PM PST 23
Finished Dec 24 12:47:18 PM PST 23
Peak memory 210984 kb
Host smart-31d37ca8-f986-494f-b6d5-0d0bd7fd8b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1055658092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1055658092
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.1631237931
Short name T388
Test name
Test status
Simulation time 2071266883 ps
CPU time 22.07 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:16 PM PST 23
Peak memory 211892 kb
Host smart-91fd2d83-c92f-4c00-96f5-8570dd8c342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631237931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.1631237931
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3839903497
Short name T238
Test name
Test status
Simulation time 10083636327 ps
CPU time 29.16 seconds
Started Dec 24 12:46:48 PM PST 23
Finished Dec 24 12:47:23 PM PST 23
Peak memory 213836 kb
Host smart-ade19a9a-c910-44c9-be64-a7e53f99a30c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839903497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3839903497
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1755634438
Short name T177
Test name
Test status
Simulation time 24935602031 ps
CPU time 3260.21 seconds
Started Dec 24 12:46:54 PM PST 23
Finished Dec 24 01:41:22 PM PST 23
Peak memory 235540 kb
Host smart-6099a16b-b9b5-4e62-ac19-841c4632fc6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755634438 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1755634438
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1940395009
Short name T272
Test name
Test status
Simulation time 5507270511 ps
CPU time 12.54 seconds
Started Dec 24 12:46:56 PM PST 23
Finished Dec 24 12:47:16 PM PST 23
Peak memory 210948 kb
Host smart-8827b0b4-e014-47e2-8fb6-038c2130380a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940395009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1940395009
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.850067774
Short name T54
Test name
Test status
Simulation time 92059577340 ps
CPU time 420.24 seconds
Started Dec 24 12:46:49 PM PST 23
Finished Dec 24 12:53:57 PM PST 23
Peak memory 212632 kb
Host smart-0ece94d8-41d3-41e7-806f-ffc3648f33a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850067774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.850067774
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.959708378
Short name T182
Test name
Test status
Simulation time 19766018465 ps
CPU time 29.78 seconds
Started Dec 24 12:46:52 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 211452 kb
Host smart-4da4d250-c055-43a5-be33-fd5fd44dd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959708378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.959708378
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1539905599
Short name T319
Test name
Test status
Simulation time 388243076 ps
CPU time 5.65 seconds
Started Dec 24 12:46:55 PM PST 23
Finished Dec 24 12:47:08 PM PST 23
Peak memory 210884 kb
Host smart-90469cc8-bf82-4235-9fa3-2658b9185eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1539905599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1539905599
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2829647079
Short name T216
Test name
Test status
Simulation time 8621311004 ps
CPU time 42.64 seconds
Started Dec 24 12:46:52 PM PST 23
Finished Dec 24 12:47:44 PM PST 23
Peak memory 213260 kb
Host smart-7154df91-9716-4dda-8ae3-17e106904f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829647079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2829647079
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.265812159
Short name T345
Test name
Test status
Simulation time 181256816 ps
CPU time 10.15 seconds
Started Dec 24 12:47:01 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 210732 kb
Host smart-2993068b-cd6e-4932-afdb-dbd5cb7de144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265812159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.265812159
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2348163831
Short name T420
Test name
Test status
Simulation time 24531573635 ps
CPU time 1060.92 seconds
Started Dec 24 12:46:54 PM PST 23
Finished Dec 24 01:04:43 PM PST 23
Peak memory 235496 kb
Host smart-67b2a765-8399-4c02-ad89-91886d74225e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348163831 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2348163831
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3950343304
Short name T429
Test name
Test status
Simulation time 1275959220 ps
CPU time 11.53 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:00 PM PST 23
Peak memory 210852 kb
Host smart-7925444e-74b9-410d-a653-d1c4ba9bfbfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950343304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3950343304
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.503356300
Short name T10
Test name
Test status
Simulation time 25448872725 ps
CPU time 200.63 seconds
Started Dec 24 12:46:44 PM PST 23
Finished Dec 24 12:50:06 PM PST 23
Peak memory 212132 kb
Host smart-2d06398c-964c-4f47-8afa-4b5e1945fd97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503356300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.503356300
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1688031365
Short name T237
Test name
Test status
Simulation time 15135175514 ps
CPU time 32.45 seconds
Started Dec 24 12:47:00 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 211448 kb
Host smart-2efe26a7-9342-463f-b5db-9888ef940cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688031365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1688031365
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1988146328
Short name T228
Test name
Test status
Simulation time 7649705329 ps
CPU time 15.51 seconds
Started Dec 24 12:46:59 PM PST 23
Finished Dec 24 12:47:24 PM PST 23
Peak memory 210900 kb
Host smart-eb6476fa-d12e-41ed-a501-638c1216b886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988146328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1988146328
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1651891157
Short name T276
Test name
Test status
Simulation time 1729231042 ps
CPU time 23.57 seconds
Started Dec 24 12:46:58 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 212368 kb
Host smart-7e866f08-d3dc-4abc-9663-ee0bc8d6eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651891157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1651891157
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2613254603
Short name T230
Test name
Test status
Simulation time 225783427 ps
CPU time 13.89 seconds
Started Dec 24 12:46:50 PM PST 23
Finished Dec 24 12:47:15 PM PST 23
Peak memory 212972 kb
Host smart-89b2e3c0-ce63-4508-9a4b-67824d1eb06b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613254603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2613254603
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3863459711
Short name T211
Test name
Test status
Simulation time 4116333865 ps
CPU time 16.12 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:47:05 PM PST 23
Peak memory 211004 kb
Host smart-3eb73bfb-5524-4059-b1e4-8e5219d38e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863459711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3863459711
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1661541277
Short name T195
Test name
Test status
Simulation time 217321631493 ps
CPU time 533.32 seconds
Started Dec 24 12:47:00 PM PST 23
Finished Dec 24 12:56:03 PM PST 23
Peak memory 212592 kb
Host smart-cbaa2eda-4348-474d-be8c-199b82a1679d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661541277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1661541277
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2207799183
Short name T172
Test name
Test status
Simulation time 6501598827 ps
CPU time 29.7 seconds
Started Dec 24 12:46:58 PM PST 23
Finished Dec 24 12:47:37 PM PST 23
Peak memory 210952 kb
Host smart-fe730cb8-35a6-4adf-9d88-864d1c63c6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207799183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2207799183
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2377401615
Short name T205
Test name
Test status
Simulation time 648280421 ps
CPU time 9.97 seconds
Started Dec 24 12:46:53 PM PST 23
Finished Dec 24 12:47:12 PM PST 23
Peak memory 210732 kb
Host smart-c85f512f-9eed-4752-9d49-a93e053c934f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377401615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2377401615
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3648791058
Short name T337
Test name
Test status
Simulation time 750836271 ps
CPU time 10.39 seconds
Started Dec 24 12:46:51 PM PST 23
Finished Dec 24 12:47:11 PM PST 23
Peak memory 212116 kb
Host smart-ed852087-a3bc-4662-b641-cb1c2db46e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648791058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3648791058
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1298768278
Short name T163
Test name
Test status
Simulation time 1369687765 ps
CPU time 15.98 seconds
Started Dec 24 12:46:50 PM PST 23
Finished Dec 24 12:47:17 PM PST 23
Peak memory 214768 kb
Host smart-5d86bad8-096f-4524-9e48-efadc45d1695
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298768278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1298768278
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2162091376
Short name T287
Test name
Test status
Simulation time 254162747203 ps
CPU time 5026.28 seconds
Started Dec 24 12:46:55 PM PST 23
Finished Dec 24 02:10:50 PM PST 23
Peak memory 235572 kb
Host smart-004c5afc-43cd-47e2-9449-243d5f2bbc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162091376 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.2162091376
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1657857770
Short name T59
Test name
Test status
Simulation time 266518957454 ps
CPU time 166.22 seconds
Started Dec 24 12:46:15 PM PST 23
Finished Dec 24 12:49:10 PM PST 23
Peak memory 211116 kb
Host smart-f00bedcc-6374-41c5-b391-0aaac56b2842
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657857770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1657857770
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.218348626
Short name T289
Test name
Test status
Simulation time 3715240666 ps
CPU time 31.69 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 12:46:51 PM PST 23
Peak memory 211084 kb
Host smart-61ec794e-8380-448f-945c-34aa2d074f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218348626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.218348626
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3022872250
Short name T231
Test name
Test status
Simulation time 336738964 ps
CPU time 7.67 seconds
Started Dec 24 12:46:03 PM PST 23
Finished Dec 24 12:46:21 PM PST 23
Peak memory 210836 kb
Host smart-936d1837-985e-4d7c-9155-99aa5ea68dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022872250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3022872250
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3693328743
Short name T290
Test name
Test status
Simulation time 753463263 ps
CPU time 10.47 seconds
Started Dec 24 12:46:26 PM PST 23
Finished Dec 24 12:46:38 PM PST 23
Peak memory 212120 kb
Host smart-c0c6a44a-19b8-44ea-859d-ecdc6aa1760c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693328743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3693328743
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1686344671
Short name T196
Test name
Test status
Simulation time 20731929380 ps
CPU time 28.94 seconds
Started Dec 24 12:46:16 PM PST 23
Finished Dec 24 12:46:53 PM PST 23
Peak memory 214948 kb
Host smart-ea46f3f1-ccc8-4d5f-aea6-1cf3201a3adc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686344671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1686344671
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.565146147
Short name T381
Test name
Test status
Simulation time 14006721443 ps
CPU time 14.41 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210936 kb
Host smart-a7ec78ad-2300-4071-ae05-f49f76dec43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565146147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.565146147
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.364118953
Short name T405
Test name
Test status
Simulation time 84731044072 ps
CPU time 188.23 seconds
Started Dec 24 12:46:49 PM PST 23
Finished Dec 24 12:50:05 PM PST 23
Peak memory 212196 kb
Host smart-ec224916-ad72-488c-95ab-8b1607c91756
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364118953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_c
orrupt_sig_fatal_chk.364118953
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.566201318
Short name T422
Test name
Test status
Simulation time 22294433742 ps
CPU time 33.31 seconds
Started Dec 24 12:46:55 PM PST 23
Finished Dec 24 12:47:36 PM PST 23
Peak memory 211200 kb
Host smart-bf47022f-df50-498b-8e14-27b43e14f9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566201318 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.566201318
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2974134867
Short name T329
Test name
Test status
Simulation time 1864451426 ps
CPU time 7.41 seconds
Started Dec 24 12:46:49 PM PST 23
Finished Dec 24 12:47:07 PM PST 23
Peak memory 210840 kb
Host smart-0458ef54-033d-4eb7-b790-55b16660b6df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974134867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2974134867
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3048212832
Short name T194
Test name
Test status
Simulation time 197119274 ps
CPU time 10.11 seconds
Started Dec 24 12:46:58 PM PST 23
Finished Dec 24 12:47:17 PM PST 23
Peak memory 212128 kb
Host smart-2e24cda7-fd07-496e-94cd-3c9c060a5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048212832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3048212832
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1409700308
Short name T234
Test name
Test status
Simulation time 4165847431 ps
CPU time 20.72 seconds
Started Dec 24 12:46:58 PM PST 23
Finished Dec 24 12:47:29 PM PST 23
Peak memory 212440 kb
Host smart-2e7cf559-4a26-4828-8326-913d3234567e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409700308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1409700308
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.3294490781
Short name T44
Test name
Test status
Simulation time 40806020894 ps
CPU time 1959.45 seconds
Started Dec 24 12:46:54 PM PST 23
Finished Dec 24 01:19:42 PM PST 23
Peak memory 235484 kb
Host smart-398745cb-c10c-4ce0-a4dd-c863269aa97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294490781 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.3294490781
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3629754136
Short name T309
Test name
Test status
Simulation time 3142036801 ps
CPU time 14.09 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210908 kb
Host smart-a71bbd5e-6bd6-4344-9ffa-cbd47797a222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629754136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3629754136
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2052701753
Short name T386
Test name
Test status
Simulation time 1780047033 ps
CPU time 107.73 seconds
Started Dec 24 12:47:01 PM PST 23
Finished Dec 24 12:48:57 PM PST 23
Peak memory 236320 kb
Host smart-b0a3391f-2c29-42bd-9fc0-dabf9ce53aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052701753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2052701753
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1058411436
Short name T18
Test name
Test status
Simulation time 7274418302 ps
CPU time 32.47 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:44 PM PST 23
Peak memory 211320 kb
Host smart-5a1df88e-1798-4509-9c09-4d2691ed1413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058411436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1058411436
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2609696371
Short name T335
Test name
Test status
Simulation time 1784506977 ps
CPU time 15.6 seconds
Started Dec 24 12:47:00 PM PST 23
Finished Dec 24 12:47:25 PM PST 23
Peak memory 210856 kb
Host smart-80a1fc64-feb8-441e-80d8-a29e28ba99f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609696371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2609696371
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.1919725818
Short name T207
Test name
Test status
Simulation time 747782938 ps
CPU time 10.34 seconds
Started Dec 24 12:46:59 PM PST 23
Finished Dec 24 12:47:19 PM PST 23
Peak memory 212932 kb
Host smart-410e8bf8-3231-43cf-87b3-88d10c799760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919725818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.1919725818
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1030387351
Short name T417
Test name
Test status
Simulation time 21852640664 ps
CPU time 65.71 seconds
Started Dec 24 12:46:59 PM PST 23
Finished Dec 24 12:48:14 PM PST 23
Peak memory 214744 kb
Host smart-95f6d62d-06fc-40d3-b49a-a14e8b2bbcf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030387351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1030387351
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3803191411
Short name T259
Test name
Test status
Simulation time 140678521849 ps
CPU time 595.84 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:57:08 PM PST 23
Peak memory 235532 kb
Host smart-6598c587-3bdd-4c28-81f1-49c788dfd233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803191411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3803191411
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1017740121
Short name T308
Test name
Test status
Simulation time 7934347245 ps
CPU time 15.77 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 210896 kb
Host smart-3d52960b-300c-498d-b80b-f60d65ed21d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017740121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1017740121
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1693165533
Short name T437
Test name
Test status
Simulation time 23766192565 ps
CPU time 260.27 seconds
Started Dec 24 12:47:21 PM PST 23
Finished Dec 24 12:51:51 PM PST 23
Peak memory 237460 kb
Host smart-9fcb054a-385b-4553-8438-662d25fc4aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693165533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1693165533
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3810787182
Short name T16
Test name
Test status
Simulation time 199993837 ps
CPU time 9.9 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:47:25 PM PST 23
Peak memory 210960 kb
Host smart-c579d1c3-2ff1-40a0-9896-e1f2a1dc7c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810787182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3810787182
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.582242492
Short name T242
Test name
Test status
Simulation time 95642496 ps
CPU time 5.63 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:18 PM PST 23
Peak memory 210860 kb
Host smart-2121691b-4b7e-4159-9df6-604b5314a59e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=582242492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.582242492
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1093280601
Short name T183
Test name
Test status
Simulation time 15403989124 ps
CPU time 31.83 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 212072 kb
Host smart-7ead4f92-aea6-487b-8141-d94650d01c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093280601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1093280601
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1187844362
Short name T46
Test name
Test status
Simulation time 3505819283 ps
CPU time 30.94 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:43 PM PST 23
Peak memory 212656 kb
Host smart-29209d68-397e-4eb5-afc0-09dc0d141459
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187844362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1187844362
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.3363934868
Short name T404
Test name
Test status
Simulation time 94837380303 ps
CPU time 1334 seconds
Started Dec 24 12:47:08 PM PST 23
Finished Dec 24 01:09:26 PM PST 23
Peak memory 228504 kb
Host smart-88a29200-9095-4247-ab63-55c4eecc0d38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363934868 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.3363934868
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2332103743
Short name T186
Test name
Test status
Simulation time 334360926 ps
CPU time 4.38 seconds
Started Dec 24 12:47:22 PM PST 23
Finished Dec 24 12:47:32 PM PST 23
Peak memory 210916 kb
Host smart-f4653772-15fa-4040-a652-cf23c6307ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332103743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2332103743
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1819757536
Short name T187
Test name
Test status
Simulation time 16447443710 ps
CPU time 156.89 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:49:53 PM PST 23
Peak memory 237392 kb
Host smart-a681c7a6-e3f2-423b-8a72-4b0fe0f03ce2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819757536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1819757536
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.3369599800
Short name T320
Test name
Test status
Simulation time 70057597730 ps
CPU time 31.74 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:48 PM PST 23
Peak memory 211276 kb
Host smart-4ed8c009-24ba-4ca3-b2f2-7ca371b3656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369599800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.3369599800
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3781183198
Short name T161
Test name
Test status
Simulation time 463624492 ps
CPU time 8.56 seconds
Started Dec 24 12:47:08 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 210868 kb
Host smart-b1c63bdd-1c4e-45ad-b329-49d1d2146fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781183198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3781183198
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.644873696
Short name T297
Test name
Test status
Simulation time 2431447893 ps
CPU time 27.08 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 212348 kb
Host smart-a674c68e-935f-4997-b2a1-0c5f4c082cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644873696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.644873696
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4065893639
Short name T277
Test name
Test status
Simulation time 34622274955 ps
CPU time 64.14 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:48:21 PM PST 23
Peak memory 215868 kb
Host smart-e7dcf52d-c954-4967-99fd-a2fe97c8288c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065893639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4065893639
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3410711257
Short name T240
Test name
Test status
Simulation time 1670171983 ps
CPU time 9.66 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:22 PM PST 23
Peak memory 210908 kb
Host smart-b12d5be7-f1d9-4ac8-9710-f40426572df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410711257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3410711257
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2281837421
Short name T174
Test name
Test status
Simulation time 1955918009 ps
CPU time 125.44 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:49:19 PM PST 23
Peak memory 237260 kb
Host smart-1373579d-6af0-43b8-ac7e-f8528812ef74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281837421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2281837421
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1982338286
Short name T193
Test name
Test status
Simulation time 3797631517 ps
CPU time 31.89 seconds
Started Dec 24 12:47:08 PM PST 23
Finished Dec 24 12:47:44 PM PST 23
Peak memory 211112 kb
Host smart-06ab1813-107d-4596-8248-ea229b9a19fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982338286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1982338286
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.759137836
Short name T413
Test name
Test status
Simulation time 707448428 ps
CPU time 7.04 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:19 PM PST 23
Peak memory 210916 kb
Host smart-6453c7bb-5578-4c58-9332-81b5cb09d20f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759137836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.759137836
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.922389261
Short name T266
Test name
Test status
Simulation time 5592089043 ps
CPU time 20.01 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:47:37 PM PST 23
Peak memory 212844 kb
Host smart-75782d20-83ee-42a3-8871-e715352451a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922389261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.922389261
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1479764190
Short name T384
Test name
Test status
Simulation time 6120856388 ps
CPU time 23.65 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 213696 kb
Host smart-05a6dcee-ba8b-433d-a21b-08373eec815f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479764190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1479764190
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2916567202
Short name T331
Test name
Test status
Simulation time 66580769565 ps
CPU time 4583.11 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 02:03:42 PM PST 23
Peak memory 237416 kb
Host smart-7f881c2e-83ed-4a6c-927e-23005cd59984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916567202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2916567202
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.4198370552
Short name T300
Test name
Test status
Simulation time 14244503655 ps
CPU time 14.81 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:28 PM PST 23
Peak memory 210900 kb
Host smart-51782e6d-bf70-4fb9-acf5-dfdda34bcf01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198370552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.4198370552
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3542903129
Short name T270
Test name
Test status
Simulation time 24117520307 ps
CPU time 276.81 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:51:52 PM PST 23
Peak memory 233280 kb
Host smart-bf9e3d00-05db-42f5-b468-ab80071cd97e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542903129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3542903129
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3839213609
Short name T408
Test name
Test status
Simulation time 177103933 ps
CPU time 9.92 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:47:24 PM PST 23
Peak memory 210808 kb
Host smart-0019590a-4c0b-48f0-84ca-b71ddc6b67e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839213609 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3839213609
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1902854685
Short name T313
Test name
Test status
Simulation time 218258271 ps
CPU time 6.97 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 210856 kb
Host smart-955b4a72-c5f2-4157-8ffe-1ffc02745124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902854685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1902854685
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3673047960
Short name T428
Test name
Test status
Simulation time 9082755150 ps
CPU time 25.82 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:39 PM PST 23
Peak memory 213320 kb
Host smart-f841111a-80ab-4d8f-b567-a9fa739b6618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673047960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3673047960
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1485384400
Short name T197
Test name
Test status
Simulation time 30216798974 ps
CPU time 73.04 seconds
Started Dec 24 12:47:08 PM PST 23
Finished Dec 24 12:48:25 PM PST 23
Peak memory 216748 kb
Host smart-51dfdd89-e220-4f11-b069-45748b7c7f5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485384400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1485384400
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3723463762
Short name T260
Test name
Test status
Simulation time 53266647392 ps
CPU time 2332.74 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 01:26:07 PM PST 23
Peak memory 235452 kb
Host smart-673bce2a-8137-4856-94c3-6702f5e8c8a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723463762 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3723463762
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1539010917
Short name T38
Test name
Test status
Simulation time 178587002 ps
CPU time 4.5 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:18 PM PST 23
Peak memory 210904 kb
Host smart-a88d0d0c-59e8-424c-9882-eae81a96f2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539010917 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1539010917
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.160790886
Short name T365
Test name
Test status
Simulation time 90249638347 ps
CPU time 256.49 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:51:33 PM PST 23
Peak memory 224236 kb
Host smart-6f07a760-6399-4621-b93a-8b93488de9eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160790886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.160790886
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.1576443573
Short name T247
Test name
Test status
Simulation time 1922354963 ps
CPU time 15.66 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:47:39 PM PST 23
Peak memory 211052 kb
Host smart-d8e817ee-1437-40f3-bc18-0df8433bc025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576443573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.1576443573
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2542336938
Short name T279
Test name
Test status
Simulation time 1403111686 ps
CPU time 13.75 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:28 PM PST 23
Peak memory 210824 kb
Host smart-5c780a7b-c58a-443d-92f3-5a51e90abb7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542336938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2542336938
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1525866070
Short name T330
Test name
Test status
Simulation time 4363118209 ps
CPU time 16.83 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:28 PM PST 23
Peak memory 212788 kb
Host smart-5575dfd0-23fc-4c3f-b647-50e9c4ff6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525866070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1525866070
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.3154324484
Short name T268
Test name
Test status
Simulation time 6933448936 ps
CPU time 16.94 seconds
Started Dec 24 12:47:22 PM PST 23
Finished Dec 24 12:47:44 PM PST 23
Peak memory 210916 kb
Host smart-65a1b4d1-956e-4767-957e-dca1dfe0982a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154324484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.3154324484
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.650491217
Short name T339
Test name
Test status
Simulation time 30587617884 ps
CPU time 1682.24 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 01:15:15 PM PST 23
Peak memory 231060 kb
Host smart-1c02f79f-c3bc-4c0d-bcab-86a401f9c030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650491217 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.650491217
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3220092557
Short name T156
Test name
Test status
Simulation time 10500120621 ps
CPU time 10.55 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210896 kb
Host smart-36473db9-5bf7-42af-a4bf-c35f60dec427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220092557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3220092557
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2181567394
Short name T354
Test name
Test status
Simulation time 20587731374 ps
CPU time 79.32 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:48:50 PM PST 23
Peak memory 237424 kb
Host smart-56fbbea7-77ea-4a39-91be-4f5918e4b0b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181567394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2181567394
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2642178053
Short name T350
Test name
Test status
Simulation time 36428609846 ps
CPU time 35.71 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:49 PM PST 23
Peak memory 211288 kb
Host smart-43dc2d9d-dd6b-4d75-8d60-4cacef94021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642178053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2642178053
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.69396755
Short name T239
Test name
Test status
Simulation time 142955875 ps
CPU time 6.65 seconds
Started Dec 24 12:47:10 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 210792 kb
Host smart-768cd809-ba32-4653-b336-2e22336f406a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69396755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.69396755
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2768500151
Short name T406
Test name
Test status
Simulation time 4025536859 ps
CPU time 38.24 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:52 PM PST 23
Peak memory 212472 kb
Host smart-a84e45ba-9f17-4755-9a36-cee19c15e6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768500151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2768500151
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4034246576
Short name T223
Test name
Test status
Simulation time 2266281060 ps
CPU time 32.76 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 215928 kb
Host smart-0dca07c4-7290-4a5c-b114-100804ca447b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034246576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4034246576
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2867025195
Short name T152
Test name
Test status
Simulation time 6200824390 ps
CPU time 13.23 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210852 kb
Host smart-224c5c4b-f727-4ed1-801d-b76df7c136e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867025195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2867025195
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.315580866
Short name T344
Test name
Test status
Simulation time 3571734723 ps
CPU time 234.44 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:51:17 PM PST 23
Peak memory 236724 kb
Host smart-1ab19fcb-eeec-451c-91ed-0e3951cdd4a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315580866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.315580866
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2938037954
Short name T170
Test name
Test status
Simulation time 5790580482 ps
CPU time 19.38 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:32 PM PST 23
Peak memory 211500 kb
Host smart-94bdf12b-5a56-4bec-a811-310f28521f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938037954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2938037954
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3218204298
Short name T349
Test name
Test status
Simulation time 20623745113 ps
CPU time 11.78 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:26 PM PST 23
Peak memory 210960 kb
Host smart-b9e08d20-6c46-41e7-8dcc-48946a204191
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3218204298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3218204298
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.3386889171
Short name T285
Test name
Test status
Simulation time 2889230581 ps
CPU time 12.38 seconds
Started Dec 24 12:47:07 PM PST 23
Finished Dec 24 12:47:24 PM PST 23
Peak memory 212632 kb
Host smart-57e79a0c-35e7-4110-b235-e09c9400cf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386889171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3386889171
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3378632667
Short name T154
Test name
Test status
Simulation time 10652677700 ps
CPU time 16.09 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:47:37 PM PST 23
Peak memory 211636 kb
Host smart-d344a553-7845-4a12-b923-12f377a1285a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378632667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3378632667
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.827526419
Short name T159
Test name
Test status
Simulation time 32541518411 ps
CPU time 7134.47 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 02:46:18 PM PST 23
Peak memory 235492 kb
Host smart-7dafd671-119f-4c9d-9193-874e511a9aa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827526419 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.827526419
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2340726569
Short name T40
Test name
Test status
Simulation time 6371926185 ps
CPU time 14.38 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 210880 kb
Host smart-52e15c57-06c9-4ca7-bfe1-48dd0dc721af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340726569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2340726569
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.382608054
Short name T294
Test name
Test status
Simulation time 41288710385 ps
CPU time 399.49 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 12:53:58 PM PST 23
Peak memory 237408 kb
Host smart-89948af2-5ad8-4e16-a18b-6f220a10241a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382608054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.382608054
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2319763503
Short name T343
Test name
Test status
Simulation time 1740492393 ps
CPU time 19.9 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 210960 kb
Host smart-9ac7bea5-347e-423f-8acc-1d47b02a076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319763503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2319763503
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1939875001
Short name T416
Test name
Test status
Simulation time 1307704767 ps
CPU time 5.8 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:22 PM PST 23
Peak memory 210780 kb
Host smart-c2f9393d-28a4-4136-9f8b-82e2427b603c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1939875001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1939875001
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2952539736
Short name T233
Test name
Test status
Simulation time 3231926426 ps
CPU time 22.64 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 212772 kb
Host smart-b93cee5c-af6d-4a05-adac-2fce065cfbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952539736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2952539736
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4277756361
Short name T168
Test name
Test status
Simulation time 15860017177 ps
CPU time 31.4 seconds
Started Dec 24 12:47:20 PM PST 23
Finished Dec 24 12:47:57 PM PST 23
Peak memory 213412 kb
Host smart-21dd88d4-27d8-4f5c-9059-c2ca04a79053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277756361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4277756361
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1169466213
Short name T157
Test name
Test status
Simulation time 347239487 ps
CPU time 4.43 seconds
Started Dec 24 12:46:38 PM PST 23
Finished Dec 24 12:46:43 PM PST 23
Peak memory 210892 kb
Host smart-5545b8a3-bde9-425a-807a-cb993149896c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169466213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1169466213
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1093155003
Short name T411
Test name
Test status
Simulation time 3311201109 ps
CPU time 157.28 seconds
Started Dec 24 12:46:15 PM PST 23
Finished Dec 24 12:49:01 PM PST 23
Peak memory 236388 kb
Host smart-380e9e60-5e21-4ad1-b8b9-4772ab0711d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093155003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1093155003
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3354746529
Short name T361
Test name
Test status
Simulation time 1017217316 ps
CPU time 13.38 seconds
Started Dec 24 12:46:14 PM PST 23
Finished Dec 24 12:46:37 PM PST 23
Peak memory 210892 kb
Host smart-9219ff40-44fb-41b8-9e08-80c51b4458a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354746529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3354746529
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4212446284
Short name T106
Test name
Test status
Simulation time 954276254 ps
CPU time 11.29 seconds
Started Dec 24 12:46:11 PM PST 23
Finished Dec 24 12:46:31 PM PST 23
Peak memory 210860 kb
Host smart-3cd64d57-7614-4a2c-b5d5-f2b756f53c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4212446284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4212446284
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3165843500
Short name T42
Test name
Test status
Simulation time 801964263 ps
CPU time 114.96 seconds
Started Dec 24 12:46:25 PM PST 23
Finished Dec 24 12:48:22 PM PST 23
Peak memory 236224 kb
Host smart-b3055072-7e6a-40eb-b0fe-13100be66676
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165843500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3165843500
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3378184441
Short name T415
Test name
Test status
Simulation time 744193955 ps
CPU time 10.43 seconds
Started Dec 24 12:46:05 PM PST 23
Finished Dec 24 12:46:25 PM PST 23
Peak memory 212652 kb
Host smart-f43c96d6-6c93-414c-9675-d0e8e4a6d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378184441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3378184441
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3005640249
Short name T432
Test name
Test status
Simulation time 16633389956 ps
CPU time 45.02 seconds
Started Dec 24 12:46:50 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 214708 kb
Host smart-5dc55b34-ceaa-4de9-92af-02062cf33255
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005640249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3005640249
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3050915036
Short name T210
Test name
Test status
Simulation time 150956785725 ps
CPU time 1717.8 seconds
Started Dec 24 12:46:34 PM PST 23
Finished Dec 24 01:15:13 PM PST 23
Peak memory 235488 kb
Host smart-a70a2c0f-c9eb-4460-a37b-49c1f09f5373
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050915036 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3050915036
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.746457948
Short name T418
Test name
Test status
Simulation time 4146362311 ps
CPU time 11.08 seconds
Started Dec 24 12:47:19 PM PST 23
Finished Dec 24 12:47:36 PM PST 23
Peak memory 210888 kb
Host smart-a8fbd7fc-8ac8-4f0b-8f03-8c3a69c76ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746457948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.746457948
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3418304106
Short name T283
Test name
Test status
Simulation time 51025815690 ps
CPU time 301.67 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:52:22 PM PST 23
Peak memory 234592 kb
Host smart-e4da7068-2200-47db-a83d-157c3dcd5c9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418304106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3418304106
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1411365797
Short name T22
Test name
Test status
Simulation time 2866410166 ps
CPU time 26.4 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 211024 kb
Host smart-6607dcf2-f2fc-4a12-a76c-3b4610a9d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411365797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1411365797
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3389364190
Short name T382
Test name
Test status
Simulation time 794035782 ps
CPU time 10.35 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210788 kb
Host smart-73b84afd-d313-410c-887c-abf3c2bfed43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3389364190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3389364190
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1292098639
Short name T245
Test name
Test status
Simulation time 8273097693 ps
CPU time 26.46 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 213432 kb
Host smart-caa8d23e-3df1-45ea-a035-1d2bb83178f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292098639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1292098639
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.634124997
Short name T325
Test name
Test status
Simulation time 9808319771 ps
CPU time 18.44 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:34 PM PST 23
Peak memory 210708 kb
Host smart-ed15eb1e-9177-4a1f-9dae-d41dabc3d231
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634124997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.rom_ctrl_stress_all.634124997
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2326853099
Short name T341
Test name
Test status
Simulation time 85578938 ps
CPU time 4.43 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:21 PM PST 23
Peak memory 210952 kb
Host smart-c2d0ede3-3107-48ba-9f7f-30a7717a0ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326853099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2326853099
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2800982516
Short name T324
Test name
Test status
Simulation time 16533619419 ps
CPU time 197.01 seconds
Started Dec 24 12:47:19 PM PST 23
Finished Dec 24 12:50:42 PM PST 23
Peak memory 236376 kb
Host smart-4357561a-1004-4c0e-8953-8f6b7f3071b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800982516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2800982516
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1692093330
Short name T359
Test name
Test status
Simulation time 3911835090 ps
CPU time 33.14 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:52 PM PST 23
Peak memory 211028 kb
Host smart-ff8d5384-c20f-440f-b3e8-7b00387bf669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692093330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1692093330
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1274216402
Short name T284
Test name
Test status
Simulation time 93686455 ps
CPU time 5.59 seconds
Started Dec 24 12:47:22 PM PST 23
Finished Dec 24 12:47:32 PM PST 23
Peak memory 210772 kb
Host smart-d54ab993-53f6-4500-820f-813abbd092bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1274216402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1274216402
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.713221205
Short name T274
Test name
Test status
Simulation time 3240252924 ps
CPU time 33.6 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:53 PM PST 23
Peak memory 212524 kb
Host smart-e0a13e1b-5d74-4742-bec9-4e32f36c73a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713221205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.713221205
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.466484767
Short name T351
Test name
Test status
Simulation time 695687162 ps
CPU time 29.92 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:47:51 PM PST 23
Peak memory 215560 kb
Host smart-dcb18255-fa41-44a6-8452-ea537ba91284
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466484767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.rom_ctrl_stress_all.466484767
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2623182904
Short name T431
Test name
Test status
Simulation time 10248684236 ps
CPU time 12.82 seconds
Started Dec 24 12:47:11 PM PST 23
Finished Dec 24 12:47:29 PM PST 23
Peak memory 210864 kb
Host smart-ed4ed639-2958-49cd-9226-72ae4e715fd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623182904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2623182904
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.228619810
Short name T271
Test name
Test status
Simulation time 55524425172 ps
CPU time 291.83 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:52:12 PM PST 23
Peak memory 233512 kb
Host smart-988ef953-198e-4d0e-96bd-15ac1667fa36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228619810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.228619810
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2826927768
Short name T206
Test name
Test status
Simulation time 175694914 ps
CPU time 9.78 seconds
Started Dec 24 12:47:17 PM PST 23
Finished Dec 24 12:47:33 PM PST 23
Peak memory 210888 kb
Host smart-6e17d1f5-e65d-4790-bea2-127ddd75445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826927768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2826927768
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.417441763
Short name T171
Test name
Test status
Simulation time 4141050002 ps
CPU time 11.74 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 210908 kb
Host smart-9a62ca11-0c2e-4723-803f-456a9ae811a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417441763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.417441763
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.3243473262
Short name T261
Test name
Test status
Simulation time 3784637612 ps
CPU time 39.62 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 212740 kb
Host smart-a90a9256-4aaa-4cd8-b70b-36822768af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243473262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3243473262
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2078601953
Short name T90
Test name
Test status
Simulation time 312372046 ps
CPU time 16.65 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 12:47:35 PM PST 23
Peak memory 215036 kb
Host smart-e118b14e-1f77-4d5d-9f47-cd6f916b22a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078601953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2078601953
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.318056159
Short name T311
Test name
Test status
Simulation time 89455023174 ps
CPU time 8782.48 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 03:13:42 PM PST 23
Peak memory 234216 kb
Host smart-18704bcc-79aa-4f85-919e-1c78920195da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318056159 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.318056159
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2330002082
Short name T153
Test name
Test status
Simulation time 168514108 ps
CPU time 4.25 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:47:27 PM PST 23
Peak memory 210928 kb
Host smart-c81b1039-c450-47ca-9e91-a87983e74e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330002082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2330002082
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2424394559
Short name T304
Test name
Test status
Simulation time 12495213395 ps
CPU time 163.01 seconds
Started Dec 24 12:47:21 PM PST 23
Finished Dec 24 12:50:09 PM PST 23
Peak memory 236284 kb
Host smart-bc467ed5-f28b-4fe0-b198-6eaf08d17075
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424394559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2424394559
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1621089013
Short name T189
Test name
Test status
Simulation time 695929842 ps
CPU time 9.5 seconds
Started Dec 24 12:47:18 PM PST 23
Finished Dec 24 12:47:33 PM PST 23
Peak memory 211388 kb
Host smart-ea8c42f3-546f-4113-9c72-e489b3ec3ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621089013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1621089013
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1126100486
Short name T9
Test name
Test status
Simulation time 1820623035 ps
CPU time 15.43 seconds
Started Dec 24 12:47:21 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 210760 kb
Host smart-e0d6d3b7-c5e3-4c3f-a24d-ed644db46751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1126100486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1126100486
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2976974933
Short name T353
Test name
Test status
Simulation time 3160301951 ps
CPU time 32.24 seconds
Started Dec 24 12:47:09 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 212072 kb
Host smart-917215e4-3d7c-4acd-a4c5-6424222d9036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976974933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2976974933
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3304045571
Short name T160
Test name
Test status
Simulation time 8423755369 ps
CPU time 75.12 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:48:36 PM PST 23
Peak memory 215812 kb
Host smart-b4d4cf00-d253-4e3a-8d98-149f968709a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304045571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3304045571
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.4115376035
Short name T212
Test name
Test status
Simulation time 97020039906 ps
CPU time 1142.87 seconds
Started Dec 24 12:47:18 PM PST 23
Finished Dec 24 01:06:27 PM PST 23
Peak memory 235440 kb
Host smart-e896f8cb-2b0c-4dc6-a224-879e496c204c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115376035 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.4115376035
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4199618040
Short name T200
Test name
Test status
Simulation time 18681506124 ps
CPU time 15.48 seconds
Started Dec 24 12:47:14 PM PST 23
Finished Dec 24 12:47:35 PM PST 23
Peak memory 211024 kb
Host smart-c1b78c1a-b458-4975-8d7e-12101e51ea49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199618040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4199618040
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1839138563
Short name T423
Test name
Test status
Simulation time 58198013629 ps
CPU time 522.92 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:56:05 PM PST 23
Peak memory 212188 kb
Host smart-a516c190-9d0c-4b68-bce8-90dec554856f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839138563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1839138563
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.698434340
Short name T378
Test name
Test status
Simulation time 4265405507 ps
CPU time 33.02 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:47:56 PM PST 23
Peak memory 211080 kb
Host smart-75b776dd-5c8e-4e82-bde9-d00feace6253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698434340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.698434340
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4094866326
Short name T199
Test name
Test status
Simulation time 1944001345 ps
CPU time 15.89 seconds
Started Dec 24 12:47:12 PM PST 23
Finished Dec 24 12:47:33 PM PST 23
Peak memory 210776 kb
Host smart-2f5ef4a6-21e3-49b6-870a-6eece17f9099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094866326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4094866326
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2641178610
Short name T375
Test name
Test status
Simulation time 23804763227 ps
CPU time 23.74 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 213392 kb
Host smart-a3e4076f-dfca-465b-a0d2-8d7aa5f24bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641178610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2641178610
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.49745250
Short name T370
Test name
Test status
Simulation time 16585395921 ps
CPU time 50.74 seconds
Started Dec 24 12:47:13 PM PST 23
Finished Dec 24 12:48:09 PM PST 23
Peak memory 216244 kb
Host smart-ac3fa897-6078-43c4-823b-bcd9d6795734
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49745250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 34.rom_ctrl_stress_all.49745250
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.3454509826
Short name T232
Test name
Test status
Simulation time 3497891493 ps
CPU time 14.4 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 210880 kb
Host smart-e6f638b7-3a72-4689-af96-bae32ac7d40f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454509826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.3454509826
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.678732663
Short name T254
Test name
Test status
Simulation time 117630022824 ps
CPU time 305.93 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:52:29 PM PST 23
Peak memory 236492 kb
Host smart-d917a1df-a6c8-4a4c-90ff-c983d2f066ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678732663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.678732663
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.268833126
Short name T334
Test name
Test status
Simulation time 2122288738 ps
CPU time 22.81 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:47:57 PM PST 23
Peak memory 210944 kb
Host smart-b68f7777-aedb-4c6e-9b6b-5be1c3895b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268833126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.268833126
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.975680598
Short name T2
Test name
Test status
Simulation time 2869550665 ps
CPU time 10.15 seconds
Started Dec 24 12:47:16 PM PST 23
Finished Dec 24 12:47:32 PM PST 23
Peak memory 210916 kb
Host smart-920b932f-8bbc-4643-a4ed-3e93536709cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975680598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.975680598
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2718574241
Short name T340
Test name
Test status
Simulation time 380044719 ps
CPU time 10.66 seconds
Started Dec 24 12:47:15 PM PST 23
Finished Dec 24 12:47:31 PM PST 23
Peak memory 212500 kb
Host smart-b618abd0-5706-4037-9b73-e9366b80fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718574241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2718574241
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.2450764785
Short name T258
Test name
Test status
Simulation time 20147244489 ps
CPU time 75.19 seconds
Started Dec 24 12:47:17 PM PST 23
Finished Dec 24 12:48:38 PM PST 23
Peak memory 217056 kb
Host smart-4ac689d6-b723-4b77-b8ef-ffca63c31547
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450764785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.2450764785
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2058452664
Short name T298
Test name
Test status
Simulation time 24681188158 ps
CPU time 1877.52 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 01:18:48 PM PST 23
Peak memory 233216 kb
Host smart-e9c10cda-d5da-4b58-8754-96cc075af68c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058452664 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2058452664
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1758542003
Short name T397
Test name
Test status
Simulation time 15613959442 ps
CPU time 13.71 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:47:50 PM PST 23
Peak memory 210968 kb
Host smart-008b016d-2029-4fff-a121-88683bd74187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758542003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1758542003
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3991592673
Short name T373
Test name
Test status
Simulation time 168984669 ps
CPU time 10.16 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 211368 kb
Host smart-00af226d-015b-462b-830e-db42b03825b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991592673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3991592673
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.2127667976
Short name T327
Test name
Test status
Simulation time 1654885541 ps
CPU time 8.48 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:47:38 PM PST 23
Peak memory 210800 kb
Host smart-bdc6ae30-a223-4383-96f6-46e074dcfe32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127667976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.2127667976
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3348126155
Short name T86
Test name
Test status
Simulation time 6023690831 ps
CPU time 31.04 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 12:48:05 PM PST 23
Peak memory 213344 kb
Host smart-9e403bb0-24a0-4918-8733-2b42215efdc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348126155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3348126155
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1257288695
Short name T88
Test name
Test status
Simulation time 17969673060 ps
CPU time 22 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:58 PM PST 23
Peak memory 211776 kb
Host smart-e187ef19-7874-4bbd-b34e-ba732e25c7d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257288695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1257288695
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.3094972970
Short name T214
Test name
Test status
Simulation time 18960096426 ps
CPU time 8804.44 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 03:14:16 PM PST 23
Peak memory 228916 kb
Host smart-5ac2ab40-aa4b-42d5-bc08-356eaa5c20df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094972970 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.3094972970
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.3107624971
Short name T204
Test name
Test status
Simulation time 3592600968 ps
CPU time 9.87 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 12:47:43 PM PST 23
Peak memory 211040 kb
Host smart-5c0e4e38-e1af-46ba-98a8-428d24664d01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107624971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.3107624971
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3050520860
Short name T369
Test name
Test status
Simulation time 4270229148 ps
CPU time 220.07 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:51:12 PM PST 23
Peak memory 234452 kb
Host smart-8b6aadd3-015b-4f60-9019-aa4d42055d5b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050520860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3050520860
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.483218654
Short name T412
Test name
Test status
Simulation time 347460123 ps
CPU time 10.39 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 215196 kb
Host smart-e33c4ad9-adee-477d-9a8d-cbcad3acf1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483218654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.483218654
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2349135000
Short name T3
Test name
Test status
Simulation time 3805811832 ps
CPU time 16.34 seconds
Started Dec 24 12:47:24 PM PST 23
Finished Dec 24 12:47:45 PM PST 23
Peak memory 210808 kb
Host smart-c7a0045d-9961-445b-af9a-d62fbab0b144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349135000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2349135000
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2371158825
Short name T288
Test name
Test status
Simulation time 4472333510 ps
CPU time 54.49 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:48:27 PM PST 23
Peak memory 216888 kb
Host smart-a5efa2bd-b1df-4b59-87d6-617ac9618a75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371158825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2371158825
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3779139202
Short name T49
Test name
Test status
Simulation time 38721311567 ps
CPU time 803.92 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 01:00:57 PM PST 23
Peak memory 231852 kb
Host smart-1f2c3421-f2ed-4cdb-8b9b-cf42ada71cdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779139202 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3779139202
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.923692636
Short name T281
Test name
Test status
Simulation time 85648281 ps
CPU time 4.4 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:39 PM PST 23
Peak memory 210876 kb
Host smart-3210d0f9-b819-4e47-9102-b4021b55ec1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923692636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.923692636
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1955565768
Short name T434
Test name
Test status
Simulation time 2233972662 ps
CPU time 22.51 seconds
Started Dec 24 12:47:34 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 214904 kb
Host smart-ffa99519-6576-4da0-9103-ee956d4200e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955565768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1955565768
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.100544437
Short name T107
Test name
Test status
Simulation time 1396975929 ps
CPU time 13.68 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 210788 kb
Host smart-21d95e2b-b904-4c06-b796-a6abd073ff07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100544437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.100544437
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.4245126306
Short name T155
Test name
Test status
Simulation time 1052459476 ps
CPU time 10.16 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 212684 kb
Host smart-acf15986-5a4c-45ef-bcbe-04fe23637aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245126306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.4245126306
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.67477591
Short name T342
Test name
Test status
Simulation time 17948725494 ps
CPU time 36.18 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:48:10 PM PST 23
Peak memory 212572 kb
Host smart-9b1ec786-5208-4847-b1eb-abb73284be7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67477591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 38.rom_ctrl_stress_all.67477591
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3835800433
Short name T303
Test name
Test status
Simulation time 5603768454 ps
CPU time 13.11 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 210976 kb
Host smart-05f7431e-7230-45da-8f9f-4d800097338e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835800433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3835800433
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2100307058
Short name T20
Test name
Test status
Simulation time 49065761774 ps
CPU time 367.05 seconds
Started Dec 24 12:47:25 PM PST 23
Finished Dec 24 12:53:37 PM PST 23
Peak memory 234420 kb
Host smart-dbbd9eb1-9875-4065-8542-3675b9dd673b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100307058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2100307058
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3517678556
Short name T217
Test name
Test status
Simulation time 3319451350 ps
CPU time 24.51 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:59 PM PST 23
Peak memory 211200 kb
Host smart-2fc1d1ea-65e1-4c4d-b025-e590b1371698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517678556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3517678556
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2962760799
Short name T19
Test name
Test status
Simulation time 2777833003 ps
CPU time 13.82 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:47:45 PM PST 23
Peak memory 210940 kb
Host smart-32db6ac1-8744-4594-a192-8ba98ced9ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962760799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2962760799
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1943485797
Short name T169
Test name
Test status
Simulation time 8354020736 ps
CPU time 33.05 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 12:48:06 PM PST 23
Peak memory 212984 kb
Host smart-a58dc1d5-6115-4e02-b5f2-e9b019ad1ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943485797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1943485797
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2963897510
Short name T314
Test name
Test status
Simulation time 10432285898 ps
CPU time 60.04 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:48:34 PM PST 23
Peak memory 213144 kb
Host smart-f81f13ec-9721-49bc-9e0e-4317794d9ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963897510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2963897510
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2542233393
Short name T50
Test name
Test status
Simulation time 51503625408 ps
CPU time 1847.11 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 01:18:18 PM PST 23
Peak memory 234016 kb
Host smart-81d072b9-5a60-4715-b9e0-713aff9fc945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542233393 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2542233393
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2814569654
Short name T275
Test name
Test status
Simulation time 23332078817 ps
CPU time 14.77 seconds
Started Dec 24 12:46:28 PM PST 23
Finished Dec 24 12:46:44 PM PST 23
Peak memory 210880 kb
Host smart-7a799b8c-6321-457b-901c-fdf455dfb823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814569654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2814569654
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2165375362
Short name T52
Test name
Test status
Simulation time 176728447915 ps
CPU time 221.41 seconds
Started Dec 24 12:46:21 PM PST 23
Finished Dec 24 12:50:07 PM PST 23
Peak memory 237476 kb
Host smart-46265832-020b-4bf9-83b8-fe2e7a1bedd8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165375362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2165375362
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.834263822
Short name T282
Test name
Test status
Simulation time 831966105 ps
CPU time 9.94 seconds
Started Dec 24 12:46:46 PM PST 23
Finished Dec 24 12:46:58 PM PST 23
Peak memory 211240 kb
Host smart-cfa38ed7-2ad3-4c11-9b09-7f940cba908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834263822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.834263822
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1025375295
Short name T310
Test name
Test status
Simulation time 920975611 ps
CPU time 11.07 seconds
Started Dec 24 12:46:13 PM PST 23
Finished Dec 24 12:46:34 PM PST 23
Peak memory 210752 kb
Host smart-6aaa4dac-dfa6-4b66-af0d-5bd0f4f0be38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025375295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1025375295
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2859042425
Short name T36
Test name
Test status
Simulation time 684010461 ps
CPU time 61.57 seconds
Started Dec 24 12:46:24 PM PST 23
Finished Dec 24 12:47:29 PM PST 23
Peak memory 235816 kb
Host smart-ec807695-97f2-4730-8d7f-784181caf960
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859042425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2859042425
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1634932056
Short name T356
Test name
Test status
Simulation time 14320894939 ps
CPU time 29.48 seconds
Started Dec 24 12:46:23 PM PST 23
Finished Dec 24 12:46:56 PM PST 23
Peak memory 213312 kb
Host smart-b84b8569-deb2-497b-8474-7102ea19efae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634932056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1634932056
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3279605035
Short name T427
Test name
Test status
Simulation time 7714806931 ps
CPU time 74.04 seconds
Started Dec 24 12:46:31 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 215736 kb
Host smart-883f8f3a-f8cb-44f0-a978-a7a36fbac031
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279605035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3279605035
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.3034919817
Short name T358
Test name
Test status
Simulation time 27439216072 ps
CPU time 2043.41 seconds
Started Dec 24 12:46:32 PM PST 23
Finished Dec 24 01:20:38 PM PST 23
Peak memory 235592 kb
Host smart-f68be8b1-329f-4bac-a9ed-b340df50fa8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034919817 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.3034919817
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.691164682
Short name T225
Test name
Test status
Simulation time 15443668451 ps
CPU time 9.58 seconds
Started Dec 24 12:47:34 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 210848 kb
Host smart-b8eec3fd-b226-4a48-ab4b-dd3147cf2f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691164682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.691164682
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1818172547
Short name T257
Test name
Test status
Simulation time 24537290531 ps
CPU time 178.5 seconds
Started Dec 24 12:47:23 PM PST 23
Finished Dec 24 12:50:27 PM PST 23
Peak memory 227816 kb
Host smart-ece318b9-ce05-4898-bff9-7b25e6281569
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818172547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1818172547
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.206667377
Short name T326
Test name
Test status
Simulation time 243581426 ps
CPU time 9.65 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 210924 kb
Host smart-d0f39e5a-ea6d-411f-be29-8e53b672e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206667377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.206667377
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3436448812
Short name T383
Test name
Test status
Simulation time 14285519312 ps
CPU time 17.66 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:49 PM PST 23
Peak memory 210920 kb
Host smart-097603fd-ef3e-4aab-9bb3-ce6648f2b782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436448812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3436448812
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.3956141564
Short name T374
Test name
Test status
Simulation time 10296266842 ps
CPU time 27.07 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:48:01 PM PST 23
Peak memory 212832 kb
Host smart-5ac02a32-8e07-481d-bd2a-04752116b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956141564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3956141564
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2803509818
Short name T318
Test name
Test status
Simulation time 111447691 ps
CPU time 7.71 seconds
Started Dec 24 12:47:25 PM PST 23
Finished Dec 24 12:47:37 PM PST 23
Peak memory 211108 kb
Host smart-92a111e9-45ea-41a9-b2a8-a51603a06ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803509818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2803509818
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2227217057
Short name T243
Test name
Test status
Simulation time 15015546747 ps
CPU time 16.47 seconds
Started Dec 24 12:47:23 PM PST 23
Finished Dec 24 12:47:44 PM PST 23
Peak memory 210892 kb
Host smart-3888e2d3-dde7-4536-add2-eb79443b91ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227217057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2227217057
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2610988025
Short name T51
Test name
Test status
Simulation time 7003119377 ps
CPU time 128.18 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:49:39 PM PST 23
Peak memory 236392 kb
Host smart-719675e6-7242-494c-a5b3-8ca30d0ede4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610988025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2610988025
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2245923777
Short name T21
Test name
Test status
Simulation time 15523197105 ps
CPU time 30.79 seconds
Started Dec 24 12:47:24 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 211348 kb
Host smart-fc22022b-8fd3-4a57-ac9c-84f99f3b0780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245923777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2245923777
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.104516762
Short name T401
Test name
Test status
Simulation time 376808716 ps
CPU time 5.78 seconds
Started Dec 24 12:47:30 PM PST 23
Finished Dec 24 12:47:40 PM PST 23
Peak memory 210868 kb
Host smart-096d01f7-7cc7-47f4-b7d8-d8694f7db87a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104516762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.104516762
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3020715063
Short name T385
Test name
Test status
Simulation time 2151947299 ps
CPU time 26.46 seconds
Started Dec 24 12:47:35 PM PST 23
Finished Dec 24 12:48:05 PM PST 23
Peak memory 212076 kb
Host smart-069e11d6-c577-43e4-b20c-64b897575129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020715063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3020715063
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.275916429
Short name T198
Test name
Test status
Simulation time 70185045157 ps
CPU time 85.93 seconds
Started Dec 24 12:47:24 PM PST 23
Finished Dec 24 12:48:55 PM PST 23
Peak memory 219000 kb
Host smart-758d2329-46e1-4dea-acae-42b3b6c73c8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275916429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.275916429
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.902675817
Short name T286
Test name
Test status
Simulation time 443075231299 ps
CPU time 1542.57 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 01:13:13 PM PST 23
Peak memory 235604 kb
Host smart-e7ee92f5-c1c7-4e5b-b960-d3e944ebbf11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902675817 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.902675817
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3015419901
Short name T346
Test name
Test status
Simulation time 2932138414 ps
CPU time 15.03 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 210992 kb
Host smart-38fd518e-f24b-45b0-a59e-b2458a3fcaf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015419901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3015419901
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1206882115
Short name T201
Test name
Test status
Simulation time 147995679782 ps
CPU time 347.85 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:53:19 PM PST 23
Peak memory 234424 kb
Host smart-1fef44ec-fe3f-4d91-a259-eca8509de7cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206882115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1206882115
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.1897504789
Short name T188
Test name
Test status
Simulation time 3757395507 ps
CPU time 32.84 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:48:08 PM PST 23
Peak memory 210956 kb
Host smart-1fb15df9-a029-4159-859c-c97c5dc58a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897504789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.1897504789
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2409307935
Short name T293
Test name
Test status
Simulation time 739149505 ps
CPU time 7.06 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 210816 kb
Host smart-64ef7d23-e0da-4c59-925c-94d0d5487278
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409307935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2409307935
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2630164653
Short name T424
Test name
Test status
Simulation time 15659415603 ps
CPU time 39.26 seconds
Started Dec 24 12:47:24 PM PST 23
Finished Dec 24 12:48:09 PM PST 23
Peak memory 213540 kb
Host smart-b89b0fef-1733-486e-8802-e967b53ebd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630164653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2630164653
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.63263242
Short name T402
Test name
Test status
Simulation time 4429561979 ps
CPU time 43.96 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:48:14 PM PST 23
Peak memory 214808 kb
Host smart-4fa54819-cfd3-41c7-807b-e467ed1c72fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63263242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 42.rom_ctrl_stress_all.63263242
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.232501529
Short name T236
Test name
Test status
Simulation time 59784114388 ps
CPU time 1006.34 seconds
Started Dec 24 12:47:34 PM PST 23
Finished Dec 24 01:04:24 PM PST 23
Peak memory 227224 kb
Host smart-47ea25c6-143d-4380-b206-8c898feb8e2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232501529 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.232501529
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3730039524
Short name T366
Test name
Test status
Simulation time 416555236 ps
CPU time 4.38 seconds
Started Dec 24 12:47:34 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 210816 kb
Host smart-c7a361b3-ca66-4e90-9889-4e1d891a533a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730039524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3730039524
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3324630238
Short name T352
Test name
Test status
Simulation time 48257423543 ps
CPU time 124.5 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:49:37 PM PST 23
Peak memory 227720 kb
Host smart-400fb489-db4a-4575-a110-9d128d86e174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324630238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3324630238
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3272113086
Short name T312
Test name
Test status
Simulation time 10869249694 ps
CPU time 28.67 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:48:04 PM PST 23
Peak memory 211288 kb
Host smart-ed321ef7-ec76-4783-ba5e-d41f536b4184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272113086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3272113086
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3241184092
Short name T387
Test name
Test status
Simulation time 10138795653 ps
CPU time 14.76 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:47:52 PM PST 23
Peak memory 210844 kb
Host smart-6ae39e18-fe54-4b7c-8844-a1d2a7de6ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241184092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3241184092
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.633788061
Short name T173
Test name
Test status
Simulation time 277495155 ps
CPU time 12.18 seconds
Started Dec 24 12:47:38 PM PST 23
Finished Dec 24 12:47:52 PM PST 23
Peak memory 212484 kb
Host smart-20484b31-7935-4873-972b-139c3b88e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633788061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.633788061
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1965504908
Short name T407
Test name
Test status
Simulation time 1508586505 ps
CPU time 22.91 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:54 PM PST 23
Peak memory 215636 kb
Host smart-d356442c-ef1a-4176-a735-bea2476e281e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965504908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1965504908
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2821208171
Short name T226
Test name
Test status
Simulation time 57229333499 ps
CPU time 8256.94 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 03:05:13 PM PST 23
Peak memory 237332 kb
Host smart-9a9360a3-fadf-491b-95f4-273c600da058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821208171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2821208171
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.149950988
Short name T425
Test name
Test status
Simulation time 3774764281 ps
CPU time 10.08 seconds
Started Dec 24 12:47:36 PM PST 23
Finished Dec 24 12:47:49 PM PST 23
Peak memory 210908 kb
Host smart-d5272946-395a-4319-b1b3-5c9c8c4c71b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149950988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.149950988
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.267301072
Short name T15
Test name
Test status
Simulation time 401008006914 ps
CPU time 309.66 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:52:45 PM PST 23
Peak memory 236296 kb
Host smart-7ef838da-3b1f-4a3c-85e4-ef6b80048c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267301072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_c
orrupt_sig_fatal_chk.267301072
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1001115244
Short name T273
Test name
Test status
Simulation time 14381918449 ps
CPU time 27.15 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:48:02 PM PST 23
Peak memory 211268 kb
Host smart-6a6a973f-6d21-4b5d-91ab-3c74552341f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001115244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1001115244
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2320127885
Short name T322
Test name
Test status
Simulation time 666717509 ps
CPU time 9.54 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:45 PM PST 23
Peak memory 210776 kb
Host smart-ace17b2f-a267-4318-bb09-e35b2d6d9151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320127885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2320127885
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3024704314
Short name T215
Test name
Test status
Simulation time 7545809034 ps
CPU time 23.93 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:59 PM PST 23
Peak memory 213392 kb
Host smart-6d5aafad-7420-4095-a8d8-debd1019e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024704314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3024704314
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.235823888
Short name T221
Test name
Test status
Simulation time 5481889884 ps
CPU time 13.92 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 211524 kb
Host smart-876a056f-8836-4bf0-bc30-824fb108df23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235823888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.235823888
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1009529472
Short name T438
Test name
Test status
Simulation time 116057839565 ps
CPU time 1862.98 seconds
Started Dec 24 12:47:44 PM PST 23
Finished Dec 24 01:18:49 PM PST 23
Peak memory 236920 kb
Host smart-e54ab5ce-de51-445f-9aa7-5893c7212bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009529472 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1009529472
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2776882154
Short name T220
Test name
Test status
Simulation time 9462784234 ps
CPU time 14.8 seconds
Started Dec 24 12:47:41 PM PST 23
Finished Dec 24 12:48:00 PM PST 23
Peak memory 210944 kb
Host smart-92efab17-2629-41c2-b09d-2fdd56903d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776882154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2776882154
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4057561804
Short name T299
Test name
Test status
Simulation time 1714285310 ps
CPU time 107.3 seconds
Started Dec 24 12:47:38 PM PST 23
Finished Dec 24 12:49:27 PM PST 23
Peak memory 237340 kb
Host smart-336b1efb-e31b-4677-b2dd-b86fcc79a279
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057561804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4057561804
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1001371465
Short name T392
Test name
Test status
Simulation time 13602445749 ps
CPU time 29.73 seconds
Started Dec 24 12:47:42 PM PST 23
Finished Dec 24 12:48:15 PM PST 23
Peak memory 211212 kb
Host smart-c2b51484-21e3-4e46-82a6-65d02d131190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001371465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1001371465
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2055638891
Short name T390
Test name
Test status
Simulation time 6956971186 ps
CPU time 17.41 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 12:47:51 PM PST 23
Peak memory 210908 kb
Host smart-2def5408-7ebe-4689-a64f-f015438b4f52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055638891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2055638891
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3251691813
Short name T241
Test name
Test status
Simulation time 183944828 ps
CPU time 10.61 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 212384 kb
Host smart-b1aafab0-6a0f-49ff-94dc-0d526525cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251691813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3251691813
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.1316095499
Short name T235
Test name
Test status
Simulation time 6991199977 ps
CPU time 45.12 seconds
Started Dec 24 12:47:35 PM PST 23
Finished Dec 24 12:48:23 PM PST 23
Peak memory 219064 kb
Host smart-3275f972-02fd-4711-9e5b-75353565e98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316095499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.1316095499
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.77122749
Short name T203
Test name
Test status
Simulation time 377632055 ps
CPU time 4.43 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 210912 kb
Host smart-6b985446-2633-4651-ad05-2ee9f561efea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77122749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.77122749
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2664684769
Short name T430
Test name
Test status
Simulation time 59466464735 ps
CPU time 348.84 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:53:24 PM PST 23
Peak memory 237304 kb
Host smart-5ad23035-9c63-490a-b06f-3acc23afc1d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664684769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2664684769
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.4116162621
Short name T246
Test name
Test status
Simulation time 693490769 ps
CPU time 9.64 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:45 PM PST 23
Peak memory 211008 kb
Host smart-b7fe663d-234e-4a26-856f-2841c1c964c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116162621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.4116162621
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1889897618
Short name T301
Test name
Test status
Simulation time 1241795248 ps
CPU time 12.44 seconds
Started Dec 24 12:47:29 PM PST 23
Finished Dec 24 12:47:46 PM PST 23
Peak memory 210888 kb
Host smart-86b0cb68-5491-4219-9f6d-562023405354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889897618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1889897618
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4243483203
Short name T48
Test name
Test status
Simulation time 542346412 ps
CPU time 11.81 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:48 PM PST 23
Peak memory 211224 kb
Host smart-0396b4ce-6620-4fd7-915e-e309032e8866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243483203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4243483203
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1676803104
Short name T87
Test name
Test status
Simulation time 929446963 ps
CPU time 15.07 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:47:52 PM PST 23
Peak memory 212508 kb
Host smart-b6a1fd8c-998e-4a5a-a179-ef00181b8286
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676803104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1676803104
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.1104571507
Short name T248
Test name
Test status
Simulation time 60216700573 ps
CPU time 935.14 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 01:03:12 PM PST 23
Peak memory 235556 kb
Host smart-0a2aa2a1-3420-4852-a3d4-73278717ee7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104571507 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.1104571507
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3976328651
Short name T389
Test name
Test status
Simulation time 5067522171 ps
CPU time 11.75 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:47:48 PM PST 23
Peak memory 210904 kb
Host smart-f9add0e3-e60b-40d4-8026-89fda00908e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976328651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3976328651
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3686292186
Short name T333
Test name
Test status
Simulation time 285673155937 ps
CPU time 428.55 seconds
Started Dec 24 12:47:42 PM PST 23
Finished Dec 24 12:54:54 PM PST 23
Peak memory 211140 kb
Host smart-1e82d4ea-030e-408e-8b20-03b53b6d9d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686292186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3686292186
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.458614262
Short name T380
Test name
Test status
Simulation time 1970581953 ps
CPU time 13 seconds
Started Dec 24 12:47:35 PM PST 23
Finished Dec 24 12:47:51 PM PST 23
Peak memory 211124 kb
Host smart-dc9f64d0-11dd-4d24-a46c-0a0247753964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458614262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.458614262
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1346354380
Short name T164
Test name
Test status
Simulation time 364297061 ps
CPU time 5.44 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:47:41 PM PST 23
Peak memory 210832 kb
Host smart-582081c5-c2c4-4b63-9495-5a9a5cff5f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1346354380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1346354380
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1831070503
Short name T166
Test name
Test status
Simulation time 6096049643 ps
CPU time 28.76 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:48:05 PM PST 23
Peak memory 213236 kb
Host smart-5db02051-354b-4808-ae26-c59d7d16dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831070503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1831070503
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3514027862
Short name T178
Test name
Test status
Simulation time 45720253148 ps
CPU time 57.93 seconds
Started Dec 24 12:47:32 PM PST 23
Finished Dec 24 12:48:34 PM PST 23
Peak memory 215456 kb
Host smart-2935b918-7dc4-4898-b490-2be7a969c6b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514027862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3514027862
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1908926421
Short name T185
Test name
Test status
Simulation time 52870044878 ps
CPU time 2020.91 seconds
Started Dec 24 12:47:48 PM PST 23
Finished Dec 24 01:21:31 PM PST 23
Peak memory 235580 kb
Host smart-6c4dfeef-b3b0-489b-b9f5-6950cb642101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908926421 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1908926421
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1540055792
Short name T347
Test name
Test status
Simulation time 332741946 ps
CPU time 4.56 seconds
Started Dec 24 12:47:47 PM PST 23
Finished Dec 24 12:47:54 PM PST 23
Peak memory 210724 kb
Host smart-e3d112aa-a11e-4c7f-89e3-5f640b26b0e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540055792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1540055792
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4019419631
Short name T305
Test name
Test status
Simulation time 49240280866 ps
CPU time 162.99 seconds
Started Dec 24 12:47:33 PM PST 23
Finished Dec 24 12:50:20 PM PST 23
Peak memory 236388 kb
Host smart-ed98706b-c05f-4f2d-a58d-f67f94945491
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019419631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4019419631
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1892887339
Short name T317
Test name
Test status
Simulation time 173780658 ps
CPU time 9.74 seconds
Started Dec 24 12:47:48 PM PST 23
Finished Dec 24 12:47:59 PM PST 23
Peak memory 211000 kb
Host smart-a967b36e-66c3-4b55-94af-96b38ae999a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892887339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1892887339
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1738145521
Short name T291
Test name
Test status
Simulation time 6069644300 ps
CPU time 10.01 seconds
Started Dec 24 12:47:31 PM PST 23
Finished Dec 24 12:47:45 PM PST 23
Peak memory 210852 kb
Host smart-84d0ed33-1d57-49fe-93ff-b38f6d5191e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1738145521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1738145521
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1050827302
Short name T218
Test name
Test status
Simulation time 3140689821 ps
CPU time 15.81 seconds
Started Dec 24 12:47:35 PM PST 23
Finished Dec 24 12:47:54 PM PST 23
Peak memory 210908 kb
Host smart-514de12d-57b0-4a4f-952d-6e25f863c936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050827302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1050827302
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.4144841238
Short name T265
Test name
Test status
Simulation time 4896546627 ps
CPU time 50.73 seconds
Started Dec 24 12:47:37 PM PST 23
Finished Dec 24 12:48:30 PM PST 23
Peak memory 215424 kb
Host smart-827a123a-9e28-4765-807d-c352a0b4be7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144841238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.4144841238
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2486378983
Short name T278
Test name
Test status
Simulation time 4614630978 ps
CPU time 11.46 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:47:42 PM PST 23
Peak memory 210272 kb
Host smart-9f8c6e52-7f98-40a9-80ba-599a68af5f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486378983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2486378983
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.3961843370
Short name T338
Test name
Test status
Simulation time 3036129262 ps
CPU time 85.4 seconds
Started Dec 24 12:47:28 PM PST 23
Finished Dec 24 12:48:58 PM PST 23
Peak memory 212216 kb
Host smart-9887fd3c-07df-413b-aa90-daef17dcecb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961843370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.3961843370
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4037244857
Short name T357
Test name
Test status
Simulation time 3949827007 ps
CPU time 34.57 seconds
Started Dec 24 12:47:25 PM PST 23
Finished Dec 24 12:48:04 PM PST 23
Peak memory 210904 kb
Host smart-1c1dcd4d-2bc1-4216-8426-54a0030b7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037244857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4037244857
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1767818017
Short name T4
Test name
Test status
Simulation time 1166666623 ps
CPU time 9.4 seconds
Started Dec 24 12:47:20 PM PST 23
Finished Dec 24 12:47:36 PM PST 23
Peak memory 211060 kb
Host smart-4ff83eaf-0674-4dd9-a518-bcd1fb4ec086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767818017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1767818017
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.340713042
Short name T409
Test name
Test status
Simulation time 2532581566 ps
CPU time 24.37 seconds
Started Dec 24 12:47:47 PM PST 23
Finished Dec 24 12:48:14 PM PST 23
Peak memory 211992 kb
Host smart-e248eff2-3656-4b5b-bdcc-aab6aff65553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340713042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.340713042
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3593175360
Short name T162
Test name
Test status
Simulation time 310700064 ps
CPU time 16.58 seconds
Started Dec 24 12:47:27 PM PST 23
Finished Dec 24 12:47:47 PM PST 23
Peak memory 214144 kb
Host smart-abc55d6a-f62f-4ca3-8c41-a7a606ef61f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593175360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3593175360
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3958342363
Short name T7
Test name
Test status
Simulation time 5963526841 ps
CPU time 542.95 seconds
Started Dec 24 12:47:26 PM PST 23
Finished Dec 24 12:56:33 PM PST 23
Peak memory 221508 kb
Host smart-3d807fa1-a33b-4f72-b84a-0b5ded2d67fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958342363 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3958342363
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2230985677
Short name T190
Test name
Test status
Simulation time 16502708357 ps
CPU time 15.97 seconds
Started Dec 24 12:46:28 PM PST 23
Finished Dec 24 12:46:45 PM PST 23
Peak memory 210912 kb
Host smart-d3dd0a9f-613f-4b7f-8c71-08c168643b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230985677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2230985677
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1561187300
Short name T323
Test name
Test status
Simulation time 105934893496 ps
CPU time 275.41 seconds
Started Dec 24 12:46:11 PM PST 23
Finished Dec 24 12:50:56 PM PST 23
Peak memory 224248 kb
Host smart-5a0216de-5380-46c1-9b70-30c639fcbca8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561187300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1561187300
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3672580911
Short name T372
Test name
Test status
Simulation time 1971047291 ps
CPU time 19.7 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 210996 kb
Host smart-93ee0256-d600-43ab-b05c-8d7553bee3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672580911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3672580911
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1594787897
Short name T249
Test name
Test status
Simulation time 3148285922 ps
CPU time 10.43 seconds
Started Dec 24 12:46:14 PM PST 23
Finished Dec 24 12:46:33 PM PST 23
Peak memory 210844 kb
Host smart-a30fd820-e5a4-4e08-b3b8-97d9fd2b49bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1594787897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1594787897
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.309255448
Short name T13
Test name
Test status
Simulation time 24789808059 ps
CPU time 28.09 seconds
Started Dec 24 12:46:25 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 212920 kb
Host smart-5c780492-195a-4ccc-974c-9358654a7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309255448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.309255448
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2152925901
Short name T167
Test name
Test status
Simulation time 1575247326 ps
CPU time 11.98 seconds
Started Dec 24 12:46:37 PM PST 23
Finished Dec 24 12:46:50 PM PST 23
Peak memory 211208 kb
Host smart-dfb25af3-e147-49b2-a585-6466ffef7866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152925901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2152925901
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2598328896
Short name T39
Test name
Test status
Simulation time 900595818 ps
CPU time 10.39 seconds
Started Dec 24 12:46:28 PM PST 23
Finished Dec 24 12:46:40 PM PST 23
Peak memory 210952 kb
Host smart-929d70ef-fc43-4c61-b53e-8024533e1cba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598328896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2598328896
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1009749446
Short name T379
Test name
Test status
Simulation time 76443840968 ps
CPU time 320.03 seconds
Started Dec 24 12:46:16 PM PST 23
Finished Dec 24 12:51:44 PM PST 23
Peak memory 233612 kb
Host smart-e90ad2ec-d75d-43dd-af6a-4aca02dd2ccc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009749446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1009749446
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3537705180
Short name T17
Test name
Test status
Simulation time 693449636 ps
CPU time 9.75 seconds
Started Dec 24 12:46:20 PM PST 23
Finished Dec 24 12:46:35 PM PST 23
Peak memory 210972 kb
Host smart-e81bebce-7c86-42fb-913f-dc2714e91f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537705180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3537705180
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.266544947
Short name T6
Test name
Test status
Simulation time 161452264 ps
CPU time 5.86 seconds
Started Dec 24 12:46:30 PM PST 23
Finished Dec 24 12:46:37 PM PST 23
Peak memory 210824 kb
Host smart-afd07720-f940-4762-a07b-c4ef40f0e852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266544947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.266544947
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2570816478
Short name T47
Test name
Test status
Simulation time 3794380244 ps
CPU time 31.5 seconds
Started Dec 24 12:46:11 PM PST 23
Finished Dec 24 12:46:52 PM PST 23
Peak memory 212204 kb
Host smart-9b3b4baa-e929-4867-9cbd-4561b8f0d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570816478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2570816478
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.858649987
Short name T363
Test name
Test status
Simulation time 827285343 ps
CPU time 25.39 seconds
Started Dec 24 12:46:25 PM PST 23
Finished Dec 24 12:46:53 PM PST 23
Peak memory 215204 kb
Host smart-28fbc9d1-0c13-45e9-976c-6a2a746dbdba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858649987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.858649987
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.707870152
Short name T398
Test name
Test status
Simulation time 208163455547 ps
CPU time 5974.62 seconds
Started Dec 24 12:46:33 PM PST 23
Finished Dec 24 02:26:10 PM PST 23
Peak memory 244380 kb
Host smart-1f0f6bb5-d0fd-4301-9dba-ec9194936c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707870152 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.707870152
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4172246124
Short name T251
Test name
Test status
Simulation time 755599965 ps
CPU time 4.38 seconds
Started Dec 24 12:46:27 PM PST 23
Finished Dec 24 12:46:33 PM PST 23
Peak memory 210824 kb
Host smart-b812901f-94c2-4735-8ffa-80246a00462b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172246124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4172246124
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3336789296
Short name T202
Test name
Test status
Simulation time 119546278357 ps
CPU time 406.68 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:53:08 PM PST 23
Peak memory 234388 kb
Host smart-bf6f3c54-31f2-4873-8461-e15752467ccf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336789296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3336789296
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1075573220
Short name T175
Test name
Test status
Simulation time 2046100578 ps
CPU time 22.23 seconds
Started Dec 24 12:46:14 PM PST 23
Finished Dec 24 12:46:45 PM PST 23
Peak memory 210880 kb
Host smart-fdaa3136-1d6f-4c00-b18d-af57882fcce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075573220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1075573220
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.186400983
Short name T391
Test name
Test status
Simulation time 1191958475 ps
CPU time 12.43 seconds
Started Dec 24 12:46:22 PM PST 23
Finished Dec 24 12:46:38 PM PST 23
Peak memory 210812 kb
Host smart-ede02256-7068-474e-85a5-81401e8cf9a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=186400983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.186400983
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.452124191
Short name T180
Test name
Test status
Simulation time 1558770273 ps
CPU time 19.59 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 12:46:39 PM PST 23
Peak memory 212476 kb
Host smart-785888f5-fc47-4d38-9de9-54f035978114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452124191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.452124191
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.1035334079
Short name T316
Test name
Test status
Simulation time 428912950 ps
CPU time 25.29 seconds
Started Dec 24 12:46:26 PM PST 23
Finished Dec 24 12:46:53 PM PST 23
Peak memory 215404 kb
Host smart-3fce4fb5-b400-4c49-aeef-783be8cf9d2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035334079 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.1035334079
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3610593761
Short name T377
Test name
Test status
Simulation time 27749856154 ps
CPU time 1262.42 seconds
Started Dec 24 12:46:44 PM PST 23
Finished Dec 24 01:07:48 PM PST 23
Peak memory 227920 kb
Host smart-3c700c30-dbcd-4798-ad6d-daa446f06ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610593761 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3610593761
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4130889808
Short name T403
Test name
Test status
Simulation time 7759615041 ps
CPU time 13.54 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:36 PM PST 23
Peak memory 210972 kb
Host smart-34eda02a-a3f2-47a3-b6fe-35cbf54ab7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130889808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4130889808
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2956544320
Short name T55
Test name
Test status
Simulation time 33736777093 ps
CPU time 197.82 seconds
Started Dec 24 12:46:30 PM PST 23
Finished Dec 24 12:49:50 PM PST 23
Peak memory 233492 kb
Host smart-c14d6599-47dc-4fe0-a56d-1cd796248059
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956544320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2956544320
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.4054599974
Short name T332
Test name
Test status
Simulation time 334251975 ps
CPU time 9.77 seconds
Started Dec 24 12:46:26 PM PST 23
Finished Dec 24 12:46:38 PM PST 23
Peak memory 210908 kb
Host smart-0da68b15-cd84-49d7-8304-d8fa5bbb5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054599974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.4054599974
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.347565963
Short name T410
Test name
Test status
Simulation time 733156186 ps
CPU time 5.93 seconds
Started Dec 24 12:46:24 PM PST 23
Finished Dec 24 12:46:33 PM PST 23
Peak memory 210884 kb
Host smart-eafa71f0-30ff-4579-af2d-de8c9269bca7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347565963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.347565963
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.2269718664
Short name T227
Test name
Test status
Simulation time 5913086378 ps
CPU time 33.08 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 212504 kb
Host smart-20b241ba-c023-4b5d-99d5-7257f3f4b0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269718664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.2269718664
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.2589862062
Short name T426
Test name
Test status
Simulation time 2288754461 ps
CPU time 29.61 seconds
Started Dec 24 12:46:16 PM PST 23
Finished Dec 24 12:46:53 PM PST 23
Peak memory 212384 kb
Host smart-d4d20941-75eb-40c8-bd3b-029b3c973d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589862062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.2589862062
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.202360967
Short name T213
Test name
Test status
Simulation time 16862935087 ps
CPU time 899.41 seconds
Started Dec 24 12:46:10 PM PST 23
Finished Dec 24 01:01:17 PM PST 23
Peak memory 227288 kb
Host smart-5a0c973d-e8ab-4358-a726-47f08c06c9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202360967 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.202360967
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4103698136
Short name T399
Test name
Test status
Simulation time 1754751340 ps
CPU time 14.21 seconds
Started Dec 24 12:46:23 PM PST 23
Finished Dec 24 12:46:41 PM PST 23
Peak memory 210872 kb
Host smart-37132239-fc98-47f9-b36a-6c86b615c7af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103698136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4103698136
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.4158205606
Short name T315
Test name
Test status
Simulation time 16125553099 ps
CPU time 273.76 seconds
Started Dec 24 12:46:15 PM PST 23
Finished Dec 24 12:50:57 PM PST 23
Peak memory 236364 kb
Host smart-e5459387-4677-433e-a6c7-6ae304e3129c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158205606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.4158205606
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.688327919
Short name T367
Test name
Test status
Simulation time 2540607021 ps
CPU time 25.83 seconds
Started Dec 24 12:46:28 PM PST 23
Finished Dec 24 12:46:55 PM PST 23
Peak memory 211008 kb
Host smart-838ce15a-1ada-4707-a29a-7df125a9b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688327919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.688327919
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3359694975
Short name T176
Test name
Test status
Simulation time 3065525385 ps
CPU time 13.87 seconds
Started Dec 24 12:46:11 PM PST 23
Finished Dec 24 12:46:34 PM PST 23
Peak memory 210924 kb
Host smart-7a89ca30-07e1-42f9-9d76-b43cba052455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359694975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3359694975
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1912159039
Short name T222
Test name
Test status
Simulation time 4010641285 ps
CPU time 23.04 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:46:45 PM PST 23
Peak memory 212672 kb
Host smart-afd90254-801a-49a7-8925-8bf9e583161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912159039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1912159039
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3513317395
Short name T395
Test name
Test status
Simulation time 8008497211 ps
CPU time 55.85 seconds
Started Dec 24 12:46:12 PM PST 23
Finished Dec 24 12:47:18 PM PST 23
Peak memory 216512 kb
Host smart-1a64b5f5-e762-464c-ac89-d53af83573eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513317395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3513317395
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.982892693
Short name T328
Test name
Test status
Simulation time 20544912454 ps
CPU time 400.57 seconds
Started Dec 24 12:46:24 PM PST 23
Finished Dec 24 12:53:08 PM PST 23
Peak memory 227272 kb
Host smart-b64f8fa5-47b8-4751-8a27-04eef87396f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982892693 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.982892693
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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