Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.60 97.11 92.68 97.88 100.00 98.37 97.89 99.30


Total test records in report: 482
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html
T269 /workspace/coverage/default/5.rom_ctrl_alert_test.3502396272 Dec 27 12:26:22 PM PST 23 Dec 27 12:26:52 PM PST 23 2106474244 ps
T270 /workspace/coverage/default/18.rom_ctrl_alert_test.2265678539 Dec 27 12:24:34 PM PST 23 Dec 27 12:24:49 PM PST 23 1660109139 ps
T271 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2265240924 Dec 27 12:27:27 PM PST 23 Dec 27 01:04:41 PM PST 23 81465222105 ps
T17 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.71022004 Dec 27 12:25:43 PM PST 23 Dec 27 12:38:19 PM PST 23 45276856283 ps
T272 /workspace/coverage/default/17.rom_ctrl_stress_all.3392095885 Dec 27 12:25:16 PM PST 23 Dec 27 12:25:36 PM PST 23 651800388 ps
T273 /workspace/coverage/default/14.rom_ctrl_alert_test.2838756137 Dec 27 12:28:12 PM PST 23 Dec 27 12:28:57 PM PST 23 174917779 ps
T274 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1172695428 Dec 27 12:26:00 PM PST 23 Dec 27 12:26:35 PM PST 23 57373440126 ps
T275 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1305535468 Dec 27 12:21:24 PM PST 23 Dec 27 12:24:52 PM PST 23 65867109639 ps
T276 /workspace/coverage/default/1.rom_ctrl_smoke.4318943 Dec 27 12:25:14 PM PST 23 Dec 27 12:25:28 PM PST 23 725894413 ps
T277 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4134835250 Dec 27 12:24:46 PM PST 23 Dec 27 12:25:03 PM PST 23 1698513964 ps
T278 /workspace/coverage/default/45.rom_ctrl_stress_all.3163279416 Dec 27 12:26:51 PM PST 23 Dec 27 12:27:24 PM PST 23 213123476 ps
T43 /workspace/coverage/default/2.rom_ctrl_sec_cm.2524944815 Dec 27 12:24:55 PM PST 23 Dec 27 12:26:56 PM PST 23 21438847296 ps
T279 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2141318648 Dec 27 12:26:26 PM PST 23 Dec 27 12:27:51 PM PST 23 4573958444 ps
T280 /workspace/coverage/default/31.rom_ctrl_stress_all.1922101586 Dec 27 12:25:42 PM PST 23 Dec 27 12:26:07 PM PST 23 2012604868 ps
T281 /workspace/coverage/default/19.rom_ctrl_stress_all.4253516708 Dec 27 12:24:33 PM PST 23 Dec 27 12:25:16 PM PST 23 9906331728 ps
T282 /workspace/coverage/default/4.rom_ctrl_alert_test.3306652628 Dec 27 12:27:16 PM PST 23 Dec 27 12:27:47 PM PST 23 691503090 ps
T283 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.702949011 Dec 27 12:28:52 PM PST 23 Dec 27 12:33:31 PM PST 23 84326385887 ps
T284 /workspace/coverage/default/35.rom_ctrl_stress_all.754328607 Dec 27 12:27:44 PM PST 23 Dec 27 12:28:30 PM PST 23 565033811 ps
T285 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1737898012 Dec 27 12:26:17 PM PST 23 Dec 27 12:30:55 PM PST 23 54268061672 ps
T286 /workspace/coverage/default/10.rom_ctrl_smoke.2523281416 Dec 27 12:27:18 PM PST 23 Dec 27 12:27:55 PM PST 23 745941771 ps
T287 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2932447490 Dec 27 12:29:10 PM PST 23 Dec 27 12:30:30 PM PST 23 6013562595 ps
T288 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3758096929 Dec 27 12:28:39 PM PST 23 Dec 27 12:29:46 PM PST 23 18666968111 ps
T289 /workspace/coverage/default/42.rom_ctrl_smoke.1169708977 Dec 27 12:25:07 PM PST 23 Dec 27 12:25:19 PM PST 23 185163052 ps
T290 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1036083769 Dec 27 12:26:47 PM PST 23 Dec 27 12:27:14 PM PST 23 1889550665 ps
T291 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3409507571 Dec 27 12:28:51 PM PST 23 Dec 27 12:30:14 PM PST 23 3570175801 ps
T292 /workspace/coverage/default/19.rom_ctrl_alert_test.4183332122 Dec 27 12:25:29 PM PST 23 Dec 27 12:25:41 PM PST 23 89724497 ps
T293 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1233220246 Dec 27 12:26:00 PM PST 23 Dec 27 12:26:39 PM PST 23 15603345489 ps
T294 /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2826687245 Dec 27 12:26:33 PM PST 23 Dec 27 12:27:20 PM PST 23 8070734965 ps
T295 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2687948537 Dec 27 12:28:39 PM PST 23 Dec 27 12:34:50 PM PST 23 24447727317 ps
T296 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2011238923 Dec 27 12:25:38 PM PST 23 Dec 27 12:26:16 PM PST 23 7840302811 ps
T297 /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2092480137 Dec 27 12:27:44 PM PST 23 Dec 27 01:06:18 PM PST 23 203010286048 ps
T298 /workspace/coverage/default/37.rom_ctrl_alert_test.1490492292 Dec 27 12:22:11 PM PST 23 Dec 27 12:22:23 PM PST 23 1025097459 ps
T299 /workspace/coverage/default/45.rom_ctrl_alert_test.1838202250 Dec 27 12:20:21 PM PST 23 Dec 27 12:20:36 PM PST 23 2032661544 ps
T300 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2454309445 Dec 27 12:24:46 PM PST 23 Dec 27 12:25:03 PM PST 23 4842479982 ps
T301 /workspace/coverage/default/9.rom_ctrl_smoke.2274374328 Dec 27 12:25:23 PM PST 23 Dec 27 12:26:07 PM PST 23 13539855662 ps
T302 /workspace/coverage/default/19.rom_ctrl_smoke.959590362 Dec 27 12:28:56 PM PST 23 Dec 27 12:30:00 PM PST 23 361966904 ps
T303 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1325458706 Dec 27 12:28:16 PM PST 23 Dec 27 12:29:12 PM PST 23 1740731854 ps
T304 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.191856100 Dec 27 12:25:13 PM PST 23 Dec 27 12:25:33 PM PST 23 3405495275 ps
T305 /workspace/coverage/default/33.rom_ctrl_alert_test.1376737723 Dec 27 12:27:11 PM PST 23 Dec 27 12:27:45 PM PST 23 676199898 ps
T306 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3814145858 Dec 27 12:28:14 PM PST 23 Dec 27 12:29:08 PM PST 23 6320468187 ps
T307 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.896837432 Dec 27 12:20:27 PM PST 23 Dec 27 12:48:40 PM PST 23 101290032142 ps
T308 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3235247552 Dec 27 12:28:29 PM PST 23 Dec 27 12:34:00 PM PST 23 93407996703 ps
T309 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.754756959 Dec 27 12:26:55 PM PST 23 Dec 27 12:27:25 PM PST 23 692726366 ps
T310 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3812677651 Dec 27 12:26:56 PM PST 23 Dec 27 12:27:33 PM PST 23 1933587811 ps
T311 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2991619510 Dec 27 12:25:20 PM PST 23 Dec 27 12:26:05 PM PST 23 4163790800 ps
T312 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3145888730 Dec 27 12:26:54 PM PST 23 Dec 27 12:27:47 PM PST 23 11080910970 ps
T313 /workspace/coverage/default/4.rom_ctrl_stress_all.665156787 Dec 27 12:26:31 PM PST 23 Dec 27 12:27:25 PM PST 23 16262489512 ps
T314 /workspace/coverage/default/11.rom_ctrl_stress_all.3116846771 Dec 27 12:21:29 PM PST 23 Dec 27 12:21:51 PM PST 23 969878870 ps
T315 /workspace/coverage/default/3.rom_ctrl_alert_test.537882744 Dec 27 12:24:38 PM PST 23 Dec 27 12:24:53 PM PST 23 5857517907 ps
T316 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3035180337 Dec 27 12:27:35 PM PST 23 Dec 27 12:33:22 PM PST 23 33413068973 ps
T317 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2684644868 Dec 27 12:26:38 PM PST 23 Dec 27 12:27:12 PM PST 23 5000831484 ps
T318 /workspace/coverage/default/15.rom_ctrl_alert_test.1355796337 Dec 27 12:22:23 PM PST 23 Dec 27 12:22:30 PM PST 23 294359250 ps
T319 /workspace/coverage/default/39.rom_ctrl_smoke.3293018172 Dec 27 12:28:54 PM PST 23 Dec 27 12:30:07 PM PST 23 17696537121 ps
T320 /workspace/coverage/default/5.rom_ctrl_stress_all.2159203105 Dec 27 12:28:29 PM PST 23 Dec 27 12:29:29 PM PST 23 648612043 ps
T321 /workspace/coverage/default/32.rom_ctrl_smoke.129321867 Dec 27 12:26:55 PM PST 23 Dec 27 12:27:51 PM PST 23 6015890755 ps
T322 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2649732666 Dec 27 12:27:19 PM PST 23 Dec 27 12:28:07 PM PST 23 8239945117 ps
T323 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2914416436 Dec 27 12:25:21 PM PST 23 Dec 27 12:25:41 PM PST 23 1006365777 ps
T324 /workspace/coverage/default/1.rom_ctrl_alert_test.259473541 Dec 27 12:26:31 PM PST 23 Dec 27 12:26:58 PM PST 23 5786936592 ps
T325 /workspace/coverage/default/44.rom_ctrl_smoke.147411658 Dec 27 12:25:58 PM PST 23 Dec 27 12:26:27 PM PST 23 2468961147 ps
T326 /workspace/coverage/default/31.rom_ctrl_alert_test.1071020598 Dec 27 12:26:55 PM PST 23 Dec 27 12:27:30 PM PST 23 1797505687 ps
T327 /workspace/coverage/default/49.rom_ctrl_alert_test.2932961322 Dec 27 12:24:47 PM PST 23 Dec 27 12:24:57 PM PST 23 683636829 ps
T328 /workspace/coverage/default/24.rom_ctrl_stress_all.4193409441 Dec 27 12:28:13 PM PST 23 Dec 27 12:29:15 PM PST 23 2102293652 ps
T329 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.386763315 Dec 27 12:24:47 PM PST 23 Dec 27 12:25:01 PM PST 23 1082500605 ps
T330 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3270040754 Dec 27 12:26:21 PM PST 23 Dec 27 12:35:55 PM PST 23 75875252879 ps
T331 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3582032874 Dec 27 12:28:05 PM PST 23 Dec 27 12:28:51 PM PST 23 1654593471 ps
T332 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2129965538 Dec 27 12:26:00 PM PST 23 Dec 27 12:31:23 PM PST 23 34192636888 ps
T333 /workspace/coverage/default/15.rom_ctrl_smoke.959092879 Dec 27 12:27:53 PM PST 23 Dec 27 12:28:59 PM PST 23 3255327872 ps
T334 /workspace/coverage/default/17.rom_ctrl_smoke.3855230057 Dec 27 12:28:40 PM PST 23 Dec 27 12:30:08 PM PST 23 3831134891 ps
T335 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.794708069 Dec 27 12:26:26 PM PST 23 Dec 27 12:28:34 PM PST 23 2675179487 ps
T336 /workspace/coverage/default/22.rom_ctrl_smoke.1457796791 Dec 27 12:28:16 PM PST 23 Dec 27 12:29:16 PM PST 23 2957369296 ps
T337 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.642427109 Dec 27 12:21:20 PM PST 23 Dec 27 12:21:26 PM PST 23 96239323 ps
T45 /workspace/coverage/default/1.rom_ctrl_sec_cm.2941683915 Dec 27 12:25:13 PM PST 23 Dec 27 12:26:18 PM PST 23 2732361064 ps
T338 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1432138181 Dec 27 12:25:29 PM PST 23 Dec 27 12:49:09 PM PST 23 57697770007 ps
T339 /workspace/coverage/default/8.rom_ctrl_smoke.651927049 Dec 27 12:21:20 PM PST 23 Dec 27 12:21:40 PM PST 23 5982818931 ps
T340 /workspace/coverage/default/36.rom_ctrl_smoke.2310621708 Dec 27 12:25:20 PM PST 23 Dec 27 12:26:03 PM PST 23 6714527745 ps
T46 /workspace/coverage/default/3.rom_ctrl_sec_cm.1383358040 Dec 27 12:21:53 PM PST 23 Dec 27 12:23:00 PM PST 23 1759591178 ps
T341 /workspace/coverage/default/29.rom_ctrl_stress_all.3619954040 Dec 27 12:22:23 PM PST 23 Dec 27 12:23:52 PM PST 23 104526869171 ps
T342 /workspace/coverage/default/5.rom_ctrl_smoke.1476228111 Dec 27 12:28:25 PM PST 23 Dec 27 12:29:41 PM PST 23 3019944913 ps
T343 /workspace/coverage/default/46.rom_ctrl_alert_test.1019500390 Dec 27 12:27:57 PM PST 23 Dec 27 12:28:42 PM PST 23 9154071319 ps
T344 /workspace/coverage/default/16.rom_ctrl_smoke.3151136103 Dec 27 12:25:40 PM PST 23 Dec 27 12:26:23 PM PST 23 3505783244 ps
T345 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2201719312 Dec 27 12:27:27 PM PST 23 Dec 27 12:28:05 PM PST 23 627762793 ps
T346 /workspace/coverage/default/3.rom_ctrl_smoke.1450125986 Dec 27 12:24:55 PM PST 23 Dec 27 12:25:08 PM PST 23 187921752 ps
T347 /workspace/coverage/default/49.rom_ctrl_smoke.2653103761 Dec 27 12:24:48 PM PST 23 Dec 27 12:25:01 PM PST 23 1059213309 ps
T348 /workspace/coverage/default/11.rom_ctrl_alert_test.3930057009 Dec 27 12:27:27 PM PST 23 Dec 27 12:28:10 PM PST 23 8259172234 ps
T349 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3071398308 Dec 27 12:28:37 PM PST 23 Dec 27 12:29:51 PM PST 23 11677627621 ps
T350 /workspace/coverage/default/23.rom_ctrl_alert_test.3465271788 Dec 27 12:28:09 PM PST 23 Dec 27 12:28:56 PM PST 23 4684651609 ps
T351 /workspace/coverage/default/12.rom_ctrl_alert_test.96746967 Dec 27 12:27:28 PM PST 23 Dec 27 12:28:00 PM PST 23 333848661 ps
T352 /workspace/coverage/default/14.rom_ctrl_stress_all.4094443508 Dec 27 12:28:59 PM PST 23 Dec 27 12:30:05 PM PST 23 111928898 ps
T353 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4238743036 Dec 27 12:26:22 PM PST 23 Dec 27 12:26:47 PM PST 23 945623292 ps
T354 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2533371231 Dec 27 12:24:48 PM PST 23 Dec 27 12:26:29 PM PST 23 10309608594 ps
T355 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3383078291 Dec 27 12:20:56 PM PST 23 Dec 27 12:27:37 PM PST 23 39647240691 ps
T356 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1205515274 Dec 27 12:28:42 PM PST 23 Dec 27 12:29:43 PM PST 23 695924694 ps
T357 /workspace/coverage/default/34.rom_ctrl_smoke.2488002213 Dec 27 12:26:55 PM PST 23 Dec 27 12:27:26 PM PST 23 262835809 ps
T113 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1390139439 Dec 27 12:26:32 PM PST 23 Dec 27 12:54:46 PM PST 23 47420756027 ps
T112 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1517227601 Dec 27 12:25:35 PM PST 23 Dec 27 01:45:32 PM PST 23 317097521153 ps
T358 /workspace/coverage/default/28.rom_ctrl_alert_test.1140841188 Dec 27 12:25:21 PM PST 23 Dec 27 12:25:39 PM PST 23 826505122 ps
T359 /workspace/coverage/default/44.rom_ctrl_stress_all.79377033 Dec 27 12:25:58 PM PST 23 Dec 27 12:27:42 PM PST 23 31492438761 ps
T360 /workspace/coverage/default/10.rom_ctrl_stress_all.4288005014 Dec 27 12:28:40 PM PST 23 Dec 27 12:30:07 PM PST 23 3680260272 ps
T361 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.130454551 Dec 27 12:26:53 PM PST 23 Dec 27 12:27:31 PM PST 23 12911785349 ps
T362 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2368220633 Dec 27 12:28:51 PM PST 23 Dec 27 12:31:50 PM PST 23 3802893036 ps
T363 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1899805971 Dec 27 12:28:17 PM PST 23 Dec 27 12:29:09 PM PST 23 175775429 ps
T364 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3702170810 Dec 27 12:26:17 PM PST 23 Dec 27 12:26:43 PM PST 23 4480764139 ps
T365 /workspace/coverage/default/47.rom_ctrl_alert_test.2924498046 Dec 27 12:26:51 PM PST 23 Dec 27 12:27:25 PM PST 23 5235423292 ps
T366 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1401152454 Dec 27 12:28:02 PM PST 23 Dec 27 12:28:53 PM PST 23 2130262301 ps
T367 /workspace/coverage/default/25.rom_ctrl_smoke.3554047138 Dec 27 12:26:57 PM PST 23 Dec 27 12:27:47 PM PST 23 2398588349 ps
T368 /workspace/coverage/default/28.rom_ctrl_stress_all.2215577683 Dec 27 12:20:08 PM PST 23 Dec 27 12:20:54 PM PST 23 6784521320 ps
T369 /workspace/coverage/default/27.rom_ctrl_alert_test.2467570137 Dec 27 12:25:18 PM PST 23 Dec 27 12:25:33 PM PST 23 175737974 ps
T370 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2528350563 Dec 27 12:26:18 PM PST 23 Dec 27 12:30:33 PM PST 23 20245846040 ps
T371 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2527568804 Dec 27 12:29:25 PM PST 23 Dec 27 12:30:45 PM PST 23 10852662093 ps
T372 /workspace/coverage/default/6.rom_ctrl_alert_test.1888156986 Dec 27 12:25:22 PM PST 23 Dec 27 12:25:38 PM PST 23 292684890 ps
T373 /workspace/coverage/default/48.rom_ctrl_stress_all.3292912854 Dec 27 12:24:58 PM PST 23 Dec 27 12:25:24 PM PST 23 6907093790 ps
T374 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4230695443 Dec 27 12:25:21 PM PST 23 Dec 27 12:30:15 PM PST 23 192258624434 ps
T375 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2454836924 Dec 27 12:21:45 PM PST 23 Dec 27 12:22:21 PM PST 23 18094776970 ps
T376 /workspace/coverage/default/21.rom_ctrl_alert_test.1896484644 Dec 27 12:20:08 PM PST 23 Dec 27 12:20:21 PM PST 23 1175128412 ps
T377 /workspace/coverage/default/6.rom_ctrl_stress_all.3819199088 Dec 27 12:25:15 PM PST 23 Dec 27 12:25:37 PM PST 23 218449743 ps
T378 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2664812643 Dec 27 12:25:21 PM PST 23 Dec 27 12:26:53 PM PST 23 5753950127 ps
T379 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1144042632 Dec 27 12:25:21 PM PST 23 Dec 27 12:25:37 PM PST 23 182859237 ps
T380 /workspace/coverage/default/1.rom_ctrl_stress_all.2572260799 Dec 27 12:25:29 PM PST 23 Dec 27 12:25:53 PM PST 23 1928847075 ps
T381 /workspace/coverage/default/43.rom_ctrl_alert_test.2396585015 Dec 27 12:25:59 PM PST 23 Dec 27 12:26:17 PM PST 23 1447512538 ps
T382 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2239326531 Dec 27 12:21:37 PM PST 23 Dec 27 12:21:45 PM PST 23 965012641 ps
T383 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3346289191 Dec 27 12:25:09 PM PST 23 Dec 27 12:26:54 PM PST 23 28631653071 ps
T384 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1982140752 Dec 27 12:26:21 PM PST 23 Dec 27 12:56:48 PM PST 23 78245877308 ps
T385 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2221151770 Dec 27 12:27:32 PM PST 23 Dec 27 12:39:57 PM PST 23 57589995236 ps
T386 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2983098362 Dec 27 12:22:40 PM PST 23 Dec 27 12:47:09 PM PST 23 80922392326 ps
T387 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2234371283 Dec 27 12:26:30 PM PST 23 Dec 27 12:31:25 PM PST 23 65644180084 ps
T388 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.375213528 Dec 27 12:26:51 PM PST 23 Dec 27 02:01:29 PM PST 23 36251692270 ps
T389 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.255976656 Dec 27 12:26:55 PM PST 23 Dec 27 12:33:00 PM PST 23 130150169725 ps
T390 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1689185286 Dec 27 12:25:22 PM PST 23 Dec 27 12:25:56 PM PST 23 2302167465 ps
T391 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1474470406 Dec 27 12:28:10 PM PST 23 Dec 27 12:28:55 PM PST 23 379284175 ps
T392 /workspace/coverage/default/46.rom_ctrl_stress_all.160392584 Dec 27 12:27:43 PM PST 23 Dec 27 12:28:21 PM PST 23 183842792 ps
T393 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1977438941 Dec 27 12:28:53 PM PST 23 Dec 27 12:29:57 PM PST 23 666648550 ps
T394 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1705788062 Dec 27 12:25:20 PM PST 23 Dec 27 12:25:39 PM PST 23 835969865 ps
T395 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2684015202 Dec 27 12:28:09 PM PST 23 Dec 27 12:28:58 PM PST 23 12959461458 ps
T396 /workspace/coverage/default/0.rom_ctrl_alert_test.982774648 Dec 27 12:26:51 PM PST 23 Dec 27 12:27:23 PM PST 23 4104831332 ps
T397 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3901943855 Dec 27 12:26:26 PM PST 23 Dec 27 12:34:16 PM PST 23 171208604403 ps
T398 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.930407083 Dec 27 12:26:17 PM PST 23 Dec 27 12:26:40 PM PST 23 475469330 ps
T399 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.576600711 Dec 27 12:28:53 PM PST 23 Dec 27 01:06:02 PM PST 23 102388259811 ps
T400 /workspace/coverage/default/37.rom_ctrl_stress_all.1517036415 Dec 27 12:27:16 PM PST 23 Dec 27 12:28:03 PM PST 23 1700157626 ps
T401 /workspace/coverage/default/35.rom_ctrl_alert_test.187833072 Dec 27 12:25:20 PM PST 23 Dec 27 12:25:36 PM PST 23 684310489 ps
T402 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3965375631 Dec 27 12:26:53 PM PST 23 Dec 27 12:27:38 PM PST 23 2449255964 ps
T403 /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4106266247 Dec 27 12:29:14 PM PST 23 Dec 27 12:34:52 PM PST 23 19682448626 ps
T404 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2802830105 Dec 27 12:25:18 PM PST 23 Dec 27 12:33:05 PM PST 23 192694151472 ps
T405 /workspace/coverage/default/20.rom_ctrl_smoke.181401756 Dec 27 12:28:43 PM PST 23 Dec 27 12:30:02 PM PST 23 2912951253 ps
T406 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2074894913 Dec 27 12:25:59 PM PST 23 Dec 27 12:30:53 PM PST 23 110114076840 ps
T407 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1291639555 Dec 27 12:24:55 PM PST 23 Dec 27 12:25:13 PM PST 23 2118020701 ps
T408 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1161551780 Dec 27 12:25:59 PM PST 23 Dec 27 12:26:14 PM PST 23 177466041 ps
T409 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2864554014 Dec 27 12:29:14 PM PST 23 Dec 27 12:30:21 PM PST 23 1362271090 ps
T410 /workspace/coverage/default/48.rom_ctrl_alert_test.2887108979 Dec 27 12:21:31 PM PST 23 Dec 27 12:21:47 PM PST 23 1682897004 ps
T411 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.63630882 Dec 27 12:21:45 PM PST 23 Dec 27 12:38:38 PM PST 23 146924351832 ps
T412 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4019314954 Dec 27 12:25:08 PM PST 23 Dec 27 12:25:33 PM PST 23 2267553370 ps
T413 /workspace/coverage/default/8.rom_ctrl_alert_test.2456268566 Dec 27 12:26:46 PM PST 23 Dec 27 12:27:18 PM PST 23 4575208556 ps
T414 /workspace/coverage/default/12.rom_ctrl_smoke.3168330227 Dec 27 12:21:01 PM PST 23 Dec 27 12:21:39 PM PST 23 3549198232 ps
T415 /workspace/coverage/default/23.rom_ctrl_stress_all.3731350718 Dec 27 12:25:21 PM PST 23 Dec 27 12:25:51 PM PST 23 4280975480 ps
T416 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3036850029 Dec 27 12:25:18 PM PST 23 Dec 27 12:25:53 PM PST 23 39751764459 ps
T417 /workspace/coverage/default/20.rom_ctrl_stress_all.675317804 Dec 27 12:28:18 PM PST 23 Dec 27 12:29:11 PM PST 23 779799934 ps
T418 /workspace/coverage/default/16.rom_ctrl_stress_all.2652844095 Dec 27 12:39:04 PM PST 23 Dec 27 12:39:39 PM PST 23 3814825781 ps
T419 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.743994601 Dec 27 12:28:14 PM PST 23 Dec 27 12:29:05 PM PST 23 516038280 ps
T420 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2506851160 Dec 27 12:22:21 PM PST 23 Dec 27 12:22:33 PM PST 23 7918515943 ps
T421 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2433073622 Dec 27 12:24:51 PM PST 23 Dec 27 01:24:32 PM PST 23 160651782649 ps
T422 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1816305419 Dec 27 12:20:22 PM PST 23 Dec 27 12:20:55 PM PST 23 7559249478 ps
T423 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.603824534 Dec 27 12:20:20 PM PST 23 Dec 27 12:20:54 PM PST 23 5929535128 ps
T424 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.875670458 Dec 27 12:26:40 PM PST 23 Dec 27 12:27:13 PM PST 23 1553353723 ps
T425 /workspace/coverage/default/36.rom_ctrl_alert_test.1508868287 Dec 27 12:21:18 PM PST 23 Dec 27 12:21:35 PM PST 23 7733064846 ps
T426 /workspace/coverage/default/25.rom_ctrl_alert_test.3735515030 Dec 27 12:28:35 PM PST 23 Dec 27 12:29:38 PM PST 23 6009354336 ps
T427 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2049374730 Dec 27 12:27:17 PM PST 23 Dec 27 01:30:25 PM PST 23 113360949838 ps
T428 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3878967788 Dec 27 12:28:45 PM PST 23 Dec 27 02:05:17 PM PST 23 369917913525 ps
T429 /workspace/coverage/default/29.rom_ctrl_alert_test.3184986718 Dec 27 12:28:15 PM PST 23 Dec 27 12:29:12 PM PST 23 8075699224 ps
T430 /workspace/coverage/default/49.rom_ctrl_stress_all.638358777 Dec 27 12:27:43 PM PST 23 Dec 27 12:28:43 PM PST 23 32426177694 ps
T431 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3103075315 Dec 27 12:29:00 PM PST 23 Dec 27 12:30:04 PM PST 23 527868785 ps
T432 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1342688925 Dec 27 12:29:03 PM PST 23 Dec 27 12:32:42 PM PST 23 6640822374 ps
T118 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2012424713 Dec 27 12:32:01 PM PST 23 Dec 27 12:34:06 PM PST 23 6577137150 ps
T433 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.42550695 Dec 27 12:29:57 PM PST 23 Dec 27 12:30:53 PM PST 23 100274870 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2969325230 Dec 27 12:30:05 PM PST 23 Dec 27 12:34:02 PM PST 23 45194329638 ps
T435 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.251082563 Dec 27 12:30:17 PM PST 23 Dec 27 12:31:50 PM PST 23 702108575 ps
T436 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.133677234 Dec 27 12:30:28 PM PST 23 Dec 27 12:31:35 PM PST 23 4737262510 ps
T437 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2756473221 Dec 27 12:30:03 PM PST 23 Dec 27 12:31:11 PM PST 23 16168381098 ps
T99 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.810637003 Dec 27 12:29:35 PM PST 23 Dec 27 12:33:38 PM PST 23 70395792568 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.155034462 Dec 27 12:30:23 PM PST 23 Dec 27 12:31:34 PM PST 23 17967686908 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1140934815 Dec 27 12:30:25 PM PST 23 Dec 27 12:31:34 PM PST 23 6321806300 ps
T439 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1534683773 Dec 27 12:32:13 PM PST 23 Dec 27 12:33:08 PM PST 23 1101060871 ps
T440 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3092775139 Dec 27 12:30:02 PM PST 23 Dec 27 12:31:03 PM PST 23 153464507 ps
T441 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2780867320 Dec 27 12:30:15 PM PST 23 Dec 27 12:31:21 PM PST 23 9884886432 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3705099990 Dec 27 12:29:22 PM PST 23 Dec 27 12:30:33 PM PST 23 2119119581 ps
T443 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1622390408 Dec 27 12:30:01 PM PST 23 Dec 27 12:32:41 PM PST 23 53764986959 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3826133621 Dec 27 12:29:33 PM PST 23 Dec 27 12:30:33 PM PST 23 103889047 ps
T445 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3010467995 Dec 27 12:29:55 PM PST 23 Dec 27 12:31:01 PM PST 23 7564673713 ps
T446 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.69531715 Dec 27 12:29:39 PM PST 23 Dec 27 12:30:48 PM PST 23 27234647494 ps
T447 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1269097170 Dec 27 12:31:28 PM PST 23 Dec 27 12:33:34 PM PST 23 2765715599 ps
T448 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2541765814 Dec 27 12:30:11 PM PST 23 Dec 27 12:31:21 PM PST 23 8672563976 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3651689773 Dec 27 12:30:21 PM PST 23 Dec 27 12:31:22 PM PST 23 835932011 ps
T92 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3388631762 Dec 27 12:29:33 PM PST 23 Dec 27 12:33:27 PM PST 23 105610743153 ps
T450 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.931569125 Dec 27 12:29:32 PM PST 23 Dec 27 12:30:40 PM PST 23 6732825292 ps
T101 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3784076447 Dec 27 12:29:11 PM PST 23 Dec 27 12:30:18 PM PST 23 391019147 ps
T93 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3598887533 Dec 27 12:30:14 PM PST 23 Dec 27 12:31:14 PM PST 23 1885698631 ps
T451 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1237405521 Dec 27 12:29:43 PM PST 23 Dec 27 12:30:53 PM PST 23 2115143299 ps
T452 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4180579635 Dec 27 12:29:18 PM PST 23 Dec 27 12:31:38 PM PST 23 12361357169 ps
T453 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3013156400 Dec 27 12:29:43 PM PST 23 Dec 27 12:30:46 PM PST 23 994479450 ps
T454 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3067331851 Dec 27 12:29:56 PM PST 23 Dec 27 12:31:02 PM PST 23 4317512903 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42689628 Dec 27 12:30:14 PM PST 23 Dec 27 12:31:22 PM PST 23 1888582194 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2544038988 Dec 27 12:29:34 PM PST 23 Dec 27 12:30:43 PM PST 23 1247051257 ps
T457 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4276632814 Dec 27 12:30:39 PM PST 23 Dec 27 12:31:40 PM PST 23 108118306 ps
T458 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3951971154 Dec 27 12:29:36 PM PST 23 Dec 27 12:30:47 PM PST 23 7775342713 ps
T102 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2493018573 Dec 27 12:29:18 PM PST 23 Dec 27 12:30:19 PM PST 23 307896507 ps
T459 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2636333936 Dec 27 12:29:30 PM PST 23 Dec 27 12:30:37 PM PST 23 1472266937 ps
T119 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3411374820 Dec 27 12:31:32 PM PST 23 Dec 27 12:33:38 PM PST 23 305934934 ps
T460 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1143869099 Dec 27 12:29:37 PM PST 23 Dec 27 12:31:21 PM PST 23 5051873863 ps
T120 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3900607964 Dec 27 12:31:27 PM PST 23 Dec 27 12:33:01 PM PST 23 3356403359 ps
T461 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1810952494 Dec 27 12:29:42 PM PST 23 Dec 27 12:30:53 PM PST 23 1802753047 ps
T94 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2286580554 Dec 27 12:29:34 PM PST 23 Dec 27 12:30:40 PM PST 23 2525647296 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1383897183 Dec 27 12:30:25 PM PST 23 Dec 27 12:33:31 PM PST 23 10736664049 ps
T463 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.365970095 Dec 27 12:29:36 PM PST 23 Dec 27 12:30:40 PM PST 23 3301157143 ps
T464 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3052701443 Dec 27 12:30:21 PM PST 23 Dec 27 12:31:28 PM PST 23 943336345 ps
T465 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2113738575 Dec 27 12:29:40 PM PST 23 Dec 27 12:30:44 PM PST 23 7221148197 ps
T466 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1758262542 Dec 27 12:31:36 PM PST 23 Dec 27 12:32:44 PM PST 23 27734840842 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2730217330 Dec 27 12:29:31 PM PST 23 Dec 27 12:30:35 PM PST 23 1301987562 ps
T468 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2836954265 Dec 27 12:30:12 PM PST 23 Dec 27 12:31:15 PM PST 23 1758757072 ps
T100 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1943317565 Dec 27 12:29:51 PM PST 23 Dec 27 12:32:16 PM PST 23 6448257241 ps
T469 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.991310317 Dec 27 12:31:13 PM PST 23 Dec 27 12:32:18 PM PST 23 1698052004 ps
T470 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1314461757 Dec 27 12:29:44 PM PST 23 Dec 27 12:31:27 PM PST 23 6476473924 ps
T471 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.927508382 Dec 27 12:29:23 PM PST 23 Dec 27 12:31:32 PM PST 23 1240323710 ps
T472 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4207692442 Dec 27 12:29:46 PM PST 23 Dec 27 12:30:48 PM PST 23 959819738 ps
T473 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.393823947 Dec 27 12:32:21 PM PST 23 Dec 27 12:33:11 PM PST 23 6462032306 ps
T474 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3474879853 Dec 27 12:29:39 PM PST 23 Dec 27 12:30:42 PM PST 23 2685477689 ps
T475 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622331164 Dec 27 12:29:44 PM PST 23 Dec 27 12:30:54 PM PST 23 1296630815 ps
T476 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2424611585 Dec 27 12:29:50 PM PST 23 Dec 27 12:30:46 PM PST 23 86432396 ps
T477 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2061977020 Dec 27 12:29:48 PM PST 23 Dec 27 12:30:53 PM PST 23 6452691251 ps
T478 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1138109637 Dec 27 12:32:08 PM PST 23 Dec 27 12:33:46 PM PST 23 7715869255 ps
T479 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2156093058 Dec 27 12:30:23 PM PST 23 Dec 27 12:31:32 PM PST 23 5263854267 ps
T480 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4086674512 Dec 27 12:30:21 PM PST 23 Dec 27 12:31:29 PM PST 23 2528113131 ps
T481 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3403251421 Dec 27 12:30:22 PM PST 23 Dec 27 12:31:24 PM PST 23 434694203 ps
T103 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.391065223 Dec 27 12:29:42 PM PST 23 Dec 27 12:33:14 PM PST 23 13070799579 ps
T482 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.113065696 Dec 27 12:29:33 PM PST 23 Dec 27 12:33:59 PM PST 23 76354897552 ps

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1881395288
Short name T32
Test name
Test status
Simulation time 2366061953 ps
CPU time 12.52 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 219336 kb
Host smart-d2189d87-9051-416f-a8cc-2daf2419db74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881395288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1881395288
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3069593851
Short name T2
Test name
Test status
Simulation time 13667336811 ps
CPU time 481.05 seconds
Started Dec 27 12:29:07 PM PST 23
Finished Dec 27 12:38:08 PM PST 23
Peak memory 227228 kb
Host smart-5fae919b-fec3-4f45-aa68-5f0936a41fd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069593851 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3069593851
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3711873718
Short name T36
Test name
Test status
Simulation time 122950280148 ps
CPU time 269.61 seconds
Started Dec 27 12:29:17 PM PST 23
Finished Dec 27 12:34:41 PM PST 23
Peak memory 211160 kb
Host smart-610c5b9f-1d7e-4506-ad34-62062c115fc8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711873718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3711873718
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.1751403945
Short name T61
Test name
Test status
Simulation time 309605261 ps
CPU time 76.52 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 212632 kb
Host smart-c28c0410-52df-4ff9-9069-e682237f9fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751403945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.1751403945
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.701742553
Short name T6
Test name
Test status
Simulation time 42527992958 ps
CPU time 153.52 seconds
Started Dec 27 12:26:35 PM PST 23
Finished Dec 27 12:29:25 PM PST 23
Peak memory 224000 kb
Host smart-cc67390e-5410-49cb-89d1-d6f79d77932d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701742553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.701742553
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1859220972
Short name T66
Test name
Test status
Simulation time 1646925483 ps
CPU time 16.33 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 219288 kb
Host smart-e0d1a6e6-fe2e-4bc1-beb7-395052ddf14a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859220972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1859220972
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2281827152
Short name T5
Test name
Test status
Simulation time 4560410142 ps
CPU time 17.05 seconds
Started Dec 27 12:26:52 PM PST 23
Finished Dec 27 12:27:29 PM PST 23
Peak memory 212884 kb
Host smart-3f9c240f-ab9b-4e33-a432-e4c67d6cf377
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281827152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2281827152
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.522820268
Short name T31
Test name
Test status
Simulation time 2386850901 ps
CPU time 127.24 seconds
Started Dec 27 12:19:28 PM PST 23
Finished Dec 27 12:21:36 PM PST 23
Peak memory 237268 kb
Host smart-1d07861f-9870-468a-8437-85c64fcd85dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522820268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.522820268
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.810637003
Short name T99
Test name
Test status
Simulation time 70395792568 ps
CPU time 189.09 seconds
Started Dec 27 12:29:35 PM PST 23
Finished Dec 27 12:33:38 PM PST 23
Peak memory 211164 kb
Host smart-fea9be42-4f28-45de-b4aa-ffdae4688a33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810637003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.810637003
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2104400851
Short name T60
Test name
Test status
Simulation time 8542790224 ps
CPU time 83.34 seconds
Started Dec 27 12:30:04 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 211848 kb
Host smart-0d74a9fe-a47d-4af6-bbb5-ca8c68033e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104400851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2104400851
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2920497260
Short name T63
Test name
Test status
Simulation time 1299336256 ps
CPU time 12.2 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 214368 kb
Host smart-ea929651-514b-4458-a2f4-15147f7c6c68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920497260 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2920497260
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3967129069
Short name T16
Test name
Test status
Simulation time 194673319016 ps
CPU time 1608.84 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:54:42 PM PST 23
Peak memory 235436 kb
Host smart-7798711f-8679-477f-b5dc-4cd759e9bce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967129069 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3967129069
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.4013147181
Short name T25
Test name
Test status
Simulation time 167150362683 ps
CPU time 391.95 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:33:09 PM PST 23
Peak memory 227624 kb
Host smart-5ca4e4dc-7dbb-4174-bdf0-25c751e164ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013147181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.4013147181
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3554707445
Short name T116
Test name
Test status
Simulation time 1017358550 ps
CPU time 43.2 seconds
Started Dec 27 12:30:02 PM PST 23
Finished Dec 27 12:31:37 PM PST 23
Peak memory 212300 kb
Host smart-755a8efc-ada1-4beb-afcd-add29b0fb09c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554707445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3554707445
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.896061350
Short name T23
Test name
Test status
Simulation time 254420953 ps
CPU time 9.7 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:25:41 PM PST 23
Peak memory 209760 kb
Host smart-749168ac-a3d9-4c9f-bc05-9089b0990cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896061350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.896061350
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.170693723
Short name T176
Test name
Test status
Simulation time 9770856141 ps
CPU time 24.84 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:27:11 PM PST 23
Peak memory 210208 kb
Host smart-d5e8d870-ec0d-453c-9778-cf049ad6e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170693723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.170693723
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1627748603
Short name T74
Test name
Test status
Simulation time 19199794005 ps
CPU time 184.55 seconds
Started Dec 27 12:29:32 PM PST 23
Finished Dec 27 12:33:32 PM PST 23
Peak memory 211148 kb
Host smart-c7a6a629-4041-4726-b45c-9f59a6dc6038
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627748603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1627748603
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.1929527831
Short name T21
Test name
Test status
Simulation time 861514768 ps
CPU time 7.05 seconds
Started Dec 27 12:27:04 PM PST 23
Finished Dec 27 12:27:35 PM PST 23
Peak memory 209680 kb
Host smart-6d7ff72b-11c0-4519-83aa-b7b2ccf86015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929527831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1929527831
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2012424713
Short name T118
Test name
Test status
Simulation time 6577137150 ps
CPU time 79.48 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:34:06 PM PST 23
Peak memory 211412 kb
Host smart-37a90a36-fcfe-43d0-a84a-95dc28531305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012424713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2012424713
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4013120649
Short name T111
Test name
Test status
Simulation time 482869546 ps
CPU time 8.39 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:27 PM PST 23
Peak memory 219368 kb
Host smart-81403e0b-956b-4137-932f-37ef0630c6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013120649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4013120649
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.1390139439
Short name T113
Test name
Test status
Simulation time 47420756027 ps
CPU time 1678.89 seconds
Started Dec 27 12:26:32 PM PST 23
Finished Dec 27 12:54:46 PM PST 23
Peak memory 235380 kb
Host smart-7433b580-363d-4912-ab78-ce6e90396bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390139439 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.1390139439
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4223723677
Short name T97
Test name
Test status
Simulation time 7320541517 ps
CPU time 15.28 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 211264 kb
Host smart-3901a655-e0e4-48bb-a139-b56215c7c0a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223723677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4223723677
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3598887533
Short name T93
Test name
Test status
Simulation time 1885698631 ps
CPU time 7.23 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:31:14 PM PST 23
Peak memory 211096 kb
Host smart-66bd3e10-ee29-4dd6-b02a-4f6a4fbf845a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598887533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3598887533
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.365970095
Short name T463
Test name
Test status
Simulation time 3301157143 ps
CPU time 9.64 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211224 kb
Host smart-a3705ebb-dad0-4303-98bb-c6f0b1f0f285
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365970095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_b
ash.365970095
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3784076447
Short name T101
Test name
Test status
Simulation time 391019147 ps
CPU time 7.66 seconds
Started Dec 27 12:29:11 PM PST 23
Finished Dec 27 12:30:18 PM PST 23
Peak memory 211072 kb
Host smart-79472c70-21da-4ea1-98c7-1394e52555ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784076447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3784076447
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1534683773
Short name T439
Test name
Test status
Simulation time 1101060871 ps
CPU time 10.97 seconds
Started Dec 27 12:32:13 PM PST 23
Finished Dec 27 12:33:08 PM PST 23
Peak memory 214460 kb
Host smart-b1faf1fd-492d-4a74-9ac2-e28566a6f360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534683773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1534683773
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1355758527
Short name T89
Test name
Test status
Simulation time 333474072 ps
CPU time 4.23 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:30:10 PM PST 23
Peak memory 211112 kb
Host smart-553ba4f9-2ab6-4224-a5c1-bfb23f3475e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355758527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1355758527
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3010467995
Short name T445
Test name
Test status
Simulation time 7564673713 ps
CPU time 14.03 seconds
Started Dec 27 12:29:55 PM PST 23
Finished Dec 27 12:31:01 PM PST 23
Peak memory 211248 kb
Host smart-f9906e5f-df17-4534-a36b-8e5a3ba86725
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010467995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3010467995
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2544038988
Short name T456
Test name
Test status
Simulation time 1247051257 ps
CPU time 11.23 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 211068 kb
Host smart-752384df-4927-4c81-88e4-26707a0de69c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544038988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.2544038988
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4207692442
Short name T472
Test name
Test status
Simulation time 959819738 ps
CPU time 9.86 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 210936 kb
Host smart-af10aee8-97e2-4466-83e6-16c93c2f9bbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207692442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4207692442
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1760617462
Short name T109
Test name
Test status
Simulation time 178806082 ps
CPU time 6.15 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:30:32 PM PST 23
Peak memory 219324 kb
Host smart-0fbe57be-f07d-4c29-a6ce-04df2c83bdfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760617462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1760617462
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1402961716
Short name T96
Test name
Test status
Simulation time 1526632727 ps
CPU time 80.6 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 211304 kb
Host smart-8564fa7c-9c0a-4cca-a753-330a2d70a392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402961716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1402961716
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1497734856
Short name T129
Test name
Test status
Simulation time 754124979 ps
CPU time 4.38 seconds
Started Dec 27 12:29:32 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 211088 kb
Host smart-80686e36-a60d-42bd-a0f6-653611aef1ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497734856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1497734856
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1087948945
Short name T143
Test name
Test status
Simulation time 1253889620 ps
CPU time 11.44 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 211180 kb
Host smart-270d4bde-ca81-49f0-ac49-38028af82f1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087948945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1087948945
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1647289520
Short name T62
Test name
Test status
Simulation time 918445483 ps
CPU time 9.79 seconds
Started Dec 27 12:29:41 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 212288 kb
Host smart-d940ee15-3e61-4596-9dfb-0976937a5c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647289520 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1647289520
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2634032037
Short name T124
Test name
Test status
Simulation time 1472638761 ps
CPU time 12.73 seconds
Started Dec 27 12:30:10 PM PST 23
Finished Dec 27 12:31:15 PM PST 23
Peak memory 211064 kb
Host smart-5730118a-463a-450f-8120-1e5e38950336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634032037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2634032037
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.450888551
Short name T138
Test name
Test status
Simulation time 85497783 ps
CPU time 4.19 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 211116 kb
Host smart-b3351267-c7cd-4b2e-9899-91cea78fd74b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450888551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.450888551
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2780867320
Short name T441
Test name
Test status
Simulation time 9884886432 ps
CPU time 12.52 seconds
Started Dec 27 12:30:15 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 211156 kb
Host smart-6d9e044d-d61f-402d-81c6-0d46d4bb6f6d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780867320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2780867320
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3812813910
Short name T77
Test name
Test status
Simulation time 2840709838 ps
CPU time 69.8 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:31:42 PM PST 23
Peak memory 211232 kb
Host smart-95a6e22e-96b8-4bca-a9e6-2f2295dd4948
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812813910 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3812813910
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3826133621
Short name T444
Test name
Test status
Simulation time 103889047 ps
CPU time 5.99 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:30:33 PM PST 23
Peak memory 211100 kb
Host smart-dafc5cdb-2376-4b27-a322-bbcef04c8c98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826133621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.3826133621
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3056424695
Short name T139
Test name
Test status
Simulation time 1226998255 ps
CPU time 13.99 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 219312 kb
Host smart-eb0a98e0-30ec-40ba-9fc2-9b66d51fea9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056424695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3056424695
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2908328338
Short name T117
Test name
Test status
Simulation time 2885243879 ps
CPU time 78.35 seconds
Started Dec 27 12:30:02 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 211332 kb
Host smart-67a8f928-ed0b-4676-9ab3-3a1768ba050d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908328338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2908328338
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1537506127
Short name T33
Test name
Test status
Simulation time 5294079806 ps
CPU time 12.37 seconds
Started Dec 27 12:29:41 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 215984 kb
Host smart-58b15cf2-5787-45eb-852e-5f4b1b57547d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537506127 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1537506127
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.385873873
Short name T87
Test name
Test status
Simulation time 1596808910 ps
CPU time 12.31 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 211084 kb
Host smart-92f3fa7c-cc10-418a-8b29-dc5d5c94cca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385873873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.385873873
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2886394192
Short name T105
Test name
Test status
Simulation time 362812495 ps
CPU time 4.15 seconds
Started Dec 27 12:32:09 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 210872 kb
Host smart-de67d77d-bab6-45f7-a061-2deff581b1c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886394192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2886394192
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1660502340
Short name T83
Test name
Test status
Simulation time 989765418 ps
CPU time 77.91 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 211500 kb
Host smart-4c9d7e29-71b8-4de2-b87f-bb43247c6338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660502340 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1660502340
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2043093147
Short name T68
Test name
Test status
Simulation time 2312276764 ps
CPU time 11.42 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 215584 kb
Host smart-1bc831c1-5f04-4c3a-a0b7-6a0b4b1b66cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043093147 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2043093147
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2271136396
Short name T134
Test name
Test status
Simulation time 12807779044 ps
CPU time 10.9 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:34 PM PST 23
Peak memory 211112 kb
Host smart-1e08f0f9-1f0e-4665-ba26-216fd04e19c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271136396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2271136396
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3388631762
Short name T92
Test name
Test status
Simulation time 105610743153 ps
CPU time 179.52 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:33:27 PM PST 23
Peak memory 211180 kb
Host smart-4d2c51a2-89f8-42fa-91c2-b8ba50d8d378
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388631762 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3388631762
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2775444108
Short name T127
Test name
Test status
Simulation time 447071626 ps
CPU time 6.18 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 211224 kb
Host smart-102a46f6-bb82-4a87-ab11-63173c217886
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775444108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2775444108
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.659654960
Short name T121
Test name
Test status
Simulation time 10562589229 ps
CPU time 18.42 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 219396 kb
Host smart-121e8a10-fdea-42e4-8a11-a6d7a35ccff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659654960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.659654960
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.787825612
Short name T122
Test name
Test status
Simulation time 3449715090 ps
CPU time 14.26 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 215620 kb
Host smart-81f45419-e27e-4841-b6a1-f9de15c78366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787825612 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.787825612
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3886107547
Short name T98
Test name
Test status
Simulation time 631936568 ps
CPU time 5.37 seconds
Started Dec 27 12:30:09 PM PST 23
Finished Dec 27 12:31:06 PM PST 23
Peak memory 211080 kb
Host smart-bc34b348-f2ca-4180-b158-bab6973965b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886107547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3886107547
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.113065696
Short name T482
Test name
Test status
Simulation time 76354897552 ps
CPU time 211.39 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:33:59 PM PST 23
Peak memory 211180 kb
Host smart-1e6a1e16-23ad-4b5b-9044-c46efd3a48d2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113065696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.113065696
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.393823947
Short name T473
Test name
Test status
Simulation time 6462032306 ps
CPU time 7.43 seconds
Started Dec 27 12:32:21 PM PST 23
Finished Dec 27 12:33:11 PM PST 23
Peak memory 211164 kb
Host smart-0be68b65-d96e-45f6-a2be-8247e6c9eefe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393823947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.393823947
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.991310317
Short name T469
Test name
Test status
Simulation time 1698052004 ps
CPU time 15.7 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:18 PM PST 23
Peak memory 216664 kb
Host smart-83f5a589-a379-49e1-95f7-4e218303785f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991310317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.991310317
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3411374820
Short name T119
Test name
Test status
Simulation time 305934934 ps
CPU time 74.96 seconds
Started Dec 27 12:31:32 PM PST 23
Finished Dec 27 12:33:38 PM PST 23
Peak memory 212208 kb
Host smart-e70bf3cd-522e-4b59-83d9-edae2dd98aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411374820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3411374820
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2836954265
Short name T468
Test name
Test status
Simulation time 1758757072 ps
CPU time 9.46 seconds
Started Dec 27 12:30:12 PM PST 23
Finished Dec 27 12:31:15 PM PST 23
Peak memory 212584 kb
Host smart-57294610-4ae9-4ad9-9fff-a903ad9a9650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836954265 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2836954265
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.3270502068
Short name T133
Test name
Test status
Simulation time 7003419888 ps
CPU time 13.51 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 211196 kb
Host smart-4d62e41f-5411-41da-9072-542e4d4ab750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270502068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.3270502068
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3257254519
Short name T75
Test name
Test status
Simulation time 27276333717 ps
CPU time 107.05 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 211092 kb
Host smart-e75c06e2-958c-4c64-aa55-250a1a387df4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257254519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3257254519
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2061977020
Short name T477
Test name
Test status
Simulation time 6452691251 ps
CPU time 13.51 seconds
Started Dec 27 12:29:48 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 211184 kb
Host smart-97b90bf2-4633-4f5f-a3fb-4a72a07e895b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061977020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2061977020
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1810952494
Short name T461
Test name
Test status
Simulation time 1802753047 ps
CPU time 17.84 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 219256 kb
Host smart-e51dc00e-ea01-4a3f-883c-44a59071492f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810952494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1810952494
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3900607964
Short name T120
Test name
Test status
Simulation time 3356403359 ps
CPU time 43.94 seconds
Started Dec 27 12:31:27 PM PST 23
Finished Dec 27 12:33:01 PM PST 23
Peak memory 211796 kb
Host smart-12878418-b248-46c3-8689-35af15489f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900607964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3900607964
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4276632814
Short name T457
Test name
Test status
Simulation time 108118306 ps
CPU time 4.72 seconds
Started Dec 27 12:30:39 PM PST 23
Finished Dec 27 12:31:40 PM PST 23
Peak memory 211968 kb
Host smart-47cb2c30-901a-4dd3-897d-b9f378bdc2f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276632814 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4276632814
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2540388617
Short name T91
Test name
Test status
Simulation time 1809653979 ps
CPU time 13.84 seconds
Started Dec 27 12:31:30 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 210824 kb
Host smart-5e2ab4ad-195b-4d11-ac24-6125a81a9b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540388617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2540388617
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4107990576
Short name T79
Test name
Test status
Simulation time 77271493808 ps
CPU time 176.19 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:34:59 PM PST 23
Peak memory 208952 kb
Host smart-27e71ecf-dba1-4cf5-b2a2-8083a199f52a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107990576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4107990576
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1434112436
Short name T40
Test name
Test status
Simulation time 700358470 ps
CPU time 8.38 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 211144 kb
Host smart-f2a05724-13ec-460e-b7ac-9bd205110566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434112436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1434112436
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1758262542
Short name T466
Test name
Test status
Simulation time 27734840842 ps
CPU time 16.31 seconds
Started Dec 27 12:31:36 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 219100 kb
Host smart-4c43565b-1424-4339-b6fd-2ce978568722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758262542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1758262542
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2816739572
Short name T64
Test name
Test status
Simulation time 8206658272 ps
CPU time 13.03 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:30 PM PST 23
Peak memory 214480 kb
Host smart-a6fe8dae-0c4b-459b-a9d1-9974d315e545
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816739572 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2816739572
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1467172331
Short name T69
Test name
Test status
Simulation time 3783303065 ps
CPU time 14.77 seconds
Started Dec 27 12:29:55 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 211140 kb
Host smart-ac79f62d-bd7b-4ca6-aca2-fa2f50e9ce7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467172331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1467172331
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.912303111
Short name T37
Test name
Test status
Simulation time 14059875575 ps
CPU time 155.58 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:33:53 PM PST 23
Peak memory 211224 kb
Host smart-a2e5c11c-82ab-41b1-94da-f022d9a00462
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912303111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.912303111
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2424611585
Short name T476
Test name
Test status
Simulation time 86432396 ps
CPU time 4.26 seconds
Started Dec 27 12:29:50 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 211056 kb
Host smart-b4bc5cba-01f6-486b-9aff-ad08b65c2588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424611585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2424611585
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2636333936
Short name T459
Test name
Test status
Simulation time 1472266937 ps
CPU time 13.24 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 219312 kb
Host smart-42de992a-5138-4b07-8e95-77924d1dfe13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636333936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2636333936
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1269097170
Short name T447
Test name
Test status
Simulation time 2765715599 ps
CPU time 75.5 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:33:34 PM PST 23
Peak memory 211292 kb
Host smart-d85415e0-4a6b-4a61-854b-93ba212af9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269097170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1269097170
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3067331851
Short name T454
Test name
Test status
Simulation time 4317512903 ps
CPU time 13.93 seconds
Started Dec 27 12:29:56 PM PST 23
Finished Dec 27 12:31:02 PM PST 23
Peak memory 216488 kb
Host smart-99395dde-b77a-49b8-a99b-3ede373cb0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067331851 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3067331851
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4086674512
Short name T480
Test name
Test status
Simulation time 2528113131 ps
CPU time 11.47 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 211132 kb
Host smart-989a5479-4cb2-4c28-bb8b-538c7ca5ab19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086674512 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4086674512
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2113738575
Short name T465
Test name
Test status
Simulation time 7221148197 ps
CPU time 10.81 seconds
Started Dec 27 12:29:40 PM PST 23
Finished Dec 27 12:30:44 PM PST 23
Peak memory 211224 kb
Host smart-1c39a2b8-9acc-4ce3-84fd-2741718e50c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113738575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2113738575
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.35350424
Short name T110
Test name
Test status
Simulation time 1622919597 ps
CPU time 7.58 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 216752 kb
Host smart-1f3609e2-bcb3-4a56-8533-c2819c7b7d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35350424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.35350424
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.251082563
Short name T435
Test name
Test status
Simulation time 702108575 ps
CPU time 38.75 seconds
Started Dec 27 12:30:17 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 212092 kb
Host smart-4fcd7047-78ca-41a3-b901-7575901bc9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251082563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.251082563
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3644741105
Short name T35
Test name
Test status
Simulation time 1301506960 ps
CPU time 12.3 seconds
Started Dec 27 12:30:10 PM PST 23
Finished Dec 27 12:31:14 PM PST 23
Peak memory 214568 kb
Host smart-2c0bd843-c155-407f-9693-641a45f6a7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644741105 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3644741105
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1889415708
Short name T86
Test name
Test status
Simulation time 1901199217 ps
CPU time 14.86 seconds
Started Dec 27 12:30:19 PM PST 23
Finished Dec 27 12:31:29 PM PST 23
Peak memory 211100 kb
Host smart-962a3ee5-f280-4726-a066-a76fee32d92e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889415708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1889415708
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.391065223
Short name T103
Test name
Test status
Simulation time 13070799579 ps
CPU time 158.98 seconds
Started Dec 27 12:29:42 PM PST 23
Finished Dec 27 12:33:14 PM PST 23
Peak memory 211168 kb
Host smart-d400a388-e899-4b0e-aeb2-c0eff9b04740
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391065223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.391065223
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1540716611
Short name T73
Test name
Test status
Simulation time 2344089649 ps
CPU time 9.23 seconds
Started Dec 27 12:30:03 PM PST 23
Finished Dec 27 12:31:04 PM PST 23
Peak memory 211224 kb
Host smart-ce3ffd73-180b-4a84-95ee-de174148872c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540716611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1540716611
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.56880673
Short name T140
Test name
Test status
Simulation time 99952427 ps
CPU time 7.2 seconds
Started Dec 27 12:29:58 PM PST 23
Finished Dec 27 12:30:57 PM PST 23
Peak memory 219320 kb
Host smart-409ca56c-141c-4900-972e-b8a911ad3ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56880673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.56880673
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1143869099
Short name T460
Test name
Test status
Simulation time 5051873863 ps
CPU time 49.77 seconds
Started Dec 27 12:29:37 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 212440 kb
Host smart-90f41a94-7735-4447-9278-4af0e62f023d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143869099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1143869099
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2721938928
Short name T67
Test name
Test status
Simulation time 97762073 ps
CPU time 5.29 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 219328 kb
Host smart-6833cdce-1f3a-40b1-aa02-5050cf99fc0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721938928 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2721938928
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.2156093058
Short name T479
Test name
Test status
Simulation time 5263854267 ps
CPU time 11.79 seconds
Started Dec 27 12:30:23 PM PST 23
Finished Dec 27 12:31:32 PM PST 23
Peak memory 211248 kb
Host smart-c5c0cc12-8f4b-4ba9-ae92-d9419bb6ca54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156093058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.2156093058
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1314461757
Short name T470
Test name
Test status
Simulation time 6476473924 ps
CPU time 50.06 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:31:27 PM PST 23
Peak memory 211276 kb
Host smart-3c0e3a06-ceef-4854-93ae-6bd2abe01233
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314461757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1314461757
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3474879853
Short name T474
Test name
Test status
Simulation time 2685477689 ps
CPU time 8.26 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 211176 kb
Host smart-e9445fda-54b2-42c6-b487-daeea1cc6f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474879853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3474879853
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.622331164
Short name T475
Test name
Test status
Simulation time 1296630815 ps
CPU time 13.68 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:30:54 PM PST 23
Peak memory 219364 kb
Host smart-7d382ca5-49ad-48aa-a4d9-fa5ab67981f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622331164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.622331164
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.69531715
Short name T446
Test name
Test status
Simulation time 27234647494 ps
CPU time 14.68 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:30:48 PM PST 23
Peak memory 216228 kb
Host smart-cc25581d-076b-49b4-98a2-3ed2ad3782de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69531715 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.69531715
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1376053498
Short name T71
Test name
Test status
Simulation time 1126429951 ps
CPU time 7.15 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 211192 kb
Host smart-cddba686-0dfa-4227-a42d-98444dbd0bc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376053498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1376053498
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2969325230
Short name T434
Test name
Test status
Simulation time 45194329638 ps
CPU time 185.79 seconds
Started Dec 27 12:30:05 PM PST 23
Finished Dec 27 12:34:02 PM PST 23
Peak memory 211104 kb
Host smart-e2cc3070-fba0-495e-ab05-58e77220d8dc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969325230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2969325230
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1995457293
Short name T130
Test name
Test status
Simulation time 1365624884 ps
CPU time 14.19 seconds
Started Dec 27 12:29:59 PM PST 23
Finished Dec 27 12:31:05 PM PST 23
Peak memory 211116 kb
Host smart-13c6335b-4c94-41ce-ba52-cd18d630eafd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995457293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1995457293
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3577771023
Short name T65
Test name
Test status
Simulation time 86659106 ps
CPU time 6.15 seconds
Started Dec 27 12:29:40 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 213792 kb
Host smart-1965958e-bc85-4c8e-8c6f-48a55bcbea5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577771023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3577771023
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3408097640
Short name T34
Test name
Test status
Simulation time 1744276542 ps
CPU time 47.55 seconds
Started Dec 27 12:29:44 PM PST 23
Finished Dec 27 12:31:25 PM PST 23
Peak memory 212340 kb
Host smart-5e87c506-d94e-4daf-ac0b-f43e3cfdf310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408097640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3408097640
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1217697601
Short name T88
Test name
Test status
Simulation time 828273260 ps
CPU time 4.17 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 211064 kb
Host smart-939c1359-b7e7-4b0b-a17f-56b2074ee78b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217697601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1217697601
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3052701443
Short name T464
Test name
Test status
Simulation time 943336345 ps
CPU time 10.11 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:28 PM PST 23
Peak memory 211112 kb
Host smart-5bc98179-7516-48b0-9742-379a4388b186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052701443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3052701443
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1787357237
Short name T90
Test name
Test status
Simulation time 1955377942 ps
CPU time 16.65 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 211176 kb
Host smart-aeb3b6ae-157e-45d5-aa26-107187663b64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787357237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1787357237
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3874501293
Short name T142
Test name
Test status
Simulation time 797812621 ps
CPU time 7.53 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:25 PM PST 23
Peak memory 214632 kb
Host smart-c4be540e-1789-4ce7-91b1-3494d2b1984d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874501293 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3874501293
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3225587074
Short name T72
Test name
Test status
Simulation time 1050409687 ps
CPU time 10.01 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:30:29 PM PST 23
Peak memory 211064 kb
Host smart-079e6858-68a4-491c-acae-961af396f079
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225587074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3225587074
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.982624698
Short name T132
Test name
Test status
Simulation time 13495289695 ps
CPU time 9.83 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211164 kb
Host smart-12d80b90-ca99-4070-ae78-bd83671c47ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982624698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl
_mem_partial_access.982624698
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3705099990
Short name T442
Test name
Test status
Simulation time 2119119581 ps
CPU time 15.81 seconds
Started Dec 27 12:29:22 PM PST 23
Finished Dec 27 12:30:33 PM PST 23
Peak memory 211108 kb
Host smart-f5d0fd6c-84e3-4964-b94f-ab2981ebb79c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705099990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3705099990
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1440655206
Short name T39
Test name
Test status
Simulation time 9796137904 ps
CPU time 11.6 seconds
Started Dec 27 12:30:25 PM PST 23
Finished Dec 27 12:31:33 PM PST 23
Peak memory 211232 kb
Host smart-ff68df95-464b-4797-a3e2-39f922e78956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440655206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1440655206
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2541765814
Short name T448
Test name
Test status
Simulation time 8672563976 ps
CPU time 16.49 seconds
Started Dec 27 12:30:11 PM PST 23
Finished Dec 27 12:31:21 PM PST 23
Peak memory 219404 kb
Host smart-5457dd93-325a-48c1-b273-d23e84b0a597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541765814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2541765814
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.4180579635
Short name T452
Test name
Test status
Simulation time 12361357169 ps
CPU time 84.08 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:31:38 PM PST 23
Peak memory 211800 kb
Host smart-8563bc21-7653-4b1e-897d-c80ecbc45b48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180579635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.4180579635
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2286580554
Short name T94
Test name
Test status
Simulation time 2525647296 ps
CPU time 11.35 seconds
Started Dec 27 12:29:34 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211128 kb
Host smart-0bf73a83-ada4-4eb1-bed5-0887d3cd7762
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286580554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2286580554
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.133677234
Short name T436
Test name
Test status
Simulation time 4737262510 ps
CPU time 10.67 seconds
Started Dec 27 12:30:28 PM PST 23
Finished Dec 27 12:31:35 PM PST 23
Peak memory 211124 kb
Host smart-11aa69bb-0278-4a1c-8c98-3c305fec419e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133677234 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.133677234
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1237405521
Short name T451
Test name
Test status
Simulation time 2115143299 ps
CPU time 17.41 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 211168 kb
Host smart-1554968b-10df-42fc-b86a-1a61bdadd7a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237405521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1237405521
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3403251421
Short name T481
Test name
Test status
Simulation time 434694203 ps
CPU time 5.44 seconds
Started Dec 27 12:30:22 PM PST 23
Finished Dec 27 12:31:24 PM PST 23
Peak memory 214324 kb
Host smart-b7dd11df-4241-4da4-a054-1d608024e719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403251421 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3403251421
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1140934815
Short name T95
Test name
Test status
Simulation time 6321806300 ps
CPU time 12.73 seconds
Started Dec 27 12:30:25 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 211168 kb
Host smart-93da6f7c-54ce-4cdb-9d31-0e821f4c03ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140934815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1140934815
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.4061510800
Short name T41
Test name
Test status
Simulation time 4267990396 ps
CPU time 16.07 seconds
Started Dec 27 12:31:37 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 211156 kb
Host smart-82cc6732-1491-4043-b66b-ec0d3bffedee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061510800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.4061510800
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2730217330
Short name T467
Test name
Test status
Simulation time 1301987562 ps
CPU time 11.8 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 211172 kb
Host smart-1eecdca0-35df-42f6-94d9-e3b0e588b0d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730217330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2730217330
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.227381153
Short name T80
Test name
Test status
Simulation time 125141391115 ps
CPU time 248.78 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:34:27 PM PST 23
Peak memory 211156 kb
Host smart-587703f7-73c2-47f6-aa75-5e25d92e0408
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227381153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.227381153
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3615372741
Short name T137
Test name
Test status
Simulation time 174938611 ps
CPU time 4.43 seconds
Started Dec 27 12:29:47 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 211096 kb
Host smart-28f9bcd8-4a4a-4541-81c5-a6b8e622fc03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615372741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.3615372741
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.4090443102
Short name T38
Test name
Test status
Simulation time 2721634760 ps
CPU time 17.71 seconds
Started Dec 27 12:29:37 PM PST 23
Finished Dec 27 12:30:49 PM PST 23
Peak memory 214724 kb
Host smart-80f40a92-e7a6-4bc5-9fa9-f1c607ff4a98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090443102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.4090443102
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2908308830
Short name T114
Test name
Test status
Simulation time 2726529687 ps
CPU time 74.3 seconds
Started Dec 27 12:29:45 PM PST 23
Finished Dec 27 12:31:52 PM PST 23
Peak memory 211544 kb
Host smart-9d437a49-b1b6-4d3e-b200-52552324cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908308830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2908308830
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.381728674
Short name T107
Test name
Test status
Simulation time 1935903159 ps
CPU time 15.1 seconds
Started Dec 27 12:30:27 PM PST 23
Finished Dec 27 12:31:37 PM PST 23
Peak memory 211092 kb
Host smart-44233e1c-896f-49a1-99a5-89b36ddc6faa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381728674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alias
ing.381728674
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.4038665996
Short name T131
Test name
Test status
Simulation time 1857314064 ps
CPU time 10.18 seconds
Started Dec 27 12:30:24 PM PST 23
Finished Dec 27 12:31:31 PM PST 23
Peak memory 211180 kb
Host smart-8511e315-7441-4a3c-86d6-9b29926d7f7e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038665996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.4038665996
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3136669437
Short name T70
Test name
Test status
Simulation time 442876231 ps
CPU time 7.62 seconds
Started Dec 27 12:29:30 PM PST 23
Finished Dec 27 12:30:31 PM PST 23
Peak memory 211116 kb
Host smart-d9f11de9-a919-4e1a-ac0a-30fe9d022ef7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136669437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3136669437
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.155034462
Short name T438
Test name
Test status
Simulation time 17967686908 ps
CPU time 14.18 seconds
Started Dec 27 12:30:23 PM PST 23
Finished Dec 27 12:31:34 PM PST 23
Peak memory 213928 kb
Host smart-b1a09d87-e480-422b-9673-d1fcd15e4b72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155034462 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.155034462
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.136464519
Short name T125
Test name
Test status
Simulation time 436911939 ps
CPU time 4.11 seconds
Started Dec 27 12:29:24 PM PST 23
Finished Dec 27 12:30:24 PM PST 23
Peak memory 211160 kb
Host smart-67e3e2d8-da47-4ff8-8b8a-19baef109906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136464519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.136464519
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.42689628
Short name T455
Test name
Test status
Simulation time 1888582194 ps
CPU time 14.95 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 211184 kb
Host smart-11923baf-f53f-4a20-8a5b-655b0ea7a499
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_
mem_partial_access.42689628
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3013156400
Short name T453
Test name
Test status
Simulation time 994479450 ps
CPU time 9.66 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:46 PM PST 23
Peak memory 211104 kb
Host smart-a5cbe9ae-5199-466e-ad37-9e7643b2bb38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013156400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3013156400
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1943317565
Short name T100
Test name
Test status
Simulation time 6448257241 ps
CPU time 93.64 seconds
Started Dec 27 12:29:51 PM PST 23
Finished Dec 27 12:32:16 PM PST 23
Peak memory 211160 kb
Host smart-ec659fad-c4de-4c1d-bc93-933dea4079eb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943317565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1943317565
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2549878282
Short name T135
Test name
Test status
Simulation time 552588782 ps
CPU time 4.46 seconds
Started Dec 27 12:29:28 PM PST 23
Finished Dec 27 12:30:26 PM PST 23
Peak memory 211088 kb
Host smart-ed887eee-d85c-4e48-8718-2456d18a039b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549878282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2549878282
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.789483645
Short name T108
Test name
Test status
Simulation time 638763232 ps
CPU time 6.51 seconds
Started Dec 27 12:30:31 PM PST 23
Finished Dec 27 12:31:44 PM PST 23
Peak memory 219420 kb
Host smart-d3609b3c-48c1-43d2-bb0a-34c1c14606ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789483645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.789483645
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.768134433
Short name T136
Test name
Test status
Simulation time 8336734950 ps
CPU time 48.97 seconds
Started Dec 27 12:30:14 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 212296 kb
Host smart-3aabc8f4-54a4-4e7a-8477-ab75c8bee1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768134433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_int
g_err.768134433
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1795468282
Short name T81
Test name
Test status
Simulation time 1309271004 ps
CPU time 5.82 seconds
Started Dec 27 12:29:35 PM PST 23
Finished Dec 27 12:30:35 PM PST 23
Peak memory 212644 kb
Host smart-752feebe-858e-40a9-8dec-edb2c650b954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795468282 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1795468282
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.931569125
Short name T450
Test name
Test status
Simulation time 6732825292 ps
CPU time 13.57 seconds
Started Dec 27 12:29:32 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211184 kb
Host smart-c6504bfb-7d29-414e-bd01-d2edf2f91cde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931569125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.931569125
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1622390408
Short name T443
Test name
Test status
Simulation time 53764986959 ps
CPU time 108.13 seconds
Started Dec 27 12:30:01 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 211156 kb
Host smart-7c354c71-0fda-4bf9-81fc-1914a43effa0
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622390408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1622390408
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3028398097
Short name T104
Test name
Test status
Simulation time 145470751 ps
CPU time 4.45 seconds
Started Dec 27 12:29:43 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211124 kb
Host smart-1a7444ce-282a-4107-abc2-e588563030d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028398097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3028398097
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3092775139
Short name T440
Test name
Test status
Simulation time 153464507 ps
CPU time 9.55 seconds
Started Dec 27 12:30:02 PM PST 23
Finished Dec 27 12:31:03 PM PST 23
Peak memory 219404 kb
Host smart-e50e1b81-eedf-4d27-9b69-120b7a725f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092775139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3092775139
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3651689773
Short name T449
Test name
Test status
Simulation time 835932011 ps
CPU time 4.37 seconds
Started Dec 27 12:30:21 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 211844 kb
Host smart-2217a058-33cc-44a0-a1e0-8b3c7ad810df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651689773 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3651689773
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.952404401
Short name T128
Test name
Test status
Simulation time 208625643 ps
CPU time 5.52 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:30:37 PM PST 23
Peak memory 211072 kb
Host smart-260741dd-f3de-4de1-8723-4f05e085f540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952404401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.952404401
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3969477823
Short name T76
Test name
Test status
Simulation time 79410522310 ps
CPU time 317.91 seconds
Started Dec 27 12:30:05 PM PST 23
Finished Dec 27 12:36:15 PM PST 23
Peak memory 211148 kb
Host smart-03c76ac6-44a8-40a8-acfb-138d459804fe
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969477823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3969477823
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2756473221
Short name T437
Test name
Test status
Simulation time 16168381098 ps
CPU time 16.47 seconds
Started Dec 27 12:30:03 PM PST 23
Finished Dec 27 12:31:11 PM PST 23
Peak memory 211164 kb
Host smart-7d09b5db-7d7a-4f1a-af2d-42b387e929a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756473221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2756473221
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.140667510
Short name T85
Test name
Test status
Simulation time 4254204773 ps
CPU time 15.14 seconds
Started Dec 27 12:30:13 PM PST 23
Finished Dec 27 12:31:22 PM PST 23
Peak memory 219360 kb
Host smart-a4f8c228-68a8-44b8-bfca-f3383a40154b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140667510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.140667510
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.774644649
Short name T82
Test name
Test status
Simulation time 18202821203 ps
CPU time 80.72 seconds
Started Dec 27 12:29:49 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 211764 kb
Host smart-b4aea79e-549b-494e-969b-e1b146408e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774644649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.774644649
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2647643688
Short name T144
Test name
Test status
Simulation time 95364121 ps
CPU time 4.67 seconds
Started Dec 27 12:29:46 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 213144 kb
Host smart-b49f4c5a-45ef-4f2c-95e7-ab215c664079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647643688 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2647643688
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.2493018573
Short name T102
Test name
Test status
Simulation time 307896507 ps
CPU time 6.38 seconds
Started Dec 27 12:29:18 PM PST 23
Finished Dec 27 12:30:19 PM PST 23
Peak memory 211064 kb
Host smart-794986d5-175a-4dc4-ad5f-b53c2f0ad9c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493018573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.2493018573
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1383897183
Short name T462
Test name
Test status
Simulation time 10736664049 ps
CPU time 130.22 seconds
Started Dec 27 12:30:25 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 211152 kb
Host smart-d9b06907-ce3d-49c9-af31-a6a53604ca9c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383897183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1383897183
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.570418623
Short name T106
Test name
Test status
Simulation time 168707314 ps
CPU time 4.36 seconds
Started Dec 27 12:30:04 PM PST 23
Finished Dec 27 12:31:00 PM PST 23
Peak memory 211072 kb
Host smart-ca776965-1cb1-42aa-a337-a355726dcd56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570418623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.570418623
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.927508382
Short name T471
Test name
Test status
Simulation time 1240323710 ps
CPU time 74.08 seconds
Started Dec 27 12:29:23 PM PST 23
Finished Dec 27 12:31:32 PM PST 23
Peak memory 211148 kb
Host smart-1e4fb8da-63d0-4378-9c93-435064d50a82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927508382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.927508382
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2200739727
Short name T123
Test name
Test status
Simulation time 6074101396 ps
CPU time 12.66 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:30:43 PM PST 23
Peak memory 214236 kb
Host smart-dbe4e23b-320b-418f-82c7-fe45c45e359d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200739727 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2200739727
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1659149653
Short name T126
Test name
Test status
Simulation time 333912322 ps
CPU time 6.79 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:30:40 PM PST 23
Peak memory 211172 kb
Host smart-dbb40e5b-d785-4fc1-a3e6-5947b0e507ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659149653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1659149653
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3920793968
Short name T78
Test name
Test status
Simulation time 39580295999 ps
CPU time 165.2 seconds
Started Dec 27 12:29:39 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 211104 kb
Host smart-88579061-42dc-42a3-a97a-0c9b1385d278
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920793968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3920793968
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.3951971154
Short name T458
Test name
Test status
Simulation time 7775342713 ps
CPU time 17.06 seconds
Started Dec 27 12:29:36 PM PST 23
Finished Dec 27 12:30:47 PM PST 23
Peak memory 211336 kb
Host smart-41d830eb-0d44-443a-8b08-8a733d2ef25a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951971154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.3951971154
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3071475422
Short name T84
Test name
Test status
Simulation time 605816159 ps
CPU time 8.55 seconds
Started Dec 27 12:29:15 PM PST 23
Finished Dec 27 12:30:17 PM PST 23
Peak memory 219360 kb
Host smart-55f03c1d-00c1-46ba-b0c4-95628380c7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071475422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3071475422
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.786252513
Short name T115
Test name
Test status
Simulation time 5199415587 ps
CPU time 77.39 seconds
Started Dec 27 12:29:38 PM PST 23
Finished Dec 27 12:31:49 PM PST 23
Peak memory 211604 kb
Host smart-130a2bcb-6355-4b40-86b5-5b372b665e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786252513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.786252513
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.42550695
Short name T433
Test name
Test status
Simulation time 100274870 ps
CPU time 4.36 seconds
Started Dec 27 12:29:57 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 211076 kb
Host smart-61748d04-ae77-4b00-9b89-84f10228c4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.42550695
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1070386502
Short name T44
Test name
Test status
Simulation time 1859217225 ps
CPU time 96.62 seconds
Started Dec 27 12:31:11 PM PST 23
Finished Dec 27 12:33:36 PM PST 23
Peak memory 210120 kb
Host smart-c9bfeed3-7aad-4c67-a649-56f94905d91c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070386502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1070386502
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.586987578
Short name T141
Test name
Test status
Simulation time 8416851141 ps
CPU time 15.64 seconds
Started Dec 27 12:29:31 PM PST 23
Finished Dec 27 12:30:42 PM PST 23
Peak memory 211100 kb
Host smart-1786566c-dc81-47bb-9115-46025f7e4dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586987578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.586987578
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1138109637
Short name T478
Test name
Test status
Simulation time 7715869255 ps
CPU time 48.92 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:33:46 PM PST 23
Peak memory 212360 kb
Host smart-e2b7c747-96f2-4bd6-82e3-baf8e6e6bb83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138109637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1138109637
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.982774648
Short name T396
Test name
Test status
Simulation time 4104831332 ps
CPU time 11.29 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:27:23 PM PST 23
Peak memory 210248 kb
Host smart-55a4bf51-a829-4845-9ec2-44a13928e70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982774648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.982774648
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2546006132
Short name T199
Test name
Test status
Simulation time 44440343055 ps
CPU time 443.96 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:33:54 PM PST 23
Peak memory 235468 kb
Host smart-0af68dae-2727-442c-a3fd-b20b296e8fc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546006132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2546006132
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.930407083
Short name T398
Test name
Test status
Simulation time 475469330 ps
CPU time 9.64 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:40 PM PST 23
Peak memory 210396 kb
Host smart-5b7aa503-5231-4f08-a1e5-fc9ba9e80b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930407083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.930407083
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2153361326
Short name T188
Test name
Test status
Simulation time 620448220 ps
CPU time 9.23 seconds
Started Dec 27 12:26:32 PM PST 23
Finished Dec 27 12:26:56 PM PST 23
Peak memory 210636 kb
Host smart-73a9a298-44b0-4ffb-b01c-e9cf4b1cbed8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153361326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2153361326
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2759432313
Short name T226
Test name
Test status
Simulation time 190679760 ps
CPU time 10.38 seconds
Started Dec 27 12:26:52 PM PST 23
Finished Dec 27 12:27:23 PM PST 23
Peak memory 211816 kb
Host smart-b4ed71d4-a3fb-475d-82bb-2d54373ac8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759432313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2759432313
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.259473541
Short name T324
Test name
Test status
Simulation time 5786936592 ps
CPU time 12.46 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:26:58 PM PST 23
Peak memory 210132 kb
Host smart-86715204-0b00-40e2-ab4b-634e7ba4ac61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259473541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.259473541
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3797311401
Short name T261
Test name
Test status
Simulation time 42422222376 ps
CPU time 347.89 seconds
Started Dec 27 12:27:04 PM PST 23
Finished Dec 27 12:33:16 PM PST 23
Peak memory 211260 kb
Host smart-4b3bf43b-81f0-464e-8ac9-791146dd4761
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797311401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3797311401
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.191856100
Short name T304
Test name
Test status
Simulation time 3405495275 ps
CPU time 14.86 seconds
Started Dec 27 12:25:13 PM PST 23
Finished Dec 27 12:25:33 PM PST 23
Peak memory 210584 kb
Host smart-5efeb083-8a77-4dbc-9e73-33a83ab1b36f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=191856100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.191856100
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2941683915
Short name T45
Test name
Test status
Simulation time 2732361064 ps
CPU time 62.48 seconds
Started Dec 27 12:25:13 PM PST 23
Finished Dec 27 12:26:18 PM PST 23
Peak memory 238508 kb
Host smart-ead31ffe-d912-4a2f-969a-8156dc75bb57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941683915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2941683915
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.4318943
Short name T276
Test name
Test status
Simulation time 725894413 ps
CPU time 10.14 seconds
Started Dec 27 12:25:14 PM PST 23
Finished Dec 27 12:25:28 PM PST 23
Peak memory 212196 kb
Host smart-968745d1-a6d9-4b0a-85a0-64c9874dcf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4318943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.4318943
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2572260799
Short name T380
Test name
Test status
Simulation time 1928847075 ps
CPU time 16.13 seconds
Started Dec 27 12:25:29 PM PST 23
Finished Dec 27 12:25:53 PM PST 23
Peak memory 210704 kb
Host smart-b2ef0a8e-3f6a-4c3f-b114-7e818a7bfd00
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572260799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2572260799
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.296966681
Short name T264
Test name
Test status
Simulation time 64129286341 ps
CPU time 1408.19 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:50:14 PM PST 23
Peak memory 226140 kb
Host smart-80ae1099-091d-4b7f-82ac-c54195e49333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296966681 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.296966681
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2649732666
Short name T322
Test name
Test status
Simulation time 8239945117 ps
CPU time 21.09 seconds
Started Dec 27 12:27:19 PM PST 23
Finished Dec 27 12:28:07 PM PST 23
Peak memory 215916 kb
Host smart-47629305-d2ad-4f01-b97f-f3e79e5cb1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649732666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2649732666
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3460290607
Short name T47
Test name
Test status
Simulation time 1772452998 ps
CPU time 9.17 seconds
Started Dec 27 12:27:19 PM PST 23
Finished Dec 27 12:27:55 PM PST 23
Peak memory 210476 kb
Host smart-d4ce5772-17f3-498e-9bab-83a7d1844aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460290607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3460290607
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2523281416
Short name T286
Test name
Test status
Simulation time 745941771 ps
CPU time 10.14 seconds
Started Dec 27 12:27:18 PM PST 23
Finished Dec 27 12:27:55 PM PST 23
Peak memory 212364 kb
Host smart-68340f56-5c12-4888-94c9-d9b36760f1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523281416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2523281416
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.4288005014
Short name T360
Test name
Test status
Simulation time 3680260272 ps
CPU time 34.5 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:30:07 PM PST 23
Peak memory 213508 kb
Host smart-f089c1e9-1907-4bcc-a6f5-757e81c27b5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288005014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.4288005014
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3590738565
Short name T14
Test name
Test status
Simulation time 149134018338 ps
CPU time 2665.88 seconds
Started Dec 27 12:20:52 PM PST 23
Finished Dec 27 01:05:19 PM PST 23
Peak memory 244684 kb
Host smart-2de1afcd-eb6d-401e-bee2-4aec704bbe3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590738565 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3590738565
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3930057009
Short name T348
Test name
Test status
Simulation time 8259172234 ps
CPU time 15.16 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:28:10 PM PST 23
Peak memory 208832 kb
Host smart-5434fccc-63fb-42b2-8f5b-b14ef1609f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930057009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3930057009
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3901943855
Short name T397
Test name
Test status
Simulation time 171208604403 ps
CPU time 456.16 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:34:16 PM PST 23
Peak memory 237172 kb
Host smart-0e26895a-0cec-434f-ad38-e4ada3ca3ba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901943855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3901943855
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3056463566
Short name T27
Test name
Test status
Simulation time 4216585048 ps
CPU time 31.69 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:28:29 PM PST 23
Peak memory 211116 kb
Host smart-d25f2a22-95ab-429a-85d8-2bbda5d8a357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056463566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3056463566
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1705788062
Short name T394
Test name
Test status
Simulation time 835969865 ps
CPU time 8.58 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:39 PM PST 23
Peak memory 209232 kb
Host smart-7157fd4d-07fe-4fee-bacf-346988f403f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705788062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1705788062
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4193704404
Short name T175
Test name
Test status
Simulation time 191746614 ps
CPU time 10.06 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 211620 kb
Host smart-842f714d-5c09-4fd6-814d-d2855cee7d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193704404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4193704404
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3116846771
Short name T314
Test name
Test status
Simulation time 969878870 ps
CPU time 21.57 seconds
Started Dec 27 12:21:29 PM PST 23
Finished Dec 27 12:21:51 PM PST 23
Peak memory 212136 kb
Host smart-a64fac13-f4bd-4ee0-b72c-6123354e316b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116846771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3116846771
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2265240924
Short name T271
Test name
Test status
Simulation time 81465222105 ps
CPU time 2205.36 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 01:04:41 PM PST 23
Peak memory 234896 kb
Host smart-00479694-d08f-4695-9bbe-e99ae8adac84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265240924 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2265240924
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.96746967
Short name T351
Test name
Test status
Simulation time 333848661 ps
CPU time 4.16 seconds
Started Dec 27 12:27:28 PM PST 23
Finished Dec 27 12:28:00 PM PST 23
Peak memory 210300 kb
Host smart-18c1b57d-260d-4b0b-b977-bf302a28aab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96746967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.96746967
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3383078291
Short name T355
Test name
Test status
Simulation time 39647240691 ps
CPU time 400.53 seconds
Started Dec 27 12:20:56 PM PST 23
Finished Dec 27 12:27:37 PM PST 23
Peak memory 212176 kb
Host smart-d41f66fc-3405-46c0-a6c2-674e8ecd29e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383078291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3383078291
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2516936185
Short name T260
Test name
Test status
Simulation time 4444340541 ps
CPU time 16.78 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:28:12 PM PST 23
Peak memory 209748 kb
Host smart-0641ab56-c2d6-4ddd-b6f7-f1341d00726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516936185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2516936185
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.4238743036
Short name T353
Test name
Test status
Simulation time 945623292 ps
CPU time 10.53 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:47 PM PST 23
Peak memory 209460 kb
Host smart-c23947f5-76b2-43d2-8f8a-35b95d2b75b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238743036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.4238743036
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3168330227
Short name T414
Test name
Test status
Simulation time 3549198232 ps
CPU time 36.67 seconds
Started Dec 27 12:21:01 PM PST 23
Finished Dec 27 12:21:39 PM PST 23
Peak memory 211792 kb
Host smart-650a3e1f-f01c-4d0f-9fad-b05c078d5724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168330227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3168330227
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.380755728
Short name T145
Test name
Test status
Simulation time 26251458254 ps
CPU time 154.75 seconds
Started Dec 27 12:25:22 PM PST 23
Finished Dec 27 12:28:06 PM PST 23
Peak memory 218032 kb
Host smart-486c9e5c-b2a1-49c3-a7c8-578702e46a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380755728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.380755728
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1837697989
Short name T200
Test name
Test status
Simulation time 346470347 ps
CPU time 4.15 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 210368 kb
Host smart-9969219c-9c10-4cd1-89b0-fe20d84ef0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837697989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1837697989
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2146370443
Short name T54
Test name
Test status
Simulation time 38908445905 ps
CPU time 352.38 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 12:36:07 PM PST 23
Peak memory 236104 kb
Host smart-7a705a5d-2860-4130-9206-458ff7fc4d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146370443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2146370443
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.3409507571
Short name T291
Test name
Test status
Simulation time 3570175801 ps
CPU time 29.15 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:14 PM PST 23
Peak memory 210660 kb
Host smart-b940b16f-136c-48ef-80c5-45c3b1bc0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409507571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.3409507571
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.861704815
Short name T241
Test name
Test status
Simulation time 3375591011 ps
CPU time 14.69 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:28:10 PM PST 23
Peak memory 208852 kb
Host smart-b0e5e31a-9f42-41d9-9a0a-a022ecd54b5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=861704815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.861704815
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2601141420
Short name T18
Test name
Test status
Simulation time 1056405298 ps
CPU time 12 seconds
Started Dec 27 12:26:30 PM PST 23
Finished Dec 27 12:26:57 PM PST 23
Peak memory 211936 kb
Host smart-fc1e5b0f-2bfa-43a8-9ad8-0453224d3dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601141420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2601141420
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3912515246
Short name T228
Test name
Test status
Simulation time 5457921093 ps
CPU time 57.16 seconds
Started Dec 27 12:29:13 PM PST 23
Finished Dec 27 12:31:05 PM PST 23
Peak memory 215352 kb
Host smart-ea968ccf-0d53-4d37-94cc-de04425f6de3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912515246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3912515246
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2838756137
Short name T273
Test name
Test status
Simulation time 174917779 ps
CPU time 5.34 seconds
Started Dec 27 12:28:12 PM PST 23
Finished Dec 27 12:28:57 PM PST 23
Peak memory 210152 kb
Host smart-3a9aede6-3425-4176-9677-fdc473d3ed11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838756137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2838756137
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.4157048875
Short name T58
Test name
Test status
Simulation time 5014239318 ps
CPU time 103.9 seconds
Started Dec 27 12:26:02 PM PST 23
Finished Dec 27 12:27:55 PM PST 23
Peak memory 211308 kb
Host smart-9af52803-9fab-40b7-8fab-3c02c888e5ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157048875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.4157048875
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3071398308
Short name T349
Test name
Test status
Simulation time 11677627621 ps
CPU time 22.65 seconds
Started Dec 27 12:28:37 PM PST 23
Finished Dec 27 12:29:51 PM PST 23
Peak memory 210976 kb
Host smart-18c637c5-579f-415e-a96d-fe245621e218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071398308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3071398308
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1118006006
Short name T187
Test name
Test status
Simulation time 40263533523 ps
CPU time 16.64 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:29:49 PM PST 23
Peak memory 210548 kb
Host smart-820510a4-e674-4ad8-a490-93d7d66620d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118006006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1118006006
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.4142648038
Short name T263
Test name
Test status
Simulation time 2257936904 ps
CPU time 23 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:53 PM PST 23
Peak memory 211560 kb
Host smart-ddad1bff-5679-4290-8b3e-20ec9b488970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142648038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.4142648038
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.4094443508
Short name T352
Test name
Test status
Simulation time 111928898 ps
CPU time 10.69 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:30:05 PM PST 23
Peak memory 210320 kb
Host smart-3de06068-481a-4b4c-b9c1-fe4105f760c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094443508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.4094443508
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1355796337
Short name T318
Test name
Test status
Simulation time 294359250 ps
CPU time 6.5 seconds
Started Dec 27 12:22:23 PM PST 23
Finished Dec 27 12:22:30 PM PST 23
Peak memory 210924 kb
Host smart-48c5e35f-49b2-49a2-bf66-cc376645ed09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355796337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1355796337
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4259084631
Short name T11
Test name
Test status
Simulation time 14359038776 ps
CPU time 134.1 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:27:45 PM PST 23
Peak memory 211752 kb
Host smart-b10dc765-30ae-422b-9e08-3f830f42922c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259084631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4259084631
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.783065727
Short name T162
Test name
Test status
Simulation time 26589941212 ps
CPU time 24.09 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:54 PM PST 23
Peak memory 210836 kb
Host smart-0eac6a6f-bbd2-48da-a773-4e394fea652e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783065727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.783065727
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3103075315
Short name T431
Test name
Test status
Simulation time 527868785 ps
CPU time 8.48 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:30:04 PM PST 23
Peak memory 210508 kb
Host smart-ef80c8d2-0d13-4af9-b2c8-1614acc6513b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103075315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3103075315
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.959092879
Short name T333
Test name
Test status
Simulation time 3255327872 ps
CPU time 31.9 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:59 PM PST 23
Peak memory 212392 kb
Host smart-cb9c5bb2-a5ca-41cd-890e-d2606cd1f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959092879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.959092879
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.431604570
Short name T51
Test name
Test status
Simulation time 17551013751 ps
CPU time 43.56 seconds
Started Dec 27 12:19:58 PM PST 23
Finished Dec 27 12:20:43 PM PST 23
Peak memory 213004 kb
Host smart-d0fb6c3f-9ffa-46d7-b8f2-5e90be297194
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431604570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.431604570
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.576600711
Short name T399
Test name
Test status
Simulation time 102388259811 ps
CPU time 2175.5 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 01:06:02 PM PST 23
Peak memory 235164 kb
Host smart-bcff47d4-62f7-462c-895d-e6a7e6c59235
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576600711 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.576600711
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1545687914
Short name T254
Test name
Test status
Simulation time 10379302009 ps
CPU time 12.42 seconds
Started Dec 27 12:25:33 PM PST 23
Finished Dec 27 12:25:52 PM PST 23
Peak memory 210568 kb
Host smart-7f7cab07-75fa-4cfd-adcd-987f788925c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545687914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1545687914
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3462953434
Short name T216
Test name
Test status
Simulation time 66880806757 ps
CPU time 241.9 seconds
Started Dec 27 12:25:17 PM PST 23
Finished Dec 27 12:29:28 PM PST 23
Peak memory 211844 kb
Host smart-dd299921-ed71-4cf1-b720-2688809fab2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462953434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3462953434
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.89230668
Short name T255
Test name
Test status
Simulation time 175269127 ps
CPU time 9.6 seconds
Started Dec 27 12:27:42 PM PST 23
Finished Dec 27 12:28:22 PM PST 23
Peak memory 210624 kb
Host smart-237ef356-77cf-46ba-8c22-dbfaf858aa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89230668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.89230668
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.3760261600
Short name T205
Test name
Test status
Simulation time 1394386617 ps
CPU time 11.23 seconds
Started Dec 27 12:26:34 PM PST 23
Finished Dec 27 12:27:01 PM PST 23
Peak memory 210736 kb
Host smart-42b00d87-2541-4584-8b7f-6ba90c87ec13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3760261600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.3760261600
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3151136103
Short name T344
Test name
Test status
Simulation time 3505783244 ps
CPU time 34.78 seconds
Started Dec 27 12:25:40 PM PST 23
Finished Dec 27 12:26:23 PM PST 23
Peak memory 212304 kb
Host smart-a66f3813-eb12-482a-83f5-e74e566665d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151136103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3151136103
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.2652844095
Short name T418
Test name
Test status
Simulation time 3814825781 ps
CPU time 17.87 seconds
Started Dec 27 12:39:04 PM PST 23
Finished Dec 27 12:39:39 PM PST 23
Peak memory 219032 kb
Host smart-6609481e-f4d5-41ee-9d0a-4d9a90ad6aa0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652844095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.2652844095
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.3878967788
Short name T428
Test name
Test status
Simulation time 369917913525 ps
CPU time 5739.49 seconds
Started Dec 27 12:28:45 PM PST 23
Finished Dec 27 02:05:17 PM PST 23
Peak memory 235108 kb
Host smart-169b943e-12d7-42f8-90e7-519a4c6c4502
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878967788 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.3878967788
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.207569640
Short name T208
Test name
Test status
Simulation time 1280620651 ps
CPU time 11.78 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 210580 kb
Host smart-9257a71a-fb46-451e-a097-b4413cf0eae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207569640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.207569640
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1097145617
Short name T242
Test name
Test status
Simulation time 80786640968 ps
CPU time 352.83 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:35:09 PM PST 23
Peak memory 212728 kb
Host smart-d8cf9e92-3335-4b4a-b9e2-546cda51b6e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097145617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1097145617
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.3082028488
Short name T186
Test name
Test status
Simulation time 11180116356 ps
CPU time 23.8 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:30:05 PM PST 23
Peak memory 211048 kb
Host smart-bdfaa6a9-03c1-437a-bf0a-3a7a03f7bf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082028488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.3082028488
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3112646798
Short name T148
Test name
Test status
Simulation time 1541319856 ps
CPU time 7.19 seconds
Started Dec 27 12:25:34 PM PST 23
Finished Dec 27 12:25:47 PM PST 23
Peak memory 210452 kb
Host smart-2ae72b93-9f7d-46b3-8f56-1e25d76f198f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112646798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3112646798
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3855230057
Short name T334
Test name
Test status
Simulation time 3831134891 ps
CPU time 35.14 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 212488 kb
Host smart-50e2cf69-4afa-4f5b-aa4d-7082ace03372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855230057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3855230057
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3392095885
Short name T272
Test name
Test status
Simulation time 651800388 ps
CPU time 10.52 seconds
Started Dec 27 12:25:16 PM PST 23
Finished Dec 27 12:25:36 PM PST 23
Peak memory 209704 kb
Host smart-d09aea48-b245-400f-8d87-c460c7c917a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392095885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3392095885
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2265678539
Short name T270
Test name
Test status
Simulation time 1660109139 ps
CPU time 14.2 seconds
Started Dec 27 12:24:34 PM PST 23
Finished Dec 27 12:24:49 PM PST 23
Peak memory 210440 kb
Host smart-0bd4a77e-20fb-4f5c-a3fe-2e7115924ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265678539 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2265678539
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.702949011
Short name T283
Test name
Test status
Simulation time 84326385887 ps
CPU time 225.53 seconds
Started Dec 27 12:28:52 PM PST 23
Finished Dec 27 12:33:31 PM PST 23
Peak memory 227220 kb
Host smart-7e7b446a-1ab2-42f7-9638-96db6335e37b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702949011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.702949011
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3061897483
Short name T225
Test name
Test status
Simulation time 3183494855 ps
CPU time 27.35 seconds
Started Dec 27 12:29:12 PM PST 23
Finished Dec 27 12:30:33 PM PST 23
Peak memory 210688 kb
Host smart-9d2dd945-c562-40f8-81e3-e2c23c6f11b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061897483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3061897483
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3814145858
Short name T306
Test name
Test status
Simulation time 6320468187 ps
CPU time 12.5 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:29:08 PM PST 23
Peak memory 210384 kb
Host smart-a7ad222e-4b5f-4851-8bd1-94f34d2dca97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814145858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3814145858
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.758850377
Short name T235
Test name
Test status
Simulation time 712324298 ps
CPU time 9.83 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:44 PM PST 23
Peak memory 212016 kb
Host smart-eccb2949-88be-4bdf-9948-7486161aa7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758850377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.758850377
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2990673615
Short name T177
Test name
Test status
Simulation time 16291784595 ps
CPU time 44.85 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 215716 kb
Host smart-32ac5088-5419-414f-9653-778f932f1d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990673615 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2990673615
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.4183332122
Short name T292
Test name
Test status
Simulation time 89724497 ps
CPU time 4.32 seconds
Started Dec 27 12:25:29 PM PST 23
Finished Dec 27 12:25:41 PM PST 23
Peak memory 210840 kb
Host smart-beca9ec5-d391-4359-a196-5249b40a8375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183332122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.4183332122
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2386928559
Short name T30
Test name
Test status
Simulation time 27139857649 ps
CPU time 337.46 seconds
Started Dec 27 12:27:49 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 237048 kb
Host smart-6e7b7689-5f90-4147-9f9c-c5abbadb11b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386928559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2386928559
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1205515274
Short name T356
Test name
Test status
Simulation time 695924694 ps
CPU time 9.57 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:43 PM PST 23
Peak memory 211044 kb
Host smart-20b744f1-5c91-488f-9646-a530f5a32d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205515274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1205515274
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2409760882
Short name T155
Test name
Test status
Simulation time 1315535090 ps
CPU time 13.52 seconds
Started Dec 27 12:20:18 PM PST 23
Finished Dec 27 12:20:38 PM PST 23
Peak memory 210820 kb
Host smart-7d4ebea8-146d-4c32-bf0e-c02d7ad96d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409760882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2409760882
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.959590362
Short name T302
Test name
Test status
Simulation time 361966904 ps
CPU time 9.85 seconds
Started Dec 27 12:28:56 PM PST 23
Finished Dec 27 12:30:00 PM PST 23
Peak memory 211840 kb
Host smart-48537aca-0f28-4316-8e38-e4325dc5d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959590362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.959590362
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.4253516708
Short name T281
Test name
Test status
Simulation time 9906331728 ps
CPU time 40.93 seconds
Started Dec 27 12:24:33 PM PST 23
Finished Dec 27 12:25:16 PM PST 23
Peak memory 212696 kb
Host smart-b4f7aaed-0dcb-4c84-a463-3d5285a3fe37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253516708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.4253516708
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.1432138181
Short name T338
Test name
Test status
Simulation time 57697770007 ps
CPU time 1411.85 seconds
Started Dec 27 12:25:29 PM PST 23
Finished Dec 27 12:49:09 PM PST 23
Peak memory 232888 kb
Host smart-cea53e34-9545-4566-89b9-6df0a5bffff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432138181 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.1432138181
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1133243393
Short name T220
Test name
Test status
Simulation time 509694502 ps
CPU time 7.33 seconds
Started Dec 27 12:25:34 PM PST 23
Finished Dec 27 12:25:47 PM PST 23
Peak memory 210840 kb
Host smart-0b83848e-1f9a-4d09-9f40-0a393c2fc6b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133243393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1133243393
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3846564330
Short name T153
Test name
Test status
Simulation time 3608465260 ps
CPU time 106.19 seconds
Started Dec 27 12:23:22 PM PST 23
Finished Dec 27 12:25:11 PM PST 23
Peak memory 236660 kb
Host smart-00747a1b-9c55-4b64-b7af-e725aa4ca9ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846564330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3846564330
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2826687245
Short name T294
Test name
Test status
Simulation time 8070734965 ps
CPU time 32.78 seconds
Started Dec 27 12:26:33 PM PST 23
Finished Dec 27 12:27:20 PM PST 23
Peak memory 211396 kb
Host smart-3ee2662e-fb7d-4da0-a0e7-02e875ea25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826687245 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2826687245
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.970727882
Short name T150
Test name
Test status
Simulation time 1178149978 ps
CPU time 10.69 seconds
Started Dec 27 12:26:08 PM PST 23
Finished Dec 27 12:26:28 PM PST 23
Peak memory 209288 kb
Host smart-17fd9d6a-f8ca-42d7-b68b-1fa86084df5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970727882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.970727882
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2524944815
Short name T43
Test name
Test status
Simulation time 21438847296 ps
CPU time 119.61 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:26:56 PM PST 23
Peak memory 236276 kb
Host smart-7ab7850b-b3a2-45ce-bda9-aeb9984b7269
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524944815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2524944815
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3629578880
Short name T26
Test name
Test status
Simulation time 3959662663 ps
CPU time 27.23 seconds
Started Dec 27 12:22:37 PM PST 23
Finished Dec 27 12:23:04 PM PST 23
Peak memory 212344 kb
Host smart-ed4d55b6-9328-4125-b98c-8e6c51462d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629578880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3629578880
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3074879795
Short name T232
Test name
Test status
Simulation time 2143098768 ps
CPU time 19.97 seconds
Started Dec 27 12:25:14 PM PST 23
Finished Dec 27 12:25:38 PM PST 23
Peak memory 214664 kb
Host smart-10b797b8-bc9d-4c8b-8b89-a914335c1c1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074879795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3074879795
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.896837432
Short name T307
Test name
Test status
Simulation time 101290032142 ps
CPU time 1690.48 seconds
Started Dec 27 12:20:27 PM PST 23
Finished Dec 27 12:48:40 PM PST 23
Peak memory 230308 kb
Host smart-ddfdfe74-4caa-4161-a576-11e5c724a070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896837432 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.896837432
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1063869239
Short name T267
Test name
Test status
Simulation time 6832927776 ps
CPU time 13.33 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:10 PM PST 23
Peak memory 210376 kb
Host smart-bc59efec-c1ea-4981-a143-186520ee4893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063869239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1063869239
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3270040754
Short name T330
Test name
Test status
Simulation time 75875252879 ps
CPU time 559.34 seconds
Started Dec 27 12:26:21 PM PST 23
Finished Dec 27 12:35:55 PM PST 23
Peak memory 237140 kb
Host smart-c75d2f2f-105b-4e2f-9f6a-249c7b4e0749
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270040754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3270040754
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.283975385
Short name T256
Test name
Test status
Simulation time 1639916110 ps
CPU time 19.68 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 210616 kb
Host smart-bf1ac7c6-e060-40ff-a6df-3a6c96d589b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283975385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.283975385
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.743994601
Short name T419
Test name
Test status
Simulation time 516038280 ps
CPU time 8.61 seconds
Started Dec 27 12:28:14 PM PST 23
Finished Dec 27 12:29:05 PM PST 23
Peak memory 210304 kb
Host smart-4374d65f-f9bb-4330-8313-17faa98a0c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=743994601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.743994601
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.181401756
Short name T405
Test name
Test status
Simulation time 2912951253 ps
CPU time 26.69 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:30:02 PM PST 23
Peak memory 212412 kb
Host smart-3d2044b8-31bc-44c2-8f52-b40e9adadd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181401756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.181401756
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.675317804
Short name T417
Test name
Test status
Simulation time 779799934 ps
CPU time 10.4 seconds
Started Dec 27 12:28:18 PM PST 23
Finished Dec 27 12:29:11 PM PST 23
Peak memory 212796 kb
Host smart-932ae2aa-77f7-4669-a3e4-4f36142019db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675317804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.675317804
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2687948537
Short name T295
Test name
Test status
Simulation time 24447727317 ps
CPU time 319.74 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:34:50 PM PST 23
Peak memory 222872 kb
Host smart-f41f4d06-09bd-4dd2-9bf4-7da380147424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687948537 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2687948537
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1896484644
Short name T376
Test name
Test status
Simulation time 1175128412 ps
CPU time 11.3 seconds
Started Dec 27 12:20:08 PM PST 23
Finished Dec 27 12:20:21 PM PST 23
Peak memory 210768 kb
Host smart-0f4dade2-97cb-495f-b430-2ab8830de15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896484644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1896484644
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1305535468
Short name T275
Test name
Test status
Simulation time 65867109639 ps
CPU time 207.68 seconds
Started Dec 27 12:21:24 PM PST 23
Finished Dec 27 12:24:52 PM PST 23
Peak memory 225732 kb
Host smart-831d2a5f-1827-442e-9328-de0a9a5c769a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305535468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1305535468
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.603824534
Short name T423
Test name
Test status
Simulation time 5929535128 ps
CPU time 28.79 seconds
Started Dec 27 12:20:20 PM PST 23
Finished Dec 27 12:20:54 PM PST 23
Peak memory 211616 kb
Host smart-43bab166-3b07-4ead-b8b2-137956d08a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603824534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.603824534
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2506851160
Short name T420
Test name
Test status
Simulation time 7918515943 ps
CPU time 10.82 seconds
Started Dec 27 12:22:21 PM PST 23
Finished Dec 27 12:22:33 PM PST 23
Peak memory 210832 kb
Host smart-7395aa11-9e40-4e6c-8721-01b2a0dc4c9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2506851160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2506851160
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.4144413215
Short name T207
Test name
Test status
Simulation time 5864381628 ps
CPU time 22.35 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:19 PM PST 23
Peak memory 212524 kb
Host smart-8ef71010-8cec-4417-833f-80f183bb4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144413215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.4144413215
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.83677193
Short name T168
Test name
Test status
Simulation time 3335005285 ps
CPU time 33.63 seconds
Started Dec 27 12:29:00 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 213044 kb
Host smart-9ebc11c9-61a8-45f9-bfbd-3f1b0cb69876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83677193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 21.rom_ctrl_stress_all.83677193
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.4060733986
Short name T151
Test name
Test status
Simulation time 161457443 ps
CPU time 4.17 seconds
Started Dec 27 12:28:31 PM PST 23
Finished Dec 27 12:29:24 PM PST 23
Peak memory 210440 kb
Host smart-864083cc-e4aa-4999-b366-b17a537731f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060733986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.4060733986
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1466891665
Short name T249
Test name
Test status
Simulation time 26325200234 ps
CPU time 277.51 seconds
Started Dec 27 12:28:46 PM PST 23
Finished Dec 27 12:34:15 PM PST 23
Peak memory 211800 kb
Host smart-7bb12ca5-073b-4383-a540-1058b87466b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466891665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1466891665
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1043069208
Short name T251
Test name
Test status
Simulation time 8168238800 ps
CPU time 31.94 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 210508 kb
Host smart-82bd4d9d-41af-42aa-992e-1d07bd77bf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043069208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1043069208
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2239326531
Short name T382
Test name
Test status
Simulation time 965012641 ps
CPU time 6.89 seconds
Started Dec 27 12:21:37 PM PST 23
Finished Dec 27 12:21:45 PM PST 23
Peak memory 210712 kb
Host smart-5dcc9e36-164f-42d3-94b6-c1ceb7c63b74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239326531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2239326531
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.1457796791
Short name T336
Test name
Test status
Simulation time 2957369296 ps
CPU time 18.06 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:16 PM PST 23
Peak memory 211836 kb
Host smart-afed1cf8-3471-4878-a852-12b1bbea6c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457796791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.1457796791
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1785735652
Short name T4
Test name
Test status
Simulation time 9893677969 ps
CPU time 31.58 seconds
Started Dec 27 12:28:48 PM PST 23
Finished Dec 27 12:30:12 PM PST 23
Peak memory 213096 kb
Host smart-d74e130e-2625-4aa1-b0cf-4105e9ed2a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785735652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1785735652
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3465271788
Short name T350
Test name
Test status
Simulation time 4684651609 ps
CPU time 8.88 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:56 PM PST 23
Peak memory 210576 kb
Host smart-fae2619a-89cc-458d-ac7e-ef86f76d13b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465271788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3465271788
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2664812643
Short name T378
Test name
Test status
Simulation time 5753950127 ps
CPU time 80.98 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:26:53 PM PST 23
Peak memory 223084 kb
Host smart-df4e46e9-e0e0-4844-b817-30be150ded3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664812643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2664812643
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1689185286
Short name T390
Test name
Test status
Simulation time 2302167465 ps
CPU time 23.92 seconds
Started Dec 27 12:25:22 PM PST 23
Finished Dec 27 12:25:56 PM PST 23
Peak memory 210556 kb
Host smart-49836256-98be-4951-a6c6-14bbe01e7d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689185286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1689185286
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1144042632
Short name T379
Test name
Test status
Simulation time 182859237 ps
CPU time 5.53 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:25:37 PM PST 23
Peak memory 209208 kb
Host smart-98a170d9-e852-4c0e-8467-6f14dfd6a5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144042632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1144042632
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.37360175
Short name T160
Test name
Test status
Simulation time 728542625 ps
CPU time 10.1 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:28:35 PM PST 23
Peak memory 211672 kb
Host smart-06dd674c-400c-4d9e-af1f-1215294f8915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37360175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.37360175
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3731350718
Short name T415
Test name
Test status
Simulation time 4280975480 ps
CPU time 19.89 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:25:51 PM PST 23
Peak memory 211756 kb
Host smart-e01da7fc-6ca5-496c-9c38-05488d979497
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731350718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3731350718
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.63630882
Short name T411
Test name
Test status
Simulation time 146924351832 ps
CPU time 1012.24 seconds
Started Dec 27 12:21:45 PM PST 23
Finished Dec 27 12:38:38 PM PST 23
Peak memory 235404 kb
Host smart-c300b5de-8c01-4950-9d17-1198c7920f68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63630882 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.63630882
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2483507680
Short name T227
Test name
Test status
Simulation time 4253007168 ps
CPU time 14.97 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:30 PM PST 23
Peak memory 210588 kb
Host smart-5caeb166-e320-4d67-a708-70c096e6bcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483507680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2483507680
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3901575217
Short name T165
Test name
Test status
Simulation time 184219293402 ps
CPU time 387.75 seconds
Started Dec 27 12:27:01 PM PST 23
Finished Dec 27 12:33:52 PM PST 23
Peak memory 223376 kb
Host smart-513ebed1-6c0d-4e7c-b17b-69edb7f7b8b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901575217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3901575217
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3582032874
Short name T331
Test name
Test status
Simulation time 1654593471 ps
CPU time 11.54 seconds
Started Dec 27 12:28:05 PM PST 23
Finished Dec 27 12:28:51 PM PST 23
Peak memory 210696 kb
Host smart-35efaa40-0135-4152-9dad-dfab32f13d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582032874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3582032874
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2684015202
Short name T395
Test name
Test status
Simulation time 12959461458 ps
CPU time 11.62 seconds
Started Dec 27 12:28:09 PM PST 23
Finished Dec 27 12:28:58 PM PST 23
Peak memory 210536 kb
Host smart-9857488c-b5e8-47ce-ad6c-f7ac9131d326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684015202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2684015202
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3460827058
Short name T19
Test name
Test status
Simulation time 9065540572 ps
CPU time 17.65 seconds
Started Dec 27 12:27:01 PM PST 23
Finished Dec 27 12:27:41 PM PST 23
Peak memory 211264 kb
Host smart-567e4721-ad8a-49bc-96c6-9bbf920f6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460827058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3460827058
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.4193409441
Short name T328
Test name
Test status
Simulation time 2102293652 ps
CPU time 21.89 seconds
Started Dec 27 12:28:13 PM PST 23
Finished Dec 27 12:29:15 PM PST 23
Peak memory 212484 kb
Host smart-07c3c425-1482-4610-a746-023133731ffa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193409441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.4193409441
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.510379490
Short name T13
Test name
Test status
Simulation time 25738882780 ps
CPU time 710.8 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:37:59 PM PST 23
Peak memory 232484 kb
Host smart-6d7a0066-efe0-4abe-b697-d56a8ed52218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510379490 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.510379490
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3735515030
Short name T426
Test name
Test status
Simulation time 6009354336 ps
CPU time 13.05 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:29:38 PM PST 23
Peak memory 210532 kb
Host smart-e58e54d0-e11c-4a27-82ec-0c013fecd46d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735515030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3735515030
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3730500661
Short name T57
Test name
Test status
Simulation time 31217418576 ps
CPU time 172.94 seconds
Started Dec 27 12:26:54 PM PST 23
Finished Dec 27 12:30:08 PM PST 23
Peak memory 237036 kb
Host smart-82d0a780-466b-41c8-ab47-c4ad43048a76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730500661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3730500661
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2454836924
Short name T375
Test name
Test status
Simulation time 18094776970 ps
CPU time 35.97 seconds
Started Dec 27 12:21:45 PM PST 23
Finished Dec 27 12:22:21 PM PST 23
Peak memory 210956 kb
Host smart-279a75f7-9383-49d9-a4f4-d498a736db40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454836924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2454836924
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.124697448
Short name T161
Test name
Test status
Simulation time 1885380763 ps
CPU time 15.32 seconds
Started Dec 27 12:27:20 PM PST 23
Finished Dec 27 12:28:04 PM PST 23
Peak memory 209960 kb
Host smart-4e1b6821-5b35-4e89-8a36-ec09defb7714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124697448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.124697448
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3554047138
Short name T367
Test name
Test status
Simulation time 2398588349 ps
CPU time 28.95 seconds
Started Dec 27 12:26:57 PM PST 23
Finished Dec 27 12:27:47 PM PST 23
Peak memory 212244 kb
Host smart-af7abc66-f4ae-471d-93bc-ecc5998cc2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554047138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3554047138
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3855579696
Short name T166
Test name
Test status
Simulation time 41365736365 ps
CPU time 86.6 seconds
Started Dec 27 12:26:39 PM PST 23
Finished Dec 27 12:28:25 PM PST 23
Peak memory 216188 kb
Host smart-7a9ffea3-cfdd-4ce9-b1b9-985988bc7304
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855579696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3855579696
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1517227601
Short name T112
Test name
Test status
Simulation time 317097521153 ps
CPU time 4789.58 seconds
Started Dec 27 12:25:35 PM PST 23
Finished Dec 27 01:45:32 PM PST 23
Peak memory 237064 kb
Host smart-4d366545-ab7b-4509-ba86-9b07d13a10b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517227601 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1517227601
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.2828368823
Short name T158
Test name
Test status
Simulation time 1544384412 ps
CPU time 12.83 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:28:59 PM PST 23
Peak memory 210024 kb
Host smart-fe11eef8-16b9-4e9d-a5b5-a7fa81c874a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828368823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.2828368823
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2436066371
Short name T56
Test name
Test status
Simulation time 33127740649 ps
CPU time 214.53 seconds
Started Dec 27 12:28:59 PM PST 23
Finished Dec 27 12:33:28 PM PST 23
Peak memory 211832 kb
Host smart-09d3b28e-31a0-4277-85d7-73c768cacf02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436066371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2436066371
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.3933390747
Short name T193
Test name
Test status
Simulation time 1838678326 ps
CPU time 9.59 seconds
Started Dec 27 12:27:25 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 210160 kb
Host smart-95e3c091-4b9c-4cfa-8bde-3e6e8f7b36ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933390747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.3933390747
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1118701504
Short name T217
Test name
Test status
Simulation time 99596576 ps
CPU time 5.6 seconds
Started Dec 27 12:20:08 PM PST 23
Finished Dec 27 12:20:15 PM PST 23
Peak memory 210708 kb
Host smart-39fb05e0-3780-481b-b264-5c9322a20136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118701504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1118701504
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3187415612
Short name T182
Test name
Test status
Simulation time 7572680271 ps
CPU time 23.93 seconds
Started Dec 27 12:29:02 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 213104 kb
Host smart-4383b762-2bde-4e68-8810-ee8977b0301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187415612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3187415612
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.456898795
Short name T218
Test name
Test status
Simulation time 144220484116 ps
CPU time 103.05 seconds
Started Dec 27 12:28:35 PM PST 23
Finished Dec 27 12:31:08 PM PST 23
Peak memory 216144 kb
Host smart-4aaa62a1-41a9-4f53-97c9-19bec2564a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456898795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 26.rom_ctrl_stress_all.456898795
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.2221151770
Short name T385
Test name
Test status
Simulation time 57589995236 ps
CPU time 716.21 seconds
Started Dec 27 12:27:32 PM PST 23
Finished Dec 27 12:39:57 PM PST 23
Peak memory 232056 kb
Host smart-a9cba453-3add-4744-bdfc-43c7e050c524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221151770 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.2221151770
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2467570137
Short name T369
Test name
Test status
Simulation time 175737974 ps
CPU time 5.24 seconds
Started Dec 27 12:25:18 PM PST 23
Finished Dec 27 12:25:33 PM PST 23
Peak memory 210228 kb
Host smart-2bb34cc7-367c-4997-85c0-9c6f3132b9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467570137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2467570137
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.4100986071
Short name T247
Test name
Test status
Simulation time 4455292100 ps
CPU time 149.98 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 218624 kb
Host smart-24f92f0c-94ab-4bc1-abfb-be058ccedbc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100986071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.4100986071
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3036850029
Short name T416
Test name
Test status
Simulation time 39751764459 ps
CPU time 24.95 seconds
Started Dec 27 12:25:18 PM PST 23
Finished Dec 27 12:25:53 PM PST 23
Peak memory 210556 kb
Host smart-c9943244-a92c-4584-a4de-98f92c81455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036850029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3036850029
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1036083769
Short name T290
Test name
Test status
Simulation time 1889550665 ps
CPU time 5.81 seconds
Started Dec 27 12:26:47 PM PST 23
Finished Dec 27 12:27:14 PM PST 23
Peak memory 210600 kb
Host smart-5cba4cb0-d0ce-4ade-bb3e-4f2eef5306f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036083769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1036083769
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2561337677
Short name T167
Test name
Test status
Simulation time 3611470852 ps
CPU time 9.91 seconds
Started Dec 27 12:28:44 PM PST 23
Finished Dec 27 12:29:46 PM PST 23
Peak memory 211740 kb
Host smart-03732ead-23b5-401b-a871-0756baeb2e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561337677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2561337677
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.4151394266
Short name T196
Test name
Test status
Simulation time 1099543043 ps
CPU time 15.91 seconds
Started Dec 27 12:28:40 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 215244 kb
Host smart-ee62f4ae-40ae-4006-bd60-b85e7a8b80f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151394266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.4151394266
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.2978043856
Short name T53
Test name
Test status
Simulation time 494099505911 ps
CPU time 4836.56 seconds
Started Dec 27 12:44:02 PM PST 23
Finished Dec 27 02:04:52 PM PST 23
Peak memory 260048 kb
Host smart-9e09b5ae-d3fa-4297-b35f-c5655fd10087
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978043856 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.2978043856
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1140841188
Short name T358
Test name
Test status
Simulation time 826505122 ps
CPU time 7.18 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:25:39 PM PST 23
Peak memory 209592 kb
Host smart-315156fe-aa77-40a3-b90c-80a862521181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140841188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1140841188
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.4230695443
Short name T374
Test name
Test status
Simulation time 192258624434 ps
CPU time 282.98 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:30:15 PM PST 23
Peak memory 234952 kb
Host smart-16ceb6de-17cc-43a1-a1b6-161acf884ce7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230695443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.4230695443
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3130353081
Short name T237
Test name
Test status
Simulation time 1277032610 ps
CPU time 9.94 seconds
Started Dec 27 12:48:22 PM PST 23
Finished Dec 27 12:48:38 PM PST 23
Peak memory 210980 kb
Host smart-c85ad6a4-ac43-4fe7-9a2a-a499f858f3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130353081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3130353081
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2605787015
Short name T197
Test name
Test status
Simulation time 2563813834 ps
CPU time 9.45 seconds
Started Dec 27 12:25:41 PM PST 23
Finished Dec 27 12:25:58 PM PST 23
Peak memory 210816 kb
Host smart-bfe092d4-da1a-4d30-b4cd-0b57f22a1458
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605787015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2605787015
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2813790227
Short name T190
Test name
Test status
Simulation time 1826321607 ps
CPU time 19.07 seconds
Started Dec 27 12:37:41 PM PST 23
Finished Dec 27 12:38:10 PM PST 23
Peak memory 212216 kb
Host smart-dc82f56f-1eab-4574-917e-3bf9a50d1f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813790227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2813790227
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.2215577683
Short name T368
Test name
Test status
Simulation time 6784521320 ps
CPU time 44.56 seconds
Started Dec 27 12:20:08 PM PST 23
Finished Dec 27 12:20:54 PM PST 23
Peak memory 217676 kb
Host smart-c55e918b-f0b8-4cbf-a752-d000c7cc94be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215577683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.2215577683
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2983098362
Short name T386
Test name
Test status
Simulation time 80922392326 ps
CPU time 1464.1 seconds
Started Dec 27 12:22:40 PM PST 23
Finished Dec 27 12:47:09 PM PST 23
Peak memory 233960 kb
Host smart-16045f5e-04f4-463f-b349-ef56dbc47b65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983098362 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2983098362
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3184986718
Short name T429
Test name
Test status
Simulation time 8075699224 ps
CPU time 15.91 seconds
Started Dec 27 12:28:15 PM PST 23
Finished Dec 27 12:29:12 PM PST 23
Peak memory 210448 kb
Host smart-545362e7-4ba0-488f-8061-e8f66ab42074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184986718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3184986718
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2802830105
Short name T404
Test name
Test status
Simulation time 192694151472 ps
CPU time 456.85 seconds
Started Dec 27 12:25:18 PM PST 23
Finished Dec 27 12:33:05 PM PST 23
Peak memory 235192 kb
Host smart-453ffde1-ff97-4b09-b2f9-f8651956d7e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802830105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2802830105
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1899805971
Short name T363
Test name
Test status
Simulation time 175775429 ps
CPU time 9.23 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:09 PM PST 23
Peak memory 210912 kb
Host smart-6f80b820-8352-4b5c-8782-cf520014f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899805971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1899805971
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1325458706
Short name T303
Test name
Test status
Simulation time 1740731854 ps
CPU time 14.69 seconds
Started Dec 27 12:28:16 PM PST 23
Finished Dec 27 12:29:12 PM PST 23
Peak memory 210248 kb
Host smart-1ddb2466-be4c-4f0a-890b-f419a5a4207a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325458706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1325458706
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.806557287
Short name T9
Test name
Test status
Simulation time 346884859 ps
CPU time 12.15 seconds
Started Dec 27 12:27:52 PM PST 23
Finished Dec 27 12:28:37 PM PST 23
Peak memory 212136 kb
Host smart-791dca26-03fd-4dff-b367-8ce74151b4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806557287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.806557287
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3619954040
Short name T341
Test name
Test status
Simulation time 104526869171 ps
CPU time 88.05 seconds
Started Dec 27 12:22:23 PM PST 23
Finished Dec 27 12:23:52 PM PST 23
Peak memory 219092 kb
Host smart-207d55b4-0985-461c-b4d2-925143561f04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619954040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3619954040
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.537882744
Short name T315
Test name
Test status
Simulation time 5857517907 ps
CPU time 13.82 seconds
Started Dec 27 12:24:38 PM PST 23
Finished Dec 27 12:24:53 PM PST 23
Peak memory 210100 kb
Host smart-dbf6a28d-1950-4cd7-b3cd-39d90be7aab3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537882744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.537882744
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1402631087
Short name T224
Test name
Test status
Simulation time 65702113619 ps
CPU time 421.98 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 226592 kb
Host smart-1f6a9f6c-ff2c-4b53-bca2-3493f8ee00ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402631087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1402631087
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2045465361
Short name T179
Test name
Test status
Simulation time 168703992 ps
CPU time 9.9 seconds
Started Dec 27 12:25:04 PM PST 23
Finished Dec 27 12:25:16 PM PST 23
Peak memory 210840 kb
Host smart-7a304b3b-17f2-424a-ad82-4e0b832e936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045465361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2045465361
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1291639555
Short name T407
Test name
Test status
Simulation time 2118020701 ps
CPU time 17 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:25:13 PM PST 23
Peak memory 210708 kb
Host smart-47de64dd-5a4d-40b9-8b8d-f30db34b93fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291639555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1291639555
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1383358040
Short name T46
Test name
Test status
Simulation time 1759591178 ps
CPU time 65.96 seconds
Started Dec 27 12:21:53 PM PST 23
Finished Dec 27 12:23:00 PM PST 23
Peak memory 235792 kb
Host smart-b8d1f8f3-f98c-417d-9901-6ad2c5527571
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383358040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1383358040
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1450125986
Short name T346
Test name
Test status
Simulation time 187921752 ps
CPU time 10.66 seconds
Started Dec 27 12:24:55 PM PST 23
Finished Dec 27 12:25:08 PM PST 23
Peak memory 212644 kb
Host smart-e6e8aabf-08ff-41d4-9b44-f0dfa6b6a1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450125986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1450125986
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3088120353
Short name T183
Test name
Test status
Simulation time 38272722983 ps
CPU time 81.59 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:26:51 PM PST 23
Peak memory 215960 kb
Host smart-e33dfb42-d1e7-400b-be95-7b35f1a9597e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088120353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3088120353
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.629296483
Short name T213
Test name
Test status
Simulation time 2082075727 ps
CPU time 15.21 seconds
Started Dec 27 12:25:42 PM PST 23
Finished Dec 27 12:26:05 PM PST 23
Peak memory 209336 kb
Host smart-d05bb916-b7e3-411d-9f91-bae46fcf7982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629296483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.629296483
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2129965538
Short name T332
Test name
Test status
Simulation time 34192636888 ps
CPU time 315.78 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:31:23 PM PST 23
Peak memory 236216 kb
Host smart-f2a31954-e435-4fd2-a690-33e74e8fcb52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129965538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2129965538
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1233220246
Short name T293
Test name
Test status
Simulation time 15603345489 ps
CPU time 32.31 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:26:39 PM PST 23
Peak memory 211056 kb
Host smart-7cab492e-aff6-46d1-a7cf-b246637d6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233220246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1233220246
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.130454551
Short name T361
Test name
Test status
Simulation time 12911785349 ps
CPU time 16.71 seconds
Started Dec 27 12:26:53 PM PST 23
Finished Dec 27 12:27:31 PM PST 23
Peak memory 210544 kb
Host smart-69c184bf-165a-483c-8fcb-5810961c87bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=130454551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.130454551
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.534476885
Short name T174
Test name
Test status
Simulation time 3540832017 ps
CPU time 28.86 seconds
Started Dec 27 12:27:01 PM PST 23
Finished Dec 27 12:27:53 PM PST 23
Peak memory 210876 kb
Host smart-f906740e-d3c8-4980-9be1-9fd3244a1a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534476885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.534476885
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.3823587987
Short name T219
Test name
Test status
Simulation time 563559782 ps
CPU time 11.56 seconds
Started Dec 27 12:26:54 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 212564 kb
Host smart-02dbef15-1f26-4d45-bef0-58cb7160ac05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823587987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.3823587987
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1071020598
Short name T326
Test name
Test status
Simulation time 1797505687 ps
CPU time 14.34 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:30 PM PST 23
Peak memory 210560 kb
Host smart-f0d91561-7d9d-4298-923c-8273c65b81c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071020598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1071020598
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3787740412
Short name T221
Test name
Test status
Simulation time 255785098292 ps
CPU time 508.8 seconds
Started Dec 27 12:25:31 PM PST 23
Finished Dec 27 12:34:07 PM PST 23
Peak memory 227980 kb
Host smart-f2eb3da9-5aa3-46ad-99d5-b4192e25a144
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787740412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3787740412
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1172695428
Short name T274
Test name
Test status
Simulation time 57373440126 ps
CPU time 27.87 seconds
Started Dec 27 12:26:00 PM PST 23
Finished Dec 27 12:26:35 PM PST 23
Peak memory 210904 kb
Host smart-100bf518-a313-440e-9e21-6d64566e1c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172695428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1172695428
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1121267589
Short name T147
Test name
Test status
Simulation time 5007594400 ps
CPU time 11.1 seconds
Started Dec 27 12:25:13 PM PST 23
Finished Dec 27 12:25:28 PM PST 23
Peak memory 209968 kb
Host smart-14a72a92-b1f2-425b-8bfa-00c6a4f4d4ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121267589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1121267589
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3630931201
Short name T212
Test name
Test status
Simulation time 729977045 ps
CPU time 9.65 seconds
Started Dec 27 12:25:32 PM PST 23
Finished Dec 27 12:25:48 PM PST 23
Peak memory 212616 kb
Host smart-ab403d23-1d37-4867-b961-9bcabc2aa900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630931201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3630931201
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1922101586
Short name T280
Test name
Test status
Simulation time 2012604868 ps
CPU time 17.64 seconds
Started Dec 27 12:25:42 PM PST 23
Finished Dec 27 12:26:07 PM PST 23
Peak memory 209456 kb
Host smart-a87e769b-e43f-4d7a-a794-724a2d2ff516
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922101586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1922101586
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2054899810
Short name T48
Test name
Test status
Simulation time 85841492 ps
CPU time 4.33 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:26:11 PM PST 23
Peak memory 210572 kb
Host smart-bfd4592b-a91b-4657-b79a-d29238c3f021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054899810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2054899810
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2074894913
Short name T406
Test name
Test status
Simulation time 110114076840 ps
CPU time 285.73 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:30:53 PM PST 23
Peak memory 237108 kb
Host smart-f5d94356-0830-4661-b666-80c000f91087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074894913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2074894913
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.754756959
Short name T309
Test name
Test status
Simulation time 692726366 ps
CPU time 9.37 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 210668 kb
Host smart-df15e8a8-c392-4615-8acb-a68c3a40d7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754756959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.754756959
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.2684644868
Short name T317
Test name
Test status
Simulation time 5000831484 ps
CPU time 14.57 seconds
Started Dec 27 12:26:38 PM PST 23
Finished Dec 27 12:27:12 PM PST 23
Peak memory 209988 kb
Host smart-cdb60ce0-3548-4b6b-bded-85e4fd33a83b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684644868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.2684644868
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.129321867
Short name T321
Test name
Test status
Simulation time 6015890755 ps
CPU time 34.86 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:51 PM PST 23
Peak memory 213144 kb
Host smart-36cfcbf5-7dea-4408-88ba-506be59fc6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129321867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.129321867
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4196740121
Short name T250
Test name
Test status
Simulation time 20643014129 ps
CPU time 56.41 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:27:03 PM PST 23
Peak memory 216676 kb
Host smart-127e7600-0e47-42f8-b1db-2790e59037fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196740121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4196740121
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1232634938
Short name T172
Test name
Test status
Simulation time 30362399960 ps
CPU time 7130.86 seconds
Started Dec 27 12:29:01 PM PST 23
Finished Dec 27 02:28:48 PM PST 23
Peak memory 232876 kb
Host smart-f8988d0c-9b07-4f7c-a2c5-7f6f32c77192
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232634938 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1232634938
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1376737723
Short name T305
Test name
Test status
Simulation time 676199898 ps
CPU time 8.16 seconds
Started Dec 27 12:27:11 PM PST 23
Finished Dec 27 12:27:45 PM PST 23
Peak memory 210604 kb
Host smart-eae409cf-82fb-432c-9473-10b8796d4326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376737723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1376737723
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.255976656
Short name T389
Test name
Test status
Simulation time 130150169725 ps
CPU time 343.3 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 237000 kb
Host smart-6b816a5a-8aa8-400b-b7e6-b0ae86e5bcd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255976656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.255976656
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.3145888730
Short name T312
Test name
Test status
Simulation time 11080910970 ps
CPU time 31.84 seconds
Started Dec 27 12:26:54 PM PST 23
Finished Dec 27 12:27:47 PM PST 23
Peak memory 210940 kb
Host smart-9a0dd28a-72d0-4eb8-ace1-e47ef01e2136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145888730 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.3145888730
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3189638350
Short name T257
Test name
Test status
Simulation time 6798098027 ps
CPU time 14.84 seconds
Started Dec 27 12:22:12 PM PST 23
Finished Dec 27 12:22:27 PM PST 23
Peak memory 210880 kb
Host smart-75728617-f70d-4f45-84a1-d45b2472610f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189638350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3189638350
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.1506566447
Short name T154
Test name
Test status
Simulation time 15315488120 ps
CPU time 30.38 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:47 PM PST 23
Peak memory 213276 kb
Host smart-090e3cdf-63a1-4a20-84f7-29e62f91ab80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506566447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.1506566447
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.330994283
Short name T52
Test name
Test status
Simulation time 18319648184 ps
CPU time 102.62 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:28:59 PM PST 23
Peak memory 217572 kb
Host smart-488ef9a8-c55d-43c3-9f30-5da8eef304ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330994283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.rom_ctrl_stress_all.330994283
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2049374730
Short name T427
Test name
Test status
Simulation time 113360949838 ps
CPU time 3760.16 seconds
Started Dec 27 12:27:17 PM PST 23
Finished Dec 27 01:30:25 PM PST 23
Peak memory 250932 kb
Host smart-6b16b6ae-5e4e-4498-a422-7ca61de249a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049374730 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2049374730
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3183428901
Short name T7
Test name
Test status
Simulation time 2036729747 ps
CPU time 15.95 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:46 PM PST 23
Peak memory 210508 kb
Host smart-6c22f64f-a859-40ca-bf63-0d2fa2e441b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183428901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3183428901
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1112267903
Short name T240
Test name
Test status
Simulation time 45663489546 ps
CPU time 151.09 seconds
Started Dec 27 12:25:00 PM PST 23
Finished Dec 27 12:27:34 PM PST 23
Peak memory 234012 kb
Host smart-9fbc5213-e5be-4569-881a-a39767d30b1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112267903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1112267903
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.349087038
Short name T24
Test name
Test status
Simulation time 168711128 ps
CPU time 9.89 seconds
Started Dec 27 12:19:58 PM PST 23
Finished Dec 27 12:20:09 PM PST 23
Peak memory 210984 kb
Host smart-e85266d0-25a9-42b2-9812-09c664fd5e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349087038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.349087038
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.875670458
Short name T424
Test name
Test status
Simulation time 1553353723 ps
CPU time 13.66 seconds
Started Dec 27 12:26:40 PM PST 23
Finished Dec 27 12:27:13 PM PST 23
Peak memory 209752 kb
Host smart-02b803b2-1dd0-4c94-9a62-b1f18c184d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875670458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.875670458
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.2488002213
Short name T357
Test name
Test status
Simulation time 262835809 ps
CPU time 9.84 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:26 PM PST 23
Peak memory 212124 kb
Host smart-95f2c3b0-d3f5-428a-9ae7-576e2f5392d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488002213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2488002213
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2574898724
Short name T191
Test name
Test status
Simulation time 12824955370 ps
CPU time 53.74 seconds
Started Dec 27 12:25:19 PM PST 23
Finished Dec 27 12:26:23 PM PST 23
Peak memory 215192 kb
Host smart-6503c638-80f8-4f0c-a47a-7c12082de6aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574898724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2574898724
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.591276043
Short name T210
Test name
Test status
Simulation time 49946032203 ps
CPU time 846.82 seconds
Started Dec 27 12:27:03 PM PST 23
Finished Dec 27 12:41:33 PM PST 23
Peak memory 235052 kb
Host smart-255449b0-4f2c-448c-9595-e94c73280937
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591276043 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.591276043
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.187833072
Short name T401
Test name
Test status
Simulation time 684310489 ps
CPU time 5.41 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:25:36 PM PST 23
Peak memory 210808 kb
Host smart-fa70d3a3-9a9e-4da9-abea-62415a685496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187833072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.187833072
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1032228140
Short name T233
Test name
Test status
Simulation time 37211795804 ps
CPU time 349.92 seconds
Started Dec 27 12:24:59 PM PST 23
Finished Dec 27 12:30:52 PM PST 23
Peak memory 223332 kb
Host smart-126285d8-a00b-4ac8-9556-ede0ae86476a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032228140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1032228140
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2991619510
Short name T311
Test name
Test status
Simulation time 4163790800 ps
CPU time 34.57 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:26:05 PM PST 23
Peak memory 210832 kb
Host smart-89322a2c-8631-4e4f-9005-904b9823566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991619510 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2991619510
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.254989176
Short name T204
Test name
Test status
Simulation time 1106823133 ps
CPU time 8.74 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:38 PM PST 23
Peak memory 210332 kb
Host smart-1aa8620a-81d3-44d4-9c5a-5e936e492323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254989176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.254989176
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.611883736
Short name T20
Test name
Test status
Simulation time 11115737715 ps
CPU time 20.25 seconds
Started Dec 27 12:24:41 PM PST 23
Finished Dec 27 12:25:02 PM PST 23
Peak memory 212700 kb
Host smart-f5d50031-52db-404a-8b41-48a33a625697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611883736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.611883736
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.754328607
Short name T284
Test name
Test status
Simulation time 565033811 ps
CPU time 15.07 seconds
Started Dec 27 12:27:44 PM PST 23
Finished Dec 27 12:28:30 PM PST 23
Peak memory 214704 kb
Host smart-63ab015e-4371-4f8b-b33b-943e287f0993
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754328607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.754328607
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1508868287
Short name T425
Test name
Test status
Simulation time 7733064846 ps
CPU time 16 seconds
Started Dec 27 12:21:18 PM PST 23
Finished Dec 27 12:21:35 PM PST 23
Peak memory 210796 kb
Host smart-513775b7-6f18-4a40-bee5-2ac2f6a256a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508868287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1508868287
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3089160622
Short name T245
Test name
Test status
Simulation time 113264328314 ps
CPU time 302.67 seconds
Started Dec 27 12:24:42 PM PST 23
Finished Dec 27 12:29:45 PM PST 23
Peak memory 237128 kb
Host smart-0e9cdede-73b7-47e0-8d2b-988bfc4d18f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089160622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3089160622
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.835362405
Short name T29
Test name
Test status
Simulation time 3073303907 ps
CPU time 19.04 seconds
Started Dec 27 12:22:15 PM PST 23
Finished Dec 27 12:22:35 PM PST 23
Peak memory 210896 kb
Host smart-c6681ca3-a669-4df6-a988-a60c9eab5039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835362405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.835362405
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1098041775
Short name T231
Test name
Test status
Simulation time 2867929435 ps
CPU time 12.34 seconds
Started Dec 27 12:24:50 PM PST 23
Finished Dec 27 12:25:04 PM PST 23
Peak memory 210832 kb
Host smart-b0dbfba2-24e0-482c-9942-ecd9fd2735dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1098041775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1098041775
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2310621708
Short name T340
Test name
Test status
Simulation time 6714527745 ps
CPU time 32.95 seconds
Started Dec 27 12:25:20 PM PST 23
Finished Dec 27 12:26:03 PM PST 23
Peak memory 212792 kb
Host smart-73942bd2-e0d2-49d5-b46a-f30babca3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310621708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2310621708
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3636107650
Short name T49
Test name
Test status
Simulation time 293742896 ps
CPU time 18.01 seconds
Started Dec 27 12:26:48 PM PST 23
Finished Dec 27 12:27:27 PM PST 23
Peak memory 214940 kb
Host smart-570c6777-85db-4226-8f14-efb6621a804e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636107650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3636107650
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1490492292
Short name T298
Test name
Test status
Simulation time 1025097459 ps
CPU time 10.84 seconds
Started Dec 27 12:22:11 PM PST 23
Finished Dec 27 12:22:23 PM PST 23
Peak memory 210744 kb
Host smart-6713b790-e5f0-41d4-9edc-9019c6fa53dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490492292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1490492292
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2932447490
Short name T287
Test name
Test status
Simulation time 6013562595 ps
CPU time 26.29 seconds
Started Dec 27 12:29:10 PM PST 23
Finished Dec 27 12:30:30 PM PST 23
Peak memory 211304 kb
Host smart-ddc5f8e9-f73d-418e-9b4c-039a929289cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932447490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2932447490
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2454309445
Short name T300
Test name
Test status
Simulation time 4842479982 ps
CPU time 16.27 seconds
Started Dec 27 12:24:46 PM PST 23
Finished Dec 27 12:25:03 PM PST 23
Peak memory 210876 kb
Host smart-222d51f1-0ff4-42fd-aef6-c35d1451a6f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454309445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2454309445
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1721364139
Short name T203
Test name
Test status
Simulation time 774338625 ps
CPU time 14.33 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:48 PM PST 23
Peak memory 211192 kb
Host smart-9a707ef1-98dd-49e4-9d06-6bbc4258baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721364139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1721364139
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1517036415
Short name T400
Test name
Test status
Simulation time 1700157626 ps
CPU time 19.69 seconds
Started Dec 27 12:27:16 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 214244 kb
Host smart-e50a1d49-3119-48bd-8762-81dd8310d95a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517036415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1517036415
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.140025185
Short name T252
Test name
Test status
Simulation time 2311662431 ps
CPU time 8.31 seconds
Started Dec 27 12:21:50 PM PST 23
Finished Dec 27 12:21:59 PM PST 23
Peak memory 210768 kb
Host smart-2f0a750f-ebf0-4e1d-a489-e0ca4ad8a12f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140025185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.140025185
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2368220633
Short name T362
Test name
Test status
Simulation time 3802893036 ps
CPU time 125.1 seconds
Started Dec 27 12:28:51 PM PST 23
Finished Dec 27 12:31:50 PM PST 23
Peak memory 223936 kb
Host smart-ff81cd06-a342-4dc3-95bf-0060f2016902
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368220633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2368220633
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1130038201
Short name T28
Test name
Test status
Simulation time 28119002675 ps
CPU time 21.91 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 209900 kb
Host smart-0ee60cfd-a786-4280-87ab-d7f4c79c98cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130038201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1130038201
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1474470406
Short name T391
Test name
Test status
Simulation time 379284175 ps
CPU time 5.53 seconds
Started Dec 27 12:28:10 PM PST 23
Finished Dec 27 12:28:55 PM PST 23
Peak memory 209720 kb
Host smart-d56e3895-cb0c-4620-b75d-a49f1d515b8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474470406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1474470406
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.1385807206
Short name T159
Test name
Test status
Simulation time 735476900 ps
CPU time 16.28 seconds
Started Dec 27 12:21:31 PM PST 23
Finished Dec 27 12:21:49 PM PST 23
Peak memory 212524 kb
Host smart-ec76b188-0901-4858-a5b2-c6b0c8233f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385807206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.1385807206
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3426389177
Short name T202
Test name
Test status
Simulation time 1140396833 ps
CPU time 14.84 seconds
Started Dec 27 12:28:08 PM PST 23
Finished Dec 27 12:29:01 PM PST 23
Peak memory 214480 kb
Host smart-7f0039a5-10c2-4118-9ada-a9c76f8b7d8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426389177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3426389177
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.4106266247
Short name T403
Test name
Test status
Simulation time 19682448626 ps
CPU time 283.93 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:34:52 PM PST 23
Peak memory 224164 kb
Host smart-8c0bce23-88f6-4678-9855-3b7803f91ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106266247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.4106266247
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3952518970
Short name T1
Test name
Test status
Simulation time 7200140817 ps
CPU time 15.03 seconds
Started Dec 27 12:28:28 PM PST 23
Finished Dec 27 12:29:31 PM PST 23
Peak memory 210488 kb
Host smart-9606c0a6-df2d-4644-9414-31e8d4826aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952518970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3952518970
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1365193799
Short name T192
Test name
Test status
Simulation time 21855116274 ps
CPU time 278.02 seconds
Started Dec 27 12:28:55 PM PST 23
Finished Dec 27 12:34:28 PM PST 23
Peak memory 237204 kb
Host smart-e2f0a040-0fd1-45f9-a22f-84d56ee65618
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365193799 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1365193799
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2527568804
Short name T371
Test name
Test status
Simulation time 10852662093 ps
CPU time 25.29 seconds
Started Dec 27 12:29:25 PM PST 23
Finished Dec 27 12:30:45 PM PST 23
Peak memory 210848 kb
Host smart-3192748d-63fd-4fa6-85a0-4e43ee44b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527568804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2527568804
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3643298057
Short name T164
Test name
Test status
Simulation time 225514007 ps
CPU time 5.58 seconds
Started Dec 27 12:24:35 PM PST 23
Finished Dec 27 12:24:42 PM PST 23
Peak memory 210852 kb
Host smart-e9119801-bb17-4b6e-b0da-bdca92e3fe07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3643298057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3643298057
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3293018172
Short name T319
Test name
Test status
Simulation time 17696537121 ps
CPU time 18.23 seconds
Started Dec 27 12:28:54 PM PST 23
Finished Dec 27 12:30:07 PM PST 23
Peak memory 212916 kb
Host smart-20e1dc4a-f579-4d75-8d5a-a7087d12e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293018172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3293018172
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.949282229
Short name T198
Test name
Test status
Simulation time 3627601507 ps
CPU time 31.31 seconds
Started Dec 27 12:28:42 PM PST 23
Finished Dec 27 12:30:06 PM PST 23
Peak memory 212040 kb
Host smart-e789523e-d535-4f3d-a2dd-2d9173429c0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949282229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.949282229
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.555886931
Short name T152
Test name
Test status
Simulation time 54689201341 ps
CPU time 4315.29 seconds
Started Dec 27 12:29:19 PM PST 23
Finished Dec 27 01:42:10 PM PST 23
Peak memory 235100 kb
Host smart-49f9fe48-f791-4bd6-9672-bf0261e34bd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555886931 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.555886931
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.3306652628
Short name T282
Test name
Test status
Simulation time 691503090 ps
CPU time 4.22 seconds
Started Dec 27 12:27:16 PM PST 23
Finished Dec 27 12:27:47 PM PST 23
Peak memory 210552 kb
Host smart-0e7885b6-cfff-46fa-aa97-f224d8ed516b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306652628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.3306652628
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2141318648
Short name T279
Test name
Test status
Simulation time 4573958444 ps
CPU time 71.27 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:27:51 PM PST 23
Peak memory 227360 kb
Host smart-b8fda142-fa4a-4799-a737-c0791c3f9375
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141318648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2141318648
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2914416436
Short name T323
Test name
Test status
Simulation time 1006365777 ps
CPU time 9.21 seconds
Started Dec 27 12:25:21 PM PST 23
Finished Dec 27 12:25:41 PM PST 23
Peak memory 209564 kb
Host smart-1d4521f1-341c-434f-bce2-16bab61b402e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914416436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2914416436
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3161171310
Short name T42
Test name
Test status
Simulation time 2093851373 ps
CPU time 70.31 seconds
Started Dec 27 12:25:04 PM PST 23
Finished Dec 27 12:26:17 PM PST 23
Peak memory 236680 kb
Host smart-4d591fe6-227f-4a6b-a390-f9de367133b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161171310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3161171310
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2898041354
Short name T234
Test name
Test status
Simulation time 191356265 ps
CPU time 10.41 seconds
Started Dec 27 12:20:24 PM PST 23
Finished Dec 27 12:20:36 PM PST 23
Peak memory 212492 kb
Host smart-44cb7363-d049-4b7f-8f36-fab191d4a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898041354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2898041354
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.665156787
Short name T313
Test name
Test status
Simulation time 16262489512 ps
CPU time 38.47 seconds
Started Dec 27 12:26:31 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 213032 kb
Host smart-ea0d0fc3-edc2-477a-a011-7f8a54999da1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665156787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.665156787
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.695059229
Short name T253
Test name
Test status
Simulation time 5410487527 ps
CPU time 12.42 seconds
Started Dec 27 12:27:54 PM PST 23
Finished Dec 27 12:28:39 PM PST 23
Peak memory 210516 kb
Host smart-e2cf0097-5426-4a28-9dbb-e11598ca2f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695059229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.695059229
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3235247552
Short name T308
Test name
Test status
Simulation time 93407996703 ps
CPU time 282.25 seconds
Started Dec 27 12:28:29 PM PST 23
Finished Dec 27 12:34:00 PM PST 23
Peak memory 227760 kb
Host smart-92253e70-d893-45fe-909a-4649df107834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235247552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3235247552
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2181882677
Short name T258
Test name
Test status
Simulation time 721836178 ps
CPU time 9.4 seconds
Started Dec 27 12:26:44 PM PST 23
Finished Dec 27 12:27:15 PM PST 23
Peak memory 210828 kb
Host smart-f859fbac-8484-4e1a-a2bc-c864995248fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181882677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2181882677
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2864554014
Short name T409
Test name
Test status
Simulation time 1362271090 ps
CPU time 13.08 seconds
Started Dec 27 12:29:14 PM PST 23
Finished Dec 27 12:30:21 PM PST 23
Peak memory 210396 kb
Host smart-48684c7a-803b-4640-b137-5758320504a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864554014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2864554014
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.451903457
Short name T230
Test name
Test status
Simulation time 5270171747 ps
CPU time 18.86 seconds
Started Dec 27 12:23:06 PM PST 23
Finished Dec 27 12:23:29 PM PST 23
Peak memory 213092 kb
Host smart-425a599f-b445-4eae-9de6-559f1105d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451903457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.451903457
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2823162296
Short name T214
Test name
Test status
Simulation time 16669046235 ps
CPU time 49.05 seconds
Started Dec 27 12:29:33 PM PST 23
Finished Dec 27 12:31:16 PM PST 23
Peak memory 216064 kb
Host smart-d7853d3c-347e-419d-b508-f17674b38d38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823162296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2823162296
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1656491369
Short name T181
Test name
Test status
Simulation time 3212486261 ps
CPU time 9.91 seconds
Started Dec 27 12:22:49 PM PST 23
Finished Dec 27 12:23:00 PM PST 23
Peak memory 210968 kb
Host smart-d7b47286-f6ae-4c03-af1b-bfdb005ca95b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656491369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1656491369
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3346289191
Short name T383
Test name
Test status
Simulation time 28631653071 ps
CPU time 101.65 seconds
Started Dec 27 12:25:09 PM PST 23
Finished Dec 27 12:26:54 PM PST 23
Peak memory 237168 kb
Host smart-387ef154-bc64-423b-bf4f-330effccd9ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346289191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3346289191
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.243263658
Short name T185
Test name
Test status
Simulation time 17961683034 ps
CPU time 21.68 seconds
Started Dec 27 12:24:51 PM PST 23
Finished Dec 27 12:25:14 PM PST 23
Peak memory 209840 kb
Host smart-6ad66858-d79d-48a6-b8d7-a43a737bea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243263658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.243263658
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1401152454
Short name T366
Test name
Test status
Simulation time 2130262301 ps
CPU time 17.19 seconds
Started Dec 27 12:28:02 PM PST 23
Finished Dec 27 12:28:53 PM PST 23
Peak memory 210476 kb
Host smart-78130513-4248-42e6-bbbf-d610218420ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401152454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1401152454
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2541142632
Short name T195
Test name
Test status
Simulation time 19005987954 ps
CPU time 25.21 seconds
Started Dec 27 12:28:27 PM PST 23
Finished Dec 27 12:29:40 PM PST 23
Peak memory 213000 kb
Host smart-bb9b055a-0641-458b-a26f-28ae86bbd06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541142632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2541142632
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.3338612077
Short name T201
Test name
Test status
Simulation time 5449231465 ps
CPU time 59.02 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:26:09 PM PST 23
Peak memory 215144 kb
Host smart-7462cc73-adf5-42e8-a555-bcf25c64a082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338612077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.3338612077
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.71022004
Short name T17
Test name
Test status
Simulation time 45276856283 ps
CPU time 748.77 seconds
Started Dec 27 12:25:43 PM PST 23
Finished Dec 27 12:38:19 PM PST 23
Peak memory 234664 kb
Host smart-0795efe8-f31c-41b8-8be2-eaa272e32c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71022004 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.71022004
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1393581637
Short name T262
Test name
Test status
Simulation time 1787134096 ps
CPU time 13.76 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:18 PM PST 23
Peak memory 210440 kb
Host smart-dccce25b-f411-4dc5-9604-f48269af0390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393581637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1393581637
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.675885553
Short name T3
Test name
Test status
Simulation time 24529907111 ps
CPU time 115.14 seconds
Started Dec 27 12:25:08 PM PST 23
Finished Dec 27 12:27:07 PM PST 23
Peak memory 232932 kb
Host smart-a9110d98-d1ed-4466-83f9-bdd4ec4eca0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675885553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.675885553
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4082695633
Short name T243
Test name
Test status
Simulation time 17118250191 ps
CPU time 33.74 seconds
Started Dec 27 12:26:42 PM PST 23
Finished Dec 27 12:27:37 PM PST 23
Peak memory 210664 kb
Host smart-40e2ff9c-3636-4aa8-8cfb-6e7fb3efc006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082695633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4082695633
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.1944993683
Short name T146
Test name
Test status
Simulation time 3370805454 ps
CPU time 15.16 seconds
Started Dec 27 12:27:06 PM PST 23
Finished Dec 27 12:27:46 PM PST 23
Peak memory 210624 kb
Host smart-1f2a0feb-b390-4aae-8116-416032bc10f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944993683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.1944993683
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1169708977
Short name T289
Test name
Test status
Simulation time 185163052 ps
CPU time 10.17 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:19 PM PST 23
Peak memory 211528 kb
Host smart-d55ac48f-8c2e-4cfd-8eb4-76f55f87c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169708977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1169708977
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2395060349
Short name T244
Test name
Test status
Simulation time 3596688821 ps
CPU time 32.83 seconds
Started Dec 27 12:25:06 PM PST 23
Finished Dec 27 12:25:42 PM PST 23
Peak memory 215180 kb
Host smart-bafc8f97-9371-4ba4-bad3-5afa39f91e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395060349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2395060349
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.2396585015
Short name T381
Test name
Test status
Simulation time 1447512538 ps
CPU time 11.74 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:26:17 PM PST 23
Peak memory 210536 kb
Host smart-9f42bc6a-dca6-4918-bd6d-c4b54d27b451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396585015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.2396585015
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3035180337
Short name T316
Test name
Test status
Simulation time 33413068973 ps
CPU time 317.06 seconds
Started Dec 27 12:27:35 PM PST 23
Finished Dec 27 12:33:22 PM PST 23
Peak memory 236524 kb
Host smart-9d8c8149-d656-49f1-9580-ef9325cd5085
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035180337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3035180337
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4019314954
Short name T412
Test name
Test status
Simulation time 2267553370 ps
CPU time 22.1 seconds
Started Dec 27 12:25:08 PM PST 23
Finished Dec 27 12:25:33 PM PST 23
Peak memory 210676 kb
Host smart-14ce18e1-825e-43a2-aaa8-5be6f0d3aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019314954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4019314954
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3582091331
Short name T10
Test name
Test status
Simulation time 6539068461 ps
CPU time 15.1 seconds
Started Dec 27 12:25:07 PM PST 23
Finished Dec 27 12:25:25 PM PST 23
Peak memory 210496 kb
Host smart-c3d967ff-dafd-4d75-a438-7f199faed678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3582091331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3582091331
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2385756024
Short name T268
Test name
Test status
Simulation time 183045402 ps
CPU time 10.16 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:15 PM PST 23
Peak memory 212336 kb
Host smart-5dd27ae6-97b3-4675-a6c7-f10a8aafecf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385756024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2385756024
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.1579483459
Short name T170
Test name
Test status
Simulation time 3713654377 ps
CPU time 36.25 seconds
Started Dec 27 12:27:55 PM PST 23
Finished Dec 27 12:29:04 PM PST 23
Peak memory 214876 kb
Host smart-f6e02ab3-e5d4-4935-820b-91b7ae9c1a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579483459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.1579483459
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2433073622
Short name T421
Test name
Test status
Simulation time 160651782649 ps
CPU time 3579.3 seconds
Started Dec 27 12:24:51 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 236248 kb
Host smart-7d9dcef3-18bd-478b-b3e3-2145d998a2f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433073622 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2433073622
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3485200507
Short name T265
Test name
Test status
Simulation time 1646301543 ps
CPU time 13.13 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:17 PM PST 23
Peak memory 210536 kb
Host smart-4db018f4-603a-43f8-8eab-0412ba12357e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485200507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3485200507
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2234371283
Short name T387
Test name
Test status
Simulation time 65644180084 ps
CPU time 280.58 seconds
Started Dec 27 12:26:30 PM PST 23
Finished Dec 27 12:31:25 PM PST 23
Peak memory 211900 kb
Host smart-6133c646-e1a1-45dd-96e7-6da8559cd0ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234371283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2234371283
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1161551780
Short name T408
Test name
Test status
Simulation time 177466041 ps
CPU time 9.18 seconds
Started Dec 27 12:25:59 PM PST 23
Finished Dec 27 12:26:14 PM PST 23
Peak memory 210644 kb
Host smart-38f8c8e8-dc8b-4fc0-99a8-7aeef843ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161551780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1161551780
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.1353002678
Short name T236
Test name
Test status
Simulation time 11298919876 ps
CPU time 13.62 seconds
Started Dec 27 12:26:59 PM PST 23
Finished Dec 27 12:27:34 PM PST 23
Peak memory 210520 kb
Host smart-fbfde94d-fa2d-4909-bdb2-e1737bb0a633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1353002678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.1353002678
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.147411658
Short name T325
Test name
Test status
Simulation time 2468961147 ps
CPU time 24.03 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:26:27 PM PST 23
Peak memory 211776 kb
Host smart-6dfa9df5-ac17-416e-8663-bd9205491cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147411658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.147411658
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.79377033
Short name T359
Test name
Test status
Simulation time 31492438761 ps
CPU time 97.77 seconds
Started Dec 27 12:25:58 PM PST 23
Finished Dec 27 12:27:42 PM PST 23
Peak memory 218700 kb
Host smart-bd28d4f4-8751-4666-b752-ed91a7950d18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79377033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.rom_ctrl_stress_all.79377033
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1838202250
Short name T299
Test name
Test status
Simulation time 2032661544 ps
CPU time 10.52 seconds
Started Dec 27 12:20:21 PM PST 23
Finished Dec 27 12:20:36 PM PST 23
Peak memory 210780 kb
Host smart-5f16f6c8-06fb-4d5a-bcba-243a1bfe9613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838202250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1838202250
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1362048679
Short name T173
Test name
Test status
Simulation time 10208455261 ps
CPU time 152.98 seconds
Started Dec 27 12:24:47 PM PST 23
Finished Dec 27 12:27:21 PM PST 23
Peak memory 236484 kb
Host smart-486822ab-b364-45e9-9b18-bd00b01241f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362048679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1362048679
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3702170810
Short name T364
Test name
Test status
Simulation time 4480764139 ps
CPU time 13.05 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:26:43 PM PST 23
Peak memory 210608 kb
Host smart-77130088-b925-4762-bdef-5b5233bcdd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702170810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3702170810
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1182362463
Short name T206
Test name
Test status
Simulation time 4086919600 ps
CPU time 16.14 seconds
Started Dec 27 12:26:54 PM PST 23
Finished Dec 27 12:27:31 PM PST 23
Peak memory 210504 kb
Host smart-1deb6dbf-ea1c-448c-8144-1152137b7661
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182362463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1182362463
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.2694830251
Short name T184
Test name
Test status
Simulation time 8547908077 ps
CPU time 26.09 seconds
Started Dec 27 12:26:55 PM PST 23
Finished Dec 27 12:27:43 PM PST 23
Peak memory 212552 kb
Host smart-3f43f9eb-6e62-4a71-b3b1-c78ba3792f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694830251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.2694830251
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3163279416
Short name T278
Test name
Test status
Simulation time 213123476 ps
CPU time 12.51 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:27:24 PM PST 23
Peak memory 212276 kb
Host smart-0c6e3b2a-15c8-4da9-8d57-d75ff803b1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163279416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3163279416
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.607686844
Short name T238
Test name
Test status
Simulation time 33041692729 ps
CPU time 1164.01 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:45:54 PM PST 23
Peak memory 229240 kb
Host smart-dc3f8b21-5e1d-4e31-ad3b-d78a31d68c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607686844 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.607686844
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1019500390
Short name T343
Test name
Test status
Simulation time 9154071319 ps
CPU time 10.9 seconds
Started Dec 27 12:27:57 PM PST 23
Finished Dec 27 12:28:42 PM PST 23
Peak memory 210564 kb
Host smart-e851f932-89cf-4671-9107-99a0d4d36582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019500390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1019500390
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2564342551
Short name T55
Test name
Test status
Simulation time 17851668866 ps
CPU time 225.6 seconds
Started Dec 27 12:20:57 PM PST 23
Finished Dec 27 12:24:44 PM PST 23
Peak memory 212204 kb
Host smart-bce2f32a-f23e-4ace-b670-800b8cba73de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564342551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2564342551
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.385284802
Short name T266
Test name
Test status
Simulation time 693599141 ps
CPU time 9.68 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:27:21 PM PST 23
Peak memory 209720 kb
Host smart-929b15ff-3573-4552-9426-32c82bf81cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385284802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.385284802
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3812677651
Short name T310
Test name
Test status
Simulation time 1933587811 ps
CPU time 16.38 seconds
Started Dec 27 12:26:56 PM PST 23
Finished Dec 27 12:27:33 PM PST 23
Peak memory 210444 kb
Host smart-4b104c38-e040-42ee-b074-42d8ecf21659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812677651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3812677651
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.184471599
Short name T50
Test name
Test status
Simulation time 3881755752 ps
CPU time 32.02 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:27:02 PM PST 23
Peak memory 212588 kb
Host smart-7424072b-5f51-4adb-b2d0-8bf66ebc2b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184471599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.184471599
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.160392584
Short name T392
Test name
Test status
Simulation time 183842792 ps
CPU time 6.82 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:21 PM PST 23
Peak memory 210140 kb
Host smart-9ada66b2-52ee-4e1e-940f-66f0bb07a092
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160392584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.160392584
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.375213528
Short name T388
Test name
Test status
Simulation time 36251692270 ps
CPU time 5655.99 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 02:01:29 PM PST 23
Peak memory 230236 kb
Host smart-a8c6fb5a-c3d3-4f6b-81e6-10a65597fadb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375213528 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.375213528
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2924498046
Short name T365
Test name
Test status
Simulation time 5235423292 ps
CPU time 12.67 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 210480 kb
Host smart-7a0905ab-2705-4328-917c-d0d2690e3098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924498046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2924498046
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1737898012
Short name T285
Test name
Test status
Simulation time 54268061672 ps
CPU time 264.83 seconds
Started Dec 27 12:26:17 PM PST 23
Finished Dec 27 12:30:55 PM PST 23
Peak memory 236544 kb
Host smart-34f910bd-fbab-4b4d-8303-14e406f3fa50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737898012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1737898012
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3965375631
Short name T402
Test name
Test status
Simulation time 2449255964 ps
CPU time 24.2 seconds
Started Dec 27 12:26:53 PM PST 23
Finished Dec 27 12:27:38 PM PST 23
Peak memory 210616 kb
Host smart-2918fdf4-4e0d-4574-a381-a08f0092f5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965375631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3965375631
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1534303383
Short name T169
Test name
Test status
Simulation time 828389204 ps
CPU time 10.08 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:27:22 PM PST 23
Peak memory 210348 kb
Host smart-a1dbb0b9-9a4f-4431-94d9-039298251b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534303383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1534303383
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.3753140980
Short name T149
Test name
Test status
Simulation time 28288505308 ps
CPU time 27.22 seconds
Started Dec 27 12:20:08 PM PST 23
Finished Dec 27 12:20:36 PM PST 23
Peak memory 212908 kb
Host smart-bb38d812-0af6-48f6-92ef-0b082b361634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753140980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.3753140980
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3185273894
Short name T59
Test name
Test status
Simulation time 1054080421 ps
CPU time 11.55 seconds
Started Dec 27 12:27:53 PM PST 23
Finished Dec 27 12:28:37 PM PST 23
Peak memory 210308 kb
Host smart-389cfcaa-fa10-40f6-9229-bb7eca1f451a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185273894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3185273894
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2887108979
Short name T410
Test name
Test status
Simulation time 1682897004 ps
CPU time 14.32 seconds
Started Dec 27 12:21:31 PM PST 23
Finished Dec 27 12:21:47 PM PST 23
Peak memory 210752 kb
Host smart-18ffb5a7-5039-42be-8762-bb89d8ac78fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887108979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2887108979
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2528350563
Short name T370
Test name
Test status
Simulation time 20245846040 ps
CPU time 241.43 seconds
Started Dec 27 12:26:18 PM PST 23
Finished Dec 27 12:30:33 PM PST 23
Peak memory 234600 kb
Host smart-fa8b85ea-0d99-4bd1-8db3-d925e95a1ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528350563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2528350563
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.4256715972
Short name T180
Test name
Test status
Simulation time 7903356370 ps
CPU time 33.86 seconds
Started Dec 27 12:20:48 PM PST 23
Finished Dec 27 12:21:23 PM PST 23
Peak memory 211596 kb
Host smart-52f67f08-0ea4-4764-ab5d-3dbbd5ebf10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256715972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.4256715972
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.386763315
Short name T329
Test name
Test status
Simulation time 1082500605 ps
CPU time 11.72 seconds
Started Dec 27 12:24:47 PM PST 23
Finished Dec 27 12:25:01 PM PST 23
Peak memory 210376 kb
Host smart-6ede1af2-eb44-4510-b276-b6dbf631f814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386763315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.386763315
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3287470584
Short name T223
Test name
Test status
Simulation time 368557954 ps
CPU time 10.59 seconds
Started Dec 27 12:26:54 PM PST 23
Finished Dec 27 12:27:25 PM PST 23
Peak memory 212072 kb
Host smart-5ffd13fc-52cf-4eb0-ade1-0817b6ebcaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287470584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3287470584
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3292912854
Short name T373
Test name
Test status
Simulation time 6907093790 ps
CPU time 24.42 seconds
Started Dec 27 12:24:58 PM PST 23
Finished Dec 27 12:25:24 PM PST 23
Peak memory 214248 kb
Host smart-e4d3fbea-a620-41c7-a02e-b33f9f761d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292912854 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3292912854
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.918550506
Short name T222
Test name
Test status
Simulation time 122539446197 ps
CPU time 2958.25 seconds
Started Dec 27 12:27:54 PM PST 23
Finished Dec 27 01:17:46 PM PST 23
Peak memory 231756 kb
Host smart-45560dfe-5553-43f1-a6ea-fd8e88f1a3a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918550506 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.918550506
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2932961322
Short name T327
Test name
Test status
Simulation time 683636829 ps
CPU time 8.29 seconds
Started Dec 27 12:24:47 PM PST 23
Finished Dec 27 12:24:57 PM PST 23
Peak memory 210140 kb
Host smart-cf832b57-bb1b-4194-b4a7-cdc8371fb96a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932961322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2932961322
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1192297199
Short name T211
Test name
Test status
Simulation time 339222336644 ps
CPU time 587.67 seconds
Started Dec 27 12:26:51 PM PST 23
Finished Dec 27 12:36:59 PM PST 23
Peak memory 226472 kb
Host smart-1b17b455-c278-4927-906c-34741fa3326f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192297199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1192297199
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.12393861
Short name T248
Test name
Test status
Simulation time 22856107408 ps
CPU time 30.52 seconds
Started Dec 27 12:20:26 PM PST 23
Finished Dec 27 12:20:59 PM PST 23
Peak memory 211192 kb
Host smart-68576062-7a27-4cba-a7fd-bb51ece70ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12393861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.12393861
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.4134835250
Short name T277
Test name
Test status
Simulation time 1698513964 ps
CPU time 15.19 seconds
Started Dec 27 12:24:46 PM PST 23
Finished Dec 27 12:25:03 PM PST 23
Peak memory 209616 kb
Host smart-3b935344-ba43-42df-b02c-b5e0f838cd67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4134835250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.4134835250
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.2653103761
Short name T347
Test name
Test status
Simulation time 1059213309 ps
CPU time 12.12 seconds
Started Dec 27 12:24:48 PM PST 23
Finished Dec 27 12:25:01 PM PST 23
Peak memory 212116 kb
Host smart-fda503a3-2ec0-42b7-98d8-ecfb4d36b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653103761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2653103761
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.638358777
Short name T430
Test name
Test status
Simulation time 32426177694 ps
CPU time 29.13 seconds
Started Dec 27 12:27:43 PM PST 23
Finished Dec 27 12:28:43 PM PST 23
Peak memory 214148 kb
Host smart-13ed6603-3819-4c9d-bab1-027f1de143d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638358777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.638358777
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.2533371231
Short name T354
Test name
Test status
Simulation time 10309608594 ps
CPU time 99.03 seconds
Started Dec 27 12:24:48 PM PST 23
Finished Dec 27 12:26:29 PM PST 23
Peak memory 221868 kb
Host smart-c8d31355-10dc-4756-864f-62b0e20c3185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533371231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.2533371231
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3502396272
Short name T269
Test name
Test status
Simulation time 2106474244 ps
CPU time 15.87 seconds
Started Dec 27 12:26:22 PM PST 23
Finished Dec 27 12:26:52 PM PST 23
Peak memory 209624 kb
Host smart-8fbb4df8-df30-43aa-bb07-3cbebd387be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502396272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3502396272
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1268935151
Short name T157
Test name
Test status
Simulation time 125052969927 ps
CPU time 234 seconds
Started Dec 27 12:24:08 PM PST 23
Finished Dec 27 12:28:03 PM PST 23
Peak memory 228096 kb
Host smart-d45a49dd-8457-4fbc-8468-597bb701b0a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268935151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.1268935151
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1977438941
Short name T393
Test name
Test status
Simulation time 666648550 ps
CPU time 9.13 seconds
Started Dec 27 12:28:53 PM PST 23
Finished Dec 27 12:29:57 PM PST 23
Peak memory 210572 kb
Host smart-8a02ba1e-f534-4ccc-b93e-3c8bf0d74084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977438941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1977438941
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2201719312
Short name T345
Test name
Test status
Simulation time 627762793 ps
CPU time 9.56 seconds
Started Dec 27 12:27:27 PM PST 23
Finished Dec 27 12:28:05 PM PST 23
Peak memory 209024 kb
Host smart-0af50743-f8c6-4b8d-8202-1452846b6253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201719312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2201719312
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1476228111
Short name T342
Test name
Test status
Simulation time 3019944913 ps
CPU time 28.56 seconds
Started Dec 27 12:28:25 PM PST 23
Finished Dec 27 12:29:41 PM PST 23
Peak memory 212188 kb
Host smart-1399def2-bdea-4ddb-96d5-777f594878f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476228111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1476228111
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2159203105
Short name T320
Test name
Test status
Simulation time 648612043 ps
CPU time 10.76 seconds
Started Dec 27 12:28:29 PM PST 23
Finished Dec 27 12:29:29 PM PST 23
Peak memory 210520 kb
Host smart-623f383c-1a12-4a3e-b898-b74eb05fd841
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159203105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2159203105
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1982140752
Short name T384
Test name
Test status
Simulation time 78245877308 ps
CPU time 1811.74 seconds
Started Dec 27 12:26:21 PM PST 23
Finished Dec 27 12:56:48 PM PST 23
Peak memory 233860 kb
Host smart-9a4df0bd-35b1-473a-9ff6-b640d9c7c874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982140752 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1982140752
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1888156986
Short name T372
Test name
Test status
Simulation time 292684890 ps
CPU time 6.27 seconds
Started Dec 27 12:25:22 PM PST 23
Finished Dec 27 12:25:38 PM PST 23
Peak memory 209788 kb
Host smart-3a658bcb-b16f-4690-988c-54e02db261a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888156986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1888156986
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2767792811
Short name T259
Test name
Test status
Simulation time 102466526036 ps
CPU time 332.26 seconds
Started Dec 27 12:28:49 PM PST 23
Finished Dec 27 12:35:15 PM PST 23
Peak memory 234012 kb
Host smart-88657f4c-656d-48a0-9200-5823cda9d732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767792811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2767792811
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1816305419
Short name T422
Test name
Test status
Simulation time 7559249478 ps
CPU time 30.22 seconds
Started Dec 27 12:20:22 PM PST 23
Finished Dec 27 12:20:55 PM PST 23
Peak memory 211196 kb
Host smart-51f2d3a1-c54e-4472-b0fd-864c1fd1ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816305419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1816305419
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3167922785
Short name T178
Test name
Test status
Simulation time 1039756068 ps
CPU time 11.68 seconds
Started Dec 27 12:20:08 PM PST 23
Finished Dec 27 12:20:22 PM PST 23
Peak memory 210708 kb
Host smart-15ceca6d-2af2-49b7-9a5b-aabc027552d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167922785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3167922785
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2652768357
Short name T209
Test name
Test status
Simulation time 25235289529 ps
CPU time 29.47 seconds
Started Dec 27 12:26:44 PM PST 23
Finished Dec 27 12:27:34 PM PST 23
Peak memory 212672 kb
Host smart-9cfe2b45-ed85-4a91-b870-59d810379391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652768357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2652768357
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3819199088
Short name T377
Test name
Test status
Simulation time 218449743 ps
CPU time 16.24 seconds
Started Dec 27 12:25:15 PM PST 23
Finished Dec 27 12:25:37 PM PST 23
Peak memory 212052 kb
Host smart-3b73a98d-51c3-4baf-a2c3-8e79b4dea0aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819199088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3819199088
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2092480137
Short name T297
Test name
Test status
Simulation time 203010286048 ps
CPU time 2281.3 seconds
Started Dec 27 12:27:44 PM PST 23
Finished Dec 27 01:06:18 PM PST 23
Peak memory 244264 kb
Host smart-9399c047-b563-485f-b552-c9ae045c4c43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092480137 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2092480137
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.1135536172
Short name T171
Test name
Test status
Simulation time 1583980998 ps
CPU time 14.05 seconds
Started Dec 27 12:21:09 PM PST 23
Finished Dec 27 12:21:24 PM PST 23
Peak memory 210776 kb
Host smart-5db604cc-0bc3-4974-8b52-29c7641a3f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135536172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1135536172
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1915713272
Short name T189
Test name
Test status
Simulation time 48564982629 ps
CPU time 486.03 seconds
Started Dec 27 12:26:34 PM PST 23
Finished Dec 27 12:34:56 PM PST 23
Peak memory 233728 kb
Host smart-30ec5eed-9687-4d02-8829-3e4bbdff1436
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915713272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1915713272
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2011238923
Short name T296
Test name
Test status
Simulation time 7840302811 ps
CPU time 29.86 seconds
Started Dec 27 12:25:38 PM PST 23
Finished Dec 27 12:26:16 PM PST 23
Peak memory 211188 kb
Host smart-a753c19d-5123-4fd9-bda0-8ee30535abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011238923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2011238923
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3758096929
Short name T288
Test name
Test status
Simulation time 18666968111 ps
CPU time 14.78 seconds
Started Dec 27 12:28:39 PM PST 23
Finished Dec 27 12:29:46 PM PST 23
Peak memory 210368 kb
Host smart-70ec69d9-a516-489e-8397-0840c57f3ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758096929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3758096929
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2006503020
Short name T246
Test name
Test status
Simulation time 3749240064 ps
CPU time 38.09 seconds
Started Dec 27 12:25:50 PM PST 23
Finished Dec 27 12:26:33 PM PST 23
Peak memory 212464 kb
Host smart-bc2b6944-4572-449f-9b84-1a1fd0f2cadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006503020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2006503020
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2220355473
Short name T215
Test name
Test status
Simulation time 10499049067 ps
CPU time 55.86 seconds
Started Dec 27 12:27:10 PM PST 23
Finished Dec 27 12:28:31 PM PST 23
Peak memory 216092 kb
Host smart-c94a7f4e-4bd4-4dc1-b71c-4ed639941fa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220355473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2220355473
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.2308482717
Short name T194
Test name
Test status
Simulation time 52502625797 ps
CPU time 9238.9 seconds
Started Dec 27 12:22:06 PM PST 23
Finished Dec 27 02:56:06 PM PST 23
Peak memory 243620 kb
Host smart-253387a1-73fc-4c7b-bc17-dce767efa3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308482717 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.2308482717
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.2456268566
Short name T413
Test name
Test status
Simulation time 4575208556 ps
CPU time 11.43 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 12:27:18 PM PST 23
Peak memory 210964 kb
Host smart-79dba9d4-8513-43a4-8b83-178f9bbe4e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456268566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.2456268566
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1342688925
Short name T432
Test name
Test status
Simulation time 6640822374 ps
CPU time 164.02 seconds
Started Dec 27 12:29:03 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 224432 kb
Host smart-48065297-578a-408b-986d-36745dc07983
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342688925 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1342688925
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2486935216
Short name T22
Test name
Test status
Simulation time 355103544 ps
CPU time 9.56 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 12:27:16 PM PST 23
Peak memory 210904 kb
Host smart-2bab4f4b-b298-4bf5-820d-03bf37fa02c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486935216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2486935216
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.642427109
Short name T337
Test name
Test status
Simulation time 96239323 ps
CPU time 5.56 seconds
Started Dec 27 12:21:20 PM PST 23
Finished Dec 27 12:21:26 PM PST 23
Peak memory 210836 kb
Host smart-1a720dd8-544a-4c40-a6bc-47d86807a320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642427109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.642427109
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.651927049
Short name T339
Test name
Test status
Simulation time 5982818931 ps
CPU time 19.24 seconds
Started Dec 27 12:21:20 PM PST 23
Finished Dec 27 12:21:40 PM PST 23
Peak memory 213208 kb
Host smart-da9d6a8d-18fb-439c-bd0a-b3ea0b622566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651927049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.651927049
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1455559342
Short name T156
Test name
Test status
Simulation time 885591807 ps
CPU time 34.37 seconds
Started Dec 27 12:28:43 PM PST 23
Finished Dec 27 12:30:09 PM PST 23
Peak memory 216356 kb
Host smart-f436ea65-4ac7-4753-83f0-d0be99880bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455559342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1455559342
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3922975729
Short name T163
Test name
Test status
Simulation time 406520795467 ps
CPU time 3786.12 seconds
Started Dec 27 12:26:38 PM PST 23
Finished Dec 27 01:30:04 PM PST 23
Peak memory 251008 kb
Host smart-873a8157-50a5-48f4-95c2-c613b5db085e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922975729 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3922975729
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2837929920
Short name T229
Test name
Test status
Simulation time 2030460778 ps
CPU time 16.06 seconds
Started Dec 27 12:23:57 PM PST 23
Finished Dec 27 12:24:14 PM PST 23
Peak memory 210872 kb
Host smart-9e058351-9359-4f51-b8e2-92237cf2a508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837929920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2837929920
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.794708069
Short name T335
Test name
Test status
Simulation time 2675179487 ps
CPU time 114.47 seconds
Started Dec 27 12:26:26 PM PST 23
Finished Dec 27 12:28:34 PM PST 23
Peak memory 236784 kb
Host smart-8cf789ab-0083-46d4-882e-127a4c4ddcab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794708069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.794708069
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1309273642
Short name T239
Test name
Test status
Simulation time 1542696349 ps
CPU time 18.84 seconds
Started Dec 27 12:25:23 PM PST 23
Finished Dec 27 12:25:51 PM PST 23
Peak memory 209736 kb
Host smart-510f896e-8f68-445f-991a-5f2f183d26a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309273642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1309273642
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1355421303
Short name T8
Test name
Test status
Simulation time 8306222204 ps
CPU time 17.06 seconds
Started Dec 27 12:26:30 PM PST 23
Finished Dec 27 12:27:02 PM PST 23
Peak memory 209668 kb
Host smart-5637ba85-0c7f-4816-8a56-14b4940af62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1355421303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1355421303
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2274374328
Short name T301
Test name
Test status
Simulation time 13539855662 ps
CPU time 34.16 seconds
Started Dec 27 12:25:23 PM PST 23
Finished Dec 27 12:26:07 PM PST 23
Peak memory 212220 kb
Host smart-f36ace49-80ce-4621-9f0b-732c75bfbf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274374328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2274374328
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2982322409
Short name T12
Test name
Test status
Simulation time 13118870588 ps
CPU time 42.11 seconds
Started Dec 27 12:28:17 PM PST 23
Finished Dec 27 12:29:42 PM PST 23
Peak memory 215860 kb
Host smart-a12afeb8-3d92-4ed7-9dd0-8befac9dcc07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982322409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2982322409
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.103206510
Short name T15
Test name
Test status
Simulation time 44831261392 ps
CPU time 4248.35 seconds
Started Dec 27 12:26:46 PM PST 23
Finished Dec 27 01:37:55 PM PST 23
Peak memory 232328 kb
Host smart-2ff031f1-a12e-415d-a4ee-968e0b693e71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103206510 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.103206510
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%