Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.54 97.11 92.83 97.88 100.00 98.69 97.89 98.38


Total test records in report: 482
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T265 /workspace/coverage/default/3.rom_ctrl_alert_test.4170943712 Dec 31 12:55:04 PM PST 23 Dec 31 12:55:24 PM PST 23 1821565794 ps
T266 /workspace/coverage/default/44.rom_ctrl_stress_all.1415401883 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:15 PM PST 23 751571035 ps
T267 /workspace/coverage/default/33.rom_ctrl_smoke.2664372897 Dec 31 12:54:45 PM PST 23 Dec 31 12:55:13 PM PST 23 9735891098 ps
T268 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2818063874 Dec 31 12:55:06 PM PST 23 Dec 31 12:55:20 PM PST 23 1342876147 ps
T269 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1600830707 Dec 31 12:55:05 PM PST 23 Dec 31 12:55:24 PM PST 23 5248042793 ps
T270 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3819167929 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:15 PM PST 23 1699368307 ps
T271 /workspace/coverage/default/45.rom_ctrl_smoke.1019808405 Dec 31 12:54:56 PM PST 23 Dec 31 12:55:33 PM PST 23 6229257728 ps
T272 /workspace/coverage/default/40.rom_ctrl_stress_all.3188266151 Dec 31 12:54:54 PM PST 23 Dec 31 12:55:37 PM PST 23 4059930690 ps
T273 /workspace/coverage/default/40.rom_ctrl_smoke.1974825218 Dec 31 12:55:05 PM PST 23 Dec 31 12:55:34 PM PST 23 2401151219 ps
T274 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4189822592 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:15 PM PST 23 663398044 ps
T275 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4122554545 Dec 31 12:54:57 PM PST 23 Dec 31 03:34:44 PM PST 23 105065286427 ps
T276 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.971569281 Dec 31 12:54:47 PM PST 23 Dec 31 12:57:39 PM PST 23 64445181918 ps
T277 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1799258834 Dec 31 12:54:33 PM PST 23 Dec 31 12:57:01 PM PST 23 4489903279 ps
T278 /workspace/coverage/default/8.rom_ctrl_smoke.3056819868 Dec 31 12:54:45 PM PST 23 Dec 31 12:55:27 PM PST 23 16371899282 ps
T279 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3406081978 Dec 31 12:54:49 PM PST 23 Dec 31 01:17:01 PM PST 23 141751176989 ps
T280 /workspace/coverage/default/6.rom_ctrl_smoke.679537924 Dec 31 12:54:52 PM PST 23 Dec 31 12:55:18 PM PST 23 1788788562 ps
T281 /workspace/coverage/default/0.rom_ctrl_stress_all.3125488386 Dec 31 12:54:48 PM PST 23 Dec 31 12:55:14 PM PST 23 396873644 ps
T282 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.405979053 Dec 31 12:54:45 PM PST 23 Dec 31 12:54:59 PM PST 23 1053085190 ps
T283 /workspace/coverage/default/14.rom_ctrl_smoke.2327796280 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:11 PM PST 23 524178089 ps
T284 /workspace/coverage/default/49.rom_ctrl_alert_test.56758804 Dec 31 12:54:53 PM PST 23 Dec 31 12:55:02 PM PST 23 499799764 ps
T285 /workspace/coverage/default/43.rom_ctrl_smoke.1632331396 Dec 31 12:54:59 PM PST 23 Dec 31 12:55:42 PM PST 23 3133824173 ps
T286 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2481828278 Dec 31 12:54:57 PM PST 23 Dec 31 12:55:08 PM PST 23 94986104 ps
T287 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2660561754 Dec 31 12:54:55 PM PST 23 Dec 31 12:55:06 PM PST 23 300568269 ps
T288 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3239119757 Dec 31 12:54:54 PM PST 23 Dec 31 12:55:08 PM PST 23 754808104 ps
T18 /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3488919187 Dec 31 12:54:50 PM PST 23 Dec 31 01:03:22 PM PST 23 61745991394 ps
T289 /workspace/coverage/default/27.rom_ctrl_smoke.1421562620 Dec 31 12:54:30 PM PST 23 Dec 31 12:54:42 PM PST 23 719861010 ps
T290 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.790722016 Dec 31 12:54:52 PM PST 23 Dec 31 12:55:06 PM PST 23 1222158475 ps
T291 /workspace/coverage/default/35.rom_ctrl_stress_all.63391649 Dec 31 12:55:01 PM PST 23 Dec 31 12:56:31 PM PST 23 43485180974 ps
T292 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2579034284 Dec 31 12:54:44 PM PST 23 Dec 31 01:41:03 PM PST 23 301173377889 ps
T293 /workspace/coverage/default/2.rom_ctrl_alert_test.1858896378 Dec 31 12:54:38 PM PST 23 Dec 31 12:54:53 PM PST 23 5845676337 ps
T294 /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.836101754 Dec 31 12:54:59 PM PST 23 Dec 31 12:55:20 PM PST 23 1713771607 ps
T295 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3543798688 Dec 31 12:54:43 PM PST 23 Dec 31 12:54:59 PM PST 23 1738485042 ps
T296 /workspace/coverage/default/35.rom_ctrl_smoke.4067992943 Dec 31 12:54:44 PM PST 23 Dec 31 12:55:23 PM PST 23 60905768161 ps
T297 /workspace/coverage/default/7.rom_ctrl_alert_test.2138040002 Dec 31 12:55:01 PM PST 23 Dec 31 12:55:22 PM PST 23 3585113265 ps
T298 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2218896229 Dec 31 12:54:42 PM PST 23 Dec 31 02:02:07 PM PST 23 89755721099 ps
T299 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.590724983 Dec 31 12:55:12 PM PST 23 Dec 31 02:31:22 PM PST 23 39917113457 ps
T300 /workspace/coverage/default/30.rom_ctrl_alert_test.1597899558 Dec 31 12:54:42 PM PST 23 Dec 31 12:54:54 PM PST 23 10909548938 ps
T301 /workspace/coverage/default/15.rom_ctrl_stress_all.3536797843 Dec 31 12:54:51 PM PST 23 Dec 31 12:55:41 PM PST 23 10888782144 ps
T302 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1280627254 Dec 31 12:54:57 PM PST 23 Dec 31 01:21:38 PM PST 23 158326567123 ps
T303 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.283550859 Dec 31 12:54:30 PM PST 23 Dec 31 12:54:58 PM PST 23 2932716654 ps
T304 /workspace/coverage/default/5.rom_ctrl_stress_all.2486127931 Dec 31 12:55:06 PM PST 23 Dec 31 12:55:50 PM PST 23 7232437222 ps
T305 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3414851073 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:14 PM PST 23 10655268302 ps
T306 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1805071024 Dec 31 12:54:43 PM PST 23 Dec 31 12:54:52 PM PST 23 277744633 ps
T307 /workspace/coverage/default/21.rom_ctrl_alert_test.1420363076 Dec 31 12:54:26 PM PST 23 Dec 31 12:54:40 PM PST 23 8223312798 ps
T308 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.185967427 Dec 31 12:55:12 PM PST 23 Dec 31 12:56:45 PM PST 23 2405722376 ps
T309 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2153305016 Dec 31 12:54:46 PM PST 23 Dec 31 12:58:13 PM PST 23 68335172066 ps
T310 /workspace/coverage/default/9.rom_ctrl_smoke.3294232743 Dec 31 12:54:15 PM PST 23 Dec 31 12:54:49 PM PST 23 42551993462 ps
T311 /workspace/coverage/default/25.rom_ctrl_alert_test.2374542415 Dec 31 12:54:27 PM PST 23 Dec 31 12:54:38 PM PST 23 1964606334 ps
T312 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3616825773 Dec 31 12:54:53 PM PST 23 Dec 31 12:55:30 PM PST 23 13561569378 ps
T313 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1721916195 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:03 PM PST 23 12621344158 ps
T314 /workspace/coverage/default/8.rom_ctrl_stress_all.1278511796 Dec 31 12:55:06 PM PST 23 Dec 31 12:55:38 PM PST 23 11228402821 ps
T315 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.469991054 Dec 31 12:54:53 PM PST 23 Dec 31 01:12:08 PM PST 23 26724796792 ps
T316 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.409643530 Dec 31 12:54:42 PM PST 23 Dec 31 01:26:33 PM PST 23 227380610490 ps
T317 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1673962692 Dec 31 12:54:24 PM PST 23 Dec 31 12:54:38 PM PST 23 5135144234 ps
T318 /workspace/coverage/default/19.rom_ctrl_alert_test.3716182862 Dec 31 12:54:55 PM PST 23 Dec 31 12:55:05 PM PST 23 96115506 ps
T319 /workspace/coverage/default/48.rom_ctrl_alert_test.3159747499 Dec 31 12:55:06 PM PST 23 Dec 31 12:55:24 PM PST 23 1499093910 ps
T320 /workspace/coverage/default/34.rom_ctrl_stress_all.1431595551 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:13 PM PST 23 999197425 ps
T321 /workspace/coverage/default/9.rom_ctrl_alert_test.29416708 Dec 31 12:54:42 PM PST 23 Dec 31 12:54:52 PM PST 23 1342910240 ps
T322 /workspace/coverage/default/47.rom_ctrl_alert_test.2214758365 Dec 31 12:55:16 PM PST 23 Dec 31 12:55:26 PM PST 23 168326696 ps
T323 /workspace/coverage/default/3.rom_ctrl_smoke.316880056 Dec 31 12:54:52 PM PST 23 Dec 31 12:55:10 PM PST 23 2378499347 ps
T324 /workspace/coverage/default/23.rom_ctrl_stress_all.1177250093 Dec 31 12:54:52 PM PST 23 Dec 31 12:55:28 PM PST 23 3534163464 ps
T325 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.34654827 Dec 31 12:54:30 PM PST 23 Dec 31 12:59:10 PM PST 23 15985594757 ps
T326 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.465474275 Dec 31 12:54:59 PM PST 23 Dec 31 01:09:20 PM PST 23 12734930215 ps
T327 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1263072016 Dec 31 12:55:07 PM PST 23 Dec 31 03:14:10 PM PST 23 76114946466 ps
T328 /workspace/coverage/default/11.rom_ctrl_stress_all.2040757432 Dec 31 12:54:33 PM PST 23 Dec 31 12:55:43 PM PST 23 7286916482 ps
T329 /workspace/coverage/default/46.rom_ctrl_smoke.686697678 Dec 31 12:55:08 PM PST 23 Dec 31 12:55:24 PM PST 23 389228356 ps
T330 /workspace/coverage/default/12.rom_ctrl_stress_all.1843004092 Dec 31 12:54:39 PM PST 23 Dec 31 12:54:58 PM PST 23 2724452415 ps
T331 /workspace/coverage/default/28.rom_ctrl_stress_all.3722588695 Dec 31 12:54:32 PM PST 23 Dec 31 12:55:14 PM PST 23 11971226878 ps
T332 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.200237138 Dec 31 12:54:46 PM PST 23 Dec 31 12:54:55 PM PST 23 377322293 ps
T333 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1683460430 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:00 PM PST 23 176896296 ps
T334 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2305334906 Dec 31 12:54:50 PM PST 23 Dec 31 12:55:17 PM PST 23 4173526970 ps
T335 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1729771528 Dec 31 12:55:30 PM PST 23 Dec 31 01:01:30 PM PST 23 281660457053 ps
T336 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3539613491 Dec 31 12:55:25 PM PST 23 Dec 31 12:59:44 PM PST 23 27441568614 ps
T337 /workspace/coverage/default/2.rom_ctrl_stress_all.701154331 Dec 31 12:55:08 PM PST 23 Dec 31 12:55:24 PM PST 23 2741905907 ps
T338 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1445755268 Dec 31 12:54:41 PM PST 23 Dec 31 12:54:58 PM PST 23 7551954134 ps
T339 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1020389645 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:11 PM PST 23 101844723 ps
T340 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2227956646 Dec 31 12:54:42 PM PST 23 Dec 31 12:54:52 PM PST 23 1189724614 ps
T33 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2060451253 Dec 31 12:55:11 PM PST 23 Dec 31 12:55:45 PM PST 23 6528941183 ps
T341 /workspace/coverage/default/36.rom_ctrl_smoke.3080608822 Dec 31 12:54:55 PM PST 23 Dec 31 12:55:16 PM PST 23 4716362343 ps
T342 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.869720832 Dec 31 12:55:07 PM PST 23 Dec 31 12:55:19 PM PST 23 349415823 ps
T343 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2142179905 Dec 31 12:54:31 PM PST 23 Dec 31 12:55:04 PM PST 23 7002614262 ps
T344 /workspace/coverage/default/34.rom_ctrl_smoke.242794497 Dec 31 12:54:59 PM PST 23 Dec 31 12:55:35 PM PST 23 15849161419 ps
T345 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.380523927 Dec 31 12:54:25 PM PST 23 Dec 31 03:30:52 PM PST 23 78893267160 ps
T346 /workspace/coverage/default/37.rom_ctrl_alert_test.1033918596 Dec 31 12:54:50 PM PST 23 Dec 31 12:55:07 PM PST 23 1482755742 ps
T347 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.980091090 Dec 31 12:55:12 PM PST 23 Dec 31 12:55:24 PM PST 23 98525044 ps
T348 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2751742919 Dec 31 12:54:22 PM PST 23 Dec 31 01:32:56 PM PST 23 46591232964 ps
T349 /workspace/coverage/default/21.rom_ctrl_smoke.2799290511 Dec 31 12:55:09 PM PST 23 Dec 31 12:55:26 PM PST 23 643309142 ps
T350 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2845874099 Dec 31 12:54:43 PM PST 23 Dec 31 12:55:16 PM PST 23 3830723757 ps
T351 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3290979275 Dec 31 12:55:00 PM PST 23 Dec 31 12:55:39 PM PST 23 4158119047 ps
T352 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3761648519 Dec 31 12:54:59 PM PST 23 Dec 31 03:49:34 PM PST 23 64548669926 ps
T353 /workspace/coverage/default/17.rom_ctrl_smoke.2675194815 Dec 31 12:54:45 PM PST 23 Dec 31 12:55:25 PM PST 23 3108429330 ps
T354 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1268599979 Dec 31 12:54:59 PM PST 23 Dec 31 12:55:28 PM PST 23 1969974745 ps
T355 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.91223936 Dec 31 12:54:58 PM PST 23 Dec 31 12:55:29 PM PST 23 2897955876 ps
T356 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.763015855 Dec 31 12:54:51 PM PST 23 Dec 31 12:56:50 PM PST 23 1997696725 ps
T357 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1570240016 Dec 31 12:54:32 PM PST 23 Dec 31 12:54:47 PM PST 23 3657434079 ps
T358 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.737140342 Dec 31 12:54:56 PM PST 23 Dec 31 01:04:20 PM PST 23 59446471050 ps
T359 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.244826200 Dec 31 12:54:40 PM PST 23 Dec 31 01:51:17 PM PST 23 16707668134 ps
T360 /workspace/coverage/default/18.rom_ctrl_stress_all.2953058722 Dec 31 12:55:01 PM PST 23 Dec 31 12:55:30 PM PST 23 5928136796 ps
T361 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.247202358 Dec 31 12:54:51 PM PST 23 Dec 31 12:55:02 PM PST 23 275698183 ps
T362 /workspace/coverage/default/38.rom_ctrl_stress_all.2133314496 Dec 31 12:54:45 PM PST 23 Dec 31 12:55:30 PM PST 23 13055167207 ps
T363 /workspace/coverage/default/4.rom_ctrl_alert_test.7058613 Dec 31 12:54:49 PM PST 23 Dec 31 12:54:58 PM PST 23 920549460 ps
T364 /workspace/coverage/default/17.rom_ctrl_alert_test.684823629 Dec 31 12:55:04 PM PST 23 Dec 31 12:55:25 PM PST 23 7627925884 ps
T365 /workspace/coverage/default/10.rom_ctrl_stress_all.2788869797 Dec 31 12:54:24 PM PST 23 Dec 31 12:54:51 PM PST 23 411825094 ps
T366 /workspace/coverage/default/44.rom_ctrl_alert_test.4183916082 Dec 31 12:55:12 PM PST 23 Dec 31 12:55:32 PM PST 23 2500251395 ps
T367 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.154751580 Dec 31 12:54:43 PM PST 23 Dec 31 12:58:46 PM PST 23 22000862051 ps
T368 /workspace/coverage/default/31.rom_ctrl_stress_all.2820000062 Dec 31 12:54:49 PM PST 23 Dec 31 12:56:44 PM PST 23 12628107956 ps
T369 /workspace/coverage/default/22.rom_ctrl_alert_test.2873513601 Dec 31 12:54:43 PM PST 23 Dec 31 12:54:52 PM PST 23 630039606 ps
T370 /workspace/coverage/default/28.rom_ctrl_alert_test.1460645389 Dec 31 12:55:10 PM PST 23 Dec 31 12:55:21 PM PST 23 416888656 ps
T371 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2979188553 Dec 31 12:54:49 PM PST 23 Dec 31 12:55:01 PM PST 23 354737067 ps
T372 /workspace/coverage/default/36.rom_ctrl_alert_test.902200100 Dec 31 12:54:54 PM PST 23 Dec 31 12:55:05 PM PST 23 578623895 ps
T373 /workspace/coverage/default/20.rom_ctrl_alert_test.1342989057 Dec 31 12:54:47 PM PST 23 Dec 31 12:55:00 PM PST 23 3410517333 ps
T374 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2290787383 Dec 31 12:54:32 PM PST 23 Dec 31 12:54:45 PM PST 23 263559015 ps
T375 /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1348795265 Dec 31 12:54:49 PM PST 23 Dec 31 01:15:48 PM PST 23 32323144596 ps
T376 /workspace/coverage/default/21.rom_ctrl_stress_all.3344271554 Dec 31 12:54:41 PM PST 23 Dec 31 12:55:44 PM PST 23 6403974179 ps
T377 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3539680364 Dec 31 12:55:11 PM PST 23 Dec 31 12:55:23 PM PST 23 583070010 ps
T378 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3925544862 Dec 31 12:54:59 PM PST 23 Dec 31 01:19:00 PM PST 23 95077101319 ps
T379 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.382917534 Dec 31 12:54:59 PM PST 23 Dec 31 12:55:27 PM PST 23 19402060897 ps
T380 /workspace/coverage/default/31.rom_ctrl_smoke.797232333 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:25 PM PST 23 4782755210 ps
T381 /workspace/coverage/default/16.rom_ctrl_smoke.562471010 Dec 31 12:55:18 PM PST 23 Dec 31 12:55:37 PM PST 23 542614773 ps
T382 /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1415172792 Dec 31 12:54:43 PM PST 23 Dec 31 12:55:17 PM PST 23 16407775904 ps
T383 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4095762996 Dec 31 12:54:38 PM PST 23 Dec 31 12:54:57 PM PST 23 4936618764 ps
T384 /workspace/coverage/default/17.rom_ctrl_stress_all.2761153413 Dec 31 12:54:47 PM PST 23 Dec 31 12:55:34 PM PST 23 15958618774 ps
T385 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3231155274 Dec 31 12:55:03 PM PST 23 Dec 31 12:55:14 PM PST 23 386504349 ps
T386 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1500747655 Dec 31 12:55:01 PM PST 23 Dec 31 12:55:19 PM PST 23 1222709028 ps
T387 /workspace/coverage/default/2.rom_ctrl_smoke.1553289929 Dec 31 12:54:38 PM PST 23 Dec 31 12:54:53 PM PST 23 1782812997 ps
T43 /workspace/coverage/default/3.rom_ctrl_sec_cm.1560810621 Dec 31 12:54:48 PM PST 23 Dec 31 12:56:47 PM PST 23 1919980694 ps
T388 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1342067485 Dec 31 12:54:48 PM PST 23 Dec 31 12:55:03 PM PST 23 1613318651 ps
T389 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3738034697 Dec 31 12:54:47 PM PST 23 Dec 31 12:55:07 PM PST 23 6941728148 ps
T390 /workspace/coverage/default/16.rom_ctrl_stress_all.825447084 Dec 31 12:55:01 PM PST 23 Dec 31 12:55:27 PM PST 23 1299475429 ps
T391 /workspace/coverage/default/31.rom_ctrl_alert_test.4180076992 Dec 31 12:54:44 PM PST 23 Dec 31 12:55:00 PM PST 23 1649933125 ps
T392 /workspace/coverage/default/41.rom_ctrl_smoke.3180447194 Dec 31 12:55:17 PM PST 23 Dec 31 12:55:49 PM PST 23 4314321283 ps
T393 /workspace/coverage/default/37.rom_ctrl_smoke.1809849569 Dec 31 12:54:54 PM PST 23 Dec 31 12:55:11 PM PST 23 374696100 ps
T394 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3712064152 Dec 31 12:55:12 PM PST 23 Dec 31 12:55:28 PM PST 23 1186188235 ps
T395 /workspace/coverage/default/25.rom_ctrl_stress_all.1075987242 Dec 31 12:54:39 PM PST 23 Dec 31 12:54:48 PM PST 23 1449165295 ps
T396 /workspace/coverage/default/28.rom_ctrl_smoke.2961103642 Dec 31 12:54:37 PM PST 23 Dec 31 12:54:50 PM PST 23 776408539 ps
T397 /workspace/coverage/default/6.rom_ctrl_stress_all.342899513 Dec 31 12:55:12 PM PST 23 Dec 31 12:55:46 PM PST 23 4198111867 ps
T398 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2650926813 Dec 31 12:55:00 PM PST 23 Dec 31 01:03:02 PM PST 23 48030491139 ps
T399 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1749774885 Dec 31 12:55:12 PM PST 23 Dec 31 12:55:34 PM PST 23 4298609599 ps
T400 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3617408511 Dec 31 12:54:51 PM PST 23 Dec 31 12:55:04 PM PST 23 168697196 ps
T401 /workspace/coverage/default/37.rom_ctrl_stress_all.2977163221 Dec 31 12:55:11 PM PST 23 Dec 31 12:55:58 PM PST 23 30885595148 ps
T402 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3395586748 Dec 31 12:54:40 PM PST 23 Dec 31 12:59:49 PM PST 23 29111223831 ps
T403 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1543661948 Dec 31 12:54:56 PM PST 23 Dec 31 12:55:30 PM PST 23 6454155188 ps
T404 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.949370091 Dec 31 12:54:44 PM PST 23 Dec 31 12:59:28 PM PST 23 12143142306 ps
T405 /workspace/coverage/default/18.rom_ctrl_smoke.1702196483 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:00 PM PST 23 367910151 ps
T44 /workspace/coverage/default/1.rom_ctrl_sec_cm.3272283505 Dec 31 12:54:51 PM PST 23 Dec 31 12:56:54 PM PST 23 2779408512 ps
T406 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3228556805 Dec 31 12:54:44 PM PST 23 Dec 31 12:55:18 PM PST 23 7880257830 ps
T407 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.873974275 Dec 31 12:54:54 PM PST 23 Dec 31 12:57:37 PM PST 23 13356094030 ps
T408 /workspace/coverage/default/29.rom_ctrl_stress_all.89467779 Dec 31 12:54:42 PM PST 23 Dec 31 12:56:17 PM PST 23 8594866385 ps
T409 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2999437718 Dec 31 12:55:02 PM PST 23 Dec 31 12:55:30 PM PST 23 28184627005 ps
T410 /workspace/coverage/default/12.rom_ctrl_alert_test.3140347896 Dec 31 12:55:07 PM PST 23 Dec 31 12:55:34 PM PST 23 12466676376 ps
T411 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1351392736 Dec 31 12:54:52 PM PST 23 Dec 31 01:00:29 PM PST 23 30729857351 ps
T412 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3208877965 Dec 31 12:55:13 PM PST 23 Dec 31 12:55:34 PM PST 23 7761413392 ps
T413 /workspace/coverage/default/32.rom_ctrl_smoke.791707015 Dec 31 12:55:05 PM PST 23 Dec 31 12:55:31 PM PST 23 3391341181 ps
T414 /workspace/coverage/default/39.rom_ctrl_smoke.1437028592 Dec 31 12:55:05 PM PST 23 Dec 31 12:55:40 PM PST 23 10143259578 ps
T415 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2605913067 Dec 31 12:54:48 PM PST 23 Dec 31 12:59:20 PM PST 23 69086552339 ps
T416 /workspace/coverage/default/30.rom_ctrl_stress_all.2390798842 Dec 31 12:54:58 PM PST 23 Dec 31 12:55:21 PM PST 23 1188451463 ps
T417 /workspace/coverage/default/29.rom_ctrl_alert_test.3748678013 Dec 31 12:54:51 PM PST 23 Dec 31 12:55:03 PM PST 23 2281178297 ps
T418 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3702900996 Dec 31 12:55:05 PM PST 23 Dec 31 12:59:12 PM PST 23 18209145204 ps
T419 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1820244548 Dec 31 12:54:40 PM PST 23 Dec 31 03:00:39 PM PST 23 214392576594 ps
T420 /workspace/coverage/default/13.rom_ctrl_stress_all.922543908 Dec 31 12:54:46 PM PST 23 Dec 31 12:55:03 PM PST 23 746505145 ps
T421 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3021833893 Dec 31 12:54:55 PM PST 23 Dec 31 12:55:27 PM PST 23 3067105254 ps
T422 /workspace/coverage/default/45.rom_ctrl_stress_all.723137025 Dec 31 12:54:50 PM PST 23 Dec 31 12:56:20 PM PST 23 18604206988 ps
T423 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2067276410 Dec 31 12:55:28 PM PST 23 Dec 31 01:05:27 PM PST 23 125370145040 ps
T424 /workspace/coverage/default/27.rom_ctrl_alert_test.2579026749 Dec 31 12:54:41 PM PST 23 Dec 31 12:54:50 PM PST 23 1014866678 ps
T425 /workspace/coverage/default/1.rom_ctrl_smoke.1738926461 Dec 31 12:54:37 PM PST 23 Dec 31 12:55:13 PM PST 23 3020748337 ps
T426 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3479179365 Dec 31 12:55:15 PM PST 23 Dec 31 01:45:50 PM PST 23 86986781779 ps
T427 /workspace/coverage/default/8.rom_ctrl_alert_test.772615572 Dec 31 12:55:07 PM PST 23 Dec 31 12:55:23 PM PST 23 5492284866 ps
T428 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2517026614 Dec 31 12:54:33 PM PST 23 Dec 31 01:08:08 PM PST 23 13282130503 ps
T429 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1264094018 Dec 31 12:54:45 PM PST 23 Dec 31 12:55:11 PM PST 23 2290383981 ps
T430 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1856895135 Dec 31 12:54:47 PM PST 23 Dec 31 01:19:49 PM PST 23 42439972450 ps
T431 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2246801184 Dec 31 12:49:53 PM PST 23 Dec 31 12:53:05 PM PST 23 15035346609 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1824474959 Dec 31 12:49:39 PM PST 23 Dec 31 12:50:22 PM PST 23 626688747 ps
T432 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1117297524 Dec 31 12:49:44 PM PST 23 Dec 31 12:49:52 PM PST 23 910902330 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1411244074 Dec 31 12:49:53 PM PST 23 Dec 31 12:52:17 PM PST 23 34158410255 ps
T433 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1996775350 Dec 31 12:49:24 PM PST 23 Dec 31 12:49:32 PM PST 23 826020416 ps
T434 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1396922451 Dec 31 12:49:33 PM PST 23 Dec 31 12:50:20 PM PST 23 5494307730 ps
T435 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3617947013 Dec 31 12:49:38 PM PST 23 Dec 31 12:49:57 PM PST 23 2084500670 ps
T436 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3726929636 Dec 31 12:49:31 PM PST 23 Dec 31 12:49:47 PM PST 23 8015587669 ps
T437 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1220030385 Dec 31 12:49:27 PM PST 23 Dec 31 12:49:41 PM PST 23 5252547063 ps
T438 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4279670275 Dec 31 12:49:10 PM PST 23 Dec 31 12:49:15 PM PST 23 90226651 ps
T110 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.744950867 Dec 31 12:49:24 PM PST 23 Dec 31 12:50:42 PM PST 23 817817812 ps
T439 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2104613587 Dec 31 12:49:13 PM PST 23 Dec 31 12:49:24 PM PST 23 3932252602 ps
T440 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1455001326 Dec 31 12:49:19 PM PST 23 Dec 31 12:49:38 PM PST 23 1946615838 ps
T89 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.759419020 Dec 31 12:49:12 PM PST 23 Dec 31 12:51:23 PM PST 23 23655358523 ps
T92 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3376081690 Dec 31 12:49:38 PM PST 23 Dec 31 12:49:53 PM PST 23 3375360256 ps
T85 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2704305521 Dec 31 12:49:14 PM PST 23 Dec 31 12:51:47 PM PST 23 131376861948 ps
T86 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1289613146 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:34 PM PST 23 379041924 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3960168339 Dec 31 12:49:25 PM PST 23 Dec 31 12:49:40 PM PST 23 1815202556 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.912444870 Dec 31 12:49:12 PM PST 23 Dec 31 12:49:25 PM PST 23 4769748520 ps
T443 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4014176131 Dec 31 12:49:21 PM PST 23 Dec 31 12:50:40 PM PST 23 1154302016 ps
T444 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2273851173 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:40 PM PST 23 6642306604 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1142891725 Dec 31 12:49:30 PM PST 23 Dec 31 12:49:42 PM PST 23 814025086 ps
T446 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1025996161 Dec 31 12:49:49 PM PST 23 Dec 31 12:49:55 PM PST 23 1650420649 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2297280784 Dec 31 12:49:41 PM PST 23 Dec 31 12:53:06 PM PST 23 14777537806 ps
T448 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3223232151 Dec 31 12:49:57 PM PST 23 Dec 31 12:50:18 PM PST 23 2051674689 ps
T449 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1985200342 Dec 31 12:49:40 PM PST 23 Dec 31 12:50:56 PM PST 23 32327661924 ps
T450 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2214389251 Dec 31 12:49:38 PM PST 23 Dec 31 12:49:53 PM PST 23 2820952455 ps
T451 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.481920434 Dec 31 12:49:56 PM PST 23 Dec 31 12:50:08 PM PST 23 1035738705 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3746172441 Dec 31 12:49:34 PM PST 23 Dec 31 12:49:54 PM PST 23 3735372115 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3108053407 Dec 31 12:49:00 PM PST 23 Dec 31 12:49:20 PM PST 23 2056249497 ps
T454 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1295511149 Dec 31 12:49:31 PM PST 23 Dec 31 12:49:45 PM PST 23 4082957643 ps
T455 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3419068919 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:26 PM PST 23 290424549 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.52655640 Dec 31 12:49:36 PM PST 23 Dec 31 12:49:51 PM PST 23 5840716920 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3792563835 Dec 31 12:49:23 PM PST 23 Dec 31 12:49:30 PM PST 23 275907356 ps
T458 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1192527236 Dec 31 12:49:27 PM PST 23 Dec 31 12:49:41 PM PST 23 11978015078 ps
T459 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4072571888 Dec 31 12:49:30 PM PST 23 Dec 31 12:49:35 PM PST 23 637493850 ps
T460 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1316444869 Dec 31 12:49:25 PM PST 23 Dec 31 12:49:45 PM PST 23 12553060831 ps
T461 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3932782964 Dec 31 12:49:18 PM PST 23 Dec 31 12:49:34 PM PST 23 6754835586 ps
T462 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3298535755 Dec 31 12:49:28 PM PST 23 Dec 31 12:49:43 PM PST 23 2075344093 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.424616110 Dec 31 12:49:38 PM PST 23 Dec 31 12:49:44 PM PST 23 333210188 ps
T463 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3884261443 Dec 31 12:49:24 PM PST 23 Dec 31 12:49:44 PM PST 23 8544881306 ps
T464 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3950679511 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:32 PM PST 23 223991555 ps
T465 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.526064548 Dec 31 12:49:41 PM PST 23 Dec 31 12:50:57 PM PST 23 2006150562 ps
T466 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2341537406 Dec 31 12:49:28 PM PST 23 Dec 31 12:49:33 PM PST 23 89184382 ps
T467 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1991125040 Dec 31 12:49:38 PM PST 23 Dec 31 12:52:36 PM PST 23 24219935718 ps
T468 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4177512023 Dec 31 12:49:11 PM PST 23 Dec 31 12:49:28 PM PST 23 2206759390 ps
T469 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4164207516 Dec 31 12:49:17 PM PST 23 Dec 31 12:49:27 PM PST 23 1407289172 ps
T87 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.186939584 Dec 31 12:49:44 PM PST 23 Dec 31 12:53:20 PM PST 23 82495662042 ps
T470 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2142391421 Dec 31 12:49:34 PM PST 23 Dec 31 12:49:40 PM PST 23 91470013 ps
T471 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4046208792 Dec 31 12:49:27 PM PST 23 Dec 31 12:50:51 PM PST 23 5118277683 ps
T472 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4222801953 Dec 31 12:49:37 PM PST 23 Dec 31 12:49:52 PM PST 23 3301881404 ps
T473 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1672028509 Dec 31 12:49:37 PM PST 23 Dec 31 12:49:50 PM PST 23 4208259413 ps
T474 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2421027312 Dec 31 12:49:19 PM PST 23 Dec 31 12:49:25 PM PST 23 333792914 ps
T475 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2118231671 Dec 31 12:49:26 PM PST 23 Dec 31 12:49:31 PM PST 23 333136973 ps
T476 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3518449162 Dec 31 12:49:41 PM PST 23 Dec 31 12:49:53 PM PST 23 4533241272 ps
T477 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.469274211 Dec 31 12:49:34 PM PST 23 Dec 31 12:49:49 PM PST 23 1577683231 ps
T478 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1303206215 Dec 31 12:49:51 PM PST 23 Dec 31 12:50:44 PM PST 23 997400519 ps
T111 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.880917112 Dec 31 12:49:14 PM PST 23 Dec 31 12:50:37 PM PST 23 1758407787 ps
T479 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1528489468 Dec 31 12:49:36 PM PST 23 Dec 31 12:49:43 PM PST 23 287217679 ps
T480 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.683703301 Dec 31 12:49:30 PM PST 23 Dec 31 12:50:50 PM PST 23 1217240994 ps
T481 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2342082561 Dec 31 12:49:10 PM PST 23 Dec 31 12:49:16 PM PST 23 319852363 ps
T482 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1435119725 Dec 31 12:49:52 PM PST 23 Dec 31 12:50:06 PM PST 23 1250873125 ps

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3250757996
Short name T21
Test name
Test status
Simulation time 2649072369 ps
CPU time 8.4 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:30 PM PST 23
Peak memory 211216 kb
Host smart-18412179-4997-4a4f-b492-f71d7f59b128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250757996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3250757996
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3408075701
Short name T3
Test name
Test status
Simulation time 5565206128 ps
CPU time 38.61 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:49 PM PST 23
Peak memory 212800 kb
Host smart-1bbf41ba-b54e-40c8-bee1-9db8aa0e0844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408075701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3408075701
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1811116714
Short name T28
Test name
Test status
Simulation time 10918175270 ps
CPU time 11.18 seconds
Started Dec 31 12:49:54 PM PST 23
Finished Dec 31 12:50:07 PM PST 23
Peak memory 219484 kb
Host smart-a5de5be5-2935-4982-9698-b62c69ec5a78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811116714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1811116714
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2437412134
Short name T66
Test name
Test status
Simulation time 40862575735 ps
CPU time 429.29 seconds
Started Dec 31 12:48:57 PM PST 23
Finished Dec 31 12:56:08 PM PST 23
Peak memory 211220 kb
Host smart-d3e9f9d6-3203-4303-a546-6583f5d9a24c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437412134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2437412134
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2044345488
Short name T25
Test name
Test status
Simulation time 1206582978 ps
CPU time 75.01 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:50:30 PM PST 23
Peak memory 213448 kb
Host smart-ab1a0ed8-7464-490b-be59-041be5a2f083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044345488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2044345488
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3364712292
Short name T12
Test name
Test status
Simulation time 22920796285 ps
CPU time 1989.5 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 01:28:26 PM PST 23
Peak memory 233444 kb
Host smart-543e94a7-cc78-454f-bb66-f9cdb6dc9305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364712292 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3364712292
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2765383056
Short name T36
Test name
Test status
Simulation time 61625063180 ps
CPU time 583.14 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 01:04:30 PM PST 23
Peak memory 227728 kb
Host smart-bb66eb4d-3072-40a7-9e8e-2b55848a0c21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765383056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2765383056
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3183596141
Short name T73
Test name
Test status
Simulation time 435130015 ps
CPU time 7.77 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 219324 kb
Host smart-db7693fd-b659-49ed-93a0-ba18333c4fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183596141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3183596141
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.744950867
Short name T110
Test name
Test status
Simulation time 817817812 ps
CPU time 76.62 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:50:42 PM PST 23
Peak memory 212548 kb
Host smart-33345553-5af3-4bdb-92a4-0da61ec58808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744950867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.744950867
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1527252347
Short name T38
Test name
Test status
Simulation time 530531296 ps
CPU time 117.53 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:56:43 PM PST 23
Peak memory 236356 kb
Host smart-18527a39-123d-4361-a6c3-7905792d2f75
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527252347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1527252347
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1057636439
Short name T24
Test name
Test status
Simulation time 28267758796 ps
CPU time 156.62 seconds
Started Dec 31 12:49:20 PM PST 23
Finished Dec 31 12:51:58 PM PST 23
Peak memory 211160 kb
Host smart-748fbd1e-6530-4d0c-aa3a-9a07dd0b22d7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057636439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1057636439
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1880968231
Short name T16
Test name
Test status
Simulation time 200231397323 ps
CPU time 5522.89 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 02:26:51 PM PST 23
Peak memory 235548 kb
Host smart-b6b03ac4-94c9-41bd-a71b-024d54358b96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880968231 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1880968231
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.2560269887
Short name T60
Test name
Test status
Simulation time 880595113 ps
CPU time 13.03 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:50:01 PM PST 23
Peak memory 219444 kb
Host smart-7954125f-6259-4712-a289-f55302bda499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560269887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.2560269887
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2206987913
Short name T174
Test name
Test status
Simulation time 2077582214 ps
CPU time 117.58 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:57:02 PM PST 23
Peak memory 227860 kb
Host smart-ee713a14-1213-44f3-b9c0-98ad4bc34850
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206987913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.2206987913
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.351666711
Short name T169
Test name
Test status
Simulation time 1185822225 ps
CPU time 17.15 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 210932 kb
Host smart-63442daa-c7a4-4016-9a20-71a2bdbd72c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351666711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.351666711
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3804741137
Short name T218
Test name
Test status
Simulation time 397072187 ps
CPU time 9.62 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 210932 kb
Host smart-4fbfa6c4-cbd6-4d95-9252-ad1a2da55c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804741137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3804741137
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2060451253
Short name T33
Test name
Test status
Simulation time 6528941183 ps
CPU time 27.98 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:45 PM PST 23
Peak memory 211344 kb
Host smart-9f709dcf-2964-438f-bbea-aff836937bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060451253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2060451253
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.204684356
Short name T108
Test name
Test status
Simulation time 3406759420 ps
CPU time 82.96 seconds
Started Dec 31 12:49:35 PM PST 23
Finished Dec 31 12:50:59 PM PST 23
Peak memory 211424 kb
Host smart-5324cbdb-8320-4394-b5be-0d8961f3f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204684356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int
g_err.204684356
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1461021195
Short name T150
Test name
Test status
Simulation time 2364421930 ps
CPU time 11.65 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 211020 kb
Host smart-88b8116a-413a-40bf-86fd-52757a5fff54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461021195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1461021195
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.683703301
Short name T480
Test name
Test status
Simulation time 1217240994 ps
CPU time 79 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:50:50 PM PST 23
Peak memory 211504 kb
Host smart-e7c76fe1-c5e8-4be1-9c98-4591bea91986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683703301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_in
tg_err.683703301
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.297956863
Short name T76
Test name
Test status
Simulation time 904170164 ps
CPU time 73.69 seconds
Started Dec 31 12:49:56 PM PST 23
Finished Dec 31 12:51:12 PM PST 23
Peak memory 211572 kb
Host smart-45408b7e-0700-46fa-a36e-d83ba86f2adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297956863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.297956863
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.424616110
Short name T84
Test name
Test status
Simulation time 333210188 ps
CPU time 4.42 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:44 PM PST 23
Peak memory 211168 kb
Host smart-41034d29-cc28-4df2-afae-7abccf589093
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424616110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.424616110
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1613081071
Short name T74
Test name
Test status
Simulation time 298910050 ps
CPU time 4.38 seconds
Started Dec 31 12:49:29 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 211124 kb
Host smart-bef7fc40-7fec-4566-beca-1173c23d5fc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613081071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1613081071
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3108053407
Short name T453
Test name
Test status
Simulation time 2056249497 ps
CPU time 13.32 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:49:20 PM PST 23
Peak memory 211132 kb
Host smart-887bad1d-81c1-45be-bd81-d35f40d79508
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108053407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3108053407
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2555493036
Short name T59
Test name
Test status
Simulation time 10432568188 ps
CPU time 16.31 seconds
Started Dec 31 12:49:16 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 215628 kb
Host smart-6559dc25-cc31-44c7-b12e-f06456a31c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555493036 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.2555493036
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.1553694417
Short name T124
Test name
Test status
Simulation time 2471812207 ps
CPU time 16.7 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:52 PM PST 23
Peak memory 211256 kb
Host smart-25e002a7-aaa4-43f7-baff-756b9eacafd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553694417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.1553694417
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1295511149
Short name T454
Test name
Test status
Simulation time 4082957643 ps
CPU time 12.79 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 211176 kb
Host smart-de60c997-2d84-4326-9178-0637dc0a9c0c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295511149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1295511149
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.360105116
Short name T116
Test name
Test status
Simulation time 779821293 ps
CPU time 9.14 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:43 PM PST 23
Peak memory 211136 kb
Host smart-80f60804-b457-4d33-abcf-4d43ed5edfcb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360105116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk.
360105116
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2090276729
Short name T69
Test name
Test status
Simulation time 44067247387 ps
CPU time 441.68 seconds
Started Dec 31 12:49:00 PM PST 23
Finished Dec 31 12:56:22 PM PST 23
Peak memory 211204 kb
Host smart-cbdd6238-2e44-451f-a9cc-e55128536b89
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090276729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2090276729
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4006685206
Short name T78
Test name
Test status
Simulation time 1743242908 ps
CPU time 10.61 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:42 PM PST 23
Peak memory 211212 kb
Host smart-c85d5ac3-8a22-46e8-94d1-acdedb343a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006685206 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.4006685206
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.2214389251
Short name T450
Test name
Test status
Simulation time 2820952455 ps
CPU time 14.28 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:53 PM PST 23
Peak memory 214536 kb
Host smart-9be6161c-af0c-4cf4-9f6f-f4d951941d3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214389251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.2214389251
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.481920434
Short name T451
Test name
Test status
Simulation time 1035738705 ps
CPU time 10.43 seconds
Started Dec 31 12:49:56 PM PST 23
Finished Dec 31 12:50:08 PM PST 23
Peak memory 211160 kb
Host smart-d98b85f2-b7aa-475f-ae64-19c6b5590040
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481920434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.481920434
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.2103407295
Short name T97
Test name
Test status
Simulation time 14022513451 ps
CPU time 11.43 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:47 PM PST 23
Peak memory 211228 kb
Host smart-9b38667c-4dd4-48df-83e8-de59425bbcba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103407295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.2103407295
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.86801167
Short name T117
Test name
Test status
Simulation time 3436448321 ps
CPU time 19.27 seconds
Started Dec 31 12:49:32 PM PST 23
Finished Dec 31 12:49:54 PM PST 23
Peak memory 211204 kb
Host smart-ddba6553-7781-4062-a528-db21066545fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86801167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_res
et.86801167
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3623721982
Short name T26
Test name
Test status
Simulation time 1374819270 ps
CPU time 12.41 seconds
Started Dec 31 12:49:41 PM PST 23
Finished Dec 31 12:49:55 PM PST 23
Peak memory 214832 kb
Host smart-488cf94b-5853-4f17-bbfb-e66760e9d4ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623721982 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.3623721982
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.2273851173
Short name T444
Test name
Test status
Simulation time 6642306604 ps
CPU time 13.37 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 211312 kb
Host smart-dea756aa-ba3d-477e-83ea-cb05b3113f54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273851173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.2273851173
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.3133751329
Short name T121
Test name
Test status
Simulation time 1275493981 ps
CPU time 7.99 seconds
Started Dec 31 12:49:47 PM PST 23
Finished Dec 31 12:49:56 PM PST 23
Peak memory 211140 kb
Host smart-8c2e0a78-0bbc-41f1-b0eb-9a7e55135ba3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133751329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.3133751329
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3422638065
Short name T125
Test name
Test status
Simulation time 362709489 ps
CPU time 4.31 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 211164 kb
Host smart-dae14c09-be9d-44d5-815e-96b1cd8fcd4d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422638065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.3422638065
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1991125040
Short name T467
Test name
Test status
Simulation time 24219935718 ps
CPU time 176.99 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:52:36 PM PST 23
Peak memory 211236 kb
Host smart-e6cceb67-1b17-478a-a334-3060a80dbaba
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991125040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1991125040
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1403601699
Short name T64
Test name
Test status
Simulation time 2174762403 ps
CPU time 15.91 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 211216 kb
Host smart-37c46680-9383-4651-b123-6c1f1ea129e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403601699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1403601699
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1142891725
Short name T445
Test name
Test status
Simulation time 814025086 ps
CPU time 11.53 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:49:42 PM PST 23
Peak memory 219324 kb
Host smart-9439a323-0093-40e2-81fa-1da707ca2060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142891725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1142891725
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.4014176131
Short name T443
Test name
Test status
Simulation time 1154302016 ps
CPU time 77.31 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:50:40 PM PST 23
Peak memory 211508 kb
Host smart-c9cc637b-07a9-4589-9042-82104ed222c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014176131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.4014176131
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2554061601
Short name T23
Test name
Test status
Simulation time 89347511 ps
CPU time 4.81 seconds
Started Dec 31 12:49:02 PM PST 23
Finished Dec 31 12:49:08 PM PST 23
Peak memory 212384 kb
Host smart-1e2bd27b-07cc-44da-a8c8-ad6c6af34b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554061601 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2554061601
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.799768094
Short name T63
Test name
Test status
Simulation time 4097656262 ps
CPU time 11.96 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:35 PM PST 23
Peak memory 211220 kb
Host smart-ecd71ec5-bb56-42e2-881a-8f2c5408a1c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799768094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.799768094
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.2704305521
Short name T85
Test name
Test status
Simulation time 131376861948 ps
CPU time 151.7 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:51:47 PM PST 23
Peak memory 211284 kb
Host smart-d0c5a4e6-889c-40ae-970d-a3fbe4e324cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704305521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.2704305521
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2727824723
Short name T123
Test name
Test status
Simulation time 3747769856 ps
CPU time 15.39 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 211276 kb
Host smart-c36a1554-d283-407d-8239-d5f8b1bcd6df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727824723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2727824723
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.341724728
Short name T61
Test name
Test status
Simulation time 2564236567 ps
CPU time 10.4 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:49:42 PM PST 23
Peak memory 219408 kb
Host smart-64277409-998e-482c-9f52-2acd6deeb1e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341724728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.341724728
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4046208792
Short name T471
Test name
Test status
Simulation time 5118277683 ps
CPU time 78.57 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:50:51 PM PST 23
Peak memory 211724 kb
Host smart-112e1c31-9841-49e8-a09b-66568c07962e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046208792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4046208792
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3298535755
Short name T462
Test name
Test status
Simulation time 2075344093 ps
CPU time 13.61 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:43 PM PST 23
Peak memory 214792 kb
Host smart-89d8aac9-07c3-41aa-9c9b-a9af721f7f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298535755 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3298535755
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.4072571888
Short name T459
Test name
Test status
Simulation time 637493850 ps
CPU time 4.26 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:49:35 PM PST 23
Peak memory 211196 kb
Host smart-0573a065-9f7c-4d1a-a454-e7e1870d5ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072571888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.4072571888
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2246801184
Short name T431
Test name
Test status
Simulation time 15035346609 ps
CPU time 189.93 seconds
Started Dec 31 12:49:53 PM PST 23
Finished Dec 31 12:53:05 PM PST 23
Peak memory 211256 kb
Host smart-976858f2-716e-4aaa-ad0a-1ba156d0c863
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246801184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2246801184
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.3419068919
Short name T455
Test name
Test status
Simulation time 290424549 ps
CPU time 6.38 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:26 PM PST 23
Peak memory 211144 kb
Host smart-822e763d-4252-4c48-b9cd-f1582a50c3fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419068919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.3419068919
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3746172441
Short name T452
Test name
Test status
Simulation time 3735372115 ps
CPU time 17.95 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:54 PM PST 23
Peak memory 219360 kb
Host smart-7e5b53b3-d2a5-4470-b378-e0fb4c7628d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746172441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3746172441
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1192527236
Short name T458
Test name
Test status
Simulation time 11978015078 ps
CPU time 12.59 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 219476 kb
Host smart-07688381-792f-42cc-b6ea-90933ac794e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192527236 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1192527236
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.699890172
Short name T65
Test name
Test status
Simulation time 2102388191 ps
CPU time 15.61 seconds
Started Dec 31 12:49:29 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 211120 kb
Host smart-fbbbece2-381f-4f8a-b781-dab80414a642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699890172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.699890172
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.186939584
Short name T87
Test name
Test status
Simulation time 82495662042 ps
CPU time 215.3 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:53:20 PM PST 23
Peak memory 211220 kb
Host smart-0fea67ac-7433-4d5b-b719-3b2c1f698b37
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186939584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.186939584
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.4075461746
Short name T118
Test name
Test status
Simulation time 1084422426 ps
CPU time 12.95 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:52 PM PST 23
Peak memory 211224 kb
Host smart-ebf8693c-b07c-484b-83ef-3d7e4ff6a94e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075461746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.4075461746
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.912169422
Short name T120
Test name
Test status
Simulation time 346591971 ps
CPU time 8.96 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 219368 kb
Host smart-7c52ed90-06e2-40da-8e13-2489988391d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912169422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.912169422
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.1396922451
Short name T434
Test name
Test status
Simulation time 5494307730 ps
CPU time 46.52 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:50:20 PM PST 23
Peak memory 212748 kb
Host smart-69bc9340-acfb-4705-b4cd-23d3d266d9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396922451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.1396922451
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1672028509
Short name T473
Test name
Test status
Simulation time 4208259413 ps
CPU time 11.4 seconds
Started Dec 31 12:49:37 PM PST 23
Finished Dec 31 12:49:50 PM PST 23
Peak memory 213628 kb
Host smart-726dd63f-aa6d-44d0-bba7-134e4783f0ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672028509 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1672028509
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.267351704
Short name T62
Test name
Test status
Simulation time 2134359421 ps
CPU time 16.1 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:47 PM PST 23
Peak memory 211120 kb
Host smart-cf20d325-a549-46cc-88bd-4b0d913021d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267351704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.267351704
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2297280784
Short name T447
Test name
Test status
Simulation time 14777537806 ps
CPU time 204.31 seconds
Started Dec 31 12:49:41 PM PST 23
Finished Dec 31 12:53:06 PM PST 23
Peak memory 211272 kb
Host smart-f55e583c-0365-4962-815a-2e1b09a9696c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297280784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2297280784
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2973379658
Short name T75
Test name
Test status
Simulation time 8031025799 ps
CPU time 16.28 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:56 PM PST 23
Peak memory 211140 kb
Host smart-7efe3ed2-fe04-48de-8ba3-69cdd34f3218
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973379658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2973379658
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.869993367
Short name T56
Test name
Test status
Simulation time 6869282345 ps
CPU time 9.93 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:49:55 PM PST 23
Peak memory 219448 kb
Host smart-31d5ee9f-68a3-4eea-8ea1-d5ef7fabdfd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869993367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.869993367
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3131569594
Short name T133
Test name
Test status
Simulation time 1373581503 ps
CPU time 78.57 seconds
Started Dec 31 12:49:56 PM PST 23
Finished Dec 31 12:51:17 PM PST 23
Peak memory 211456 kb
Host smart-50b64652-0392-42bf-804c-1fcbbd44dcd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131569594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3131569594
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4164207516
Short name T469
Test name
Test status
Simulation time 1407289172 ps
CPU time 9.12 seconds
Started Dec 31 12:49:17 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 214168 kb
Host smart-5ab8a319-326b-45d2-a6bf-cf54ee57e6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164207516 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4164207516
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.256979894
Short name T122
Test name
Test status
Simulation time 8945315703 ps
CPU time 12.89 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:33 PM PST 23
Peak memory 211232 kb
Host smart-56d10ec0-8901-4522-b80d-eb1393e6ff42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256979894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.256979894
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.1303206215
Short name T478
Test name
Test status
Simulation time 997400519 ps
CPU time 50.88 seconds
Started Dec 31 12:49:51 PM PST 23
Finished Dec 31 12:50:44 PM PST 23
Peak memory 211224 kb
Host smart-eb7b9780-7834-48a4-86a0-94288a35e79c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303206215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.1303206215
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.4204546246
Short name T27
Test name
Test status
Simulation time 1890772983 ps
CPU time 16.08 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:36 PM PST 23
Peak memory 211168 kb
Host smart-6766e6dc-74e0-4210-9d13-7726558ce064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204546246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.4204546246
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3950679511
Short name T464
Test name
Test status
Simulation time 223991555 ps
CPU time 5.03 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:32 PM PST 23
Peak memory 214216 kb
Host smart-8dd7eefa-ad52-416d-b962-80689336dc34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950679511 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3950679511
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1025996161
Short name T446
Test name
Test status
Simulation time 1650420649 ps
CPU time 5.27 seconds
Started Dec 31 12:49:49 PM PST 23
Finished Dec 31 12:49:55 PM PST 23
Peak memory 211160 kb
Host smart-7269187f-a914-4fdd-85c2-231ce11d38f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025996161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1025996161
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.4287328520
Short name T68
Test name
Test status
Simulation time 5656020383 ps
CPU time 83.46 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:50:40 PM PST 23
Peak memory 211196 kb
Host smart-01b65d34-5503-4c75-be51-9fce2abdd920
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287328520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.4287328520
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.2938600057
Short name T131
Test name
Test status
Simulation time 1071125032 ps
CPU time 10.72 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:39 PM PST 23
Peak memory 211164 kb
Host smart-df4c59cd-ca88-42f4-bf2b-40a639efea7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938600057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.2938600057
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.607882676
Short name T119
Test name
Test status
Simulation time 5183407888 ps
CPU time 14.26 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 219436 kb
Host smart-9f04c044-6d9c-412b-8d2d-831eb70f51b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607882676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.607882676
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3839070589
Short name T113
Test name
Test status
Simulation time 998475758 ps
CPU time 11.63 seconds
Started Dec 31 12:49:52 PM PST 23
Finished Dec 31 12:50:05 PM PST 23
Peak memory 219360 kb
Host smart-1cc1a925-b534-4d8d-be8c-cc14936b5101
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839070589 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3839070589
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.151134733
Short name T98
Test name
Test status
Simulation time 724938414 ps
CPU time 8.52 seconds
Started Dec 31 12:49:30 PM PST 23
Finished Dec 31 12:49:39 PM PST 23
Peak memory 211128 kb
Host smart-3b39e248-f90e-4ecd-a7cf-75736c240e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151134733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.151134733
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3782268172
Short name T72
Test name
Test status
Simulation time 46148115496 ps
CPU time 203.67 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:53:09 PM PST 23
Peak memory 211272 kb
Host smart-021d66ab-a0cc-450e-88a6-58184885f595
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782268172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3782268172
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3098102472
Short name T93
Test name
Test status
Simulation time 347180398 ps
CPU time 4.29 seconds
Started Dec 31 12:49:56 PM PST 23
Finished Dec 31 12:50:03 PM PST 23
Peak memory 211108 kb
Host smart-0aff85e7-1701-4d89-a395-9cc52a0b968a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098102472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3098102472
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2536175255
Short name T29
Test name
Test status
Simulation time 171690570 ps
CPU time 6.64 seconds
Started Dec 31 12:49:33 PM PST 23
Finished Dec 31 12:49:42 PM PST 23
Peak memory 213968 kb
Host smart-f3839d59-409d-4806-b3ba-e11fc4091c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536175255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2536175255
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1075082460
Short name T52
Test name
Test status
Simulation time 504792753 ps
CPU time 41.34 seconds
Started Dec 31 12:49:49 PM PST 23
Finished Dec 31 12:50:32 PM PST 23
Peak memory 212188 kb
Host smart-4b1c9e54-ff04-4c2c-bb32-5b058cface79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075082460 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1075082460
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4039303643
Short name T126
Test name
Test status
Simulation time 2176920732 ps
CPU time 7.96 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:44 PM PST 23
Peak memory 213576 kb
Host smart-79d1d543-abc5-4d1e-94f0-fa2313af55ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039303643 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4039303643
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1289613146
Short name T86
Test name
Test status
Simulation time 379041924 ps
CPU time 6.85 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 211140 kb
Host smart-83e7474f-add9-4620-8e1f-c1ca8ba1eb54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289613146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1289613146
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.577390752
Short name T70
Test name
Test status
Simulation time 22240612559 ps
CPU time 115.35 seconds
Started Dec 31 12:49:36 PM PST 23
Finished Dec 31 12:51:32 PM PST 23
Peak memory 211204 kb
Host smart-e5bebd88-7881-46aa-8cf4-ec6df0820183
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577390752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.577390752
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.2960055846
Short name T79
Test name
Test status
Simulation time 1279872763 ps
CPU time 8.35 seconds
Started Dec 31 12:49:06 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 211164 kb
Host smart-a884ae07-d3d9-4d94-af46-a648f8a30bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960055846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.2960055846
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1599544367
Short name T58
Test name
Test status
Simulation time 2215665917 ps
CPU time 17.83 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 219384 kb
Host smart-4aca4066-3039-4450-9d56-f05ebadfb5bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599544367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1599544367
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2594037707
Short name T104
Test name
Test status
Simulation time 1994215077 ps
CPU time 48.77 seconds
Started Dec 31 12:49:51 PM PST 23
Finished Dec 31 12:50:42 PM PST 23
Peak memory 211940 kb
Host smart-8d962ee7-8b35-4a26-8c0e-ed405f138df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594037707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2594037707
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.4222801953
Short name T472
Test name
Test status
Simulation time 3301881404 ps
CPU time 13.93 seconds
Started Dec 31 12:49:37 PM PST 23
Finished Dec 31 12:49:52 PM PST 23
Peak memory 214436 kb
Host smart-fc55c665-28b0-4eb2-ae31-0c92caf1b1cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222801953 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.4222801953
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4131809189
Short name T83
Test name
Test status
Simulation time 692461356 ps
CPU time 4.23 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:49:53 PM PST 23
Peak memory 211128 kb
Host smart-5cfae1f0-6029-4c60-be6e-76849cff9d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131809189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4131809189
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.1087454983
Short name T129
Test name
Test status
Simulation time 1784323317 ps
CPU time 15.17 seconds
Started Dec 31 12:49:48 PM PST 23
Finished Dec 31 12:50:04 PM PST 23
Peak memory 211188 kb
Host smart-35e46fc7-de96-4312-8d78-56282804ccd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087454983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.1087454983
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1389139897
Short name T55
Test name
Test status
Simulation time 2081558271 ps
CPU time 18.66 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:43 PM PST 23
Peak memory 215840 kb
Host smart-b0dd519c-d9fe-45a3-9ba4-56439f676745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389139897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1389139897
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.880307885
Short name T106
Test name
Test status
Simulation time 416938961 ps
CPU time 77.09 seconds
Started Dec 31 12:49:49 PM PST 23
Finished Dec 31 12:51:06 PM PST 23
Peak memory 211516 kb
Host smart-a1838e5c-525b-450c-9cd6-987b175b4ade
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880307885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.880307885
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1213685091
Short name T54
Test name
Test status
Simulation time 870852086 ps
CPU time 9.74 seconds
Started Dec 31 12:49:45 PM PST 23
Finished Dec 31 12:49:56 PM PST 23
Peak memory 212976 kb
Host smart-261a95b4-4d63-4790-a7c1-e51a037f3481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213685091 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1213685091
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1528489468
Short name T479
Test name
Test status
Simulation time 287217679 ps
CPU time 6.26 seconds
Started Dec 31 12:49:36 PM PST 23
Finished Dec 31 12:49:43 PM PST 23
Peak memory 211184 kb
Host smart-f0e599c5-48a2-431a-bb28-a6bed677deaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528489468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1528489468
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.3579708445
Short name T67
Test name
Test status
Simulation time 13917950476 ps
CPU time 194.83 seconds
Started Dec 31 12:49:45 PM PST 23
Finished Dec 31 12:53:01 PM PST 23
Peak memory 211352 kb
Host smart-734c3ace-4085-48af-9925-f7c155c0035f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579708445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.3579708445
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3127131633
Short name T127
Test name
Test status
Simulation time 6566994598 ps
CPU time 14.39 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 211256 kb
Host smart-c9cd5ec9-ca55-4405-aaf4-0b64270ed8c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127131633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3127131633
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3223232151
Short name T448
Test name
Test status
Simulation time 2051674689 ps
CPU time 18.65 seconds
Started Dec 31 12:49:57 PM PST 23
Finished Dec 31 12:50:18 PM PST 23
Peak memory 219296 kb
Host smart-560f3a48-f84b-4bd5-b4eb-c9c7eab2be87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223232151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.3223232151
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3426961209
Short name T57
Test name
Test status
Simulation time 2039929057 ps
CPU time 49.34 seconds
Started Dec 31 12:49:57 PM PST 23
Finished Dec 31 12:50:49 PM PST 23
Peak memory 212336 kb
Host smart-c43c311d-97b5-44fb-8407-c8bc0a563f34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426961209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3426961209
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2118231671
Short name T475
Test name
Test status
Simulation time 333136973 ps
CPU time 4.24 seconds
Started Dec 31 12:49:26 PM PST 23
Finished Dec 31 12:49:31 PM PST 23
Peak memory 211120 kb
Host smart-cfa9011a-6f2b-4ab7-b016-bb5b95e80715
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118231671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2118231671
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.912444870
Short name T442
Test name
Test status
Simulation time 4769748520 ps
CPU time 11.65 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:49:25 PM PST 23
Peak memory 211220 kb
Host smart-5565b6ca-4c84-4dfe-8c3a-a5a90e771868
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912444870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b
ash.912444870
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3074036292
Short name T77
Test name
Test status
Simulation time 1323260578 ps
CPU time 13.37 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:52 PM PST 23
Peak memory 211104 kb
Host smart-50884c6a-2d8e-4dc0-b34a-340f43ef0cd2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074036292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3074036292
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2104613587
Short name T439
Test name
Test status
Simulation time 3932252602 ps
CPU time 9.65 seconds
Started Dec 31 12:49:13 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 214356 kb
Host smart-1da958b6-ae88-40a1-af31-55298ac5cdbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104613587 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.2104613587
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2469338905
Short name T90
Test name
Test status
Simulation time 171504833 ps
CPU time 5.65 seconds
Started Dec 31 12:50:07 PM PST 23
Finished Dec 31 12:50:13 PM PST 23
Peak memory 211232 kb
Host smart-48a627c8-c88b-44d4-b842-6e92ea3b0d77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469338905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2469338905
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3518449162
Short name T476
Test name
Test status
Simulation time 4533241272 ps
CPU time 11 seconds
Started Dec 31 12:49:41 PM PST 23
Finished Dec 31 12:49:53 PM PST 23
Peak memory 211208 kb
Host smart-cd191c25-fe48-4ea4-a54f-643ac72e44e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518449162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3518449162
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.1985200342
Short name T449
Test name
Test status
Simulation time 32327661924 ps
CPU time 74.24 seconds
Started Dec 31 12:49:40 PM PST 23
Finished Dec 31 12:50:56 PM PST 23
Peak memory 211204 kb
Host smart-4096b4b9-15ac-4ab5-96a3-f68df4f838ed
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985200342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.1985200342
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3023023840
Short name T130
Test name
Test status
Simulation time 1700150048 ps
CPU time 13.56 seconds
Started Dec 31 12:48:58 PM PST 23
Finished Dec 31 12:49:13 PM PST 23
Peak memory 211184 kb
Host smart-02472083-d21c-42cb-a240-20f96e5cc3ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023023840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3023023840
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.612544032
Short name T134
Test name
Test status
Simulation time 1566915230 ps
CPU time 78.21 seconds
Started Dec 31 12:49:42 PM PST 23
Finished Dec 31 12:51:01 PM PST 23
Peak memory 211452 kb
Host smart-1b544241-cde0-4de0-ac69-55ef88abc5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612544032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.612544032
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2342082561
Short name T481
Test name
Test status
Simulation time 319852363 ps
CPU time 4.48 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:49:16 PM PST 23
Peak memory 211168 kb
Host smart-093045d2-2c57-4858-8e02-4b373c8dcc0e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342082561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2342082561
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.1117297524
Short name T432
Test name
Test status
Simulation time 910902330 ps
CPU time 7.51 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:49:52 PM PST 23
Peak memory 211128 kb
Host smart-4996d622-8e92-48b7-af65-2e2ee80299c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117297524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.1117297524
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1059161106
Short name T95
Test name
Test status
Simulation time 3461333026 ps
CPU time 17.76 seconds
Started Dec 31 12:49:08 PM PST 23
Finished Dec 31 12:49:27 PM PST 23
Peak memory 211164 kb
Host smart-854bf385-a65a-4950-a04e-2391529693d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059161106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1059161106
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3932782964
Short name T461
Test name
Test status
Simulation time 6754835586 ps
CPU time 14.28 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:34 PM PST 23
Peak memory 214860 kb
Host smart-480fda60-2801-418e-8263-ef7ab0880fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932782964 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.3932782964
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1996775350
Short name T433
Test name
Test status
Simulation time 826020416 ps
CPU time 7.18 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:32 PM PST 23
Peak memory 211168 kb
Host smart-9c654d3a-ef9b-43da-b719-a6301158059e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996775350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1996775350
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2341537406
Short name T466
Test name
Test status
Simulation time 89184382 ps
CPU time 4.3 seconds
Started Dec 31 12:49:28 PM PST 23
Finished Dec 31 12:49:33 PM PST 23
Peak memory 211140 kb
Host smart-92b3c036-2a22-407a-8146-8b39a01088e6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341537406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2341537406
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.3960168339
Short name T441
Test name
Test status
Simulation time 1815202556 ps
CPU time 14.54 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 211180 kb
Host smart-d5342fd5-a917-4e64-b663-56d9cd1ff851
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960168339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.3960168339
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.759419020
Short name T89
Test name
Test status
Simulation time 23655358523 ps
CPU time 129.91 seconds
Started Dec 31 12:49:12 PM PST 23
Finished Dec 31 12:51:23 PM PST 23
Peak memory 211216 kb
Host smart-1cfe39da-d691-4418-9f07-5bcc9ff515a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759419020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pas
sthru_mem_tl_intg_err.759419020
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1455001326
Short name T440
Test name
Test status
Simulation time 1946615838 ps
CPU time 17.21 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:38 PM PST 23
Peak memory 211184 kb
Host smart-156cc575-ecf7-44cc-85fe-366fd79a7a5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455001326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1455001326
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2962755757
Short name T138
Test name
Test status
Simulation time 88908068 ps
CPU time 8.04 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 214260 kb
Host smart-b7d8ba32-f6e5-4ec3-8772-bc46b5e2d8c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962755757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2962755757
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2163099978
Short name T132
Test name
Test status
Simulation time 1603644671 ps
CPU time 6.5 seconds
Started Dec 31 12:49:15 PM PST 23
Finished Dec 31 12:49:24 PM PST 23
Peak memory 211148 kb
Host smart-71be9735-9a1e-4cb3-a1e7-3aec6af2dab5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163099978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2163099978
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1220030385
Short name T437
Test name
Test status
Simulation time 5252547063 ps
CPU time 12.52 seconds
Started Dec 31 12:49:27 PM PST 23
Finished Dec 31 12:49:41 PM PST 23
Peak memory 211188 kb
Host smart-3d55d4e9-630a-4346-a85b-7d66447917d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220030385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1220030385
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.855883060
Short name T88
Test name
Test status
Simulation time 1980275944 ps
CPU time 18.3 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:37 PM PST 23
Peak memory 211184 kb
Host smart-49a4036a-9273-46ae-9d42-b2b1ba05ba41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855883060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.855883060
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2947459819
Short name T112
Test name
Test status
Simulation time 7675609533 ps
CPU time 15.91 seconds
Started Dec 31 12:49:22 PM PST 23
Finished Dec 31 12:49:39 PM PST 23
Peak memory 214628 kb
Host smart-0b42879c-463f-4b83-aff6-7f2f9bb95b8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947459819 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2947459819
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3376081690
Short name T92
Test name
Test status
Simulation time 3375360256 ps
CPU time 13.81 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:53 PM PST 23
Peak memory 210872 kb
Host smart-ef9e3a16-cbd0-4b95-8c2f-1efc51c8d1aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376081690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3376081690
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1500802037
Short name T137
Test name
Test status
Simulation time 85802509 ps
CPU time 4.29 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 211256 kb
Host smart-774fa7f5-61b7-4d9e-b91e-a4290a4414bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500802037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1500802037
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.4279670275
Short name T438
Test name
Test status
Simulation time 90226651 ps
CPU time 4.3 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:49:15 PM PST 23
Peak memory 211188 kb
Host smart-ccf74bc4-a649-473c-9c72-54f67d386847
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279670275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.4279670275
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2830951778
Short name T22
Test name
Test status
Simulation time 75888138290 ps
CPU time 209.97 seconds
Started Dec 31 12:49:44 PM PST 23
Finished Dec 31 12:53:15 PM PST 23
Peak memory 211184 kb
Host smart-e6f081c0-faff-4819-b818-635ed6caa1ec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830951778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2830951778
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.4177512023
Short name T468
Test name
Test status
Simulation time 2206759390 ps
CPU time 16.26 seconds
Started Dec 31 12:49:11 PM PST 23
Finished Dec 31 12:49:28 PM PST 23
Peak memory 211260 kb
Host smart-43c12093-10e8-4f12-84ef-6729d9be8f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177512023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.4177512023
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2512435859
Short name T103
Test name
Test status
Simulation time 1510603054 ps
CPU time 47.11 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:50:19 PM PST 23
Peak memory 212340 kb
Host smart-292351f0-b952-47b7-85a2-efdd8899c352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512435859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.2512435859
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3884261443
Short name T463
Test name
Test status
Simulation time 8544881306 ps
CPU time 18.18 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:44 PM PST 23
Peak memory 216716 kb
Host smart-d7f3e526-bdd6-491b-9c9f-2201025f955e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884261443 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3884261443
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3617947013
Short name T435
Test name
Test status
Simulation time 2084500670 ps
CPU time 12.49 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:57 PM PST 23
Peak memory 211124 kb
Host smart-21479b2a-e238-46b1-b772-a5f9350cbc50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617947013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3617947013
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.966370425
Short name T42
Test name
Test status
Simulation time 35116095077 ps
CPU time 291.33 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:54:06 PM PST 23
Peak memory 219380 kb
Host smart-388411fa-d6c9-4a19-a5eb-3a0424a50109
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966370425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.966370425
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.52655640
Short name T456
Test name
Test status
Simulation time 5840716920 ps
CPU time 13.19 seconds
Started Dec 31 12:49:36 PM PST 23
Finished Dec 31 12:49:51 PM PST 23
Peak memory 211284 kb
Host smart-602d0231-7e60-41af-b807-300f57bbcf20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52655640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctr
l_same_csr_outstanding.52655640
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.439756556
Short name T101
Test name
Test status
Simulation time 429072236 ps
CPU time 9.02 seconds
Started Dec 31 12:49:18 PM PST 23
Finished Dec 31 12:49:29 PM PST 23
Peak memory 213912 kb
Host smart-c617bdf2-1761-4140-9e8c-6493c001ae16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439756556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.439756556
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.526064548
Short name T465
Test name
Test status
Simulation time 2006150562 ps
CPU time 74.56 seconds
Started Dec 31 12:49:41 PM PST 23
Finished Dec 31 12:50:57 PM PST 23
Peak memory 211492 kb
Host smart-867af2a2-5a4e-4e47-9c3b-fe9f456e27d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526064548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.526064548
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2142391421
Short name T470
Test name
Test status
Simulation time 91470013 ps
CPU time 4.6 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 212440 kb
Host smart-3be5b2f4-8b18-4845-93ad-42d8726cd20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142391421 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2142391421
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3726929636
Short name T436
Test name
Test status
Simulation time 8015587669 ps
CPU time 15.4 seconds
Started Dec 31 12:49:31 PM PST 23
Finished Dec 31 12:49:47 PM PST 23
Peak memory 211212 kb
Host smart-2e6163f8-2120-4596-81f8-58fcd7ad1efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726929636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3726929636
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2939541274
Short name T71
Test name
Test status
Simulation time 4036157468 ps
CPU time 50.83 seconds
Started Dec 31 12:49:06 PM PST 23
Finished Dec 31 12:49:58 PM PST 23
Peak memory 211204 kb
Host smart-99e6b488-0972-4b4e-8f5a-94aeff6915c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939541274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2939541274
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2692416614
Short name T135
Test name
Test status
Simulation time 161418783 ps
CPU time 4.38 seconds
Started Dec 31 12:49:05 PM PST 23
Finished Dec 31 12:49:11 PM PST 23
Peak memory 211128 kb
Host smart-5e4b442b-3939-4610-845e-13a0b2069362
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692416614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2692416614
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1677043289
Short name T136
Test name
Test status
Simulation time 437792845 ps
CPU time 6.26 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:46 PM PST 23
Peak memory 219372 kb
Host smart-840d66eb-58b4-46a8-aba5-15ab8804fb94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677043289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1677043289
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2576546223
Short name T109
Test name
Test status
Simulation time 4606091910 ps
CPU time 79.73 seconds
Started Dec 31 12:49:10 PM PST 23
Finished Dec 31 12:50:33 PM PST 23
Peak memory 211556 kb
Host smart-6b10ea8b-f8ab-43e2-9dca-b60e3f53abff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576546223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2576546223
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.1435119725
Short name T482
Test name
Test status
Simulation time 1250873125 ps
CPU time 11.89 seconds
Started Dec 31 12:49:52 PM PST 23
Finished Dec 31 12:50:06 PM PST 23
Peak memory 214072 kb
Host smart-0e0d047a-1b8a-4871-af28-f76e4c19e865
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435119725 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.1435119725
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.323462961
Short name T96
Test name
Test status
Simulation time 7547561623 ps
CPU time 14.55 seconds
Started Dec 31 12:49:32 PM PST 23
Finished Dec 31 12:49:47 PM PST 23
Peak memory 211188 kb
Host smart-90c57bb6-fca4-48fa-a29a-d81106cd42cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323462961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.323462961
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.469274211
Short name T477
Test name
Test status
Simulation time 1577683231 ps
CPU time 13.15 seconds
Started Dec 31 12:49:34 PM PST 23
Finished Dec 31 12:49:49 PM PST 23
Peak memory 211196 kb
Host smart-1a4b8118-0398-4954-9539-02db8f62d2fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469274211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.469274211
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3033556388
Short name T114
Test name
Test status
Simulation time 1569584670 ps
CPU time 16.13 seconds
Started Dec 31 12:49:51 PM PST 23
Finished Dec 31 12:50:08 PM PST 23
Peak memory 219336 kb
Host smart-4e3f3c5d-69b4-4d96-9df1-6d041dd7557f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033556388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3033556388
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1824474959
Short name T107
Test name
Test status
Simulation time 626688747 ps
CPU time 40.54 seconds
Started Dec 31 12:49:39 PM PST 23
Finished Dec 31 12:50:22 PM PST 23
Peak memory 212132 kb
Host smart-52be3855-f468-4b99-8e1d-622d75069aef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824474959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1824474959
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3792563835
Short name T457
Test name
Test status
Simulation time 275907356 ps
CPU time 5.39 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:30 PM PST 23
Peak memory 213940 kb
Host smart-4d74cabd-471e-4c3a-b88b-e9510117defd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792563835 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3792563835
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.703809603
Short name T80
Test name
Test status
Simulation time 1137206126 ps
CPU time 11.11 seconds
Started Dec 31 12:49:46 PM PST 23
Finished Dec 31 12:49:58 PM PST 23
Peak memory 211128 kb
Host smart-0c1d6ad8-0855-4f0a-b0e1-6c674a405750
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703809603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.703809603
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.1411244074
Short name T91
Test name
Test status
Simulation time 34158410255 ps
CPU time 141.21 seconds
Started Dec 31 12:49:53 PM PST 23
Finished Dec 31 12:52:17 PM PST 23
Peak memory 211276 kb
Host smart-51d01664-ba2b-459f-a5e4-8198a9342dbd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411244074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.1411244074
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2604018619
Short name T128
Test name
Test status
Simulation time 85536993 ps
CPU time 4.44 seconds
Started Dec 31 12:49:23 PM PST 23
Finished Dec 31 12:49:29 PM PST 23
Peak memory 211140 kb
Host smart-8a7f54be-2e9a-41be-8f33-e1ceb397bef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604018619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2604018619
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.3749660243
Short name T115
Test name
Test status
Simulation time 2306047601 ps
CPU time 13.98 seconds
Started Dec 31 12:49:24 PM PST 23
Finished Dec 31 12:49:40 PM PST 23
Peak memory 219432 kb
Host smart-bf3fc1e8-1423-4023-b8a0-b65cef4b74fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749660243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.3749660243
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.880917112
Short name T111
Test name
Test status
Simulation time 1758407787 ps
CPU time 82.38 seconds
Started Dec 31 12:49:14 PM PST 23
Finished Dec 31 12:50:37 PM PST 23
Peak memory 211332 kb
Host smart-ce9c4184-bc60-40aa-bba7-ea40327668e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880917112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.880917112
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1316444869
Short name T460
Test name
Test status
Simulation time 12553060831 ps
CPU time 14.74 seconds
Started Dec 31 12:49:25 PM PST 23
Finished Dec 31 12:49:45 PM PST 23
Peak memory 214168 kb
Host smart-fb3147da-fd98-49fa-81b9-dd33ce289a14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316444869 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1316444869
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2124068083
Short name T30
Test name
Test status
Simulation time 1138636311 ps
CPU time 10.51 seconds
Started Dec 31 12:49:38 PM PST 23
Finished Dec 31 12:49:50 PM PST 23
Peak memory 210924 kb
Host smart-1e1d88dd-5af7-40db-942f-2ca7e9faa821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124068083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2124068083
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2421027312
Short name T474
Test name
Test status
Simulation time 333792914 ps
CPU time 4.31 seconds
Started Dec 31 12:49:19 PM PST 23
Finished Dec 31 12:49:25 PM PST 23
Peak memory 211172 kb
Host smart-8b7ca719-3edc-46e3-89ad-bf73ec5bb792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421027312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c
trl_same_csr_outstanding.2421027312
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1565039508
Short name T51
Test name
Test status
Simulation time 1766621301 ps
CPU time 16.96 seconds
Started Dec 31 12:49:21 PM PST 23
Finished Dec 31 12:49:39 PM PST 23
Peak memory 219392 kb
Host smart-074c7b2c-2bcd-4182-83d5-ab8dd3a42505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565039508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1565039508
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3502267765
Short name T105
Test name
Test status
Simulation time 1549126737 ps
CPU time 76.39 seconds
Started Dec 31 12:49:42 PM PST 23
Finished Dec 31 12:51:00 PM PST 23
Peak memory 211324 kb
Host smart-12e7f699-90fd-43b7-a310-07f7728e3af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502267765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3502267765
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.1371909255
Short name T229
Test name
Test status
Simulation time 174675353 ps
CPU time 4.29 seconds
Started Dec 31 12:54:17 PM PST 23
Finished Dec 31 12:54:28 PM PST 23
Peak memory 210892 kb
Host smart-d7537b8c-4f2e-49df-ac22-53d422075060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371909255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1371909255
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1799258834
Short name T277
Test name
Test status
Simulation time 4489903279 ps
CPU time 146.91 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 12:57:01 PM PST 23
Peak memory 237384 kb
Host smart-e2df023e-1fe6-4d34-a1ab-038ffca80fc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799258834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1799258834
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.1673962692
Short name T317
Test name
Test status
Simulation time 5135144234 ps
CPU time 12.06 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 210860 kb
Host smart-e5e71893-c0bc-47ed-b614-638b432bb174
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673962692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.1673962692
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1856100012
Short name T4
Test name
Test status
Simulation time 373081624 ps
CPU time 10.35 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 212100 kb
Host smart-34d47dd9-9a5d-4cd0-b18c-d85b6c8dcc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856100012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1856100012
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.3125488386
Short name T281
Test name
Test status
Simulation time 396873644 ps
CPU time 22.14 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 215024 kb
Host smart-582accae-5f70-4769-bcbb-36532b1c1974
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125488386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.3125488386
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2751742919
Short name T348
Test name
Test status
Simulation time 46591232964 ps
CPU time 2311.97 seconds
Started Dec 31 12:54:22 PM PST 23
Finished Dec 31 01:32:56 PM PST 23
Peak memory 236588 kb
Host smart-30e95133-d5e2-478d-8157-ab0ad40616c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751742919 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2751742919
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2557526376
Short name T226
Test name
Test status
Simulation time 1707130332 ps
CPU time 14.76 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 210916 kb
Host smart-b9c1292c-f953-42ec-aa4e-e8ecfe278242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557526376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2557526376
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3762616147
Short name T262
Test name
Test status
Simulation time 210014247851 ps
CPU time 406.25 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 01:01:39 PM PST 23
Peak memory 233792 kb
Host smart-174ebb29-2ae4-419f-8f95-26c98ed57082
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762616147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3762616147
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3300505805
Short name T204
Test name
Test status
Simulation time 791983461 ps
CPU time 9.61 seconds
Started Dec 31 12:54:09 PM PST 23
Finished Dec 31 12:54:23 PM PST 23
Peak memory 211048 kb
Host smart-5218e005-ab10-4659-960b-58cd7e702bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300505805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3300505805
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.397090580
Short name T256
Test name
Test status
Simulation time 1365039070 ps
CPU time 13.49 seconds
Started Dec 31 12:54:13 PM PST 23
Finished Dec 31 12:54:30 PM PST 23
Peak memory 210808 kb
Host smart-31401d81-7bbd-4382-a5da-d05a9d0ad2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397090580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.397090580
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3272283505
Short name T44
Test name
Test status
Simulation time 2779408512 ps
CPU time 118.24 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:56:54 PM PST 23
Peak memory 236476 kb
Host smart-61999af6-9dc5-4d2c-9725-7f7a52fe3d84
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272283505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3272283505
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1738926461
Short name T425
Test name
Test status
Simulation time 3020748337 ps
CPU time 33.47 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 212004 kb
Host smart-41bcf6d3-57d6-475d-9a18-3b4beaf2cb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738926461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1738926461
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.1660171457
Short name T172
Test name
Test status
Simulation time 1704832333 ps
CPU time 15.69 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 210640 kb
Host smart-59578227-e604-4d39-92a4-43cc82dccd57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660171457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.1660171457
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4122554545
Short name T275
Test name
Test status
Simulation time 105065286427 ps
CPU time 9581.24 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 03:34:44 PM PST 23
Peak memory 235464 kb
Host smart-f9b353f3-20a5-4b21-931c-212a6056e210
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122554545 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4122554545
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.165139622
Short name T199
Test name
Test status
Simulation time 2271248132 ps
CPU time 16.13 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 210980 kb
Host smart-0d54897d-0084-4587-a9e2-ff1c56d58e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165139622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.165139622
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1264094018
Short name T429
Test name
Test status
Simulation time 2290383981 ps
CPU time 23.62 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 210812 kb
Host smart-44389ec5-1b38-461c-a658-35c55a7ed1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264094018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1264094018
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.405979053
Short name T282
Test name
Test status
Simulation time 1053085190 ps
CPU time 11.46 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 210812 kb
Host smart-b6db0adf-8aef-4757-8d9c-1b98e8241903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=405979053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.405979053
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.831328912
Short name T180
Test name
Test status
Simulation time 1657667283 ps
CPU time 22.4 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 212636 kb
Host smart-463db0d5-ec52-4536-9dee-d3d0bff5fdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831328912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.831328912
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.2788869797
Short name T365
Test name
Test status
Simulation time 411825094 ps
CPU time 25.54 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 215408 kb
Host smart-ed41885b-fcb3-46f0-9b31-9711166a5ed7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788869797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.2788869797
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.965638771
Short name T212
Test name
Test status
Simulation time 3914589745 ps
CPU time 9.84 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210840 kb
Host smart-b311ddae-8667-4b3a-8f9d-65e143a1f5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965638771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.965638771
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2153305016
Short name T309
Test name
Test status
Simulation time 68335172066 ps
CPU time 204.02 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:58:13 PM PST 23
Peak memory 237440 kb
Host smart-7d70a649-513c-4571-ae6d-ac4f8d1d6ffb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153305016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2153305016
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1020389645
Short name T339
Test name
Test status
Simulation time 101844723 ps
CPU time 5.82 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 210836 kb
Host smart-2f0d14cc-4415-490d-ac75-d70e48d2c48e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020389645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1020389645
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.592156977
Short name T46
Test name
Test status
Simulation time 14096417881 ps
CPU time 35.46 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 211404 kb
Host smart-f02b0f8b-7b9a-453a-b2ac-604adeb489ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592156977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.592156977
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.2040757432
Short name T328
Test name
Test status
Simulation time 7286916482 ps
CPU time 68.85 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 12:55:43 PM PST 23
Peak memory 216048 kb
Host smart-25101313-8169-467b-8dd6-b6e259f3fa50
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040757432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.2040757432
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.3488919187
Short name T18
Test name
Test status
Simulation time 61745991394 ps
CPU time 507.56 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 01:03:22 PM PST 23
Peak memory 232872 kb
Host smart-2e84ff14-e6f4-4c1a-aecd-5d7b5cbd2fb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488919187 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.3488919187
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.3140347896
Short name T410
Test name
Test status
Simulation time 12466676376 ps
CPU time 16.17 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 211004 kb
Host smart-8b326e95-23f3-46d3-9d7d-42489fa7049b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140347896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.3140347896
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1570240016
Short name T357
Test name
Test status
Simulation time 3657434079 ps
CPU time 14.03 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:47 PM PST 23
Peak memory 210864 kb
Host smart-150656de-8f2c-4350-ada0-417404c64d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570240016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1570240016
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.200237138
Short name T332
Test name
Test status
Simulation time 377322293 ps
CPU time 5.48 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 210864 kb
Host smart-2b7cfc89-482c-447d-8932-97b85fba0522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=200237138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.200237138
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1238037147
Short name T11
Test name
Test status
Simulation time 7945922228 ps
CPU time 23.14 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 212888 kb
Host smart-c4e64869-b17a-49f0-8a21-465fa9df1eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238037147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1238037147
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1843004092
Short name T330
Test name
Test status
Simulation time 2724452415 ps
CPU time 17.02 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 213948 kb
Host smart-4680d491-5dc5-48a6-8a9b-1017770e2050
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843004092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1843004092
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.565163489
Short name T148
Test name
Test status
Simulation time 46719807752 ps
CPU time 2188.62 seconds
Started Dec 31 12:54:10 PM PST 23
Finished Dec 31 01:30:43 PM PST 23
Peak memory 229612 kb
Host smart-04f3a2d5-af1b-491a-8237-ba2c77971159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565163489 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.565163489
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.270912611
Short name T261
Test name
Test status
Simulation time 2040775648 ps
CPU time 15.98 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 210908 kb
Host smart-fb9027fa-75da-45b4-bca4-8c8493e17499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270912611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.270912611
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.1600830707
Short name T269
Test name
Test status
Simulation time 5248042793 ps
CPU time 13.79 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210840 kb
Host smart-a9458a5b-c0b1-4800-b527-b6d78378a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600830707 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.1600830707
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1496114223
Short name T99
Test name
Test status
Simulation time 380809576 ps
CPU time 5.83 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 210676 kb
Host smart-3e94b5bc-94ce-4731-88e9-5efa10025d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1496114223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1496114223
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2815518893
Short name T211
Test name
Test status
Simulation time 7529207818 ps
CPU time 16.66 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 213336 kb
Host smart-114dd40d-ed1d-4d06-9c84-2fc0a58c0c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815518893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2815518893
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.922543908
Short name T420
Test name
Test status
Simulation time 746505145 ps
CPU time 14.79 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 212780 kb
Host smart-51b5fb13-2364-4d63-bd7b-47daa81dd053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922543908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.922543908
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.380523927
Short name T345
Test name
Test status
Simulation time 78893267160 ps
CPU time 9383.89 seconds
Started Dec 31 12:54:25 PM PST 23
Finished Dec 31 03:30:52 PM PST 23
Peak memory 237412 kb
Host smart-b9ff7397-53b4-4f74-aa69-ab150d6560de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380523927 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.380523927
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1834937826
Short name T250
Test name
Test status
Simulation time 50283105340 ps
CPU time 320.04 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:59:47 PM PST 23
Peak memory 236356 kb
Host smart-dfd1a3ed-0ed1-48f9-9ea2-356242bc2402
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834937826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1834937826
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.2609619849
Short name T202
Test name
Test status
Simulation time 171742320 ps
CPU time 9.77 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 210968 kb
Host smart-618a2fc1-0021-4354-a729-db9429067d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609619849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.2609619849
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.1721916195
Short name T313
Test name
Test status
Simulation time 12621344158 ps
CPU time 13.84 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 210864 kb
Host smart-74b11a96-340f-4331-9853-c1d9c952f3fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721916195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.1721916195
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2327796280
Short name T283
Test name
Test status
Simulation time 524178089 ps
CPU time 14.18 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 212784 kb
Host smart-3f240e9c-e496-4502-9cdd-b9578867450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327796280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2327796280
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2261789513
Short name T160
Test name
Test status
Simulation time 1159225784 ps
CPU time 17.46 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 212748 kb
Host smart-2e7664bd-ead4-48ab-b458-69b272a86bc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261789513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2261789513
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.280452960
Short name T140
Test name
Test status
Simulation time 2200868478 ps
CPU time 13.06 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 210960 kb
Host smart-88d435e5-2236-4dcf-a234-089d06ec4c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280452960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.280452960
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1236176483
Short name T249
Test name
Test status
Simulation time 856528200 ps
CPU time 15.03 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 210988 kb
Host smart-fcb46327-492b-42b3-a22a-fde8e90a26df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236176483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1236176483
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.790722016
Short name T290
Test name
Test status
Simulation time 1222158475 ps
CPU time 9.31 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 210816 kb
Host smart-d6a0c068-a3a4-41ec-9352-34a47a8f9223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=790722016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.790722016
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.2505189258
Short name T142
Test name
Test status
Simulation time 184570840 ps
CPU time 10.85 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:54:43 PM PST 23
Peak memory 212484 kb
Host smart-970f3d28-5b4e-4d1a-9096-5a215ea33be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505189258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2505189258
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3536797843
Short name T301
Test name
Test status
Simulation time 10888782144 ps
CPU time 46.66 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:41 PM PST 23
Peak memory 214016 kb
Host smart-f57be6c3-6abb-4141-81e2-c161df73c7bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536797843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3536797843
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2218896229
Short name T298
Test name
Test status
Simulation time 89755721099 ps
CPU time 4043.23 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 02:02:07 PM PST 23
Peak memory 235584 kb
Host smart-28dac4ad-b9d1-4c54-bb97-55ea6cd090e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218896229 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2218896229
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1815798477
Short name T8
Test name
Test status
Simulation time 8411187856 ps
CPU time 13.91 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:54:46 PM PST 23
Peak memory 211000 kb
Host smart-23ca717b-74fd-4b85-b1d8-5849acf750ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815798477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1815798477
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2534289886
Short name T175
Test name
Test status
Simulation time 66604062330 ps
CPU time 320.85 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 01:00:23 PM PST 23
Peak memory 236372 kb
Host smart-d214b080-1872-4411-88f5-7f227405d9d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534289886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2534289886
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.496913889
Short name T2
Test name
Test status
Simulation time 334723079 ps
CPU time 9.81 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 210992 kb
Host smart-020bcdbf-8b2d-4015-a4fe-c0960ede3478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496913889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.496913889
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1298393572
Short name T189
Test name
Test status
Simulation time 2034023655 ps
CPU time 11.7 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 210784 kb
Host smart-a4e3dd07-0c9f-47a0-b4b8-27f983b23cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1298393572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1298393572
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.562471010
Short name T381
Test name
Test status
Simulation time 542614773 ps
CPU time 13.79 seconds
Started Dec 31 12:55:18 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 212628 kb
Host smart-c45b8626-1763-4086-bc8d-aaf703fe9a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562471010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.562471010
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.825447084
Short name T390
Test name
Test status
Simulation time 1299475429 ps
CPU time 20.41 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 212712 kb
Host smart-ad33133c-ee20-42d7-990f-dbed48785306
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825447084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.825447084
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2579034284
Short name T292
Test name
Test status
Simulation time 301173377889 ps
CPU time 2775.73 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 01:41:03 PM PST 23
Peak memory 243780 kb
Host smart-d14563c0-f990-4a2f-aa64-2dc908225fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579034284 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2579034284
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.684823629
Short name T364
Test name
Test status
Simulation time 7627925884 ps
CPU time 15.91 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 211020 kb
Host smart-0d2bef8a-e209-4b19-a62b-454f0a823b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684823629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.684823629
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1869014525
Short name T47
Test name
Test status
Simulation time 23911645487 ps
CPU time 322.77 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 01:00:43 PM PST 23
Peak memory 237436 kb
Host smart-d3761e42-faeb-4306-bdb7-0310d099d803
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869014525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1869014525
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.957609489
Short name T5
Test name
Test status
Simulation time 38558967450 ps
CPU time 33.39 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:42 PM PST 23
Peak memory 211412 kb
Host smart-d92b7090-f2bb-4b6d-9f8a-b624b492daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957609489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.957609489
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3539680364
Short name T377
Test name
Test status
Simulation time 583070010 ps
CPU time 5.77 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 210872 kb
Host smart-08119bc0-f2b6-4375-976d-b5b54c75484b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539680364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3539680364
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2675194815
Short name T353
Test name
Test status
Simulation time 3108429330 ps
CPU time 36.89 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 212428 kb
Host smart-01e6bdd8-536b-4633-b092-9472c0163b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675194815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2675194815
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2761153413
Short name T384
Test name
Test status
Simulation time 15958618774 ps
CPU time 42.96 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 219060 kb
Host smart-fba86e2d-6631-4113-964d-42dc9bc9a80f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761153413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2761153413
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.244826200
Short name T359
Test name
Test status
Simulation time 16707668134 ps
CPU time 3394.84 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 01:51:17 PM PST 23
Peak memory 227408 kb
Host smart-932a12fe-7036-4fc0-8352-8632ca80ac5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244826200 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.244826200
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.97283562
Short name T40
Test name
Test status
Simulation time 7665093067 ps
CPU time 15.47 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210976 kb
Host smart-e6390549-8efa-4b5c-9a5b-b728ddb732b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97283562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.97283562
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.905776922
Short name T248
Test name
Test status
Simulation time 32243991834 ps
CPU time 282.96 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:59:55 PM PST 23
Peak memory 228176 kb
Host smart-1c69cff5-d651-4544-b5cd-26aa0116e5bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905776922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.905776922
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.1289013699
Short name T219
Test name
Test status
Simulation time 414785282 ps
CPU time 12.46 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 211908 kb
Host smart-63447666-a720-4c07-864d-ba7440d18c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289013699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.1289013699
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1445755268
Short name T338
Test name
Test status
Simulation time 7551954134 ps
CPU time 15.34 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210900 kb
Host smart-ed8fb804-66df-4243-9d9c-aa983d617f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445755268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1445755268
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1702196483
Short name T405
Test name
Test status
Simulation time 367910151 ps
CPU time 9.78 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 212356 kb
Host smart-97a75f2f-5656-4ef6-81f2-26453fc757dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702196483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1702196483
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2953058722
Short name T360
Test name
Test status
Simulation time 5928136796 ps
CPU time 23.55 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 214056 kb
Host smart-55db0a55-c98a-4566-910e-34bb3f480d6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953058722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2953058722
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3761648519
Short name T352
Test name
Test status
Simulation time 64548669926 ps
CPU time 10468 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 03:49:34 PM PST 23
Peak memory 248824 kb
Host smart-a493da81-5d86-42a5-977a-82c326bb8ecc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761648519 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3761648519
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.3716182862
Short name T318
Test name
Test status
Simulation time 96115506 ps
CPU time 4.45 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 210948 kb
Host smart-4c56178f-09c3-4267-9668-722538ba6ee5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716182862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.3716182862
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1290454737
Short name T50
Test name
Test status
Simulation time 144501125701 ps
CPU time 382.98 seconds
Started Dec 31 12:55:21 PM PST 23
Finished Dec 31 01:01:49 PM PST 23
Peak memory 212116 kb
Host smart-38cf907a-862d-47cf-9c31-853dbae5ffec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290454737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1290454737
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.2717891352
Short name T10
Test name
Test status
Simulation time 175806552 ps
CPU time 9.67 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 210872 kb
Host smart-0ccbafed-136e-49b5-9364-4ccf85dbb750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717891352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.2717891352
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.2349652904
Short name T13
Test name
Test status
Simulation time 3725300186 ps
CPU time 16.42 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 210884 kb
Host smart-68f5464b-c788-42e6-85f3-a0c3620e7a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2349652904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.2349652904
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1430949824
Short name T9
Test name
Test status
Simulation time 3450379460 ps
CPU time 29.93 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:45 PM PST 23
Peak memory 212504 kb
Host smart-648dc9e0-829f-454e-a6cf-32fbec031ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430949824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1430949824
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.1759885002
Short name T166
Test name
Test status
Simulation time 1108509534 ps
CPU time 16.29 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 215480 kb
Host smart-0ca622e3-796b-424a-9fac-542453997d32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759885002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.1759885002
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.856428096
Short name T190
Test name
Test status
Simulation time 28318570492 ps
CPU time 2972.72 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 01:44:53 PM PST 23
Peak memory 229876 kb
Host smart-359d1210-cb4e-40a2-8430-e3803634fabe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856428096 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.856428096
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1858896378
Short name T293
Test name
Test status
Simulation time 5845676337 ps
CPU time 13.34 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 210900 kb
Host smart-742b01cb-7716-42f1-984c-df067b8e06bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858896378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1858896378
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.329374940
Short name T184
Test name
Test status
Simulation time 158797450969 ps
CPU time 374.84 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 01:00:57 PM PST 23
Peak memory 227272 kb
Host smart-a0f852b2-11b2-4982-b4c2-e6a3a2e9df54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329374940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.329374940
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.617729260
Short name T162
Test name
Test status
Simulation time 4193475154 ps
CPU time 32.38 seconds
Started Dec 31 12:54:15 PM PST 23
Finished Dec 31 12:54:50 PM PST 23
Peak memory 211064 kb
Host smart-7b965594-4ba7-4097-8722-1c4ef4cf3dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617729260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.617729260
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.254448960
Short name T168
Test name
Test status
Simulation time 1340156120 ps
CPU time 13.78 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 210848 kb
Host smart-6a0f5809-4754-4df9-b4f6-f1a4c43ad0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=254448960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.254448960
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2411840567
Short name T39
Test name
Test status
Simulation time 8754895895 ps
CPU time 67.86 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:56:26 PM PST 23
Peak memory 236384 kb
Host smart-89cbae32-5386-43ae-93d1-9eca3c09a15a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411840567 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2411840567
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.1553289929
Short name T387
Test name
Test status
Simulation time 1782812997 ps
CPU time 13.31 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 212576 kb
Host smart-f7d5cf6b-5b95-4fd7-a538-99e30e2c0839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553289929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1553289929
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.701154331
Short name T337
Test name
Test status
Simulation time 2741905907 ps
CPU time 11.57 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 211224 kb
Host smart-cadd7ee9-f2b8-42fc-861f-b1620ab41854
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701154331 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.rom_ctrl_stress_all.701154331
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1820244548
Short name T419
Test name
Test status
Simulation time 214392576594 ps
CPU time 7556.15 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 03:00:39 PM PST 23
Peak memory 243748 kb
Host smart-e765dbb3-0e7f-4f75-ba90-f73fcf6bb51d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820244548 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1820244548
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1342989057
Short name T373
Test name
Test status
Simulation time 3410517333 ps
CPU time 9.05 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 211004 kb
Host smart-cdc3215a-7264-4cdf-b977-09e52217682a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342989057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1342989057
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.2192718627
Short name T246
Test name
Test status
Simulation time 24062587018 ps
CPU time 261.65 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:59:35 PM PST 23
Peak memory 236504 kb
Host smart-faf552a9-b4db-4754-980a-a41a256fecac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192718627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.2192718627
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2142179905
Short name T343
Test name
Test status
Simulation time 7002614262 ps
CPU time 31.07 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 211320 kb
Host smart-08d31c6b-b308-4c1c-95e2-a4bdb4e05fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142179905 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2142179905
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2192512927
Short name T149
Test name
Test status
Simulation time 3464323587 ps
CPU time 15.41 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 210896 kb
Host smart-877f483d-68be-4fa7-bd32-3a7ea94b9e20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192512927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2192512927
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.26984665
Short name T220
Test name
Test status
Simulation time 5995961125 ps
CPU time 19.26 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 213556 kb
Host smart-14a7c559-2168-4285-b651-e2e0d3ea1230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26984665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.26984665
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.729384465
Short name T242
Test name
Test status
Simulation time 6691301874 ps
CPU time 60.98 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:55:41 PM PST 23
Peak memory 215908 kb
Host smart-fd9a0425-4096-4429-a4f9-1f536fdde514
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729384465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.rom_ctrl_stress_all.729384465
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.590724983
Short name T299
Test name
Test status
Simulation time 39917113457 ps
CPU time 5762.76 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 02:31:22 PM PST 23
Peak memory 231080 kb
Host smart-c7467557-e54c-47cf-b5dc-8061df209030
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590724983 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.590724983
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1420363076
Short name T307
Test name
Test status
Simulation time 8223312798 ps
CPU time 12.53 seconds
Started Dec 31 12:54:26 PM PST 23
Finished Dec 31 12:54:40 PM PST 23
Peak memory 211008 kb
Host smart-c074fc82-4618-44e6-9c46-48aed30041d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420363076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1420363076
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2753003171
Short name T195
Test name
Test status
Simulation time 520614533351 ps
CPU time 322.49 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 01:00:17 PM PST 23
Peak memory 236300 kb
Host smart-d1a795c7-9a83-4cd1-b998-d1e86053350c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753003171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.2753003171
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.4092418056
Short name T191
Test name
Test status
Simulation time 22154575825 ps
CPU time 28.05 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 211832 kb
Host smart-c148cd8f-5382-414c-9f58-4572c75d216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092418056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.4092418056
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.702225194
Short name T210
Test name
Test status
Simulation time 8226327986 ps
CPU time 17.22 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 210948 kb
Host smart-c1323705-369c-471f-9d2b-ce65d66fca86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=702225194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.702225194
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2799290511
Short name T349
Test name
Test status
Simulation time 643309142 ps
CPU time 10.49 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 212984 kb
Host smart-4035257d-b647-4fc7-8214-7b10a82bd216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799290511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2799290511
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3344271554
Short name T376
Test name
Test status
Simulation time 6403974179 ps
CPU time 61.27 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:55:44 PM PST 23
Peak memory 212688 kb
Host smart-6da34211-3b46-493e-a79c-0fbcf3c15554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344271554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3344271554
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2061727368
Short name T102
Test name
Test status
Simulation time 50259373739 ps
CPU time 2141.43 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 01:30:51 PM PST 23
Peak memory 251356 kb
Host smart-5a9b14df-94d6-4a2e-b860-2b34378c3236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061727368 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2061727368
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2873513601
Short name T369
Test name
Test status
Simulation time 630039606 ps
CPU time 6.54 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 210964 kb
Host smart-fbeb0962-ef94-4eea-ac7c-b2e53b7600ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873513601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2873513601
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.411058679
Short name T237
Test name
Test status
Simulation time 205631296212 ps
CPU time 494.2 seconds
Started Dec 31 12:55:14 PM PST 23
Finished Dec 31 01:03:35 PM PST 23
Peak memory 236348 kb
Host smart-e5c1b489-a4bb-4fca-b3f6-0e0708112608
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411058679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.411058679
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.1415172792
Short name T382
Test name
Test status
Simulation time 16407775904 ps
CPU time 31.98 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 211872 kb
Host smart-7156e943-5d03-42fa-83ff-69a78e29aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415172792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.1415172792
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2873670179
Short name T230
Test name
Test status
Simulation time 2068976174 ps
CPU time 11.66 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:40 PM PST 23
Peak memory 210804 kb
Host smart-6d933d37-69d4-42a7-b979-5b4574591ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873670179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2873670179
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.914647047
Short name T254
Test name
Test status
Simulation time 11585829399 ps
CPU time 29.91 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 212956 kb
Host smart-99097f40-abd7-4bd6-a3f7-6791540dfc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914647047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.914647047
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.3393528284
Short name T253
Test name
Test status
Simulation time 589839316 ps
CPU time 17.9 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:51 PM PST 23
Peak memory 215316 kb
Host smart-d1037b6e-2e1e-4df4-8467-7022a7cfa2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393528284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.3393528284
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1145508374
Short name T258
Test name
Test status
Simulation time 520863659 ps
CPU time 4.58 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 210864 kb
Host smart-9b792bd1-3535-48a0-b7b5-d4ff51046808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145508374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1145508374
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3480603832
Short name T198
Test name
Test status
Simulation time 46491138185 ps
CPU time 463.03 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 01:02:38 PM PST 23
Peak memory 212232 kb
Host smart-108702af-697c-40ab-a5d3-1ab2fb1fdffc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480603832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3480603832
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3882462381
Short name T19
Test name
Test status
Simulation time 3015216684 ps
CPU time 14.63 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 210888 kb
Host smart-b8047e47-6ec0-4e69-a83c-228f8af1b6f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882462381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3882462381
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.768670990
Short name T234
Test name
Test status
Simulation time 11583497849 ps
CPU time 26.73 seconds
Started Dec 31 12:54:24 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 213480 kb
Host smart-73f03890-9317-4904-850c-b50f84bef285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768670990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.768670990
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1177250093
Short name T324
Test name
Test status
Simulation time 3534163464 ps
CPU time 32.22 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 215344 kb
Host smart-7b1cbe88-4ea4-4c38-9c5b-edfb67298583
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177250093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1177250093
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.1637582516
Short name T7
Test name
Test status
Simulation time 520079354 ps
CPU time 7.68 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 210920 kb
Host smart-be2bfc0b-a243-45e5-b66c-cb8eaa510c5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637582516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.1637582516
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.1729771528
Short name T335
Test name
Test status
Simulation time 281660457053 ps
CPU time 356.98 seconds
Started Dec 31 12:55:30 PM PST 23
Finished Dec 31 01:01:30 PM PST 23
Peak memory 224240 kb
Host smart-6a2e1752-065e-4980-9cf6-336b2e3d26ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729771528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.1729771528
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4026373786
Short name T178
Test name
Test status
Simulation time 16742938998 ps
CPU time 33.09 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 211272 kb
Host smart-4ed97ce1-1fcd-4589-8b80-c99b984ffb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026373786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4026373786
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2227956646
Short name T340
Test name
Test status
Simulation time 1189724614 ps
CPU time 7.63 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 210796 kb
Host smart-7dfe9202-d48c-4243-a1ce-ab5e4440cea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227956646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2227956646
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1991875151
Short name T236
Test name
Test status
Simulation time 2579962219 ps
CPU time 14.96 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 212500 kb
Host smart-7c020fd6-2e1e-4382-9093-51819ba5ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991875151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1991875151
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.3593703093
Short name T147
Test name
Test status
Simulation time 298294658 ps
CPU time 15.98 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 214300 kb
Host smart-3b928e69-753f-4edf-bfab-d98832b96fe4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593703093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.3593703093
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.469991054
Short name T315
Test name
Test status
Simulation time 26724796792 ps
CPU time 1029.56 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 01:12:08 PM PST 23
Peak memory 235592 kb
Host smart-d5c0047b-52c1-43ce-9699-0671b32deb3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469991054 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.469991054
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2374542415
Short name T311
Test name
Test status
Simulation time 1964606334 ps
CPU time 7.48 seconds
Started Dec 31 12:54:27 PM PST 23
Finished Dec 31 12:54:38 PM PST 23
Peak memory 210884 kb
Host smart-1e1e4997-dcc0-42d4-bc5f-0fea4d3c242d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374542415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2374542415
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.429064666
Short name T48
Test name
Test status
Simulation time 122745363333 ps
CPU time 269 seconds
Started Dec 31 12:54:22 PM PST 23
Finished Dec 31 12:58:53 PM PST 23
Peak memory 236544 kb
Host smart-cda74fe1-2c05-4252-a75f-3650de46242c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429064666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_c
orrupt_sig_fatal_chk.429064666
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.1281853242
Short name T217
Test name
Test status
Simulation time 7823734547 ps
CPU time 32.49 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 211576 kb
Host smart-f5a96859-f724-4125-9a61-8b58e739f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281853242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.1281853242
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2782849462
Short name T225
Test name
Test status
Simulation time 21369447584 ps
CPU time 13.26 seconds
Started Dec 31 12:54:21 PM PST 23
Finished Dec 31 12:54:36 PM PST 23
Peak memory 210880 kb
Host smart-b4f94cd5-d8b6-465b-9607-413aa98bf219
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2782849462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2782849462
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.910869030
Short name T158
Test name
Test status
Simulation time 18963912305 ps
CPU time 24.69 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 213320 kb
Host smart-d28f6911-b476-4548-b0a0-c912edf34ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910869030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.910869030
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1075987242
Short name T395
Test name
Test status
Simulation time 1449165295 ps
CPU time 7.61 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 210860 kb
Host smart-2221d706-86cf-42b8-b90e-4b4dfa354b69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075987242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1075987242
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3836468177
Short name T143
Test name
Test status
Simulation time 175060636 ps
CPU time 4.34 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 210952 kb
Host smart-5963ad2d-f9d1-4592-a685-dedd262b7dde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836468177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3836468177
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2650926813
Short name T398
Test name
Test status
Simulation time 48030491139 ps
CPU time 475.41 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 01:03:02 PM PST 23
Peak memory 212412 kb
Host smart-0f0cbe4c-6ecf-4b98-81ee-85184596d157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650926813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.2650926813
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2045776907
Short name T31
Test name
Test status
Simulation time 335457518 ps
CPU time 9.65 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 211288 kb
Host smart-8916dce7-fb1c-4df8-a05b-bc068179ad69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045776907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2045776907
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.2818063874
Short name T268
Test name
Test status
Simulation time 1342876147 ps
CPU time 8.02 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 210872 kb
Host smart-af35cddc-160a-4288-8583-ed425aceaa07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2818063874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.2818063874
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3317195473
Short name T228
Test name
Test status
Simulation time 3816112575 ps
CPU time 18.33 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 212644 kb
Host smart-477fc304-4f17-4085-a13e-b65be36ce654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317195473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3317195473
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2931560979
Short name T252
Test name
Test status
Simulation time 21477518418 ps
CPU time 58.88 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:55:41 PM PST 23
Peak memory 216476 kb
Host smart-af394bce-80f8-453c-a476-cf5434a682d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931560979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2931560979
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.949370091
Short name T404
Test name
Test status
Simulation time 12143142306 ps
CPU time 281.35 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:59:28 PM PST 23
Peak memory 221928 kb
Host smart-6e381fb2-e6bd-444d-a0de-6c4995ffb332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949370091 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.949370091
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2579026749
Short name T424
Test name
Test status
Simulation time 1014866678 ps
CPU time 7.8 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:50 PM PST 23
Peak memory 210872 kb
Host smart-b985c15d-3232-4364-a401-a7b6f43f6f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579026749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2579026749
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.1775371389
Short name T173
Test name
Test status
Simulation time 19771041557 ps
CPU time 209.33 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:58:27 PM PST 23
Peak memory 234392 kb
Host smart-d3560bb0-ea93-45b8-92c1-e1ad4d6a439e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775371389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.1775371389
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.4095762996
Short name T383
Test name
Test status
Simulation time 4936618764 ps
CPU time 17.22 seconds
Started Dec 31 12:54:38 PM PST 23
Finished Dec 31 12:54:57 PM PST 23
Peak memory 211380 kb
Host smart-a46d6800-4f13-4f5c-a77d-5d1715b053f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095762996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.4095762996
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2634480374
Short name T205
Test name
Test status
Simulation time 3889297300 ps
CPU time 12.55 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:57 PM PST 23
Peak memory 210912 kb
Host smart-4acaa52e-646d-4c0d-b891-a2b4555ec156
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634480374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2634480374
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.1421562620
Short name T289
Test name
Test status
Simulation time 719861010 ps
CPU time 10.31 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:54:42 PM PST 23
Peak memory 212832 kb
Host smart-4079d54d-912a-4e38-a01e-793361fb14e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421562620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.1421562620
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3634624545
Short name T247
Test name
Test status
Simulation time 691117721 ps
CPU time 38.32 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 215256 kb
Host smart-7276e5cd-eef4-4d40-94da-8e2441379d02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634624545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3634624545
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1460645389
Short name T370
Test name
Test status
Simulation time 416888656 ps
CPU time 4.44 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 210908 kb
Host smart-4039cfe9-5571-4080-8a36-d6714d0fdd91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460645389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1460645389
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3559945353
Short name T49
Test name
Test status
Simulation time 4609886593 ps
CPU time 144.46 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:57:08 PM PST 23
Peak memory 237504 kb
Host smart-93d3475f-8dd8-4fd5-8207-7284eb64bcb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559945353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3559945353
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3228556805
Short name T406
Test name
Test status
Simulation time 7880257830 ps
CPU time 32.12 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 211392 kb
Host smart-0c424ca4-08a5-4b66-bf7b-2cbf748d753b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228556805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3228556805
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.287003746
Short name T197
Test name
Test status
Simulation time 5453842094 ps
CPU time 13.8 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 210948 kb
Host smart-d951def3-108c-435d-84e8-8a1119b92cb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287003746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.287003746
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2961103642
Short name T396
Test name
Test status
Simulation time 776408539 ps
CPU time 10.23 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:50 PM PST 23
Peak memory 212468 kb
Host smart-b891c36a-16f6-441a-8608-f72d18e2736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961103642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2961103642
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3722588695
Short name T331
Test name
Test status
Simulation time 11971226878 ps
CPU time 40.59 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 216132 kb
Host smart-af06c077-3dd4-412b-9f50-4745495c1812
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722588695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3722588695
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.1280627254
Short name T302
Test name
Test status
Simulation time 158326567123 ps
CPU time 1591.1 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 01:21:38 PM PST 23
Peak memory 241644 kb
Host smart-5a3deca2-f51e-4c8a-a952-7cc69c62050a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280627254 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.1280627254
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.3748678013
Short name T417
Test name
Test status
Simulation time 2281178297 ps
CPU time 7.98 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 211044 kb
Host smart-a970bd26-152b-4ff4-bc2c-6a895594f0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748678013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.3748678013
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.185967427
Short name T308
Test name
Test status
Simulation time 2405722376 ps
CPU time 86.6 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:56:45 PM PST 23
Peak memory 232324 kb
Host smart-639b80e8-e1c6-4db2-af30-b10941ace206
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185967427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.185967427
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.3664181051
Short name T185
Test name
Test status
Simulation time 504224602 ps
CPU time 9.79 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 211064 kb
Host smart-4149c53f-4c1b-4b2c-8d46-6b059aedcdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664181051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.3664181051
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.2979188553
Short name T371
Test name
Test status
Simulation time 354737067 ps
CPU time 7.98 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 210836 kb
Host smart-4b6903c1-331e-44f3-8bd3-d3d1d1195233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979188553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.2979188553
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3176676422
Short name T206
Test name
Test status
Simulation time 720055775 ps
CPU time 10.12 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:55:01 PM PST 23
Peak memory 212520 kb
Host smart-d07a3534-4254-40e7-8fd5-ded01f221735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176676422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3176676422
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.89467779
Short name T408
Test name
Test status
Simulation time 8594866385 ps
CPU time 92.07 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:56:17 PM PST 23
Peak memory 215524 kb
Host smart-10f1e3a2-90bd-4341-8c68-9834cfbc7af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89467779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.89467779
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3406081978
Short name T279
Test name
Test status
Simulation time 141751176989 ps
CPU time 1327.53 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 01:17:01 PM PST 23
Peak memory 232028 kb
Host smart-4dcd0911-30e9-4991-ace1-7ae6412d51c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406081978 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3406081978
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.4170943712
Short name T265
Test name
Test status
Simulation time 1821565794 ps
CPU time 14.82 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210920 kb
Host smart-20582768-3f5c-40fc-8221-bfe8ba1f1e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170943712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.4170943712
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3778986713
Short name T193
Test name
Test status
Simulation time 17872749671 ps
CPU time 155.27 seconds
Started Dec 31 12:55:04 PM PST 23
Finished Dec 31 12:57:45 PM PST 23
Peak memory 212128 kb
Host smart-81504477-5e85-4ecd-a234-d93656ef9d45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778986713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.3778986713
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.4168131448
Short name T35
Test name
Test status
Simulation time 12073155785 ps
CPU time 25.19 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 211700 kb
Host smart-511bd1e2-28a4-4af1-a072-2b42ebc63bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168131448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.4168131448
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.1342067485
Short name T388
Test name
Test status
Simulation time 1613318651 ps
CPU time 10.72 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 210768 kb
Host smart-e7506b68-3224-40f5-bef8-2e9ee3cfd66a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342067485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.1342067485
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.1560810621
Short name T43
Test name
Test status
Simulation time 1919980694 ps
CPU time 114.93 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:56:47 PM PST 23
Peak memory 236312 kb
Host smart-93c05e0d-cc35-4289-ade0-6ff68e145238
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560810621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.1560810621
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.316880056
Short name T323
Test name
Test status
Simulation time 2378499347 ps
CPU time 13.5 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 212344 kb
Host smart-9f4371b0-6b34-4053-a00d-96fc2697f3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316880056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.316880056
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.1228427070
Short name T159
Test name
Test status
Simulation time 251940598 ps
CPU time 7.68 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210812 kb
Host smart-bb17b664-83c8-42f0-99c0-7d73819857cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228427070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.1228427070
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1348795265
Short name T375
Test name
Test status
Simulation time 32323144596 ps
CPU time 1254.5 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 01:15:48 PM PST 23
Peak memory 235560 kb
Host smart-83d9ed74-37fb-4d6d-ab98-d58baf2afccb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348795265 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1348795265
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1597899558
Short name T300
Test name
Test status
Simulation time 10909548938 ps
CPU time 10.66 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:54 PM PST 23
Peak memory 211012 kb
Host smart-5a4bb951-05b6-4e78-8143-b4f1b9083a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597899558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1597899558
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.34654827
Short name T325
Test name
Test status
Simulation time 15985594757 ps
CPU time 278.52 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:59:10 PM PST 23
Peak memory 237484 kb
Host smart-1f195ac3-61b1-49c1-b0e5-7889aa6c4ed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34654827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_co
rrupt_sig_fatal_chk.34654827
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.3239119757
Short name T288
Test name
Test status
Simulation time 754808104 ps
CPU time 9.71 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 210888 kb
Host smart-54fe7ba7-4e75-4aaf-bbf2-d8e00e034005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239119757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.3239119757
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.342320248
Short name T154
Test name
Test status
Simulation time 483087924 ps
CPU time 8.62 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:03 PM PST 23
Peak memory 210848 kb
Host smart-303f1b47-e926-4c14-b00e-87f0ec841ba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342320248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.342320248
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2689905545
Short name T153
Test name
Test status
Simulation time 3679475843 ps
CPU time 17.5 seconds
Started Dec 31 12:54:37 PM PST 23
Finished Dec 31 12:54:56 PM PST 23
Peak memory 212528 kb
Host smart-5ebe82fc-a617-4536-b27d-81c8b42c80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689905545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2689905545
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2390798842
Short name T416
Test name
Test status
Simulation time 1188451463 ps
CPU time 17.33 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:21 PM PST 23
Peak memory 211124 kb
Host smart-d84809ba-68e1-433c-a58d-c594db132898
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390798842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2390798842
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.4180076992
Short name T391
Test name
Test status
Simulation time 1649933125 ps
CPU time 13.72 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 210852 kb
Host smart-e16aaaee-08b7-4051-a9e0-f5b61a7a4b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180076992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.4180076992
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1351392736
Short name T411
Test name
Test status
Simulation time 30729857351 ps
CPU time 331.86 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 01:00:29 PM PST 23
Peak memory 237308 kb
Host smart-1c1f2fca-c583-402e-9d59-76d93bed4890
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351392736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.1351392736
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3936789371
Short name T171
Test name
Test status
Simulation time 42910109966 ps
CPU time 32.77 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 211004 kb
Host smart-eb7a9d60-0be3-4b1d-8c8d-8d85d2974202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936789371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3936789371
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3543798688
Short name T295
Test name
Test status
Simulation time 1738485042 ps
CPU time 14.66 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 210804 kb
Host smart-b7ef56bc-c1ab-4367-b83b-bbab3e3d97a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543798688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3543798688
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.797232333
Short name T380
Test name
Test status
Simulation time 4782755210 ps
CPU time 34.3 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 212676 kb
Host smart-47afb32c-9bb9-430a-bb4e-fa8df61aa7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797232333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.797232333
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2820000062
Short name T368
Test name
Test status
Simulation time 12628107956 ps
CPU time 110.68 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:56:44 PM PST 23
Peak memory 217660 kb
Host smart-d79bfa07-47c1-4069-aed2-dfd3f0ef0379
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820000062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2820000062
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3455372764
Short name T216
Test name
Test status
Simulation time 7377292060 ps
CPU time 15.42 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 210884 kb
Host smart-9d8a0d7e-65ad-439e-bdaa-b5466671d9a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455372764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3455372764
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.2927792103
Short name T1
Test name
Test status
Simulation time 295460495314 ps
CPU time 247.7 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:59:00 PM PST 23
Peak memory 234528 kb
Host smart-db1af32c-607e-4953-bb9d-540a69360364
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927792103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.2927792103
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2290787383
Short name T374
Test name
Test status
Simulation time 263559015 ps
CPU time 11.55 seconds
Started Dec 31 12:54:32 PM PST 23
Finished Dec 31 12:54:45 PM PST 23
Peak memory 211020 kb
Host smart-62008023-f4dc-4b43-8dc4-697cc3b8dcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290787383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2290787383
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3208877965
Short name T412
Test name
Test status
Simulation time 7761413392 ps
CPU time 14.55 seconds
Started Dec 31 12:55:13 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 210860 kb
Host smart-17de621e-b0af-4395-8bcb-83124905712d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3208877965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3208877965
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.791707015
Short name T413
Test name
Test status
Simulation time 3391341181 ps
CPU time 20.62 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:31 PM PST 23
Peak memory 212208 kb
Host smart-706db9cb-3f47-4d44-9153-b67ea9d26827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791707015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.791707015
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.2192501788
Short name T45
Test name
Test status
Simulation time 440526736 ps
CPU time 17.3 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 214076 kb
Host smart-facc038b-d64b-4a89-89c3-f36203705d58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192501788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.2192501788
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.3271431097
Short name T144
Test name
Test status
Simulation time 140724982717 ps
CPU time 8410.25 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 03:14:58 PM PST 23
Peak memory 240508 kb
Host smart-9006b2aa-f005-4e4b-a55c-3d597818676b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271431097 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.3271431097
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.4291640242
Short name T151
Test name
Test status
Simulation time 1732691423 ps
CPU time 14.38 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 210852 kb
Host smart-ee82e5f6-aee3-4453-b382-70aa3b3e2eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291640242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.4291640242
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1030838427
Short name T235
Test name
Test status
Simulation time 22413218120 ps
CPU time 355.4 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 01:00:46 PM PST 23
Peak memory 233752 kb
Host smart-83252ada-da9d-4875-bac1-39074a3e95ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030838427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1030838427
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2002928314
Short name T164
Test name
Test status
Simulation time 8009789178 ps
CPU time 33.1 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 211412 kb
Host smart-80f05855-9e5c-448c-a198-d4f141c874f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002928314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2002928314
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2716551354
Short name T182
Test name
Test status
Simulation time 1242406213 ps
CPU time 12.63 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 210868 kb
Host smart-7362628d-1993-433c-bdc0-fef37d9f9167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716551354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2716551354
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2664372897
Short name T267
Test name
Test status
Simulation time 9735891098 ps
CPU time 25.87 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 213616 kb
Host smart-a23eeee7-75d6-4a2a-992b-f0b46a88512a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664372897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2664372897
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3793846355
Short name T240
Test name
Test status
Simulation time 43254388614 ps
CPU time 104.61 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:56:53 PM PST 23
Peak memory 219044 kb
Host smart-b7fe0279-f75c-4d38-980b-23dd31221b74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793846355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3793846355
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1856895135
Short name T430
Test name
Test status
Simulation time 42439972450 ps
CPU time 1497.78 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 01:19:49 PM PST 23
Peak memory 235084 kb
Host smart-7afdcc74-fc76-47f5-96c3-bd4ac07d6e6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856895135 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1856895135
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3733598320
Short name T145
Test name
Test status
Simulation time 12028704179 ps
CPU time 16.39 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210924 kb
Host smart-550aa208-3045-4eff-a1d9-fb7f1e2c2af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733598320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3733598320
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2824486568
Short name T221
Test name
Test status
Simulation time 41260037988 ps
CPU time 206.55 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:58:29 PM PST 23
Peak memory 237352 kb
Host smart-80eebb56-4508-4786-bd16-5919440f48fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824486568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2824486568
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.91223936
Short name T355
Test name
Test status
Simulation time 2897955876 ps
CPU time 26.29 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 210960 kb
Host smart-8d6674aa-e00a-4391-add4-df1d378c147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91223936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.91223936
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1749774885
Short name T399
Test name
Test status
Simulation time 4298609599 ps
CPU time 16.02 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 210900 kb
Host smart-57a7e1e6-6f4e-4120-9d23-5fc9c2d2159d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749774885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1749774885
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.242794497
Short name T344
Test name
Test status
Simulation time 15849161419 ps
CPU time 31.07 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 213244 kb
Host smart-0b5e53c2-4fc3-4c08-bfd2-c0c4c8811719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242794497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.242794497
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.1431595551
Short name T320
Test name
Test status
Simulation time 999197425 ps
CPU time 7.26 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 210820 kb
Host smart-2f0830cf-23bb-40a0-9e4a-1dfd9659e280
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431595551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.1431595551
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.1065081414
Short name T165
Test name
Test status
Simulation time 1539211509 ps
CPU time 6.97 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:54:53 PM PST 23
Peak memory 210968 kb
Host smart-734a0c9f-2ae3-455f-8906-668b53fecc70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065081414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1065081414
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.873974275
Short name T407
Test name
Test status
Simulation time 13356094030 ps
CPU time 158.44 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:57:37 PM PST 23
Peak memory 227568 kb
Host smart-526c72cf-7eed-431b-88f3-b94fa31070db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873974275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c
orrupt_sig_fatal_chk.873974275
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3617408511
Short name T400
Test name
Test status
Simulation time 168697196 ps
CPU time 9.65 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:04 PM PST 23
Peak memory 211020 kb
Host smart-1960633a-f27f-408d-a7ab-a2bcd7c8fa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617408511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3617408511
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.2899170807
Short name T255
Test name
Test status
Simulation time 720133820 ps
CPU time 9.98 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 210800 kb
Host smart-99667f5f-877c-4db2-afd3-463f682b82dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899170807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.2899170807
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.4067992943
Short name T296
Test name
Test status
Simulation time 60905768161 ps
CPU time 35.88 seconds
Started Dec 31 12:54:44 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 212968 kb
Host smart-c836abd6-f6e5-4d0c-b324-013b0839dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067992943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.4067992943
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.63391649
Short name T291
Test name
Test status
Simulation time 43485180974 ps
CPU time 84.13 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:56:31 PM PST 23
Peak memory 218052 kb
Host smart-8cb2ca02-62cb-41ac-b992-af13a167c60f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63391649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 35.rom_ctrl_stress_all.63391649
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.902200100
Short name T372
Test name
Test status
Simulation time 578623895 ps
CPU time 6.5 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 210764 kb
Host smart-b2f51c5b-a9f3-4d85-9eab-dd78dceb5b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902200100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.902200100
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.763015855
Short name T356
Test name
Test status
Simulation time 1997696725 ps
CPU time 114.49 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:56:50 PM PST 23
Peak memory 227540 kb
Host smart-17dda365-9136-423e-9b08-7460f5f07577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763015855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.763015855
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.137571771
Short name T215
Test name
Test status
Simulation time 5724032953 ps
CPU time 26.19 seconds
Started Dec 31 12:55:22 PM PST 23
Finished Dec 31 12:55:54 PM PST 23
Peak memory 211380 kb
Host smart-d3a15460-4182-4f2e-ab42-5ebfb264a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137571771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.137571771
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.4189822592
Short name T274
Test name
Test status
Simulation time 663398044 ps
CPU time 9.19 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 210796 kb
Host smart-26490b13-367e-404d-9a06-c1ea2ec53533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189822592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.4189822592
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3080608822
Short name T341
Test name
Test status
Simulation time 4716362343 ps
CPU time 16.78 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 212152 kb
Host smart-bd6f98bd-3b22-43c2-b461-5c2489e91308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080608822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3080608822
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1033918596
Short name T346
Test name
Test status
Simulation time 1482755742 ps
CPU time 12.91 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 210928 kb
Host smart-3d514726-2408-4ca1-b44f-40f566afe842
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033918596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1033918596
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4230660692
Short name T233
Test name
Test status
Simulation time 43086907731 ps
CPU time 415.09 seconds
Started Dec 31 12:55:14 PM PST 23
Finished Dec 31 01:02:16 PM PST 23
Peak memory 227328 kb
Host smart-a20c6bbd-a9b9-4d7b-a4f8-c9581ccd0e7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230660692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4230660692
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3414851073
Short name T305
Test name
Test status
Simulation time 10655268302 ps
CPU time 23.94 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 211308 kb
Host smart-4b5ad784-f3f7-4de9-b3f4-960d8ce6bd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414851073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3414851073
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3231155274
Short name T385
Test name
Test status
Simulation time 386504349 ps
CPU time 5.41 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 210740 kb
Host smart-7874e5d9-69d9-4604-8a65-d85cf0e11f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231155274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3231155274
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.1809849569
Short name T393
Test name
Test status
Simulation time 374696100 ps
CPU time 12.32 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 211272 kb
Host smart-2fa1faef-e009-4707-ab77-df6b7adbbd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809849569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1809849569
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.2977163221
Short name T401
Test name
Test status
Simulation time 30885595148 ps
CPU time 40.98 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:58 PM PST 23
Peak memory 219116 kb
Host smart-f3455030-47ce-4d48-9193-268f835914a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977163221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.2977163221
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.409643530
Short name T316
Test name
Test status
Simulation time 227380610490 ps
CPU time 1908.53 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 01:26:33 PM PST 23
Peak memory 238624 kb
Host smart-7d526164-49a1-4467-9d33-b373f85f1c4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409643530 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.409643530
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4202421907
Short name T41
Test name
Test status
Simulation time 7340104474 ps
CPU time 15.16 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:12 PM PST 23
Peak memory 210912 kb
Host smart-3e266402-140e-4f39-a374-f27c032048fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202421907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4202421907
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.775870145
Short name T53
Test name
Test status
Simulation time 4518669998 ps
CPU time 100.51 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:56:52 PM PST 23
Peak memory 237424 kb
Host smart-16d98cd1-e281-4b19-b9fe-dd5424965575
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775870145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c
orrupt_sig_fatal_chk.775870145
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1736925176
Short name T196
Test name
Test status
Simulation time 692713191 ps
CPU time 9.59 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 210848 kb
Host smart-62e2c398-1972-4790-9f11-a4b6e7db8311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736925176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1736925176
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2929141590
Short name T167
Test name
Test status
Simulation time 1240764073 ps
CPU time 7.66 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 210812 kb
Host smart-8d7ab416-7c9f-43fa-82a1-c3189a50e329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2929141590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2929141590
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3323586684
Short name T157
Test name
Test status
Simulation time 14072779345 ps
CPU time 34.08 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:29 PM PST 23
Peak memory 213012 kb
Host smart-ba9defea-f6b2-4cf2-8e08-dc311049d680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323586684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3323586684
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.2133314496
Short name T362
Test name
Test status
Simulation time 13055167207 ps
CPU time 41.82 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 216116 kb
Host smart-a460285c-d032-47cb-9506-05229f8271d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133314496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.2133314496
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3732833259
Short name T257
Test name
Test status
Simulation time 43634943315 ps
CPU time 862.95 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 01:09:26 PM PST 23
Peak memory 229776 kb
Host smart-f68ffd34-e96a-4115-9452-0a51a3efeee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732833259 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3732833259
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2448972255
Short name T177
Test name
Test status
Simulation time 1897900462 ps
CPU time 15.19 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 210924 kb
Host smart-e5cf2e02-e5a2-4335-bdbe-b5a699c4bd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448972255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2448972255
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3539613491
Short name T336
Test name
Test status
Simulation time 27441568614 ps
CPU time 254.69 seconds
Started Dec 31 12:55:25 PM PST 23
Finished Dec 31 12:59:44 PM PST 23
Peak memory 237232 kb
Host smart-1f19040f-710d-4164-b9d8-0f6cba411c69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539613491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3539613491
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3712064152
Short name T394
Test name
Test status
Simulation time 1186188235 ps
CPU time 9.9 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 211040 kb
Host smart-23b9eee8-0966-441f-b609-2991354ad5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712064152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3712064152
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1924080271
Short name T232
Test name
Test status
Simulation time 472761836 ps
CPU time 6.85 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:10 PM PST 23
Peak memory 210768 kb
Host smart-da64811e-117f-48ea-a123-9eec195d711a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924080271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1924080271
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1437028592
Short name T414
Test name
Test status
Simulation time 10143259578 ps
CPU time 29.95 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:40 PM PST 23
Peak memory 212980 kb
Host smart-d8fc6823-bbce-4335-8367-09c3ec92cd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437028592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1437028592
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2530744335
Short name T152
Test name
Test status
Simulation time 7872109289 ps
CPU time 76.26 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:56:09 PM PST 23
Peak memory 216300 kb
Host smart-0889ccb2-61b5-4c5a-bd3e-041777007b95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530744335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2530744335
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3900234611
Short name T15
Test name
Test status
Simulation time 11358268419 ps
CPU time 1435.03 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 01:19:05 PM PST 23
Peak memory 223448 kb
Host smart-e5930d04-2e1e-41a2-a66c-eae5d0a8c147
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900234611 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3900234611
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.7058613
Short name T363
Test name
Test status
Simulation time 920549460 ps
CPU time 4.41 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210928 kb
Host smart-17c6b458-cf7f-4d49-900a-db4ee2ff3169
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7058613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.7058613
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.154751580
Short name T367
Test name
Test status
Simulation time 22000862051 ps
CPU time 241.06 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:58:46 PM PST 23
Peak memory 233192 kb
Host smart-accb6dcf-1d9e-4fa4-be49-6687b9436d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154751580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.154751580
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2953900819
Short name T224
Test name
Test status
Simulation time 11989026803 ps
CPU time 18.92 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 211280 kb
Host smart-a7b6e214-e0bb-4d21-b633-e127cc05b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953900819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2953900819
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2660561754
Short name T287
Test name
Test status
Simulation time 300568269 ps
CPU time 6.38 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 210872 kb
Host smart-ed9db312-4a8e-4027-9258-3797dc906c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2660561754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2660561754
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2485792809
Short name T37
Test name
Test status
Simulation time 2057925530 ps
CPU time 62.95 seconds
Started Dec 31 12:54:22 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 235852 kb
Host smart-01caa56f-b7b5-40fb-9a42-e3b843049623
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485792809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2485792809
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.334460758
Short name T181
Test name
Test status
Simulation time 8568654937 ps
CPU time 27.8 seconds
Started Dec 31 12:54:23 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 212800 kb
Host smart-25d56486-0529-4454-947b-2bbcab3e93e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334460758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.334460758
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3197009085
Short name T238
Test name
Test status
Simulation time 6587349900 ps
CPU time 35.17 seconds
Started Dec 31 12:54:20 PM PST 23
Finished Dec 31 12:54:57 PM PST 23
Peak memory 213516 kb
Host smart-4d5c52e3-19ec-4458-8d20-f302dfd3c4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197009085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3197009085
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2517026614
Short name T428
Test name
Test status
Simulation time 13282130503 ps
CPU time 814.58 seconds
Started Dec 31 12:54:33 PM PST 23
Finished Dec 31 01:08:08 PM PST 23
Peak memory 227320 kb
Host smart-f45da6a1-b048-40b3-8b0d-7e7cb0fa7f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517026614 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2517026614
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.1688267226
Short name T188
Test name
Test status
Simulation time 617609438 ps
CPU time 8.38 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 210836 kb
Host smart-7f46cbe6-d27e-4897-b12d-bcca34781bf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688267226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.1688267226
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2605913067
Short name T415
Test name
Test status
Simulation time 69086552339 ps
CPU time 267.79 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:59:20 PM PST 23
Peak memory 237368 kb
Host smart-fb602d71-9bd8-40ed-bf1b-14d96e0a4c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605913067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2605913067
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3616825773
Short name T312
Test name
Test status
Simulation time 13561569378 ps
CPU time 32.04 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 211260 kb
Host smart-c7524091-7057-4cbd-b436-6dd1bb4e54e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616825773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3616825773
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.247202358
Short name T361
Test name
Test status
Simulation time 275698183 ps
CPU time 6.75 seconds
Started Dec 31 12:54:51 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 210876 kb
Host smart-535d35ef-7767-47da-b2a1-59a9eebcebad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247202358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.247202358
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1974825218
Short name T273
Test name
Test status
Simulation time 2401151219 ps
CPU time 23.75 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 212012 kb
Host smart-16bf5dff-c923-4ddb-9713-7d6d1ddb407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974825218 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1974825218
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.3188266151
Short name T272
Test name
Test status
Simulation time 4059930690 ps
CPU time 38.32 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 212176 kb
Host smart-05d87eb6-5fe0-4c34-8a21-c90b90a8a8f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188266151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.3188266151
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3479179365
Short name T426
Test name
Test status
Simulation time 86986781779 ps
CPU time 3027.63 seconds
Started Dec 31 12:55:15 PM PST 23
Finished Dec 31 01:45:50 PM PST 23
Peak memory 235560 kb
Host smart-c9b3db64-d0f5-48c8-949a-b5aedaa3a7f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479179365 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3479179365
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.2562527547
Short name T146
Test name
Test status
Simulation time 2067728242 ps
CPU time 16.39 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 12:55:14 PM PST 23
Peak memory 210928 kb
Host smart-b324a83b-a8be-4547-8c81-4696d7745f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562527547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.2562527547
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.971569281
Short name T276
Test name
Test status
Simulation time 64445181918 ps
CPU time 168.59 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:57:39 PM PST 23
Peak memory 236372 kb
Host smart-cc71d192-9184-4065-bfc8-e29584ed25c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971569281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.971569281
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.958888712
Short name T156
Test name
Test status
Simulation time 12725251516 ps
CPU time 30.23 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 211176 kb
Host smart-4a69e6cd-7ad0-4fa2-80d8-7883b57978c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958888712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.958888712
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2481828278
Short name T286
Test name
Test status
Simulation time 94986104 ps
CPU time 5.51 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 210740 kb
Host smart-9d33be03-8c44-487c-96da-e8d64af21525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481828278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2481828278
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3180447194
Short name T392
Test name
Test status
Simulation time 4314321283 ps
CPU time 25.95 seconds
Started Dec 31 12:55:17 PM PST 23
Finished Dec 31 12:55:49 PM PST 23
Peak memory 212044 kb
Host smart-74c48f97-9764-48fb-8c68-e60a5ef07625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180447194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3180447194
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1793689656
Short name T213
Test name
Test status
Simulation time 599816165 ps
CPU time 17.83 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 212704 kb
Host smart-ccec784f-918f-45a7-b2ef-939ce3f15f71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793689656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1793689656
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2067276410
Short name T423
Test name
Test status
Simulation time 125370145040 ps
CPU time 595.62 seconds
Started Dec 31 12:55:28 PM PST 23
Finished Dec 31 01:05:27 PM PST 23
Peak memory 228928 kb
Host smart-fa0f8a61-cebe-4beb-92f5-4e2f47331c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067276410 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2067276410
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3408818622
Short name T176
Test name
Test status
Simulation time 1626841623 ps
CPU time 13.82 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 210936 kb
Host smart-11a8c2da-d2ea-45c6-a234-bed0e509aced
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408818622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3408818622
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3702900996
Short name T418
Test name
Test status
Simulation time 18209145204 ps
CPU time 241.91 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:59:12 PM PST 23
Peak memory 228208 kb
Host smart-b13db1b6-3aeb-4639-805d-79faa7420af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702900996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3702900996
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.943176983
Short name T34
Test name
Test status
Simulation time 11227576659 ps
CPU time 20.47 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 210860 kb
Host smart-d2cb3f0b-83b9-4e67-a794-c55e53fbd366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943176983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.943176983
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.261140098
Short name T243
Test name
Test status
Simulation time 3103732520 ps
CPU time 14.44 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:11 PM PST 23
Peak memory 210936 kb
Host smart-2121b1b1-0c79-4f5d-9075-44c66cf2e866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261140098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.261140098
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2868856739
Short name T81
Test name
Test status
Simulation time 715889682 ps
CPU time 10.58 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:55:08 PM PST 23
Peak memory 212544 kb
Host smart-1fe5e388-d2d1-4ef0-ad9b-c82a9cfce662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868856739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2868856739
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.1032056233
Short name T227
Test name
Test status
Simulation time 1194052124 ps
CPU time 14.28 seconds
Started Dec 31 12:54:48 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 211076 kb
Host smart-d43d5cb3-829e-4bbf-b62d-44ada745b5d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032056233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.1032056233
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3925544862
Short name T378
Test name
Test status
Simulation time 95077101319 ps
CPU time 1435.67 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 01:19:00 PM PST 23
Peak memory 235532 kb
Host smart-4b682c46-acde-4597-b420-1430802af6f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925544862 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3925544862
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.10467107
Short name T155
Test name
Test status
Simulation time 1029504474 ps
CPU time 6.41 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 210928 kb
Host smart-1dd772c8-f6b5-47e8-89d4-581d569839aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10467107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.10467107
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3395586748
Short name T402
Test name
Test status
Simulation time 29111223831 ps
CPU time 306.62 seconds
Started Dec 31 12:54:40 PM PST 23
Finished Dec 31 12:59:49 PM PST 23
Peak memory 234268 kb
Host smart-524a38b1-fc5e-40ec-bce8-20e30d3c3208
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395586748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3395586748
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.1268599979
Short name T354
Test name
Test status
Simulation time 1969974745 ps
CPU time 22.42 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:28 PM PST 23
Peak memory 210944 kb
Host smart-cb2c1b36-ed0c-4639-a9bd-56cca1151f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268599979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.1268599979
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.869720832
Short name T342
Test name
Test status
Simulation time 349415823 ps
CPU time 6.28 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 210824 kb
Host smart-5872f3a7-f24c-4b4a-8784-c8f1b355b436
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869720832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.869720832
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1632331396
Short name T285
Test name
Test status
Simulation time 3133824173 ps
CPU time 37.55 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:42 PM PST 23
Peak memory 212368 kb
Host smart-84923e1d-d0f2-40b3-a491-4c9717f79c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632331396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1632331396
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2549962087
Short name T203
Test name
Test status
Simulation time 1508716467 ps
CPU time 21.97 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 213508 kb
Host smart-968e3844-e307-494b-8d48-91563c3784fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549962087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2549962087
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.1647803135
Short name T260
Test name
Test status
Simulation time 39528382810 ps
CPU time 1372.72 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 01:17:53 PM PST 23
Peak memory 225860 kb
Host smart-90d47473-080f-49b2-b951-936ec6562994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647803135 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.1647803135
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.4183916082
Short name T366
Test name
Test status
Simulation time 2500251395 ps
CPU time 13.67 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:32 PM PST 23
Peak memory 210900 kb
Host smart-c4ca81eb-093f-4d80-9f1b-31332d12236b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183916082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.4183916082
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1984550352
Short name T214
Test name
Test status
Simulation time 29713881811 ps
CPU time 183.83 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:58:17 PM PST 23
Peak memory 236652 kb
Host smart-f27af17e-0176-421b-8edc-443b2c7528f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984550352 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.1984550352
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3021833893
Short name T421
Test name
Test status
Simulation time 3067105254 ps
CPU time 27.1 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 211080 kb
Host smart-33fd9806-14ec-483b-a7f6-bfef9a195934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021833893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3021833893
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.980091090
Short name T347
Test name
Test status
Simulation time 98525044 ps
CPU time 5.74 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210832 kb
Host smart-216c754e-877e-426e-ad10-ed6e537a9a16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980091090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.980091090
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.3816810463
Short name T192
Test name
Test status
Simulation time 2068750712 ps
CPU time 22.94 seconds
Started Dec 31 12:55:11 PM PST 23
Finished Dec 31 12:55:40 PM PST 23
Peak memory 212020 kb
Host smart-5dc47974-724c-4d8b-9b31-5d9c9d4b88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816810463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.3816810463
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1415401883
Short name T266
Test name
Test status
Simulation time 751571035 ps
CPU time 24.53 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 215680 kb
Host smart-cb641307-41ce-47e6-af95-cab51cc95058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415401883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1415401883
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.359018073
Short name T186
Test name
Test status
Simulation time 1191238056 ps
CPU time 8.13 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210916 kb
Host smart-66532aa3-ff11-4086-868c-67c10040b8be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359018073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.359018073
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.3002684773
Short name T209
Test name
Test status
Simulation time 120937721526 ps
CPU time 338.84 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 01:00:50 PM PST 23
Peak memory 237208 kb
Host smart-9cfe1696-e9c4-408b-8fbd-e4746b4fb552
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002684773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.3002684773
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.382917534
Short name T379
Test name
Test status
Simulation time 19402060897 ps
CPU time 22.74 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 211420 kb
Host smart-f4659fe9-3ed0-46ba-8096-8134fe5fef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382917534 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.382917534
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4234623338
Short name T259
Test name
Test status
Simulation time 16599974692 ps
CPU time 14.87 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 210836 kb
Host smart-e541819c-52c6-4b0b-a945-a81cb91be0ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4234623338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4234623338
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1019808405
Short name T271
Test name
Test status
Simulation time 6229257728 ps
CPU time 31.75 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:33 PM PST 23
Peak memory 213184 kb
Host smart-0ba68bfb-9c67-464f-801c-ce7590ddcf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019808405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1019808405
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.723137025
Short name T422
Test name
Test status
Simulation time 18604206988 ps
CPU time 86.47 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:56:20 PM PST 23
Peak memory 219092 kb
Host smart-495d10fb-32fa-454e-a5cc-1c0634bdc8c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723137025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.723137025
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.465474275
Short name T326
Test name
Test status
Simulation time 12734930215 ps
CPU time 856.16 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 01:09:20 PM PST 23
Peak memory 221512 kb
Host smart-f8bcd714-1808-4cdb-9081-38904f9d3ab7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465474275 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.465474275
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2491711936
Short name T201
Test name
Test status
Simulation time 1338161692 ps
CPU time 7.6 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:54:59 PM PST 23
Peak memory 210984 kb
Host smart-dabfc636-5312-42c2-b6a1-8b123b22e8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491711936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2491711936
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3384874281
Short name T208
Test name
Test status
Simulation time 6133624677 ps
CPU time 126.18 seconds
Started Dec 31 12:54:34 PM PST 23
Finished Dec 31 12:56:42 PM PST 23
Peak memory 234372 kb
Host smart-4e908c12-aaa4-40f7-96dd-a604c60044c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384874281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3384874281
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1683460430
Short name T333
Test name
Test status
Simulation time 176896296 ps
CPU time 9.88 seconds
Started Dec 31 12:54:46 PM PST 23
Finished Dec 31 12:55:00 PM PST 23
Peak memory 210880 kb
Host smart-b79adf07-9204-4d98-9012-6dc620445bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683460430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1683460430
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2894995559
Short name T207
Test name
Test status
Simulation time 4138065781 ps
CPU time 11.83 seconds
Started Dec 31 12:55:19 PM PST 23
Finished Dec 31 12:55:35 PM PST 23
Peak memory 210864 kb
Host smart-b1ca78a4-0b2f-4b9f-ab11-3a61559428e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894995559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2894995559
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.686697678
Short name T329
Test name
Test status
Simulation time 389228356 ps
CPU time 10.33 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 212124 kb
Host smart-7f6e11a9-1ccf-4a86-92ce-a226bc77f220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686697678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.686697678
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.4149217839
Short name T239
Test name
Test status
Simulation time 1633414510 ps
CPU time 19.43 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:13 PM PST 23
Peak memory 210772 kb
Host smart-60e79e03-5312-40db-9ab1-207105091296
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149217839 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.4149217839
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.2214758365
Short name T322
Test name
Test status
Simulation time 168326696 ps
CPU time 4.37 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:55:26 PM PST 23
Peak memory 210884 kb
Host smart-8ae96cd8-f861-423c-a409-59fd20f3b18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214758365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.2214758365
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.737140342
Short name T358
Test name
Test status
Simulation time 59446471050 ps
CPU time 558.69 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 01:04:20 PM PST 23
Peak memory 237440 kb
Host smart-52a698b5-19de-4bb5-853a-faf2710cd08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737140342 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.737140342
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3290979275
Short name T351
Test name
Test status
Simulation time 4158119047 ps
CPU time 33.37 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:39 PM PST 23
Peak memory 211072 kb
Host smart-234e5215-08cf-4bc8-a780-b85841edd8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290979275 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3290979275
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3819167929
Short name T270
Test name
Test status
Simulation time 1699368307 ps
CPU time 9 seconds
Started Dec 31 12:55:00 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 210828 kb
Host smart-66b968d5-56e2-4e6e-a8e6-d894848e87b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819167929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3819167929
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2764108129
Short name T163
Test name
Test status
Simulation time 31679514231 ps
CPU time 20.77 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 212920 kb
Host smart-b3bc8d7b-f2e0-4cc9-b76e-f2ba33c3a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764108129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2764108129
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.2026445404
Short name T200
Test name
Test status
Simulation time 3263921772 ps
CPU time 30.07 seconds
Started Dec 31 12:55:10 PM PST 23
Finished Dec 31 12:55:46 PM PST 23
Peak memory 212804 kb
Host smart-3d4c9f84-5dde-4f7c-b088-ebdd15553f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026445404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.2026445404
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1263072016
Short name T327
Test name
Test status
Simulation time 76114946466 ps
CPU time 8336.13 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 03:14:10 PM PST 23
Peak memory 235432 kb
Host smart-1c94cdbc-1f69-4606-b4cb-af6870ff41b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263072016 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1263072016
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3159747499
Short name T319
Test name
Test status
Simulation time 1499093910 ps
CPU time 13.16 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:24 PM PST 23
Peak memory 210944 kb
Host smart-e5a93c92-d040-4069-b0a2-aa4332201863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159747499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3159747499
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.3640018535
Short name T241
Test name
Test status
Simulation time 122558012867 ps
CPU time 280.64 seconds
Started Dec 31 12:55:08 PM PST 23
Finished Dec 31 12:59:54 PM PST 23
Peak memory 233788 kb
Host smart-a2c4a09a-2eea-4245-ad4e-bb473f4c5732
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640018535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.3640018535
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1159826158
Short name T222
Test name
Test status
Simulation time 3372585882 ps
CPU time 30.26 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 211068 kb
Host smart-1e94891a-fb14-49cb-8aee-1fffbaa8ac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159826158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1159826158
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1500747655
Short name T386
Test name
Test status
Simulation time 1222709028 ps
CPU time 12.82 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:19 PM PST 23
Peak memory 210840 kb
Host smart-1a53c917-7a17-4f57-ba08-dab8e848c540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500747655 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1500747655
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.1937642035
Short name T194
Test name
Test status
Simulation time 2068316646 ps
CPU time 17.16 seconds
Started Dec 31 12:55:03 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 212364 kb
Host smart-892810ea-210b-4da8-b055-fec531a0180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937642035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.1937642035
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2851414815
Short name T141
Test name
Test status
Simulation time 14452914725 ps
CPU time 37.47 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:34 PM PST 23
Peak memory 213436 kb
Host smart-fa001178-8e3f-4ae6-86b8-0e813e993982
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851414815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2851414815
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.56758804
Short name T284
Test name
Test status
Simulation time 499799764 ps
CPU time 5.19 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:55:02 PM PST 23
Peak memory 210848 kb
Host smart-b44bb880-cbc4-4043-bb8c-e3b238c267cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56758804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.56758804
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.1494084532
Short name T6
Test name
Test status
Simulation time 106534566882 ps
CPU time 256.15 seconds
Started Dec 31 12:55:16 PM PST 23
Finished Dec 31 12:59:38 PM PST 23
Peak memory 224220 kb
Host smart-9664d7c4-ce66-4793-921e-f0e8f8aca23b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494084532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.1494084532
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2999437718
Short name T409
Test name
Test status
Simulation time 28184627005 ps
CPU time 21.76 seconds
Started Dec 31 12:55:02 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 212120 kb
Host smart-09a0a57e-971c-4ecd-8d70-77578a08c15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999437718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2999437718
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.836101754
Short name T294
Test name
Test status
Simulation time 1713771607 ps
CPU time 15.37 seconds
Started Dec 31 12:54:59 PM PST 23
Finished Dec 31 12:55:20 PM PST 23
Peak memory 210868 kb
Host smart-ac55d24d-cf71-42b0-aebd-b67a35d03353
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836101754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.836101754
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.411186322
Short name T20
Test name
Test status
Simulation time 15661404521 ps
CPU time 27.76 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 12:55:25 PM PST 23
Peak memory 213020 kb
Host smart-690d7202-a748-445f-931c-c145386971d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411186322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.411186322
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.4194292669
Short name T251
Test name
Test status
Simulation time 5971970521 ps
CPU time 33.85 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 216632 kb
Host smart-272449fd-94e6-4297-b525-9a690fbf58b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194292669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.4194292669
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2916831370
Short name T139
Test name
Test status
Simulation time 6505474682 ps
CPU time 10.79 seconds
Started Dec 31 12:54:36 PM PST 23
Finished Dec 31 12:54:48 PM PST 23
Peak memory 210992 kb
Host smart-c1eef3c9-206d-4a2b-92b0-b691a6186c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916831370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2916831370
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3165018160
Short name T183
Test name
Test status
Simulation time 78772162986 ps
CPU time 314.39 seconds
Started Dec 31 12:54:55 PM PST 23
Finished Dec 31 01:00:14 PM PST 23
Peak memory 228108 kb
Host smart-0668a421-0f4b-4750-84c0-493521c3e834
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165018160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3165018160
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2305334906
Short name T334
Test name
Test status
Simulation time 4173526970 ps
CPU time 22.87 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:17 PM PST 23
Peak memory 211036 kb
Host smart-fbb41a9e-2557-43ce-b2d9-2438d37c65a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305334906 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2305334906
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.4079151832
Short name T100
Test name
Test status
Simulation time 6201718848 ps
CPU time 13.2 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 210900 kb
Host smart-35008c18-526c-4f51-af5b-a2d57a5dbf3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4079151832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.4079151832
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.1016838625
Short name T170
Test name
Test status
Simulation time 3279117239 ps
CPU time 29.19 seconds
Started Dec 31 12:54:35 PM PST 23
Finished Dec 31 12:55:05 PM PST 23
Peak memory 212528 kb
Host smart-96262742-6343-45a0-8511-8e42fbf7dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016838625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.1016838625
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2486127931
Short name T304
Test name
Test status
Simulation time 7232437222 ps
CPU time 38.07 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:50 PM PST 23
Peak memory 213760 kb
Host smart-35609ae5-b1fc-432a-99d8-4269d9d68d5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486127931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2486127931
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2301741515
Short name T263
Test name
Test status
Simulation time 48836228118 ps
CPU time 854.43 seconds
Started Dec 31 12:54:58 PM PST 23
Finished Dec 31 01:09:18 PM PST 23
Peak memory 227356 kb
Host smart-7a7150fc-a545-4bde-a748-ab3c3a85c287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301741515 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.2301741515
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1183369549
Short name T187
Test name
Test status
Simulation time 5572654571 ps
CPU time 11.92 seconds
Started Dec 31 12:54:50 PM PST 23
Finished Dec 31 12:55:06 PM PST 23
Peak memory 211008 kb
Host smart-7e5b8791-aa02-4251-a73d-245af6f020b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183369549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1183369549
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.4120354217
Short name T32
Test name
Test status
Simulation time 11356860533 ps
CPU time 132.97 seconds
Started Dec 31 12:54:31 PM PST 23
Finished Dec 31 12:56:45 PM PST 23
Peak memory 228136 kb
Host smart-fbd1ed60-ef58-4764-9229-c60f055c67e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120354217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.4120354217
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2845874099
Short name T350
Test name
Test status
Simulation time 3830723757 ps
CPU time 31.14 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:55:16 PM PST 23
Peak memory 211040 kb
Host smart-4bf669b7-07a1-42ba-b55a-e008f85847a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845874099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2845874099
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.1805071024
Short name T306
Test name
Test status
Simulation time 277744633 ps
CPU time 7.65 seconds
Started Dec 31 12:54:43 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 210804 kb
Host smart-a24e2703-39c9-481e-9059-9740895d805c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1805071024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.1805071024
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.679537924
Short name T280
Test name
Test status
Simulation time 1788788562 ps
CPU time 20.92 seconds
Started Dec 31 12:54:52 PM PST 23
Finished Dec 31 12:55:18 PM PST 23
Peak memory 212092 kb
Host smart-1979156e-4217-4763-ac4f-946634329d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679537924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.679537924
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.342899513
Short name T397
Test name
Test status
Simulation time 4198111867 ps
CPU time 27.6 seconds
Started Dec 31 12:55:12 PM PST 23
Finished Dec 31 12:55:46 PM PST 23
Peak memory 213176 kb
Host smart-ef33bd86-ab6d-4467-9fb4-1e6019077ad3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342899513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.342899513
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2138040002
Short name T297
Test name
Test status
Simulation time 3585113265 ps
CPU time 14.99 seconds
Started Dec 31 12:55:01 PM PST 23
Finished Dec 31 12:55:22 PM PST 23
Peak memory 210936 kb
Host smart-d56c482f-1289-45dc-8d45-61c857328dcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138040002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2138040002
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.856073885
Short name T223
Test name
Test status
Simulation time 112190890562 ps
CPU time 295.17 seconds
Started Dec 31 12:54:57 PM PST 23
Finished Dec 31 12:59:57 PM PST 23
Peak memory 237404 kb
Host smart-99548f42-0970-4991-9a0a-87e65273d810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856073885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.856073885
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2795760993
Short name T264
Test name
Test status
Simulation time 8002391642 ps
CPU time 33.13 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 12:55:44 PM PST 23
Peak memory 211548 kb
Host smart-9db93cda-445a-4988-8df1-5adc10a09420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795760993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2795760993
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3738034697
Short name T389
Test name
Test status
Simulation time 6941728148 ps
CPU time 15.56 seconds
Started Dec 31 12:54:47 PM PST 23
Finished Dec 31 12:55:07 PM PST 23
Peak memory 210828 kb
Host smart-ba5631be-1c3a-447f-9884-5b9eb92385c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738034697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3738034697
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2282663993
Short name T82
Test name
Test status
Simulation time 1683534050 ps
CPU time 22.24 seconds
Started Dec 31 12:54:49 PM PST 23
Finished Dec 31 12:55:15 PM PST 23
Peak memory 212008 kb
Host smart-a5d2050b-203f-44fc-8771-0904a22542f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282663993 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2282663993
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.339621009
Short name T245
Test name
Test status
Simulation time 1547209744 ps
CPU time 22.16 seconds
Started Dec 31 12:55:09 PM PST 23
Finished Dec 31 12:55:37 PM PST 23
Peak memory 215668 kb
Host smart-550439af-f19c-4cb9-961f-fb962e28b4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339621009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.339621009
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4283228583
Short name T161
Test name
Test status
Simulation time 150602968795 ps
CPU time 2597.52 seconds
Started Dec 31 12:54:53 PM PST 23
Finished Dec 31 01:38:15 PM PST 23
Peak memory 242796 kb
Host smart-26c58dfd-57e0-4823-a050-a77d716e0271
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283228583 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4283228583
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.772615572
Short name T427
Test name
Test status
Simulation time 5492284866 ps
CPU time 11.2 seconds
Started Dec 31 12:55:07 PM PST 23
Finished Dec 31 12:55:23 PM PST 23
Peak memory 210932 kb
Host smart-f1a7e429-32f8-4732-b3dd-4a0a228c427a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772615572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.772615572
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1543661948
Short name T403
Test name
Test status
Simulation time 6454155188 ps
CPU time 29.41 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:30 PM PST 23
Peak memory 211612 kb
Host smart-baff92b2-5d1c-427d-bdf1-4343416d657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543661948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1543661948
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3410565953
Short name T179
Test name
Test status
Simulation time 1163719566 ps
CPU time 12.14 seconds
Started Dec 31 12:54:41 PM PST 23
Finished Dec 31 12:54:55 PM PST 23
Peak memory 210812 kb
Host smart-945de177-b613-4442-9298-74cae74b33d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410565953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3410565953
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3056819868
Short name T278
Test name
Test status
Simulation time 16371899282 ps
CPU time 39.21 seconds
Started Dec 31 12:54:45 PM PST 23
Finished Dec 31 12:55:27 PM PST 23
Peak memory 212824 kb
Host smart-91139122-c92f-4b83-9d95-57a6aab1d7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056819868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3056819868
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1278511796
Short name T314
Test name
Test status
Simulation time 11228402821 ps
CPU time 26.83 seconds
Started Dec 31 12:55:06 PM PST 23
Finished Dec 31 12:55:38 PM PST 23
Peak memory 213652 kb
Host smart-146f5daf-81dc-4b7b-876b-0054512a4741
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278511796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1278511796
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1022113695
Short name T14
Test name
Test status
Simulation time 103772878564 ps
CPU time 970.06 seconds
Started Dec 31 12:55:05 PM PST 23
Finished Dec 31 01:11:20 PM PST 23
Peak memory 235536 kb
Host smart-ef039417-d8ef-4ba0-9db0-3d67b51c75cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022113695 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1022113695
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.29416708
Short name T321
Test name
Test status
Simulation time 1342910240 ps
CPU time 8.85 seconds
Started Dec 31 12:54:42 PM PST 23
Finished Dec 31 12:54:52 PM PST 23
Peak memory 210936 kb
Host smart-65884b08-8b50-4701-859f-f347090a4e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29416708 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.29416708
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1791541277
Short name T244
Test name
Test status
Simulation time 119738600907 ps
CPU time 353.46 seconds
Started Dec 31 12:54:39 PM PST 23
Finished Dec 31 01:00:45 PM PST 23
Peak memory 236128 kb
Host smart-e9a11cff-e914-4eeb-a998-6e47ad042ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791541277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1791541277
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.283550859
Short name T303
Test name
Test status
Simulation time 2932716654 ps
CPU time 26.59 seconds
Started Dec 31 12:54:30 PM PST 23
Finished Dec 31 12:54:58 PM PST 23
Peak memory 210956 kb
Host smart-e1792b0d-9e59-4471-8fbc-58adf16857ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283550859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.283550859
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.732090197
Short name T231
Test name
Test status
Simulation time 892909660 ps
CPU time 10.45 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:55:12 PM PST 23
Peak memory 210872 kb
Host smart-8a2b6b4e-aab9-4ab6-a162-44eb206b80aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=732090197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.732090197
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3294232743
Short name T310
Test name
Test status
Simulation time 42551993462 ps
CPU time 31.5 seconds
Started Dec 31 12:54:15 PM PST 23
Finished Dec 31 12:54:49 PM PST 23
Peak memory 213604 kb
Host smart-1d272a41-1f6e-438f-a0d2-5f29bb74e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294232743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3294232743
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.227032221
Short name T94
Test name
Test status
Simulation time 39747940064 ps
CPU time 69.23 seconds
Started Dec 31 12:54:56 PM PST 23
Finished Dec 31 12:56:09 PM PST 23
Peak memory 217384 kb
Host smart-519749df-96fc-4b6f-835c-eeac13ee9e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227032221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.227032221
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1154476652
Short name T17
Test name
Test status
Simulation time 20002065183 ps
CPU time 2024.05 seconds
Started Dec 31 12:54:54 PM PST 23
Finished Dec 31 01:28:43 PM PST 23
Peak memory 222432 kb
Host smart-617445ce-809e-43bd-8cc6-2df38fe339e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154476652 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1154476652
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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