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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.54 97.11 92.83 97.88 100.00 98.69 97.89 98.38


Total test records in report: 476
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T265 /workspace/coverage/default/17.rom_ctrl_stress_all.1758614408 Jan 03 12:28:59 PM PST 24 Jan 03 12:29:55 PM PST 24 5077293337 ps
T266 /workspace/coverage/default/26.rom_ctrl_stress_all.2196279772 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:37 PM PST 24 5431516543 ps
T267 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2110366861 Jan 03 12:36:13 PM PST 24 Jan 03 12:38:06 PM PST 24 168738786 ps
T268 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4170951271 Jan 03 12:27:32 PM PST 24 Jan 03 12:28:45 PM PST 24 1025135618 ps
T269 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3353847879 Jan 03 12:27:31 PM PST 24 Jan 03 12:42:18 PM PST 24 225024137293 ps
T270 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2254588311 Jan 03 12:38:28 PM PST 24 Jan 03 12:46:14 PM PST 24 174322901749 ps
T271 /workspace/coverage/default/33.rom_ctrl_alert_test.1787411577 Jan 03 12:29:52 PM PST 24 Jan 03 12:30:47 PM PST 24 1405341932 ps
T272 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.240384355 Jan 03 12:29:15 PM PST 24 Jan 03 12:29:52 PM PST 24 319615885 ps
T273 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2697751957 Jan 03 12:28:53 PM PST 24 Jan 03 12:57:11 PM PST 24 40269137412 ps
T274 /workspace/coverage/default/16.rom_ctrl_alert_test.2291631177 Jan 03 12:24:35 PM PST 24 Jan 03 12:24:51 PM PST 24 1542752629 ps
T275 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4110359205 Jan 03 12:29:39 PM PST 24 Jan 03 12:30:22 PM PST 24 383698287 ps
T276 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3469399208 Jan 03 12:29:37 PM PST 24 Jan 03 12:30:27 PM PST 24 1185484364 ps
T277 /workspace/coverage/default/19.rom_ctrl_smoke.1498054291 Jan 03 12:28:06 PM PST 24 Jan 03 12:28:49 PM PST 24 7347669870 ps
T278 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1595513619 Jan 03 12:30:39 PM PST 24 Jan 03 12:31:48 PM PST 24 306922655 ps
T279 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3646144201 Jan 03 12:30:43 PM PST 24 Jan 03 01:15:28 PM PST 24 73049014221 ps
T280 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1278512105 Jan 03 12:29:50 PM PST 24 Jan 03 12:39:28 PM PST 24 55498907840 ps
T281 /workspace/coverage/default/12.rom_ctrl_stress_all.1793220838 Jan 03 12:22:56 PM PST 24 Jan 03 12:23:09 PM PST 24 369015415 ps
T282 /workspace/coverage/default/30.rom_ctrl_stress_all.2379559085 Jan 03 12:29:05 PM PST 24 Jan 03 12:30:07 PM PST 24 11646144679 ps
T283 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3927544495 Jan 03 12:29:18 PM PST 24 Jan 03 12:29:52 PM PST 24 97748839 ps
T284 /workspace/coverage/default/31.rom_ctrl_alert_test.2743036019 Jan 03 12:35:42 PM PST 24 Jan 03 12:37:34 PM PST 24 2196683572 ps
T285 /workspace/coverage/default/18.rom_ctrl_alert_test.2302396238 Jan 03 12:30:06 PM PST 24 Jan 03 12:30:55 PM PST 24 396390148 ps
T286 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3468357130 Jan 03 12:29:17 PM PST 24 Jan 03 12:30:18 PM PST 24 22413446959 ps
T287 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2921776493 Jan 03 12:29:19 PM PST 24 Jan 03 12:30:05 PM PST 24 4500327072 ps
T288 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3963722411 Jan 03 12:36:00 PM PST 24 Jan 03 01:05:52 PM PST 24 152856978055 ps
T289 /workspace/coverage/default/40.rom_ctrl_stress_all.640628397 Jan 03 12:29:45 PM PST 24 Jan 03 12:30:35 PM PST 24 154799580 ps
T290 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3455516837 Jan 03 12:29:10 PM PST 24 Jan 03 12:30:09 PM PST 24 7901464462 ps
T291 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2772792849 Jan 03 12:30:10 PM PST 24 Jan 03 12:31:27 PM PST 24 15007965853 ps
T292 /workspace/coverage/default/40.rom_ctrl_smoke.1454983565 Jan 03 12:29:35 PM PST 24 Jan 03 12:30:38 PM PST 24 2394016035 ps
T293 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3065351742 Jan 03 12:29:35 PM PST 24 Jan 03 12:30:25 PM PST 24 17371117781 ps
T294 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3123702199 Jan 03 12:30:05 PM PST 24 Jan 03 12:30:59 PM PST 24 175480666 ps
T295 /workspace/coverage/default/48.rom_ctrl_smoke.668278751 Jan 03 12:33:53 PM PST 24 Jan 03 12:35:21 PM PST 24 1098622233 ps
T296 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3116960930 Jan 03 12:29:37 PM PST 24 Jan 03 12:32:05 PM PST 24 1961214089 ps
T297 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1011416181 Jan 03 12:29:44 PM PST 24 Jan 03 03:04:27 PM PST 24 162874175410 ps
T298 /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2288767388 Jan 03 12:23:18 PM PST 24 Jan 03 12:40:46 PM PST 24 85601023949 ps
T299 /workspace/coverage/default/5.rom_ctrl_smoke.2571821626 Jan 03 12:27:15 PM PST 24 Jan 03 12:27:59 PM PST 24 8056225446 ps
T300 /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.438350347 Jan 03 12:27:38 PM PST 24 Jan 03 12:27:56 PM PST 24 6005391991 ps
T301 /workspace/coverage/default/12.rom_ctrl_smoke.3419865617 Jan 03 12:29:15 PM PST 24 Jan 03 12:29:54 PM PST 24 365044540 ps
T302 /workspace/coverage/default/35.rom_ctrl_stress_all.646758995 Jan 03 12:26:34 PM PST 24 Jan 03 12:27:02 PM PST 24 5965273937 ps
T303 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.727438199 Jan 03 12:28:34 PM PST 24 Jan 03 12:28:59 PM PST 24 490173194 ps
T304 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2054021092 Jan 03 12:27:30 PM PST 24 Jan 03 12:27:52 PM PST 24 11470541229 ps
T305 /workspace/coverage/default/25.rom_ctrl_alert_test.1207288379 Jan 03 12:34:54 PM PST 24 Jan 03 12:36:32 PM PST 24 661550459 ps
T306 /workspace/coverage/default/1.rom_ctrl_stress_all.304381436 Jan 03 12:29:23 PM PST 24 Jan 03 12:30:10 PM PST 24 2919430540 ps
T307 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2240650295 Jan 03 12:31:38 PM PST 24 Jan 03 12:33:29 PM PST 24 3460870340 ps
T308 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3743878203 Jan 03 12:29:54 PM PST 24 Jan 03 12:30:44 PM PST 24 361052673 ps
T309 /workspace/coverage/default/1.rom_ctrl_smoke.319941733 Jan 03 12:27:24 PM PST 24 Jan 03 12:28:02 PM PST 24 4128591174 ps
T310 /workspace/coverage/default/6.rom_ctrl_alert_test.1357239479 Jan 03 12:29:19 PM PST 24 Jan 03 12:30:01 PM PST 24 15333700605 ps
T311 /workspace/coverage/default/35.rom_ctrl_smoke.2281480732 Jan 03 12:29:08 PM PST 24 Jan 03 12:29:48 PM PST 24 1628446227 ps
T312 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3040204116 Jan 03 12:29:53 PM PST 24 Jan 03 12:31:08 PM PST 24 18503962479 ps
T313 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1312476820 Jan 03 12:27:32 PM PST 24 Jan 03 02:30:06 PM PST 24 345057566388 ps
T314 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.279354044 Jan 03 12:29:32 PM PST 24 Jan 03 12:30:12 PM PST 24 541842431 ps
T315 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1059751115 Jan 03 12:26:46 PM PST 24 Jan 03 12:42:45 PM PST 24 46013369963 ps
T316 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1177316247 Jan 03 12:28:49 PM PST 24 Jan 03 12:57:26 PM PST 24 73695288914 ps
T317 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2344468073 Jan 03 12:23:47 PM PST 24 Jan 03 12:24:03 PM PST 24 3143927691 ps
T318 /workspace/coverage/default/42.rom_ctrl_smoke.2753520980 Jan 03 12:30:03 PM PST 24 Jan 03 12:31:11 PM PST 24 1961159665 ps
T319 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1981942457 Jan 03 12:29:52 PM PST 24 Jan 03 12:30:50 PM PST 24 15766759932 ps
T320 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3556301028 Jan 03 12:28:46 PM PST 24 Jan 03 12:33:04 PM PST 24 52392180930 ps
T321 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.353200969 Jan 03 12:30:22 PM PST 24 Jan 03 12:31:50 PM PST 24 16373889749 ps
T322 /workspace/coverage/default/37.rom_ctrl_smoke.233270172 Jan 03 12:29:12 PM PST 24 Jan 03 12:30:02 PM PST 24 8897233661 ps
T323 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.834472163 Jan 03 12:29:51 PM PST 24 Jan 03 12:30:43 PM PST 24 664484329 ps
T48 /workspace/coverage/default/1.rom_ctrl_sec_cm.889309677 Jan 03 12:25:44 PM PST 24 Jan 03 12:27:44 PM PST 24 6772242560 ps
T324 /workspace/coverage/default/1.rom_ctrl_alert_test.1837923843 Jan 03 12:29:19 PM PST 24 Jan 03 12:29:52 PM PST 24 346421735 ps
T325 /workspace/coverage/default/27.rom_ctrl_smoke.2144822310 Jan 03 12:29:03 PM PST 24 Jan 03 12:29:58 PM PST 24 3373627664 ps
T326 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3694596358 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:08 PM PST 24 9207842797 ps
T327 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1725986025 Jan 03 12:29:52 PM PST 24 Jan 03 12:52:51 PM PST 24 76608100954 ps
T328 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2849384198 Jan 03 12:29:23 PM PST 24 Jan 03 12:32:34 PM PST 24 18541411878 ps
T329 /workspace/coverage/default/30.rom_ctrl_alert_test.364296564 Jan 03 12:29:03 PM PST 24 Jan 03 12:29:43 PM PST 24 2927426989 ps
T330 /workspace/coverage/default/38.rom_ctrl_alert_test.2165549847 Jan 03 12:29:39 PM PST 24 Jan 03 12:30:31 PM PST 24 6206165421 ps
T331 /workspace/coverage/default/41.rom_ctrl_stress_all.2560990125 Jan 03 12:26:34 PM PST 24 Jan 03 12:27:25 PM PST 24 66886756697 ps
T332 /workspace/coverage/default/26.rom_ctrl_smoke.2354377056 Jan 03 12:29:21 PM PST 24 Jan 03 12:30:01 PM PST 24 380133675 ps
T333 /workspace/coverage/default/14.rom_ctrl_stress_all.3487161222 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:50 PM PST 24 24771743087 ps
T334 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1452071889 Jan 03 12:22:56 PM PST 24 Jan 03 12:29:29 PM PST 24 74008873282 ps
T335 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4174948471 Jan 03 12:29:21 PM PST 24 Jan 03 12:33:30 PM PST 24 80004526525 ps
T336 /workspace/coverage/default/43.rom_ctrl_smoke.2568135868 Jan 03 12:29:46 PM PST 24 Jan 03 12:30:56 PM PST 24 6180277189 ps
T337 /workspace/coverage/default/41.rom_ctrl_alert_test.557657533 Jan 03 12:28:44 PM PST 24 Jan 03 12:29:24 PM PST 24 1461179961 ps
T338 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4167222166 Jan 03 12:29:00 PM PST 24 Jan 03 12:33:07 PM PST 24 16118879048 ps
T339 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.422054334 Jan 03 12:31:18 PM PST 24 Jan 03 12:53:01 PM PST 24 159078910103 ps
T340 /workspace/coverage/default/47.rom_ctrl_alert_test.3785229951 Jan 03 12:28:32 PM PST 24 Jan 03 12:28:51 PM PST 24 85475228 ps
T341 /workspace/coverage/default/31.rom_ctrl_stress_all.2721654401 Jan 03 12:29:20 PM PST 24 Jan 03 12:30:48 PM PST 24 10233227355 ps
T342 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.444819812 Jan 03 12:26:26 PM PST 24 Jan 03 12:26:37 PM PST 24 341660126 ps
T343 /workspace/coverage/default/18.rom_ctrl_smoke.1263919260 Jan 03 12:22:57 PM PST 24 Jan 03 12:23:25 PM PST 24 2042739106 ps
T344 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1065290804 Jan 03 12:28:41 PM PST 24 Jan 03 12:47:19 PM PST 24 20855802397 ps
T345 /workspace/coverage/default/42.rom_ctrl_stress_all.394051084 Jan 03 12:41:56 PM PST 24 Jan 03 12:44:08 PM PST 24 21083369660 ps
T346 /workspace/coverage/default/4.rom_ctrl_smoke.1815823696 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:06 PM PST 24 7546676335 ps
T347 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1753767847 Jan 03 12:35:35 PM PST 24 Jan 03 12:39:38 PM PST 24 32055043388 ps
T348 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2425872938 Jan 03 12:30:09 PM PST 24 Jan 03 12:31:08 PM PST 24 5289557412 ps
T349 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2111798766 Jan 03 12:28:56 PM PST 24 Jan 03 02:21:35 PM PST 24 119656667615 ps
T36 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.168037817 Jan 03 12:29:00 PM PST 24 Jan 03 12:29:47 PM PST 24 3557245621 ps
T350 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3366993806 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:22 PM PST 24 1847195975 ps
T351 /workspace/coverage/default/27.rom_ctrl_alert_test.2802835335 Jan 03 12:32:25 PM PST 24 Jan 03 12:34:02 PM PST 24 931916029 ps
T352 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4032088338 Jan 03 12:29:27 PM PST 24 Jan 03 12:30:16 PM PST 24 1902886543 ps
T353 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1531582109 Jan 03 12:29:08 PM PST 24 Jan 03 12:29:46 PM PST 24 260206390 ps
T354 /workspace/coverage/default/40.rom_ctrl_alert_test.2467469678 Jan 03 12:29:20 PM PST 24 Jan 03 12:30:03 PM PST 24 12906484556 ps
T355 /workspace/coverage/default/0.rom_ctrl_stress_all.470814832 Jan 03 12:29:09 PM PST 24 Jan 03 12:29:46 PM PST 24 379236673 ps
T356 /workspace/coverage/default/2.rom_ctrl_smoke.2338218991 Jan 03 12:29:16 PM PST 24 Jan 03 12:30:23 PM PST 24 23007540042 ps
T357 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1639865366 Jan 03 12:29:20 PM PST 24 Jan 03 12:30:00 PM PST 24 175698280 ps
T358 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3116196130 Jan 03 12:29:13 PM PST 24 Jan 03 12:47:26 PM PST 24 86828800844 ps
T359 /workspace/coverage/default/11.rom_ctrl_alert_test.818014133 Jan 03 12:29:50 PM PST 24 Jan 03 12:30:48 PM PST 24 2046725069 ps
T360 /workspace/coverage/default/10.rom_ctrl_smoke.2295020314 Jan 03 12:29:20 PM PST 24 Jan 03 12:30:02 PM PST 24 1066187648 ps
T361 /workspace/coverage/default/26.rom_ctrl_alert_test.918853292 Jan 03 12:28:43 PM PST 24 Jan 03 12:29:25 PM PST 24 28597066755 ps
T362 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2332722184 Jan 03 12:28:20 PM PST 24 Jan 03 12:28:42 PM PST 24 14572381700 ps
T363 /workspace/coverage/default/24.rom_ctrl_stress_all.2812197421 Jan 03 12:35:12 PM PST 24 Jan 03 12:37:24 PM PST 24 21779515898 ps
T364 /workspace/coverage/default/5.rom_ctrl_alert_test.4071124842 Jan 03 12:30:07 PM PST 24 Jan 03 12:31:05 PM PST 24 1106377550 ps
T365 /workspace/coverage/default/8.rom_ctrl_alert_test.1168226237 Jan 03 12:41:49 PM PST 24 Jan 03 12:43:31 PM PST 24 1761405843 ps
T366 /workspace/coverage/default/16.rom_ctrl_smoke.734750629 Jan 03 12:30:40 PM PST 24 Jan 03 12:31:53 PM PST 24 672141589 ps
T367 /workspace/coverage/default/32.rom_ctrl_alert_test.3381102280 Jan 03 12:29:11 PM PST 24 Jan 03 12:29:51 PM PST 24 2844414334 ps
T368 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3598613798 Jan 03 12:29:18 PM PST 24 Jan 03 12:29:57 PM PST 24 2195667160 ps
T369 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.145687267 Jan 03 12:29:00 PM PST 24 Jan 03 12:32:09 PM PST 24 5677355662 ps
T370 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3686810037 Jan 03 12:26:14 PM PST 24 Jan 03 12:29:37 PM PST 24 19865849088 ps
T371 /workspace/coverage/default/20.rom_ctrl_alert_test.377980984 Jan 03 12:30:09 PM PST 24 Jan 03 12:31:11 PM PST 24 1970883011 ps
T372 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1636697257 Jan 03 12:32:19 PM PST 24 Jan 03 12:34:57 PM PST 24 3846257332 ps
T373 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1580459516 Jan 03 12:35:44 PM PST 24 Jan 03 12:37:44 PM PST 24 1836614801 ps
T374 /workspace/coverage/default/25.rom_ctrl_smoke.4007201524 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:02 PM PST 24 1195513812 ps
T375 /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4170673880 Jan 03 12:29:50 PM PST 24 Jan 03 12:39:39 PM PST 24 240771161498 ps
T376 /workspace/coverage/default/17.rom_ctrl_smoke.4141313250 Jan 03 12:41:47 PM PST 24 Jan 03 12:43:26 PM PST 24 795984985 ps
T377 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2909017094 Jan 03 12:29:24 PM PST 24 Jan 03 12:30:26 PM PST 24 3755129341 ps
T378 /workspace/coverage/default/23.rom_ctrl_smoke.4152619858 Jan 03 12:29:15 PM PST 24 Jan 03 12:30:12 PM PST 24 3193804769 ps
T379 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3321145316 Jan 03 12:29:08 PM PST 24 Jan 03 12:32:20 PM PST 24 16194130229 ps
T380 /workspace/coverage/default/20.rom_ctrl_smoke.4003057501 Jan 03 12:27:38 PM PST 24 Jan 03 12:27:54 PM PST 24 756531192 ps
T381 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.315935684 Jan 03 12:28:50 PM PST 24 Jan 03 12:29:27 PM PST 24 270043170 ps
T382 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2778898270 Jan 03 12:30:39 PM PST 24 Jan 03 12:31:49 PM PST 24 224642960 ps
T383 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1656429808 Jan 03 12:23:18 PM PST 24 Jan 03 12:23:29 PM PST 24 722953259 ps
T384 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3608913599 Jan 03 12:26:44 PM PST 24 Jan 03 12:29:56 PM PST 24 36912892665 ps
T385 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2347483686 Jan 03 12:29:57 PM PST 24 Jan 03 12:31:04 PM PST 24 3948664436 ps
T386 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2891651386 Jan 03 12:29:46 PM PST 24 Jan 03 12:30:41 PM PST 24 1637701371 ps
T387 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3526754794 Jan 03 12:30:04 PM PST 24 Jan 03 12:30:58 PM PST 24 665295710 ps
T388 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.240871923 Jan 03 12:29:02 PM PST 24 Jan 03 12:29:43 PM PST 24 3073381775 ps
T389 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.825503468 Jan 03 12:30:22 PM PST 24 Jan 03 01:34:22 PM PST 24 49964087604 ps
T390 /workspace/coverage/default/8.rom_ctrl_smoke.3546182229 Jan 03 12:36:16 PM PST 24 Jan 03 12:38:21 PM PST 24 9020422199 ps
T391 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.889480274 Jan 03 12:30:40 PM PST 24 Jan 03 01:14:59 PM PST 24 73719600628 ps
T392 /workspace/coverage/default/8.rom_ctrl_stress_all.3082490641 Jan 03 12:29:52 PM PST 24 Jan 03 12:31:18 PM PST 24 10489527405 ps
T393 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3586178103 Jan 03 12:29:07 PM PST 24 Jan 03 12:29:48 PM PST 24 7054579622 ps
T394 /workspace/coverage/default/34.rom_ctrl_alert_test.417159080 Jan 03 12:29:27 PM PST 24 Jan 03 12:30:13 PM PST 24 1565534317 ps
T395 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1670998811 Jan 03 12:27:31 PM PST 24 Jan 03 12:28:09 PM PST 24 4014014175 ps
T396 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2330230651 Jan 03 12:28:36 PM PST 24 Jan 03 12:28:57 PM PST 24 96089639 ps
T397 /workspace/coverage/default/35.rom_ctrl_alert_test.2093167541 Jan 03 12:28:30 PM PST 24 Jan 03 12:28:49 PM PST 24 289753331 ps
T398 /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1749224106 Jan 03 12:29:36 PM PST 24 Jan 03 12:32:42 PM PST 24 8649988535 ps
T399 /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2531552688 Jan 03 12:29:34 PM PST 24 Jan 03 01:05:44 PM PST 24 40759037372 ps
T400 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1359353966 Jan 03 12:29:49 PM PST 24 Jan 03 12:31:38 PM PST 24 2286419573 ps
T401 /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4153534711 Jan 03 12:38:49 PM PST 24 Jan 03 12:40:16 PM PST 24 173877861 ps
T96 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2074945280 Jan 03 12:45:22 PM PST 24 Jan 03 01:15:13 PM PST 24 48590627103 ps
T402 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.415414616 Jan 03 12:29:06 PM PST 24 Jan 03 12:29:48 PM PST 24 5963349130 ps
T403 /workspace/coverage/default/45.rom_ctrl_alert_test.3950899040 Jan 03 12:28:32 PM PST 24 Jan 03 12:28:57 PM PST 24 2400263652 ps
T404 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2608584344 Jan 03 12:29:16 PM PST 24 Jan 03 12:30:01 PM PST 24 4137103803 ps
T405 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3031687984 Jan 03 12:29:04 PM PST 24 Jan 03 01:16:11 PM PST 24 30288915478 ps
T406 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.968084769 Jan 03 12:29:24 PM PST 24 Jan 03 12:30:01 PM PST 24 549495929 ps
T407 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1963799613 Jan 03 12:29:59 PM PST 24 Jan 03 12:30:56 PM PST 24 5508431126 ps
T408 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3357269669 Jan 03 12:30:09 PM PST 24 Jan 03 02:11:00 PM PST 24 119470032124 ps
T409 /workspace/coverage/default/45.rom_ctrl_smoke.3917762433 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:43 PM PST 24 7396704998 ps
T49 /workspace/coverage/default/4.rom_ctrl_sec_cm.2475514840 Jan 03 12:30:00 PM PST 24 Jan 03 12:31:43 PM PST 24 4153236691 ps
T410 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2882013832 Jan 03 12:28:26 PM PST 24 Jan 03 12:31:37 PM PST 24 11616362265 ps
T411 /workspace/coverage/default/25.rom_ctrl_stress_all.3733117246 Jan 03 12:35:14 PM PST 24 Jan 03 12:37:07 PM PST 24 1919773096 ps
T412 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4266030573 Jan 03 12:29:55 PM PST 24 Jan 03 12:30:51 PM PST 24 2951126067 ps
T413 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1985275284 Jan 03 12:28:41 PM PST 24 Jan 03 12:30:27 PM PST 24 6055633785 ps
T414 /workspace/coverage/default/15.rom_ctrl_stress_all.3854388408 Jan 03 12:23:36 PM PST 24 Jan 03 12:24:54 PM PST 24 7747938566 ps
T415 /workspace/coverage/default/49.rom_ctrl_alert_test.3479606364 Jan 03 12:29:54 PM PST 24 Jan 03 12:30:52 PM PST 24 1797393312 ps
T416 /workspace/coverage/default/29.rom_ctrl_stress_all.4051545271 Jan 03 12:26:47 PM PST 24 Jan 03 12:27:03 PM PST 24 264073735 ps
T417 /workspace/coverage/default/44.rom_ctrl_smoke.2507237431 Jan 03 12:35:17 PM PST 24 Jan 03 12:37:29 PM PST 24 5242247122 ps
T418 /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4077880047 Jan 03 12:29:52 PM PST 24 Jan 03 12:30:50 PM PST 24 3298740472 ps
T419 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.515213693 Jan 03 12:30:55 PM PST 24 Jan 03 12:32:05 PM PST 24 90839517 ps
T420 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.156643198 Jan 03 12:26:05 PM PST 24 Jan 03 12:26:17 PM PST 24 1152650761 ps
T421 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2782253485 Jan 03 12:27:26 PM PST 24 Jan 03 12:27:40 PM PST 24 1772560321 ps
T422 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2306654407 Jan 03 12:24:51 PM PST 24 Jan 03 12:25:00 PM PST 24 4114864807 ps
T423 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3945737737 Jan 03 12:28:43 PM PST 24 Jan 03 12:29:14 PM PST 24 92171555 ps
T424 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2354130477 Jan 03 12:28:33 PM PST 24 Jan 03 12:28:55 PM PST 24 487750946 ps
T83 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2548274102 Jan 03 12:30:38 PM PST 24 Jan 03 12:31:46 PM PST 24 208848195 ps
T425 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1454760845 Jan 03 12:29:49 PM PST 24 Jan 03 12:30:46 PM PST 24 6173454053 ps
T426 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.575115625 Jan 03 12:27:19 PM PST 24 Jan 03 12:27:38 PM PST 24 8072523031 ps
T75 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.663056143 Jan 03 12:27:05 PM PST 24 Jan 03 12:27:20 PM PST 24 4773210254 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.26753955 Jan 03 12:29:22 PM PST 24 Jan 03 12:30:44 PM PST 24 13824563335 ps
T84 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2512502033 Jan 03 12:28:56 PM PST 24 Jan 03 12:29:38 PM PST 24 1553728833 ps
T101 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.904903147 Jan 03 12:28:46 PM PST 24 Jan 03 12:30:32 PM PST 24 1707451024 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1905671258 Jan 03 12:28:34 PM PST 24 Jan 03 12:29:06 PM PST 24 9189725243 ps
T429 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2691631412 Jan 03 12:28:42 PM PST 24 Jan 03 12:29:12 PM PST 24 87162797 ps
T99 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3472060120 Jan 03 12:25:55 PM PST 24 Jan 03 12:27:19 PM PST 24 2123807855 ps
T430 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2782192196 Jan 03 12:29:23 PM PST 24 Jan 03 12:30:39 PM PST 24 1528186895 ps
T85 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.696876237 Jan 03 12:30:39 PM PST 24 Jan 03 12:32:32 PM PST 24 4058123871 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3589228210 Jan 03 12:24:09 PM PST 24 Jan 03 12:24:22 PM PST 24 1420436121 ps
T432 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2777539937 Jan 03 12:27:16 PM PST 24 Jan 03 12:28:24 PM PST 24 2352837664 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2723995950 Jan 03 12:27:51 PM PST 24 Jan 03 12:28:00 PM PST 24 129120234 ps
T434 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.612892669 Jan 03 12:27:19 PM PST 24 Jan 03 12:27:27 PM PST 24 85756015 ps
T435 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2696556013 Jan 03 12:28:13 PM PST 24 Jan 03 12:28:31 PM PST 24 976199208 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2540141666 Jan 03 12:27:05 PM PST 24 Jan 03 12:32:40 PM PST 24 63809843844 ps
T437 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3942092180 Jan 03 12:29:15 PM PST 24 Jan 03 12:29:57 PM PST 24 12465319620 ps
T438 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1389822382 Jan 03 12:27:26 PM PST 24 Jan 03 12:28:49 PM PST 24 569514691 ps
T439 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.5029197 Jan 03 12:22:45 PM PST 24 Jan 03 12:23:04 PM PST 24 3344093350 ps
T440 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.290271978 Jan 03 12:27:38 PM PST 24 Jan 03 12:27:52 PM PST 24 669620790 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3908705896 Jan 03 12:29:58 PM PST 24 Jan 03 12:31:28 PM PST 24 1489675365 ps
T442 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2915107846 Jan 03 12:29:02 PM PST 24 Jan 03 12:29:38 PM PST 24 2046786173 ps
T443 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1694555660 Jan 03 12:29:57 PM PST 24 Jan 03 12:30:59 PM PST 24 16448318529 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.457353561 Jan 03 12:28:16 PM PST 24 Jan 03 12:28:29 PM PST 24 690997045 ps
T445 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3556414965 Jan 03 12:27:05 PM PST 24 Jan 03 12:27:25 PM PST 24 4145582898 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2909340983 Jan 03 12:27:05 PM PST 24 Jan 03 12:27:21 PM PST 24 1612188508 ps
T447 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3961220689 Jan 03 12:37:26 PM PST 24 Jan 03 12:39:34 PM PST 24 3655831709 ps
T448 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1006355535 Jan 03 12:24:02 PM PST 24 Jan 03 12:24:15 PM PST 24 387757097 ps
T449 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2552646759 Jan 03 12:30:07 PM PST 24 Jan 03 12:31:00 PM PST 24 488864195 ps
T450 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3357508777 Jan 03 12:29:32 PM PST 24 Jan 03 12:30:15 PM PST 24 1568214078 ps
T451 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.659583757 Jan 03 12:26:27 PM PST 24 Jan 03 12:26:38 PM PST 24 2600748639 ps
T452 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2724745200 Jan 03 12:23:38 PM PST 24 Jan 03 12:23:45 PM PST 24 387714444 ps
T453 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.414906269 Jan 03 12:30:10 PM PST 24 Jan 03 12:31:05 PM PST 24 3139073232 ps
T454 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3047136889 Jan 03 12:24:30 PM PST 24 Jan 03 12:25:17 PM PST 24 399116325 ps
T455 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.801127012 Jan 03 12:28:28 PM PST 24 Jan 03 12:29:25 PM PST 24 3569460860 ps
T456 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3583884306 Jan 03 12:27:26 PM PST 24 Jan 03 12:27:43 PM PST 24 1115452815 ps
T457 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1320989164 Jan 03 12:24:45 PM PST 24 Jan 03 12:24:57 PM PST 24 3241433958 ps
T458 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2872919282 Jan 03 12:25:29 PM PST 24 Jan 03 12:25:47 PM PST 24 25051194111 ps
T459 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2581816608 Jan 03 12:30:54 PM PST 24 Jan 03 12:32:15 PM PST 24 38664211376 ps
T460 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3375401507 Jan 03 12:29:31 PM PST 24 Jan 03 12:32:50 PM PST 24 17138147442 ps
T461 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2211054319 Jan 03 12:36:01 PM PST 24 Jan 03 12:38:02 PM PST 24 1473035941 ps
T105 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3939631635 Jan 03 12:23:43 PM PST 24 Jan 03 12:25:11 PM PST 24 883695927 ps
T462 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.759277858 Jan 03 12:29:57 PM PST 24 Jan 03 12:30:56 PM PST 24 1363979517 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3491183809 Jan 03 12:27:19 PM PST 24 Jan 03 12:27:36 PM PST 24 1147968462 ps
T464 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.769752568 Jan 03 12:29:21 PM PST 24 Jan 03 12:30:04 PM PST 24 24596043021 ps
T465 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1826871126 Jan 03 12:29:09 PM PST 24 Jan 03 12:29:51 PM PST 24 1863099574 ps
T466 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2016397761 Jan 03 12:28:41 PM PST 24 Jan 03 12:29:16 PM PST 24 7320391406 ps
T467 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1935843392 Jan 03 12:27:19 PM PST 24 Jan 03 12:28:15 PM PST 24 1034204957 ps
T468 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3440981722 Jan 03 12:27:39 PM PST 24 Jan 03 12:27:54 PM PST 24 1992088990 ps
T469 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2379112170 Jan 03 12:29:14 PM PST 24 Jan 03 12:29:50 PM PST 24 1529633612 ps
T470 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1119498685 Jan 03 12:30:50 PM PST 24 Jan 03 12:32:12 PM PST 24 6188152491 ps
T104 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3014952193 Jan 03 12:29:07 PM PST 24 Jan 03 12:30:49 PM PST 24 399451219 ps
T471 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3321325366 Jan 03 12:27:25 PM PST 24 Jan 03 12:27:42 PM PST 24 4320948868 ps
T472 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3406301796 Jan 03 12:27:20 PM PST 24 Jan 03 12:27:35 PM PST 24 5447087488 ps
T76 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2650925046 Jan 03 12:29:15 PM PST 24 Jan 03 12:30:01 PM PST 24 6115012576 ps
T102 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.6410248 Jan 03 12:29:17 PM PST 24 Jan 03 12:31:01 PM PST 24 2048010768 ps
T473 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3937993859 Jan 03 12:22:44 PM PST 24 Jan 03 12:22:57 PM PST 24 3973828834 ps
T474 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.543855724 Jan 03 12:27:20 PM PST 24 Jan 03 12:29:56 PM PST 24 98910924176 ps
T475 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3948134357 Jan 03 12:28:17 PM PST 24 Jan 03 12:28:36 PM PST 24 5647209391 ps
T476 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3206534682 Jan 03 12:30:22 PM PST 24 Jan 03 12:37:21 PM PST 24 38803029198 ps

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.3475924115
Short name T20
Test name
Test status
Simulation time 739837255 ps
CPU time 6.65 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:14 PM PST 24
Peak memory 209340 kb
Host smart-5ab7a757-5667-4dbe-bf3d-4a8d833ade94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475924115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.3475924115
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.1348223196
Short name T2
Test name
Test status
Simulation time 38203156090 ps
CPU time 5450.86 seconds
Started Jan 03 12:29:00 PM PST 24
Finished Jan 03 02:00:17 PM PST 24
Peak memory 235536 kb
Host smart-b29fdff3-8c99-4660-b06f-f9bb9e25fc1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348223196 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.1348223196
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.2278114350
Short name T23
Test name
Test status
Simulation time 27140275801 ps
CPU time 274.46 seconds
Started Jan 03 12:28:45 PM PST 24
Finished Jan 03 12:33:48 PM PST 24
Peak memory 211132 kb
Host smart-f7e14c9e-5497-4bd0-b0bc-b5d9b0b0fcc3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278114350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.2278114350
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1792321369
Short name T47
Test name
Test status
Simulation time 237660130 ps
CPU time 78.6 seconds
Started Jan 03 12:23:32 PM PST 24
Finished Jan 03 12:24:51 PM PST 24
Peak memory 213580 kb
Host smart-7d31352d-43cf-4bef-9d0e-8b3b83dce672
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792321369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1792321369
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.93343400
Short name T59
Test name
Test status
Simulation time 2068803079 ps
CPU time 19.88 seconds
Started Jan 03 12:27:59 PM PST 24
Finished Jan 03 12:28:28 PM PST 24
Peak memory 218140 kb
Host smart-bc276784-cd8d-4626-b4ba-68429c9cd031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93343400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.93343400
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2290673059
Short name T19
Test name
Test status
Simulation time 123855915296 ps
CPU time 564.66 seconds
Started Jan 03 12:27:25 PM PST 24
Finished Jan 03 12:36:55 PM PST 24
Peak memory 224308 kb
Host smart-9d7a849a-c623-4c7d-ba32-bd6043246dca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290673059 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2290673059
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.680807479
Short name T88
Test name
Test status
Simulation time 2709630512 ps
CPU time 30.91 seconds
Started Jan 03 12:29:13 PM PST 24
Finished Jan 03 12:30:11 PM PST 24
Peak memory 212684 kb
Host smart-2b4116a9-5e55-47c2-8598-8769460a79fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680807479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.680807479
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3472060120
Short name T99
Test name
Test status
Simulation time 2123807855 ps
CPU time 83.6 seconds
Started Jan 03 12:25:55 PM PST 24
Finished Jan 03 12:27:19 PM PST 24
Peak memory 212156 kb
Host smart-f0b28aa6-abe9-4c13-a660-407797c9273a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472060120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3472060120
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.3971506144
Short name T108
Test name
Test status
Simulation time 1739574422 ps
CPU time 14.01 seconds
Started Jan 03 12:24:35 PM PST 24
Finished Jan 03 12:24:51 PM PST 24
Peak memory 219280 kb
Host smart-a94a193d-fbc9-48bd-ae3f-8df9166a2780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971506144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.3971506144
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.889309677
Short name T48
Test name
Test status
Simulation time 6772242560 ps
CPU time 118.88 seconds
Started Jan 03 12:25:44 PM PST 24
Finished Jan 03 12:27:44 PM PST 24
Peak memory 236296 kb
Host smart-dcc78d2d-6ba4-4cfc-b1ad-864eb71a8647
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889309677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.889309677
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2804555998
Short name T35
Test name
Test status
Simulation time 11394457666 ps
CPU time 25.87 seconds
Started Jan 03 12:28:55 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 211260 kb
Host smart-bd987bf6-57ac-4d88-9acf-41cfe98e9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804555998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2804555998
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.380101881
Short name T106
Test name
Test status
Simulation time 2705513190 ps
CPU time 16.69 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:29:07 PM PST 24
Peak memory 214180 kb
Host smart-a41c643e-a044-4af0-ba82-a7c0b6a51eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380101881 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.380101881
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.2871421952
Short name T172
Test name
Test status
Simulation time 883428392 ps
CPU time 15.94 seconds
Started Jan 03 12:27:32 PM PST 24
Finished Jan 03 12:27:52 PM PST 24
Peak memory 210544 kb
Host smart-3d4c0c8d-674b-4466-9b59-68890941c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871421952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.2871421952
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.168037817
Short name T36
Test name
Test status
Simulation time 3557245621 ps
CPU time 20.83 seconds
Started Jan 03 12:29:00 PM PST 24
Finished Jan 03 12:29:47 PM PST 24
Peak memory 210796 kb
Host smart-dec219fc-962a-4f5e-9bd1-4185f569f4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168037817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.168037817
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3014952193
Short name T104
Test name
Test status
Simulation time 399451219 ps
CPU time 75.31 seconds
Started Jan 03 12:29:07 PM PST 24
Finished Jan 03 12:30:49 PM PST 24
Peak memory 211276 kb
Host smart-611db6af-8192-4370-b2e6-a1a08e7c341f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014952193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3014952193
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3047136889
Short name T454
Test name
Test status
Simulation time 399116325 ps
CPU time 41.06 seconds
Started Jan 03 12:24:30 PM PST 24
Finished Jan 03 12:25:17 PM PST 24
Peak memory 212280 kb
Host smart-ccbe53f3-f64f-40f7-9bbb-c3bbc7635b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047136889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3047136889
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3397933191
Short name T13
Test name
Test status
Simulation time 54635422708 ps
CPU time 7902.36 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 02:40:51 PM PST 24
Peak memory 234176 kb
Host smart-a99ac913-44c6-45e7-a334-ef4a019b9424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397933191 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3397933191
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.3255987634
Short name T134
Test name
Test status
Simulation time 332879539 ps
CPU time 4.43 seconds
Started Jan 03 12:29:05 PM PST 24
Finished Jan 03 12:29:36 PM PST 24
Peak memory 210048 kb
Host smart-cc0f24d5-6f24-43e4-a91f-ef30250637fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255987634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.3255987634
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.3939631635
Short name T105
Test name
Test status
Simulation time 883695927 ps
CPU time 87.5 seconds
Started Jan 03 12:23:43 PM PST 24
Finished Jan 03 12:25:11 PM PST 24
Peak memory 211648 kb
Host smart-70f12fe7-74b8-4ff7-b1eb-e1c717420df4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939631635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.3939631635
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.6410248
Short name T102
Test name
Test status
Simulation time 2048010768 ps
CPU time 75.6 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:31:01 PM PST 24
Peak memory 211196 kb
Host smart-b823d1f1-a91b-4b40-a114-8de491ecc24c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6410248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_intg
_err.6410248
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2074945280
Short name T96
Test name
Test status
Simulation time 48590627103 ps
CPU time 1699.17 seconds
Started Jan 03 12:45:22 PM PST 24
Finished Jan 03 01:15:13 PM PST 24
Peak memory 235468 kb
Host smart-b56d0c4e-9904-43d8-bd07-84f364c3a696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074945280 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2074945280
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.2548274102
Short name T83
Test name
Test status
Simulation time 208848195 ps
CPU time 5.52 seconds
Started Jan 03 12:30:38 PM PST 24
Finished Jan 03 12:31:46 PM PST 24
Peak memory 210884 kb
Host smart-fa731ae2-cdb3-4cf6-b5b4-fc86caa6c5b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548274102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.2548274102
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3341764624
Short name T57
Test name
Test status
Simulation time 85704764 ps
CPU time 6.35 seconds
Started Jan 03 12:34:45 PM PST 24
Finished Jan 03 12:36:07 PM PST 24
Peak memory 218692 kb
Host smart-401c3c21-e1e1-4dd8-845c-e0f78cff95c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341764624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3341764624
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3647020372
Short name T123
Test name
Test status
Simulation time 1381862592 ps
CPU time 4.38 seconds
Started Jan 03 12:27:40 PM PST 24
Finished Jan 03 12:27:49 PM PST 24
Peak memory 211032 kb
Host smart-c86544fd-2925-4675-ac50-b30d91b6055e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647020372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.3647020372
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2948793098
Short name T81
Test name
Test status
Simulation time 171606119 ps
CPU time 4.68 seconds
Started Jan 03 12:22:43 PM PST 24
Finished Jan 03 12:22:50 PM PST 24
Peak memory 211180 kb
Host smart-9e318616-8795-4f39-9280-43714824a8d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948793098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.2948793098
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1454760845
Short name T425
Test name
Test status
Simulation time 6173454053 ps
CPU time 14.31 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:30:46 PM PST 24
Peak memory 209576 kb
Host smart-9009f762-0941-429e-af96-dde9683714d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454760845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1454760845
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.3321325366
Short name T471
Test name
Test status
Simulation time 4320948868 ps
CPU time 10.54 seconds
Started Jan 03 12:27:25 PM PST 24
Finished Jan 03 12:27:42 PM PST 24
Peak memory 219080 kb
Host smart-84219b60-8701-4cd2-b82a-f7347019da21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321325366 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.3321325366
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.654509323
Short name T115
Test name
Test status
Simulation time 208757643 ps
CPU time 5.88 seconds
Started Jan 03 12:26:02 PM PST 24
Finished Jan 03 12:26:08 PM PST 24
Peak memory 211176 kb
Host smart-e39cdcee-0645-401a-aa5d-47f31d203c35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654509323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.654509323
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.3011012760
Short name T120
Test name
Test status
Simulation time 1886063577 ps
CPU time 15.27 seconds
Started Jan 03 12:25:48 PM PST 24
Finished Jan 03 12:26:04 PM PST 24
Peak memory 211180 kb
Host smart-daeaf715-4466-4326-8e05-20330d7239ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011012760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.3011012760
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1328077677
Short name T112
Test name
Test status
Simulation time 1694255439 ps
CPU time 13.67 seconds
Started Jan 03 12:27:22 PM PST 24
Finished Jan 03 12:27:40 PM PST 24
Peak memory 209748 kb
Host smart-6a67b625-a99c-4bf3-abaa-626f83f3bb76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328077677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1328077677
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3206534682
Short name T476
Test name
Test status
Simulation time 38803029198 ps
CPU time 363.57 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:37:21 PM PST 24
Peak memory 210828 kb
Host smart-0a06aa25-73f3-480e-806e-e2953237563c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206534682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3206534682
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.414906269
Short name T453
Test name
Test status
Simulation time 3139073232 ps
CPU time 8.96 seconds
Started Jan 03 12:30:10 PM PST 24
Finished Jan 03 12:31:05 PM PST 24
Peak memory 210892 kb
Host smart-f7c60121-3c47-4689-adcf-b238bb1902be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414906269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.414906269
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.663056143
Short name T75
Test name
Test status
Simulation time 4773210254 ps
CPU time 11.55 seconds
Started Jan 03 12:27:05 PM PST 24
Finished Jan 03 12:27:20 PM PST 24
Peak memory 209244 kb
Host smart-cf678c0e-c786-450f-9712-ca52bdbdec2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663056143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alias
ing.663056143
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3589228210
Short name T431
Test name
Test status
Simulation time 1420436121 ps
CPU time 8.84 seconds
Started Jan 03 12:24:09 PM PST 24
Finished Jan 03 12:24:22 PM PST 24
Peak memory 211024 kb
Host smart-100a0c50-7522-4f54-b8bd-2ce2a1922fb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589228210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3589228210
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.2909340983
Short name T446
Test name
Test status
Simulation time 1612188508 ps
CPU time 12.84 seconds
Started Jan 03 12:27:05 PM PST 24
Finished Jan 03 12:27:21 PM PST 24
Peak memory 209408 kb
Host smart-5854683f-cce9-4fb5-8c70-135e248cbcf5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909340983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.2909340983
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2407959694
Short name T124
Test name
Test status
Simulation time 428900119 ps
CPU time 7.79 seconds
Started Jan 03 12:28:15 PM PST 24
Finished Jan 03 12:28:30 PM PST 24
Peak memory 213932 kb
Host smart-b631f8e9-cac8-4468-a5fc-f56882344b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407959694 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2407959694
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3556414965
Short name T445
Test name
Test status
Simulation time 4145582898 ps
CPU time 16.4 seconds
Started Jan 03 12:27:05 PM PST 24
Finished Jan 03 12:27:25 PM PST 24
Peak memory 209592 kb
Host smart-e669786b-6234-4157-9fa8-9d284aa956a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556414965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3556414965
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2782253485
Short name T421
Test name
Test status
Simulation time 1772560321 ps
CPU time 8.55 seconds
Started Jan 03 12:27:26 PM PST 24
Finished Jan 03 12:27:40 PM PST 24
Peak memory 211092 kb
Host smart-9cf7165a-b455-4669-92da-56b144441596
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782253485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2782253485
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.986589563
Short name T122
Test name
Test status
Simulation time 333342808 ps
CPU time 4.25 seconds
Started Jan 03 12:24:57 PM PST 24
Finished Jan 03 12:25:02 PM PST 24
Peak memory 211168 kb
Host smart-6537b892-3cc1-45b5-85b6-905b0ef1b292
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986589563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk.
986589563
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3107079626
Short name T70
Test name
Test status
Simulation time 35983452727 ps
CPU time 102.3 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:29:12 PM PST 24
Peak memory 210756 kb
Host smart-bc91293f-3b7e-461c-829c-cdd33e158481
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107079626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3107079626
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.972863316
Short name T79
Test name
Test status
Simulation time 1448989473 ps
CPU time 12.28 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 209980 kb
Host smart-a4ddf7dc-86bf-4075-941d-0c274e423051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972863316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.972863316
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1229509062
Short name T29
Test name
Test status
Simulation time 8524868740 ps
CPU time 19.83 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:27:49 PM PST 24
Peak memory 218824 kb
Host smart-b0a857eb-c418-4fbc-a174-648b91440cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229509062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.1229509062
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2245808594
Short name T132
Test name
Test status
Simulation time 2453626499 ps
CPU time 11.59 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:28:06 PM PST 24
Peak memory 214768 kb
Host smart-ee1568f3-4e58-44ce-b508-fbe9100609ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245808594 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2245808594
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2860702679
Short name T63
Test name
Test status
Simulation time 6659938195 ps
CPU time 13.54 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:17 PM PST 24
Peak memory 211088 kb
Host smart-21139570-8b12-4747-9859-b6184c3b32cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860702679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2860702679
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3047887624
Short name T45
Test name
Test status
Simulation time 58022549044 ps
CPU time 193.98 seconds
Started Jan 03 12:29:56 PM PST 24
Finished Jan 03 12:33:53 PM PST 24
Peak memory 210896 kb
Host smart-bb99d797-14e3-4c1d-9fe6-37eb3cb4a104
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047887624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3047887624
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2723995950
Short name T433
Test name
Test status
Simulation time 129120234 ps
CPU time 4.98 seconds
Started Jan 03 12:27:51 PM PST 24
Finished Jan 03 12:28:00 PM PST 24
Peak memory 211096 kb
Host smart-db98ce49-beee-4e3e-849b-f8dcba0c4220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723995950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2723995950
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1544306918
Short name T55
Test name
Test status
Simulation time 13471752038 ps
CPU time 13.19 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:54 PM PST 24
Peak memory 219136 kb
Host smart-1020bdf9-8e21-4b8e-87c3-a6916dbcfbf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544306918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1544306918
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.172078106
Short name T56
Test name
Test status
Simulation time 2901463933 ps
CPU time 8.56 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:10 PM PST 24
Peak memory 211400 kb
Host smart-b9afb000-91bc-4f68-b697-f319911504ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172078106 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.172078106
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2354130477
Short name T424
Test name
Test status
Simulation time 487750946 ps
CPU time 4.4 seconds
Started Jan 03 12:28:33 PM PST 24
Finished Jan 03 12:28:55 PM PST 24
Peak memory 209324 kb
Host smart-d91948b0-b4d7-460a-bda5-5b6f31f951b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354130477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2354130477
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1071759095
Short name T119
Test name
Test status
Simulation time 7198607678 ps
CPU time 17.92 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:25 PM PST 24
Peak memory 217356 kb
Host smart-29a5bc4a-dc0b-4aaa-8422-b85cc01a8aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071759095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1071759095
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2499058817
Short name T58
Test name
Test status
Simulation time 512586104 ps
CPU time 43.7 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:44 PM PST 24
Peak memory 212304 kb
Host smart-ef9b83be-20ba-42b5-9b83-c78a4a34f392
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499058817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.2499058817
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3440981722
Short name T468
Test name
Test status
Simulation time 1992088990 ps
CPU time 10.54 seconds
Started Jan 03 12:27:39 PM PST 24
Finished Jan 03 12:27:54 PM PST 24
Peak memory 219116 kb
Host smart-9c61f223-445a-4534-a9bc-e39ecf31d67a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440981722 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3440981722
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1919918356
Short name T121
Test name
Test status
Simulation time 1958377118 ps
CPU time 14.85 seconds
Started Jan 03 12:38:55 PM PST 24
Finished Jan 03 12:40:18 PM PST 24
Peak memory 211144 kb
Host smart-23d2a24c-cf09-48d5-b4a4-6c931127c185
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919918356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1919918356
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.3375401507
Short name T460
Test name
Test status
Simulation time 17138147442 ps
CPU time 164.73 seconds
Started Jan 03 12:29:31 PM PST 24
Finished Jan 03 12:32:50 PM PST 24
Peak memory 209788 kb
Host smart-81cefa52-9542-404d-8522-6e0cf53cb2e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375401507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.3375401507
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.2192021562
Short name T86
Test name
Test status
Simulation time 1449060247 ps
CPU time 12.27 seconds
Started Jan 03 12:27:35 PM PST 24
Finished Jan 03 12:27:51 PM PST 24
Peak memory 211080 kb
Host smart-b0cecdd0-af47-4e33-9290-726b4227f364
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192021562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.2192021562
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2734712836
Short name T60
Test name
Test status
Simulation time 7501648687 ps
CPU time 17.08 seconds
Started Jan 03 12:28:36 PM PST 24
Finished Jan 03 12:29:08 PM PST 24
Peak memory 219328 kb
Host smart-656d6337-4b13-4f3e-ad4a-fbdf255b6595
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734712836 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2734712836
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.515213693
Short name T419
Test name
Test status
Simulation time 90839517 ps
CPU time 4.96 seconds
Started Jan 03 12:30:55 PM PST 24
Finished Jan 03 12:32:05 PM PST 24
Peak memory 214060 kb
Host smart-480c3b54-a17d-4cb4-aaaa-134714a33503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515213693 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.515213693
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2872919282
Short name T458
Test name
Test status
Simulation time 25051194111 ps
CPU time 17.14 seconds
Started Jan 03 12:25:29 PM PST 24
Finished Jan 03 12:25:47 PM PST 24
Peak memory 211364 kb
Host smart-94ed3a32-f16e-47b3-b4c8-8384ac905c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872919282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2872919282
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2358365273
Short name T71
Test name
Test status
Simulation time 4900554684 ps
CPU time 96.92 seconds
Started Jan 03 12:30:27 PM PST 24
Finished Jan 03 12:33:03 PM PST 24
Peak memory 210340 kb
Host smart-df2e011d-614d-4dd5-a8bb-6ab1ecb765fb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358365273 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2358365273
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.2724745200
Short name T452
Test name
Test status
Simulation time 387714444 ps
CPU time 6.44 seconds
Started Jan 03 12:23:38 PM PST 24
Finished Jan 03 12:23:45 PM PST 24
Peak memory 211100 kb
Host smart-7cdbeae8-e870-414b-9c33-d20a38776834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724745200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.2724745200
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.288705003
Short name T21
Test name
Test status
Simulation time 1792204584 ps
CPU time 10.28 seconds
Started Jan 03 12:30:59 PM PST 24
Finished Jan 03 12:32:17 PM PST 24
Peak memory 219048 kb
Host smart-fb6304c7-8b8c-4ff5-ae94-f2cd7878ce8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288705003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.288705003
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3961220689
Short name T447
Test name
Test status
Simulation time 3655831709 ps
CPU time 47.15 seconds
Started Jan 03 12:37:26 PM PST 24
Finished Jan 03 12:39:34 PM PST 24
Peak memory 212028 kb
Host smart-8d926e3a-bc29-42ce-a142-0763d84d14b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961220689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3961220689
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1336295712
Short name T109
Test name
Test status
Simulation time 1754699030 ps
CPU time 14.39 seconds
Started Jan 03 12:24:09 PM PST 24
Finished Jan 03 12:24:28 PM PST 24
Peak memory 215112 kb
Host smart-1ecf7fb0-51a6-440c-b6af-158a95c276c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336295712 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1336295712
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.4084195873
Short name T67
Test name
Test status
Simulation time 1028557646 ps
CPU time 52.09 seconds
Started Jan 03 12:30:38 PM PST 24
Finished Jan 03 12:32:33 PM PST 24
Peak memory 210864 kb
Host smart-0cbd444a-a062-4e7f-9455-30ed3f9a5e9a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084195873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.4084195873
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3937993859
Short name T473
Test name
Test status
Simulation time 3973828834 ps
CPU time 10.4 seconds
Started Jan 03 12:22:44 PM PST 24
Finished Jan 03 12:22:57 PM PST 24
Peak memory 211128 kb
Host smart-217bc469-909d-4587-b2d3-9e284f282800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937993859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3937993859
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.5029197
Short name T439
Test name
Test status
Simulation time 3344093350 ps
CPU time 17.27 seconds
Started Jan 03 12:22:45 PM PST 24
Finished Jan 03 12:23:04 PM PST 24
Peak memory 219328 kb
Host smart-7992e1ec-ebe4-4e81-9f0a-014007ec728f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5029197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.5029197
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1389822382
Short name T438
Test name
Test status
Simulation time 569514691 ps
CPU time 76.72 seconds
Started Jan 03 12:27:26 PM PST 24
Finished Jan 03 12:28:49 PM PST 24
Peak memory 211404 kb
Host smart-59f94966-7911-4eb8-a113-7cc48da283a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389822382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.1389822382
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.3948134357
Short name T475
Test name
Test status
Simulation time 5647209391 ps
CPU time 10.36 seconds
Started Jan 03 12:28:17 PM PST 24
Finished Jan 03 12:28:36 PM PST 24
Peak memory 214628 kb
Host smart-25b2a02e-6176-4b45-87d9-52e552793993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948134357 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.3948134357
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.769752568
Short name T464
Test name
Test status
Simulation time 24596043021 ps
CPU time 11.65 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:30:04 PM PST 24
Peak memory 209384 kb
Host smart-bea21546-1f74-4952-bc5e-54a929d0c486
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769752568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.769752568
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.696876237
Short name T85
Test name
Test status
Simulation time 4058123871 ps
CPU time 50.94 seconds
Started Jan 03 12:30:39 PM PST 24
Finished Jan 03 12:32:32 PM PST 24
Peak memory 210920 kb
Host smart-251143fa-e5d7-4807-9b77-cb42409d0390
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696876237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.696876237
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.570280253
Short name T125
Test name
Test status
Simulation time 377310703 ps
CPU time 7.27 seconds
Started Jan 03 12:24:51 PM PST 24
Finished Jan 03 12:25:00 PM PST 24
Peak memory 211080 kb
Host smart-fb01f0b5-52a4-48c9-94c3-9bb32fd0d238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570280253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.570280253
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.290271978
Short name T440
Test name
Test status
Simulation time 669620790 ps
CPU time 9.65 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:52 PM PST 24
Peak memory 218624 kb
Host smart-b853add4-bed5-433e-a5c6-8048268d5b43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290271978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.290271978
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1264048820
Short name T78
Test name
Test status
Simulation time 1613189033 ps
CPU time 47.23 seconds
Started Jan 03 12:29:22 PM PST 24
Finished Jan 03 12:30:40 PM PST 24
Peak memory 211908 kb
Host smart-628c3771-e032-4ba3-841e-d92fe8a9fb44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264048820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.1264048820
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1006355535
Short name T448
Test name
Test status
Simulation time 387757097 ps
CPU time 5.44 seconds
Started Jan 03 12:24:02 PM PST 24
Finished Jan 03 12:24:15 PM PST 24
Peak memory 215364 kb
Host smart-77c248d3-3b1f-4260-b6b1-9edcb304f95c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006355535 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1006355535
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2763790877
Short name T73
Test name
Test status
Simulation time 1461778941 ps
CPU time 12.55 seconds
Started Jan 03 12:28:37 PM PST 24
Finished Jan 03 12:29:04 PM PST 24
Peak memory 211080 kb
Host smart-ad9f9b0f-8e9c-414d-9e8d-d442c4c5f352
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763790877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2763790877
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3279885139
Short name T44
Test name
Test status
Simulation time 38127135635 ps
CPU time 326.67 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:34:43 PM PST 24
Peak memory 210204 kb
Host smart-a3a6090d-1c67-426f-9a32-1d7ade29bc97
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279885139 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3279885139
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.1874361353
Short name T131
Test name
Test status
Simulation time 851888837 ps
CPU time 9.49 seconds
Started Jan 03 12:29:03 PM PST 24
Finished Jan 03 12:29:39 PM PST 24
Peak memory 210260 kb
Host smart-846b5ae4-2268-45e9-b9c1-e7a1c99f2fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874361353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.1874361353
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.759277858
Short name T462
Test name
Test status
Simulation time 1363979517 ps
CPU time 15.09 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:56 PM PST 24
Peak memory 218896 kb
Host smart-010b4f64-8cc9-4337-a263-b33acd8cc215
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759277858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.759277858
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.908121318
Short name T80
Test name
Test status
Simulation time 7295755783 ps
CPU time 15.32 seconds
Started Jan 03 12:30:01 PM PST 24
Finished Jan 03 12:31:01 PM PST 24
Peak memory 219140 kb
Host smart-196ea23a-c306-496f-89c1-c963938c6a7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908121318 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.908121318
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3675572647
Short name T89
Test name
Test status
Simulation time 1062150800 ps
CPU time 7.66 seconds
Started Jan 03 12:24:02 PM PST 24
Finished Jan 03 12:24:18 PM PST 24
Peak memory 211284 kb
Host smart-4cf71178-b384-4813-b819-aa5415e46b82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675572647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3675572647
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.659583757
Short name T451
Test name
Test status
Simulation time 2600748639 ps
CPU time 9.96 seconds
Started Jan 03 12:26:27 PM PST 24
Finished Jan 03 12:26:38 PM PST 24
Peak memory 211184 kb
Host smart-c540392a-480a-403b-8940-1de451ebcf4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659583757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.659583757
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.904903147
Short name T101
Test name
Test status
Simulation time 1707451024 ps
CPU time 75.82 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:30:32 PM PST 24
Peak memory 211152 kb
Host smart-9953db10-e343-49ad-bfd0-3243f798305a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904903147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.904903147
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.435724151
Short name T127
Test name
Test status
Simulation time 3859566487 ps
CPU time 15.49 seconds
Started Jan 03 12:28:43 PM PST 24
Finished Jan 03 12:29:25 PM PST 24
Peak memory 213972 kb
Host smart-36b63a63-307c-4502-abd2-a168d3bdd309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435724151 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.435724151
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.457353561
Short name T444
Test name
Test status
Simulation time 690997045 ps
CPU time 4.21 seconds
Started Jan 03 12:28:16 PM PST 24
Finished Jan 03 12:28:29 PM PST 24
Peak memory 210284 kb
Host smart-62223061-12fd-4c1c-96ed-53432514c866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457353561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.457353561
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1935843392
Short name T467
Test name
Test status
Simulation time 1034204957 ps
CPU time 52.36 seconds
Started Jan 03 12:27:19 PM PST 24
Finished Jan 03 12:28:15 PM PST 24
Peak memory 210816 kb
Host smart-679438ed-c8d1-4f11-b450-6618c0825ee5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935843392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1935843392
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.3630012204
Short name T26
Test name
Test status
Simulation time 5133096701 ps
CPU time 11.45 seconds
Started Jan 03 12:28:44 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 211168 kb
Host smart-8d4599e2-4a4e-4c3d-b27a-94ac84dae728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630012204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.3630012204
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1694555660
Short name T443
Test name
Test status
Simulation time 16448318529 ps
CPU time 18.98 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 219140 kb
Host smart-1e9f26ba-be9c-49e6-b5b3-32aa4188efcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694555660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1694555660
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.775047339
Short name T98
Test name
Test status
Simulation time 1094173060 ps
CPU time 44.13 seconds
Started Jan 03 12:29:06 PM PST 24
Finished Jan 03 12:30:17 PM PST 24
Peak memory 211356 kb
Host smart-a6184641-3f4e-4785-b875-9ddd1715295e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775047339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.775047339
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.2237468598
Short name T118
Test name
Test status
Simulation time 195882990 ps
CPU time 4.72 seconds
Started Jan 03 12:30:53 PM PST 24
Finished Jan 03 12:32:03 PM PST 24
Peak memory 213352 kb
Host smart-4451e0d5-d893-440a-8c2a-ddc4e798a075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237468598 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.2237468598
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2011919313
Short name T77
Test name
Test status
Simulation time 171202246 ps
CPU time 4.22 seconds
Started Jan 03 12:27:39 PM PST 24
Finished Jan 03 12:27:48 PM PST 24
Peak memory 210888 kb
Host smart-a929cc26-b873-41a0-a604-51ee17befb76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011919313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2011919313
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2777539937
Short name T432
Test name
Test status
Simulation time 2352837664 ps
CPU time 66.49 seconds
Started Jan 03 12:27:16 PM PST 24
Finished Jan 03 12:28:24 PM PST 24
Peak memory 210900 kb
Host smart-e591456e-7912-4bc9-871b-291dbec834ca
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777539937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.2777539937
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.612892669
Short name T434
Test name
Test status
Simulation time 85756015 ps
CPU time 4.4 seconds
Started Jan 03 12:27:19 PM PST 24
Finished Jan 03 12:27:27 PM PST 24
Peak memory 209388 kb
Host smart-23fef8e5-9a9f-4512-bf98-274369fc3bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612892669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_c
trl_same_csr_outstanding.612892669
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2353855035
Short name T95
Test name
Test status
Simulation time 476191695 ps
CPU time 8.83 seconds
Started Jan 03 12:27:17 PM PST 24
Finished Jan 03 12:27:28 PM PST 24
Peak memory 219040 kb
Host smart-c4cd7f87-2e22-449c-9bd5-6fc6c232a715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353855035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2353855035
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.2479392221
Short name T103
Test name
Test status
Simulation time 2528651394 ps
CPU time 41.42 seconds
Started Jan 03 12:28:57 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 211996 kb
Host smart-3004527a-c817-43cc-a819-08dc18d111ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479392221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.2479392221
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.2379112170
Short name T469
Test name
Test status
Simulation time 1529633612 ps
CPU time 8.69 seconds
Started Jan 03 12:29:14 PM PST 24
Finished Jan 03 12:29:50 PM PST 24
Peak memory 210856 kb
Host smart-a2a4fd75-0aee-420f-9dac-f3165c37da52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379112170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.2379112170
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1119498685
Short name T470
Test name
Test status
Simulation time 6188152491 ps
CPU time 15.73 seconds
Started Jan 03 12:30:50 PM PST 24
Finished Jan 03 12:32:12 PM PST 24
Peak memory 210936 kb
Host smart-10e56efa-1c13-4de6-bd4e-fb29e2c5ff0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119498685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1119498685
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2650925046
Short name T76
Test name
Test status
Simulation time 6115012576 ps
CPU time 17.17 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 210940 kb
Host smart-2e4e6987-10dc-4e14-851e-50ffcb043c9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650925046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2650925046
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.4248840632
Short name T107
Test name
Test status
Simulation time 2029854952 ps
CPU time 16.88 seconds
Started Jan 03 12:28:32 PM PST 24
Finished Jan 03 12:29:03 PM PST 24
Peak memory 215588 kb
Host smart-be622b03-08c5-491f-8876-3beaae119414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248840632 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.4248840632
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2696556013
Short name T435
Test name
Test status
Simulation time 976199208 ps
CPU time 10.19 seconds
Started Jan 03 12:28:13 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 210096 kb
Host smart-1b74da0b-19e1-4d9a-b580-a42058e6e694
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696556013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2696556013
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2822174078
Short name T113
Test name
Test status
Simulation time 766192598 ps
CPU time 8.26 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:29:52 PM PST 24
Peak memory 210852 kb
Host smart-be6ab9bc-384b-4089-ac4a-3be175557101
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822174078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2822174078
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.547312623
Short name T130
Test name
Test status
Simulation time 347423667 ps
CPU time 4.31 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:39 PM PST 24
Peak memory 210032 kb
Host smart-5dcd666c-e78c-440a-bb44-88c93e6860cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547312623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
547312623
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.26753955
Short name T427
Test name
Test status
Simulation time 13824563335 ps
CPU time 50.06 seconds
Started Jan 03 12:29:22 PM PST 24
Finished Jan 03 12:30:44 PM PST 24
Peak memory 210760 kb
Host smart-682123ed-f0ab-42f0-b6d5-b616ce287663
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26753955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.26753955
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1905671258
Short name T428
Test name
Test status
Simulation time 9189725243 ps
CPU time 15.65 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:29:06 PM PST 24
Peak memory 210988 kb
Host smart-b0341658-2b9c-4ba7-8fd9-e3d127756f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905671258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1905671258
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2915107846
Short name T442
Test name
Test status
Simulation time 2046786173 ps
CPU time 9.48 seconds
Started Jan 03 12:29:02 PM PST 24
Finished Jan 03 12:29:38 PM PST 24
Peak memory 214668 kb
Host smart-7f5f000e-69b4-4268-b9c7-30dc30d7e07a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915107846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2915107846
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.481960295
Short name T61
Test name
Test status
Simulation time 1549611542 ps
CPU time 76.52 seconds
Started Jan 03 12:29:02 PM PST 24
Finished Jan 03 12:30:45 PM PST 24
Peak memory 212188 kb
Host smart-8e84a38b-4c49-46f5-a7ac-15ce2da31d14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481960295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_int
g_err.481960295
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1826871126
Short name T465
Test name
Test status
Simulation time 1863099574 ps
CPU time 14.96 seconds
Started Jan 03 12:29:09 PM PST 24
Finished Jan 03 12:29:51 PM PST 24
Peak memory 210764 kb
Host smart-42fc80c4-c509-42c8-881e-263bd3ea57b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826871126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1826871126
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2016397761
Short name T466
Test name
Test status
Simulation time 7320391406 ps
CPU time 15.32 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:16 PM PST 24
Peak memory 211044 kb
Host smart-8ecd4e7f-7f22-4041-a46c-c033db866e77
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016397761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2016397761
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2512502033
Short name T84
Test name
Test status
Simulation time 1553728833 ps
CPU time 14.83 seconds
Started Jan 03 12:28:56 PM PST 24
Finished Jan 03 12:29:38 PM PST 24
Peak memory 210852 kb
Host smart-fd9d479c-c051-4995-8a7e-8f62cf0875ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512502033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2512502033
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2691631412
Short name T429
Test name
Test status
Simulation time 87162797 ps
CPU time 4.42 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:29:12 PM PST 24
Peak memory 208776 kb
Host smart-97339f85-4ba8-408f-80f7-1ee675504b9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691631412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2691631412
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3357508777
Short name T450
Test name
Test status
Simulation time 1568214078 ps
CPU time 8.79 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:15 PM PST 24
Peak memory 210716 kb
Host smart-67f0c817-cb83-4b7a-b762-7f1de79dfd05
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357508777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3357508777
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2497513735
Short name T129
Test name
Test status
Simulation time 10529875905 ps
CPU time 14.05 seconds
Started Jan 03 12:27:19 PM PST 24
Finished Jan 03 12:27:37 PM PST 24
Peak memory 210856 kb
Host smart-2144a058-4187-4a65-b10c-2749f492d98f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497513735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.2497513735
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3493718607
Short name T69
Test name
Test status
Simulation time 10318516965 ps
CPU time 110.85 seconds
Started Jan 03 12:28:15 PM PST 24
Finished Jan 03 12:30:12 PM PST 24
Peak memory 210236 kb
Host smart-be226112-03b1-44bf-8514-c5e66a74ec6d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493718607 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3493718607
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1659610371
Short name T133
Test name
Test status
Simulation time 753639961 ps
CPU time 4.38 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:40 PM PST 24
Peak memory 210728 kb
Host smart-3f5fc614-8dd8-4f79-9689-ab7478aa7cd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659610371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1659610371
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3491183809
Short name T463
Test name
Test status
Simulation time 1147968462 ps
CPU time 13.55 seconds
Started Jan 03 12:27:19 PM PST 24
Finished Jan 03 12:27:36 PM PST 24
Peak memory 219004 kb
Host smart-f4676c32-547e-4e38-b202-4fb756e781ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491183809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3491183809
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3908705896
Short name T441
Test name
Test status
Simulation time 1489675365 ps
CPU time 46.82 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:31:28 PM PST 24
Peak memory 211668 kb
Host smart-121cf643-f21e-46d0-919e-b643432ab511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908705896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.3908705896
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2211054319
Short name T461
Test name
Test status
Simulation time 1473035941 ps
CPU time 13.29 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:38:02 PM PST 24
Peak memory 211192 kb
Host smart-ecb8cfa0-fedd-411c-aa62-7135cd9d5a43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211054319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2211054319
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3406301796
Short name T472
Test name
Test status
Simulation time 5447087488 ps
CPU time 11.79 seconds
Started Jan 03 12:27:20 PM PST 24
Finished Jan 03 12:27:35 PM PST 24
Peak memory 209732 kb
Host smart-a680680e-d526-4344-9c69-a7d3d516f54a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406301796 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3406301796
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.3945737737
Short name T423
Test name
Test status
Simulation time 92171555 ps
CPU time 5.9 seconds
Started Jan 03 12:28:43 PM PST 24
Finished Jan 03 12:29:14 PM PST 24
Peak memory 210628 kb
Host smart-18e156fd-1c51-4449-82dd-1b0b8723b93e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945737737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.3945737737
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.575115625
Short name T426
Test name
Test status
Simulation time 8072523031 ps
CPU time 15.4 seconds
Started Jan 03 12:27:19 PM PST 24
Finished Jan 03 12:27:38 PM PST 24
Peak memory 217492 kb
Host smart-f6ea3745-8ad5-458a-88f4-07b8f96dbba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575115625 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.575115625
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2581816608
Short name T459
Test name
Test status
Simulation time 38664211376 ps
CPU time 16.1 seconds
Started Jan 03 12:30:54 PM PST 24
Finished Jan 03 12:32:15 PM PST 24
Peak memory 210824 kb
Host smart-450f4d07-416d-4f22-a32a-27578c53e01c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581816608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.2581816608
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.345813140
Short name T114
Test name
Test status
Simulation time 19774960612 ps
CPU time 13.61 seconds
Started Jan 03 12:29:55 PM PST 24
Finished Jan 03 12:30:52 PM PST 24
Peak memory 209560 kb
Host smart-776cfb12-8282-49c2-8577-34995d174b51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345813140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl
_mem_partial_access.345813140
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1657146223
Short name T116
Test name
Test status
Simulation time 622760479 ps
CPU time 7.3 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:14 PM PST 24
Peak memory 210704 kb
Host smart-a42edb40-8b8a-41ba-b138-121e16105921
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657146223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1657146223
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.2586986500
Short name T65
Test name
Test status
Simulation time 25178618990 ps
CPU time 250.36 seconds
Started Jan 03 12:23:11 PM PST 24
Finished Jan 03 12:27:22 PM PST 24
Peak memory 211228 kb
Host smart-9e8cda2f-5c88-4cac-bdd1-08e75608a927
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586986500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.2586986500
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.734359253
Short name T64
Test name
Test status
Simulation time 424319535 ps
CPU time 6.13 seconds
Started Jan 03 12:41:46 PM PST 24
Finished Jan 03 12:43:16 PM PST 24
Peak memory 211052 kb
Host smart-dfe7ea92-38bd-4ce7-9640-22a3ef7731ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734359253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.734359253
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1971024778
Short name T97
Test name
Test status
Simulation time 184500903 ps
CPU time 40 seconds
Started Jan 03 12:29:09 PM PST 24
Finished Jan 03 12:30:16 PM PST 24
Peak memory 211952 kb
Host smart-685fdc8c-a667-4e10-985e-69bfb90740e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971024778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1971024778
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3583884306
Short name T456
Test name
Test status
Simulation time 1115452815 ps
CPU time 11.45 seconds
Started Jan 03 12:27:26 PM PST 24
Finished Jan 03 12:27:43 PM PST 24
Peak memory 214176 kb
Host smart-ca41bd7c-2023-4afb-a18c-571152f5b671
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583884306 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3583884306
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2306654407
Short name T422
Test name
Test status
Simulation time 4114864807 ps
CPU time 7.42 seconds
Started Jan 03 12:24:51 PM PST 24
Finished Jan 03 12:25:00 PM PST 24
Peak memory 211148 kb
Host smart-fe7d2873-36a2-4790-9d42-6a6736b15762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306654407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2306654407
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.543855724
Short name T474
Test name
Test status
Simulation time 98910924176 ps
CPU time 153.22 seconds
Started Jan 03 12:27:20 PM PST 24
Finished Jan 03 12:29:56 PM PST 24
Peak memory 209952 kb
Host smart-7075e344-91e2-4db5-b0eb-3af221c6dda4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543855724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.543855724
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.641162083
Short name T128
Test name
Test status
Simulation time 5152751839 ps
CPU time 13.47 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:31 PM PST 24
Peak memory 210892 kb
Host smart-5631b277-46de-45bd-9b29-5af6920b1ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641162083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ct
rl_same_csr_outstanding.641162083
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3756570123
Short name T27
Test name
Test status
Simulation time 6851955685 ps
CPU time 16.96 seconds
Started Jan 03 12:30:35 PM PST 24
Finished Jan 03 12:31:53 PM PST 24
Peak memory 218660 kb
Host smart-d50e132e-b5ab-415e-9d91-25d9da8a0c52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756570123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.3756570123
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3387096971
Short name T100
Test name
Test status
Simulation time 578560918 ps
CPU time 75.3 seconds
Started Jan 03 12:27:58 PM PST 24
Finished Jan 03 12:29:24 PM PST 24
Peak memory 210928 kb
Host smart-686eca71-6445-4431-88b7-2cf49ffb288a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387096971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3387096971
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3217420655
Short name T117
Test name
Test status
Simulation time 15460243746 ps
CPU time 10.99 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:50 PM PST 24
Peak memory 215380 kb
Host smart-dc900678-fc3e-4cd7-9480-da48c955bfc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217420655 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3217420655
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3753558793
Short name T72
Test name
Test status
Simulation time 8186610051 ps
CPU time 16.28 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:55 PM PST 24
Peak memory 210940 kb
Host smart-82f7ba53-fc56-4842-996d-85adf729e88c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753558793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3753558793
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.2575614428
Short name T68
Test name
Test status
Simulation time 8825988895 ps
CPU time 49.31 seconds
Started Jan 03 12:30:52 PM PST 24
Finished Jan 03 12:32:47 PM PST 24
Peak memory 210800 kb
Host smart-398e20e9-d55a-4719-975d-ad2f1f8a890e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575614428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.2575614428
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.499662392
Short name T90
Test name
Test status
Simulation time 235143289 ps
CPU time 5.59 seconds
Started Jan 03 12:30:39 PM PST 24
Finished Jan 03 12:31:47 PM PST 24
Peak memory 210884 kb
Host smart-60527b51-4018-45d0-908d-fbb20682ee6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499662392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.499662392
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2552646759
Short name T449
Test name
Test status
Simulation time 488864195 ps
CPU time 6.38 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:31:00 PM PST 24
Peak memory 218412 kb
Host smart-e383629f-d7c0-431d-9718-c5e28a8306d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552646759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2552646759
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3775417918
Short name T111
Test name
Test status
Simulation time 219379569 ps
CPU time 6.01 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:50 PM PST 24
Peak memory 214248 kb
Host smart-8b248e85-f022-4ef5-adfa-ddfdbd46c32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775417918 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3775417918
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1041428934
Short name T25
Test name
Test status
Simulation time 3501016314 ps
CPU time 10.03 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 210904 kb
Host smart-9e7810f8-05c2-43e0-b732-990de89c590c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041428934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1041428934
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2540141666
Short name T436
Test name
Test status
Simulation time 63809843844 ps
CPU time 331.5 seconds
Started Jan 03 12:27:05 PM PST 24
Finished Jan 03 12:32:40 PM PST 24
Peak memory 209560 kb
Host smart-878f4eaa-9943-484d-b68f-f64612d996c1
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540141666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2540141666
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.487772444
Short name T22
Test name
Test status
Simulation time 1439661041 ps
CPU time 9.88 seconds
Started Jan 03 12:28:18 PM PST 24
Finished Jan 03 12:28:37 PM PST 24
Peak memory 211100 kb
Host smart-ef575750-a0e7-49e4-a4b6-b00c23939a31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487772444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ct
rl_same_csr_outstanding.487772444
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1239590327
Short name T110
Test name
Test status
Simulation time 4550248321 ps
CPU time 13.16 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:29:30 PM PST 24
Peak memory 218760 kb
Host smart-a9f345a1-4c3d-42c4-9eac-dfa4c2a921c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239590327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1239590327
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.771215526
Short name T28
Test name
Test status
Simulation time 852088266 ps
CPU time 74.27 seconds
Started Jan 03 12:30:13 PM PST 24
Finished Jan 03 12:32:15 PM PST 24
Peak memory 210132 kb
Host smart-f3e50b9a-55f0-4d0a-b112-45e8e85a8a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771215526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.771215526
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3942092180
Short name T437
Test name
Test status
Simulation time 12465319620 ps
CPU time 13.79 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:57 PM PST 24
Peak memory 214292 kb
Host smart-0b50a143-7ec7-4fcb-b284-0927d1c13517
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942092180 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3942092180
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.1320989164
Short name T457
Test name
Test status
Simulation time 3241433958 ps
CPU time 8.94 seconds
Started Jan 03 12:24:45 PM PST 24
Finished Jan 03 12:24:57 PM PST 24
Peak memory 211204 kb
Host smart-14b322af-0418-4120-a1d9-4aa06a9a1581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320989164 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.1320989164
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2487056584
Short name T74
Test name
Test status
Simulation time 179450301946 ps
CPU time 254.72 seconds
Started Jan 03 12:30:29 PM PST 24
Finished Jan 03 12:35:43 PM PST 24
Peak memory 210872 kb
Host smart-dc7786b7-fa2a-44f2-993f-4be718c415e5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487056584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2487056584
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2032725228
Short name T62
Test name
Test status
Simulation time 1440001132 ps
CPU time 14.22 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:49 PM PST 24
Peak memory 210692 kb
Host smart-341292cf-bb8c-4f95-9d65-744e53bc855d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032725228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2032725228
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2079385098
Short name T24
Test name
Test status
Simulation time 149179063 ps
CPU time 9.23 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:30:50 PM PST 24
Peak memory 213536 kb
Host smart-976699da-aad3-4f32-bd0a-ac4a716f4c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079385098 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2079385098
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.801127012
Short name T455
Test name
Test status
Simulation time 3569460860 ps
CPU time 44.22 seconds
Started Jan 03 12:28:28 PM PST 24
Finished Jan 03 12:29:25 PM PST 24
Peak memory 212308 kb
Host smart-899afdb6-afb7-4c94-8367-f0198349fa1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801127012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_int
g_err.801127012
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.843158451
Short name T46
Test name
Test status
Simulation time 1894906661 ps
CPU time 14.96 seconds
Started Jan 03 12:28:33 PM PST 24
Finished Jan 03 12:29:05 PM PST 24
Peak memory 215660 kb
Host smart-e19d0023-60c4-4778-8b9c-c45a9c21eabe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843158451 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.843158451
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.2134075271
Short name T82
Test name
Test status
Simulation time 1989069131 ps
CPU time 15.29 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 210860 kb
Host smart-f99d45d0-62ed-4f58-874a-62b2dce920ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134075271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.2134075271
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2056617290
Short name T66
Test name
Test status
Simulation time 97791381483 ps
CPU time 249.97 seconds
Started Jan 03 12:28:31 PM PST 24
Finished Jan 03 12:32:55 PM PST 24
Peak memory 210844 kb
Host smart-09ec5505-bf8f-4e04-81ec-acdb43fe01a9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056617290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2056617290
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.156643198
Short name T420
Test name
Test status
Simulation time 1152650761 ps
CPU time 11.16 seconds
Started Jan 03 12:26:05 PM PST 24
Finished Jan 03 12:26:17 PM PST 24
Peak memory 211192 kb
Host smart-51137512-68b7-47e2-a0f4-a4b9b546a84a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156643198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.156643198
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3780040339
Short name T126
Test name
Test status
Simulation time 1729415635 ps
CPU time 8.86 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:28:59 PM PST 24
Peak memory 219300 kb
Host smart-655406b7-e0ab-4067-ba15-2aad5cf0ea33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780040339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3780040339
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.2782192196
Short name T430
Test name
Test status
Simulation time 1528186895 ps
CPU time 45.16 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:30:39 PM PST 24
Peak memory 211744 kb
Host smart-c61173d0-aea9-4867-a300-702bcd8e3a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782192196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.2782192196
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2306987476
Short name T187
Test name
Test status
Simulation time 6066876661 ps
CPU time 8.34 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:15 PM PST 24
Peak memory 210408 kb
Host smart-0389a098-cf62-4288-ad47-0e330b453825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306987476 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2306987476
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1596747842
Short name T232
Test name
Test status
Simulation time 51772482073 ps
CPU time 494.53 seconds
Started Jan 03 12:28:42 PM PST 24
Finished Jan 03 12:37:23 PM PST 24
Peak memory 226940 kb
Host smart-6889e0e3-9d9e-4d25-acc8-01e33b83f56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596747842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1596747842
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3579785967
Short name T230
Test name
Test status
Simulation time 3689296455 ps
CPU time 31.37 seconds
Started Jan 03 12:27:23 PM PST 24
Finished Jan 03 12:28:00 PM PST 24
Peak memory 209700 kb
Host smart-e397c9c0-0dc8-4e98-8793-b6ac95499ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579785967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3579785967
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2425872938
Short name T348
Test name
Test status
Simulation time 5289557412 ps
CPU time 12.71 seconds
Started Jan 03 12:30:09 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 210528 kb
Host smart-fd7f374d-79d3-4260-b080-c220ba467d3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425872938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2425872938
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1891061409
Short name T40
Test name
Test status
Simulation time 889198986 ps
CPU time 63.02 seconds
Started Jan 03 12:27:23 PM PST 24
Finished Jan 03 12:28:31 PM PST 24
Peak memory 235644 kb
Host smart-eb588c58-3a0e-41dd-b14b-f6de4947ddd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891061409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1891061409
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3105855142
Short name T193
Test name
Test status
Simulation time 12525561708 ps
CPU time 28.57 seconds
Started Jan 03 12:29:31 PM PST 24
Finished Jan 03 12:30:33 PM PST 24
Peak memory 211996 kb
Host smart-ab0388fc-c1b3-4a79-b905-58d696afb823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105855142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3105855142
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.470814832
Short name T355
Test name
Test status
Simulation time 379236673 ps
CPU time 10.35 seconds
Started Jan 03 12:29:09 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 210396 kb
Host smart-2cf48567-b68b-403d-8a16-5a057dde597c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470814832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.rom_ctrl_stress_all.470814832
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.1837923843
Short name T324
Test name
Test status
Simulation time 346421735 ps
CPU time 4.29 seconds
Started Jan 03 12:29:19 PM PST 24
Finished Jan 03 12:29:52 PM PST 24
Peak memory 210460 kb
Host smart-dfcbf7a7-1cbf-4d1a-aadf-b2bf0b249556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837923843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.1837923843
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3468357130
Short name T286
Test name
Test status
Simulation time 22413446959 ps
CPU time 33.19 seconds
Started Jan 03 12:29:17 PM PST 24
Finished Jan 03 12:30:18 PM PST 24
Peak memory 211828 kb
Host smart-64f99442-0fc1-42cf-831c-e3ce8528be34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468357130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3468357130
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2608584344
Short name T404
Test name
Test status
Simulation time 4137103803 ps
CPU time 16.03 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 209508 kb
Host smart-11eb8292-f547-41bf-adc1-1bb33aad9aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2608584344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2608584344
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.319941733
Short name T309
Test name
Test status
Simulation time 4128591174 ps
CPU time 32.55 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:28:02 PM PST 24
Peak memory 211908 kb
Host smart-ce058ee3-e11c-40e1-8c59-b98542ee0d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319941733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.319941733
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.304381436
Short name T306
Test name
Test status
Simulation time 2919430540 ps
CPU time 15.89 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:30:10 PM PST 24
Peak memory 212472 kb
Host smart-77e33792-4220-4569-8498-4229e56fd763
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304381436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.304381436
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2477762337
Short name T190
Test name
Test status
Simulation time 41634624085 ps
CPU time 537.82 seconds
Started Jan 03 12:28:19 PM PST 24
Finished Jan 03 12:37:26 PM PST 24
Peak memory 222204 kb
Host smart-7734ed11-fce7-4fc5-bd03-5b43d53157b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477762337 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2477762337
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.52366255
Short name T135
Test name
Test status
Simulation time 493379128 ps
CPU time 5.63 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:41 PM PST 24
Peak memory 210328 kb
Host smart-dea47d2d-d5f9-489c-9475-cadaa666d354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52366255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.52366255
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1452071889
Short name T334
Test name
Test status
Simulation time 74008873282 ps
CPU time 392.18 seconds
Started Jan 03 12:22:56 PM PST 24
Finished Jan 03 12:29:29 PM PST 24
Peak memory 212136 kb
Host smart-d7f59aeb-3292-4929-8887-c8632a509925
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452071889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1452071889
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.4153534711
Short name T401
Test name
Test status
Simulation time 173877861 ps
CPU time 9.36 seconds
Started Jan 03 12:38:49 PM PST 24
Finished Jan 03 12:40:16 PM PST 24
Peak memory 211272 kb
Host smart-43ce8e75-030f-4378-9a96-d5765a6d2240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153534711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.4153534711
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4260125042
Short name T245
Test name
Test status
Simulation time 1985622891 ps
CPU time 16.65 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:30:00 PM PST 24
Peak memory 209464 kb
Host smart-564c3e3a-dd1a-48cb-903c-10e09c002356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260125042 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4260125042
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2295020314
Short name T360
Test name
Test status
Simulation time 1066187648 ps
CPU time 11.99 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:30:02 PM PST 24
Peak memory 212104 kb
Host smart-8d1fc7e1-fa07-4224-8b10-fe5bd79ba6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295020314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2295020314
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1358683140
Short name T144
Test name
Test status
Simulation time 123105155 ps
CPU time 8 seconds
Started Jan 03 12:25:55 PM PST 24
Finished Jan 03 12:26:03 PM PST 24
Peak memory 210696 kb
Host smart-60053ce9-af60-4a70-a8d5-973afe0d1d84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358683140 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1358683140
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.818014133
Short name T359
Test name
Test status
Simulation time 2046725069 ps
CPU time 16.59 seconds
Started Jan 03 12:29:50 PM PST 24
Finished Jan 03 12:30:48 PM PST 24
Peak memory 210584 kb
Host smart-e19da0a0-1679-4479-8f2e-4438823c943d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818014133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.818014133
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1032172219
Short name T226
Test name
Test status
Simulation time 86085518559 ps
CPU time 172.95 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:32:14 PM PST 24
Peak memory 223052 kb
Host smart-f8e659f2-6ffb-4260-a8b8-73b11e560ce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032172219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.1032172219
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.1656429808
Short name T383
Test name
Test status
Simulation time 722953259 ps
CPU time 10.33 seconds
Started Jan 03 12:23:18 PM PST 24
Finished Jan 03 12:23:29 PM PST 24
Peak memory 210856 kb
Host smart-60ccefa5-61e3-4a05-8600-1cba6903c249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656429808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.1656429808
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.3994138487
Short name T141
Test name
Test status
Simulation time 790410426 ps
CPU time 10.17 seconds
Started Jan 03 12:29:33 PM PST 24
Finished Jan 03 12:30:18 PM PST 24
Peak memory 210424 kb
Host smart-4a145cbe-639e-41e3-9b4d-7227d4718068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994138487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.3994138487
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2035447755
Short name T170
Test name
Test status
Simulation time 11475959341 ps
CPU time 27.82 seconds
Started Jan 03 12:40:34 PM PST 24
Finished Jan 03 12:42:28 PM PST 24
Peak memory 213580 kb
Host smart-8a64c94e-90d2-49e4-ab35-ee23b5045038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035447755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2035447755
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.431660931
Short name T137
Test name
Test status
Simulation time 5408864917 ps
CPU time 45.74 seconds
Started Jan 03 12:29:09 PM PST 24
Finished Jan 03 12:30:22 PM PST 24
Peak memory 214580 kb
Host smart-5c14f56f-1309-4f5c-aafd-9d39dc93e1d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431660931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.431660931
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.4007941068
Short name T198
Test name
Test status
Simulation time 88267545 ps
CPU time 4.32 seconds
Started Jan 03 12:27:33 PM PST 24
Finished Jan 03 12:27:41 PM PST 24
Peak memory 210452 kb
Host smart-b62f6d41-1bec-4ac5-b8c7-e658ec5fd1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007941068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.4007941068
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2109770453
Short name T256
Test name
Test status
Simulation time 46873229943 ps
CPU time 420.36 seconds
Started Jan 03 12:30:21 PM PST 24
Finished Jan 03 12:38:15 PM PST 24
Peak memory 237064 kb
Host smart-505799e7-7609-4a90-9083-5820b887e08e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109770453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2109770453
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.4032088338
Short name T352
Test name
Test status
Simulation time 1902886543 ps
CPU time 17.64 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:30:16 PM PST 24
Peak memory 210904 kb
Host smart-785da540-e535-41b7-bd33-b9097b46564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032088338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.4032088338
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2778898270
Short name T382
Test name
Test status
Simulation time 224642960 ps
CPU time 7.44 seconds
Started Jan 03 12:30:39 PM PST 24
Finished Jan 03 12:31:49 PM PST 24
Peak memory 210496 kb
Host smart-6f4539fe-96d6-4262-88ec-9493bbcde432
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2778898270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2778898270
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3419865617
Short name T301
Test name
Test status
Simulation time 365044540 ps
CPU time 10.01 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:54 PM PST 24
Peak memory 212424 kb
Host smart-733109cb-f5d0-40a6-8105-885b59c0aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419865617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3419865617
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1793220838
Short name T281
Test name
Test status
Simulation time 369015415 ps
CPU time 12.11 seconds
Started Jan 03 12:22:56 PM PST 24
Finished Jan 03 12:23:09 PM PST 24
Peak memory 213132 kb
Host smart-7e01bedf-64dc-4338-9c54-daca87cdff29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793220838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1793220838
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.2058498205
Short name T164
Test name
Test status
Simulation time 299580518 ps
CPU time 4.96 seconds
Started Jan 03 12:28:35 PM PST 24
Finished Jan 03 12:28:56 PM PST 24
Peak memory 210656 kb
Host smart-d0d6d739-18f4-4aeb-a9a9-8267dd8e374d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058498205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.2058498205
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3093858338
Short name T53
Test name
Test status
Simulation time 9342418341 ps
CPU time 131.91 seconds
Started Jan 03 12:27:28 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 235856 kb
Host smart-1c28b78c-6753-4e4c-b74f-7ad93ebb917f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093858338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3093858338
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.2330230651
Short name T396
Test name
Test status
Simulation time 96089639 ps
CPU time 5.43 seconds
Started Jan 03 12:28:36 PM PST 24
Finished Jan 03 12:28:57 PM PST 24
Peak memory 210552 kb
Host smart-1652c63e-f78d-42e8-ae63-898649d9fb94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2330230651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.2330230651
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3000054494
Short name T1
Test name
Test status
Simulation time 1535239655 ps
CPU time 21.56 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:27:57 PM PST 24
Peak memory 211696 kb
Host smart-b15d4eea-683a-4be5-8280-2f9125d45606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000054494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3000054494
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.883540214
Short name T261
Test name
Test status
Simulation time 2412476415 ps
CPU time 12.06 seconds
Started Jan 03 12:23:36 PM PST 24
Finished Jan 03 12:23:48 PM PST 24
Peak memory 211212 kb
Host smart-5b90c7a0-7aa2-4a72-ae12-957f7e662ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883540214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.883540214
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3353847879
Short name T269
Test name
Test status
Simulation time 225024137293 ps
CPU time 882.15 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:42:18 PM PST 24
Peak memory 231912 kb
Host smart-b079cd0c-c7fe-44ae-bf11-4863d0fffdd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353847879 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3353847879
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3366993806
Short name T350
Test name
Test status
Simulation time 1847195975 ps
CPU time 20.56 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:22 PM PST 24
Peak memory 208704 kb
Host smart-c0b68756-dca3-4007-b401-32c3d0b23528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366993806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3366993806
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3140202351
Short name T139
Test name
Test status
Simulation time 1395010211 ps
CPU time 13.29 seconds
Started Jan 03 12:45:32 PM PST 24
Finished Jan 03 12:47:14 PM PST 24
Peak memory 210872 kb
Host smart-f883d916-3be1-4af8-8e57-92921e75b8c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140202351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3140202351
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1983597947
Short name T91
Test name
Test status
Simulation time 8570187226 ps
CPU time 45.37 seconds
Started Jan 03 12:30:29 PM PST 24
Finished Jan 03 12:32:14 PM PST 24
Peak memory 211072 kb
Host smart-ab73ea75-d69d-4e2a-8846-263402874d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983597947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1983597947
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3487161222
Short name T333
Test name
Test status
Simulation time 24771743087 ps
CPU time 65.86 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:50 PM PST 24
Peak memory 216428 kb
Host smart-02cc5dea-cb22-4046-995b-9a2c0cc3bc0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487161222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3487161222
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.422054334
Short name T339
Test name
Test status
Simulation time 159078910103 ps
CPU time 1234.63 seconds
Started Jan 03 12:31:18 PM PST 24
Finished Jan 03 12:53:01 PM PST 24
Peak memory 229072 kb
Host smart-d2d84134-2334-41c4-bf4f-c699d51032f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422054334 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.422054334
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1672659686
Short name T43
Test name
Test status
Simulation time 1488079886 ps
CPU time 12.67 seconds
Started Jan 03 12:30:37 PM PST 24
Finished Jan 03 12:31:52 PM PST 24
Peak memory 210552 kb
Host smart-3acc72f2-9a1f-4dbf-9c88-e6d5a15b1566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672659686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1672659686
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.4170951271
Short name T268
Test name
Test status
Simulation time 1025135618 ps
CPU time 67.56 seconds
Started Jan 03 12:27:32 PM PST 24
Finished Jan 03 12:28:45 PM PST 24
Peak memory 227852 kb
Host smart-5f4743f0-8871-44fd-8f23-fa51fcac49ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170951271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.4170951271
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.839493419
Short name T15
Test name
Test status
Simulation time 3706547056 ps
CPU time 29.71 seconds
Started Jan 03 12:35:05 PM PST 24
Finished Jan 03 12:36:58 PM PST 24
Peak memory 211392 kb
Host smart-5f8c1ac5-b232-48e4-95c8-0d6f277c4a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839493419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.839493419
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3854388408
Short name T414
Test name
Test status
Simulation time 7747938566 ps
CPU time 78.15 seconds
Started Jan 03 12:23:36 PM PST 24
Finished Jan 03 12:24:54 PM PST 24
Peak memory 213932 kb
Host smart-23d0ed67-fe9f-4dab-976b-ad9f8d6d778c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854388408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3854388408
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.2291631177
Short name T274
Test name
Test status
Simulation time 1542752629 ps
CPU time 13.53 seconds
Started Jan 03 12:24:35 PM PST 24
Finished Jan 03 12:24:51 PM PST 24
Peak memory 210884 kb
Host smart-a0dd076b-c834-4c22-adaf-2a14e8132224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291631177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.2291631177
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.4185688434
Short name T154
Test name
Test status
Simulation time 2494398503 ps
CPU time 78.13 seconds
Started Jan 03 12:24:14 PM PST 24
Finished Jan 03 12:25:35 PM PST 24
Peak memory 236348 kb
Host smart-c767ec50-6eab-458f-847e-b67324fb00cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185688434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.4185688434
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.1639865366
Short name T357
Test name
Test status
Simulation time 175698280 ps
CPU time 9.64 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:30:00 PM PST 24
Peak memory 210024 kb
Host smart-15d4fdb8-70f9-471e-925d-3768cd830ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639865366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.1639865366
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.229083827
Short name T236
Test name
Test status
Simulation time 282432984 ps
CPU time 6.94 seconds
Started Jan 03 12:38:30 PM PST 24
Finished Jan 03 12:40:01 PM PST 24
Peak memory 210800 kb
Host smart-52185062-7ca8-462f-8c45-a1f226b6af93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229083827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.229083827
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.734750629
Short name T366
Test name
Test status
Simulation time 672141589 ps
CPU time 10.55 seconds
Started Jan 03 12:30:40 PM PST 24
Finished Jan 03 12:31:53 PM PST 24
Peak memory 212296 kb
Host smart-5477c1d3-4608-4049-a9be-5c6b9c240907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734750629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.734750629
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4265836172
Short name T156
Test name
Test status
Simulation time 14319612248 ps
CPU time 77.64 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 216144 kb
Host smart-f76a42dd-c347-4a3f-8200-efc131ff5ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265836172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4265836172
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.242289972
Short name T240
Test name
Test status
Simulation time 168181309 ps
CPU time 4.14 seconds
Started Jan 03 12:30:51 PM PST 24
Finished Jan 03 12:32:01 PM PST 24
Peak memory 210380 kb
Host smart-6243b5ad-032b-46f6-b800-4c563e45425a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242289972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.242289972
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1359353966
Short name T400
Test name
Test status
Simulation time 2286419573 ps
CPU time 67.28 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:31:38 PM PST 24
Peak memory 233424 kb
Host smart-66936205-7db1-4a7c-a306-e36f30a2dadb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359353966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1359353966
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1531582109
Short name T353
Test name
Test status
Simulation time 260206390 ps
CPU time 10.96 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 210432 kb
Host smart-b0061322-a035-4202-8094-396781281524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531582109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1531582109
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.4141313250
Short name T376
Test name
Test status
Simulation time 795984985 ps
CPU time 9.86 seconds
Started Jan 03 12:41:47 PM PST 24
Finished Jan 03 12:43:26 PM PST 24
Peak memory 212516 kb
Host smart-5251fe02-a59e-4b49-994c-6b0e0a25d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141313250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.4141313250
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1758614408
Short name T265
Test name
Test status
Simulation time 5077293337 ps
CPU time 28.53 seconds
Started Jan 03 12:28:59 PM PST 24
Finished Jan 03 12:29:55 PM PST 24
Peak memory 214884 kb
Host smart-8a5f17e3-7fc8-4913-b985-f935c2709593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758614408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1758614408
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2288767388
Short name T298
Test name
Test status
Simulation time 85601023949 ps
CPU time 1047.48 seconds
Started Jan 03 12:23:18 PM PST 24
Finished Jan 03 12:40:46 PM PST 24
Peak memory 235424 kb
Host smart-3655be5f-3dd2-4257-9047-6725eab840ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288767388 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2288767388
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2302396238
Short name T285
Test name
Test status
Simulation time 396390148 ps
CPU time 4.39 seconds
Started Jan 03 12:30:06 PM PST 24
Finished Jan 03 12:30:55 PM PST 24
Peak memory 210828 kb
Host smart-18a84845-522e-46e9-8660-4e700d36db1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302396238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2302396238
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1939867800
Short name T209
Test name
Test status
Simulation time 17888461450 ps
CPU time 88.72 seconds
Started Jan 03 12:29:43 PM PST 24
Finished Jan 03 12:31:51 PM PST 24
Peak memory 227160 kb
Host smart-9930ef4f-57a5-4184-a157-681e455ad09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939867800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.1939867800
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2891651386
Short name T386
Test name
Test status
Simulation time 1637701371 ps
CPU time 14.69 seconds
Started Jan 03 12:29:46 PM PST 24
Finished Jan 03 12:30:41 PM PST 24
Peak memory 210672 kb
Host smart-26e5f0fe-5253-4aa1-bc38-a922f62077f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891651386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2891651386
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.3445263497
Short name T159
Test name
Test status
Simulation time 94555013 ps
CPU time 5.39 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:29:49 PM PST 24
Peak memory 209728 kb
Host smart-14cc4846-fd2e-4f00-b8ed-ac777e0e8222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445263497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.3445263497
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1263919260
Short name T343
Test name
Test status
Simulation time 2042739106 ps
CPU time 27.38 seconds
Started Jan 03 12:22:57 PM PST 24
Finished Jan 03 12:23:25 PM PST 24
Peak memory 212344 kb
Host smart-3564d895-88ac-4c2d-a6c5-1adaeb6b6fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263919260 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1263919260
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3214312896
Short name T17
Test name
Test status
Simulation time 11749818744 ps
CPU time 40.83 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:30:02 PM PST 24
Peak memory 215024 kb
Host smart-b48da57d-a543-46bd-b9d6-57727bf86da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214312896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3214312896
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.3646144201
Short name T279
Test name
Test status
Simulation time 73049014221 ps
CPU time 2620.06 seconds
Started Jan 03 12:30:43 PM PST 24
Finished Jan 03 01:15:28 PM PST 24
Peak memory 243268 kb
Host smart-f877e323-15d4-4054-9d5a-ac8415ef268f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646144201 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.3646144201
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.701942024
Short name T233
Test name
Test status
Simulation time 723738859 ps
CPU time 8.91 seconds
Started Jan 03 12:30:25 PM PST 24
Finished Jan 03 12:31:29 PM PST 24
Peak memory 210552 kb
Host smart-9f2585f6-2ae0-4f5f-b310-a0e646cbba8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701942024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.701942024
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1233660237
Short name T218
Test name
Test status
Simulation time 22098547691 ps
CPU time 133.19 seconds
Started Jan 03 12:35:49 PM PST 24
Finished Jan 03 12:39:51 PM PST 24
Peak memory 212132 kb
Host smart-9a9c45cf-bc14-496f-928d-5333e19bc8cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233660237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1233660237
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.444819812
Short name T342
Test name
Test status
Simulation time 341660126 ps
CPU time 10.26 seconds
Started Jan 03 12:26:26 PM PST 24
Finished Jan 03 12:26:37 PM PST 24
Peak memory 211036 kb
Host smart-ae8d8162-8cf1-4673-950a-5675f919c7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444819812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.444819812
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.4110359205
Short name T275
Test name
Test status
Simulation time 383698287 ps
CPU time 5.79 seconds
Started Jan 03 12:29:39 PM PST 24
Finished Jan 03 12:30:22 PM PST 24
Peak memory 210776 kb
Host smart-099a922f-686c-45c6-8a7b-4ff5444d896d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4110359205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.4110359205
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1498054291
Short name T277
Test name
Test status
Simulation time 7347669870 ps
CPU time 32.31 seconds
Started Jan 03 12:28:06 PM PST 24
Finished Jan 03 12:28:49 PM PST 24
Peak memory 211924 kb
Host smart-4abab72d-db75-41bb-a8fe-944e178c6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498054291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1498054291
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.891674452
Short name T173
Test name
Test status
Simulation time 2775088397 ps
CPU time 16.37 seconds
Started Jan 03 12:32:12 PM PST 24
Finished Jan 03 12:34:01 PM PST 24
Peak memory 213220 kb
Host smart-076d33a7-7d9f-4343-9c9e-54bf88056ac1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891674452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.891674452
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.825503468
Short name T389
Test name
Test status
Simulation time 49964087604 ps
CPU time 3785.3 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 01:34:22 PM PST 24
Peak memory 235180 kb
Host smart-ddfc7993-6a66-4db2-9376-764adf7869aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825503468 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.825503468
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2512968212
Short name T227
Test name
Test status
Simulation time 220697985 ps
CPU time 4.14 seconds
Started Jan 03 12:29:36 PM PST 24
Finished Jan 03 12:30:15 PM PST 24
Peak memory 210428 kb
Host smart-9349e159-d9a4-4af7-8758-24edc0d05947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512968212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2512968212
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1972165845
Short name T248
Test name
Test status
Simulation time 82546310809 ps
CPU time 399.27 seconds
Started Jan 03 12:26:02 PM PST 24
Finished Jan 03 12:32:42 PM PST 24
Peak memory 237392 kb
Host smart-58036c84-3059-4122-868b-6dc22db8204d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972165845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.1972165845
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.1588515070
Short name T167
Test name
Test status
Simulation time 1283655116 ps
CPU time 9.45 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 209648 kb
Host smart-22a30622-b8ed-4e8d-a13b-688f087bfb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588515070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.1588515070
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2921776493
Short name T287
Test name
Test status
Simulation time 4500327072 ps
CPU time 16.79 seconds
Started Jan 03 12:29:19 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 210504 kb
Host smart-2acbeda0-ff46-4a41-bd75-c293d234317c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2921776493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2921776493
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.3004340715
Short name T41
Test name
Test status
Simulation time 4072796789 ps
CPU time 117.63 seconds
Started Jan 03 12:28:35 PM PST 24
Finished Jan 03 12:30:49 PM PST 24
Peak memory 235992 kb
Host smart-e916a7ad-9c9d-44d3-b25a-b3844019b976
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004340715 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.3004340715
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.2338218991
Short name T356
Test name
Test status
Simulation time 23007540042 ps
CPU time 38.36 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:30:23 PM PST 24
Peak memory 210328 kb
Host smart-d593fdd9-705e-45f2-af9b-50dcedb7080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338218991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.2338218991
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.3743414850
Short name T204
Test name
Test status
Simulation time 1723920515 ps
CPU time 18.84 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:31:12 PM PST 24
Peak memory 210340 kb
Host smart-2fde3bfe-d4bc-40c2-9ac5-49c8d648f5b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743414850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.3743414850
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.895716436
Short name T250
Test name
Test status
Simulation time 33120964914 ps
CPU time 1199.48 seconds
Started Jan 03 12:29:06 PM PST 24
Finished Jan 03 12:49:33 PM PST 24
Peak memory 234504 kb
Host smart-6a06bcd6-10ef-45ba-8d99-b967ceb68644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895716436 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.895716436
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.377980984
Short name T371
Test name
Test status
Simulation time 1970883011 ps
CPU time 15.51 seconds
Started Jan 03 12:30:09 PM PST 24
Finished Jan 03 12:31:11 PM PST 24
Peak memory 210544 kb
Host smart-130c9479-f7a2-44c8-b4a0-34ca7159a0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377980984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.377980984
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1743930251
Short name T54
Test name
Test status
Simulation time 28304807752 ps
CPU time 208.93 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:34:10 PM PST 24
Peak memory 236288 kb
Host smart-5c40bb86-bf97-4e41-a2df-7ced4e4788a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743930251 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1743930251
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.324829120
Short name T38
Test name
Test status
Simulation time 9078103787 ps
CPU time 32.63 seconds
Started Jan 03 12:28:35 PM PST 24
Finished Jan 03 12:29:24 PM PST 24
Peak memory 211000 kb
Host smart-724c20e1-2288-4e94-bd82-e64ec56b1905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324829120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.324829120
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.2332722184
Short name T362
Test name
Test status
Simulation time 14572381700 ps
CPU time 13.1 seconds
Started Jan 03 12:28:20 PM PST 24
Finished Jan 03 12:28:42 PM PST 24
Peak memory 210000 kb
Host smart-065687bc-01f0-44dd-9297-11b20d6895fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332722184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.2332722184
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.4003057501
Short name T380
Test name
Test status
Simulation time 756531192 ps
CPU time 10.44 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:54 PM PST 24
Peak memory 213080 kb
Host smart-f96eab8e-c926-47be-9364-9c17168df1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003057501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4003057501
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2090624934
Short name T176
Test name
Test status
Simulation time 6290355029 ps
CPU time 55.3 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:31:29 PM PST 24
Peak memory 212048 kb
Host smart-f07ee234-1a2e-46b5-9907-c423c7bee2dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090624934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2090624934
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1725986025
Short name T327
Test name
Test status
Simulation time 76608100954 ps
CPU time 1336.72 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:52:51 PM PST 24
Peak memory 226876 kb
Host smart-225c64c8-b4c0-465b-8655-68823a0607cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725986025 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1725986025
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.3766713338
Short name T222
Test name
Test status
Simulation time 2229468568 ps
CPU time 15.89 seconds
Started Jan 03 12:29:14 PM PST 24
Finished Jan 03 12:29:58 PM PST 24
Peak memory 210100 kb
Host smart-4e76901b-0cd9-425e-9335-604e36b4aadf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766713338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.3766713338
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.1753767847
Short name T347
Test name
Test status
Simulation time 32055043388 ps
CPU time 150.41 seconds
Started Jan 03 12:35:35 PM PST 24
Finished Jan 03 12:39:38 PM PST 24
Peak memory 212872 kb
Host smart-370d5889-7212-42a0-aa8e-d577a6eeadfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753767847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.1753767847
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1670998811
Short name T395
Test name
Test status
Simulation time 4014014175 ps
CPU time 33.46 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:28:09 PM PST 24
Peak memory 210692 kb
Host smart-8ec6b093-fafa-451a-ae11-92c5655d2d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670998811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1670998811
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2054021092
Short name T304
Test name
Test status
Simulation time 11470541229 ps
CPU time 16.49 seconds
Started Jan 03 12:27:30 PM PST 24
Finished Jan 03 12:27:52 PM PST 24
Peak memory 210476 kb
Host smart-fa128656-b786-4aea-97c3-69ff612dfd71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054021092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2054021092
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.552387554
Short name T231
Test name
Test status
Simulation time 3648399484 ps
CPU time 30.88 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:31:12 PM PST 24
Peak memory 211256 kb
Host smart-aa061194-55b0-4e2f-9301-901a693888f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552387554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.552387554
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2411610902
Short name T87
Test name
Test status
Simulation time 26592324781 ps
CPU time 30.41 seconds
Started Jan 03 12:27:15 PM PST 24
Finished Jan 03 12:27:48 PM PST 24
Peak memory 212564 kb
Host smart-f12707b0-022f-42a2-86fa-a7e7807fbae5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411610902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2411610902
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.1007555538
Short name T7
Test name
Test status
Simulation time 385450638 ps
CPU time 6.51 seconds
Started Jan 03 12:29:13 PM PST 24
Finished Jan 03 12:29:46 PM PST 24
Peak memory 210460 kb
Host smart-630c8a2b-c296-4bee-8a5b-5ff1dd9d80b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007555538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1007555538
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1551090571
Short name T264
Test name
Test status
Simulation time 18711228538 ps
CPU time 242.32 seconds
Started Jan 03 12:27:30 PM PST 24
Finished Jan 03 12:31:38 PM PST 24
Peak memory 223920 kb
Host smart-26fec6bc-da51-4174-bae5-25605e6984da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551090571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1551090571
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3414885792
Short name T32
Test name
Test status
Simulation time 169884754 ps
CPU time 9.57 seconds
Started Jan 03 12:38:56 PM PST 24
Finished Jan 03 12:40:21 PM PST 24
Peak memory 210932 kb
Host smart-d5d593a9-e893-4556-9b15-f828ff552a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414885792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3414885792
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.4074718221
Short name T171
Test name
Test status
Simulation time 5890407948 ps
CPU time 13.98 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:30:07 PM PST 24
Peak memory 210584 kb
Host smart-97c0629c-d783-4a10-9db6-3abb536dc876
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074718221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.4074718221
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.2630537883
Short name T155
Test name
Test status
Simulation time 6699339779 ps
CPU time 32.4 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 12:28:08 PM PST 24
Peak memory 213252 kb
Host smart-d482c1b1-3eac-4c2c-aded-a7268862f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630537883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.2630537883
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.257212284
Short name T162
Test name
Test status
Simulation time 10704800673 ps
CPU time 80.4 seconds
Started Jan 03 12:30:12 PM PST 24
Finished Jan 03 12:32:20 PM PST 24
Peak memory 215948 kb
Host smart-7724a53a-9966-4607-a6a7-183fd3d3b8c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257212284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.257212284
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1312476820
Short name T313
Test name
Test status
Simulation time 345057566388 ps
CPU time 7348.46 seconds
Started Jan 03 12:27:32 PM PST 24
Finished Jan 03 02:30:06 PM PST 24
Peak memory 235712 kb
Host smart-ad325cad-755b-48d8-aa1c-a41c6d7f5c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312476820 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1312476820
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2493030111
Short name T3
Test name
Test status
Simulation time 2360954944 ps
CPU time 10.29 seconds
Started Jan 03 12:23:11 PM PST 24
Finished Jan 03 12:23:22 PM PST 24
Peak memory 210812 kb
Host smart-4767307b-6907-4004-a638-3bb00458ac30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493030111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2493030111
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4011658766
Short name T211
Test name
Test status
Simulation time 97350902620 ps
CPU time 214.64 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:41:23 PM PST 24
Peak memory 228132 kb
Host smart-ce0d40ab-cb2e-4afb-8bdb-ad02a818a33f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011658766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4011658766
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.4077880047
Short name T418
Test name
Test status
Simulation time 3298740472 ps
CPU time 15.58 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:30:50 PM PST 24
Peak memory 210632 kb
Host smart-b21eac25-0c31-4658-b9a3-2579871edb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077880047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.4077880047
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.240384355
Short name T272
Test name
Test status
Simulation time 319615885 ps
CPU time 8.03 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:52 PM PST 24
Peak memory 210412 kb
Host smart-0fb154d7-7bdf-44e7-b925-ca06094a7eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=240384355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.240384355
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.4152619858
Short name T378
Test name
Test status
Simulation time 3193804769 ps
CPU time 28.41 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:30:12 PM PST 24
Peak memory 212136 kb
Host smart-d4fea1c7-0c93-48af-a24e-d29d89b1173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152619858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.4152619858
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1410096697
Short name T191
Test name
Test status
Simulation time 3769642789 ps
CPU time 38.1 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:30:22 PM PST 24
Peak memory 211524 kb
Host smart-3726a8eb-3b24-4d5b-97ae-cf4f1df95d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410096697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1410096697
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.3609035986
Short name T50
Test name
Test status
Simulation time 89304049 ps
CPU time 4.46 seconds
Started Jan 03 12:26:47 PM PST 24
Finished Jan 03 12:26:59 PM PST 24
Peak memory 210800 kb
Host smart-aaa0bfa0-16f8-4a11-8e78-485c703168bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609035986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.3609035986
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3321145316
Short name T379
Test name
Test status
Simulation time 16194130229 ps
CPU time 164.8 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:32:20 PM PST 24
Peak memory 237972 kb
Host smart-ba5a30d4-4eec-46ab-a5f0-ecd7b48240e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321145316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3321145316
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.1636697257
Short name T372
Test name
Test status
Simulation time 3846257332 ps
CPU time 29.93 seconds
Started Jan 03 12:32:19 PM PST 24
Finished Jan 03 12:34:57 PM PST 24
Peak memory 211724 kb
Host smart-cb132ea3-2a05-4d53-93eb-bb45c62486ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636697257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.1636697257
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3586178103
Short name T393
Test name
Test status
Simulation time 7054579622 ps
CPU time 14.72 seconds
Started Jan 03 12:29:07 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 210400 kb
Host smart-edca2f60-2e32-4dbf-8179-f5ee4b0f2a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586178103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3586178103
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1647589824
Short name T169
Test name
Test status
Simulation time 8288685487 ps
CPU time 32.44 seconds
Started Jan 03 12:35:53 PM PST 24
Finished Jan 03 12:38:12 PM PST 24
Peak memory 213300 kb
Host smart-7af9ee3f-9785-4af2-b542-4fff3329d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647589824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1647589824
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2812197421
Short name T363
Test name
Test status
Simulation time 21779515898 ps
CPU time 38.26 seconds
Started Jan 03 12:35:12 PM PST 24
Finished Jan 03 12:37:24 PM PST 24
Peak memory 213996 kb
Host smart-e9b7906c-50ec-4d3a-9cbf-2a1a72850047
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812197421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2812197421
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.1207288379
Short name T305
Test name
Test status
Simulation time 661550459 ps
CPU time 8.33 seconds
Started Jan 03 12:34:54 PM PST 24
Finished Jan 03 12:36:32 PM PST 24
Peak memory 210824 kb
Host smart-61fee64d-60c1-4c40-be3f-31d42c3d1aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207288379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.1207288379
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1056160760
Short name T203
Test name
Test status
Simulation time 86007091811 ps
CPU time 222.82 seconds
Started Jan 03 12:26:45 PM PST 24
Finished Jan 03 12:30:36 PM PST 24
Peak memory 232600 kb
Host smart-0cc29b4e-eed0-44fc-a0b6-8011735a3846
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056160760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.1056160760
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2756279104
Short name T260
Test name
Test status
Simulation time 8369571764 ps
CPU time 32.61 seconds
Started Jan 03 12:29:28 PM PST 24
Finished Jan 03 12:30:33 PM PST 24
Peak memory 211324 kb
Host smart-597020e6-f119-40ab-ac87-4869fd75a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756279104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2756279104
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.315935684
Short name T381
Test name
Test status
Simulation time 270043170 ps
CPU time 7.58 seconds
Started Jan 03 12:28:50 PM PST 24
Finished Jan 03 12:29:27 PM PST 24
Peak memory 210796 kb
Host smart-c8c4c103-690d-4013-bb15-35a59812455c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315935684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.315935684
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.4007201524
Short name T374
Test name
Test status
Simulation time 1195513812 ps
CPU time 17.73 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:02 PM PST 24
Peak memory 212452 kb
Host smart-880414d1-0a41-4833-964c-e510ab91982e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007201524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4007201524
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3733117246
Short name T411
Test name
Test status
Simulation time 1919773096 ps
CPU time 13.09 seconds
Started Jan 03 12:35:14 PM PST 24
Finished Jan 03 12:37:07 PM PST 24
Peak memory 210972 kb
Host smart-34c27a76-7cda-4233-b973-7b90ca3c7ae9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733117246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3733117246
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1525671252
Short name T163
Test name
Test status
Simulation time 23370531688 ps
CPU time 1632.68 seconds
Started Jan 03 12:36:22 PM PST 24
Finished Jan 03 01:05:33 PM PST 24
Peak memory 227364 kb
Host smart-0b00cfd6-f09f-4866-b96a-85e1661af74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525671252 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1525671252
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.918853292
Short name T361
Test name
Test status
Simulation time 28597066755 ps
CPU time 15.08 seconds
Started Jan 03 12:28:43 PM PST 24
Finished Jan 03 12:29:25 PM PST 24
Peak memory 210756 kb
Host smart-faa82d91-33f4-42ec-87d9-33ce902b0a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918853292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.918853292
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2772792849
Short name T291
Test name
Test status
Simulation time 15007965853 ps
CPU time 30.24 seconds
Started Jan 03 12:30:10 PM PST 24
Finished Jan 03 12:31:27 PM PST 24
Peak memory 209916 kb
Host smart-ab18aa3e-5d8a-44d3-816b-ed99489fc414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772792849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2772792849
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1595513619
Short name T278
Test name
Test status
Simulation time 306922655 ps
CPU time 5.88 seconds
Started Jan 03 12:30:39 PM PST 24
Finished Jan 03 12:31:48 PM PST 24
Peak memory 210456 kb
Host smart-61a4fa45-92bf-4bda-b342-be921fd2ede8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595513619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1595513619
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2354377056
Short name T332
Test name
Test status
Simulation time 380133675 ps
CPU time 9.86 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 212216 kb
Host smart-d9e990dc-e18b-44e5-a023-2ce1cb1e781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354377056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2354377056
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2196279772
Short name T266
Test name
Test status
Simulation time 5431516543 ps
CPU time 52.23 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:37 PM PST 24
Peak memory 215996 kb
Host smart-6b91f98a-fd21-4623-9995-d30b213f71b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196279772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2196279772
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3104365501
Short name T11
Test name
Test status
Simulation time 312003581891 ps
CPU time 2889.18 seconds
Started Jan 03 12:32:33 PM PST 24
Finished Jan 03 01:22:46 PM PST 24
Peak memory 237040 kb
Host smart-decdbcb4-c7a2-4777-80b4-c4e5e2205871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104365501 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3104365501
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2802835335
Short name T351
Test name
Test status
Simulation time 931916029 ps
CPU time 9.82 seconds
Started Jan 03 12:32:25 PM PST 24
Finished Jan 03 12:34:02 PM PST 24
Peak memory 210840 kb
Host smart-40bf5370-aece-45a4-ae9d-6f6bd73c87fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802835335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2802835335
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3957501366
Short name T235
Test name
Test status
Simulation time 102814045067 ps
CPU time 523.61 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:38:38 PM PST 24
Peak memory 234200 kb
Host smart-8ed1516b-42f8-4b96-aa15-af42d28b5762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957501366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3957501366
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3123702199
Short name T294
Test name
Test status
Simulation time 175480666 ps
CPU time 9.72 seconds
Started Jan 03 12:30:05 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 211040 kb
Host smart-1f14b1c3-2ca6-4e5b-9250-fbddf8e678c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123702199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3123702199
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3065351742
Short name T293
Test name
Test status
Simulation time 17371117781 ps
CPU time 15.86 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:30:25 PM PST 24
Peak memory 210832 kb
Host smart-035561f2-4181-491e-a575-536368591646
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065351742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3065351742
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2144822310
Short name T325
Test name
Test status
Simulation time 3373627664 ps
CPU time 29.16 seconds
Started Jan 03 12:29:03 PM PST 24
Finished Jan 03 12:29:58 PM PST 24
Peak memory 212656 kb
Host smart-50a535a1-495e-4431-be95-1b19486d06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144822310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2144822310
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3614819394
Short name T219
Test name
Test status
Simulation time 1219947893 ps
CPU time 11.75 seconds
Started Jan 03 12:25:57 PM PST 24
Finished Jan 03 12:26:09 PM PST 24
Peak memory 210900 kb
Host smart-44526d14-4a9b-4822-b59f-2eed6ad0a73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614819394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3614819394
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3556301028
Short name T320
Test name
Test status
Simulation time 52392180930 ps
CPU time 228.87 seconds
Started Jan 03 12:28:46 PM PST 24
Finished Jan 03 12:33:04 PM PST 24
Peak memory 236332 kb
Host smart-0f749b9a-b76b-49a9-964c-a751e520d44f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556301028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3556301028
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2909017094
Short name T377
Test name
Test status
Simulation time 3755129341 ps
CPU time 30.72 seconds
Started Jan 03 12:29:24 PM PST 24
Finished Jan 03 12:30:26 PM PST 24
Peak memory 210892 kb
Host smart-f1533018-f249-4129-bb10-367efa467d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909017094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2909017094
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2955072630
Short name T188
Test name
Test status
Simulation time 95147586 ps
CPU time 5.79 seconds
Started Jan 03 12:26:32 PM PST 24
Finished Jan 03 12:26:38 PM PST 24
Peak memory 210804 kb
Host smart-4c2e5598-0cfe-4e4e-b71e-5e094339237e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955072630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2955072630
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1774460231
Short name T140
Test name
Test status
Simulation time 11232957813 ps
CPU time 29.86 seconds
Started Jan 03 12:28:38 PM PST 24
Finished Jan 03 12:29:24 PM PST 24
Peak memory 213160 kb
Host smart-13aac3cf-9f80-462c-a004-0bb781c45242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774460231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1774460231
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1013779879
Short name T214
Test name
Test status
Simulation time 12923781056 ps
CPU time 69.65 seconds
Started Jan 03 12:30:41 PM PST 24
Finished Jan 03 12:32:55 PM PST 24
Peak memory 218572 kb
Host smart-c9109bd2-169b-427e-ab13-0931eb7aca36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013779879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1013779879
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2285788254
Short name T207
Test name
Test status
Simulation time 29965414198 ps
CPU time 1086.58 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:48:16 PM PST 24
Peak memory 235360 kb
Host smart-4eaf16b9-faa1-4a40-9566-a48ded4de881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285788254 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2285788254
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1110308362
Short name T182
Test name
Test status
Simulation time 168149814 ps
CPU time 4.37 seconds
Started Jan 03 12:29:56 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 210784 kb
Host smart-0d7ef1dc-2aec-428b-b20a-a930ef5b044f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110308362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1110308362
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.145687267
Short name T369
Test name
Test status
Simulation time 5677355662 ps
CPU time 162.34 seconds
Started Jan 03 12:29:00 PM PST 24
Finished Jan 03 12:32:09 PM PST 24
Peak memory 234324 kb
Host smart-ff8ddc9a-e8b7-4a1a-90cd-ee873c46d4bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145687267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.145687267
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.571104820
Short name T192
Test name
Test status
Simulation time 14520383157 ps
CPU time 29.54 seconds
Started Jan 03 12:29:13 PM PST 24
Finished Jan 03 12:30:10 PM PST 24
Peak memory 213268 kb
Host smart-78cb253d-0537-41d2-8fbd-537dbfa0da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571104820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.571104820
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3189544630
Short name T252
Test name
Test status
Simulation time 6959532624 ps
CPU time 12.78 seconds
Started Jan 03 12:29:12 PM PST 24
Finished Jan 03 12:29:52 PM PST 24
Peak memory 209988 kb
Host smart-8ca5bba7-af14-4693-adff-b95dfc3beb13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189544630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3189544630
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2631499060
Short name T10
Test name
Test status
Simulation time 1208497175 ps
CPU time 17.24 seconds
Started Jan 03 12:26:43 PM PST 24
Finished Jan 03 12:27:01 PM PST 24
Peak memory 212416 kb
Host smart-2a238ae7-a118-43ca-9b48-6af5c78860bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631499060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2631499060
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.4051545271
Short name T416
Test name
Test status
Simulation time 264073735 ps
CPU time 8.39 seconds
Started Jan 03 12:26:47 PM PST 24
Finished Jan 03 12:27:03 PM PST 24
Peak memory 210896 kb
Host smart-7d04569a-1342-42c9-9f1c-272e70111fa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051545271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.4051545271
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3116196130
Short name T358
Test name
Test status
Simulation time 86828800844 ps
CPU time 1065.35 seconds
Started Jan 03 12:29:13 PM PST 24
Finished Jan 03 12:47:26 PM PST 24
Peak memory 235428 kb
Host smart-ab69cfb6-ea90-4cc6-a5f7-e102b4900883
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116196130 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3116196130
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1139687777
Short name T177
Test name
Test status
Simulation time 346574880 ps
CPU time 4.34 seconds
Started Jan 03 12:29:16 PM PST 24
Finished Jan 03 12:29:49 PM PST 24
Peak memory 209488 kb
Host smart-f7b4882c-7eb1-4f92-9519-0c97ae3c4458
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139687777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1139687777
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1902703256
Short name T201
Test name
Test status
Simulation time 6434971051 ps
CPU time 166.88 seconds
Started Jan 03 12:29:02 PM PST 24
Finished Jan 03 12:32:16 PM PST 24
Peak memory 236628 kb
Host smart-b9622fb0-7743-4706-8d1c-558e82164053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902703256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1902703256
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.834472163
Short name T323
Test name
Test status
Simulation time 664484329 ps
CPU time 9.88 seconds
Started Jan 03 12:29:51 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 210700 kb
Host smart-fc8685fb-5223-4a60-897a-08de10c38b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834472163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.834472163
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.438350347
Short name T300
Test name
Test status
Simulation time 6005391991 ps
CPU time 13.96 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:56 PM PST 24
Peak memory 210468 kb
Host smart-fc6f896f-7dad-467e-ae16-86145be07203
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438350347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.438350347
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2283069381
Short name T6
Test name
Test status
Simulation time 2298036181 ps
CPU time 69.52 seconds
Started Jan 03 12:29:38 PM PST 24
Finished Jan 03 12:31:24 PM PST 24
Peak memory 235444 kb
Host smart-592084a9-e11a-4b73-9e33-4723859448d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283069381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2283069381
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1133614889
Short name T160
Test name
Test status
Simulation time 13647030926 ps
CPU time 29.95 seconds
Started Jan 03 12:25:46 PM PST 24
Finished Jan 03 12:26:17 PM PST 24
Peak memory 212872 kb
Host smart-ab850d26-e27a-4493-849b-40d60e296532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133614889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1133614889
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.305947294
Short name T4
Test name
Test status
Simulation time 9872163840 ps
CPU time 75.39 seconds
Started Jan 03 12:24:46 PM PST 24
Finished Jan 03 12:26:05 PM PST 24
Peak memory 216736 kb
Host smart-94b8171f-547c-4e33-9c30-595c8ce2363a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305947294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.305947294
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3437400325
Short name T12
Test name
Test status
Simulation time 19304324842 ps
CPU time 725.57 seconds
Started Jan 03 12:27:21 PM PST 24
Finished Jan 03 12:39:30 PM PST 24
Peak memory 231608 kb
Host smart-a49d1334-aa7a-4b44-b2df-61b4dd3b96db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437400325 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.3437400325
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.364296564
Short name T329
Test name
Test status
Simulation time 2927426989 ps
CPU time 12.97 seconds
Started Jan 03 12:29:03 PM PST 24
Finished Jan 03 12:29:43 PM PST 24
Peak memory 210876 kb
Host smart-ef36a5ba-e1ac-4f13-9db6-ffdbbc4a1ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364296564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.364296564
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.4174948471
Short name T335
Test name
Test status
Simulation time 80004526525 ps
CPU time 219.2 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:33:30 PM PST 24
Peak memory 223720 kb
Host smart-07eeda84-a447-4934-9aad-ba70efb64cf2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174948471 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.4174948471
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.353200969
Short name T321
Test name
Test status
Simulation time 16373889749 ps
CPU time 34 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:31:50 PM PST 24
Peak memory 210908 kb
Host smart-adf6cb94-d3b1-40c2-865e-73c811ae6dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353200969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.353200969
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1963799613
Short name T407
Test name
Test status
Simulation time 5508431126 ps
CPU time 12.89 seconds
Started Jan 03 12:29:59 PM PST 24
Finished Jan 03 12:30:56 PM PST 24
Peak memory 210344 kb
Host smart-e5225e8c-d7a1-43cb-b64b-8ae086c293f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963799613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1963799613
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1256551167
Short name T238
Test name
Test status
Simulation time 6832268006 ps
CPU time 28.4 seconds
Started Jan 03 12:30:48 PM PST 24
Finished Jan 03 12:32:22 PM PST 24
Peak memory 212880 kb
Host smart-342e92f4-cafa-4282-8d34-46e91bf6f1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256551167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1256551167
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2379559085
Short name T282
Test name
Test status
Simulation time 11646144679 ps
CPU time 35.11 seconds
Started Jan 03 12:29:05 PM PST 24
Finished Jan 03 12:30:07 PM PST 24
Peak memory 214044 kb
Host smart-ba3a9b8b-1d09-45da-a496-9c090ef53a6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379559085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2379559085
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.844068182
Short name T161
Test name
Test status
Simulation time 9078907673 ps
CPU time 878.98 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:45:09 PM PST 24
Peak memory 221168 kb
Host smart-2edb3a72-b0a6-4958-9137-db4696545a50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844068182 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.844068182
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2743036019
Short name T284
Test name
Test status
Simulation time 2196683572 ps
CPU time 10.76 seconds
Started Jan 03 12:35:42 PM PST 24
Finished Jan 03 12:37:34 PM PST 24
Peak memory 210992 kb
Host smart-0a27ba09-4fcf-449b-86d1-6a3527577635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743036019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2743036019
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2582125015
Short name T37
Test name
Test status
Simulation time 3098250848 ps
CPU time 26.13 seconds
Started Jan 03 12:32:24 PM PST 24
Finished Jan 03 12:34:27 PM PST 24
Peak memory 210988 kb
Host smart-cf0f18ca-4954-4804-9e8d-3bdfabc2bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582125015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2582125015
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.1595915612
Short name T243
Test name
Test status
Simulation time 4500130948 ps
CPU time 11.67 seconds
Started Jan 03 12:25:55 PM PST 24
Finished Jan 03 12:26:07 PM PST 24
Peak memory 210784 kb
Host smart-eb84fe81-7811-4b14-96bb-b5da0afa1712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595915612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.1595915612
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.988762549
Short name T179
Test name
Test status
Simulation time 14019045805 ps
CPU time 33.96 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:30:20 PM PST 24
Peak memory 212584 kb
Host smart-7cc10569-692f-4329-8db0-1a3606ecfb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988762549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.988762549
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.2721654401
Short name T341
Test name
Test status
Simulation time 10233227355 ps
CPU time 59.87 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:30:48 PM PST 24
Peak memory 216680 kb
Host smart-0ebccb98-7455-40e1-9ebe-9cc34138fdf1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721654401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.2721654401
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3381102280
Short name T367
Test name
Test status
Simulation time 2844414334 ps
CPU time 13.05 seconds
Started Jan 03 12:29:11 PM PST 24
Finished Jan 03 12:29:51 PM PST 24
Peak memory 210944 kb
Host smart-7caa508c-c691-4dbd-a748-98a5e14dcbd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381102280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3381102280
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2110366861
Short name T267
Test name
Test status
Simulation time 168738786 ps
CPU time 9.51 seconds
Started Jan 03 12:36:13 PM PST 24
Finished Jan 03 12:38:06 PM PST 24
Peak memory 210848 kb
Host smart-c794e624-b252-438b-999d-0c6b8d917e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110366861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2110366861
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.513021879
Short name T242
Test name
Test status
Simulation time 395295352 ps
CPU time 7.98 seconds
Started Jan 03 12:27:27 PM PST 24
Finished Jan 03 12:27:42 PM PST 24
Peak memory 209672 kb
Host smart-62362191-1c4c-4a5a-94d3-1d0553122111
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513021879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.513021879
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1748789030
Short name T255
Test name
Test status
Simulation time 1159585677 ps
CPU time 21.91 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:31:02 PM PST 24
Peak memory 215524 kb
Host smart-32cb6341-59f9-4070-94f0-405d72fa44ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748789030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1748789030
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1787411577
Short name T271
Test name
Test status
Simulation time 1405341932 ps
CPU time 12.86 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:30:47 PM PST 24
Peak memory 210808 kb
Host smart-6140b69e-3a9f-4f8b-8c98-c04dc61e68b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787411577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1787411577
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1346059377
Short name T51
Test name
Test status
Simulation time 92709633602 ps
CPU time 240.04 seconds
Started Jan 03 12:32:06 PM PST 24
Finished Jan 03 12:37:40 PM PST 24
Peak memory 237300 kb
Host smart-7168a0d4-6149-4499-b6de-1e28755dcda0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346059377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1346059377
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1064764270
Short name T196
Test name
Test status
Simulation time 3155715676 ps
CPU time 28.13 seconds
Started Jan 03 12:38:56 PM PST 24
Finished Jan 03 12:40:31 PM PST 24
Peak memory 211076 kb
Host smart-8a5dd6b5-51fe-4483-a516-02c12f42d393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064764270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1064764270
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.968084769
Short name T406
Test name
Test status
Simulation time 549495929 ps
CPU time 6.07 seconds
Started Jan 03 12:29:24 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 210664 kb
Host smart-31782045-9643-487e-8320-8863fb9c24d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968084769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.968084769
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.2143207240
Short name T223
Test name
Test status
Simulation time 725625786 ps
CPU time 10.22 seconds
Started Jan 03 12:28:51 PM PST 24
Finished Jan 03 12:29:30 PM PST 24
Peak memory 212300 kb
Host smart-7e8acfc5-c8fd-4078-a717-a56de76399c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143207240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2143207240
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3610775787
Short name T138
Test name
Test status
Simulation time 1691053765 ps
CPU time 16.63 seconds
Started Jan 03 12:29:04 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 209316 kb
Host smart-85727783-1faa-410b-baa9-f292bef6d116
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610775787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3610775787
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.417159080
Short name T394
Test name
Test status
Simulation time 1565534317 ps
CPU time 13.16 seconds
Started Jan 03 12:29:27 PM PST 24
Finished Jan 03 12:30:13 PM PST 24
Peak memory 210476 kb
Host smart-74821c32-da31-4695-96ad-81342078668e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417159080 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.417159080
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2268362695
Short name T217
Test name
Test status
Simulation time 17011274508 ps
CPU time 193.38 seconds
Started Jan 03 12:32:29 PM PST 24
Finished Jan 03 12:37:06 PM PST 24
Peak memory 234440 kb
Host smart-863cd07c-9cca-44e3-8664-c2f1e8e27287
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268362695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.2268362695
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1580459516
Short name T373
Test name
Test status
Simulation time 1836614801 ps
CPU time 20.48 seconds
Started Jan 03 12:35:44 PM PST 24
Finished Jan 03 12:37:44 PM PST 24
Peak memory 210928 kb
Host smart-92bf6a95-4004-4022-82fb-4944797c8f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580459516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1580459516
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.4039922718
Short name T251
Test name
Test status
Simulation time 9693982208 ps
CPU time 12.53 seconds
Started Jan 03 12:28:56 PM PST 24
Finished Jan 03 12:29:35 PM PST 24
Peak memory 210788 kb
Host smart-10d3a369-cf9b-4b3f-b5fe-8949687ae5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039922718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.4039922718
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.1086710875
Short name T202
Test name
Test status
Simulation time 5690110736 ps
CPU time 25.79 seconds
Started Jan 03 12:31:59 PM PST 24
Finished Jan 03 12:33:56 PM PST 24
Peak memory 212940 kb
Host smart-e75f975d-7990-48a7-a03b-c2b0b25ae6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086710875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.1086710875
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.348439062
Short name T94
Test name
Test status
Simulation time 1987666333 ps
CPU time 18.04 seconds
Started Jan 03 12:34:27 PM PST 24
Finished Jan 03 12:36:29 PM PST 24
Peak memory 211156 kb
Host smart-325234ae-92b8-41d8-8df9-2da689fe0d34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348439062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.348439062
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.1059751115
Short name T315
Test name
Test status
Simulation time 46013369963 ps
CPU time 949.51 seconds
Started Jan 03 12:26:46 PM PST 24
Finished Jan 03 12:42:45 PM PST 24
Peak memory 228552 kb
Host smart-4cf16315-c5fb-4367-987a-449ce3362653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059751115 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.1059751115
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2093167541
Short name T397
Test name
Test status
Simulation time 289753331 ps
CPU time 6.12 seconds
Started Jan 03 12:28:30 PM PST 24
Finished Jan 03 12:28:49 PM PST 24
Peak memory 210820 kb
Host smart-e72725be-2e3c-4ad4-80d6-3b541f0b1b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093167541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2093167541
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2849384198
Short name T328
Test name
Test status
Simulation time 18541411878 ps
CPU time 159.49 seconds
Started Jan 03 12:29:23 PM PST 24
Finished Jan 03 12:32:34 PM PST 24
Peak memory 236008 kb
Host smart-8202c3eb-6027-45f9-b9cc-b98c3a77f56e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849384198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2849384198
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.3526754794
Short name T387
Test name
Test status
Simulation time 665295710 ps
CPU time 9.53 seconds
Started Jan 03 12:30:04 PM PST 24
Finished Jan 03 12:30:58 PM PST 24
Peak memory 211024 kb
Host smart-66a19cb9-3ccc-47d4-95c7-49358a37d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526754794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.3526754794
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.279354044
Short name T314
Test name
Test status
Simulation time 541842431 ps
CPU time 5.42 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:12 PM PST 24
Peak memory 210816 kb
Host smart-a6f9f925-05cf-409e-ba4c-5e3ce64ed0d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279354044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.279354044
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2281480732
Short name T311
Test name
Test status
Simulation time 1628446227 ps
CPU time 13.36 seconds
Started Jan 03 12:29:08 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 211568 kb
Host smart-c745ac27-c0a7-4658-89be-e1460d3ffd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281480732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2281480732
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.646758995
Short name T302
Test name
Test status
Simulation time 5965273937 ps
CPU time 27.4 seconds
Started Jan 03 12:26:34 PM PST 24
Finished Jan 03 12:27:02 PM PST 24
Peak memory 215980 kb
Host smart-b2fcf7b1-7dca-461a-8705-8605e4df954e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646758995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.646758995
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3742456189
Short name T200
Test name
Test status
Simulation time 24366944768 ps
CPU time 1740.28 seconds
Started Jan 03 12:29:43 PM PST 24
Finished Jan 03 12:59:23 PM PST 24
Peak memory 227184 kb
Host smart-f6cebc21-0194-4741-9469-eb00b57dfddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742456189 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3742456189
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3601757606
Short name T178
Test name
Test status
Simulation time 332782667 ps
CPU time 4.23 seconds
Started Jan 03 12:28:33 PM PST 24
Finished Jan 03 12:28:55 PM PST 24
Peak memory 210688 kb
Host smart-296709c6-89e3-4ddf-8284-2c6bacd25b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601757606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3601757606
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3686810037
Short name T370
Test name
Test status
Simulation time 19865849088 ps
CPU time 201.83 seconds
Started Jan 03 12:26:14 PM PST 24
Finished Jan 03 12:29:37 PM PST 24
Peak memory 211108 kb
Host smart-42bc34ee-2a23-4c9f-a358-3f2c21b4901f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686810037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3686810037
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.3622581198
Short name T241
Test name
Test status
Simulation time 22443818085 ps
CPU time 32.81 seconds
Started Jan 03 12:29:49 PM PST 24
Finished Jan 03 12:31:03 PM PST 24
Peak memory 211252 kb
Host smart-4a2f5f2d-c8ab-4100-bfe8-cecb147dfa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622581198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.3622581198
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.864401287
Short name T185
Test name
Test status
Simulation time 97225769 ps
CPU time 5.66 seconds
Started Jan 03 12:29:15 PM PST 24
Finished Jan 03 12:29:49 PM PST 24
Peak memory 210468 kb
Host smart-63ecadef-dddb-4cd1-9370-233c7ec6ea22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864401287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.864401287
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2578566479
Short name T215
Test name
Test status
Simulation time 8937195780 ps
CPU time 25.52 seconds
Started Jan 03 12:29:40 PM PST 24
Finished Jan 03 12:30:43 PM PST 24
Peak memory 212940 kb
Host smart-ecaa7669-5130-44d3-81e9-53d2ab47b75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578566479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2578566479
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3801249962
Short name T174
Test name
Test status
Simulation time 2493584835 ps
CPU time 25.96 seconds
Started Jan 03 12:36:01 PM PST 24
Finished Jan 03 12:38:15 PM PST 24
Peak memory 212704 kb
Host smart-22c2692e-11a0-4700-a55a-94f672b6d5d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801249962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3801249962
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2531552688
Short name T399
Test name
Test status
Simulation time 40759037372 ps
CPU time 2135.05 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 01:05:44 PM PST 24
Peak memory 235440 kb
Host smart-f58566c5-cea0-4421-afba-3020398b8caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531552688 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2531552688
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.1670397492
Short name T136
Test name
Test status
Simulation time 1264525469 ps
CPU time 11.69 seconds
Started Jan 03 12:30:22 PM PST 24
Finished Jan 03 12:31:28 PM PST 24
Peak memory 210580 kb
Host smart-7e562d9b-28ea-47a9-8068-57da79cba4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670397492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.1670397492
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.1749224106
Short name T398
Test name
Test status
Simulation time 8649988535 ps
CPU time 151.08 seconds
Started Jan 03 12:29:36 PM PST 24
Finished Jan 03 12:32:42 PM PST 24
Peak memory 228044 kb
Host smart-ef928d77-460a-447f-ad9e-5366bf000f6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749224106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.1749224106
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.415414616
Short name T402
Test name
Test status
Simulation time 5963349130 ps
CPU time 14.95 seconds
Started Jan 03 12:29:06 PM PST 24
Finished Jan 03 12:29:48 PM PST 24
Peak memory 209856 kb
Host smart-17ba1411-7a9d-4817-b61d-af6b863a0cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415414616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.415414616
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.233270172
Short name T322
Test name
Test status
Simulation time 8897233661 ps
CPU time 23.08 seconds
Started Jan 03 12:29:12 PM PST 24
Finished Jan 03 12:30:02 PM PST 24
Peak memory 213408 kb
Host smart-5026e439-4167-4f09-af48-b17bad6af42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233270172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.233270172
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3321043850
Short name T34
Test name
Test status
Simulation time 15313374991 ps
CPU time 156.55 seconds
Started Jan 03 12:35:51 PM PST 24
Finished Jan 03 12:40:11 PM PST 24
Peak memory 219100 kb
Host smart-6c4a5dbe-cc5c-4efc-af48-b21020f47235
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321043850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3321043850
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.3963722411
Short name T288
Test name
Test status
Simulation time 152856978055 ps
CPU time 1683.86 seconds
Started Jan 03 12:36:00 PM PST 24
Finished Jan 03 01:05:52 PM PST 24
Peak memory 233528 kb
Host smart-767c8ea8-22cd-46c9-b5f0-2b67ca46e73b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963722411 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.3963722411
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2165549847
Short name T330
Test name
Test status
Simulation time 6206165421 ps
CPU time 13.63 seconds
Started Jan 03 12:29:39 PM PST 24
Finished Jan 03 12:30:31 PM PST 24
Peak memory 210612 kb
Host smart-eb09932c-f362-4e2f-9379-15436a0f6a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165549847 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2165549847
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4167222166
Short name T338
Test name
Test status
Simulation time 16118879048 ps
CPU time 220.49 seconds
Started Jan 03 12:29:00 PM PST 24
Finished Jan 03 12:33:07 PM PST 24
Peak memory 225508 kb
Host smart-3c1a062b-7f24-4e18-af77-a95be8fa245a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167222166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4167222166
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1969838171
Short name T157
Test name
Test status
Simulation time 16572379681 ps
CPU time 33.68 seconds
Started Jan 03 12:26:34 PM PST 24
Finished Jan 03 12:27:08 PM PST 24
Peak memory 211140 kb
Host smart-f8160a6e-9aed-4bfe-a2b3-c13e20936bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969838171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1969838171
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3737403728
Short name T92
Test name
Test status
Simulation time 366909614 ps
CPU time 5.37 seconds
Started Jan 03 12:29:25 PM PST 24
Finished Jan 03 12:30:02 PM PST 24
Peak memory 210728 kb
Host smart-0249a6ff-c853-42bc-a65b-ef6ee9d6e6ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737403728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3737403728
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2925062024
Short name T254
Test name
Test status
Simulation time 2306916553 ps
CPU time 13.47 seconds
Started Jan 03 12:32:19 PM PST 24
Finished Jan 03 12:34:00 PM PST 24
Peak memory 212852 kb
Host smart-fd28fa2d-d707-4e6b-bf7f-60f5a9a4258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925062024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2925062024
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1764382370
Short name T145
Test name
Test status
Simulation time 800379883 ps
CPU time 10.02 seconds
Started Jan 03 12:32:25 PM PST 24
Finished Jan 03 12:34:05 PM PST 24
Peak memory 213444 kb
Host smart-0f2b5b30-40fd-48b5-a3d7-5b5952654880
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764382370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1764382370
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3597618051
Short name T221
Test name
Test status
Simulation time 1672062121 ps
CPU time 13.86 seconds
Started Jan 03 12:26:39 PM PST 24
Finished Jan 03 12:26:54 PM PST 24
Peak memory 210920 kb
Host smart-9d48d409-8645-467d-bfed-bd20d0975052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597618051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3597618051
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1278512105
Short name T280
Test name
Test status
Simulation time 55498907840 ps
CPU time 536.72 seconds
Started Jan 03 12:29:50 PM PST 24
Finished Jan 03 12:39:28 PM PST 24
Peak memory 233292 kb
Host smart-26a7dff8-474f-4776-9be4-fb938badacf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278512105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1278512105
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3455516837
Short name T290
Test name
Test status
Simulation time 7901464462 ps
CPU time 31.53 seconds
Started Jan 03 12:29:10 PM PST 24
Finished Jan 03 12:30:09 PM PST 24
Peak memory 213256 kb
Host smart-f0ed7edf-1161-4f62-b767-7f79d1be50a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455516837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3455516837
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.1461209834
Short name T181
Test name
Test status
Simulation time 397831011 ps
CPU time 5.21 seconds
Started Jan 03 12:30:50 PM PST 24
Finished Jan 03 12:32:01 PM PST 24
Peak memory 210360 kb
Host smart-bc7c193c-e0e7-4c24-993a-dbdf9c7cff17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461209834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.1461209834
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1287028392
Short name T197
Test name
Test status
Simulation time 35424172354 ps
CPU time 33.32 seconds
Started Jan 03 12:29:33 PM PST 24
Finished Jan 03 12:30:40 PM PST 24
Peak memory 212508 kb
Host smart-42476100-b1f9-484b-b253-2cd60666c89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287028392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1287028392
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.62675267
Short name T262
Test name
Test status
Simulation time 113704942 ps
CPU time 6.98 seconds
Started Jan 03 12:28:49 PM PST 24
Finished Jan 03 12:29:26 PM PST 24
Peak memory 210608 kb
Host smart-fc753620-26bb-414e-9727-319edcc3f931
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62675267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.rom_ctrl_stress_all.62675267
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.3048668835
Short name T14
Test name
Test status
Simulation time 69014719632 ps
CPU time 763.7 seconds
Started Jan 03 12:30:45 PM PST 24
Finished Jan 03 12:44:35 PM PST 24
Peak memory 235048 kb
Host smart-880064f7-420a-4c71-9f1a-70c292945b15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048668835 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.3048668835
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2542556955
Short name T165
Test name
Test status
Simulation time 17234837526 ps
CPU time 10.27 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:29:02 PM PST 24
Peak memory 210520 kb
Host smart-401132a9-3419-41a7-9678-65c4592101f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542556955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2542556955
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.641465184
Short name T249
Test name
Test status
Simulation time 29138363957 ps
CPU time 289.99 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:35:48 PM PST 24
Peak memory 234748 kb
Host smart-429ba3ff-ce2b-4609-8811-2475650fb0b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641465184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.641465184
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3339335785
Short name T33
Test name
Test status
Simulation time 42721140467 ps
CPU time 28.62 seconds
Started Jan 03 12:30:35 PM PST 24
Finished Jan 03 12:32:05 PM PST 24
Peak memory 210960 kb
Host smart-ac740370-13fe-4300-8d6f-2544fba0ab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339335785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3339335785
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1249400914
Short name T149
Test name
Test status
Simulation time 1234851173 ps
CPU time 11.69 seconds
Started Jan 03 12:30:40 PM PST 24
Finished Jan 03 12:31:54 PM PST 24
Peak memory 210556 kb
Host smart-c4e3e4fe-5c23-4a82-8e0b-cf3fe817b423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249400914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1249400914
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2475514840
Short name T49
Test name
Test status
Simulation time 4153236691 ps
CPU time 58.52 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:43 PM PST 24
Peak memory 234028 kb
Host smart-9ce1b042-4766-4770-bb93-ac64efb954ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475514840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2475514840
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1815823696
Short name T346
Test name
Test status
Simulation time 7546676335 ps
CPU time 21.18 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:06 PM PST 24
Peak memory 211320 kb
Host smart-e0c7a165-f562-4eb3-8b57-267d47e162d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815823696 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1815823696
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3433518747
Short name T246
Test name
Test status
Simulation time 764634398 ps
CPU time 23.9 seconds
Started Jan 03 12:30:11 PM PST 24
Finished Jan 03 12:31:22 PM PST 24
Peak memory 213556 kb
Host smart-bdd652e9-b405-4023-ac00-246e2ed55659
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433518747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3433518747
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2467469678
Short name T354
Test name
Test status
Simulation time 12906484556 ps
CPU time 13.56 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:30:03 PM PST 24
Peak memory 210468 kb
Host smart-9a702ef8-abbd-438e-badd-db17939545ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467469678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2467469678
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2882013832
Short name T410
Test name
Test status
Simulation time 11616362265 ps
CPU time 180.67 seconds
Started Jan 03 12:28:26 PM PST 24
Finished Jan 03 12:31:37 PM PST 24
Peak memory 233252 kb
Host smart-eafd5a2b-a9fd-4531-8374-85204c90e705
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882013832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2882013832
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.3452880862
Short name T210
Test name
Test status
Simulation time 9405431410 ps
CPU time 25.96 seconds
Started Jan 03 12:28:21 PM PST 24
Finished Jan 03 12:28:56 PM PST 24
Peak memory 211072 kb
Host smart-b66a7ec4-1eb6-4130-8b99-7a69c8e6345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452880862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.3452880862
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3927544495
Short name T283
Test name
Test status
Simulation time 97748839 ps
CPU time 5.51 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:52 PM PST 24
Peak memory 210708 kb
Host smart-2400efc1-faed-41c5-8717-14de589218f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927544495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3927544495
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1454983565
Short name T292
Test name
Test status
Simulation time 2394016035 ps
CPU time 27.92 seconds
Started Jan 03 12:29:35 PM PST 24
Finished Jan 03 12:30:38 PM PST 24
Peak memory 211696 kb
Host smart-92158bdf-64eb-4a5b-b8ed-18c23a1d9ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454983565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1454983565
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.640628397
Short name T289
Test name
Test status
Simulation time 154799580 ps
CPU time 10.14 seconds
Started Jan 03 12:29:45 PM PST 24
Finished Jan 03 12:30:35 PM PST 24
Peak memory 211296 kb
Host smart-09de5739-e42c-4455-9e08-52de64877626
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640628397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.640628397
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1643911443
Short name T244
Test name
Test status
Simulation time 38254146297 ps
CPU time 4985.8 seconds
Started Jan 03 12:29:42 PM PST 24
Finished Jan 03 01:53:28 PM PST 24
Peak memory 235400 kb
Host smart-97572b0f-a0fc-4c72-b9c7-60b5120dcd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643911443 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1643911443
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.557657533
Short name T337
Test name
Test status
Simulation time 1461179961 ps
CPU time 12.71 seconds
Started Jan 03 12:28:44 PM PST 24
Finished Jan 03 12:29:24 PM PST 24
Peak memory 210792 kb
Host smart-54e36f3a-6921-43b8-9506-e32a7f03dedc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557657533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.557657533
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.3608913599
Short name T384
Test name
Test status
Simulation time 36912892665 ps
CPU time 190.32 seconds
Started Jan 03 12:26:44 PM PST 24
Finished Jan 03 12:29:56 PM PST 24
Peak memory 236388 kb
Host smart-c7b46155-eb7f-49eb-9b35-1f2123dd1d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608913599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.3608913599
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.240871923
Short name T388
Test name
Test status
Simulation time 3073381775 ps
CPU time 14.2 seconds
Started Jan 03 12:29:02 PM PST 24
Finished Jan 03 12:29:43 PM PST 24
Peak memory 211212 kb
Host smart-3841341d-49d8-4325-bee8-23acd4a65764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240871923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.240871923
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3598613798
Short name T368
Test name
Test status
Simulation time 2195667160 ps
CPU time 11.54 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:29:57 PM PST 24
Peak memory 210828 kb
Host smart-f77e6cc3-1484-491d-b3e5-1bd9cd1f8a6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598613798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3598613798
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2647793345
Short name T158
Test name
Test status
Simulation time 14074673484 ps
CPU time 39.6 seconds
Started Jan 03 12:28:54 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 212936 kb
Host smart-2761c007-a3f8-416c-868a-7bf04d8f6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647793345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2647793345
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2560990125
Short name T331
Test name
Test status
Simulation time 66886756697 ps
CPU time 50 seconds
Started Jan 03 12:26:34 PM PST 24
Finished Jan 03 12:27:25 PM PST 24
Peak memory 215356 kb
Host smart-5e343258-64a6-4c13-9c75-cd9054a31fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560990125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2560990125
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.2697751957
Short name T273
Test name
Test status
Simulation time 40269137412 ps
CPU time 1670.14 seconds
Started Jan 03 12:28:53 PM PST 24
Finished Jan 03 12:57:11 PM PST 24
Peak memory 237928 kb
Host smart-0e2df4f4-16fb-4bbc-a552-08436af99120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697751957 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.2697751957
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4046627084
Short name T8
Test name
Test status
Simulation time 13048841274 ps
CPU time 15.87 seconds
Started Jan 03 12:29:58 PM PST 24
Finished Jan 03 12:30:58 PM PST 24
Peak memory 210324 kb
Host smart-30eb0135-10ee-4f64-a186-09eaa9512122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046627084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4046627084
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3751977644
Short name T183
Test name
Test status
Simulation time 60901835066 ps
CPU time 315.24 seconds
Started Jan 03 12:35:10 PM PST 24
Finished Jan 03 12:41:52 PM PST 24
Peak memory 237276 kb
Host smart-9bbafc46-9f45-433e-9f2a-fa214db3e926
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751977644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.3751977644
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3792066015
Short name T225
Test name
Test status
Simulation time 61658272979 ps
CPU time 30.84 seconds
Started Jan 03 12:26:29 PM PST 24
Finished Jan 03 12:27:01 PM PST 24
Peak memory 211200 kb
Host smart-82b87e86-2861-4411-85e6-4c2d48418635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792066015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3792066015
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2059183097
Short name T150
Test name
Test status
Simulation time 3265855160 ps
CPU time 15.3 seconds
Started Jan 03 12:26:26 PM PST 24
Finished Jan 03 12:26:42 PM PST 24
Peak memory 210896 kb
Host smart-59c20633-935e-48b3-8469-0e0046cee0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059183097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2059183097
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2753520980
Short name T318
Test name
Test status
Simulation time 1961159665 ps
CPU time 23.18 seconds
Started Jan 03 12:30:03 PM PST 24
Finished Jan 03 12:31:11 PM PST 24
Peak memory 212288 kb
Host smart-ddea4e15-94c9-45aa-aca5-79991b8ede16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753520980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2753520980
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.394051084
Short name T345
Test name
Test status
Simulation time 21083369660 ps
CPU time 43.08 seconds
Started Jan 03 12:41:56 PM PST 24
Finished Jan 03 12:44:08 PM PST 24
Peak memory 219084 kb
Host smart-86738cd7-7b72-4e7e-aafa-e4aa85ef3617
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394051084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.394051084
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.1177316247
Short name T316
Test name
Test status
Simulation time 73695288914 ps
CPU time 1687.33 seconds
Started Jan 03 12:28:49 PM PST 24
Finished Jan 03 12:57:26 PM PST 24
Peak memory 235388 kb
Host smart-6c061465-6443-427e-9041-a5d12ccc5db7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177316247 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.1177316247
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1693393734
Short name T151
Test name
Test status
Simulation time 2120548574 ps
CPU time 16.36 seconds
Started Jan 03 12:31:34 PM PST 24
Finished Jan 03 12:33:08 PM PST 24
Peak memory 210760 kb
Host smart-8e085c39-0b15-4c59-9f4a-424bf614b5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693393734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1693393734
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1306108451
Short name T237
Test name
Test status
Simulation time 1391898495 ps
CPU time 104.85 seconds
Started Jan 03 12:33:20 PM PST 24
Finished Jan 03 12:36:13 PM PST 24
Peak memory 237240 kb
Host smart-7aee0730-7005-4fef-8234-0a2e42f5a6dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306108451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1306108451
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3694596358
Short name T326
Test name
Test status
Simulation time 9207842797 ps
CPU time 23.49 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 210384 kb
Host smart-f3c755dc-0c2f-4044-a210-455a67cea3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694596358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3694596358
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3518920131
Short name T5
Test name
Test status
Simulation time 373424805 ps
CPU time 5.83 seconds
Started Jan 03 12:29:44 PM PST 24
Finished Jan 03 12:30:30 PM PST 24
Peak memory 210748 kb
Host smart-6aa7e507-111c-4acf-88f7-729b00e79d50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518920131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3518920131
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2568135868
Short name T336
Test name
Test status
Simulation time 6180277189 ps
CPU time 29.34 seconds
Started Jan 03 12:29:46 PM PST 24
Finished Jan 03 12:30:56 PM PST 24
Peak memory 212648 kb
Host smart-0a14d869-7ac4-426a-97d0-52de13d3be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568135868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2568135868
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.311399858
Short name T228
Test name
Test status
Simulation time 1209478559 ps
CPU time 19.19 seconds
Started Jan 03 12:26:44 PM PST 24
Finished Jan 03 12:27:04 PM PST 24
Peak memory 215184 kb
Host smart-0af6b3e7-d5ab-444f-9d3f-072393496e21
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311399858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.311399858
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2111798766
Short name T349
Test name
Test status
Simulation time 119656667615 ps
CPU time 6731.71 seconds
Started Jan 03 12:28:56 PM PST 24
Finished Jan 03 02:21:35 PM PST 24
Peak memory 232656 kb
Host smart-b707c349-9476-48fb-9946-c6763eb9873c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111798766 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2111798766
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.535295186
Short name T184
Test name
Test status
Simulation time 3262144667 ps
CPU time 13.59 seconds
Started Jan 03 12:32:15 PM PST 24
Finished Jan 03 12:33:57 PM PST 24
Peak memory 210872 kb
Host smart-7157a4d3-bd58-465a-8dc1-5e8b118bd743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535295186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.535295186
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3544523328
Short name T212
Test name
Test status
Simulation time 31661136132 ps
CPU time 315.37 seconds
Started Jan 03 12:42:55 PM PST 24
Finished Jan 03 12:49:32 PM PST 24
Peak memory 237396 kb
Host smart-6aa46614-bccd-4cfb-bd9b-88bed6c309b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544523328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3544523328
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2240650295
Short name T307
Test name
Test status
Simulation time 3460870340 ps
CPU time 29.52 seconds
Started Jan 03 12:31:38 PM PST 24
Finished Jan 03 12:33:29 PM PST 24
Peak memory 210836 kb
Host smart-b97974d4-ba18-4de7-a45d-633828042b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240650295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2240650295
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3836108526
Short name T199
Test name
Test status
Simulation time 3265073732 ps
CPU time 14.59 seconds
Started Jan 03 12:30:00 PM PST 24
Finished Jan 03 12:30:59 PM PST 24
Peak memory 210344 kb
Host smart-7f4c36fa-da8f-4d0e-8e6f-21a415cf1dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836108526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3836108526
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2507237431
Short name T417
Test name
Test status
Simulation time 5242247122 ps
CPU time 31.75 seconds
Started Jan 03 12:35:17 PM PST 24
Finished Jan 03 12:37:29 PM PST 24
Peak memory 211980 kb
Host smart-608cd5b2-ee52-4afa-a4fc-999b69beb66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507237431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2507237431
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1954445468
Short name T239
Test name
Test status
Simulation time 1291347580 ps
CPU time 19.47 seconds
Started Jan 03 12:29:18 PM PST 24
Finished Jan 03 12:30:05 PM PST 24
Peak memory 213996 kb
Host smart-c096bbb2-fe11-4cf0-90e1-6cf1f80e6e2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954445468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1954445468
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.1011416181
Short name T297
Test name
Test status
Simulation time 162874175410 ps
CPU time 9241.03 seconds
Started Jan 03 12:29:44 PM PST 24
Finished Jan 03 03:04:27 PM PST 24
Peak memory 243740 kb
Host smart-e5db5223-1de5-42d9-8d6a-f9fda39beebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011416181 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.1011416181
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3950899040
Short name T403
Test name
Test status
Simulation time 2400263652 ps
CPU time 8.11 seconds
Started Jan 03 12:28:32 PM PST 24
Finished Jan 03 12:28:57 PM PST 24
Peak memory 210848 kb
Host smart-60fbadd6-5c96-4ae3-9211-1ad73165fe08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950899040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3950899040
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1651414814
Short name T208
Test name
Test status
Simulation time 36976565142 ps
CPU time 327.73 seconds
Started Jan 03 12:29:00 PM PST 24
Finished Jan 03 12:34:54 PM PST 24
Peak memory 227292 kb
Host smart-99fdebd2-176f-4255-b1b4-c71bebd86f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651414814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1651414814
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.2158286142
Short name T31
Test name
Test status
Simulation time 367370245 ps
CPU time 11.86 seconds
Started Jan 03 12:28:26 PM PST 24
Finished Jan 03 12:28:49 PM PST 24
Peak memory 210836 kb
Host smart-cb9b95c2-09ff-4c93-bf57-429bcca5e8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158286142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.2158286142
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.4266030573
Short name T412
Test name
Test status
Simulation time 2951126067 ps
CPU time 14 seconds
Started Jan 03 12:29:55 PM PST 24
Finished Jan 03 12:30:51 PM PST 24
Peak memory 210668 kb
Host smart-f74a53e4-bd51-47e6-808e-84fc61b89710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4266030573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.4266030573
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3917762433
Short name T409
Test name
Test status
Simulation time 7396704998 ps
CPU time 41.56 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:43 PM PST 24
Peak memory 213544 kb
Host smart-da690d70-7252-49cc-b9db-dbf5c3dc66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917762433 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3917762433
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.3976386619
Short name T186
Test name
Test status
Simulation time 1599318861 ps
CPU time 13.06 seconds
Started Jan 03 12:29:32 PM PST 24
Finished Jan 03 12:30:19 PM PST 24
Peak memory 210752 kb
Host smart-1ab570fa-7346-42ee-93fc-2d62339bb889
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976386619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.3976386619
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2012404464
Short name T153
Test name
Test status
Simulation time 922523215 ps
CPU time 10.17 seconds
Started Jan 03 12:28:50 PM PST 24
Finished Jan 03 12:29:29 PM PST 24
Peak memory 210760 kb
Host smart-b09ea319-b1c8-498d-9055-3e4aa23a5c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012404464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2012404464
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4170673880
Short name T375
Test name
Test status
Simulation time 240771161498 ps
CPU time 547.71 seconds
Started Jan 03 12:29:50 PM PST 24
Finished Jan 03 12:39:39 PM PST 24
Peak memory 223920 kb
Host smart-d7f034ab-fea9-405c-8cb4-06750fecb536
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170673880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4170673880
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3469399208
Short name T276
Test name
Test status
Simulation time 1185484364 ps
CPU time 13.46 seconds
Started Jan 03 12:29:37 PM PST 24
Finished Jan 03 12:30:27 PM PST 24
Peak memory 210956 kb
Host smart-4c1522c8-cae6-4468-8d7a-5e01bc793e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469399208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3469399208
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.265658558
Short name T194
Test name
Test status
Simulation time 146976567 ps
CPU time 5.88 seconds
Started Jan 03 12:30:06 PM PST 24
Finished Jan 03 12:30:56 PM PST 24
Peak memory 210772 kb
Host smart-3ab8132f-22a0-4233-a252-b2825f92c663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265658558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.265658558
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4294136424
Short name T9
Test name
Test status
Simulation time 866972528 ps
CPU time 13.03 seconds
Started Jan 03 12:29:37 PM PST 24
Finished Jan 03 12:30:26 PM PST 24
Peak memory 211224 kb
Host smart-2a8609a9-319b-4a56-8819-bbe4b0e9c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294136424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4294136424
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.2774249561
Short name T257
Test name
Test status
Simulation time 5262916175 ps
CPU time 33.61 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:35 PM PST 24
Peak memory 215956 kb
Host smart-c17aba17-1393-49cb-a19a-5aa8f41fbb29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774249561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.2774249561
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2765408573
Short name T216
Test name
Test status
Simulation time 18786473101 ps
CPU time 2313.79 seconds
Started Jan 03 12:28:50 PM PST 24
Finished Jan 03 01:07:53 PM PST 24
Peak memory 226508 kb
Host smart-61e1eccb-c225-4ff1-9027-da895b18e233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765408573 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2765408573
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3785229951
Short name T340
Test name
Test status
Simulation time 85475228 ps
CPU time 4.27 seconds
Started Jan 03 12:28:32 PM PST 24
Finished Jan 03 12:28:51 PM PST 24
Peak memory 210796 kb
Host smart-ad1bba3d-e957-4cac-b494-116be073b352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785229951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3785229951
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3116960930
Short name T296
Test name
Test status
Simulation time 1961214089 ps
CPU time 111.86 seconds
Started Jan 03 12:29:37 PM PST 24
Finished Jan 03 12:32:05 PM PST 24
Peak memory 237216 kb
Host smart-99dc19d3-af0b-412d-8cf3-b95c730996e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116960930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3116960930
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2347483686
Short name T385
Test name
Test status
Simulation time 3948664436 ps
CPU time 22.84 seconds
Started Jan 03 12:29:57 PM PST 24
Finished Jan 03 12:31:04 PM PST 24
Peak memory 210936 kb
Host smart-33228e76-f2c5-498b-bdfc-30a5a07c2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347483686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2347483686
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3938859305
Short name T146
Test name
Test status
Simulation time 2517000100 ps
CPU time 12.68 seconds
Started Jan 03 12:31:44 PM PST 24
Finished Jan 03 12:33:24 PM PST 24
Peak memory 210872 kb
Host smart-bdc208f2-0047-4580-a2e9-fa2f82dbd37b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938859305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3938859305
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1254664816
Short name T152
Test name
Test status
Simulation time 3429863127 ps
CPU time 24.01 seconds
Started Jan 03 12:30:29 PM PST 24
Finished Jan 03 12:31:53 PM PST 24
Peak memory 210936 kb
Host smart-e9f51ff1-57d7-432e-a1b8-d570f6a6eb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254664816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1254664816
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.4162019663
Short name T259
Test name
Test status
Simulation time 9357717003 ps
CPU time 15.23 seconds
Started Jan 03 12:28:37 PM PST 24
Finished Jan 03 12:29:09 PM PST 24
Peak memory 211700 kb
Host smart-bdade16f-d19e-4d57-9932-3ee7fa76fe1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162019663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.4162019663
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3411530811
Short name T234
Test name
Test status
Simulation time 175656506 ps
CPU time 4.21 seconds
Started Jan 03 12:28:54 PM PST 24
Finished Jan 03 12:29:25 PM PST 24
Peak memory 210824 kb
Host smart-f293f191-5a82-4260-89ec-073f06eac7de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411530811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3411530811
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4272160969
Short name T42
Test name
Test status
Simulation time 102451973412 ps
CPU time 314.64 seconds
Started Jan 03 12:29:21 PM PST 24
Finished Jan 03 12:35:05 PM PST 24
Peak memory 227676 kb
Host smart-a62509ca-7242-4e0e-baeb-1f96105dd8c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272160969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4272160969
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.2901083360
Short name T147
Test name
Test status
Simulation time 26497487535 ps
CPU time 24.77 seconds
Started Jan 03 12:29:31 PM PST 24
Finished Jan 03 12:30:30 PM PST 24
Peak memory 211328 kb
Host smart-bce56125-aca3-405f-b498-6481ac7701e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901083360 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.2901083360
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3743878203
Short name T308
Test name
Test status
Simulation time 361052673 ps
CPU time 7.91 seconds
Started Jan 03 12:29:54 PM PST 24
Finished Jan 03 12:30:44 PM PST 24
Peak memory 210656 kb
Host smart-fcce84eb-dc2d-4eb8-a593-58bead048720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743878203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3743878203
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.668278751
Short name T295
Test name
Test status
Simulation time 1098622233 ps
CPU time 12.12 seconds
Started Jan 03 12:33:53 PM PST 24
Finished Jan 03 12:35:21 PM PST 24
Peak memory 212456 kb
Host smart-31b6b1a8-5e69-462a-b7d9-e6dced7f177a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668278751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.668278751
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.437445282
Short name T247
Test name
Test status
Simulation time 7785095307 ps
CPU time 75.39 seconds
Started Jan 03 12:33:07 PM PST 24
Finished Jan 03 12:35:55 PM PST 24
Peak memory 218924 kb
Host smart-600deca3-3092-46d8-80e7-c82af7a93c20
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437445282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.rom_ctrl_stress_all.437445282
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.3479606364
Short name T415
Test name
Test status
Simulation time 1797393312 ps
CPU time 14.73 seconds
Started Jan 03 12:29:54 PM PST 24
Finished Jan 03 12:30:52 PM PST 24
Peak memory 210792 kb
Host smart-ac713142-250d-4d1b-a094-302235990811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479606364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.3479606364
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2254588311
Short name T270
Test name
Test status
Simulation time 174322901749 ps
CPU time 394.3 seconds
Started Jan 03 12:38:28 PM PST 24
Finished Jan 03 12:46:14 PM PST 24
Peak memory 212200 kb
Host smart-c591e5a6-1250-4176-8fdc-014c12c460a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254588311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2254588311
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3040204116
Short name T312
Test name
Test status
Simulation time 18503962479 ps
CPU time 33.38 seconds
Started Jan 03 12:29:53 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 210988 kb
Host smart-19d65669-37b0-4d97-9137-3454157c5bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040204116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3040204116
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.2456909086
Short name T148
Test name
Test status
Simulation time 1316760981 ps
CPU time 13.28 seconds
Started Jan 03 12:29:34 PM PST 24
Finished Jan 03 12:30:23 PM PST 24
Peak memory 210744 kb
Host smart-1a02f597-73f7-47d0-929b-1e3f4de06918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2456909086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.2456909086
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.835364155
Short name T220
Test name
Test status
Simulation time 13374536291 ps
CPU time 31.41 seconds
Started Jan 03 12:30:34 PM PST 24
Finished Jan 03 12:32:07 PM PST 24
Peak memory 212872 kb
Host smart-83c26942-5cfc-4d81-b7ff-ead09ccb8765
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835364155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.rom_ctrl_stress_all.835364155
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.3031687984
Short name T405
Test name
Test status
Simulation time 30288915478 ps
CPU time 2800.03 seconds
Started Jan 03 12:29:04 PM PST 24
Finished Jan 03 01:16:11 PM PST 24
Peak memory 234176 kb
Host smart-c87dd531-7fa7-46e0-999f-33e9f00b623d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031687984 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.3031687984
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4071124842
Short name T364
Test name
Test status
Simulation time 1106377550 ps
CPU time 10.93 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:31:05 PM PST 24
Peak memory 210532 kb
Host smart-3c63954d-bcbc-4492-b17f-d2a85ca6f963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071124842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4071124842
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3454080833
Short name T52
Test name
Test status
Simulation time 35708394031 ps
CPU time 297.34 seconds
Started Jan 03 12:25:43 PM PST 24
Finished Jan 03 12:30:42 PM PST 24
Peak memory 213060 kb
Host smart-f73f6511-bfbb-4062-9368-fb83ca1ae3a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454080833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3454080833
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.4098372375
Short name T206
Test name
Test status
Simulation time 2251491673 ps
CPU time 23.66 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:29:14 PM PST 24
Peak memory 210848 kb
Host smart-7584ac45-5f1c-4094-b0d8-2fef03f343d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098372375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.4098372375
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.727438199
Short name T303
Test name
Test status
Simulation time 490173194 ps
CPU time 7.32 seconds
Started Jan 03 12:28:34 PM PST 24
Finished Jan 03 12:28:59 PM PST 24
Peak memory 210352 kb
Host smart-7f3e35b7-b275-44b6-841f-7a83ada6f81a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727438199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.727438199
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2571821626
Short name T299
Test name
Test status
Simulation time 8056225446 ps
CPU time 42.45 seconds
Started Jan 03 12:27:15 PM PST 24
Finished Jan 03 12:27:59 PM PST 24
Peak memory 212916 kb
Host smart-cd56874d-6f0f-4805-b589-e828551cb667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571821626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2571821626
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3198643272
Short name T142
Test name
Test status
Simulation time 1982931859 ps
CPU time 21.63 seconds
Started Jan 03 12:30:35 PM PST 24
Finished Jan 03 12:31:58 PM PST 24
Peak memory 215236 kb
Host smart-d4f3a5a0-c890-4e3d-95fe-f971bf159769
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198643272 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3198643272
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.257089651
Short name T263
Test name
Test status
Simulation time 65424644945 ps
CPU time 2021.49 seconds
Started Jan 03 12:27:31 PM PST 24
Finished Jan 03 01:01:18 PM PST 24
Peak memory 228652 kb
Host smart-c4eb8cc0-0256-4928-b3f1-0904b4d09588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257089651 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.257089651
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1357239479
Short name T310
Test name
Test status
Simulation time 15333700605 ps
CPU time 12.69 seconds
Started Jan 03 12:29:19 PM PST 24
Finished Jan 03 12:30:01 PM PST 24
Peak memory 210592 kb
Host smart-2738b7b2-02de-419e-afce-901f878943b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357239479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1357239479
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2123258642
Short name T18
Test name
Test status
Simulation time 5004471938 ps
CPU time 66.63 seconds
Started Jan 03 12:30:29 PM PST 24
Finished Jan 03 12:32:35 PM PST 24
Peak memory 236028 kb
Host smart-6aa7e66a-dbab-4bc7-a203-a7e5e0a10fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123258642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.2123258642
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.4132670720
Short name T166
Test name
Test status
Simulation time 23920239921 ps
CPU time 29.24 seconds
Started Jan 03 12:25:54 PM PST 24
Finished Jan 03 12:26:24 PM PST 24
Peak memory 211292 kb
Host smart-5a7e2f0f-f2de-4509-b35c-d545625973ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132670720 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.4132670720
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3918904368
Short name T143
Test name
Test status
Simulation time 28677957871 ps
CPU time 14.31 seconds
Started Jan 03 12:30:29 PM PST 24
Finished Jan 03 12:31:43 PM PST 24
Peak memory 209812 kb
Host smart-29039ee7-62ee-444b-bd37-142e64652b4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918904368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3918904368
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.627398290
Short name T175
Test name
Test status
Simulation time 4340822370 ps
CPU time 33.6 seconds
Started Jan 03 12:27:24 PM PST 24
Finished Jan 03 12:28:03 PM PST 24
Peak memory 212384 kb
Host smart-1e92d05b-0b8a-40fb-88ac-68b9c822666f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627398290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.627398290
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1359839381
Short name T258
Test name
Test status
Simulation time 771606484 ps
CPU time 23.69 seconds
Started Jan 03 12:27:00 PM PST 24
Finished Jan 03 12:27:29 PM PST 24
Peak memory 212400 kb
Host smart-ca318595-3794-491d-8c4c-5b4b4af9a233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359839381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1359839381
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.572716114
Short name T229
Test name
Test status
Simulation time 14686417655 ps
CPU time 500.19 seconds
Started Jan 03 12:28:35 PM PST 24
Finished Jan 03 12:37:12 PM PST 24
Peak memory 221728 kb
Host smart-40716107-84d5-44f6-8085-32002840c70a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572716114 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.572716114
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.870280402
Short name T168
Test name
Test status
Simulation time 1419437851 ps
CPU time 12.81 seconds
Started Jan 03 12:30:08 PM PST 24
Finished Jan 03 12:31:08 PM PST 24
Peak memory 210564 kb
Host smart-07b27786-fb79-4b49-bbe4-025cb145620e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870280402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.870280402
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3137281835
Short name T39
Test name
Test status
Simulation time 38884458180 ps
CPU time 168.22 seconds
Started Jan 03 12:30:07 PM PST 24
Finished Jan 03 12:33:41 PM PST 24
Peak memory 224804 kb
Host smart-b6a1ea8b-6781-4a63-bef5-210d9c28373f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137281835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3137281835
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.7669295
Short name T213
Test name
Test status
Simulation time 12234877404 ps
CPU time 30.3 seconds
Started Jan 03 12:46:54 PM PST 24
Finished Jan 03 12:48:30 PM PST 24
Peak memory 211256 kb
Host smart-a3caf248-4e86-4f0e-a635-5ac687abc8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7669295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.7669295
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1981942457
Short name T319
Test name
Test status
Simulation time 15766759932 ps
CPU time 15.74 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:30:50 PM PST 24
Peak memory 209508 kb
Host smart-dc759597-33bc-4030-aa0d-d15bb9540c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1981942457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1981942457
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3367800980
Short name T93
Test name
Test status
Simulation time 15501565036 ps
CPU time 18.79 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:28:01 PM PST 24
Peak memory 212652 kb
Host smart-f225c7f7-57ea-4e8b-9c74-d37de789ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367800980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3367800980
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4081700824
Short name T16
Test name
Test status
Simulation time 1071763871 ps
CPU time 13.31 seconds
Started Jan 03 12:27:38 PM PST 24
Finished Jan 03 12:27:56 PM PST 24
Peak memory 210724 kb
Host smart-d7208a97-9dde-488f-ad76-0c6a5d95f81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081700824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4081700824
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1065290804
Short name T344
Test name
Test status
Simulation time 20855802397 ps
CPU time 1096.93 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:47:19 PM PST 24
Peak memory 229784 kb
Host smart-31d788b8-b79b-4149-a363-4a6f0ceb0393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065290804 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1065290804
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1168226237
Short name T365
Test name
Test status
Simulation time 1761405843 ps
CPU time 15.14 seconds
Started Jan 03 12:41:49 PM PST 24
Finished Jan 03 12:43:31 PM PST 24
Peak memory 210800 kb
Host smart-43bf4fb8-6422-4197-ab88-69a47e25da23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168226237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1168226237
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.1985275284
Short name T413
Test name
Test status
Simulation time 6055633785 ps
CPU time 85.08 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:30:27 PM PST 24
Peak memory 235156 kb
Host smart-e6f0d941-96c5-43ac-8b57-7c3959631e45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985275284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.1985275284
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.575098802
Short name T205
Test name
Test status
Simulation time 170249272 ps
CPU time 9.49 seconds
Started Jan 03 12:29:29 PM PST 24
Finished Jan 03 12:30:12 PM PST 24
Peak memory 210680 kb
Host smart-109468af-111d-46f7-ae7a-507f0d689127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575098802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.575098802
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.432106641
Short name T224
Test name
Test status
Simulation time 582156890 ps
CPU time 9.33 seconds
Started Jan 03 12:28:41 PM PST 24
Finished Jan 03 12:29:11 PM PST 24
Peak memory 208660 kb
Host smart-4be8ca28-08d8-4605-9ef7-615090c564f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432106641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.432106641
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3546182229
Short name T390
Test name
Test status
Simulation time 9020422199 ps
CPU time 26.35 seconds
Started Jan 03 12:36:16 PM PST 24
Finished Jan 03 12:38:21 PM PST 24
Peak memory 212620 kb
Host smart-cedb3768-c2b6-4a4b-8ae0-97c3d8be99b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546182229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3546182229
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3082490641
Short name T392
Test name
Test status
Simulation time 10489527405 ps
CPU time 43.7 seconds
Started Jan 03 12:29:52 PM PST 24
Finished Jan 03 12:31:18 PM PST 24
Peak memory 215980 kb
Host smart-b430d52a-cde7-45a5-85a0-71c5ef94428d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082490641 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3082490641
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3357269669
Short name T408
Test name
Test status
Simulation time 119470032124 ps
CPU time 6003.82 seconds
Started Jan 03 12:30:09 PM PST 24
Finished Jan 03 02:11:00 PM PST 24
Peak memory 236572 kb
Host smart-3b788e83-8886-4d52-8113-fb47661a0670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357269669 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3357269669
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1725524183
Short name T189
Test name
Test status
Simulation time 1873257011 ps
CPU time 5.76 seconds
Started Jan 03 12:30:23 PM PST 24
Finished Jan 03 12:31:24 PM PST 24
Peak memory 210020 kb
Host smart-75f357f1-c2ce-4d05-bd20-b8088fd78a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725524183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1725524183
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3140875326
Short name T195
Test name
Test status
Simulation time 3612461540 ps
CPU time 127.16 seconds
Started Jan 03 12:29:20 PM PST 24
Finished Jan 03 12:31:57 PM PST 24
Peak memory 227084 kb
Host smart-b4df3440-482e-42aa-af9c-be76dcc4e4ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140875326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3140875326
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.3472118296
Short name T30
Test name
Test status
Simulation time 723064066 ps
CPU time 9.43 seconds
Started Jan 03 12:29:30 PM PST 24
Finished Jan 03 12:30:13 PM PST 24
Peak memory 210688 kb
Host smart-21d6fee2-041c-4036-8f8d-7ce95e4eaffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472118296 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.3472118296
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2344468073
Short name T317
Test name
Test status
Simulation time 3143927691 ps
CPU time 14.23 seconds
Started Jan 03 12:23:47 PM PST 24
Finished Jan 03 12:24:03 PM PST 24
Peak memory 210860 kb
Host smart-a57e1797-b791-4c9f-97fb-61d9a74332c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2344468073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2344468073
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.2653247845
Short name T180
Test name
Test status
Simulation time 4804142099 ps
CPU time 27.46 seconds
Started Jan 03 12:29:29 PM PST 24
Finished Jan 03 12:30:30 PM PST 24
Peak memory 212560 kb
Host smart-624359ed-8fe1-4a42-ab96-bc32403c8e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653247845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.2653247845
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3513069535
Short name T253
Test name
Test status
Simulation time 6841662522 ps
CPU time 79.95 seconds
Started Jan 03 12:22:39 PM PST 24
Finished Jan 03 12:24:00 PM PST 24
Peak memory 215856 kb
Host smart-4feeb5aa-1b10-4d53-8040-61cebd8f070f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513069535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3513069535
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.889480274
Short name T391
Test name
Test status
Simulation time 73719600628 ps
CPU time 2595.08 seconds
Started Jan 03 12:30:40 PM PST 24
Finished Jan 03 01:14:59 PM PST 24
Peak memory 235156 kb
Host smart-3465c636-b4b4-4543-8990-a73c0177e130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889480274 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.889480274
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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