Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.49 97.11 92.68 97.88 100.00 98.37 98.04 98.38


Total test records in report: 347
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T61 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1425368968 Jan 07 12:29:33 PM PST 24 Jan 07 12:31:15 PM PST 24 5996353603 ps
T62 /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3858369603 Jan 07 12:25:39 PM PST 24 Jan 07 12:26:54 PM PST 24 5086145808 ps
T63 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3439029997 Jan 07 12:27:19 PM PST 24 Jan 07 12:28:36 PM PST 24 112385101 ps
T64 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2701617654 Jan 07 12:41:45 PM PST 24 Jan 07 12:43:25 PM PST 24 1566343587 ps
T50 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1375361146 Jan 07 12:30:53 PM PST 24 Jan 07 12:33:20 PM PST 24 870429603 ps
T107 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3965782092 Jan 07 12:31:11 PM PST 24 Jan 07 12:32:41 PM PST 24 10045545586 ps
T288 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4225178456 Jan 07 12:28:48 PM PST 24 Jan 07 12:30:29 PM PST 24 2183614365 ps
T289 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2321530474 Jan 07 12:27:58 PM PST 24 Jan 07 12:29:02 PM PST 24 121992907 ps
T290 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2465241121 Jan 07 12:25:31 PM PST 24 Jan 07 12:26:46 PM PST 24 1652253129 ps
T291 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4055532534 Jan 07 12:31:15 PM PST 24 Jan 07 12:33:19 PM PST 24 3996432476 ps
T72 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2940907378 Jan 07 12:29:32 PM PST 24 Jan 07 12:31:59 PM PST 24 6355145470 ps
T73 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4243585480 Jan 07 12:29:36 PM PST 24 Jan 07 12:31:13 PM PST 24 85809845 ps
T82 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2092308076 Jan 07 12:29:05 PM PST 24 Jan 07 12:30:44 PM PST 24 3853287292 ps
T83 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3078933598 Jan 07 12:34:17 PM PST 24 Jan 07 12:36:56 PM PST 24 2032616444 ps
T84 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.940192745 Jan 07 12:30:04 PM PST 24 Jan 07 12:32:45 PM PST 24 866043442 ps
T85 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3607792032 Jan 07 12:28:47 PM PST 24 Jan 07 12:30:30 PM PST 24 4443324424 ps
T74 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.237329966 Jan 07 12:28:22 PM PST 24 Jan 07 12:29:39 PM PST 24 1658727817 ps
T86 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2225105010 Jan 07 12:29:08 PM PST 24 Jan 07 12:32:19 PM PST 24 1589358204 ps
T87 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2440463904 Jan 07 12:28:28 PM PST 24 Jan 07 12:29:47 PM PST 24 7985060014 ps
T88 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2397903773 Jan 07 12:33:54 PM PST 24 Jan 07 12:35:09 PM PST 24 836167219 ps
T292 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1375042754 Jan 07 12:25:21 PM PST 24 Jan 07 12:26:40 PM PST 24 2062599775 ps
T116 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1034891032 Jan 07 12:29:05 PM PST 24 Jan 07 12:32:17 PM PST 24 863856677 ps
T75 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3408607287 Jan 07 12:35:23 PM PST 24 Jan 07 12:37:19 PM PST 24 3855446699 ps
T76 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.482920724 Jan 07 12:29:35 PM PST 24 Jan 07 12:31:40 PM PST 24 8499257669 ps
T77 /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2569197432 Jan 07 12:30:16 PM PST 24 Jan 07 12:33:39 PM PST 24 8102523942 ps
T115 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3058358536 Jan 07 12:27:28 PM PST 24 Jan 07 12:29:59 PM PST 24 8705790182 ps
T119 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3076198020 Jan 07 12:30:23 PM PST 24 Jan 07 12:33:10 PM PST 24 3149083524 ps
T293 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.315423162 Jan 07 12:31:32 PM PST 24 Jan 07 12:33:21 PM PST 24 516079932 ps
T108 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4084016430 Jan 07 12:27:30 PM PST 24 Jan 07 12:29:11 PM PST 24 7272796119 ps
T294 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2496061225 Jan 07 12:29:03 PM PST 24 Jan 07 12:30:26 PM PST 24 1115559824 ps
T78 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4068626384 Jan 07 12:27:28 PM PST 24 Jan 07 12:32:31 PM PST 24 34447043683 ps
T295 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4289923395 Jan 07 12:29:38 PM PST 24 Jan 07 12:31:49 PM PST 24 707493121 ps
T296 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1827358166 Jan 07 12:29:10 PM PST 24 Jan 07 12:31:01 PM PST 24 1399685903 ps
T297 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.614571710 Jan 07 12:31:35 PM PST 24 Jan 07 12:33:20 PM PST 24 1534257515 ps
T298 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1038686201 Jan 07 12:27:15 PM PST 24 Jan 07 12:28:48 PM PST 24 775322138 ps
T299 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.315485558 Jan 07 12:30:18 PM PST 24 Jan 07 12:32:01 PM PST 24 11838347673 ps
T300 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1570398174 Jan 07 12:28:53 PM PST 24 Jan 07 12:30:19 PM PST 24 1782989741 ps
T79 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.801224236 Jan 07 12:27:36 PM PST 24 Jan 07 12:28:54 PM PST 24 2996486874 ps
T301 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2293657235 Jan 07 12:29:06 PM PST 24 Jan 07 12:30:40 PM PST 24 1405368806 ps
T120 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3374166697 Jan 07 12:28:41 PM PST 24 Jan 07 12:30:44 PM PST 24 1354601306 ps
T121 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.966428304 Jan 07 12:28:10 PM PST 24 Jan 07 12:30:29 PM PST 24 1677713024 ps
T80 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.205224969 Jan 07 12:28:41 PM PST 24 Jan 07 12:32:44 PM PST 24 11157595355 ps
T302 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2593087309 Jan 07 12:27:53 PM PST 24 Jan 07 12:29:15 PM PST 24 1875124141 ps
T303 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.792747420 Jan 07 12:27:37 PM PST 24 Jan 07 12:29:03 PM PST 24 1253899504 ps
T81 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3779695230 Jan 07 12:30:03 PM PST 24 Jan 07 12:38:19 PM PST 24 55624637595 ps
T304 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2028393508 Jan 07 12:29:33 PM PST 24 Jan 07 12:31:02 PM PST 24 346357499 ps
T305 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.301906165 Jan 07 12:27:13 PM PST 24 Jan 07 12:28:39 PM PST 24 3680225845 ps
T306 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1529075741 Jan 07 12:29:34 PM PST 24 Jan 07 12:31:14 PM PST 24 12123678524 ps
T93 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3946146961 Jan 07 12:30:05 PM PST 24 Jan 07 12:32:54 PM PST 24 6170071109 ps
T307 /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2205927177 Jan 07 12:30:50 PM PST 24 Jan 07 12:33:00 PM PST 24 7375848313 ps
T308 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.228471816 Jan 07 12:30:04 PM PST 24 Jan 07 12:31:45 PM PST 24 670571266 ps
T309 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.907466006 Jan 07 12:28:48 PM PST 24 Jan 07 12:30:29 PM PST 24 332526848 ps
T310 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2222346291 Jan 07 12:27:28 PM PST 24 Jan 07 12:29:03 PM PST 24 8709275383 ps
T311 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3742871026 Jan 07 12:31:05 PM PST 24 Jan 07 12:33:18 PM PST 24 98180363 ps
T312 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1672228437 Jan 07 12:27:28 PM PST 24 Jan 07 12:29:31 PM PST 24 669518413 ps
T313 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3038432309 Jan 07 12:29:35 PM PST 24 Jan 07 12:31:10 PM PST 24 5525163020 ps
T314 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3287849861 Jan 07 12:31:08 PM PST 24 Jan 07 12:32:44 PM PST 24 86682278 ps
T315 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1869741580 Jan 07 12:27:09 PM PST 24 Jan 07 12:28:31 PM PST 24 85559461 ps
T89 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.247606274 Jan 07 12:30:56 PM PST 24 Jan 07 12:35:25 PM PST 24 20972715117 ps
T117 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.997509101 Jan 07 12:27:28 PM PST 24 Jan 07 12:29:55 PM PST 24 2457578632 ps
T90 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.395972180 Jan 07 12:28:56 PM PST 24 Jan 07 12:33:53 PM PST 24 23351879134 ps
T316 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3494180111 Jan 07 12:29:06 PM PST 24 Jan 07 12:30:42 PM PST 24 636621485 ps
T317 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2854821039 Jan 07 12:27:30 PM PST 24 Jan 07 12:28:42 PM PST 24 89245601 ps
T118 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.205585532 Jan 07 12:30:16 PM PST 24 Jan 07 12:33:19 PM PST 24 3605288363 ps
T318 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.214083048 Jan 07 12:31:21 PM PST 24 Jan 07 12:32:48 PM PST 24 2467284535 ps
T94 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3986219019 Jan 07 12:31:45 PM PST 24 Jan 07 12:33:24 PM PST 24 6982571914 ps
T319 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1298486768 Jan 07 12:27:06 PM PST 24 Jan 07 12:28:28 PM PST 24 336047607 ps
T320 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2547406035 Jan 07 12:27:09 PM PST 24 Jan 07 12:28:24 PM PST 24 127678221 ps
T321 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3685885480 Jan 07 12:27:28 PM PST 24 Jan 07 12:30:10 PM PST 24 1231573473 ps
T322 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3704810388 Jan 07 12:30:18 PM PST 24 Jan 07 12:32:01 PM PST 24 9273324966 ps
T323 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.407205744 Jan 07 12:31:20 PM PST 24 Jan 07 12:33:58 PM PST 24 2090622092 ps
T324 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1386254335 Jan 07 12:29:32 PM PST 24 Jan 07 12:31:56 PM PST 24 5474004743 ps
T325 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4071545048 Jan 07 12:27:36 PM PST 24 Jan 07 12:28:55 PM PST 24 1632054796 ps
T326 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2359386805 Jan 07 12:28:21 PM PST 24 Jan 07 12:29:45 PM PST 24 789745462 ps
T327 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3228519557 Jan 07 12:25:21 PM PST 24 Jan 07 12:29:37 PM PST 24 21218497384 ps
T328 /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1094552916 Jan 07 12:29:20 PM PST 24 Jan 07 12:37:07 PM PST 24 161728612098 ps
T329 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1714180480 Jan 07 12:29:05 PM PST 24 Jan 07 12:30:43 PM PST 24 174931434 ps
T330 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.161353098 Jan 07 12:27:07 PM PST 24 Jan 07 12:28:34 PM PST 24 6722052943 ps
T331 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2787893851 Jan 07 12:31:19 PM PST 24 Jan 07 12:32:40 PM PST 24 85738222 ps
T332 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3884289553 Jan 07 12:29:09 PM PST 24 Jan 07 12:31:05 PM PST 24 2200600373 ps
T333 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1884322551 Jan 07 12:28:26 PM PST 24 Jan 07 12:29:39 PM PST 24 11885247742 ps
T334 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1967861129 Jan 07 12:29:03 PM PST 24 Jan 07 12:30:58 PM PST 24 1827728944 ps
T91 /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3941801073 Jan 07 12:29:38 PM PST 24 Jan 07 12:35:22 PM PST 24 20692209096 ps
T335 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.184180518 Jan 07 12:28:03 PM PST 24 Jan 07 12:30:34 PM PST 24 3584475545 ps
T336 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4279746041 Jan 07 12:31:12 PM PST 24 Jan 07 12:33:07 PM PST 24 1522650220 ps
T337 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3187840320 Jan 07 12:29:32 PM PST 24 Jan 07 12:31:10 PM PST 24 347073643 ps
T338 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2949650899 Jan 07 12:31:35 PM PST 24 Jan 07 12:33:34 PM PST 24 1738229275 ps
T339 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2909852674 Jan 07 12:27:28 PM PST 24 Jan 07 12:29:06 PM PST 24 11441806263 ps
T92 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.751135120 Jan 07 12:29:56 PM PST 24 Jan 07 12:34:18 PM PST 24 13416069985 ps
T340 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2720809447 Jan 07 12:30:48 PM PST 24 Jan 07 12:32:23 PM PST 24 1098844422 ps
T341 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.960725881 Jan 07 12:27:21 PM PST 24 Jan 07 12:31:11 PM PST 24 24248421394 ps
T342 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3825351805 Jan 07 12:29:15 PM PST 24 Jan 07 12:30:43 PM PST 24 237275158 ps
T343 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2337396821 Jan 07 12:25:34 PM PST 24 Jan 07 12:27:00 PM PST 24 20453081044 ps
T344 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2205851933 Jan 07 12:42:14 PM PST 24 Jan 07 12:44:06 PM PST 24 7512095267 ps
T345 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.861224847 Jan 07 12:27:33 PM PST 24 Jan 07 12:29:04 PM PST 24 377097502 ps
T346 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2463655432 Jan 07 12:28:14 PM PST 24 Jan 07 12:29:23 PM PST 24 1104233350 ps
T347 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1820937007 Jan 07 12:29:03 PM PST 24 Jan 07 12:30:31 PM PST 24 3445479137 ps

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3191862404
Short name T4
Test name
Test status
Simulation time 95176996388 ps
CPU time 254.89 seconds
Started Jan 07 12:29:06 PM PST 24
Finished Jan 07 12:35:03 PM PST 24
Peak memory 224076 kb
Host smart-85d42a5d-6b38-46b6-99b0-287095fe67af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191862404 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.3191862404
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2309703180
Short name T13
Test name
Test status
Simulation time 57565795571 ps
CPU time 10486.5 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 03:28:27 PM PST 24
Peak memory 233560 kb
Host smart-91b0ce4b-5fa8-4bfb-bea5-1c9c97a794ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309703180 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.2309703180
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2542465029
Short name T49
Test name
Test status
Simulation time 13955733558 ps
CPU time 45.13 seconds
Started Jan 07 12:27:47 PM PST 24
Finished Jan 07 12:29:36 PM PST 24
Peak memory 212188 kb
Host smart-0c31dc48-276e-4083-8ab0-21f7e2e4b780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542465029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2542465029
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.3581385353
Short name T22
Test name
Test status
Simulation time 58517305290 ps
CPU time 366.9 seconds
Started Jan 07 12:30:25 PM PST 24
Finished Jan 07 12:38:15 PM PST 24
Peak memory 234480 kb
Host smart-ab3f6432-9352-4eab-8de7-3613d8425a8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581385353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.3581385353
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1941742036
Short name T37
Test name
Test status
Simulation time 7464506412 ps
CPU time 112.06 seconds
Started Jan 07 12:31:32 PM PST 24
Finished Jan 07 12:34:48 PM PST 24
Peak memory 233772 kb
Host smart-85d6dbb7-2b49-4859-8efa-fc0d82f68ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941742036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.1941742036
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2266664222
Short name T30
Test name
Test status
Simulation time 1009119498 ps
CPU time 113.43 seconds
Started Jan 07 12:30:26 PM PST 24
Finished Jan 07 12:34:20 PM PST 24
Peak memory 236260 kb
Host smart-cef4cc50-cf8e-4b77-b54e-cba37be7ac7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266664222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2266664222
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.2474715201
Short name T48
Test name
Test status
Simulation time 2920079087 ps
CPU time 82.77 seconds
Started Jan 07 12:29:33 PM PST 24
Finished Jan 07 12:32:37 PM PST 24
Peak memory 211012 kb
Host smart-3d5d1cec-e845-4329-97f3-ef989557527b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474715201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.2474715201
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.2297026672
Short name T65
Test name
Test status
Simulation time 15733649763 ps
CPU time 56.76 seconds
Started Jan 07 12:30:32 PM PST 24
Finished Jan 07 12:32:54 PM PST 24
Peak memory 218860 kb
Host smart-a5898783-4d61-4e65-bd19-5f2f649a2ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297026672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.2297026672
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.2569197432
Short name T77
Test name
Test status
Simulation time 8102523942 ps
CPU time 97.12 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 12:33:39 PM PST 24
Peak memory 210648 kb
Host smart-e1479074-c19d-42f8-8af5-fdaaf33eeeaf
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569197432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.2569197432
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.824138726
Short name T5
Test name
Test status
Simulation time 1026125430 ps
CPU time 6.26 seconds
Started Jan 07 12:30:24 PM PST 24
Finished Jan 07 12:32:17 PM PST 24
Peak memory 210924 kb
Host smart-d72a665c-3c7b-4d09-b822-aa07d62adf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824138726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.824138726
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2225105010
Short name T86
Test name
Test status
Simulation time 1589358204 ps
CPU time 80.34 seconds
Started Jan 07 12:29:08 PM PST 24
Finished Jan 07 12:32:19 PM PST 24
Peak memory 210972 kb
Host smart-2d50e980-b547-4246-8719-f904b8318633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225105010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2225105010
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.3216906675
Short name T26
Test name
Test status
Simulation time 839388608 ps
CPU time 14.8 seconds
Started Jan 07 12:33:31 PM PST 24
Finished Jan 07 12:34:44 PM PST 24
Peak memory 211040 kb
Host smart-d7ec8d96-e7d4-4c89-9a00-59d88013f68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216906675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.3216906675
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1476116633
Short name T152
Test name
Test status
Simulation time 664967053 ps
CPU time 9.71 seconds
Started Jan 07 12:31:33 PM PST 24
Finished Jan 07 12:33:03 PM PST 24
Peak memory 211436 kb
Host smart-854c4035-6401-4cc4-89b5-5bd61fe86c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476116633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1476116633
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2587792792
Short name T114
Test name
Test status
Simulation time 24544115211 ps
CPU time 931.82 seconds
Started Jan 07 12:31:58 PM PST 24
Finished Jan 07 12:49:23 PM PST 24
Peak memory 230764 kb
Host smart-b4beb091-072e-4631-b15f-1fe79aad267a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587792792 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2587792792
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3887421303
Short name T57
Test name
Test status
Simulation time 9879827374 ps
CPU time 14.53 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:53 PM PST 24
Peak memory 210932 kb
Host smart-0cdc889f-8cd0-487d-aab8-93b87857265e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887421303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3887421303
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.997509101
Short name T117
Test name
Test status
Simulation time 2457578632 ps
CPU time 80.84 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:29:55 PM PST 24
Peak memory 211384 kb
Host smart-288cbecd-0b8b-42bd-9763-3101539f3196
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997509101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_in
tg_err.997509101
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1933547325
Short name T95
Test name
Test status
Simulation time 474109028 ps
CPU time 8.3 seconds
Started Jan 07 12:31:21 PM PST 24
Finished Jan 07 12:34:20 PM PST 24
Peak memory 210836 kb
Host smart-99dab5a8-1732-4eb3-9144-7ae1d6ee16c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933547325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1933547325
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3682003596
Short name T14
Test name
Test status
Simulation time 106633145350 ps
CPU time 3463.85 seconds
Started Jan 07 12:31:14 PM PST 24
Finished Jan 07 01:31:01 PM PST 24
Peak memory 229856 kb
Host smart-6cec0bc8-a3f7-486f-8905-0b7bbfaa6f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682003596 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3682003596
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4193081127
Short name T173
Test name
Test status
Simulation time 9244842265 ps
CPU time 23.35 seconds
Started Jan 07 12:31:51 PM PST 24
Finished Jan 07 12:34:35 PM PST 24
Peak memory 212768 kb
Host smart-ab223522-7b34-41b2-8e7f-c78dee675ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193081127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4193081127
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.214083048
Short name T318
Test name
Test status
Simulation time 2467284535 ps
CPU time 7.92 seconds
Started Jan 07 12:31:21 PM PST 24
Finished Jan 07 12:32:48 PM PST 24
Peak memory 210428 kb
Host smart-71dd4770-6635-42f2-947b-3757045c4e48
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214083048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.214083048
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1967861129
Short name T334
Test name
Test status
Simulation time 1827728944 ps
CPU time 14.48 seconds
Started Jan 07 12:29:03 PM PST 24
Finished Jan 07 12:30:58 PM PST 24
Peak memory 210864 kb
Host smart-8b70a0fa-c59d-46a8-b165-57d661172122
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967861129 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1967861129
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3742871026
Short name T311
Test name
Test status
Simulation time 98180363 ps
CPU time 7.76 seconds
Started Jan 07 12:31:05 PM PST 24
Finished Jan 07 12:33:18 PM PST 24
Peak memory 210748 kb
Host smart-2001ac36-2f29-47be-98e0-c365ae159b82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742871026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3742871026
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.940192745
Short name T84
Test name
Test status
Simulation time 866043442 ps
CPU time 9.53 seconds
Started Jan 07 12:30:04 PM PST 24
Finished Jan 07 12:32:45 PM PST 24
Peak memory 210832 kb
Host smart-3a22c2b5-b543-4ec4-9290-3074c61c5156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940192745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.940192745
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3779695230
Short name T81
Test name
Test status
Simulation time 55624637595 ps
CPU time 375.9 seconds
Started Jan 07 12:30:03 PM PST 24
Finished Jan 07 12:38:19 PM PST 24
Peak memory 210908 kb
Host smart-573d44bf-5980-40d7-bf19-d0b86d809fad
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779695230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.3779695230
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.1529075741
Short name T306
Test name
Test status
Simulation time 12123678524 ps
CPU time 15.28 seconds
Started Jan 07 12:29:34 PM PST 24
Finished Jan 07 12:31:14 PM PST 24
Peak memory 210940 kb
Host smart-f186ade6-cc57-4b7e-8b3a-74e157b62500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529075741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.1529075741
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3685885480
Short name T321
Test name
Test status
Simulation time 1231573473 ps
CPU time 80.99 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:30:10 PM PST 24
Peak memory 211400 kb
Host smart-caba1cce-1974-484d-b7a6-b040357f0cbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685885480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.3685885480
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.315485558
Short name T299
Test name
Test status
Simulation time 11838347673 ps
CPU time 10.02 seconds
Started Jan 07 12:30:18 PM PST 24
Finished Jan 07 12:32:01 PM PST 24
Peak memory 213736 kb
Host smart-126a075a-a572-4930-a2e1-6015f29db067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315485558 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.315485558
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3704810388
Short name T322
Test name
Test status
Simulation time 9273324966 ps
CPU time 10.74 seconds
Started Jan 07 12:30:18 PM PST 24
Finished Jan 07 12:32:01 PM PST 24
Peak memory 210060 kb
Host smart-ab445d4b-6685-4b53-a866-8ed0815dff35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704810388 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3704810388
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.2937798127
Short name T59
Test name
Test status
Simulation time 2851002799 ps
CPU time 12.66 seconds
Started Jan 07 12:28:26 PM PST 24
Finished Jan 07 12:29:45 PM PST 24
Peak memory 210920 kb
Host smart-d6f55657-f106-4c90-8776-4c560ec1ed5a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937798127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.2937798127
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1884322551
Short name T333
Test name
Test status
Simulation time 11885247742 ps
CPU time 12.76 seconds
Started Jan 07 12:28:26 PM PST 24
Finished Jan 07 12:29:39 PM PST 24
Peak memory 209884 kb
Host smart-91c9474d-0529-4a41-87f4-5f12c1914343
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884322551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1884322551
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2205927177
Short name T307
Test name
Test status
Simulation time 7375848313 ps
CPU time 16.36 seconds
Started Jan 07 12:30:50 PM PST 24
Finished Jan 07 12:33:00 PM PST 24
Peak memory 210836 kb
Host smart-0d830a7e-3ab2-4c07-8c32-5f69c68d83ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205927177 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.2205927177
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.407205744
Short name T323
Test name
Test status
Simulation time 2090622092 ps
CPU time 20.6 seconds
Started Jan 07 12:31:20 PM PST 24
Finished Jan 07 12:33:58 PM PST 24
Peak memory 219024 kb
Host smart-c85c3b8a-71fe-4a2f-b6c3-f3023abeeffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407205744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.407205744
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1298486768
Short name T319
Test name
Test status
Simulation time 336047607 ps
CPU time 4.53 seconds
Started Jan 07 12:27:06 PM PST 24
Finished Jan 07 12:28:28 PM PST 24
Peak memory 212652 kb
Host smart-154baf93-a239-44d2-bcc3-4afa81b0e516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298486768 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1298486768
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1094552916
Short name T328
Test name
Test status
Simulation time 161728612098 ps
CPU time 358.57 seconds
Started Jan 07 12:29:20 PM PST 24
Finished Jan 07 12:37:07 PM PST 24
Peak memory 210392 kb
Host smart-22859952-e8ad-4b9c-80cd-f45902ecbc5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094552916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1094552916
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.2463655432
Short name T346
Test name
Test status
Simulation time 1104233350 ps
CPU time 8 seconds
Started Jan 07 12:28:14 PM PST 24
Finished Jan 07 12:29:23 PM PST 24
Peak memory 211136 kb
Host smart-4129e65b-5484-454b-bb61-d1caeec0316c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463655432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.2463655432
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.228471816
Short name T308
Test name
Test status
Simulation time 670571266 ps
CPU time 8.57 seconds
Started Jan 07 12:30:04 PM PST 24
Finished Jan 07 12:31:45 PM PST 24
Peak memory 218972 kb
Host smart-e00ac1cf-7856-4bc1-8443-047da879c3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228471816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.228471816
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.184180518
Short name T335
Test name
Test status
Simulation time 3584475545 ps
CPU time 80.31 seconds
Started Jan 07 12:28:03 PM PST 24
Finished Jan 07 12:30:34 PM PST 24
Peak memory 211164 kb
Host smart-d6847fd1-a05d-419c-ad40-7227dcd7ed2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184180518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in
tg_err.184180518
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.161353098
Short name T330
Test name
Test status
Simulation time 6722052943 ps
CPU time 14.93 seconds
Started Jan 07 12:27:07 PM PST 24
Finished Jan 07 12:28:34 PM PST 24
Peak memory 216320 kb
Host smart-503f375a-2a14-49cf-9fe7-e62a967bf767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161353098 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.161353098
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3946146961
Short name T93
Test name
Test status
Simulation time 6170071109 ps
CPU time 84.14 seconds
Started Jan 07 12:30:05 PM PST 24
Finished Jan 07 12:32:54 PM PST 24
Peak memory 210804 kb
Host smart-95d15c81-87dd-4f63-ad3d-226cbfc75713
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946146961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3946146961
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1869741580
Short name T315
Test name
Test status
Simulation time 85559461 ps
CPU time 4.39 seconds
Started Jan 07 12:27:09 PM PST 24
Finished Jan 07 12:28:31 PM PST 24
Peak memory 211240 kb
Host smart-da757a2e-0653-44b0-a0b6-93c5bf153f57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869741580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1869741580
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3374166697
Short name T120
Test name
Test status
Simulation time 1354601306 ps
CPU time 44.68 seconds
Started Jan 07 12:28:41 PM PST 24
Finished Jan 07 12:30:44 PM PST 24
Peak memory 212316 kb
Host smart-d6298319-968b-455a-b278-f839c0ac90c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374166697 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3374166697
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1038686201
Short name T298
Test name
Test status
Simulation time 775322138 ps
CPU time 9.72 seconds
Started Jan 07 12:27:15 PM PST 24
Finished Jan 07 12:28:48 PM PST 24
Peak memory 214908 kb
Host smart-53b723ae-949b-4ca3-8045-628c79f832b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038686201 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1038686201
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.237329966
Short name T74
Test name
Test status
Simulation time 1658727817 ps
CPU time 13.77 seconds
Started Jan 07 12:28:22 PM PST 24
Finished Jan 07 12:29:39 PM PST 24
Peak memory 211088 kb
Host smart-0a907790-751d-4993-8591-b1dcc82d1109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237329966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.237329966
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.205224969
Short name T80
Test name
Test status
Simulation time 11157595355 ps
CPU time 169.34 seconds
Started Jan 07 12:28:41 PM PST 24
Finished Jan 07 12:32:44 PM PST 24
Peak memory 211176 kb
Host smart-b6ddfb5f-170d-46f9-bf13-f4d218da82a8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205224969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.205224969
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3439029997
Short name T63
Test name
Test status
Simulation time 112385101 ps
CPU time 6.47 seconds
Started Jan 07 12:27:19 PM PST 24
Finished Jan 07 12:28:36 PM PST 24
Peak memory 211172 kb
Host smart-7a4513b5-9169-4bcb-9bfb-4fc68afd7b1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439029997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3439029997
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3666366239
Short name T287
Test name
Test status
Simulation time 706663739 ps
CPU time 8.84 seconds
Started Jan 07 12:28:28 PM PST 24
Finished Jan 07 12:29:44 PM PST 24
Peak memory 214404 kb
Host smart-d384a058-33bc-4ca2-ad02-af010b4c3e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666366239 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3666366239
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4084016430
Short name T108
Test name
Test status
Simulation time 7272796119 ps
CPU time 15.56 seconds
Started Jan 07 12:27:30 PM PST 24
Finished Jan 07 12:29:11 PM PST 24
Peak memory 211196 kb
Host smart-b5a441b1-7dcd-4998-bdca-89ae83df2751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084016430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4084016430
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2359386805
Short name T326
Test name
Test status
Simulation time 789745462 ps
CPU time 12.78 seconds
Started Jan 07 12:28:21 PM PST 24
Finished Jan 07 12:29:45 PM PST 24
Peak memory 219288 kb
Host smart-1ac35e93-ddfa-4a5d-b612-9a333dbc282b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359386805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2359386805
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3076198020
Short name T119
Test name
Test status
Simulation time 3149083524 ps
CPU time 42.45 seconds
Started Jan 07 12:30:23 PM PST 24
Finished Jan 07 12:33:10 PM PST 24
Peak memory 211532 kb
Host smart-089f534a-ad77-4121-864d-6eeca539f372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076198020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3076198020
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.2440463904
Short name T87
Test name
Test status
Simulation time 7985060014 ps
CPU time 15.16 seconds
Started Jan 07 12:28:28 PM PST 24
Finished Jan 07 12:29:47 PM PST 24
Peak memory 214892 kb
Host smart-370be859-6ffb-4dff-9335-711d194a7f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440463904 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.2440463904
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.482920724
Short name T76
Test name
Test status
Simulation time 8499257669 ps
CPU time 15.59 seconds
Started Jan 07 12:29:35 PM PST 24
Finished Jan 07 12:31:40 PM PST 24
Peak memory 210400 kb
Host smart-88306567-5545-4f66-bdcd-e22f1f710e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482920724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.482920724
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3029321758
Short name T58
Test name
Test status
Simulation time 1652621288 ps
CPU time 4.38 seconds
Started Jan 07 12:28:27 PM PST 24
Finished Jan 07 12:30:01 PM PST 24
Peak memory 211084 kb
Host smart-940824cb-0079-4b7d-886c-6c4f0fc224a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029321758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3029321758
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.966428304
Short name T121
Test name
Test status
Simulation time 1677713024 ps
CPU time 81.98 seconds
Started Jan 07 12:28:10 PM PST 24
Finished Jan 07 12:30:29 PM PST 24
Peak memory 211352 kb
Host smart-313cffd9-5c11-4606-929e-cd552755751e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966428304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in
tg_err.966428304
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2936668066
Short name T286
Test name
Test status
Simulation time 2860796981 ps
CPU time 12.41 seconds
Started Jan 07 12:27:32 PM PST 24
Finished Jan 07 12:28:48 PM PST 24
Peak memory 215100 kb
Host smart-00deb805-7db9-489c-850f-edde965a34cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936668066 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2936668066
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3254852330
Short name T52
Test name
Test status
Simulation time 4209789610 ps
CPU time 16.39 seconds
Started Jan 07 12:28:00 PM PST 24
Finished Jan 07 12:29:25 PM PST 24
Peak memory 211152 kb
Host smart-ee7f1450-08b8-4ad8-b587-fef1f18ea83b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254852330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3254852330
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.301906165
Short name T305
Test name
Test status
Simulation time 3680225845 ps
CPU time 14.88 seconds
Started Jan 07 12:27:13 PM PST 24
Finished Jan 07 12:28:39 PM PST 24
Peak memory 211160 kb
Host smart-dea4ebda-a288-45e8-b5fb-6cf8b2dc7d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301906165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c
trl_same_csr_outstanding.301906165
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2593087309
Short name T302
Test name
Test status
Simulation time 1875124141 ps
CPU time 13.29 seconds
Started Jan 07 12:27:53 PM PST 24
Finished Jan 07 12:29:15 PM PST 24
Peak memory 219328 kb
Host smart-c8501c17-c796-4b6c-adff-64a334da198a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593087309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2593087309
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2909852674
Short name T339
Test name
Test status
Simulation time 11441806263 ps
CPU time 16.32 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:29:06 PM PST 24
Peak memory 213100 kb
Host smart-654f9951-fd39-47c7-b64c-94d9d9c006d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909852674 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2909852674
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.628804761
Short name T56
Test name
Test status
Simulation time 29372465396 ps
CPU time 270.99 seconds
Started Jan 07 12:27:34 PM PST 24
Finished Jan 07 12:33:36 PM PST 24
Peak memory 211172 kb
Host smart-3686eb6f-2e47-4354-95e2-be598819ad2c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628804761 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.628804761
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2944141195
Short name T104
Test name
Test status
Simulation time 1901543263 ps
CPU time 15.08 seconds
Started Jan 07 12:27:31 PM PST 24
Finished Jan 07 12:28:51 PM PST 24
Peak memory 211136 kb
Host smart-725b989f-7b0d-498a-93b2-9d9f5580a4ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944141195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2944141195
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2854821039
Short name T317
Test name
Test status
Simulation time 89245601 ps
CPU time 6.17 seconds
Started Jan 07 12:27:30 PM PST 24
Finished Jan 07 12:28:42 PM PST 24
Peak memory 219296 kb
Host smart-f13ccc83-21c1-4a1f-b203-6169ea887d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854821039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.2854821039
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.1672228437
Short name T312
Test name
Test status
Simulation time 669518413 ps
CPU time 41.13 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:29:31 PM PST 24
Peak memory 212340 kb
Host smart-c7b36d03-1b9f-457a-a696-d7f0fc72b6c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672228437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.1672228437
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1570398174
Short name T300
Test name
Test status
Simulation time 1782989741 ps
CPU time 14.21 seconds
Started Jan 07 12:28:53 PM PST 24
Finished Jan 07 12:30:19 PM PST 24
Peak memory 213288 kb
Host smart-be18b1b1-eced-4759-a356-09ca1a6073d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570398174 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1570398174
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.801224236
Short name T79
Test name
Test status
Simulation time 2996486874 ps
CPU time 12.87 seconds
Started Jan 07 12:27:36 PM PST 24
Finished Jan 07 12:28:54 PM PST 24
Peak memory 211128 kb
Host smart-0b768b9b-1659-4897-8650-1e34b34bd54a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801224236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.801224236
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.960725881
Short name T341
Test name
Test status
Simulation time 24248421394 ps
CPU time 162.18 seconds
Started Jan 07 12:27:21 PM PST 24
Finished Jan 07 12:31:11 PM PST 24
Peak memory 211188 kb
Host smart-111df0d5-ed6e-4898-8d95-0033b19f69aa
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960725881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.960725881
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3187840320
Short name T337
Test name
Test status
Simulation time 347073643 ps
CPU time 4.36 seconds
Started Jan 07 12:29:32 PM PST 24
Finished Jan 07 12:31:10 PM PST 24
Peak memory 210880 kb
Host smart-365be198-5286-4a0e-8a8e-0f6a3bfd544b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187840320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.3187840320
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3825351805
Short name T342
Test name
Test status
Simulation time 237275158 ps
CPU time 7.94 seconds
Started Jan 07 12:29:15 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 212452 kb
Host smart-e898cf26-135f-4a2c-8f67-e2e243a2feba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825351805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.3825351805
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.792747420
Short name T303
Test name
Test status
Simulation time 1253899504 ps
CPU time 11.82 seconds
Started Jan 07 12:27:37 PM PST 24
Finished Jan 07 12:29:03 PM PST 24
Peak memory 219292 kb
Host smart-e1b8ebc0-5d18-4053-8bef-9b7f6d060b68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792747420 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.792747420
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4071545048
Short name T325
Test name
Test status
Simulation time 1632054796 ps
CPU time 13.19 seconds
Started Jan 07 12:27:36 PM PST 24
Finished Jan 07 12:28:55 PM PST 24
Peak memory 211072 kb
Host smart-c47a7755-9b66-42ef-938c-31985b7bbc1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071545048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4071545048
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2028393508
Short name T304
Test name
Test status
Simulation time 346357499 ps
CPU time 4.15 seconds
Started Jan 07 12:29:33 PM PST 24
Finished Jan 07 12:31:02 PM PST 24
Peak memory 210880 kb
Host smart-f7d793f8-e087-4009-981f-0e83945231a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028393508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2028393508
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4289923395
Short name T295
Test name
Test status
Simulation time 707493121 ps
CPU time 9.77 seconds
Started Jan 07 12:29:38 PM PST 24
Finished Jan 07 12:31:49 PM PST 24
Peak memory 219036 kb
Host smart-e7fb7999-639d-48c9-8aa6-b0132b349878
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289923395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4289923395
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3058358536
Short name T115
Test name
Test status
Simulation time 8705790182 ps
CPU time 85.3 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:29:59 PM PST 24
Peak memory 211684 kb
Host smart-b1d0e8d8-9006-47a9-9068-85c3ab4d64dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058358536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3058358536
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.861224847
Short name T345
Test name
Test status
Simulation time 377097502 ps
CPU time 4.79 seconds
Started Jan 07 12:27:33 PM PST 24
Finished Jan 07 12:29:04 PM PST 24
Peak memory 213928 kb
Host smart-b9fcdfaf-75ad-4f10-9b69-c7a4c26d1c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861224847 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.861224847
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2940907378
Short name T72
Test name
Test status
Simulation time 6355145470 ps
CPU time 13.22 seconds
Started Jan 07 12:29:32 PM PST 24
Finished Jan 07 12:31:59 PM PST 24
Peak memory 210864 kb
Host smart-f788dea5-3718-486f-9b05-bd0f16cdd19f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940907378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2940907378
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.4068626384
Short name T78
Test name
Test status
Simulation time 34447043683 ps
CPU time 223.41 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:32:31 PM PST 24
Peak memory 211184 kb
Host smart-1a6cd994-4434-4afc-af21-fbd5c80a9064
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068626384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.4068626384
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.4279746041
Short name T336
Test name
Test status
Simulation time 1522650220 ps
CPU time 13.93 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 12:33:07 PM PST 24
Peak memory 210396 kb
Host smart-77a87fcd-e395-4496-b81a-b09637822197
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279746041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.4279746041
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2222346291
Short name T310
Test name
Test status
Simulation time 8709275383 ps
CPU time 18.31 seconds
Started Jan 07 12:27:28 PM PST 24
Finished Jan 07 12:29:03 PM PST 24
Peak memory 219376 kb
Host smart-5efe70fc-3d47-4ac1-88f0-655575120fc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222346291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2222346291
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1386254335
Short name T324
Test name
Test status
Simulation time 5474004743 ps
CPU time 44.36 seconds
Started Jan 07 12:29:32 PM PST 24
Finished Jan 07 12:31:56 PM PST 24
Peak memory 211980 kb
Host smart-610e58d4-3804-4881-971b-7660c6d9e753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386254335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1386254335
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3607792032
Short name T85
Test name
Test status
Simulation time 4443324424 ps
CPU time 11.05 seconds
Started Jan 07 12:28:47 PM PST 24
Finished Jan 07 12:30:30 PM PST 24
Peak memory 210344 kb
Host smart-051a92b1-d506-4baf-bc34-4f1129ab94bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607792032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3607792032
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.2092308076
Short name T82
Test name
Test status
Simulation time 3853287292 ps
CPU time 12.1 seconds
Started Jan 07 12:29:05 PM PST 24
Finished Jan 07 12:30:44 PM PST 24
Peak memory 210888 kb
Host smart-fcd950a8-0926-417c-836b-ed0c06dfa845
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092308076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.2092308076
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1425368968
Short name T61
Test name
Test status
Simulation time 5996353603 ps
CPU time 14.82 seconds
Started Jan 07 12:29:33 PM PST 24
Finished Jan 07 12:31:15 PM PST 24
Peak memory 210928 kb
Host smart-bf9830bb-1cbb-474d-a9a5-d2b63eccf815
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425368968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1425368968
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3038432309
Short name T313
Test name
Test status
Simulation time 5525163020 ps
CPU time 12.62 seconds
Started Jan 07 12:29:35 PM PST 24
Finished Jan 07 12:31:10 PM PST 24
Peak memory 214628 kb
Host smart-7130690e-9190-4fb7-a272-944b269806fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038432309 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3038432309
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.3287849861
Short name T314
Test name
Test status
Simulation time 86682278 ps
CPU time 4.59 seconds
Started Jan 07 12:31:08 PM PST 24
Finished Jan 07 12:32:44 PM PST 24
Peak memory 210852 kb
Host smart-686776d6-6868-447f-a8e2-12e111a909cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287849861 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.3287849861
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2293657235
Short name T301
Test name
Test status
Simulation time 1405368806 ps
CPU time 11.33 seconds
Started Jan 07 12:29:06 PM PST 24
Finished Jan 07 12:30:40 PM PST 24
Peak memory 210840 kb
Host smart-21d266ce-cc9a-4bd5-a727-ffa83b52f215
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293657235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2293657235
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.315423162
Short name T293
Test name
Test status
Simulation time 516079932 ps
CPU time 4.86 seconds
Started Jan 07 12:31:32 PM PST 24
Finished Jan 07 12:33:21 PM PST 24
Peak memory 210784 kb
Host smart-2531d856-16ed-41e1-ab49-12c350dd79b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315423162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk.
315423162
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3228519557
Short name T327
Test name
Test status
Simulation time 21218497384 ps
CPU time 192.69 seconds
Started Jan 07 12:25:21 PM PST 24
Finished Jan 07 12:29:37 PM PST 24
Peak memory 211260 kb
Host smart-c2a72f4e-1439-40d1-9d31-8f49ab7c6508
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228519557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.3228519557
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3884289553
Short name T332
Test name
Test status
Simulation time 2200600373 ps
CPU time 19.45 seconds
Started Jan 07 12:29:09 PM PST 24
Finished Jan 07 12:31:05 PM PST 24
Peak memory 219084 kb
Host smart-1e2e122d-4daf-4e39-a7bc-705c5bec9368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884289553 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3884289553
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3128777353
Short name T51
Test name
Test status
Simulation time 3854889116 ps
CPU time 15.06 seconds
Started Jan 07 12:31:24 PM PST 24
Finished Jan 07 12:33:39 PM PST 24
Peak memory 210880 kb
Host smart-5b1872cf-eb21-4da1-9b6c-0875e35b26a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128777353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3128777353
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1820937007
Short name T347
Test name
Test status
Simulation time 3445479137 ps
CPU time 15.38 seconds
Started Jan 07 12:29:03 PM PST 24
Finished Jan 07 12:30:31 PM PST 24
Peak memory 210940 kb
Host smart-a7b27e87-979f-4df9-824f-d1c299e7c234
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820937007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1820937007
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.2465241121
Short name T290
Test name
Test status
Simulation time 1652253129 ps
CPU time 13.92 seconds
Started Jan 07 12:25:31 PM PST 24
Finished Jan 07 12:26:46 PM PST 24
Peak memory 212160 kb
Host smart-fb207ac6-8177-4594-8dd8-cc224bc73897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465241121 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.2465241121
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.4243585480
Short name T73
Test name
Test status
Simulation time 85809845 ps
CPU time 4.1 seconds
Started Jan 07 12:29:36 PM PST 24
Finished Jan 07 12:31:13 PM PST 24
Peak memory 210880 kb
Host smart-e0f51503-5f7e-4f2d-bd4d-78f7f69c970f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243585480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.4243585480
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2496061225
Short name T294
Test name
Test status
Simulation time 1115559824 ps
CPU time 10.31 seconds
Started Jan 07 12:29:03 PM PST 24
Finished Jan 07 12:30:26 PM PST 24
Peak memory 210884 kb
Host smart-2e3c721c-3e81-49aa-8e35-fb556a23b6cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496061225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2496061225
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1714180480
Short name T329
Test name
Test status
Simulation time 174931434 ps
CPU time 4.37 seconds
Started Jan 07 12:29:05 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 210860 kb
Host smart-4dd2df8a-46fa-414b-b0da-9f36dec3b42f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714180480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1714180480
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3408607287
Short name T75
Test name
Test status
Simulation time 3855446699 ps
CPU time 50.31 seconds
Started Jan 07 12:35:23 PM PST 24
Finished Jan 07 12:37:19 PM PST 24
Peak memory 210892 kb
Host smart-6c831e6a-868e-4ba3-939b-e75de30a8fff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408607287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.3408607287
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.907466006
Short name T309
Test name
Test status
Simulation time 332526848 ps
CPU time 4.22 seconds
Started Jan 07 12:28:48 PM PST 24
Finished Jan 07 12:30:29 PM PST 24
Peak memory 210860 kb
Host smart-ec2e4b65-9eda-4638-bd68-eb80ef102e20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907466006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.907466006
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3494180111
Short name T316
Test name
Test status
Simulation time 636621485 ps
CPU time 11.5 seconds
Started Jan 07 12:29:06 PM PST 24
Finished Jan 07 12:30:42 PM PST 24
Peak memory 213640 kb
Host smart-6fbd1424-1573-41a4-812c-bc6dff73c3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494180111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3494180111
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1034891032
Short name T116
Test name
Test status
Simulation time 863856677 ps
CPU time 75.76 seconds
Started Jan 07 12:29:05 PM PST 24
Finished Jan 07 12:32:17 PM PST 24
Peak memory 211184 kb
Host smart-63d02fbc-312f-4749-8ad4-5e36f7be1157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034891032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1034891032
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2205851933
Short name T344
Test name
Test status
Simulation time 7512095267 ps
CPU time 12.8 seconds
Started Jan 07 12:42:14 PM PST 24
Finished Jan 07 12:44:06 PM PST 24
Peak memory 211268 kb
Host smart-cddd830f-63a7-4ac7-ab02-354e2cd54ec2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205851933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.2205851933
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2949650899
Short name T338
Test name
Test status
Simulation time 1738229275 ps
CPU time 14.02 seconds
Started Jan 07 12:31:35 PM PST 24
Finished Jan 07 12:33:34 PM PST 24
Peak memory 210284 kb
Host smart-a8158bbb-6559-4a4b-aa51-058405f7669f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949650899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.2949650899
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2915444347
Short name T60
Test name
Test status
Simulation time 4858127285 ps
CPU time 14.25 seconds
Started Jan 07 12:32:19 PM PST 24
Finished Jan 07 12:33:52 PM PST 24
Peak memory 210920 kb
Host smart-8b5d13e5-cdd4-4909-bb3d-526727e1684f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915444347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2915444347
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1375042754
Short name T292
Test name
Test status
Simulation time 2062599775 ps
CPU time 15.99 seconds
Started Jan 07 12:25:21 PM PST 24
Finished Jan 07 12:26:40 PM PST 24
Peak memory 211204 kb
Host smart-0ded07e6-0f3e-43a1-82c7-ad9bb1a01728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375042754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1375042754
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2547406035
Short name T320
Test name
Test status
Simulation time 127678221 ps
CPU time 5.08 seconds
Started Jan 07 12:27:09 PM PST 24
Finished Jan 07 12:28:24 PM PST 24
Peak memory 211168 kb
Host smart-0ccc5442-757d-4db2-aa5c-195baf7e5fad
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547406035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2547406035
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.614571710
Short name T297
Test name
Test status
Simulation time 1534257515 ps
CPU time 12.35 seconds
Started Jan 07 12:31:35 PM PST 24
Finished Jan 07 12:33:20 PM PST 24
Peak memory 210432 kb
Host smart-fd6a491b-afae-476c-8902-b5ecd875fc26
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614571710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk.
614571710
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2701617654
Short name T64
Test name
Test status
Simulation time 1566343587 ps
CPU time 13.26 seconds
Started Jan 07 12:41:45 PM PST 24
Finished Jan 07 12:43:25 PM PST 24
Peak memory 211156 kb
Host smart-8d445338-41c0-4df6-8201-55229d691c9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701617654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.2701617654
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4225178456
Short name T288
Test name
Test status
Simulation time 2183614365 ps
CPU time 18.3 seconds
Started Jan 07 12:28:48 PM PST 24
Finished Jan 07 12:30:29 PM PST 24
Peak memory 219072 kb
Host smart-beb25478-3fe6-4836-9666-a2c0623674cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225178456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.4225178456
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1867396888
Short name T106
Test name
Test status
Simulation time 1573298122 ps
CPU time 8.24 seconds
Started Jan 07 12:30:48 PM PST 24
Finished Jan 07 12:32:47 PM PST 24
Peak memory 213604 kb
Host smart-76e79cc3-7b3b-4c97-a44c-80661ad3f87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867396888 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1867396888
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.395972180
Short name T90
Test name
Test status
Simulation time 23351879134 ps
CPU time 221.61 seconds
Started Jan 07 12:28:56 PM PST 24
Finished Jan 07 12:33:53 PM PST 24
Peak memory 211096 kb
Host smart-0b72b72a-79ad-4287-9777-ab91de3daa93
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395972180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.395972180
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2720809447
Short name T340
Test name
Test status
Simulation time 1098844422 ps
CPU time 10.8 seconds
Started Jan 07 12:30:48 PM PST 24
Finished Jan 07 12:32:23 PM PST 24
Peak memory 210292 kb
Host smart-9561f8b8-3ec0-4a9c-9683-8d970a97de58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720809447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.2720809447
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.205585532
Short name T118
Test name
Test status
Simulation time 3605288363 ps
CPU time 76.64 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 12:33:19 PM PST 24
Peak memory 211204 kb
Host smart-675ce2d2-1147-4a5f-9111-c06373de7617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205585532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int
g_err.205585532
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2337396821
Short name T343
Test name
Test status
Simulation time 20453081044 ps
CPU time 14.25 seconds
Started Jan 07 12:25:34 PM PST 24
Finished Jan 07 12:27:00 PM PST 24
Peak memory 215272 kb
Host smart-64cbe5d0-962e-4d8c-a921-92f7c699af3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337396821 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2337396821
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2787893851
Short name T331
Test name
Test status
Simulation time 85738222 ps
CPU time 4.11 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:32:40 PM PST 24
Peak memory 210864 kb
Host smart-abed1687-1908-4fd5-a4c9-b4aa8bb4cf32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787893851 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2787893851
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3858369603
Short name T62
Test name
Test status
Simulation time 5086145808 ps
CPU time 15.68 seconds
Started Jan 07 12:25:39 PM PST 24
Finished Jan 07 12:26:54 PM PST 24
Peak memory 211264 kb
Host smart-0e1b7525-7f4f-46b0-98c4-66d5b19c43c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858369603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3858369603
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.2620997006
Short name T105
Test name
Test status
Simulation time 4782141114 ps
CPU time 11.45 seconds
Started Jan 07 12:27:20 PM PST 24
Finished Jan 07 12:28:45 PM PST 24
Peak memory 213800 kb
Host smart-a4ebf92e-39c3-4337-8e6c-cb5185974590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620997006 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.2620997006
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.247606274
Short name T89
Test name
Test status
Simulation time 20972715117 ps
CPU time 184.01 seconds
Started Jan 07 12:30:56 PM PST 24
Finished Jan 07 12:35:25 PM PST 24
Peak memory 210920 kb
Host smart-ecca7da6-50be-45f8-9782-e34340e78f02
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247606274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas
sthru_mem_tl_intg_err.247606274
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3965782092
Short name T107
Test name
Test status
Simulation time 10045545586 ps
CPU time 16.19 seconds
Started Jan 07 12:31:11 PM PST 24
Finished Jan 07 12:32:41 PM PST 24
Peak memory 210500 kb
Host smart-b615a1d2-e078-432f-92d3-2755069d7141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965782092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3965782092
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2397903773
Short name T88
Test name
Test status
Simulation time 836167219 ps
CPU time 10.45 seconds
Started Jan 07 12:33:54 PM PST 24
Finished Jan 07 12:35:09 PM PST 24
Peak memory 213052 kb
Host smart-c33c3f52-a932-481b-9f8f-81ba8c8a3ad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397903773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.2397903773
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3078933598
Short name T83
Test name
Test status
Simulation time 2032616444 ps
CPU time 48.86 seconds
Started Jan 07 12:34:17 PM PST 24
Finished Jan 07 12:36:56 PM PST 24
Peak memory 212080 kb
Host smart-c0d13664-8f44-4bcc-a21b-674ccf9f767d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078933598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3078933598
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.4055532534
Short name T291
Test name
Test status
Simulation time 3996432476 ps
CPU time 10.33 seconds
Started Jan 07 12:31:15 PM PST 24
Finished Jan 07 12:33:19 PM PST 24
Peak memory 214500 kb
Host smart-c192cf67-a91b-432d-b388-44d3e3eaa650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055532534 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.4055532534
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3986219019
Short name T94
Test name
Test status
Simulation time 6982571914 ps
CPU time 14.66 seconds
Started Jan 07 12:31:45 PM PST 24
Finished Jan 07 12:33:24 PM PST 24
Peak memory 210916 kb
Host smart-c3712ce2-fa78-46b3-a384-996947aa8a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986219019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3986219019
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3941801073
Short name T91
Test name
Test status
Simulation time 20692209096 ps
CPU time 248.87 seconds
Started Jan 07 12:29:38 PM PST 24
Finished Jan 07 12:35:22 PM PST 24
Peak memory 210048 kb
Host smart-5a378261-c1d7-4d99-8b69-fb9d290039b7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941801073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3941801073
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1375361146
Short name T50
Test name
Test status
Simulation time 870429603 ps
CPU time 72.64 seconds
Started Jan 07 12:30:53 PM PST 24
Finished Jan 07 12:33:20 PM PST 24
Peak memory 212692 kb
Host smart-1930c5c4-f9ff-4b96-9535-762437f7e12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375361146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.1375361146
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2321530474
Short name T289
Test name
Test status
Simulation time 121992907 ps
CPU time 4.45 seconds
Started Jan 07 12:27:58 PM PST 24
Finished Jan 07 12:29:02 PM PST 24
Peak memory 212804 kb
Host smart-ae374722-2261-4a7f-9dcd-988fa4aadfe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321530474 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2321530474
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1827358166
Short name T296
Test name
Test status
Simulation time 1399685903 ps
CPU time 12 seconds
Started Jan 07 12:29:10 PM PST 24
Finished Jan 07 12:31:01 PM PST 24
Peak memory 209912 kb
Host smart-460c2869-38e2-429f-91b2-66525133e7c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827358166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1827358166
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.751135120
Short name T92
Test name
Test status
Simulation time 13416069985 ps
CPU time 131.52 seconds
Started Jan 07 12:29:56 PM PST 24
Finished Jan 07 12:34:18 PM PST 24
Peak memory 210880 kb
Host smart-31bd20e4-5d54-41a5-9ef8-025077dbb75e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751135120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pas
sthru_mem_tl_intg_err.751135120
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.2949729376
Short name T279
Test name
Test status
Simulation time 830043612 ps
CPU time 4.35 seconds
Started Jan 07 12:29:10 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 210780 kb
Host smart-75cfe7bf-3968-4849-a99c-468d249128c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949729376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.2949729376
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.458737745
Short name T253
Test name
Test status
Simulation time 48847658439 ps
CPU time 277.4 seconds
Started Jan 07 12:30:23 PM PST 24
Finished Jan 07 12:36:34 PM PST 24
Peak memory 233288 kb
Host smart-1bc3630d-d9c9-4840-82e6-a07be7b6c7e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458737745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.458737745
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.2168755874
Short name T180
Test name
Test status
Simulation time 4348346879 ps
CPU time 22.86 seconds
Started Jan 07 12:30:27 PM PST 24
Finished Jan 07 12:33:52 PM PST 24
Peak memory 211272 kb
Host smart-8c628fd7-a3be-4618-80eb-b190c1c15273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168755874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.2168755874
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3733973263
Short name T141
Test name
Test status
Simulation time 6155327893 ps
CPU time 13.87 seconds
Started Jan 07 12:30:19 PM PST 24
Finished Jan 07 12:32:04 PM PST 24
Peak memory 210832 kb
Host smart-b87c0936-64a8-43e7-9229-ad9733d95558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733973263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3733973263
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.3256467200
Short name T187
Test name
Test status
Simulation time 52302854674 ps
CPU time 34.69 seconds
Started Jan 07 12:30:30 PM PST 24
Finished Jan 07 12:33:01 PM PST 24
Peak memory 212732 kb
Host smart-1278084c-9dca-424e-a6ae-f188995e1e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256467200 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.3256467200
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2741646123
Short name T263
Test name
Test status
Simulation time 1218259621 ps
CPU time 18.71 seconds
Started Jan 07 12:30:17 PM PST 24
Finished Jan 07 12:32:29 PM PST 24
Peak memory 213320 kb
Host smart-ecbf316c-5fae-4850-afb8-8fb5d755d412
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741646123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2741646123
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2015368118
Short name T100
Test name
Test status
Simulation time 754691886 ps
CPU time 9.6 seconds
Started Jan 07 12:28:54 PM PST 24
Finished Jan 07 12:30:21 PM PST 24
Peak memory 210924 kb
Host smart-734e2a12-89b5-4eeb-b406-152ab457ed9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015368118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2015368118
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.357330057
Short name T67
Test name
Test status
Simulation time 2433364957 ps
CPU time 29.71 seconds
Started Jan 07 12:31:05 PM PST 24
Finished Jan 07 12:33:16 PM PST 24
Peak memory 212600 kb
Host smart-01f46f65-7daa-4066-8d07-44e71ecf68da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357330057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.357330057
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2495483945
Short name T257
Test name
Test status
Simulation time 20325874906 ps
CPU time 33.73 seconds
Started Jan 07 12:29:41 PM PST 24
Finished Jan 07 12:32:00 PM PST 24
Peak memory 211180 kb
Host smart-29b7a99f-a7f2-43eb-8df9-42a5a529f4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495483945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2495483945
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3795522065
Short name T12
Test name
Test status
Simulation time 12563281769 ps
CPU time 17.7 seconds
Started Jan 07 12:30:48 PM PST 24
Finished Jan 07 12:33:00 PM PST 24
Peak memory 210816 kb
Host smart-b62508fc-fd66-4c73-88e7-f469ed370d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795522065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3795522065
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3722776096
Short name T40
Test name
Test status
Simulation time 18452234154 ps
CPU time 1017.36 seconds
Started Jan 07 12:30:12 PM PST 24
Finished Jan 07 12:48:30 PM PST 24
Peak memory 223868 kb
Host smart-de584fb9-3e00-469f-9996-c54ef38a9a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722776096 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.3722776096
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2643411994
Short name T239
Test name
Test status
Simulation time 5857042485 ps
CPU time 136.86 seconds
Started Jan 07 12:30:31 PM PST 24
Finished Jan 07 12:34:32 PM PST 24
Peak memory 237296 kb
Host smart-6be42ab4-a20f-4f8e-ae00-3ff1e453f12d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643411994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2643411994
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1907608803
Short name T183
Test name
Test status
Simulation time 9246383985 ps
CPU time 13.83 seconds
Started Jan 07 12:30:12 PM PST 24
Finished Jan 07 12:32:10 PM PST 24
Peak memory 210896 kb
Host smart-aaaa2840-af6a-4d92-a83c-b956626d2deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1907608803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1907608803
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.258023012
Short name T269
Test name
Test status
Simulation time 987630861 ps
CPU time 15.32 seconds
Started Jan 07 12:29:30 PM PST 24
Finished Jan 07 12:31:33 PM PST 24
Peak memory 211176 kb
Host smart-ea893807-d2f9-4e59-b973-5449d206263b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258023012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.258023012
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.3694476300
Short name T272
Test name
Test status
Simulation time 8199731606 ps
CPU time 32.78 seconds
Started Jan 07 12:30:47 PM PST 24
Finished Jan 07 12:33:42 PM PST 24
Peak memory 213328 kb
Host smart-a4120854-039f-43e2-95fb-c4ec7178a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694476300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.3694476300
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2052638453
Short name T249
Test name
Test status
Simulation time 18894688277 ps
CPU time 37.23 seconds
Started Jan 07 12:30:04 PM PST 24
Finished Jan 07 12:32:13 PM PST 24
Peak memory 213208 kb
Host smart-10e6abbf-49bb-4622-85b5-86171ad5d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052638453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2052638453
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.3917111984
Short name T134
Test name
Test status
Simulation time 470479629 ps
CPU time 12.23 seconds
Started Jan 07 12:30:19 PM PST 24
Finished Jan 07 12:31:56 PM PST 24
Peak memory 210704 kb
Host smart-bb852132-992a-4cd0-99e9-8e8629a92af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917111984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.3917111984
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.4106962568
Short name T246
Test name
Test status
Simulation time 146399998351 ps
CPU time 5646.85 seconds
Started Jan 07 12:33:47 PM PST 24
Finished Jan 07 02:09:07 PM PST 24
Peak memory 236080 kb
Host smart-f61e6f33-0030-4716-9077-c3aa9dfb3df2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106962568 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.4106962568
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3483674822
Short name T34
Test name
Test status
Simulation time 155326320988 ps
CPU time 319.75 seconds
Started Jan 07 12:34:07 PM PST 24
Finished Jan 07 12:41:01 PM PST 24
Peak memory 236172 kb
Host smart-eb96ce00-e19f-4913-b235-28dfd2e8d2c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483674822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3483674822
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.1879418192
Short name T258
Test name
Test status
Simulation time 755839778 ps
CPU time 10.34 seconds
Started Jan 07 12:30:11 PM PST 24
Finished Jan 07 12:32:48 PM PST 24
Peak memory 212452 kb
Host smart-d3ded594-38f0-4dd9-9f42-158c1aa3c96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879418192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.1879418192
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3995760125
Short name T216
Test name
Test status
Simulation time 34756915481 ps
CPU time 9618.39 seconds
Started Jan 07 12:30:23 PM PST 24
Finished Jan 07 03:12:16 PM PST 24
Peak memory 230032 kb
Host smart-9de82e9d-1d42-4760-ac94-7cb721eb4f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995760125 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3995760125
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.79562361
Short name T227
Test name
Test status
Simulation time 2926662525 ps
CPU time 13.03 seconds
Started Jan 07 12:29:53 PM PST 24
Finished Jan 07 12:31:41 PM PST 24
Peak memory 210960 kb
Host smart-a6e6b461-8e51-4372-b9c8-06d8efd27d5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79562361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.79562361
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3420111831
Short name T212
Test name
Test status
Simulation time 12320135640 ps
CPU time 167.46 seconds
Started Jan 07 12:33:20 PM PST 24
Finished Jan 07 12:37:24 PM PST 24
Peak memory 238732 kb
Host smart-94179b9a-d893-4210-ba17-c38aba49d39c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420111831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.3420111831
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.672403176
Short name T153
Test name
Test status
Simulation time 102919676 ps
CPU time 5.95 seconds
Started Jan 07 12:30:55 PM PST 24
Finished Jan 07 12:32:33 PM PST 24
Peak memory 210832 kb
Host smart-a8ff6e5d-5be2-417b-8cec-e432f5a86fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672403176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.672403176
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2450262013
Short name T231
Test name
Test status
Simulation time 14394874400 ps
CPU time 33.7 seconds
Started Jan 07 12:33:19 PM PST 24
Finished Jan 07 12:35:10 PM PST 24
Peak memory 212528 kb
Host smart-d82e1904-28c3-4354-86fb-57b7065a863a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450262013 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2450262013
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.596483688
Short name T131
Test name
Test status
Simulation time 22251980939 ps
CPU time 92.66 seconds
Started Jan 07 12:30:00 PM PST 24
Finished Jan 07 12:33:37 PM PST 24
Peak memory 217164 kb
Host smart-ef0d53f6-c9c4-4b54-9c2f-918c1168aece
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596483688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.rom_ctrl_stress_all.596483688
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.952183894
Short name T38
Test name
Test status
Simulation time 32756656751 ps
CPU time 2329.97 seconds
Started Jan 07 12:29:42 PM PST 24
Finished Jan 07 01:10:37 PM PST 24
Peak memory 235536 kb
Host smart-d30077b6-d110-4e96-bd68-07bdf6f967ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952183894 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.952183894
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2210087148
Short name T262
Test name
Test status
Simulation time 1630962980 ps
CPU time 13.92 seconds
Started Jan 07 12:30:53 PM PST 24
Finished Jan 07 12:33:34 PM PST 24
Peak memory 210820 kb
Host smart-df98a9f7-fe44-41b0-a7f6-c3aa090b1bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210087148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2210087148
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1764369627
Short name T260
Test name
Test status
Simulation time 29658749096 ps
CPU time 215.45 seconds
Started Jan 07 12:30:23 PM PST 24
Finished Jan 07 12:35:59 PM PST 24
Peak memory 237420 kb
Host smart-7a07128f-cca0-4378-ade7-611381b89c23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764369627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1764369627
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.3924501625
Short name T247
Test name
Test status
Simulation time 6875691017 ps
CPU time 30.03 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 12:32:25 PM PST 24
Peak memory 211512 kb
Host smart-8dc57601-11f2-4c4a-b5ab-47daf9fc6edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924501625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.3924501625
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3538262989
Short name T135
Test name
Test status
Simulation time 4317705475 ps
CPU time 11.73 seconds
Started Jan 07 12:30:29 PM PST 24
Finished Jan 07 12:33:17 PM PST 24
Peak memory 210840 kb
Host smart-6edaaccc-89d8-4bd9-8a1f-c543603b40dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3538262989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3538262989
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3823727778
Short name T218
Test name
Test status
Simulation time 4459092732 ps
CPU time 30 seconds
Started Jan 07 12:30:27 PM PST 24
Finished Jan 07 12:32:43 PM PST 24
Peak memory 213260 kb
Host smart-479bda16-70c0-4b07-8534-02545423aef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823727778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3823727778
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.3482230309
Short name T66
Test name
Test status
Simulation time 38039143324 ps
CPU time 96.92 seconds
Started Jan 07 12:29:52 PM PST 24
Finished Jan 07 12:33:25 PM PST 24
Peak memory 219076 kb
Host smart-5c40ac0c-ff10-45d0-97a0-33869f4fffaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482230309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.3482230309
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1214760087
Short name T44
Test name
Test status
Simulation time 118857605288 ps
CPU time 3251.9 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 01:26:03 PM PST 24
Peak memory 230512 kb
Host smart-86089ebd-feef-4576-9d56-5c58283cd848
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214760087 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1214760087
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1365203875
Short name T55
Test name
Test status
Simulation time 1382586860 ps
CPU time 12.35 seconds
Started Jan 07 12:30:31 PM PST 24
Finished Jan 07 12:32:02 PM PST 24
Peak memory 210560 kb
Host smart-0295c592-83a9-4359-9369-a003fb562086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365203875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1365203875
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.121765593
Short name T139
Test name
Test status
Simulation time 1965174357 ps
CPU time 21.34 seconds
Started Jan 07 12:30:28 PM PST 24
Finished Jan 07 12:32:13 PM PST 24
Peak memory 210668 kb
Host smart-acbef65c-ef54-4f56-bae9-9cce9ca60cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121765593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.121765593
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.1405724704
Short name T282
Test name
Test status
Simulation time 3779778739 ps
CPU time 23.63 seconds
Started Jan 07 12:29:59 PM PST 24
Finished Jan 07 12:32:01 PM PST 24
Peak memory 215004 kb
Host smart-43826973-d68e-41ca-846c-089d711ebce3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405724704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.1405724704
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1534842223
Short name T256
Test name
Test status
Simulation time 186131461918 ps
CPU time 9377.34 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 03:08:53 PM PST 24
Peak memory 236352 kb
Host smart-67668f39-cef8-414c-83ea-4319e36b1083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534842223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1534842223
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1693774428
Short name T244
Test name
Test status
Simulation time 85597991 ps
CPU time 4.19 seconds
Started Jan 07 12:30:19 PM PST 24
Finished Jan 07 12:31:55 PM PST 24
Peak memory 210820 kb
Host smart-852902cf-dd12-4191-a60d-d7cf633cfc1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693774428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1693774428
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1103783654
Short name T222
Test name
Test status
Simulation time 1673926236 ps
CPU time 112.61 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:34:36 PM PST 24
Peak memory 236344 kb
Host smart-33d9cb1e-4337-487b-a1fa-72987e776e5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103783654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1103783654
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.4294692982
Short name T170
Test name
Test status
Simulation time 722024724 ps
CPU time 9.42 seconds
Started Jan 07 12:30:31 PM PST 24
Finished Jan 07 12:32:00 PM PST 24
Peak memory 210624 kb
Host smart-da9829aa-115f-48df-a4fc-206077c69928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294692982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.4294692982
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.684978621
Short name T127
Test name
Test status
Simulation time 1046402171 ps
CPU time 11.74 seconds
Started Jan 07 12:30:29 PM PST 24
Finished Jan 07 12:33:21 PM PST 24
Peak memory 210768 kb
Host smart-984474f7-701e-4b72-835e-967cc6325dc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=684978621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.684978621
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.3812617614
Short name T101
Test name
Test status
Simulation time 1926920321 ps
CPU time 19.96 seconds
Started Jan 07 12:30:34 PM PST 24
Finished Jan 07 12:32:37 PM PST 24
Peak memory 211188 kb
Host smart-4bbb1063-f188-4c64-ab60-3fd09eb0c57d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812617614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.3812617614
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.3921852031
Short name T129
Test name
Test status
Simulation time 5717913252 ps
CPU time 12.86 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:26 PM PST 24
Peak memory 210536 kb
Host smart-fb47725a-2885-4ce3-9a3d-949ef870f792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921852031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.3921852031
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.970191692
Short name T184
Test name
Test status
Simulation time 35488832869 ps
CPU time 317.3 seconds
Started Jan 07 12:31:51 PM PST 24
Finished Jan 07 12:39:02 PM PST 24
Peak memory 223708 kb
Host smart-cd8b99c4-ce3f-4a45-99fd-0dd95b7852db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970191692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.970191692
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.3748767842
Short name T125
Test name
Test status
Simulation time 6262069547 ps
CPU time 19.25 seconds
Started Jan 07 12:30:02 PM PST 24
Finished Jan 07 12:32:05 PM PST 24
Peak memory 211400 kb
Host smart-beb10a4b-eeac-4327-b08e-1900b9ee0c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748767842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.3748767842
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.392683820
Short name T196
Test name
Test status
Simulation time 482219429 ps
CPU time 8.69 seconds
Started Jan 07 12:31:36 PM PST 24
Finished Jan 07 12:33:11 PM PST 24
Peak memory 208840 kb
Host smart-b7ebaff3-0544-43ad-9dcc-64c3faf37b7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392683820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.392683820
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.341726026
Short name T146
Test name
Test status
Simulation time 4255398858 ps
CPU time 33.23 seconds
Started Jan 07 12:31:36 PM PST 24
Finished Jan 07 12:33:35 PM PST 24
Peak memory 210628 kb
Host smart-122cd6ae-6e64-41e3-ad8c-28b00c473116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341726026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.341726026
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2036592038
Short name T140
Test name
Test status
Simulation time 1495246327 ps
CPU time 12.78 seconds
Started Jan 07 12:30:33 PM PST 24
Finished Jan 07 12:32:40 PM PST 24
Peak memory 210756 kb
Host smart-ca9ce2a5-ffeb-412b-bbf0-734b4522b999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036592038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2036592038
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.4259305635
Short name T35
Test name
Test status
Simulation time 70613547575 ps
CPU time 337.67 seconds
Started Jan 07 12:30:31 PM PST 24
Finished Jan 07 12:37:35 PM PST 24
Peak memory 236044 kb
Host smart-4bc9e068-71ad-4cc8-ba81-19c49db99142
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259305635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.4259305635
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3129446623
Short name T277
Test name
Test status
Simulation time 168836430 ps
CPU time 9.78 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:32:45 PM PST 24
Peak memory 210864 kb
Host smart-c192ef5e-e3fe-4776-a575-de56839cfb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129446623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3129446623
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.1725979405
Short name T195
Test name
Test status
Simulation time 9083107655 ps
CPU time 33.35 seconds
Started Jan 07 12:30:29 PM PST 24
Finished Jan 07 12:32:37 PM PST 24
Peak memory 213708 kb
Host smart-3c768992-3b72-45ed-a3df-08972ab3bad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725979405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.1725979405
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.567579532
Short name T181
Test name
Test status
Simulation time 898008542 ps
CPU time 15.49 seconds
Started Jan 07 12:30:35 PM PST 24
Finished Jan 07 12:32:14 PM PST 24
Peak memory 212712 kb
Host smart-f484f53b-9313-4593-b8bf-a78f22cbd3fe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567579532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.567579532
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.3930325288
Short name T151
Test name
Test status
Simulation time 88962685 ps
CPU time 4.32 seconds
Started Jan 07 12:29:48 PM PST 24
Finished Jan 07 12:31:23 PM PST 24
Peak memory 210820 kb
Host smart-f5edcd96-a86b-474a-a084-f15cc9cd3a6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930325288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.3930325288
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3819849246
Short name T178
Test name
Test status
Simulation time 6221133768 ps
CPU time 20.22 seconds
Started Jan 07 12:29:20 PM PST 24
Finished Jan 07 12:31:00 PM PST 24
Peak memory 211516 kb
Host smart-168f9f9b-ba91-44f6-8ddb-d88c1d797ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819849246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3819849246
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2233241556
Short name T235
Test name
Test status
Simulation time 4128651325 ps
CPU time 17.4 seconds
Started Jan 07 12:28:56 PM PST 24
Finished Jan 07 12:30:43 PM PST 24
Peak memory 210808 kb
Host smart-18603b13-34f1-4254-adee-c8729781ad04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233241556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2233241556
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2416293409
Short name T32
Test name
Test status
Simulation time 4326353838 ps
CPU time 63.51 seconds
Started Jan 07 12:28:55 PM PST 24
Finished Jan 07 12:31:15 PM PST 24
Peak memory 236208 kb
Host smart-56e55f32-c47e-4993-ad96-99418162e8c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416293409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2416293409
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.2376745366
Short name T142
Test name
Test status
Simulation time 3082807275 ps
CPU time 13.75 seconds
Started Jan 07 12:31:18 PM PST 24
Finished Jan 07 12:32:49 PM PST 24
Peak memory 210808 kb
Host smart-8550a16a-b903-4ec6-a590-5e6ffb07fcb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376745366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2376745366
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1431343825
Short name T259
Test name
Test status
Simulation time 13752408995 ps
CPU time 206.71 seconds
Started Jan 07 12:31:02 PM PST 24
Finished Jan 07 12:35:48 PM PST 24
Peak memory 237292 kb
Host smart-a8f65931-8c1d-43a0-8e19-ba61be19394a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431343825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.1431343825
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.746209589
Short name T138
Test name
Test status
Simulation time 15393289833 ps
CPU time 31.47 seconds
Started Jan 07 12:31:40 PM PST 24
Finished Jan 07 12:34:18 PM PST 24
Peak memory 210892 kb
Host smart-ed5d2caa-c6d3-424d-a3ff-1cb18679773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746209589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.746209589
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.3004855020
Short name T112
Test name
Test status
Simulation time 102374312 ps
CPU time 5.85 seconds
Started Jan 07 12:31:39 PM PST 24
Finished Jan 07 12:33:13 PM PST 24
Peak memory 210476 kb
Host smart-3e0abcb8-835b-4010-8b79-cf2953da5604
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004855020 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.3004855020
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.2563758147
Short name T102
Test name
Test status
Simulation time 6570345383 ps
CPU time 27.92 seconds
Started Jan 07 12:31:08 PM PST 24
Finished Jan 07 12:32:53 PM PST 24
Peak memory 212964 kb
Host smart-b431e7f8-7e36-4066-8f34-44224f5cc6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563758147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.2563758147
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.54020493
Short name T155
Test name
Test status
Simulation time 2384566770 ps
CPU time 11.55 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:34:07 PM PST 24
Peak memory 210844 kb
Host smart-db14174d-655d-4031-9d37-20ad368410e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54020493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.54020493
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3497341057
Short name T203
Test name
Test status
Simulation time 2571750286 ps
CPU time 182.97 seconds
Started Jan 07 12:31:04 PM PST 24
Finished Jan 07 12:35:50 PM PST 24
Peak memory 237380 kb
Host smart-96c477c9-9424-4448-9897-3d56bb4f1700
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497341057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3497341057
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.2588122279
Short name T205
Test name
Test status
Simulation time 2019364051 ps
CPU time 16 seconds
Started Jan 07 12:31:33 PM PST 24
Finished Jan 07 12:33:14 PM PST 24
Peak memory 210872 kb
Host smart-42e5c980-6e26-4bd8-bb8f-02850ed1c576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588122279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.2588122279
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3744301403
Short name T185
Test name
Test status
Simulation time 751824261 ps
CPU time 10.37 seconds
Started Jan 07 12:31:18 PM PST 24
Finished Jan 07 12:33:57 PM PST 24
Peak memory 212276 kb
Host smart-e9a55e96-01cb-4a7d-9c30-200eda4e5d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744301403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3744301403
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2520666923
Short name T264
Test name
Test status
Simulation time 3430293801 ps
CPU time 23.54 seconds
Started Jan 07 12:30:31 PM PST 24
Finished Jan 07 12:32:59 PM PST 24
Peak memory 215892 kb
Host smart-ad89e5b2-2d88-4bf7-8ba2-7c90e35f9f2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520666923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2520666923
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.539870136
Short name T275
Test name
Test status
Simulation time 171700598 ps
CPU time 4.27 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:32:58 PM PST 24
Peak memory 210860 kb
Host smart-fb4de9ed-ed18-4b91-a2d9-11319f0aad55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539870136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.539870136
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1031963523
Short name T207
Test name
Test status
Simulation time 1029949910 ps
CPU time 6.99 seconds
Started Jan 07 12:31:21 PM PST 24
Finished Jan 07 12:32:59 PM PST 24
Peak memory 210788 kb
Host smart-0c1063fd-6b82-4969-bad8-31645b1fddf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1031963523 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1031963523
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.30809238
Short name T163
Test name
Test status
Simulation time 2906556571 ps
CPU time 26.34 seconds
Started Jan 07 12:31:52 PM PST 24
Finished Jan 07 12:33:37 PM PST 24
Peak memory 212616 kb
Host smart-71c558f5-1ddf-4698-a54b-53ce2a77d691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30809238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.30809238
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.220108623
Short name T160
Test name
Test status
Simulation time 5292982105 ps
CPU time 18.93 seconds
Started Jan 07 12:31:09 PM PST 24
Finished Jan 07 12:33:26 PM PST 24
Peak memory 213532 kb
Host smart-a227ba4c-90c5-4619-b725-662cf9fa4ed1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220108623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.rom_ctrl_stress_all.220108623
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.3817209665
Short name T202
Test name
Test status
Simulation time 23523713784 ps
CPU time 138.33 seconds
Started Jan 07 12:31:20 PM PST 24
Finished Jan 07 12:35:16 PM PST 24
Peak memory 237260 kb
Host smart-63732f07-3bb8-4665-a50b-7e7e505eee79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817209665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.3817209665
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.778286849
Short name T24
Test name
Test status
Simulation time 5821519000 ps
CPU time 18.56 seconds
Started Jan 07 12:31:18 PM PST 24
Finished Jan 07 12:33:12 PM PST 24
Peak memory 211552 kb
Host smart-647a84e7-4cf2-4642-b447-6d35dbdfd36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778286849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.778286849
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.103684376
Short name T157
Test name
Test status
Simulation time 5266153327 ps
CPU time 25.49 seconds
Started Jan 07 12:31:06 PM PST 24
Finished Jan 07 12:32:48 PM PST 24
Peak memory 212756 kb
Host smart-dd06a57d-e02d-4127-bbcf-7b1831afa648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103684376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.103684376
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3984526474
Short name T176
Test name
Test status
Simulation time 3500619781 ps
CPU time 16.44 seconds
Started Jan 07 12:31:07 PM PST 24
Finished Jan 07 12:32:59 PM PST 24
Peak memory 210648 kb
Host smart-a7409b7c-44d3-4acb-825c-46265919e020
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984526474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3984526474
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3172574422
Short name T27
Test name
Test status
Simulation time 132664061800 ps
CPU time 335.36 seconds
Started Jan 07 12:33:43 PM PST 24
Finished Jan 07 12:40:31 PM PST 24
Peak memory 236848 kb
Host smart-052c1295-7373-4dd5-8e01-ab376463eed5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172574422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.3172574422
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3530244729
Short name T211
Test name
Test status
Simulation time 6176608459 ps
CPU time 15.95 seconds
Started Jan 07 12:30:34 PM PST 24
Finished Jan 07 12:32:39 PM PST 24
Peak memory 213280 kb
Host smart-9d2c8c3b-ab77-4e93-a87c-84f421171821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530244729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3530244729
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.3211659577
Short name T113
Test name
Test status
Simulation time 23627008181 ps
CPU time 15.45 seconds
Started Jan 07 12:31:10 PM PST 24
Finished Jan 07 12:32:55 PM PST 24
Peak memory 210812 kb
Host smart-1baf8e79-4ded-4a9a-986b-d2cbdb6e2ece
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211659577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.3211659577
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.1764827674
Short name T194
Test name
Test status
Simulation time 18962676759 ps
CPU time 23.73 seconds
Started Jan 07 12:31:15 PM PST 24
Finished Jan 07 12:33:15 PM PST 24
Peak memory 213056 kb
Host smart-070c5f80-ca5a-4d80-ab5e-fca1b39b95f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764827674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.1764827674
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2249738223
Short name T278
Test name
Test status
Simulation time 5517465325 ps
CPU time 12.23 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:32:49 PM PST 24
Peak memory 210880 kb
Host smart-4d39bce6-b8bb-4da7-beab-4126b25c790e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249738223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2249738223
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.2509217996
Short name T3
Test name
Test status
Simulation time 19938532970 ps
CPU time 30.56 seconds
Started Jan 07 12:30:58 PM PST 24
Finished Jan 07 12:33:00 PM PST 24
Peak memory 211300 kb
Host smart-f34012d0-75fc-4624-a8fc-22e5a4f772ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509217996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.2509217996
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.182154221
Short name T156
Test name
Test status
Simulation time 8051415578 ps
CPU time 16.6 seconds
Started Jan 07 12:31:10 PM PST 24
Finished Jan 07 12:33:06 PM PST 24
Peak memory 210752 kb
Host smart-407ed5ae-f820-404b-aed2-2fa1eb612b02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182154221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.182154221
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1232934957
Short name T168
Test name
Test status
Simulation time 381306151 ps
CPU time 10.02 seconds
Started Jan 07 12:31:07 PM PST 24
Finished Jan 07 12:33:23 PM PST 24
Peak memory 211976 kb
Host smart-a69c0b92-fe3d-4246-b0ad-7f1ab48511c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232934957 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1232934957
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3218108130
Short name T209
Test name
Test status
Simulation time 1098819796 ps
CPU time 30.02 seconds
Started Jan 07 12:31:21 PM PST 24
Finished Jan 07 12:34:50 PM PST 24
Peak memory 215540 kb
Host smart-db9a7a38-3912-45db-9ce7-15383909fc2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218108130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3218108130
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3738057622
Short name T270
Test name
Test status
Simulation time 102241664743 ps
CPU time 922.63 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:47:57 PM PST 24
Peak memory 235464 kb
Host smart-d82d5809-50cf-4c42-b136-29fc41d17006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738057622 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3738057622
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.3811134467
Short name T192
Test name
Test status
Simulation time 687212186 ps
CPU time 8.32 seconds
Started Jan 07 12:31:03 PM PST 24
Finished Jan 07 12:32:39 PM PST 24
Peak memory 210800 kb
Host smart-14a9cdd9-c3b3-4b64-b431-23e9d9643a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811134467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.3811134467
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1794930423
Short name T241
Test name
Test status
Simulation time 116866940674 ps
CPU time 603.97 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:45:06 PM PST 24
Peak memory 227952 kb
Host smart-634d74d0-e5ce-4505-88b1-e4d92370f89d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794930423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1794930423
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2181675900
Short name T123
Test name
Test status
Simulation time 29364525553 ps
CPU time 22.91 seconds
Started Jan 07 12:31:30 PM PST 24
Finished Jan 07 12:33:40 PM PST 24
Peak memory 210848 kb
Host smart-b61f9b3b-0f5b-4212-b674-010e9d2056fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181675900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2181675900
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.570058643
Short name T169
Test name
Test status
Simulation time 2072404900 ps
CPU time 16.43 seconds
Started Jan 07 12:31:35 PM PST 24
Finished Jan 07 12:33:44 PM PST 24
Peak memory 210736 kb
Host smart-7ca51cbe-ff2d-4b45-9401-af8d6c067502
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570058643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.570058643
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1052671794
Short name T71
Test name
Test status
Simulation time 6877797280 ps
CPU time 34.27 seconds
Started Jan 07 12:31:53 PM PST 24
Finished Jan 07 12:34:34 PM PST 24
Peak memory 213840 kb
Host smart-cfc5fecc-ecdc-4109-a967-6e66a0bd09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052671794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1052671794
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2297971966
Short name T128
Test name
Test status
Simulation time 6248506562 ps
CPU time 17.07 seconds
Started Jan 07 12:31:23 PM PST 24
Finished Jan 07 12:33:06 PM PST 24
Peak memory 210752 kb
Host smart-2d0d4f86-964f-43aa-9f39-665da808a24c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297971966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2297971966
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.3921475590
Short name T188
Test name
Test status
Simulation time 4642736907 ps
CPU time 10.67 seconds
Started Jan 07 12:31:01 PM PST 24
Finished Jan 07 12:34:31 PM PST 24
Peak memory 210776 kb
Host smart-298c3489-0836-4ab4-94d1-7d6b48c22450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921475590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.3921475590
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.481765248
Short name T36
Test name
Test status
Simulation time 10974924488 ps
CPU time 183 seconds
Started Jan 07 12:31:03 PM PST 24
Finished Jan 07 12:35:29 PM PST 24
Peak memory 237284 kb
Host smart-67e54c58-56d5-48ae-9e7d-3a2aedd76e3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481765248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.481765248
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1513659267
Short name T193
Test name
Test status
Simulation time 1911566552 ps
CPU time 20.84 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:34:49 PM PST 24
Peak memory 210912 kb
Host smart-3b74f343-86cb-4795-826e-dcc22a069a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513659267 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1513659267
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1973845180
Short name T10
Test name
Test status
Simulation time 2644502650 ps
CPU time 12.91 seconds
Started Jan 07 12:30:44 PM PST 24
Finished Jan 07 12:32:39 PM PST 24
Peak memory 210880 kb
Host smart-ac49eca0-0775-47c6-b570-1bc20e5ed541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973845180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1973845180
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.47228650
Short name T110
Test name
Test status
Simulation time 183237010 ps
CPU time 9.84 seconds
Started Jan 07 12:31:53 PM PST 24
Finished Jan 07 12:33:17 PM PST 24
Peak memory 212500 kb
Host smart-c8b32108-4579-43ad-9641-7c6e3c91fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47228650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.47228650
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1435909918
Short name T220
Test name
Test status
Simulation time 7458853532 ps
CPU time 34.76 seconds
Started Jan 07 12:30:55 PM PST 24
Finished Jan 07 12:32:57 PM PST 24
Peak memory 213924 kb
Host smart-89a7b7cc-9427-499b-8933-14f66a7da025
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435909918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1435909918
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.807767087
Short name T214
Test name
Test status
Simulation time 1081046198 ps
CPU time 12.08 seconds
Started Jan 07 12:32:00 PM PST 24
Finished Jan 07 12:34:01 PM PST 24
Peak memory 210804 kb
Host smart-7551fe1a-e267-4fd0-851c-5cbd79453933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807767087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.807767087
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1346064356
Short name T133
Test name
Test status
Simulation time 11828321110 ps
CPU time 28.78 seconds
Started Jan 07 12:31:08 PM PST 24
Finished Jan 07 12:33:08 PM PST 24
Peak memory 211244 kb
Host smart-99dc2057-478c-47d5-a2d6-5cba7a610890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346064356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1346064356
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1688289385
Short name T53
Test name
Test status
Simulation time 905782286 ps
CPU time 9.89 seconds
Started Jan 07 12:30:12 PM PST 24
Finished Jan 07 12:31:43 PM PST 24
Peak memory 210636 kb
Host smart-1a8c8b71-a332-4151-a7d4-16a5cb205c22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688289385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1688289385
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1688971278
Short name T254
Test name
Test status
Simulation time 23439274313 ps
CPU time 312.48 seconds
Started Jan 07 12:30:15 PM PST 24
Finished Jan 07 12:37:00 PM PST 24
Peak memory 233280 kb
Host smart-f468f2c1-52f6-4202-9dc3-0fed04ea10a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688971278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1688971278
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1558579812
Short name T145
Test name
Test status
Simulation time 3088121215 ps
CPU time 14.85 seconds
Started Jan 07 12:29:20 PM PST 24
Finished Jan 07 12:30:54 PM PST 24
Peak memory 211252 kb
Host smart-51eaab81-3a7c-4bbf-9990-264ce0860d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558579812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1558579812
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3966966884
Short name T29
Test name
Test status
Simulation time 3877960427 ps
CPU time 122.43 seconds
Started Jan 07 12:29:56 PM PST 24
Finished Jan 07 12:34:06 PM PST 24
Peak memory 236412 kb
Host smart-dfe6f605-c4b1-4079-abd0-0764d78d41ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966966884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3966966884
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3829110524
Short name T98
Test name
Test status
Simulation time 6993206163 ps
CPU time 30.76 seconds
Started Jan 07 12:28:55 PM PST 24
Finished Jan 07 12:30:42 PM PST 24
Peak memory 213012 kb
Host smart-9fca9701-8ad7-4d5a-9e47-5d4338d2671d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829110524 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3829110524
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.4228863212
Short name T177
Test name
Test status
Simulation time 390064883 ps
CPU time 23.4 seconds
Started Jan 07 12:32:19 PM PST 24
Finished Jan 07 12:34:54 PM PST 24
Peak memory 213880 kb
Host smart-1be7277c-1674-454d-8832-f7b249028c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228863212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.4228863212
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.1554149157
Short name T31
Test name
Test status
Simulation time 1206147469 ps
CPU time 6.27 seconds
Started Jan 07 12:31:24 PM PST 24
Finished Jan 07 12:33:30 PM PST 24
Peak memory 210848 kb
Host smart-fddc7734-ebd3-40a0-9192-af4f5a4617f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554149157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.1554149157
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3085075243
Short name T210
Test name
Test status
Simulation time 73013271836 ps
CPU time 177.69 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 12:36:10 PM PST 24
Peak memory 240116 kb
Host smart-c19b65c0-cc7f-432c-9c59-45050fd22d76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085075243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3085075243
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.945521551
Short name T243
Test name
Test status
Simulation time 315429593 ps
CPU time 9.73 seconds
Started Jan 07 12:30:46 PM PST 24
Finished Jan 07 12:32:20 PM PST 24
Peak memory 210932 kb
Host smart-92e00db6-cd9b-4c83-9dd5-6ceb1076baba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945521551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.945521551
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.873458334
Short name T261
Test name
Test status
Simulation time 822145860 ps
CPU time 5.5 seconds
Started Jan 07 12:30:56 PM PST 24
Finished Jan 07 12:32:16 PM PST 24
Peak memory 210364 kb
Host smart-39daf61a-b154-4ad0-b523-3f280a9f819c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873458334 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.873458334
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2622488661
Short name T252
Test name
Test status
Simulation time 186663774 ps
CPU time 10.01 seconds
Started Jan 07 12:31:25 PM PST 24
Finished Jan 07 12:33:10 PM PST 24
Peak memory 212012 kb
Host smart-cd95b3b6-eab0-4f0e-9d83-ef2f916f435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622488661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2622488661
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.2308135746
Short name T251
Test name
Test status
Simulation time 19456188179 ps
CPU time 2926.33 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 01:21:52 PM PST 24
Peak memory 235340 kb
Host smart-f508a165-848d-40f8-ae05-72001fd44520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308135746 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.2308135746
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.3723853819
Short name T204
Test name
Test status
Simulation time 6036236279 ps
CPU time 10.52 seconds
Started Jan 07 12:30:46 PM PST 24
Finished Jan 07 12:32:25 PM PST 24
Peak memory 210892 kb
Host smart-185b24dc-5a66-46e8-af00-43d0e0043999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723853819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.3723853819
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2324454255
Short name T201
Test name
Test status
Simulation time 30557690157 ps
CPU time 105.12 seconds
Started Jan 07 12:30:44 PM PST 24
Finished Jan 07 12:33:57 PM PST 24
Peak memory 224248 kb
Host smart-a67767aa-805f-4a02-b3c6-73833293e408
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324454255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2324454255
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2048905291
Short name T174
Test name
Test status
Simulation time 22027930594 ps
CPU time 17.48 seconds
Started Jan 07 12:31:12 PM PST 24
Finished Jan 07 12:33:48 PM PST 24
Peak memory 211152 kb
Host smart-f480de2e-361d-4c15-a234-34d3bcf3f200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048905291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2048905291
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2176353868
Short name T284
Test name
Test status
Simulation time 2761435500 ps
CPU time 13.25 seconds
Started Jan 07 12:30:49 PM PST 24
Finished Jan 07 12:32:47 PM PST 24
Peak memory 210792 kb
Host smart-e4ddc707-9d11-432a-a5db-58a3a3c4ae7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176353868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2176353868
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.957700437
Short name T255
Test name
Test status
Simulation time 4571028376 ps
CPU time 26.08 seconds
Started Jan 07 12:34:01 PM PST 24
Finished Jan 07 12:35:55 PM PST 24
Peak memory 212388 kb
Host smart-ed96fe1b-4284-4482-8003-f0117cc54c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957700437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.957700437
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1180621112
Short name T144
Test name
Test status
Simulation time 23171544755 ps
CPU time 33.38 seconds
Started Jan 07 12:31:19 PM PST 24
Finished Jan 07 12:33:10 PM PST 24
Peak memory 211196 kb
Host smart-5fd8e33d-8865-4a5b-87b9-639b3ce49600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180621112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1180621112
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.1370594935
Short name T199
Test name
Test status
Simulation time 8076616963 ps
CPU time 16.07 seconds
Started Jan 07 12:30:42 PM PST 24
Finished Jan 07 12:32:33 PM PST 24
Peak memory 210016 kb
Host smart-4ff349e7-2d1d-4dd9-b7d0-b908dff196b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370594935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.1370594935
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1833294932
Short name T245
Test name
Test status
Simulation time 2633481377 ps
CPU time 36.2 seconds
Started Jan 07 12:31:25 PM PST 24
Finished Jan 07 12:33:45 PM PST 24
Peak memory 215704 kb
Host smart-a7be0b0c-56a5-42ed-94f5-098d4365aa51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833294932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1833294932
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2945560956
Short name T172
Test name
Test status
Simulation time 1621869958 ps
CPU time 10.25 seconds
Started Jan 07 12:31:04 PM PST 24
Finished Jan 07 12:32:43 PM PST 24
Peak memory 210828 kb
Host smart-91538b48-79f8-4290-a5bf-590ff8a1ed99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945560956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2945560956
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.2794491694
Short name T149
Test name
Test status
Simulation time 786263712 ps
CPU time 8.99 seconds
Started Jan 07 12:34:28 PM PST 24
Finished Jan 07 12:36:07 PM PST 24
Peak memory 210540 kb
Host smart-cdb22d3f-46b7-4089-b912-7d613d9b3d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794491694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2794491694
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1736179278
Short name T7
Test name
Test status
Simulation time 548060137 ps
CPU time 8.61 seconds
Started Jan 07 12:33:50 PM PST 24
Finished Jan 07 12:35:22 PM PST 24
Peak memory 210472 kb
Host smart-e7446f50-b5be-4f8f-b688-b953a858f17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736179278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1736179278
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.211290590
Short name T23
Test name
Test status
Simulation time 8060690445 ps
CPU time 32.06 seconds
Started Jan 07 12:31:23 PM PST 24
Finished Jan 07 12:33:49 PM PST 24
Peak memory 212364 kb
Host smart-e7fb6a90-71a2-4fa0-a8df-3be8313f2169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211290590 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.211290590
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.631299683
Short name T161
Test name
Test status
Simulation time 707177692 ps
CPU time 8.61 seconds
Started Jan 07 12:31:34 PM PST 24
Finished Jan 07 12:33:06 PM PST 24
Peak memory 210852 kb
Host smart-6db35f1b-be37-430e-9a6e-bac3a3759c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631299683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.631299683
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1167009105
Short name T179
Test name
Test status
Simulation time 22625066966 ps
CPU time 234.87 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:38:34 PM PST 24
Peak memory 213124 kb
Host smart-0d3aa626-3a94-4c38-94bb-310481c4d9f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167009105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1167009105
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2971288597
Short name T230
Test name
Test status
Simulation time 189941856 ps
CPU time 9.93 seconds
Started Jan 07 12:31:28 PM PST 24
Finished Jan 07 12:33:29 PM PST 24
Peak memory 215156 kb
Host smart-99fc1d6a-8202-47ae-945b-eaa500fde9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971288597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2971288597
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3140045090
Short name T175
Test name
Test status
Simulation time 6536172278 ps
CPU time 14.59 seconds
Started Jan 07 12:31:48 PM PST 24
Finished Jan 07 12:33:35 PM PST 24
Peak memory 210792 kb
Host smart-9a2cbbf7-3a6a-4dd2-a14a-9081cfa89afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3140045090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3140045090
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.1132167417
Short name T11
Test name
Test status
Simulation time 2443222898 ps
CPU time 24.08 seconds
Started Jan 07 12:31:20 PM PST 24
Finished Jan 07 12:33:03 PM PST 24
Peak memory 212372 kb
Host smart-282b1e42-49bd-42f6-a368-29b7971183c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132167417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.1132167417
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.277486262
Short name T96
Test name
Test status
Simulation time 3284505379 ps
CPU time 28.38 seconds
Started Jan 07 12:31:03 PM PST 24
Finished Jan 07 12:32:45 PM PST 24
Peak memory 212588 kb
Host smart-a274b3aa-1713-4027-8a0b-f4b491b830f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277486262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.277486262
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.3769376093
Short name T43
Test name
Test status
Simulation time 46240114423 ps
CPU time 5399.15 seconds
Started Jan 07 12:31:26 PM PST 24
Finished Jan 07 02:02:58 PM PST 24
Peak memory 232928 kb
Host smart-fd7d9a7d-1efa-415c-9937-378f2f73d328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769376093 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.3769376093
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3810631949
Short name T283
Test name
Test status
Simulation time 8445473960 ps
CPU time 104.69 seconds
Started Jan 07 12:31:40 PM PST 24
Finished Jan 07 12:34:57 PM PST 24
Peak memory 213204 kb
Host smart-fa25534a-9125-4e50-bdbb-e0b26e2d92cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810631949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3810631949
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3518155102
Short name T109
Test name
Test status
Simulation time 463692424 ps
CPU time 5.43 seconds
Started Jan 07 12:31:37 PM PST 24
Finished Jan 07 12:33:35 PM PST 24
Peak memory 210688 kb
Host smart-6ea5d66e-6e62-4165-97ba-175c892ba004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518155102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3518155102
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.1126767617
Short name T206
Test name
Test status
Simulation time 13131151414 ps
CPU time 29.48 seconds
Started Jan 07 12:31:28 PM PST 24
Finished Jan 07 12:33:51 PM PST 24
Peak memory 213300 kb
Host smart-e441c6c5-2e6a-4499-94ab-58c500ea7783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126767617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1126767617
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.1711813281
Short name T274
Test name
Test status
Simulation time 173402054917 ps
CPU time 2984.93 seconds
Started Jan 07 12:31:22 PM PST 24
Finished Jan 07 01:22:39 PM PST 24
Peak memory 228940 kb
Host smart-a72d50cd-17cd-4566-9775-76f8fe0fbb92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711813281 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.1711813281
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.70714096
Short name T159
Test name
Test status
Simulation time 396294805 ps
CPU time 4.37 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:33:47 PM PST 24
Peak memory 210824 kb
Host smart-2bc096c2-23a5-47c3-83e6-015fcd757cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70714096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.70714096
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.4130725601
Short name T70
Test name
Test status
Simulation time 15765336616 ps
CPU time 39.5 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:37:08 PM PST 24
Peak memory 213428 kb
Host smart-1fa677d5-4acd-4a17-8e48-2b8e40ff3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130725601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.4130725601
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1669489238
Short name T224
Test name
Test status
Simulation time 2881987063 ps
CPU time 17.86 seconds
Started Jan 07 12:31:30 PM PST 24
Finished Jan 07 12:33:44 PM PST 24
Peak memory 213096 kb
Host smart-ffecbc8d-6ed1-4bce-bc0f-94f97cc07225
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669489238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1669489238
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.2318802030
Short name T186
Test name
Test status
Simulation time 625737758 ps
CPU time 8.59 seconds
Started Jan 07 12:31:28 PM PST 24
Finished Jan 07 12:32:59 PM PST 24
Peak memory 210832 kb
Host smart-e85c152c-5447-435c-a505-f07cbf6c1a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318802030 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2318802030
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.4199762173
Short name T280
Test name
Test status
Simulation time 71655531006 ps
CPU time 206.34 seconds
Started Jan 07 12:31:02 PM PST 24
Finished Jan 07 12:35:49 PM PST 24
Peak memory 233324 kb
Host smart-053b89a2-7ef9-4965-b15d-d4836c50ecb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199762173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.4199762173
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3576425327
Short name T19
Test name
Test status
Simulation time 693826229 ps
CPU time 9.63 seconds
Started Jan 07 12:31:21 PM PST 24
Finished Jan 07 12:32:45 PM PST 24
Peak memory 211036 kb
Host smart-83f88ff8-9f25-4f73-ae63-aefad7bd4c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576425327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3576425327
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3519399833
Short name T271
Test name
Test status
Simulation time 3652213557 ps
CPU time 37.28 seconds
Started Jan 07 12:31:30 PM PST 24
Finished Jan 07 12:33:50 PM PST 24
Peak memory 212720 kb
Host smart-63f570fb-4ee2-4744-85a6-ba05cb7794df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519399833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3519399833
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3091517798
Short name T236
Test name
Test status
Simulation time 2798412797 ps
CPU time 33.95 seconds
Started Jan 07 12:31:25 PM PST 24
Finished Jan 07 12:33:41 PM PST 24
Peak memory 214972 kb
Host smart-a6cfbdfe-7a99-4308-a4de-c6d1216f570a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091517798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3091517798
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1535726237
Short name T99
Test name
Test status
Simulation time 4983442414 ps
CPU time 11.63 seconds
Started Jan 07 12:31:40 PM PST 24
Finished Jan 07 12:33:44 PM PST 24
Peak memory 210616 kb
Host smart-fe30e8ac-73b8-43b0-8763-dca98819926d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535726237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1535726237
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.2133655643
Short name T18
Test name
Test status
Simulation time 7263091769 ps
CPU time 123.08 seconds
Started Jan 07 12:31:27 PM PST 24
Finished Jan 07 12:35:20 PM PST 24
Peak memory 227832 kb
Host smart-9fa16c3a-ca58-4a80-8e2e-145a47bf5f8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133655643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.2133655643
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1133320759
Short name T21
Test name
Test status
Simulation time 340627032 ps
CPU time 10 seconds
Started Jan 07 12:31:02 PM PST 24
Finished Jan 07 12:32:31 PM PST 24
Peak memory 211032 kb
Host smart-7496463b-ec45-43fb-ac33-b0e64eca7126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133320759 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1133320759
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.1588231494
Short name T69
Test name
Test status
Simulation time 13099884655 ps
CPU time 51.61 seconds
Started Jan 07 12:31:40 PM PST 24
Finished Jan 07 12:34:11 PM PST 24
Peak memory 215804 kb
Host smart-f513c918-c82c-43c9-8282-781f5c4ce585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588231494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.1588231494
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2881589619
Short name T103
Test name
Test status
Simulation time 8145449492 ps
CPU time 15.48 seconds
Started Jan 07 12:31:00 PM PST 24
Finished Jan 07 12:32:31 PM PST 24
Peak memory 210896 kb
Host smart-1b979f39-2f88-48ca-b189-75cb1a655e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881589619 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2881589619
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2354943810
Short name T1
Test name
Test status
Simulation time 6718672775 ps
CPU time 92.76 seconds
Started Jan 07 12:29:08 PM PST 24
Finished Jan 07 12:32:23 PM PST 24
Peak memory 211820 kb
Host smart-bdb6175d-d64b-4643-9ad4-bb6bf2c9abf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354943810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2354943810
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.83959575
Short name T219
Test name
Test status
Simulation time 2064127748 ps
CPU time 22.38 seconds
Started Jan 07 12:29:24 PM PST 24
Finished Jan 07 12:31:16 PM PST 24
Peak memory 210908 kb
Host smart-3cd05b76-6319-4181-bea8-a466e4875545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83959575 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.83959575
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.464109112
Short name T221
Test name
Test status
Simulation time 3282085390 ps
CPU time 15.22 seconds
Started Jan 07 12:29:10 PM PST 24
Finished Jan 07 12:30:49 PM PST 24
Peak memory 210548 kb
Host smart-7a186d64-4f23-4d6a-ba9b-9071376ceedf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=464109112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.464109112
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3655489247
Short name T6
Test name
Test status
Simulation time 378823658 ps
CPU time 60.13 seconds
Started Jan 07 12:29:58 PM PST 24
Finished Jan 07 12:32:33 PM PST 24
Peak memory 238200 kb
Host smart-2cbb8a1a-721a-4b99-b14f-9c0657473804
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655489247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3655489247
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.2885200506
Short name T2
Test name
Test status
Simulation time 2196974601 ps
CPU time 25.98 seconds
Started Jan 07 12:29:00 PM PST 24
Finished Jan 07 12:31:00 PM PST 24
Peak memory 213184 kb
Host smart-e8705fa6-17ee-4c62-9bc3-23c3280a86aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885200506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.2885200506
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1211631887
Short name T250
Test name
Test status
Simulation time 36648770494 ps
CPU time 2959.92 seconds
Started Jan 07 12:29:48 PM PST 24
Finished Jan 07 01:21:00 PM PST 24
Peak memory 235468 kb
Host smart-ed445c52-77f1-45a3-ad16-f3f4f2c67891
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211631887 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1211631887
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2590449926
Short name T191
Test name
Test status
Simulation time 2352373261 ps
CPU time 15.98 seconds
Started Jan 07 12:34:05 PM PST 24
Finished Jan 07 12:35:57 PM PST 24
Peak memory 210568 kb
Host smart-f663026e-99d1-4dee-a542-28808915ff2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590449926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2590449926
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.881498632
Short name T198
Test name
Test status
Simulation time 13536503450 ps
CPU time 123.55 seconds
Started Jan 07 12:30:54 PM PST 24
Finished Jan 07 12:34:29 PM PST 24
Peak memory 233320 kb
Host smart-18c86274-5c77-4cc1-8584-7be6b1e335f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881498632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_c
orrupt_sig_fatal_chk.881498632
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.585958782
Short name T147
Test name
Test status
Simulation time 1584927606 ps
CPU time 8.04 seconds
Started Jan 07 12:31:34 PM PST 24
Finished Jan 07 12:33:31 PM PST 24
Peak memory 210844 kb
Host smart-a31a2058-a919-4ac9-a4bf-d71a054db978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585958782 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.585958782
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.1641650283
Short name T166
Test name
Test status
Simulation time 544233406 ps
CPU time 10.07 seconds
Started Jan 07 12:31:42 PM PST 24
Finished Jan 07 12:33:21 PM PST 24
Peak memory 212620 kb
Host smart-2e34b69f-7503-46f9-889f-5052b102788e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641650283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.1641650283
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.793667329
Short name T167
Test name
Test status
Simulation time 18887399971 ps
CPU time 261.38 seconds
Started Jan 07 12:32:00 PM PST 24
Finished Jan 07 12:37:50 PM PST 24
Peak memory 237356 kb
Host smart-a7651b69-5f87-4b87-ba6b-5ea7d9fa38ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793667329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.793667329
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1154697816
Short name T226
Test name
Test status
Simulation time 175521538 ps
CPU time 9.6 seconds
Started Jan 07 12:33:20 PM PST 24
Finished Jan 07 12:34:43 PM PST 24
Peak memory 209156 kb
Host smart-d3c5613c-161b-46b6-a735-b7b362cfae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154697816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1154697816
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3840163565
Short name T234
Test name
Test status
Simulation time 7195371495 ps
CPU time 15.46 seconds
Started Jan 07 12:34:46 PM PST 24
Finished Jan 07 12:36:52 PM PST 24
Peak memory 210608 kb
Host smart-d6e5621d-5b82-4172-86b6-8ab11df11075
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3840163565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3840163565
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.2429163044
Short name T273
Test name
Test status
Simulation time 873173903 ps
CPU time 16.09 seconds
Started Jan 07 12:33:20 PM PST 24
Finished Jan 07 12:34:49 PM PST 24
Peak memory 210048 kb
Host smart-fe19118f-eb01-4f3d-aab6-1bbe0f6988c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429163044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.2429163044
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.351274645
Short name T182
Test name
Test status
Simulation time 4637883709 ps
CPU time 22.28 seconds
Started Jan 07 12:33:51 PM PST 24
Finished Jan 07 12:36:08 PM PST 24
Peak memory 215840 kb
Host smart-c1b71ffd-e254-4c8b-8c47-13fb2c5bdcd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351274645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.351274645
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3046985714
Short name T97
Test name
Test status
Simulation time 245481513976 ps
CPU time 4073.09 seconds
Started Jan 07 12:33:20 PM PST 24
Finished Jan 07 01:42:27 PM PST 24
Peak memory 242036 kb
Host smart-95ccce20-bb3f-4acb-93a4-6f5033cabbe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046985714 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3046985714
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1456333056
Short name T148
Test name
Test status
Simulation time 2380881354 ps
CPU time 7.47 seconds
Started Jan 07 12:30:54 PM PST 24
Finished Jan 07 12:33:05 PM PST 24
Peak memory 210908 kb
Host smart-e9dd015f-0981-4cd6-a0c4-94d119ed9da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456333056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1456333056
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.603369983
Short name T265
Test name
Test status
Simulation time 5767609649 ps
CPU time 94.06 seconds
Started Jan 07 12:31:31 PM PST 24
Finished Jan 07 12:35:14 PM PST 24
Peak memory 237324 kb
Host smart-1faa23ff-cc20-4250-bc6f-f6547956acdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603369983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_c
orrupt_sig_fatal_chk.603369983
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4192199093
Short name T233
Test name
Test status
Simulation time 1809614621 ps
CPU time 21.1 seconds
Started Jan 07 12:31:36 PM PST 24
Finished Jan 07 12:33:14 PM PST 24
Peak memory 210860 kb
Host smart-2f0ad143-3ea1-4c32-a9a4-4152090778bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192199093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4192199093
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.2776371997
Short name T217
Test name
Test status
Simulation time 1114977569 ps
CPU time 11.33 seconds
Started Jan 07 12:31:36 PM PST 24
Finished Jan 07 12:34:46 PM PST 24
Peak memory 210780 kb
Host smart-a0170ad6-71b4-4099-9130-cc204e512fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776371997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.2776371997
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2823781693
Short name T213
Test name
Test status
Simulation time 1972381526 ps
CPU time 25.03 seconds
Started Jan 07 12:33:53 PM PST 24
Finished Jan 07 12:35:49 PM PST 24
Peak memory 211932 kb
Host smart-88981495-ec2a-4bea-bc2e-113c04b80b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823781693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2823781693
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3880960572
Short name T189
Test name
Test status
Simulation time 894449315 ps
CPU time 7.56 seconds
Started Jan 07 12:31:43 PM PST 24
Finished Jan 07 12:33:12 PM PST 24
Peak memory 210892 kb
Host smart-75800ab5-d037-4131-8c42-f0f4f5d8e73c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880960572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3880960572
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2722820585
Short name T162
Test name
Test status
Simulation time 1258845018 ps
CPU time 12.41 seconds
Started Jan 07 12:32:25 PM PST 24
Finished Jan 07 12:34:09 PM PST 24
Peak memory 210772 kb
Host smart-4d55b141-637a-457a-a5d5-edeb93623978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722820585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2722820585
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.1387647736
Short name T54
Test name
Test status
Simulation time 1625411273 ps
CPU time 14.02 seconds
Started Jan 07 12:31:59 PM PST 24
Finished Jan 07 12:34:17 PM PST 24
Peak memory 210952 kb
Host smart-9d7fd947-c9ff-4d69-b171-4a77f7450c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387647736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.1387647736
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.4001595022
Short name T228
Test name
Test status
Simulation time 364959318995 ps
CPU time 243 seconds
Started Jan 07 12:31:54 PM PST 24
Finished Jan 07 12:37:14 PM PST 24
Peak memory 237416 kb
Host smart-9c5bf46c-9096-45ee-972c-8fe745b541d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001595022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.4001595022
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1671511560
Short name T266
Test name
Test status
Simulation time 12601206796 ps
CPU time 27.84 seconds
Started Jan 07 12:32:25 PM PST 24
Finished Jan 07 12:34:24 PM PST 24
Peak memory 211108 kb
Host smart-7adbb830-cae5-45dc-ade8-d81f5a2c7118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671511560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1671511560
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3556854742
Short name T16
Test name
Test status
Simulation time 95244543369 ps
CPU time 6206.39 seconds
Started Jan 07 12:32:17 PM PST 24
Finished Jan 07 02:17:27 PM PST 24
Peak memory 243736 kb
Host smart-a2c4b365-f0d5-49e4-bd09-6e936e76b480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556854742 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3556854742
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.2853870937
Short name T28
Test name
Test status
Simulation time 13771894807 ps
CPU time 200.82 seconds
Started Jan 07 12:32:23 PM PST 24
Finished Jan 07 12:37:32 PM PST 24
Peak memory 212764 kb
Host smart-2711783c-62b5-4205-8c51-a1f23826cb7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853870937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.2853870937
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3004948684
Short name T124
Test name
Test status
Simulation time 4572911351 ps
CPU time 16.68 seconds
Started Jan 07 12:32:06 PM PST 24
Finished Jan 07 12:35:07 PM PST 24
Peak memory 212524 kb
Host smart-7dbdc33d-5a87-4c61-a4f7-93f7a78294a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004948684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3004948684
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.1868473223
Short name T190
Test name
Test status
Simulation time 5564047227 ps
CPU time 11.87 seconds
Started Jan 07 12:32:18 PM PST 24
Finished Jan 07 12:34:01 PM PST 24
Peak memory 210784 kb
Host smart-7d853c08-541a-41f9-85b7-1d6a42ad7d14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1868473223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.1868473223
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4048130304
Short name T215
Test name
Test status
Simulation time 471391258 ps
CPU time 27.29 seconds
Started Jan 07 12:31:50 PM PST 24
Finished Jan 07 12:33:56 PM PST 24
Peak memory 214812 kb
Host smart-8a605c4d-c01a-453b-bd21-d8c8c68debdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048130304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4048130304
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1120777548
Short name T126
Test name
Test status
Simulation time 452442974 ps
CPU time 7.33 seconds
Started Jan 07 12:32:22 PM PST 24
Finished Jan 07 12:34:41 PM PST 24
Peak memory 210832 kb
Host smart-ecdb6d32-587d-4303-ae78-93493ff8c856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120777548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1120777548
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.449781564
Short name T248
Test name
Test status
Simulation time 6576208520 ps
CPU time 30.4 seconds
Started Jan 07 12:32:21 PM PST 24
Finished Jan 07 12:34:41 PM PST 24
Peak memory 211664 kb
Host smart-f47cf906-45dd-40b1-b443-8aaf245c363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449781564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.449781564
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3147335727
Short name T150
Test name
Test status
Simulation time 8431427311 ps
CPU time 17.44 seconds
Started Jan 07 12:32:00 PM PST 24
Finished Jan 07 12:34:06 PM PST 24
Peak memory 210532 kb
Host smart-3367e675-cf12-4306-b2f8-2d80fddca656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3147335727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3147335727
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2227233065
Short name T9
Test name
Test status
Simulation time 3556144202 ps
CPU time 37.53 seconds
Started Jan 07 12:32:23 PM PST 24
Finished Jan 07 12:34:49 PM PST 24
Peak memory 212376 kb
Host smart-a1c7e347-b25e-40b6-b16d-791300eaedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227233065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2227233065
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.352875695
Short name T33
Test name
Test status
Simulation time 7428556686 ps
CPU time 15.31 seconds
Started Jan 07 12:31:50 PM PST 24
Finished Jan 07 12:33:20 PM PST 24
Peak memory 210400 kb
Host smart-8fe8e1e6-fb9b-429c-880d-832cfa64eb59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352875695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.352875695
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3515744358
Short name T15
Test name
Test status
Simulation time 140916300686 ps
CPU time 962.05 seconds
Started Jan 07 12:31:51 PM PST 24
Finished Jan 07 12:50:01 PM PST 24
Peak memory 235452 kb
Host smart-8c536cf5-1a6c-41d8-bdc0-855fe7263193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515744358 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3515744358
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.1089852254
Short name T164
Test name
Test status
Simulation time 8579631501 ps
CPU time 16.15 seconds
Started Jan 07 12:32:20 PM PST 24
Finished Jan 07 12:34:09 PM PST 24
Peak memory 210940 kb
Host smart-33c64fc5-b2c2-4b19-9010-78410a34c6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089852254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1089852254
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1525903048
Short name T281
Test name
Test status
Simulation time 3946831436 ps
CPU time 128.82 seconds
Started Jan 07 12:31:52 PM PST 24
Finished Jan 07 12:35:31 PM PST 24
Peak memory 236372 kb
Host smart-19b04157-48b1-4634-85ad-64b891e1bd58
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525903048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1525903048
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3665253881
Short name T223
Test name
Test status
Simulation time 366461721 ps
CPU time 11.84 seconds
Started Jan 07 12:32:18 PM PST 24
Finished Jan 07 12:33:54 PM PST 24
Peak memory 210948 kb
Host smart-4a3095cb-29ef-4ef8-8937-8af005a86d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665253881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3665253881
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1619137649
Short name T154
Test name
Test status
Simulation time 772651501 ps
CPU time 5.82 seconds
Started Jan 07 12:32:20 PM PST 24
Finished Jan 07 12:34:00 PM PST 24
Peak memory 210780 kb
Host smart-53894b04-a31f-4288-99d0-cedd35c333e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619137649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1619137649
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2083404054
Short name T237
Test name
Test status
Simulation time 381151404 ps
CPU time 10.58 seconds
Started Jan 07 12:32:22 PM PST 24
Finished Jan 07 12:33:53 PM PST 24
Peak memory 212420 kb
Host smart-6c2598ae-6a74-481e-a0e5-17389d13a3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083404054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2083404054
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.1530824379
Short name T267
Test name
Test status
Simulation time 28312787590 ps
CPU time 53.65 seconds
Started Jan 07 12:31:56 PM PST 24
Finished Jan 07 12:34:40 PM PST 24
Peak memory 216364 kb
Host smart-63167acc-5ccf-4220-86ab-fcaeb9dd0585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530824379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.1530824379
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1052785311
Short name T42
Test name
Test status
Simulation time 26083820181 ps
CPU time 1004.82 seconds
Started Jan 07 12:31:51 PM PST 24
Finished Jan 07 12:50:15 PM PST 24
Peak memory 227844 kb
Host smart-e09b94e2-cc36-4daf-861a-0c7f22c8d1f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052785311 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1052785311
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.4022068623
Short name T268
Test name
Test status
Simulation time 12590249695 ps
CPU time 13.66 seconds
Started Jan 07 12:32:24 PM PST 24
Finished Jan 07 12:34:11 PM PST 24
Peak memory 210964 kb
Host smart-d6498346-170b-4381-9991-25b60b12d827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022068623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.4022068623
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.132158810
Short name T46
Test name
Test status
Simulation time 4179079344 ps
CPU time 33.22 seconds
Started Jan 07 12:32:23 PM PST 24
Finished Jan 07 12:34:24 PM PST 24
Peak memory 210904 kb
Host smart-a686c862-e5db-488f-a566-1af367809fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132158810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.132158810
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.2774836644
Short name T225
Test name
Test status
Simulation time 4336722066 ps
CPU time 34.13 seconds
Started Jan 07 12:32:25 PM PST 24
Finished Jan 07 12:34:30 PM PST 24
Peak memory 212380 kb
Host smart-80cbc8ae-2499-4f41-b0a4-f14a31a08800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774836644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.2774836644
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1538973027
Short name T45
Test name
Test status
Simulation time 9391118518 ps
CPU time 20.05 seconds
Started Jan 07 12:32:19 PM PST 24
Finished Jan 07 12:33:57 PM PST 24
Peak memory 213436 kb
Host smart-02ddbcd2-1560-438e-b763-32beec33e28a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538973027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1538973027
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.1427453461
Short name T41
Test name
Test status
Simulation time 74193857428 ps
CPU time 2758.68 seconds
Started Jan 07 12:32:23 PM PST 24
Finished Jan 07 01:19:50 PM PST 24
Peak memory 235484 kb
Host smart-7654c2d5-c3fb-4417-930d-9150d405740c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427453461 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.1427453461
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2166104971
Short name T136
Test name
Test status
Simulation time 4972952379 ps
CPU time 11.43 seconds
Started Jan 07 12:32:01 PM PST 24
Finished Jan 07 12:34:27 PM PST 24
Peak memory 210604 kb
Host smart-ec131e4f-1838-43dd-ba52-368050840dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166104971 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2166104971
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.579100920
Short name T122
Test name
Test status
Simulation time 32701594600 ps
CPU time 311.28 seconds
Started Jan 07 12:31:55 PM PST 24
Finished Jan 07 12:38:34 PM PST 24
Peak memory 234344 kb
Host smart-1dba7a1b-e426-432e-83e7-ae268bd6a805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579100920 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_c
orrupt_sig_fatal_chk.579100920
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.4146765034
Short name T20
Test name
Test status
Simulation time 175401943 ps
CPU time 9.62 seconds
Started Jan 07 12:32:30 PM PST 24
Finished Jan 07 12:33:59 PM PST 24
Peak memory 210756 kb
Host smart-d1fcdb77-3ac6-45be-9aed-8a8ed24ec83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146765034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.4146765034
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.400098104
Short name T285
Test name
Test status
Simulation time 3344040080 ps
CPU time 14.65 seconds
Started Jan 07 12:31:53 PM PST 24
Finished Jan 07 12:33:27 PM PST 24
Peak memory 210532 kb
Host smart-21556a53-8eb0-45e9-bfc8-90d3b456008e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=400098104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.400098104
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3741051564
Short name T158
Test name
Test status
Simulation time 29457674444 ps
CPU time 223.07 seconds
Started Jan 07 12:29:03 PM PST 24
Finished Jan 07 12:33:58 PM PST 24
Peak memory 212096 kb
Host smart-bb16d869-7a72-49d6-aa4e-874b3fc94a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741051564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3741051564
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.2251073990
Short name T197
Test name
Test status
Simulation time 15743034766 ps
CPU time 31.35 seconds
Started Jan 07 12:29:04 PM PST 24
Finished Jan 07 12:30:46 PM PST 24
Peak memory 211408 kb
Host smart-9fca4bf4-e68f-41a1-b14c-97c343c0010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251073990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.2251073990
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.69470276
Short name T132
Test name
Test status
Simulation time 194895068 ps
CPU time 5.97 seconds
Started Jan 07 12:29:39 PM PST 24
Finished Jan 07 12:32:04 PM PST 24
Peak memory 210824 kb
Host smart-744095c3-bd3f-4f2e-afe3-9d4f6c7377fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69470276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.69470276
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.4041356351
Short name T229
Test name
Test status
Simulation time 3624939568 ps
CPU time 39.18 seconds
Started Jan 07 12:29:07 PM PST 24
Finished Jan 07 12:31:14 PM PST 24
Peak memory 215336 kb
Host smart-7ea139da-cbb0-4d9e-8e82-ed246d0dbccb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041356351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.4041356351
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.169528207
Short name T130
Test name
Test status
Simulation time 37521863296 ps
CPU time 15.72 seconds
Started Jan 07 12:29:46 PM PST 24
Finished Jan 07 12:32:20 PM PST 24
Peak memory 210856 kb
Host smart-ceb5f6d5-3d52-4c7b-bef3-6c1bb8086cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169528207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.169528207
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1781357229
Short name T171
Test name
Test status
Simulation time 1541916471 ps
CPU time 98.28 seconds
Started Jan 07 12:29:11 PM PST 24
Finished Jan 07 12:32:31 PM PST 24
Peak memory 236252 kb
Host smart-b302e6e1-ab20-4a08-b6f5-b686771a3731
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781357229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1781357229
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.624733938
Short name T232
Test name
Test status
Simulation time 20319763598 ps
CPU time 28.02 seconds
Started Jan 07 12:29:11 PM PST 24
Finished Jan 07 12:31:16 PM PST 24
Peak memory 212144 kb
Host smart-2b6e5852-4ef2-4916-9266-95006b35de42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624733938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.624733938
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3131123110
Short name T137
Test name
Test status
Simulation time 9767759521 ps
CPU time 11.45 seconds
Started Jan 07 12:29:04 PM PST 24
Finished Jan 07 12:30:32 PM PST 24
Peak memory 210912 kb
Host smart-9be3f44d-c8a4-4a2c-a115-c713dd617416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131123110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3131123110
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1090773794
Short name T68
Test name
Test status
Simulation time 1858966572 ps
CPU time 13.59 seconds
Started Jan 07 12:29:04 PM PST 24
Finished Jan 07 12:30:45 PM PST 24
Peak memory 213144 kb
Host smart-c7be8965-fda8-4dc0-9fb0-c39e05a87b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090773794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1090773794
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.1848167656
Short name T165
Test name
Test status
Simulation time 27183736402 ps
CPU time 59.77 seconds
Started Jan 07 12:29:00 PM PST 24
Finished Jan 07 12:31:45 PM PST 24
Peak memory 216568 kb
Host smart-ca4e6644-54c3-4c57-b020-19deee7d6826
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848167656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.1848167656
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.2866939704
Short name T8
Test name
Test status
Simulation time 1981178834 ps
CPU time 7.85 seconds
Started Jan 07 12:29:45 PM PST 24
Finished Jan 07 12:31:32 PM PST 24
Peak memory 210932 kb
Host smart-50e3e56e-ff57-452c-a427-4a2783fb8827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866939704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.2866939704
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2820636980
Short name T200
Test name
Test status
Simulation time 36263546092 ps
CPU time 386.57 seconds
Started Jan 07 12:30:47 PM PST 24
Finished Jan 07 12:39:44 PM PST 24
Peak memory 212872 kb
Host smart-90045204-612a-402f-a6d1-e8be881a1180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820636980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2820636980
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1132457439
Short name T276
Test name
Test status
Simulation time 4470822052 ps
CPU time 10.43 seconds
Started Jan 07 12:30:45 PM PST 24
Finished Jan 07 12:32:10 PM PST 24
Peak memory 210744 kb
Host smart-ffa68c33-52a2-41e1-840f-65fa82f83d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132457439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1132457439
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1882649877
Short name T47
Test name
Test status
Simulation time 2476456719 ps
CPU time 23.99 seconds
Started Jan 07 12:30:43 PM PST 24
Finished Jan 07 12:32:53 PM PST 24
Peak memory 211032 kb
Host smart-5275bcfd-b318-4ffb-9adb-26866fa07feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882649877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1882649877
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.3876862811
Short name T143
Test name
Test status
Simulation time 469887684 ps
CPU time 8.35 seconds
Started Jan 07 12:29:19 PM PST 24
Finished Jan 07 12:31:01 PM PST 24
Peak memory 210772 kb
Host smart-599a9901-e22b-493d-8114-9e280b80b3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3876862811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.3876862811
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1759858268
Short name T240
Test name
Test status
Simulation time 1024005349 ps
CPU time 18.02 seconds
Started Jan 07 12:29:16 PM PST 24
Finished Jan 07 12:31:07 PM PST 24
Peak memory 212232 kb
Host smart-7a9beaad-b612-442e-917d-a42d0efa3cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759858268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1759858268
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.1581668679
Short name T238
Test name
Test status
Simulation time 17128117807 ps
CPU time 50.23 seconds
Started Jan 07 12:29:25 PM PST 24
Finished Jan 07 12:31:49 PM PST 24
Peak memory 216268 kb
Host smart-3ce715f7-57b5-499d-bb3c-6854877221de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581668679 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.1581668679
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.3149384627
Short name T39
Test name
Test status
Simulation time 15804156022 ps
CPU time 2872.78 seconds
Started Jan 07 12:30:16 PM PST 24
Finished Jan 07 01:19:41 PM PST 24
Peak memory 224504 kb
Host smart-8c91c76a-2c8b-4066-a669-506251a513ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149384627 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.3149384627
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2567414065
Short name T25
Test name
Test status
Simulation time 6990412665 ps
CPU time 30 seconds
Started Jan 07 12:30:05 PM PST 24
Finished Jan 07 12:31:58 PM PST 24
Peak memory 211312 kb
Host smart-c264cf55-82ed-4cdb-97ab-d9bea4502373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567414065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2567414065
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1986644424
Short name T208
Test name
Test status
Simulation time 4117588019 ps
CPU time 16.53 seconds
Started Jan 07 12:30:38 PM PST 24
Finished Jan 07 12:33:02 PM PST 24
Peak memory 210828 kb
Host smart-a42eda28-fffd-45a7-a730-50c0a3f70677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986644424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1986644424
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.3354051918
Short name T242
Test name
Test status
Simulation time 32777671551 ps
CPU time 25.72 seconds
Started Jan 07 12:30:27 PM PST 24
Finished Jan 07 12:32:39 PM PST 24
Peak memory 212900 kb
Host smart-92937a56-0162-454a-b03b-aaedf0cc10e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354051918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.3354051918
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.390084886
Short name T111
Test name
Test status
Simulation time 15278713206 ps
CPU time 34.95 seconds
Started Jan 07 12:30:47 PM PST 24
Finished Jan 07 12:32:48 PM PST 24
Peak memory 213012 kb
Host smart-41c3178d-388c-4e4f-b150-8cce2ac1b6a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390084886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.390084886
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.514716096
Short name T17
Test name
Test status
Simulation time 137665999333 ps
CPU time 4610.4 seconds
Started Jan 07 12:30:41 PM PST 24
Finished Jan 07 01:48:59 PM PST 24
Peak memory 235468 kb
Host smart-e2cb533e-860f-4597-ab65-42f67f21af8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514716096 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.514716096
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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