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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.67 97.11 93.12 97.88 100.00 98.69 98.04 98.84


Total test records in report: 476
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T263 /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4263656131 Jan 10 01:04:08 PM PST 24 Jan 10 01:18:57 PM PST 24 49266581509 ps
T264 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3777938572 Jan 10 01:04:08 PM PST 24 Jan 10 01:07:44 PM PST 24 15970902810 ps
T265 /workspace/coverage/default/16.rom_ctrl_stress_all.4078972416 Jan 10 01:04:17 PM PST 24 Jan 10 01:06:08 PM PST 24 6212154110 ps
T266 /workspace/coverage/default/5.rom_ctrl_stress_all.674087321 Jan 10 01:04:02 PM PST 24 Jan 10 01:05:33 PM PST 24 848437676 ps
T267 /workspace/coverage/default/36.rom_ctrl_stress_all.519849418 Jan 10 01:05:11 PM PST 24 Jan 10 01:07:55 PM PST 24 8883162125 ps
T268 /workspace/coverage/default/19.rom_ctrl_stress_all.3423003535 Jan 10 01:04:27 PM PST 24 Jan 10 01:06:36 PM PST 24 819050704 ps
T269 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.374984092 Jan 10 01:04:45 PM PST 24 Jan 10 01:06:11 PM PST 24 371788674 ps
T270 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.121031816 Jan 10 01:05:12 PM PST 24 Jan 10 01:06:48 PM PST 24 696289803 ps
T271 /workspace/coverage/default/39.rom_ctrl_smoke.4267156907 Jan 10 01:05:04 PM PST 24 Jan 10 01:07:00 PM PST 24 194275415 ps
T272 /workspace/coverage/default/40.rom_ctrl_smoke.381899562 Jan 10 01:04:54 PM PST 24 Jan 10 01:06:43 PM PST 24 8253467707 ps
T273 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2497141951 Jan 10 01:04:57 PM PST 24 Jan 10 01:39:45 PM PST 24 192928898983 ps
T274 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3258677826 Jan 10 01:04:16 PM PST 24 Jan 10 01:05:40 PM PST 24 196498431 ps
T275 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3175917125 Jan 10 01:06:27 PM PST 24 Jan 10 01:08:50 PM PST 24 4566702336 ps
T276 /workspace/coverage/default/23.rom_ctrl_alert_test.2529563451 Jan 10 01:04:42 PM PST 24 Jan 10 01:06:15 PM PST 24 1725649359 ps
T277 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2172874571 Jan 10 01:06:43 PM PST 24 Jan 10 01:08:05 PM PST 24 172094424 ps
T278 /workspace/coverage/default/8.rom_ctrl_smoke.1395364682 Jan 10 01:03:58 PM PST 24 Jan 10 01:05:47 PM PST 24 10972344487 ps
T279 /workspace/coverage/default/25.rom_ctrl_alert_test.2517448554 Jan 10 01:04:46 PM PST 24 Jan 10 01:06:27 PM PST 24 9240426775 ps
T280 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.438200856 Jan 10 01:04:18 PM PST 24 Jan 10 01:07:30 PM PST 24 1660096316 ps
T281 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.557142738 Jan 10 01:04:25 PM PST 24 Jan 10 02:07:30 PM PST 24 206744769714 ps
T282 /workspace/coverage/default/3.rom_ctrl_alert_test.1637641916 Jan 10 01:04:10 PM PST 24 Jan 10 01:05:40 PM PST 24 347474459 ps
T283 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.617861659 Jan 10 01:04:22 PM PST 24 Jan 10 01:05:45 PM PST 24 839319768 ps
T284 /workspace/coverage/default/5.rom_ctrl_alert_test.2144695986 Jan 10 01:04:06 PM PST 24 Jan 10 01:05:41 PM PST 24 16838088595 ps
T285 /workspace/coverage/default/21.rom_ctrl_stress_all.2230724653 Jan 10 01:04:46 PM PST 24 Jan 10 01:07:26 PM PST 24 30238891634 ps
T286 /workspace/coverage/default/21.rom_ctrl_alert_test.2859504551 Jan 10 01:03:59 PM PST 24 Jan 10 01:05:34 PM PST 24 1465526311 ps
T287 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.250993528 Jan 10 01:04:44 PM PST 24 Jan 10 01:10:31 PM PST 24 27518371732 ps
T288 /workspace/coverage/default/34.rom_ctrl_alert_test.3469408322 Jan 10 01:04:47 PM PST 24 Jan 10 01:06:37 PM PST 24 3135325919 ps
T289 /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3065357369 Jan 10 01:04:53 PM PST 24 Jan 10 01:06:43 PM PST 24 14321343569 ps
T290 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3314494758 Jan 10 01:04:41 PM PST 24 Jan 10 01:06:12 PM PST 24 3376952826 ps
T291 /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3162860678 Jan 10 01:04:54 PM PST 24 Jan 10 01:15:44 PM PST 24 116342962208 ps
T292 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.466991578 Jan 10 01:03:58 PM PST 24 Jan 10 01:05:29 PM PST 24 4466534432 ps
T293 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1897402151 Jan 10 01:04:58 PM PST 24 Jan 10 01:06:37 PM PST 24 1510558862 ps
T294 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2221838726 Jan 10 01:04:10 PM PST 24 Jan 10 01:09:43 PM PST 24 40465279015 ps
T295 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.629168100 Jan 10 01:04:44 PM PST 24 Jan 10 01:06:33 PM PST 24 168595182 ps
T296 /workspace/coverage/default/38.rom_ctrl_stress_all.1484386286 Jan 10 01:04:53 PM PST 24 Jan 10 01:08:09 PM PST 24 12947698537 ps
T297 /workspace/coverage/default/31.rom_ctrl_alert_test.2227003242 Jan 10 01:04:45 PM PST 24 Jan 10 01:06:24 PM PST 24 8419416418 ps
T298 /workspace/coverage/default/36.rom_ctrl_smoke.881383881 Jan 10 01:04:52 PM PST 24 Jan 10 01:06:59 PM PST 24 2133301910 ps
T299 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1678643644 Jan 10 01:04:05 PM PST 24 Jan 10 01:51:24 PM PST 24 80138720728 ps
T300 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.318165549 Jan 10 01:05:20 PM PST 24 Jan 10 01:07:18 PM PST 24 15637394868 ps
T301 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.725469219 Jan 10 01:04:32 PM PST 24 Jan 10 01:06:39 PM PST 24 16700151291 ps
T302 /workspace/coverage/default/42.rom_ctrl_smoke.1529762417 Jan 10 01:05:03 PM PST 24 Jan 10 01:07:03 PM PST 24 8456526070 ps
T303 /workspace/coverage/default/14.rom_ctrl_alert_test.2628290127 Jan 10 01:04:32 PM PST 24 Jan 10 01:06:03 PM PST 24 992634693 ps
T304 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4238182449 Jan 10 01:04:05 PM PST 24 Jan 10 01:05:32 PM PST 24 168793173 ps
T305 /workspace/coverage/default/41.rom_ctrl_stress_all.2428733823 Jan 10 01:05:18 PM PST 24 Jan 10 01:07:10 PM PST 24 3031221500 ps
T306 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4121662783 Jan 10 01:03:57 PM PST 24 Jan 10 01:07:19 PM PST 24 40546667221 ps
T307 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2957038770 Jan 10 01:04:52 PM PST 24 Jan 10 01:09:50 PM PST 24 129108697097 ps
T308 /workspace/coverage/default/11.rom_ctrl_alert_test.3244709816 Jan 10 01:04:06 PM PST 24 Jan 10 01:05:39 PM PST 24 754625077 ps
T309 /workspace/coverage/default/42.rom_ctrl_stress_all.3075723349 Jan 10 01:04:57 PM PST 24 Jan 10 01:07:17 PM PST 24 4946526442 ps
T310 /workspace/coverage/default/35.rom_ctrl_stress_all.904245628 Jan 10 01:04:50 PM PST 24 Jan 10 01:06:59 PM PST 24 3251098705 ps
T311 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2660861173 Jan 10 01:04:34 PM PST 24 Jan 10 01:06:11 PM PST 24 4530624698 ps
T312 /workspace/coverage/default/9.rom_ctrl_stress_all.2182025311 Jan 10 01:03:59 PM PST 24 Jan 10 01:06:09 PM PST 24 4353388944 ps
T313 /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1222592631 Jan 10 01:04:42 PM PST 24 Jan 10 01:13:16 PM PST 24 605181049216 ps
T314 /workspace/coverage/default/30.rom_ctrl_stress_all.2453987500 Jan 10 01:04:42 PM PST 24 Jan 10 01:06:13 PM PST 24 1026140365 ps
T315 /workspace/coverage/default/44.rom_ctrl_smoke.1385916305 Jan 10 01:04:57 PM PST 24 Jan 10 01:06:38 PM PST 24 186161572 ps
T316 /workspace/coverage/default/40.rom_ctrl_stress_all.425760587 Jan 10 01:04:51 PM PST 24 Jan 10 01:06:44 PM PST 24 7362418879 ps
T317 /workspace/coverage/default/13.rom_ctrl_smoke.3806114882 Jan 10 01:04:04 PM PST 24 Jan 10 01:05:57 PM PST 24 7570019650 ps
T318 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.965478416 Jan 10 01:03:52 PM PST 24 Jan 10 01:05:20 PM PST 24 1482378934 ps
T319 /workspace/coverage/default/4.rom_ctrl_stress_all.1166912144 Jan 10 01:03:56 PM PST 24 Jan 10 01:05:50 PM PST 24 34577922303 ps
T320 /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3929786792 Jan 10 01:04:03 PM PST 24 Jan 10 01:23:10 PM PST 24 57391973262 ps
T321 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.784009535 Jan 10 01:03:52 PM PST 24 Jan 10 01:34:41 PM PST 24 163063350070 ps
T322 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1719974095 Jan 10 01:04:25 PM PST 24 Jan 10 01:05:56 PM PST 24 717542532 ps
T323 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3740627513 Jan 10 01:04:05 PM PST 24 Jan 10 01:05:47 PM PST 24 1426122113 ps
T324 /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2702953764 Jan 10 01:04:10 PM PST 24 Jan 10 01:06:04 PM PST 24 8168114323 ps
T325 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1112782227 Jan 10 01:03:59 PM PST 24 Jan 10 01:12:36 PM PST 24 157990275397 ps
T326 /workspace/coverage/default/46.rom_ctrl_alert_test.2475420723 Jan 10 01:05:11 PM PST 24 Jan 10 01:06:58 PM PST 24 1869747553 ps
T327 /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.172264711 Jan 10 01:06:27 PM PST 24 Jan 10 01:14:39 PM PST 24 258530766938 ps
T328 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1010862263 Jan 10 01:04:47 PM PST 24 Jan 10 01:07:26 PM PST 24 5781402631 ps
T329 /workspace/coverage/default/43.rom_ctrl_stress_all.2698993822 Jan 10 01:04:50 PM PST 24 Jan 10 01:06:23 PM PST 24 2736553466 ps
T330 /workspace/coverage/default/29.rom_ctrl_stress_all.3614129753 Jan 10 01:06:16 PM PST 24 Jan 10 01:08:21 PM PST 24 18248674212 ps
T331 /workspace/coverage/default/46.rom_ctrl_smoke.4067765961 Jan 10 01:05:30 PM PST 24 Jan 10 01:07:45 PM PST 24 10560864277 ps
T332 /workspace/coverage/default/48.rom_ctrl_alert_test.3018315838 Jan 10 01:05:39 PM PST 24 Jan 10 01:07:20 PM PST 24 1535150126 ps
T333 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.395819531 Jan 10 01:06:43 PM PST 24 Jan 10 01:08:23 PM PST 24 3076495578 ps
T334 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3572362538 Jan 10 01:04:25 PM PST 24 Jan 10 01:11:52 PM PST 24 134786937172 ps
T335 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3349581178 Jan 10 01:03:58 PM PST 24 Jan 10 01:05:43 PM PST 24 2811867406 ps
T336 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2540668483 Jan 10 01:04:54 PM PST 24 Jan 10 01:06:28 PM PST 24 171913937 ps
T337 /workspace/coverage/default/20.rom_ctrl_stress_all.2381919498 Jan 10 01:04:14 PM PST 24 Jan 10 01:06:18 PM PST 24 24002835532 ps
T338 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1759563052 Jan 10 01:04:04 PM PST 24 Jan 10 01:05:49 PM PST 24 2156836056 ps
T339 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2662671111 Jan 10 01:04:15 PM PST 24 Jan 10 01:09:18 PM PST 24 43196761093 ps
T340 /workspace/coverage/default/6.rom_ctrl_stress_all.3956378338 Jan 10 01:03:57 PM PST 24 Jan 10 01:05:49 PM PST 24 685519969 ps
T341 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1242323889 Jan 10 01:05:18 PM PST 24 Jan 10 01:07:12 PM PST 24 29715127180 ps
T342 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4127949954 Jan 10 01:04:51 PM PST 24 Jan 10 01:12:51 PM PST 24 43731367944 ps
T343 /workspace/coverage/default/27.rom_ctrl_alert_test.2961721145 Jan 10 01:06:43 PM PST 24 Jan 10 01:08:23 PM PST 24 4826749467 ps
T344 /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.51879 Jan 10 01:04:03 PM PST 24 Jan 10 01:35:30 PM PST 24 41889888108 ps
T345 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3354177546 Jan 10 01:04:56 PM PST 24 Jan 10 02:26:22 PM PST 24 186069718021 ps
T346 /workspace/coverage/default/8.rom_ctrl_stress_all.484829739 Jan 10 01:04:06 PM PST 24 Jan 10 01:05:44 PM PST 24 2633048117 ps
T347 /workspace/coverage/default/12.rom_ctrl_smoke.1951988514 Jan 10 01:04:09 PM PST 24 Jan 10 01:05:59 PM PST 24 6622095230 ps
T348 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1757975283 Jan 10 01:04:53 PM PST 24 Jan 10 01:12:18 PM PST 24 379988140852 ps
T349 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3651996596 Jan 10 01:04:51 PM PST 24 Jan 10 01:06:50 PM PST 24 25135467340 ps
T350 /workspace/coverage/default/26.rom_ctrl_stress_all.1358301192 Jan 10 01:04:54 PM PST 24 Jan 10 01:06:30 PM PST 24 226209438 ps
T351 /workspace/coverage/default/29.rom_ctrl_alert_test.1378779633 Jan 10 01:04:19 PM PST 24 Jan 10 01:05:41 PM PST 24 1381291451 ps
T352 /workspace/coverage/default/36.rom_ctrl_alert_test.1087828403 Jan 10 01:05:03 PM PST 24 Jan 10 01:06:51 PM PST 24 2996797318 ps
T353 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1610025072 Jan 10 01:04:05 PM PST 24 Jan 10 01:11:29 PM PST 24 149436733089 ps
T354 /workspace/coverage/default/19.rom_ctrl_smoke.3048250298 Jan 10 01:04:14 PM PST 24 Jan 10 01:06:27 PM PST 24 16414960603 ps
T355 /workspace/coverage/default/10.rom_ctrl_alert_test.3862069600 Jan 10 01:04:10 PM PST 24 Jan 10 01:05:53 PM PST 24 4095902765 ps
T356 /workspace/coverage/default/22.rom_ctrl_alert_test.466328991 Jan 10 01:04:11 PM PST 24 Jan 10 01:05:50 PM PST 24 7211721187 ps
T357 /workspace/coverage/default/19.rom_ctrl_alert_test.785232237 Jan 10 01:04:13 PM PST 24 Jan 10 01:05:35 PM PST 24 346640456 ps
T358 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.404547434 Jan 10 01:04:48 PM PST 24 Jan 10 01:06:36 PM PST 24 2933392881 ps
T359 /workspace/coverage/default/3.rom_ctrl_smoke.3103931766 Jan 10 01:04:09 PM PST 24 Jan 10 01:06:07 PM PST 24 3533028929 ps
T360 /workspace/coverage/default/17.rom_ctrl_alert_test.2933513737 Jan 10 01:04:35 PM PST 24 Jan 10 01:06:32 PM PST 24 1843462927 ps
T361 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4233650149 Jan 10 01:04:29 PM PST 24 Jan 10 01:14:09 PM PST 24 197495318605 ps
T362 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2561124706 Jan 10 01:04:34 PM PST 24 Jan 10 01:12:45 PM PST 24 149628861761 ps
T363 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.403229390 Jan 10 01:04:26 PM PST 24 Jan 10 01:06:13 PM PST 24 13520031318 ps
T364 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2746561950 Jan 10 01:04:50 PM PST 24 Jan 10 01:06:28 PM PST 24 6717373344 ps
T365 /workspace/coverage/default/28.rom_ctrl_smoke.2769436949 Jan 10 01:04:21 PM PST 24 Jan 10 01:06:21 PM PST 24 25758911226 ps
T45 /workspace/coverage/default/4.rom_ctrl_sec_cm.2053929364 Jan 10 01:04:07 PM PST 24 Jan 10 01:06:26 PM PST 24 469695197 ps
T366 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2405577340 Jan 10 01:04:34 PM PST 24 Jan 10 01:43:55 PM PST 24 60156739707 ps
T367 /workspace/coverage/default/18.rom_ctrl_smoke.2663547638 Jan 10 01:04:14 PM PST 24 Jan 10 01:06:01 PM PST 24 2838036920 ps
T368 /workspace/coverage/default/2.rom_ctrl_alert_test.4167507208 Jan 10 01:04:00 PM PST 24 Jan 10 01:05:27 PM PST 24 348160494 ps
T369 /workspace/coverage/default/18.rom_ctrl_stress_all.666727148 Jan 10 01:04:19 PM PST 24 Jan 10 01:05:55 PM PST 24 2911620995 ps
T370 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.748846519 Jan 10 01:04:05 PM PST 24 Jan 10 01:13:22 PM PST 24 176539868353 ps
T371 /workspace/coverage/default/30.rom_ctrl_alert_test.3650049557 Jan 10 01:04:44 PM PST 24 Jan 10 01:06:16 PM PST 24 85650772 ps
T372 /workspace/coverage/default/32.rom_ctrl_smoke.525152822 Jan 10 01:06:27 PM PST 24 Jan 10 01:08:18 PM PST 24 3239668697 ps
T373 /workspace/coverage/default/24.rom_ctrl_alert_test.733727293 Jan 10 01:04:19 PM PST 24 Jan 10 01:06:01 PM PST 24 1284815762 ps
T374 /workspace/coverage/default/42.rom_ctrl_alert_test.3569445383 Jan 10 01:04:52 PM PST 24 Jan 10 01:06:43 PM PST 24 1614982838 ps
T375 /workspace/coverage/default/11.rom_ctrl_smoke.2787777435 Jan 10 01:04:08 PM PST 24 Jan 10 01:05:41 PM PST 24 4694959640 ps
T376 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1375351311 Jan 10 01:04:44 PM PST 24 Jan 10 01:06:51 PM PST 24 2438537515 ps
T377 /workspace/coverage/default/49.rom_ctrl_stress_all.2962804783 Jan 10 01:05:10 PM PST 24 Jan 10 01:07:25 PM PST 24 28728392415 ps
T378 /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3859875881 Jan 10 01:04:50 PM PST 24 Jan 10 01:07:59 PM PST 24 1511391349 ps
T379 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3666917664 Jan 10 01:04:42 PM PST 24 Jan 10 01:06:25 PM PST 24 1850562726 ps
T380 /workspace/coverage/default/6.rom_ctrl_alert_test.3928938473 Jan 10 01:04:05 PM PST 24 Jan 10 01:05:28 PM PST 24 88870462 ps
T381 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2106648899 Jan 10 01:04:05 PM PST 24 Jan 10 01:05:47 PM PST 24 581430416 ps
T382 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3576815550 Jan 10 01:04:41 PM PST 24 Jan 10 01:06:11 PM PST 24 3335964899 ps
T383 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.417390293 Jan 10 01:04:22 PM PST 24 Jan 10 01:05:53 PM PST 24 1243176810 ps
T384 /workspace/coverage/default/15.rom_ctrl_stress_all.2229971876 Jan 10 01:04:31 PM PST 24 Jan 10 01:07:11 PM PST 24 34539878848 ps
T385 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.982323521 Jan 10 01:04:11 PM PST 24 Jan 10 01:06:03 PM PST 24 27173038002 ps
T386 /workspace/coverage/default/15.rom_ctrl_smoke.1192265104 Jan 10 01:04:07 PM PST 24 Jan 10 01:05:41 PM PST 24 713331934 ps
T387 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2435856242 Jan 10 01:04:37 PM PST 24 Jan 10 01:06:20 PM PST 24 4040866048 ps
T388 /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2487244187 Jan 10 01:04:48 PM PST 24 Jan 10 01:35:10 PM PST 24 9553004101 ps
T389 /workspace/coverage/default/24.rom_ctrl_stress_all.1206548709 Jan 10 01:04:51 PM PST 24 Jan 10 01:07:13 PM PST 24 10638188013 ps
T390 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2783127459 Jan 10 01:04:35 PM PST 24 Jan 10 01:31:05 PM PST 24 78889309111 ps
T391 /workspace/coverage/default/12.rom_ctrl_stress_all.2959823586 Jan 10 01:04:12 PM PST 24 Jan 10 01:05:52 PM PST 24 231567807 ps
T392 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2220965879 Jan 10 01:04:41 PM PST 24 Jan 10 01:06:35 PM PST 24 1683950912 ps
T393 /workspace/coverage/default/45.rom_ctrl_stress_all.145527087 Jan 10 01:05:05 PM PST 24 Jan 10 01:07:59 PM PST 24 16850935501 ps
T110 /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.34190500 Jan 10 01:05:03 PM PST 24 Jan 10 01:46:30 PM PST 24 268804465021 ps
T394 /workspace/coverage/default/35.rom_ctrl_alert_test.2911890138 Jan 10 01:05:19 PM PST 24 Jan 10 01:06:52 PM PST 24 309518222 ps
T395 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1030834390 Jan 10 01:04:07 PM PST 24 Jan 10 01:06:14 PM PST 24 8544195891 ps
T396 /workspace/coverage/default/2.rom_ctrl_smoke.870760133 Jan 10 01:04:03 PM PST 24 Jan 10 01:05:49 PM PST 24 9482757424 ps
T397 /workspace/coverage/default/39.rom_ctrl_alert_test.3034762868 Jan 10 01:04:51 PM PST 24 Jan 10 01:06:32 PM PST 24 1142282385 ps
T398 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2749800278 Jan 10 01:04:54 PM PST 24 Jan 10 01:10:30 PM PST 24 9801420207 ps
T399 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1243411918 Jan 10 01:04:07 PM PST 24 Jan 10 01:05:34 PM PST 24 430383622 ps
T400 /workspace/coverage/default/38.rom_ctrl_alert_test.4277019026 Jan 10 01:04:51 PM PST 24 Jan 10 01:06:28 PM PST 24 593519618 ps
T401 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1036778095 Jan 10 01:04:09 PM PST 24 Jan 10 01:06:03 PM PST 24 3026128825 ps
T402 /workspace/coverage/default/0.rom_ctrl_alert_test.3620343672 Jan 10 01:03:58 PM PST 24 Jan 10 01:05:32 PM PST 24 6032026380 ps
T403 /workspace/coverage/default/9.rom_ctrl_alert_test.4247505989 Jan 10 01:04:47 PM PST 24 Jan 10 01:06:38 PM PST 24 4739139775 ps
T404 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.397882716 Jan 10 01:04:08 PM PST 24 Jan 10 01:06:39 PM PST 24 1686606784 ps
T405 /workspace/coverage/default/17.rom_ctrl_stress_all.44891194 Jan 10 01:03:57 PM PST 24 Jan 10 01:05:43 PM PST 24 1975050162 ps
T406 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2118412644 Jan 10 01:04:13 PM PST 24 Jan 10 01:33:13 PM PST 24 27497660846 ps
T407 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1280460367 Jan 10 01:04:33 PM PST 24 Jan 10 01:33:08 PM PST 24 26836626418 ps
T408 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3566212618 Jan 10 01:04:06 PM PST 24 Jan 10 01:05:36 PM PST 24 897208033 ps
T409 /workspace/coverage/default/35.rom_ctrl_smoke.2707202705 Jan 10 01:04:47 PM PST 24 Jan 10 01:06:36 PM PST 24 8957051381 ps
T410 /workspace/coverage/default/41.rom_ctrl_alert_test.1010750298 Jan 10 01:04:55 PM PST 24 Jan 10 01:06:32 PM PST 24 1519161555 ps
T411 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.346750988 Jan 10 01:04:06 PM PST 24 Jan 10 01:05:44 PM PST 24 703783534 ps
T412 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3649418744 Jan 10 01:03:57 PM PST 24 Jan 10 01:05:30 PM PST 24 1471739941 ps
T413 /workspace/coverage/default/14.rom_ctrl_smoke.3022696375 Jan 10 01:04:10 PM PST 24 Jan 10 01:06:01 PM PST 24 4451285393 ps
T414 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1303534279 Jan 10 01:05:03 PM PST 24 Jan 10 01:08:07 PM PST 24 1452098671 ps
T415 /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2573238662 Jan 10 01:04:42 PM PST 24 Jan 10 01:06:21 PM PST 24 2735873423 ps
T416 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3677273223 Jan 10 01:04:41 PM PST 24 Jan 10 02:00:19 PM PST 24 107473869328 ps
T417 /workspace/coverage/default/23.rom_ctrl_smoke.2265472968 Jan 10 01:04:04 PM PST 24 Jan 10 01:06:01 PM PST 24 3429114914 ps
T418 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3728686227 Jan 10 01:04:57 PM PST 24 Jan 10 01:06:30 PM PST 24 826774890 ps
T419 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1819625237 Jan 10 12:27:18 PM PST 24 Jan 10 12:27:40 PM PST 24 5285537875 ps
T420 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.67282286 Jan 10 12:27:50 PM PST 24 Jan 10 12:28:15 PM PST 24 1068329391 ps
T421 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2099170428 Jan 10 12:28:37 PM PST 24 Jan 10 12:31:56 PM PST 24 28431741721 ps
T422 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.559346112 Jan 10 12:26:38 PM PST 24 Jan 10 12:26:48 PM PST 24 520719640 ps
T91 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1046791907 Jan 10 12:27:50 PM PST 24 Jan 10 12:31:19 PM PST 24 43258117055 ps
T115 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1102354768 Jan 10 12:28:37 PM PST 24 Jan 10 12:29:36 PM PST 24 1327699740 ps
T423 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2966040258 Jan 10 12:23:08 PM PST 24 Jan 10 12:23:24 PM PST 24 3025382850 ps
T424 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2115882823 Jan 10 12:28:38 PM PST 24 Jan 10 12:28:57 PM PST 24 2381199137 ps
T425 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2792870612 Jan 10 12:27:38 PM PST 24 Jan 10 12:28:02 PM PST 24 1976329057 ps
T426 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1435049802 Jan 10 12:27:49 PM PST 24 Jan 10 12:28:17 PM PST 24 1422226562 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.31404086 Jan 10 12:28:09 PM PST 24 Jan 10 12:28:28 PM PST 24 172068471 ps
T428 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3581624027 Jan 10 12:31:57 PM PST 24 Jan 10 12:32:54 PM PST 24 1421429497 ps
T429 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4142717792 Jan 10 12:27:02 PM PST 24 Jan 10 12:27:22 PM PST 24 3558606885 ps
T430 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721180114 Jan 10 12:29:05 PM PST 24 Jan 10 12:31:43 PM PST 24 32476668560 ps
T431 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1699981519 Jan 10 12:22:09 PM PST 24 Jan 10 12:22:19 PM PST 24 811578564 ps
T432 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1178587653 Jan 10 12:26:38 PM PST 24 Jan 10 12:26:54 PM PST 24 1054280969 ps
T433 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1667310622 Jan 10 12:28:16 PM PST 24 Jan 10 12:28:43 PM PST 24 1099688519 ps
T434 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.278312472 Jan 10 12:23:56 PM PST 24 Jan 10 12:24:12 PM PST 24 8161278543 ps
T435 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4271562692 Jan 10 12:27:51 PM PST 24 Jan 10 12:28:13 PM PST 24 693311632 ps
T436 /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1051173710 Jan 10 12:31:16 PM PST 24 Jan 10 12:32:51 PM PST 24 1000480882 ps
T437 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3198907819 Jan 10 12:28:11 PM PST 24 Jan 10 12:29:44 PM PST 24 2467729740 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3399814249 Jan 10 12:30:00 PM PST 24 Jan 10 12:34:01 PM PST 24 55551820953 ps
T439 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2362234997 Jan 10 12:22:18 PM PST 24 Jan 10 12:23:46 PM PST 24 2444675241 ps
T440 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3547549902 Jan 10 12:27:07 PM PST 24 Jan 10 12:27:19 PM PST 24 326581292 ps
T441 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3436536623 Jan 10 12:23:03 PM PST 24 Jan 10 12:23:21 PM PST 24 2050610650 ps
T442 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.45235773 Jan 10 12:24:29 PM PST 24 Jan 10 12:25:54 PM PST 24 5491360476 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2664082554 Jan 10 12:30:01 PM PST 24 Jan 10 12:30:51 PM PST 24 552515825 ps
T444 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3613124386 Jan 10 12:30:01 PM PST 24 Jan 10 12:30:52 PM PST 24 4284890271 ps
T92 /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.35263135 Jan 10 12:28:03 PM PST 24 Jan 10 12:31:02 PM PST 24 18211805671 ps
T445 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1248851459 Jan 10 12:23:00 PM PST 24 Jan 10 12:23:07 PM PST 24 1033012017 ps
T116 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1919870713 Jan 10 12:24:14 PM PST 24 Jan 10 12:25:04 PM PST 24 27264425912 ps
T446 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2596561918 Jan 10 12:29:10 PM PST 24 Jan 10 12:29:45 PM PST 24 6857290248 ps
T118 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1155181057 Jan 10 12:22:02 PM PST 24 Jan 10 12:22:44 PM PST 24 701290419 ps
T447 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2318673150 Jan 10 12:26:07 PM PST 24 Jan 10 12:26:16 PM PST 24 333752550 ps
T93 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2215560286 Jan 10 12:26:26 PM PST 24 Jan 10 12:27:20 PM PST 24 1028240830 ps
T448 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2443210581 Jan 10 12:26:38 PM PST 24 Jan 10 12:26:57 PM PST 24 7997543434 ps
T449 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2552027508 Jan 10 12:29:08 PM PST 24 Jan 10 12:30:15 PM PST 24 1430437504 ps
T450 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2031906755 Jan 10 12:22:03 PM PST 24 Jan 10 12:22:11 PM PST 24 854571678 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1103827251 Jan 10 12:26:50 PM PST 24 Jan 10 12:27:02 PM PST 24 1207009613 ps
T452 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.439013383 Jan 10 12:27:52 PM PST 24 Jan 10 12:28:18 PM PST 24 3293507357 ps
T453 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2772652469 Jan 10 12:26:52 PM PST 24 Jan 10 12:27:03 PM PST 24 371348053 ps
T94 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1686927702 Jan 10 12:27:51 PM PST 24 Jan 10 12:28:16 PM PST 24 2042161969 ps
T454 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3114178106 Jan 10 12:23:14 PM PST 24 Jan 10 12:23:22 PM PST 24 86186931 ps
T455 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3963375376 Jan 10 12:26:38 PM PST 24 Jan 10 12:28:02 PM PST 24 8152356531 ps
T95 /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1680479780 Jan 10 12:24:44 PM PST 24 Jan 10 12:30:17 PM PST 24 152083643683 ps
T456 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3809334918 Jan 10 12:25:21 PM PST 24 Jan 10 12:27:08 PM PST 24 7489337535 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.907236429 Jan 10 12:26:26 PM PST 24 Jan 10 12:26:44 PM PST 24 4129418093 ps
T458 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.165547379 Jan 10 12:28:38 PM PST 24 Jan 10 12:28:59 PM PST 24 500892519 ps
T459 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1826953984 Jan 10 12:27:49 PM PST 24 Jan 10 12:28:17 PM PST 24 3195617360 ps
T460 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2395599802 Jan 10 12:32:04 PM PST 24 Jan 10 12:33:03 PM PST 24 6282134217 ps
T461 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.604566547 Jan 10 12:26:18 PM PST 24 Jan 10 12:26:36 PM PST 24 8126135822 ps
T462 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3253671182 Jan 10 12:22:06 PM PST 24 Jan 10 12:23:27 PM PST 24 5679560830 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1002767014 Jan 10 12:23:29 PM PST 24 Jan 10 12:23:40 PM PST 24 3939551864 ps
T464 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.630084757 Jan 10 12:26:36 PM PST 24 Jan 10 12:26:52 PM PST 24 1411765066 ps
T465 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2912949537 Jan 10 12:29:17 PM PST 24 Jan 10 12:29:50 PM PST 24 340997395 ps
T466 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3713243601 Jan 10 12:30:01 PM PST 24 Jan 10 12:30:49 PM PST 24 104780025 ps
T100 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3425723775 Jan 10 12:23:11 PM PST 24 Jan 10 12:24:58 PM PST 24 7750645264 ps
T467 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1509870220 Jan 10 12:28:11 PM PST 24 Jan 10 12:28:35 PM PST 24 3765749696 ps
T468 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1829425569 Jan 10 12:22:56 PM PST 24 Jan 10 12:23:09 PM PST 24 1266523659 ps
T469 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2929302236 Jan 10 12:27:03 PM PST 24 Jan 10 12:27:26 PM PST 24 6802310737 ps
T99 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2402335624 Jan 10 12:26:19 PM PST 24 Jan 10 12:29:38 PM PST 24 12433773866 ps
T470 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2713611409 Jan 10 12:31:47 PM PST 24 Jan 10 12:32:49 PM PST 24 1713395078 ps
T471 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2106942873 Jan 10 12:22:01 PM PST 24 Jan 10 12:22:14 PM PST 24 468270880 ps
T472 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.868400841 Jan 10 12:22:14 PM PST 24 Jan 10 12:22:21 PM PST 24 689712549 ps
T473 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.118933253 Jan 10 12:21:58 PM PST 24 Jan 10 12:22:03 PM PST 24 95586382 ps
T474 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.73632407 Jan 10 12:26:38 PM PST 24 Jan 10 12:26:50 PM PST 24 236285633 ps
T475 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3423274791 Jan 10 12:26:39 PM PST 24 Jan 10 12:26:51 PM PST 24 2852156358 ps
T476 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1261522705 Jan 10 12:31:49 PM PST 24 Jan 10 12:32:51 PM PST 24 3384961528 ps

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3246134221
Short name T20
Test name
Test status
Simulation time 1540058024 ps
CPU time 48.14 seconds
Started Jan 10 12:24:00 PM PST 24
Finished Jan 10 12:24:54 PM PST 24
Peak memory 212620 kb
Host smart-69c467be-36be-4d15-906c-7751fa4eb22b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246134221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3246134221
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.2021547190
Short name T3
Test name
Test status
Simulation time 32394729539 ps
CPU time 7101.21 seconds
Started Jan 10 01:04:56 PM PST 24
Finished Jan 10 03:04:42 PM PST 24
Peak memory 235456 kb
Host smart-bd1ac432-6574-4a40-a15a-09951fc7825d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021547190 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.2021547190
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2933399806
Short name T56
Test name
Test status
Simulation time 266301539 ps
CPU time 8.14 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 213384 kb
Host smart-15f7f39f-c455-4947-904a-bc893727198c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933399806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2933399806
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.1899686623
Short name T35
Test name
Test status
Simulation time 2330034927 ps
CPU time 69.56 seconds
Started Jan 10 12:22:41 PM PST 24
Finished Jan 10 12:23:51 PM PST 24
Peak memory 211468 kb
Host smart-4d8d0417-34bd-4cf3-9b5e-723aefdae942
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899686623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.1899686623
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3352149831
Short name T8
Test name
Test status
Simulation time 93326096465 ps
CPU time 455.76 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:13:12 PM PST 24
Peak memory 227324 kb
Host smart-d79f5f8c-dd06-4291-838c-dcdea537f540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352149831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.3352149831
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.23381105
Short name T27
Test name
Test status
Simulation time 5915868444 ps
CPU time 14.95 seconds
Started Jan 10 12:28:09 PM PST 24
Finished Jan 10 12:28:39 PM PST 24
Peak memory 218964 kb
Host smart-005dc322-b394-4c77-9f43-89b72b0eaf0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23381105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.23381105
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.701137961
Short name T25
Test name
Test status
Simulation time 20427746792 ps
CPU time 22.68 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:24 PM PST 24
Peak memory 213928 kb
Host smart-28889a47-8606-482b-8820-300cb84554f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701137961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.rom_ctrl_stress_all.701137961
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.10346832
Short name T33
Test name
Test status
Simulation time 4344812149 ps
CPU time 83.76 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:28:07 PM PST 24
Peak memory 211464 kb
Host smart-5ab7915b-db30-4c32-b61e-f00c430e7c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10346832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_int
g_err.10346832
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1699981519
Short name T431
Test name
Test status
Simulation time 811578564 ps
CPU time 9.18 seconds
Started Jan 10 12:22:09 PM PST 24
Finished Jan 10 12:22:19 PM PST 24
Peak memory 211144 kb
Host smart-1a78ae0c-b7a7-4637-bc82-1364bc0d455d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699981519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1699981519
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.412943056
Short name T36
Test name
Test status
Simulation time 1785077207 ps
CPU time 66.33 seconds
Started Jan 10 01:03:56 PM PST 24
Finished Jan 10 01:06:20 PM PST 24
Peak memory 236376 kb
Host smart-cd135575-ddf2-45c4-a1c0-5238f3902e44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412943056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.412943056
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3971668675
Short name T114
Test name
Test status
Simulation time 2973575641 ps
CPU time 77.39 seconds
Started Jan 10 12:25:16 PM PST 24
Finished Jan 10 12:26:34 PM PST 24
Peak memory 211572 kb
Host smart-ba9fc8bd-397c-4185-bffa-85408725dac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971668675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3971668675
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.34190500
Short name T110
Test name
Test status
Simulation time 268804465021 ps
CPU time 2400.29 seconds
Started Jan 10 01:05:03 PM PST 24
Finished Jan 10 01:46:30 PM PST 24
Peak memory 242700 kb
Host smart-1d0af8de-dcc7-4ca7-8ecb-203d44ea3431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190500 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.34190500
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1776122998
Short name T16
Test name
Test status
Simulation time 134254124391 ps
CPU time 312.75 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:10:44 PM PST 24
Peak memory 237412 kb
Host smart-a6e638d6-bb1c-4ab9-b3e8-e3d021f9d9b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776122998 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1776122998
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.2094483825
Short name T24
Test name
Test status
Simulation time 37295826386 ps
CPU time 1691.12 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:34:41 PM PST 24
Peak memory 235548 kb
Host smart-d1e7297d-5f43-4be3-ad5d-4d5ebaf15196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094483825 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.2094483825
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3556797643
Short name T113
Test name
Test status
Simulation time 1225904848 ps
CPU time 78.36 seconds
Started Jan 10 12:27:46 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 211448 kb
Host smart-35fa41fe-1e97-4a99-aaec-bc9636e639e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556797643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.3556797643
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.831277605
Short name T18
Test name
Test status
Simulation time 18901359560 ps
CPU time 32.44 seconds
Started Jan 10 01:04:12 PM PST 24
Finished Jan 10 01:06:17 PM PST 24
Peak memory 211388 kb
Host smart-d3ae7df7-1e1d-434d-9cf7-8ea58649962b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831277605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.831277605
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2798118025
Short name T256
Test name
Test status
Simulation time 616501213 ps
CPU time 10.09 seconds
Started Jan 10 01:04:15 PM PST 24
Finished Jan 10 01:05:48 PM PST 24
Peak memory 211072 kb
Host smart-9bcfa787-a0a1-4dd2-8ca2-35b6947b0df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798118025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2798118025
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4008937627
Short name T86
Test name
Test status
Simulation time 3414871473 ps
CPU time 9.71 seconds
Started Jan 10 12:24:15 PM PST 24
Finished Jan 10 12:24:26 PM PST 24
Peak memory 211152 kb
Host smart-1a2084d3-ba3d-4c4a-a84b-0de4a4b27d61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008937627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4008937627
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.1030067684
Short name T39
Test name
Test status
Simulation time 334519667 ps
CPU time 4.42 seconds
Started Jan 10 01:04:17 PM PST 24
Finished Jan 10 01:05:42 PM PST 24
Peak memory 210956 kb
Host smart-a898493f-0468-4248-bf9c-c91d47417340
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030067684 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.1030067684
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.773347046
Short name T63
Test name
Test status
Simulation time 1332278672 ps
CPU time 14.72 seconds
Started Jan 10 12:22:04 PM PST 24
Finished Jan 10 12:22:20 PM PST 24
Peak memory 219256 kb
Host smart-ff1e10ee-c173-477f-8925-7a75d1b40630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773347046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.773347046
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.1946617587
Short name T101
Test name
Test status
Simulation time 6083218635 ps
CPU time 15.03 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:06:49 PM PST 24
Peak memory 211004 kb
Host smart-bbd72d55-0157-4955-8326-5a3419223dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1946617587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.1946617587
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.118933253
Short name T473
Test name
Test status
Simulation time 95586382 ps
CPU time 4.45 seconds
Started Jan 10 12:21:58 PM PST 24
Finished Jan 10 12:22:03 PM PST 24
Peak memory 210740 kb
Host smart-290fe599-192b-4547-a8eb-63ad851ed676
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118933253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alias
ing.118933253
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1447064319
Short name T140
Test name
Test status
Simulation time 1455404779 ps
CPU time 16.42 seconds
Started Jan 10 12:27:13 PM PST 24
Finished Jan 10 12:27:34 PM PST 24
Peak memory 211164 kb
Host smart-d46a8eb8-a9cb-4a54-abf3-4ce80fad3028
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447064319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.1447064319
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1104307219
Short name T121
Test name
Test status
Simulation time 2097529845 ps
CPU time 10.58 seconds
Started Jan 10 12:21:55 PM PST 24
Finished Jan 10 12:22:07 PM PST 24
Peak memory 213248 kb
Host smart-21d60290-27ec-4f7d-9fc5-702fdd75145b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104307219 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1104307219
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.361339392
Short name T78
Test name
Test status
Simulation time 7919562443 ps
CPU time 12.92 seconds
Started Jan 10 12:25:57 PM PST 24
Finished Jan 10 12:26:12 PM PST 24
Peak memory 211468 kb
Host smart-ce0a4f24-ece5-448c-aece-fd6343677473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361339392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.361339392
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1819625237
Short name T419
Test name
Test status
Simulation time 5285537875 ps
CPU time 16.45 seconds
Started Jan 10 12:27:18 PM PST 24
Finished Jan 10 12:27:40 PM PST 24
Peak memory 211156 kb
Host smart-125c29b3-a2db-4c15-91f3-e8d9d127dc13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819625237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1819625237
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1330626745
Short name T130
Test name
Test status
Simulation time 5148220998 ps
CPU time 11.83 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:25 PM PST 24
Peak memory 211164 kb
Host smart-d8ad5778-85f1-46a3-8c66-2df27e9f5821
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330626745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1330626745
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.671047386
Short name T42
Test name
Test status
Simulation time 132934890347 ps
CPU time 227.19 seconds
Started Jan 10 12:28:48 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 211160 kb
Host smart-d6cb31d7-851f-40e6-ab5c-429453b3e6de
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671047386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pas
sthru_mem_tl_intg_err.671047386
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2596561918
Short name T446
Test name
Test status
Simulation time 6857290248 ps
CPU time 13.09 seconds
Started Jan 10 12:29:10 PM PST 24
Finished Jan 10 12:29:45 PM PST 24
Peak memory 211144 kb
Host smart-274a2d36-0a21-4feb-924e-871864f28ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596561918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2596561918
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1919870713
Short name T116
Test name
Test status
Simulation time 27264425912 ps
CPU time 48.56 seconds
Started Jan 10 12:24:14 PM PST 24
Finished Jan 10 12:25:04 PM PST 24
Peak memory 212556 kb
Host smart-db85325a-78a5-4be5-9625-2bac64b91a50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919870713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1919870713
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3547549902
Short name T440
Test name
Test status
Simulation time 326581292 ps
CPU time 5.89 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:19 PM PST 24
Peak memory 211108 kb
Host smart-23208059-ddfd-4958-a9d7-71099f0def09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547549902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3547549902
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.3287549532
Short name T98
Test name
Test status
Simulation time 1323769694 ps
CPU time 9.98 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:23 PM PST 24
Peak memory 211108 kb
Host smart-a603f699-50c2-4d37-b50a-9bb47ce6854d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287549532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.3287549532
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2238084462
Short name T120
Test name
Test status
Simulation time 16848032566 ps
CPU time 14.26 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:40 PM PST 24
Peak memory 215744 kb
Host smart-7711bbc6-e653-4384-a9f0-c9a993d9cf14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238084462 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2238084462
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1907643231
Short name T31
Test name
Test status
Simulation time 1817703412 ps
CPU time 15.37 seconds
Started Jan 10 12:25:20 PM PST 24
Finished Jan 10 12:25:36 PM PST 24
Peak memory 211124 kb
Host smart-84dc6c5b-0daa-4d23-989d-1cffc948d156
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907643231 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1907643231
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1606681077
Short name T32
Test name
Test status
Simulation time 1846414048 ps
CPU time 9.78 seconds
Started Jan 10 12:22:01 PM PST 24
Finished Jan 10 12:22:12 PM PST 24
Peak memory 210884 kb
Host smart-af7dcd4d-57e9-4ef1-98ef-53a6ad942d0e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606681077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1606681077
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.2743904399
Short name T127
Test name
Test status
Simulation time 89055395 ps
CPU time 4.3 seconds
Started Jan 10 12:22:08 PM PST 24
Finished Jan 10 12:22:14 PM PST 24
Peak memory 211124 kb
Host smart-278e5e29-03c6-4ef6-8d75-4dbc7419c731
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743904399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.2743904399
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3647527068
Short name T73
Test name
Test status
Simulation time 79579989689 ps
CPU time 206.6 seconds
Started Jan 10 12:22:07 PM PST 24
Finished Jan 10 12:25:35 PM PST 24
Peak memory 211140 kb
Host smart-afa00c8f-b86a-4685-a779-edfb865460ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647527068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3647527068
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.300256529
Short name T132
Test name
Test status
Simulation time 87219015 ps
CPU time 4.44 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:18 PM PST 24
Peak memory 211108 kb
Host smart-015f149a-43da-49bc-a5f4-3da456ce53ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300256529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.300256529
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2106942873
Short name T471
Test name
Test status
Simulation time 468270880 ps
CPU time 11.17 seconds
Started Jan 10 12:22:01 PM PST 24
Finished Jan 10 12:22:14 PM PST 24
Peak memory 219260 kb
Host smart-d33ff736-aac3-427c-9e49-88bdd04c20b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106942873 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2106942873
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3715156094
Short name T76
Test name
Test status
Simulation time 1715019386 ps
CPU time 45.78 seconds
Started Jan 10 12:27:07 PM PST 24
Finished Jan 10 12:27:59 PM PST 24
Peak memory 211964 kb
Host smart-354b472d-dbeb-4679-ae4a-e2e0776967f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715156094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3715156094
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.604566547
Short name T461
Test name
Test status
Simulation time 8126135822 ps
CPU time 16.3 seconds
Started Jan 10 12:26:18 PM PST 24
Finished Jan 10 12:26:36 PM PST 24
Peak memory 213520 kb
Host smart-1d615e4e-3227-4351-b897-76c0a824e212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604566547 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.604566547
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.2043222634
Short name T67
Test name
Test status
Simulation time 8658448474 ps
CPU time 16.32 seconds
Started Jan 10 12:24:15 PM PST 24
Finished Jan 10 12:24:32 PM PST 24
Peak memory 211140 kb
Host smart-238dc51c-d569-4f9e-b68c-9c6055d4078f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043222634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.2043222634
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1331850737
Short name T72
Test name
Test status
Simulation time 115175861223 ps
CPU time 266.99 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 211152 kb
Host smart-3271e1a7-4150-448a-98c9-906510012222
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331850737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.1331850737
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3162397323
Short name T81
Test name
Test status
Simulation time 5437364865 ps
CPU time 12.16 seconds
Started Jan 10 12:27:53 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 211156 kb
Host smart-7f409f39-a263-49b1-aef9-9a22cf69c931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162397323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3162397323
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.165547379
Short name T458
Test name
Test status
Simulation time 500892519 ps
CPU time 8.81 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:59 PM PST 24
Peak memory 218960 kb
Host smart-e7b439ef-0329-4ef1-8ea0-8f9831fe10a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165547379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.165547379
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2552027508
Short name T449
Test name
Test status
Simulation time 1430437504 ps
CPU time 45.83 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:30:15 PM PST 24
Peak memory 211848 kb
Host smart-d5b87800-cd05-45dd-93b5-611e646cf760
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552027508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2552027508
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.2664082554
Short name T443
Test name
Test status
Simulation time 552515825 ps
CPU time 8.17 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:51 PM PST 24
Peak memory 214228 kb
Host smart-538875e4-c83a-40a5-a798-f443ada50246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664082554 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.2664082554
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.1626574961
Short name T65
Test name
Test status
Simulation time 3302898279 ps
CPU time 5.21 seconds
Started Jan 10 12:29:16 PM PST 24
Finished Jan 10 12:29:46 PM PST 24
Peak memory 210928 kb
Host smart-d2ff034e-53f7-49cc-8cdb-6021ec564598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626574961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.1626574961
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3399814249
Short name T438
Test name
Test status
Simulation time 55551820953 ps
CPU time 198.48 seconds
Started Jan 10 12:30:00 PM PST 24
Finished Jan 10 12:34:01 PM PST 24
Peak memory 210316 kb
Host smart-8c212f29-e5b8-4210-8952-efeb43c85921
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399814249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3399814249
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2792870612
Short name T425
Test name
Test status
Simulation time 1976329057 ps
CPU time 14.7 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:28:02 PM PST 24
Peak memory 211092 kb
Host smart-6147e9a4-b6e3-4ad2-8515-ae3584c4ede9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792870612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2792870612
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1722611526
Short name T122
Test name
Test status
Simulation time 4083619809 ps
CPU time 15.11 seconds
Started Jan 10 12:26:05 PM PST 24
Finished Jan 10 12:26:27 PM PST 24
Peak memory 219412 kb
Host smart-a72cedb7-abb5-4ec6-b572-db5bb37b95ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722611526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1722611526
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3171707132
Short name T117
Test name
Test status
Simulation time 1379041454 ps
CPU time 47.28 seconds
Started Jan 10 12:26:16 PM PST 24
Finished Jan 10 12:27:06 PM PST 24
Peak memory 212084 kb
Host smart-210c2459-d70d-4043-859c-fbe833016cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171707132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.3171707132
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3114178106
Short name T454
Test name
Test status
Simulation time 86186931 ps
CPU time 4.51 seconds
Started Jan 10 12:23:14 PM PST 24
Finished Jan 10 12:23:22 PM PST 24
Peak memory 211160 kb
Host smart-798b77e3-fe2f-44b0-bf82-6fc002eb662b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114178106 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3114178106
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.667164355
Short name T125
Test name
Test status
Simulation time 2121679635 ps
CPU time 16.65 seconds
Started Jan 10 12:24:44 PM PST 24
Finished Jan 10 12:25:02 PM PST 24
Peak memory 211124 kb
Host smart-aa8a3204-003e-4191-b479-a31926e16168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667164355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.667164355
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.593209806
Short name T82
Test name
Test status
Simulation time 5130371018 ps
CPU time 13.03 seconds
Started Jan 10 12:23:53 PM PST 24
Finished Jan 10 12:24:07 PM PST 24
Peak memory 211160 kb
Host smart-045eefae-064b-41c9-ac90-184725b72951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593209806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_c
trl_same_csr_outstanding.593209806
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2912949537
Short name T465
Test name
Test status
Simulation time 340997395 ps
CPU time 7.87 seconds
Started Jan 10 12:29:17 PM PST 24
Finished Jan 10 12:29:50 PM PST 24
Peak memory 219068 kb
Host smart-12eed4b8-c0c0-44b8-ab09-8dd668df98b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912949537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2912949537
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.515723511
Short name T111
Test name
Test status
Simulation time 1114288271 ps
CPU time 78.44 seconds
Started Jan 10 12:30:23 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 211192 kb
Host smart-82f34d1f-7211-4bc5-9686-d634910d3c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515723511 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_in
tg_err.515723511
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.3696025451
Short name T139
Test name
Test status
Simulation time 3704516329 ps
CPU time 10.98 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 213696 kb
Host smart-042f625f-a055-4830-a0bb-4eb2f1ca91ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696025451 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.3696025451
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.1549835399
Short name T131
Test name
Test status
Simulation time 578734326 ps
CPU time 7.68 seconds
Started Jan 10 12:22:08 PM PST 24
Finished Jan 10 12:22:17 PM PST 24
Peak memory 211076 kb
Host smart-810c21ec-7c1f-4af6-80a5-a4ae44856ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549835399 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.1549835399
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.1719622528
Short name T43
Test name
Test status
Simulation time 7447303362 ps
CPU time 52.38 seconds
Started Jan 10 12:23:59 PM PST 24
Finished Jan 10 12:24:58 PM PST 24
Peak memory 211484 kb
Host smart-78dabe59-0d1e-4db1-ba57-bd9922259c22
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719622528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.1719622528
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.1951570501
Short name T136
Test name
Test status
Simulation time 1095257186 ps
CPU time 11.04 seconds
Started Jan 10 12:27:36 PM PST 24
Finished Jan 10 12:27:54 PM PST 24
Peak memory 211428 kb
Host smart-48f95e1e-4030-454e-a59d-44430de16ce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951570501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.1951570501
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2200682804
Short name T123
Test name
Test status
Simulation time 3690436346 ps
CPU time 12.22 seconds
Started Jan 10 12:27:47 PM PST 24
Finished Jan 10 12:28:12 PM PST 24
Peak memory 219388 kb
Host smart-18bc101d-4f9d-48c0-9aea-e0727ed28827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200682804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.2200682804
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1509870220
Short name T467
Test name
Test status
Simulation time 3765749696 ps
CPU time 9.55 seconds
Started Jan 10 12:28:11 PM PST 24
Finished Jan 10 12:28:35 PM PST 24
Peak memory 211772 kb
Host smart-fcc18606-cdff-4333-a527-a012eb1ca917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509870220 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1509870220
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1686927702
Short name T94
Test name
Test status
Simulation time 2042161969 ps
CPU time 9.45 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:16 PM PST 24
Peak memory 211076 kb
Host smart-ada2cdd7-e182-49d0-bd1f-dcdb881a04a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686927702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1686927702
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.518124780
Short name T29
Test name
Test status
Simulation time 67332338718 ps
CPU time 211.47 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:25:39 PM PST 24
Peak memory 210096 kb
Host smart-cc37fb4a-a401-4117-a313-a5562fc9be12
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518124780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa
ssthru_mem_tl_intg_err.518124780
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3584789640
Short name T138
Test name
Test status
Simulation time 108467970 ps
CPU time 6.84 seconds
Started Jan 10 12:23:54 PM PST 24
Finished Jan 10 12:24:01 PM PST 24
Peak memory 211100 kb
Host smart-13fc9a89-2c7a-4329-9f28-e6eac8961d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584789640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3584789640
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.4271562692
Short name T435
Test name
Test status
Simulation time 693311632 ps
CPU time 6.52 seconds
Started Jan 10 12:27:51 PM PST 24
Finished Jan 10 12:28:13 PM PST 24
Peak memory 213812 kb
Host smart-403b5c03-4081-420f-86fd-074825c06857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271562692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.4271562692
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.12698585
Short name T34
Test name
Test status
Simulation time 1502070557 ps
CPU time 79.39 seconds
Started Jan 10 12:27:38 PM PST 24
Finished Jan 10 12:29:07 PM PST 24
Peak memory 211344 kb
Host smart-cb4abc55-1d2f-4d30-b44c-1d027b3ade60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_int
g_err.12698585
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.2237890116
Short name T57
Test name
Test status
Simulation time 604473393 ps
CPU time 4.85 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:26:48 PM PST 24
Peak memory 214376 kb
Host smart-64afc127-8e99-4af7-a0dc-67bbc2475571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237890116 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.2237890116
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.1435049802
Short name T426
Test name
Test status
Simulation time 1422226562 ps
CPU time 13.31 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:17 PM PST 24
Peak memory 210328 kb
Host smart-11e7eda1-ca57-415e-89f8-b9a539aa5ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435049802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.1435049802
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.3425723775
Short name T100
Test name
Test status
Simulation time 7750645264 ps
CPU time 100 seconds
Started Jan 10 12:23:11 PM PST 24
Finished Jan 10 12:24:58 PM PST 24
Peak memory 211180 kb
Host smart-7a122383-9e9d-4500-8190-e109a1a7974d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425723775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.3425723775
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3050124574
Short name T66
Test name
Test status
Simulation time 594051193 ps
CPU time 4.68 seconds
Started Jan 10 12:28:30 PM PST 24
Finished Jan 10 12:28:46 PM PST 24
Peak memory 209804 kb
Host smart-c64ae071-ef25-40be-94c9-4df47f7e3fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050124574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3050124574
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.439013383
Short name T452
Test name
Test status
Simulation time 3293507357 ps
CPU time 11.68 seconds
Started Jan 10 12:27:52 PM PST 24
Finished Jan 10 12:28:18 PM PST 24
Peak memory 219376 kb
Host smart-43d56343-69d0-43e7-b16e-b19a18c481ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439013383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.439013383
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1826953984
Short name T459
Test name
Test status
Simulation time 3195617360 ps
CPU time 12.98 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:28:17 PM PST 24
Peak memory 215092 kb
Host smart-f86ebe3d-84de-4f67-9b7b-51f830508fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826953984 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1826953984
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.67282286
Short name T420
Test name
Test status
Simulation time 1068329391 ps
CPU time 10.36 seconds
Started Jan 10 12:27:50 PM PST 24
Finished Jan 10 12:28:15 PM PST 24
Peak memory 210716 kb
Host smart-d82af375-aa24-4ab6-8b05-87cbbeceba60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67282286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.67282286
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2721180114
Short name T430
Test name
Test status
Simulation time 32476668560 ps
CPU time 138.12 seconds
Started Jan 10 12:29:05 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 210972 kb
Host smart-f82e3aee-0336-4f71-9dfc-1b4de053890f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721180114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2721180114
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2548439647
Short name T133
Test name
Test status
Simulation time 369824686 ps
CPU time 7.85 seconds
Started Jan 10 12:25:55 PM PST 24
Finished Jan 10 12:26:04 PM PST 24
Peak memory 211236 kb
Host smart-b6bdae1b-9ac7-4d9f-ad83-8406642b5b88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548439647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.2548439647
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1906897901
Short name T109
Test name
Test status
Simulation time 437238465 ps
CPU time 8.53 seconds
Started Jan 10 12:28:31 PM PST 24
Finished Jan 10 12:28:50 PM PST 24
Peak memory 212584 kb
Host smart-74b6e735-0bbf-461f-9511-ecb60b22b07e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906897901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1906897901
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3963375376
Short name T455
Test name
Test status
Simulation time 8152356531 ps
CPU time 78.56 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:28:02 PM PST 24
Peak memory 211164 kb
Host smart-f22ca1cc-a605-40b1-8ca5-89a97192650f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963375376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3963375376
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.3131227727
Short name T74
Test name
Test status
Simulation time 910133086 ps
CPU time 8.03 seconds
Started Jan 10 12:22:04 PM PST 24
Finished Jan 10 12:22:13 PM PST 24
Peak memory 214340 kb
Host smart-4e79d8af-9518-44c2-9f90-a449c01b7cbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131227727 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.3131227727
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.2966040258
Short name T423
Test name
Test status
Simulation time 3025382850 ps
CPU time 7.51 seconds
Started Jan 10 12:23:08 PM PST 24
Finished Jan 10 12:23:24 PM PST 24
Peak memory 211472 kb
Host smart-8fd83f85-b6bb-42be-b1a4-b8d5a53eee42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966040258 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.2966040258
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.1046791907
Short name T91
Test name
Test status
Simulation time 43258117055 ps
CPU time 192.3 seconds
Started Jan 10 12:27:50 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 211156 kb
Host smart-a40f3995-50e2-4c26-8cd4-1c2c21f789f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046791907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.1046791907
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1829425569
Short name T468
Test name
Test status
Simulation time 1266523659 ps
CPU time 12.08 seconds
Started Jan 10 12:22:56 PM PST 24
Finished Jan 10 12:23:09 PM PST 24
Peak memory 211120 kb
Host smart-40fd2d45-abce-46f4-addb-f439fd2b3385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829425569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1829425569
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1667310622
Short name T433
Test name
Test status
Simulation time 1099688519 ps
CPU time 12.54 seconds
Started Jan 10 12:28:16 PM PST 24
Finished Jan 10 12:28:43 PM PST 24
Peak memory 219288 kb
Host smart-3c17c630-87ef-41ba-b161-f378830df8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667310622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1667310622
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.2772652469
Short name T453
Test name
Test status
Simulation time 371348053 ps
CPU time 6.72 seconds
Started Jan 10 12:26:52 PM PST 24
Finished Jan 10 12:27:03 PM PST 24
Peak memory 215460 kb
Host smart-ff1b3084-64df-461a-b558-5031a8121fb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772652469 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.2772652469
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1210588362
Short name T96
Test name
Test status
Simulation time 4624335184 ps
CPU time 11.37 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:27:07 PM PST 24
Peak memory 211132 kb
Host smart-cb62da4b-11e6-4ecd-80e6-632d69c538f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210588362 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1210588362
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3809334918
Short name T456
Test name
Test status
Simulation time 7489337535 ps
CPU time 105.39 seconds
Started Jan 10 12:25:21 PM PST 24
Finished Jan 10 12:27:08 PM PST 24
Peak memory 211180 kb
Host smart-75bbaebc-8c60-4716-8099-4f3cc6a35a41
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809334918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3809334918
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2861875341
Short name T135
Test name
Test status
Simulation time 91610791 ps
CPU time 4.31 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:27:00 PM PST 24
Peak memory 211076 kb
Host smart-bcec482f-4c88-4789-9978-25188032159c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861875341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2861875341
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.4275797142
Short name T59
Test name
Test status
Simulation time 1413999852 ps
CPU time 12.18 seconds
Started Jan 10 12:27:28 PM PST 24
Finished Jan 10 12:27:45 PM PST 24
Peak memory 219296 kb
Host smart-51feff4a-78ad-4db2-8162-21ab36ec73a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275797142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.4275797142
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2362234997
Short name T439
Test name
Test status
Simulation time 2444675241 ps
CPU time 87.92 seconds
Started Jan 10 12:22:18 PM PST 24
Finished Jan 10 12:23:46 PM PST 24
Peak memory 211384 kb
Host smart-fe6336e3-d0a4-4197-8b0f-85c408644640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362234997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2362234997
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.1103827251
Short name T451
Test name
Test status
Simulation time 1207009613 ps
CPU time 6.9 seconds
Started Jan 10 12:26:50 PM PST 24
Finished Jan 10 12:27:02 PM PST 24
Peak memory 219324 kb
Host smart-6be4751c-4b77-4c61-a6cc-8960a0afba1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103827251 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.1103827251
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2126965434
Short name T126
Test name
Test status
Simulation time 3854469533 ps
CPU time 12.93 seconds
Started Jan 10 12:22:18 PM PST 24
Finished Jan 10 12:22:31 PM PST 24
Peak memory 211164 kb
Host smart-c5abac32-5d46-4269-81db-d03e07e534eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126965434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2126965434
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1550778911
Short name T70
Test name
Test status
Simulation time 55587784161 ps
CPU time 183.32 seconds
Started Jan 10 12:26:51 PM PST 24
Finished Jan 10 12:29:59 PM PST 24
Peak memory 211136 kb
Host smart-f2962dd2-7357-47e5-95ea-afcde13e05c2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550778911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1550778911
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3581624027
Short name T428
Test name
Test status
Simulation time 1421429497 ps
CPU time 10.97 seconds
Started Jan 10 12:31:57 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 210944 kb
Host smart-c2a16c15-1b02-499e-a5a0-96cecc2b0729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581624027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3581624027
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.828355841
Short name T75
Test name
Test status
Simulation time 120970163 ps
CPU time 8.59 seconds
Started Jan 10 12:28:14 PM PST 24
Finished Jan 10 12:28:36 PM PST 24
Peak memory 219288 kb
Host smart-e4c6a46a-a054-41e6-b3c2-a52710a2b5a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828355841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.828355841
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3198907819
Short name T437
Test name
Test status
Simulation time 2467729740 ps
CPU time 78.99 seconds
Started Jan 10 12:28:11 PM PST 24
Finished Jan 10 12:29:44 PM PST 24
Peak memory 211192 kb
Host smart-61b8d2b5-4bbb-41bb-bc00-3b6c6d49b16a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198907819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.3198907819
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.1002767014
Short name T463
Test name
Test status
Simulation time 3939551864 ps
CPU time 9.95 seconds
Started Jan 10 12:23:29 PM PST 24
Finished Jan 10 12:23:40 PM PST 24
Peak memory 211156 kb
Host smart-e07c125b-c264-4117-91c4-fe408f892d9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002767014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.1002767014
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.31404086
Short name T427
Test name
Test status
Simulation time 172068471 ps
CPU time 4.33 seconds
Started Jan 10 12:28:09 PM PST 24
Finished Jan 10 12:28:28 PM PST 24
Peak memory 211092 kb
Host smart-aecfc6bb-4d36-486a-93ee-83c1dfa8c6d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31404086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_ba
sh.31404086
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2175410239
Short name T129
Test name
Test status
Simulation time 1212610890 ps
CPU time 14.9 seconds
Started Jan 10 12:23:50 PM PST 24
Finished Jan 10 12:24:06 PM PST 24
Peak memory 209972 kb
Host smart-b100e271-4770-4a5d-89d4-95c07dc213fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175410239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2175410239
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3066010718
Short name T60
Test name
Test status
Simulation time 3874202920 ps
CPU time 8.63 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:45 PM PST 24
Peak memory 212632 kb
Host smart-dbd01e01-d730-4c99-b5dd-4f364de38138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066010718 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3066010718
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2230970883
Short name T85
Test name
Test status
Simulation time 4855025303 ps
CPU time 11.43 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:22:19 PM PST 24
Peak memory 211184 kb
Host smart-d3e40abf-9454-45f2-9fb5-da97247ad91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230970883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2230970883
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2091759451
Short name T134
Test name
Test status
Simulation time 8695168900 ps
CPU time 14.05 seconds
Started Jan 10 12:29:06 PM PST 24
Finished Jan 10 12:29:42 PM PST 24
Peak memory 209700 kb
Host smart-66023893-0ef8-45ef-9b76-b27d54ecc6ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091759451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2091759451
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2318673150
Short name T447
Test name
Test status
Simulation time 333752550 ps
CPU time 4.32 seconds
Started Jan 10 12:26:07 PM PST 24
Finished Jan 10 12:26:16 PM PST 24
Peak memory 211248 kb
Host smart-bf43ddbb-b892-4716-890b-337d150aa736
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318673150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2318673150
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.35263135
Short name T92
Test name
Test status
Simulation time 18211805671 ps
CPU time 162.77 seconds
Started Jan 10 12:28:03 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 210612 kb
Host smart-0a441087-0218-46bf-a9c9-fd177377ac29
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35263135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pass
thru_mem_tl_intg_err.35263135
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.4014903252
Short name T77
Test name
Test status
Simulation time 1635763145 ps
CPU time 14.6 seconds
Started Jan 10 12:25:58 PM PST 24
Finished Jan 10 12:26:18 PM PST 24
Peak memory 211128 kb
Host smart-0b5c9c96-b2e2-4b5d-b10b-4e837711f690
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014903252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.4014903252
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.3108043351
Short name T124
Test name
Test status
Simulation time 1210065045 ps
CPU time 8.98 seconds
Started Jan 10 12:24:14 PM PST 24
Finished Jan 10 12:24:25 PM PST 24
Peak memory 219308 kb
Host smart-f200ed1a-1d60-46f0-819a-4b90489906bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108043351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.3108043351
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2822692191
Short name T61
Test name
Test status
Simulation time 517887414 ps
CPU time 80.34 seconds
Started Jan 10 12:29:08 PM PST 24
Finished Jan 10 12:30:50 PM PST 24
Peak memory 213304 kb
Host smart-e676e495-943d-45d7-8397-001f791cfe90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822692191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.2822692191
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.3990736838
Short name T97
Test name
Test status
Simulation time 7516817430 ps
CPU time 16.01 seconds
Started Jan 10 12:22:07 PM PST 24
Finished Jan 10 12:22:24 PM PST 24
Peak memory 211148 kb
Host smart-931fc7cf-2eed-4441-9fb7-3a32d6afd79e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990736838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.3990736838
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2432513980
Short name T30
Test name
Test status
Simulation time 3274861934 ps
CPU time 14.52 seconds
Started Jan 10 12:22:08 PM PST 24
Finished Jan 10 12:22:23 PM PST 24
Peak memory 211180 kb
Host smart-253dcd92-5e02-4533-b915-7546dda3ef82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432513980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2432513980
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1423169647
Short name T69
Test name
Test status
Simulation time 3232027159 ps
CPU time 17.02 seconds
Started Jan 10 12:24:02 PM PST 24
Finished Jan 10 12:24:23 PM PST 24
Peak memory 211064 kb
Host smart-c4d8bb2a-0807-4183-99c1-ab4ac29ac2e4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423169647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1423169647
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1261522705
Short name T476
Test name
Test status
Simulation time 3384961528 ps
CPU time 14.86 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 215832 kb
Host smart-5f8eb5da-ce75-45ef-b392-ccebec5c2a2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261522705 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1261522705
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1248851459
Short name T445
Test name
Test status
Simulation time 1033012017 ps
CPU time 6.02 seconds
Started Jan 10 12:23:00 PM PST 24
Finished Jan 10 12:23:07 PM PST 24
Peak memory 211096 kb
Host smart-f354f2ad-c35b-4f7d-839d-0c5faff93253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248851459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1248851459
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.559346112
Short name T422
Test name
Test status
Simulation time 520719640 ps
CPU time 4.11 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:26:48 PM PST 24
Peak memory 210804 kb
Host smart-270321cf-5ac0-4b09-9be1-e06f7dbfc71e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559346112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl
_mem_partial_access.559346112
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.868400841
Short name T472
Test name
Test status
Simulation time 689712549 ps
CPU time 6.46 seconds
Started Jan 10 12:22:14 PM PST 24
Finished Jan 10 12:22:21 PM PST 24
Peak memory 211116 kb
Host smart-bc188883-2bd6-4c0d-8154-4b35be662c6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868400841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
868400841
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1680479780
Short name T95
Test name
Test status
Simulation time 152083643683 ps
CPU time 331.18 seconds
Started Jan 10 12:24:44 PM PST 24
Finished Jan 10 12:30:17 PM PST 24
Peak memory 211184 kb
Host smart-aace6a6e-58c5-4002-9749-dc206a508806
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680479780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1680479780
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.907236429
Short name T457
Test name
Test status
Simulation time 4129418093 ps
CPU time 16.54 seconds
Started Jan 10 12:26:26 PM PST 24
Finished Jan 10 12:26:44 PM PST 24
Peak memory 209764 kb
Host smart-a297fa06-f36c-4497-b975-8d2e1ecc506a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907236429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ct
rl_same_csr_outstanding.907236429
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.2929302236
Short name T469
Test name
Test status
Simulation time 6802310737 ps
CPU time 16.79 seconds
Started Jan 10 12:27:03 PM PST 24
Finished Jan 10 12:27:26 PM PST 24
Peak memory 218972 kb
Host smart-9b35ca84-c5e0-4997-b602-ff76c0dca3bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929302236 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.2929302236
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.229040222
Short name T64
Test name
Test status
Simulation time 9794618524 ps
CPU time 48.22 seconds
Started Jan 10 12:27:50 PM PST 24
Finished Jan 10 12:28:54 PM PST 24
Peak memory 212336 kb
Host smart-6812514f-db9c-49ce-8574-a96ea0cd321c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229040222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_int
g_err.229040222
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3613124386
Short name T444
Test name
Test status
Simulation time 4284890271 ps
CPU time 9.69 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:52 PM PST 24
Peak memory 210168 kb
Host smart-2bae3450-44e6-44cd-8bed-d26b1fc828dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613124386 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3613124386
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.630084757
Short name T464
Test name
Test status
Simulation time 1411765066 ps
CPU time 12.12 seconds
Started Jan 10 12:26:36 PM PST 24
Finished Jan 10 12:26:52 PM PST 24
Peak memory 210832 kb
Host smart-98f3e004-0979-467c-a935-8aec99a7a520
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630084757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_b
ash.630084757
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.870012341
Short name T84
Test name
Test status
Simulation time 2017214589 ps
CPU time 19.57 seconds
Started Jan 10 12:22:01 PM PST 24
Finished Jan 10 12:22:22 PM PST 24
Peak memory 211036 kb
Host smart-f47b4119-4fcf-474f-ae53-18689c033db7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870012341 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_re
set.870012341
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.278312472
Short name T434
Test name
Test status
Simulation time 8161278543 ps
CPU time 14.79 seconds
Started Jan 10 12:23:56 PM PST 24
Finished Jan 10 12:24:12 PM PST 24
Peak memory 214788 kb
Host smart-4707e569-3404-435e-920e-46f9ebbe99f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278312472 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.278312472
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3436536623
Short name T441
Test name
Test status
Simulation time 2050610650 ps
CPU time 16.67 seconds
Started Jan 10 12:23:03 PM PST 24
Finished Jan 10 12:23:21 PM PST 24
Peak memory 211144 kb
Host smart-f3b4fb83-a2f1-4a02-ac6a-a082e7172fe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436536623 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3436536623
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2395599802
Short name T460
Test name
Test status
Simulation time 6282134217 ps
CPU time 12.81 seconds
Started Jan 10 12:32:04 PM PST 24
Finished Jan 10 12:33:03 PM PST 24
Peak memory 210956 kb
Host smart-0c753f87-1d31-489a-8296-92e8568485b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395599802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2395599802
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1178587653
Short name T432
Test name
Test status
Simulation time 1054280969 ps
CPU time 10.36 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:26:54 PM PST 24
Peak memory 210488 kb
Host smart-081e7dcd-b41d-460f-8c2e-7babcd469b29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178587653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1178587653
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1888511834
Short name T71
Test name
Test status
Simulation time 5546229782 ps
CPU time 92.2 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 210916 kb
Host smart-b3c488a1-0d2a-4512-93a8-d800812f7384
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888511834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.1888511834
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.474199888
Short name T68
Test name
Test status
Simulation time 9299418526 ps
CPU time 18.14 seconds
Started Jan 10 12:28:03 PM PST 24
Finished Jan 10 12:28:37 PM PST 24
Peak memory 210740 kb
Host smart-c8c01fbf-47c7-4bc2-898c-9c8041df5388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474199888 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.474199888
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1639481250
Short name T112
Test name
Test status
Simulation time 768806854 ps
CPU time 74.41 seconds
Started Jan 10 12:27:49 PM PST 24
Finished Jan 10 12:29:17 PM PST 24
Peak memory 213600 kb
Host smart-6483a726-b77c-4aad-b6e3-bfd1f7702e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639481250 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1639481250
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.73632407
Short name T474
Test name
Test status
Simulation time 236285633 ps
CPU time 6.56 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:26:50 PM PST 24
Peak memory 214456 kb
Host smart-937c4ccd-b0de-4ac3-b0d9-4f8a2e354fff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73632407 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.73632407
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.2443210581
Short name T448
Test name
Test status
Simulation time 7997543434 ps
CPU time 13.22 seconds
Started Jan 10 12:26:38 PM PST 24
Finished Jan 10 12:26:57 PM PST 24
Peak memory 210884 kb
Host smart-be772256-3288-4d01-9f1e-55990b8e4569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443210581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.2443210581
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2402335624
Short name T99
Test name
Test status
Simulation time 12433773866 ps
CPU time 197.27 seconds
Started Jan 10 12:26:19 PM PST 24
Finished Jan 10 12:29:38 PM PST 24
Peak memory 210344 kb
Host smart-e76c8d96-c3f7-4f8a-b52a-483e1d396552
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402335624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.2402335624
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3713243601
Short name T466
Test name
Test status
Simulation time 104780025 ps
CPU time 6.25 seconds
Started Jan 10 12:30:01 PM PST 24
Finished Jan 10 12:30:49 PM PST 24
Peak memory 210708 kb
Host smart-c2e0fca8-5ac8-4a11-a586-033239a138d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713243601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3713243601
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.757396528
Short name T137
Test name
Test status
Simulation time 7851150755 ps
CPU time 17.42 seconds
Started Jan 10 12:26:39 PM PST 24
Finished Jan 10 12:27:01 PM PST 24
Peak memory 219116 kb
Host smart-1a4870c3-9a35-4029-b58c-199e83868442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757396528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.757396528
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.45235773
Short name T442
Test name
Test status
Simulation time 5491360476 ps
CPU time 83.63 seconds
Started Jan 10 12:24:29 PM PST 24
Finished Jan 10 12:25:54 PM PST 24
Peak memory 212096 kb
Host smart-1b308c85-d2bb-4f79-b56a-47576e3309c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45235773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_intg
_err.45235773
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.2713611409
Short name T470
Test name
Test status
Simulation time 1713395078 ps
CPU time 13.93 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:49 PM PST 24
Peak memory 214580 kb
Host smart-e65294ea-295b-43c9-8a5c-4e34cbab1301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713611409 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.2713611409
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.3589383997
Short name T80
Test name
Test status
Simulation time 1743533186 ps
CPU time 10.32 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 210172 kb
Host smart-927f5314-34c3-4d74-a3e5-636a97b9a7e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589383997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.3589383997
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.1051173710
Short name T436
Test name
Test status
Simulation time 1000480882 ps
CPU time 49.61 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 210864 kb
Host smart-f44e1829-3d5d-4237-962a-bad1e68307f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051173710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.1051173710
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.2058120284
Short name T128
Test name
Test status
Simulation time 3540965017 ps
CPU time 15.52 seconds
Started Jan 10 12:22:18 PM PST 24
Finished Jan 10 12:22:34 PM PST 24
Peak memory 211156 kb
Host smart-5b35ccf3-a482-4541-bae8-a56fb73128b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058120284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.2058120284
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.2989930503
Short name T58
Test name
Test status
Simulation time 4360490431 ps
CPU time 13.5 seconds
Started Jan 10 12:22:53 PM PST 24
Finished Jan 10 12:23:07 PM PST 24
Peak memory 219412 kb
Host smart-88af81c3-f579-4af7-a7fe-1040d61547e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989930503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.2989930503
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.1155181057
Short name T118
Test name
Test status
Simulation time 701290419 ps
CPU time 41.01 seconds
Started Jan 10 12:22:02 PM PST 24
Finished Jan 10 12:22:44 PM PST 24
Peak memory 212688 kb
Host smart-231b83e9-5f1d-495c-b394-5f0830810af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155181057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.1155181057
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3771785310
Short name T119
Test name
Test status
Simulation time 11218013823 ps
CPU time 11.66 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:13 PM PST 24
Peak memory 214832 kb
Host smart-de6526c5-43de-4d16-8863-65ce597b706f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771785310 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3771785310
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3423274791
Short name T475
Test name
Test status
Simulation time 2852156358 ps
CPU time 6.75 seconds
Started Jan 10 12:26:39 PM PST 24
Finished Jan 10 12:26:51 PM PST 24
Peak memory 211160 kb
Host smart-224205ac-33e4-4738-8214-41e626f2ee5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423274791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3423274791
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.2215560286
Short name T93
Test name
Test status
Simulation time 1028240830 ps
CPU time 52.14 seconds
Started Jan 10 12:26:26 PM PST 24
Finished Jan 10 12:27:20 PM PST 24
Peak memory 209468 kb
Host smart-3d9657e9-90c7-428f-89b7-c8e4f7ef2720
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215560286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.2215560286
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1181848778
Short name T79
Test name
Test status
Simulation time 1073935438 ps
CPU time 10.21 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 210916 kb
Host smart-4ca0122e-0b94-44b3-8196-e11c7026f9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181848778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1181848778
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.4142717792
Short name T429
Test name
Test status
Simulation time 3558606885 ps
CPU time 13.34 seconds
Started Jan 10 12:27:02 PM PST 24
Finished Jan 10 12:27:22 PM PST 24
Peak memory 217644 kb
Host smart-29b3d106-692f-4d42-9970-d9c89fc2ed2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142717792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.4142717792
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.3253671182
Short name T462
Test name
Test status
Simulation time 5679560830 ps
CPU time 80.31 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:23:27 PM PST 24
Peak memory 211528 kb
Host smart-70fcbbcc-739b-4fa6-8256-298e0c60ce0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253671182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.3253671182
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2031906755
Short name T450
Test name
Test status
Simulation time 854571678 ps
CPU time 6.72 seconds
Started Jan 10 12:22:03 PM PST 24
Finished Jan 10 12:22:11 PM PST 24
Peak memory 219180 kb
Host smart-58f81c53-12ef-4972-abf3-f7da9ba5cdfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031906755 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2031906755
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2829051939
Short name T83
Test name
Test status
Simulation time 3311157317 ps
CPU time 13.64 seconds
Started Jan 10 12:26:37 PM PST 24
Finished Jan 10 12:26:55 PM PST 24
Peak memory 210884 kb
Host smart-1b9c36de-bd31-453f-8a86-7c7b3812ecc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829051939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2829051939
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.1649814658
Short name T28
Test name
Test status
Simulation time 1271532823 ps
CPU time 6.82 seconds
Started Jan 10 12:22:06 PM PST 24
Finished Jan 10 12:22:14 PM PST 24
Peak memory 209896 kb
Host smart-7bacf516-a9dd-424b-aa90-8161118f2b09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649814658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.1649814658
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2115882823
Short name T424
Test name
Test status
Simulation time 2381199137 ps
CPU time 6.96 seconds
Started Jan 10 12:28:38 PM PST 24
Finished Jan 10 12:28:57 PM PST 24
Peak memory 213816 kb
Host smart-35b6b96c-def7-4ed7-bb12-b37ffcbdd34c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115882823 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2115882823
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3294836653
Short name T87
Test name
Test status
Simulation time 2859577584 ps
CPU time 12.66 seconds
Started Jan 10 12:22:55 PM PST 24
Finished Jan 10 12:23:08 PM PST 24
Peak memory 211180 kb
Host smart-12cb1586-ebe0-49ca-8279-70745bf87b32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294836653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3294836653
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2099170428
Short name T421
Test name
Test status
Simulation time 28431741721 ps
CPU time 186.93 seconds
Started Jan 10 12:28:37 PM PST 24
Finished Jan 10 12:31:56 PM PST 24
Peak memory 210772 kb
Host smart-b72d122b-1a3b-44ac-bf2e-2bb412028889
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099170428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2099170428
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.587407830
Short name T107
Test name
Test status
Simulation time 741375982 ps
CPU time 8.75 seconds
Started Jan 10 12:24:32 PM PST 24
Finished Jan 10 12:24:41 PM PST 24
Peak memory 211112 kb
Host smart-4a9fd11b-0478-45a6-a8f3-da045bd7f228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587407830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.587407830
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1748991867
Short name T62
Test name
Test status
Simulation time 1589288985 ps
CPU time 18.38 seconds
Started Jan 10 12:24:02 PM PST 24
Finished Jan 10 12:24:24 PM PST 24
Peak memory 219344 kb
Host smart-2ef05b25-8560-418a-baa8-5a9cb1ab7973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748991867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1748991867
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1102354768
Short name T115
Test name
Test status
Simulation time 1327699740 ps
CPU time 47.23 seconds
Started Jan 10 12:28:37 PM PST 24
Finished Jan 10 12:29:36 PM PST 24
Peak memory 211596 kb
Host smart-192dd033-1f0e-4572-8845-9556e089a883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102354768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1102354768
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3620343672
Short name T402
Test name
Test status
Simulation time 6032026380 ps
CPU time 13.04 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:32 PM PST 24
Peak memory 211016 kb
Host smart-2daf620f-9634-4d30-afd6-6c5ed5abdd57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620343672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3620343672
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.742322047
Short name T262
Test name
Test status
Simulation time 4978796287 ps
CPU time 144.64 seconds
Started Jan 10 01:04:35 PM PST 24
Finished Jan 10 01:08:18 PM PST 24
Peak memory 236504 kb
Host smart-007684cb-6aca-4675-90b9-2e55861021f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742322047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.742322047
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.907971773
Short name T260
Test name
Test status
Simulation time 4199616571 ps
CPU time 34.37 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:58 PM PST 24
Peak memory 211236 kb
Host smart-abd8392d-3b8a-4415-bfae-a6b996acdbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907971773 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.907971773
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3566212618
Short name T408
Test name
Test status
Simulation time 897208033 ps
CPU time 10.94 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:36 PM PST 24
Peak memory 210872 kb
Host smart-49a92f79-4259-4e18-be94-e00dcf61a235
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3566212618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3566212618
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.2388354542
Short name T44
Test name
Test status
Simulation time 1435704482 ps
CPU time 111.91 seconds
Started Jan 10 01:03:54 PM PST 24
Finished Jan 10 01:07:07 PM PST 24
Peak memory 236252 kb
Host smart-68494c79-e8fb-4fb8-8ba5-d3c22416e474
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388354542 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2388354542
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.1171386566
Short name T90
Test name
Test status
Simulation time 19083440892 ps
CPU time 41.28 seconds
Started Jan 10 01:03:47 PM PST 24
Finished Jan 10 01:05:39 PM PST 24
Peak memory 213592 kb
Host smart-5e77a781-a207-4f45-8606-b60034e33815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171386566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.1171386566
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.4263656131
Short name T263
Test name
Test status
Simulation time 49266581509 ps
CPU time 800.38 seconds
Started Jan 10 01:04:08 PM PST 24
Finished Jan 10 01:18:57 PM PST 24
Peak memory 235464 kb
Host smart-c39e0dbf-9033-4564-ae41-8883f221f92d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263656131 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.4263656131
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3817914897
Short name T163
Test name
Test status
Simulation time 2110468949 ps
CPU time 17.16 seconds
Started Jan 10 01:04:02 PM PST 24
Finished Jan 10 01:05:49 PM PST 24
Peak memory 210868 kb
Host smart-07291f54-76d4-44d1-a4d0-a52274568fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817914897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3817914897
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.508952566
Short name T212
Test name
Test status
Simulation time 1158903860 ps
CPU time 13.73 seconds
Started Jan 10 01:04:37 PM PST 24
Finished Jan 10 01:06:17 PM PST 24
Peak memory 210968 kb
Host smart-7651a1f3-796e-4a50-aa41-17491008eb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508952566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.508952566
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3258677826
Short name T274
Test name
Test status
Simulation time 196498431 ps
CPU time 5.69 seconds
Started Jan 10 01:04:16 PM PST 24
Finished Jan 10 01:05:40 PM PST 24
Peak memory 210800 kb
Host smart-20728db4-a477-48f9-8b15-5bd76eb20805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258677826 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3258677826
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.3417707226
Short name T38
Test name
Test status
Simulation time 2857793139 ps
CPU time 113.82 seconds
Started Jan 10 01:03:49 PM PST 24
Finished Jan 10 01:06:58 PM PST 24
Peak memory 236368 kb
Host smart-74edce99-400e-4246-a8f1-8e7a675a6494
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417707226 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.3417707226
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3563094868
Short name T150
Test name
Test status
Simulation time 16374011363 ps
CPU time 41.21 seconds
Started Jan 10 01:03:52 PM PST 24
Finished Jan 10 01:05:58 PM PST 24
Peak memory 213712 kb
Host smart-26932c1f-0934-421e-9f27-c5a2f947363b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563094868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3563094868
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.279916620
Short name T142
Test name
Test status
Simulation time 9167389143 ps
CPU time 22.05 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:45 PM PST 24
Peak memory 210768 kb
Host smart-18efa5ca-cb25-4641-96b1-07e11aa88358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279916620 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.279916620
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.2783127459
Short name T390
Test name
Test status
Simulation time 78889309111 ps
CPU time 1487.8 seconds
Started Jan 10 01:04:35 PM PST 24
Finished Jan 10 01:31:05 PM PST 24
Peak memory 235432 kb
Host smart-b9e49dab-174e-4a36-b244-fb31345983a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783127459 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.2783127459
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.3862069600
Short name T355
Test name
Test status
Simulation time 4095902765 ps
CPU time 16.7 seconds
Started Jan 10 01:04:10 PM PST 24
Finished Jan 10 01:05:53 PM PST 24
Peak memory 211008 kb
Host smart-0bf3563b-c277-499b-a6ff-477149dd94fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862069600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.3862069600
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.2070570674
Short name T53
Test name
Test status
Simulation time 179283376779 ps
CPU time 398.52 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:12:06 PM PST 24
Peak memory 233552 kb
Host smart-f0499121-1481-4df3-961b-5bc2cf6ddf62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070570674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.2070570674
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.466991578
Short name T292
Test name
Test status
Simulation time 4466534432 ps
CPU time 11.87 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:29 PM PST 24
Peak memory 210888 kb
Host smart-abac1b08-c0b7-4756-a4e9-89138ac84266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466991578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.466991578
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.3052845289
Short name T233
Test name
Test status
Simulation time 22861735691 ps
CPU time 28.92 seconds
Started Jan 10 01:04:03 PM PST 24
Finished Jan 10 01:05:54 PM PST 24
Peak memory 211032 kb
Host smart-89de080d-19b0-426c-8781-140c43cae500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052845289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.3052845289
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3474003442
Short name T151
Test name
Test status
Simulation time 1533613162 ps
CPU time 24.05 seconds
Started Jan 10 01:04:02 PM PST 24
Finished Jan 10 01:05:48 PM PST 24
Peak memory 215328 kb
Host smart-7ed07798-eb49-409e-9fb3-7fc93a9bf51f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474003442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3474003442
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.3244709816
Short name T308
Test name
Test status
Simulation time 754625077 ps
CPU time 4.72 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:39 PM PST 24
Peak memory 210960 kb
Host smart-aff5c49c-964a-43d4-bae0-4c09fb205b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244709816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3244709816
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3563053022
Short name T178
Test name
Test status
Simulation time 86711139167 ps
CPU time 206.53 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:09:03 PM PST 24
Peak memory 227896 kb
Host smart-b352494b-818f-461b-8a50-e325d6b1e2e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563053022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3563053022
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3061842001
Short name T214
Test name
Test status
Simulation time 8352169512 ps
CPU time 33.97 seconds
Started Jan 10 01:03:46 PM PST 24
Finished Jan 10 01:05:32 PM PST 24
Peak memory 211672 kb
Host smart-4c827513-143d-40e2-a77a-8562ed228e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061842001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3061842001
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1243411918
Short name T399
Test name
Test status
Simulation time 430383622 ps
CPU time 8.35 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:05:34 PM PST 24
Peak memory 210888 kb
Host smart-eb66ea6b-6512-40d6-bbea-bab04b5f3136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243411918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1243411918
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.2787777435
Short name T375
Test name
Test status
Simulation time 4694959640 ps
CPU time 15.17 seconds
Started Jan 10 01:04:08 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 212848 kb
Host smart-d0ec6dd3-c511-478a-aef8-17df8f6a855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787777435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.2787777435
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3736317744
Short name T9
Test name
Test status
Simulation time 2466806388 ps
CPU time 29.86 seconds
Started Jan 10 01:04:26 PM PST 24
Finished Jan 10 01:06:17 PM PST 24
Peak memory 212972 kb
Host smart-e4a5b6a5-e0df-462c-9bf4-951c4355c136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736317744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3736317744
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4072407382
Short name T23
Test name
Test status
Simulation time 139917162196 ps
CPU time 1206.94 seconds
Started Jan 10 01:03:56 PM PST 24
Finished Jan 10 01:25:29 PM PST 24
Peak memory 235456 kb
Host smart-96a8b363-91cc-4374-a70f-7fde48ee22c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072407382 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.4072407382
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.2240007693
Short name T176
Test name
Test status
Simulation time 1626288182 ps
CPU time 8.02 seconds
Started Jan 10 01:04:18 PM PST 24
Finished Jan 10 01:05:46 PM PST 24
Peak memory 210948 kb
Host smart-2dffe411-07a6-4d04-88b1-dcb2f70fa2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240007693 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.2240007693
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.3777938572
Short name T264
Test name
Test status
Simulation time 15970902810 ps
CPU time 122.25 seconds
Started Jan 10 01:04:08 PM PST 24
Finished Jan 10 01:07:44 PM PST 24
Peak memory 237400 kb
Host smart-e608d55b-371f-4566-84a0-659741e66c2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777938572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.3777938572
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.2702953764
Short name T324
Test name
Test status
Simulation time 8168114323 ps
CPU time 34.47 seconds
Started Jan 10 01:04:10 PM PST 24
Finished Jan 10 01:06:04 PM PST 24
Peak memory 211352 kb
Host smart-5f7aeabc-f8e9-4559-88ea-c7cf1f85bca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702953764 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.2702953764
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1719974095
Short name T322
Test name
Test status
Simulation time 717542532 ps
CPU time 8.08 seconds
Started Jan 10 01:04:25 PM PST 24
Finished Jan 10 01:05:56 PM PST 24
Peak memory 210752 kb
Host smart-7cac8eae-4d44-4c5d-a480-27fb22365a47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719974095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1719974095
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.1951988514
Short name T347
Test name
Test status
Simulation time 6622095230 ps
CPU time 14.85 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:05:59 PM PST 24
Peak memory 213264 kb
Host smart-4314749e-6556-4031-8be0-b96910f29b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951988514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.1951988514
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2959823586
Short name T391
Test name
Test status
Simulation time 231567807 ps
CPU time 7.83 seconds
Started Jan 10 01:04:12 PM PST 24
Finished Jan 10 01:05:52 PM PST 24
Peak memory 211596 kb
Host smart-05ef831b-ea74-47b3-8502-f7d919910299
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959823586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2959823586
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.1610025072
Short name T353
Test name
Test status
Simulation time 149436733089 ps
CPU time 361.27 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:11:29 PM PST 24
Peak memory 234388 kb
Host smart-7b067e01-f16a-4b5c-a153-fd0177625b5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610025072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.1610025072
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.417390293
Short name T383
Test name
Test status
Simulation time 1243176810 ps
CPU time 12.86 seconds
Started Jan 10 01:04:22 PM PST 24
Finished Jan 10 01:05:53 PM PST 24
Peak memory 210900 kb
Host smart-ba5525b9-3e53-4173-a9f8-b15c4f50aa3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417390293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.417390293
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.3806114882
Short name T317
Test name
Test status
Simulation time 7570019650 ps
CPU time 21.94 seconds
Started Jan 10 01:04:04 PM PST 24
Finished Jan 10 01:05:57 PM PST 24
Peak memory 213548 kb
Host smart-81713d75-fcf8-4f02-829f-de880130d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806114882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.3806114882
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.3987405123
Short name T217
Test name
Test status
Simulation time 30613047948 ps
CPU time 34 seconds
Started Jan 10 01:04:13 PM PST 24
Finished Jan 10 01:06:21 PM PST 24
Peak memory 212912 kb
Host smart-fc00f265-4f63-4b02-86d2-67c86bb6379a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987405123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.3987405123
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2628290127
Short name T303
Test name
Test status
Simulation time 992634693 ps
CPU time 10.79 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:06:03 PM PST 24
Peak memory 210928 kb
Host smart-1889afba-b12d-4e02-ac61-49fc16f04205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628290127 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2628290127
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1222592631
Short name T313
Test name
Test status
Simulation time 605181049216 ps
CPU time 430.76 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:13:16 PM PST 24
Peak memory 236472 kb
Host smart-92537e43-7c94-41e7-bb45-e0e4685905e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222592631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1222592631
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3336795033
Short name T158
Test name
Test status
Simulation time 102110708 ps
CPU time 5.91 seconds
Started Jan 10 01:04:30 PM PST 24
Finished Jan 10 01:05:58 PM PST 24
Peak memory 210832 kb
Host smart-e605f440-624d-42cf-8042-32f7cf5b45b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336795033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3336795033
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.3022696375
Short name T413
Test name
Test status
Simulation time 4451285393 ps
CPU time 33.21 seconds
Started Jan 10 01:04:10 PM PST 24
Finished Jan 10 01:06:01 PM PST 24
Peak memory 212440 kb
Host smart-21dc5834-e321-45d5-8b81-c1a8ece65fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022696375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.3022696375
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2484389190
Short name T197
Test name
Test status
Simulation time 321966470 ps
CPU time 19.89 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:56 PM PST 24
Peak memory 214936 kb
Host smart-420a0ba6-f039-4cfb-819e-1b83f719faa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484389190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2484389190
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.2804334321
Short name T156
Test name
Test status
Simulation time 1074987360 ps
CPU time 10.96 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:05:43 PM PST 24
Peak memory 210868 kb
Host smart-43b8108f-da79-49a6-985e-4fea86561d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804334321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2804334321
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2662671111
Short name T339
Test name
Test status
Simulation time 43196761093 ps
CPU time 218.41 seconds
Started Jan 10 01:04:15 PM PST 24
Finished Jan 10 01:09:18 PM PST 24
Peak memory 233368 kb
Host smart-d416cf4f-e085-483c-83a9-f3ce0d3be2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662671111 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.2662671111
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.403229390
Short name T363
Test name
Test status
Simulation time 13520031318 ps
CPU time 30.49 seconds
Started Jan 10 01:04:26 PM PST 24
Finished Jan 10 01:06:13 PM PST 24
Peak memory 211188 kb
Host smart-32023875-399e-4a1f-a0c8-623aa94d3fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403229390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.403229390
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3994796554
Short name T180
Test name
Test status
Simulation time 387578909 ps
CPU time 5.89 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:05:43 PM PST 24
Peak memory 210884 kb
Host smart-c6b77a81-1d4c-47c4-99d5-088db800cef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994796554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3994796554
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1192265104
Short name T386
Test name
Test status
Simulation time 713331934 ps
CPU time 10.85 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 212496 kb
Host smart-f1e4c331-70e3-49c6-aa82-fae365cd49b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192265104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1192265104
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2229971876
Short name T384
Test name
Test status
Simulation time 34539878848 ps
CPU time 81.29 seconds
Started Jan 10 01:04:31 PM PST 24
Finished Jan 10 01:07:11 PM PST 24
Peak memory 216980 kb
Host smart-ae430705-aa99-433a-933f-8e3a50b44946
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229971876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2229971876
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.2405577340
Short name T366
Test name
Test status
Simulation time 60156739707 ps
CPU time 2281.41 seconds
Started Jan 10 01:04:34 PM PST 24
Finished Jan 10 01:43:55 PM PST 24
Peak memory 238288 kb
Host smart-f1a19cc9-f088-4d2c-9aa8-94bf7f4ad245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405577340 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.2405577340
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1083641883
Short name T241
Test name
Test status
Simulation time 1798675646 ps
CPU time 7.54 seconds
Started Jan 10 01:04:31 PM PST 24
Finished Jan 10 01:05:57 PM PST 24
Peak memory 210860 kb
Host smart-00272723-db07-466b-9136-2793be340ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083641883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1083641883
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2903639269
Short name T222
Test name
Test status
Simulation time 183921794246 ps
CPU time 362.71 seconds
Started Jan 10 01:04:15 PM PST 24
Finished Jan 10 01:11:41 PM PST 24
Peak memory 233460 kb
Host smart-26b99610-6eb9-48aa-9956-2da64531457a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903639269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2903639269
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3604010564
Short name T208
Test name
Test status
Simulation time 11489418860 ps
CPU time 26.57 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:06:13 PM PST 24
Peak memory 211388 kb
Host smart-0ad1b182-48cf-41bf-83c6-e9b9f1df9cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604010564 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3604010564
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.346750988
Short name T411
Test name
Test status
Simulation time 703783534 ps
CPU time 9.87 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:44 PM PST 24
Peak memory 210888 kb
Host smart-8bf549cc-4e40-4c44-8289-6242e1ac81f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=346750988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.346750988
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.4078972416
Short name T265
Test name
Test status
Simulation time 6212154110 ps
CPU time 28.2 seconds
Started Jan 10 01:04:17 PM PST 24
Finished Jan 10 01:06:08 PM PST 24
Peak memory 213908 kb
Host smart-ab0174b2-87e3-41f9-b114-6b139779ca74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078972416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.4078972416
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.105064672
Short name T188
Test name
Test status
Simulation time 134123113297 ps
CPU time 4361.42 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 02:18:10 PM PST 24
Peak memory 230508 kb
Host smart-841407ea-1f7c-415e-b7b3-50e24f23ece2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105064672 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.105064672
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.2933513737
Short name T360
Test name
Test status
Simulation time 1843462927 ps
CPU time 14.83 seconds
Started Jan 10 01:04:35 PM PST 24
Finished Jan 10 01:06:32 PM PST 24
Peak memory 210956 kb
Host smart-873513cd-9a81-4bb3-b8b3-9993064c0bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933513737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2933513737
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1257051122
Short name T10
Test name
Test status
Simulation time 32809382196 ps
CPU time 281.82 seconds
Started Jan 10 01:04:15 PM PST 24
Finished Jan 10 01:10:18 PM PST 24
Peak memory 212148 kb
Host smart-717da26f-ccbc-4f71-ac91-c61d57f7faaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257051122 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1257051122
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.1330518429
Short name T261
Test name
Test status
Simulation time 14476748322 ps
CPU time 21.54 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:06:08 PM PST 24
Peak memory 211660 kb
Host smart-3972d84b-4744-4185-86fe-8c63e048c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330518429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.1330518429
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.3740627513
Short name T323
Test name
Test status
Simulation time 1426122113 ps
CPU time 14.29 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:47 PM PST 24
Peak memory 210832 kb
Host smart-990cfaa0-2656-4439-8f9e-cabcb77c3871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740627513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.3740627513
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2529228187
Short name T26
Test name
Test status
Simulation time 718354596 ps
CPU time 10.12 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:05:36 PM PST 24
Peak memory 211920 kb
Host smart-14964153-ae3e-4c33-bd09-f3ce519fdbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529228187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2529228187
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.44891194
Short name T405
Test name
Test status
Simulation time 1975050162 ps
CPU time 21.68 seconds
Started Jan 10 01:03:57 PM PST 24
Finished Jan 10 01:05:43 PM PST 24
Peak memory 211080 kb
Host smart-920dfb97-f6f6-4019-8086-918c7eac7397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44891194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 17.rom_ctrl_stress_all.44891194
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.1347893005
Short name T187
Test name
Test status
Simulation time 52393511342 ps
CPU time 954.8 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:21:34 PM PST 24
Peak memory 235588 kb
Host smart-1f48d2ec-78a8-4821-8e22-4d9c757e001a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347893005 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.1347893005
Directory /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.1965247436
Short name T167
Test name
Test status
Simulation time 175223541 ps
CPU time 4.48 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:37 PM PST 24
Peak memory 210940 kb
Host smart-de0f348b-2a8a-4518-9019-4152e9cbdac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965247436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.1965247436
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.397882716
Short name T404
Test name
Test status
Simulation time 1686606784 ps
CPU time 68.64 seconds
Started Jan 10 01:04:08 PM PST 24
Finished Jan 10 01:06:39 PM PST 24
Peak memory 236176 kb
Host smart-5bf5dfc0-b539-4a95-b4d5-fcf290507136
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397882716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_c
orrupt_sig_fatal_chk.397882716
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.982323521
Short name T385
Test name
Test status
Simulation time 27173038002 ps
CPU time 30.56 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:06:03 PM PST 24
Peak memory 211328 kb
Host smart-be835c90-74cb-4c5e-bd0f-b31e009f0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982323521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.982323521
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1175664741
Short name T240
Test name
Test status
Simulation time 99761770 ps
CPU time 5.6 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:05:52 PM PST 24
Peak memory 210896 kb
Host smart-755197db-16c5-4ddd-8b88-98ae0caf00ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175664741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1175664741
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2663547638
Short name T367
Test name
Test status
Simulation time 2838036920 ps
CPU time 30.19 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:06:01 PM PST 24
Peak memory 211960 kb
Host smart-9d2d9f40-6291-44ff-adde-f27813e33ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663547638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2663547638
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.666727148
Short name T369
Test name
Test status
Simulation time 2911620995 ps
CPU time 18.42 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:05:55 PM PST 24
Peak memory 213040 kb
Host smart-58a0acf7-8bde-43b1-a149-c0aa7f928e2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666727148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.rom_ctrl_stress_all.666727148
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2118412644
Short name T406
Test name
Test status
Simulation time 27497660846 ps
CPU time 1657.84 seconds
Started Jan 10 01:04:13 PM PST 24
Finished Jan 10 01:33:13 PM PST 24
Peak memory 235492 kb
Host smart-16a2d10d-4215-4a87-9d66-27d971a6b545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118412644 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2118412644
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.785232237
Short name T357
Test name
Test status
Simulation time 346640456 ps
CPU time 4.42 seconds
Started Jan 10 01:04:13 PM PST 24
Finished Jan 10 01:05:35 PM PST 24
Peak memory 210940 kb
Host smart-26c150de-963f-4191-a89d-1c11525b31cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785232237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.785232237
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.3289708894
Short name T243
Test name
Test status
Simulation time 13378580965 ps
CPU time 28.88 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:50 PM PST 24
Peak memory 210880 kb
Host smart-f37b5f95-6f32-4dd0-86f7-fcc9ed6d0871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289708894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.3289708894
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.683522380
Short name T211
Test name
Test status
Simulation time 196543789 ps
CPU time 5.77 seconds
Started Jan 10 01:04:12 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 210900 kb
Host smart-8ee7db43-e4dd-491b-98ce-5cee70d4ee03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=683522380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.683522380
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3048250298
Short name T354
Test name
Test status
Simulation time 16414960603 ps
CPU time 40.58 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:06:27 PM PST 24
Peak memory 213124 kb
Host smart-a3d34930-ceb1-4b51-85c3-c207922dcffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048250298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3048250298
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.3423003535
Short name T268
Test name
Test status
Simulation time 819050704 ps
CPU time 44.1 seconds
Started Jan 10 01:04:27 PM PST 24
Finished Jan 10 01:06:36 PM PST 24
Peak memory 215636 kb
Host smart-4c81950a-76f9-4c09-a90a-5625ae0b7d53
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423003535 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.3423003535
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.936240354
Short name T141
Test name
Test status
Simulation time 178413251627 ps
CPU time 2862.87 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:54:04 PM PST 24
Peak memory 237580 kb
Host smart-887ef496-b2c3-45b3-880b-2d2658f4f06d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936240354 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.936240354
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.4167507208
Short name T368
Test name
Test status
Simulation time 348160494 ps
CPU time 4.31 seconds
Started Jan 10 01:04:00 PM PST 24
Finished Jan 10 01:05:27 PM PST 24
Peak memory 210940 kb
Host smart-a98ab1a5-e64b-4c46-a0c0-d2cd63d10b94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167507208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.4167507208
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3893501792
Short name T224
Test name
Test status
Simulation time 50103925351 ps
CPU time 505.29 seconds
Started Jan 10 01:04:04 PM PST 24
Finished Jan 10 01:13:58 PM PST 24
Peak memory 236404 kb
Host smart-248f4a29-17a3-49c2-af2a-29b8fa6cc49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893501792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.3893501792
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2161543368
Short name T215
Test name
Test status
Simulation time 169915582 ps
CPU time 9.96 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:37 PM PST 24
Peak memory 212596 kb
Host smart-dd9bd479-a971-476b-95fb-dd2e3d38bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161543368 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2161543368
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.617861659
Short name T283
Test name
Test status
Simulation time 839319768 ps
CPU time 5.8 seconds
Started Jan 10 01:04:22 PM PST 24
Finished Jan 10 01:05:45 PM PST 24
Peak memory 210876 kb
Host smart-a61d57a6-7f42-4c7e-8c0a-125ba7c92283
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=617861659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.617861659
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.870760133
Short name T396
Test name
Test status
Simulation time 9482757424 ps
CPU time 24.52 seconds
Started Jan 10 01:04:03 PM PST 24
Finished Jan 10 01:05:49 PM PST 24
Peak memory 213168 kb
Host smart-8414ada4-41ee-499a-87eb-9e52fdb6f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870760133 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.870760133
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.2391015179
Short name T182
Test name
Test status
Simulation time 13009047514 ps
CPU time 35.33 seconds
Started Jan 10 01:04:01 PM PST 24
Finished Jan 10 01:05:55 PM PST 24
Peak memory 215980 kb
Host smart-f63be39b-3dc6-4cb5-9ffd-fc045f74b004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391015179 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.2391015179
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1065572623
Short name T206
Test name
Test status
Simulation time 106309461729 ps
CPU time 1437.59 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:29:47 PM PST 24
Peak memory 235592 kb
Host smart-dbfef4aa-7fe4-4df1-939e-dd82939f06c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065572623 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.1065572623
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3001553107
Short name T148
Test name
Test status
Simulation time 69483817346 ps
CPU time 136.29 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:07:52 PM PST 24
Peak memory 233488 kb
Host smart-a001d5a9-e777-492c-a9dc-d9ec790468f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001553107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3001553107
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.973422545
Short name T190
Test name
Test status
Simulation time 22712652621 ps
CPU time 22.89 seconds
Started Jan 10 01:04:25 PM PST 24
Finished Jan 10 01:06:10 PM PST 24
Peak memory 211352 kb
Host smart-f96efe9d-912f-43be-acd4-e90b44848823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973422545 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.973422545
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.17403381
Short name T147
Test name
Test status
Simulation time 412417978 ps
CPU time 5.57 seconds
Started Jan 10 01:04:15 PM PST 24
Finished Jan 10 01:05:43 PM PST 24
Peak memory 210808 kb
Host smart-c02fdd4a-d441-44b8-b3b5-d10817152846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=17403381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.17403381
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.3860743478
Short name T181
Test name
Test status
Simulation time 2160319693 ps
CPU time 18.59 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:05:59 PM PST 24
Peak memory 212848 kb
Host smart-5f7488a3-4041-4e6e-b359-2fa03534d5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860743478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.3860743478
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.2381919498
Short name T337
Test name
Test status
Simulation time 24002835532 ps
CPU time 46.83 seconds
Started Jan 10 01:04:14 PM PST 24
Finished Jan 10 01:06:18 PM PST 24
Peak memory 213168 kb
Host smart-60ccacb3-e3a8-4806-8a6c-35f22b2175f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381919498 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.2381919498
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.2859504551
Short name T286
Test name
Test status
Simulation time 1465526311 ps
CPU time 13.47 seconds
Started Jan 10 01:03:59 PM PST 24
Finished Jan 10 01:05:34 PM PST 24
Peak memory 210824 kb
Host smart-70e5e8c6-1153-49fd-947f-765185e6c502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859504551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2859504551
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.3419867101
Short name T46
Test name
Test status
Simulation time 8762776303 ps
CPU time 76.97 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:06:53 PM PST 24
Peak memory 228256 kb
Host smart-8f696975-be69-4fe1-addf-dfb416c218c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419867101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_
corrupt_sig_fatal_chk.3419867101
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.777137103
Short name T12
Test name
Test status
Simulation time 6813554774 ps
CPU time 28.84 seconds
Started Jan 10 01:04:20 PM PST 24
Finished Jan 10 01:06:19 PM PST 24
Peak memory 211876 kb
Host smart-49e1cbe8-fe5c-4e69-b7d6-e98fc4b2790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777137103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.777137103
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.875243083
Short name T104
Test name
Test status
Simulation time 1849698440 ps
CPU time 8.36 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:32 PM PST 24
Peak memory 210884 kb
Host smart-f9cc31e1-a701-458f-9ae0-f3a8386f6f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875243083 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.875243083
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.2930866413
Short name T172
Test name
Test status
Simulation time 7910771863 ps
CPU time 26.77 seconds
Started Jan 10 01:04:49 PM PST 24
Finished Jan 10 01:06:46 PM PST 24
Peak memory 213848 kb
Host smart-d1dd251d-869c-47c5-a046-fb347d223ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930866413 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.2930866413
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.2230724653
Short name T285
Test name
Test status
Simulation time 30238891634 ps
CPU time 75.74 seconds
Started Jan 10 01:04:46 PM PST 24
Finished Jan 10 01:07:26 PM PST 24
Peak memory 216324 kb
Host smart-1b558c8d-62c7-429a-98cb-a98c63966103
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230724653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.2230724653
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.3929786792
Short name T320
Test name
Test status
Simulation time 57391973262 ps
CPU time 1042.63 seconds
Started Jan 10 01:04:03 PM PST 24
Finished Jan 10 01:23:10 PM PST 24
Peak memory 235600 kb
Host smart-27414421-f178-42e2-a838-518641e84946
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929786792 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.3929786792
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.466328991
Short name T356
Test name
Test status
Simulation time 7211721187 ps
CPU time 14.36 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:50 PM PST 24
Peak memory 211020 kb
Host smart-312e0bef-940a-46c6-8304-3f3b3e40a3c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466328991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.466328991
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.4121662783
Short name T306
Test name
Test status
Simulation time 40546667221 ps
CPU time 116.87 seconds
Started Jan 10 01:03:57 PM PST 24
Finished Jan 10 01:07:19 PM PST 24
Peak memory 227376 kb
Host smart-86a03b53-305f-4ee3-8dd2-9bc8b1cb655f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121662783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.4121662783
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2437794357
Short name T234
Test name
Test status
Simulation time 1384923355 ps
CPU time 9.7 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:35 PM PST 24
Peak memory 210900 kb
Host smart-3727f17d-839a-4686-b699-c32480ebe92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437794357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2437794357
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2350547552
Short name T218
Test name
Test status
Simulation time 31993553096 ps
CPU time 16.04 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:45 PM PST 24
Peak memory 210968 kb
Host smart-28b9993b-f055-405c-bb53-28f0c86dd17a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350547552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2350547552
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.831082975
Short name T245
Test name
Test status
Simulation time 853325510 ps
CPU time 9.97 seconds
Started Jan 10 01:04:33 PM PST 24
Finished Jan 10 01:06:06 PM PST 24
Peak memory 212856 kb
Host smart-d5ff3cf7-de53-43f3-93a6-cd79df80c316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831082975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.831082975
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2151875355
Short name T48
Test name
Test status
Simulation time 55612640515 ps
CPU time 76.45 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:06:44 PM PST 24
Peak memory 215932 kb
Host smart-5ae37066-1eb4-4fdb-9553-09915d6ffba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151875355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2151875355
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.1992569805
Short name T144
Test name
Test status
Simulation time 87883998756 ps
CPU time 2062.79 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:39:50 PM PST 24
Peak memory 234008 kb
Host smart-29fab2f8-28a8-4fba-85be-be99b66620ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992569805 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.1992569805
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.2529563451
Short name T276
Test name
Test status
Simulation time 1725649359 ps
CPU time 14.77 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:06:15 PM PST 24
Peak memory 210960 kb
Host smart-7f065e76-036c-46be-9c64-9de558404c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529563451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.2529563451
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.1010862263
Short name T328
Test name
Test status
Simulation time 5781402631 ps
CPU time 78.08 seconds
Started Jan 10 01:04:47 PM PST 24
Finished Jan 10 01:07:26 PM PST 24
Peak memory 212176 kb
Host smart-ac0cf0a3-adcb-4360-ac4a-b469699acda9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010862263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.1010862263
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2479314819
Short name T244
Test name
Test status
Simulation time 36148720460 ps
CPU time 24.83 seconds
Started Jan 10 01:04:39 PM PST 24
Finished Jan 10 01:06:22 PM PST 24
Peak memory 214936 kb
Host smart-cd77e07d-d2ab-4755-acfc-8d00d2bcc7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479314819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2479314819
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.1192360092
Short name T216
Test name
Test status
Simulation time 5124357358 ps
CPU time 13.66 seconds
Started Jan 10 01:04:38 PM PST 24
Finished Jan 10 01:06:10 PM PST 24
Peak memory 210984 kb
Host smart-9df633d0-6498-4748-9f89-a9c82701963a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192360092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.1192360092
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.2265472968
Short name T417
Test name
Test status
Simulation time 3429114914 ps
CPU time 37.87 seconds
Started Jan 10 01:04:04 PM PST 24
Finished Jan 10 01:06:01 PM PST 24
Peak memory 212356 kb
Host smart-0702a70c-0416-46b5-8c68-2b0b1f0630e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265472968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.2265472968
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.1427674401
Short name T203
Test name
Test status
Simulation time 17990233712 ps
CPU time 35.96 seconds
Started Jan 10 01:04:18 PM PST 24
Finished Jan 10 01:06:38 PM PST 24
Peak memory 219028 kb
Host smart-5590e82b-a4df-42a2-bf7a-8bfba3c2f6cd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427674401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.1427674401
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.733727293
Short name T373
Test name
Test status
Simulation time 1284815762 ps
CPU time 12.05 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:06:01 PM PST 24
Peak memory 211020 kb
Host smart-1d1d3736-282f-4609-9217-2d4a2d34851b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733727293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.733727293
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.4233650149
Short name T361
Test name
Test status
Simulation time 197495318605 ps
CPU time 503.8 seconds
Started Jan 10 01:04:29 PM PST 24
Finished Jan 10 01:14:09 PM PST 24
Peak memory 212116 kb
Host smart-5d4accc6-dfbf-4258-91d6-adaf3344dc81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233650149 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.4233650149
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.3955789063
Short name T17
Test name
Test status
Simulation time 4099494218 ps
CPU time 32.97 seconds
Started Jan 10 01:04:49 PM PST 24
Finished Jan 10 01:06:42 PM PST 24
Peak memory 210976 kb
Host smart-050f1664-efed-4350-85b2-e55ca069ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955789063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.3955789063
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2435856242
Short name T387
Test name
Test status
Simulation time 4040866048 ps
CPU time 16.65 seconds
Started Jan 10 01:04:37 PM PST 24
Finished Jan 10 01:06:20 PM PST 24
Peak memory 210952 kb
Host smart-1d60f78f-b86c-4bf7-9489-fea777c0d8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435856242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2435856242
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2549653422
Short name T89
Test name
Test status
Simulation time 2758129083 ps
CPU time 19.43 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:33 PM PST 24
Peak memory 213188 kb
Host smart-4e50b189-3e6d-4dc0-8b1a-a0785da122f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549653422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2549653422
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.1206548709
Short name T389
Test name
Test status
Simulation time 10638188013 ps
CPU time 52.23 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:07:13 PM PST 24
Peak memory 216736 kb
Host smart-49093429-da2c-49b7-910e-2684b92610c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206548709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.1206548709
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.3802676208
Short name T1
Test name
Test status
Simulation time 47679462596 ps
CPU time 895.12 seconds
Started Jan 10 01:04:22 PM PST 24
Finished Jan 10 01:20:40 PM PST 24
Peak memory 235564 kb
Host smart-e581bdee-dbb1-43ad-830a-8610a426e16d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802676208 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.3802676208
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.2517448554
Short name T279
Test name
Test status
Simulation time 9240426775 ps
CPU time 16.88 seconds
Started Jan 10 01:04:46 PM PST 24
Finished Jan 10 01:06:27 PM PST 24
Peak memory 210920 kb
Host smart-bfd939ff-244c-49d3-888b-13fc4838a801
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517448554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2517448554
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3476785198
Short name T196
Test name
Test status
Simulation time 80129480086 ps
CPU time 234.3 seconds
Started Jan 10 01:04:37 PM PST 24
Finished Jan 10 01:10:16 PM PST 24
Peak memory 224072 kb
Host smart-e729dc35-36e2-4dbe-aa09-74d6e209c266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476785198 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3476785198
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.725469219
Short name T301
Test name
Test status
Simulation time 16700151291 ps
CPU time 33.81 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:06:39 PM PST 24
Peak memory 211328 kb
Host smart-182bd671-f136-4920-a41a-8685b24042c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725469219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.725469219
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.3138721630
Short name T157
Test name
Test status
Simulation time 650614014 ps
CPU time 5.6 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:05:54 PM PST 24
Peak memory 210900 kb
Host smart-604e4c3f-edec-4bf2-8e4b-c5a21a6a333e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138721630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.3138721630
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.2885138934
Short name T103
Test name
Test status
Simulation time 1010901077 ps
CPU time 17.19 seconds
Started Jan 10 01:04:22 PM PST 24
Finished Jan 10 01:06:02 PM PST 24
Peak memory 212464 kb
Host smart-d53c8816-daa9-4fda-877b-452b57e5fc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885138934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.2885138934
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.2197250941
Short name T7
Test name
Test status
Simulation time 9133394948 ps
CPU time 41.94 seconds
Started Jan 10 01:04:18 PM PST 24
Finished Jan 10 01:06:20 PM PST 24
Peak memory 217448 kb
Host smart-42ca64f7-045c-434c-a268-2c1bb0c0de45
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197250941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.2197250941
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.557142738
Short name T281
Test name
Test status
Simulation time 206744769714 ps
CPU time 3706.41 seconds
Started Jan 10 01:04:25 PM PST 24
Finished Jan 10 02:07:30 PM PST 24
Peak memory 235432 kb
Host smart-17278873-4a6f-4d64-a907-3a32e4037c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557142738 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.557142738
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1726597087
Short name T171
Test name
Test status
Simulation time 2830302521 ps
CPU time 15.78 seconds
Started Jan 10 01:04:46 PM PST 24
Finished Jan 10 01:06:26 PM PST 24
Peak memory 210980 kb
Host smart-5d5736fd-7639-4c5d-ab42-ccaa78f1f7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726597087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1726597087
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.438200856
Short name T280
Test name
Test status
Simulation time 1660096316 ps
CPU time 112.26 seconds
Started Jan 10 01:04:18 PM PST 24
Finished Jan 10 01:07:30 PM PST 24
Peak memory 237244 kb
Host smart-3a41e12f-038a-4b80-a0fd-a1fd89e17368
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438200856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_c
orrupt_sig_fatal_chk.438200856
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.384584811
Short name T198
Test name
Test status
Simulation time 2005551385 ps
CPU time 21.96 seconds
Started Jan 10 01:04:47 PM PST 24
Finished Jan 10 01:06:49 PM PST 24
Peak memory 211064 kb
Host smart-a8455237-e095-4097-967b-5cf8541c6733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384584811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.384584811
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3314494758
Short name T290
Test name
Test status
Simulation time 3376952826 ps
CPU time 10.96 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:12 PM PST 24
Peak memory 210800 kb
Host smart-4a6fed4f-7100-4448-9ee4-584409a24932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314494758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3314494758
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2451199337
Short name T249
Test name
Test status
Simulation time 8553815274 ps
CPU time 22.84 seconds
Started Jan 10 01:04:39 PM PST 24
Finished Jan 10 01:06:27 PM PST 24
Peak memory 212876 kb
Host smart-398839f2-1921-4aab-ae0f-fba84e23065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451199337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2451199337
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1358301192
Short name T350
Test name
Test status
Simulation time 226209438 ps
CPU time 14.86 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:06:30 PM PST 24
Peak memory 213156 kb
Host smart-58678e37-b7ff-41f0-9e32-ce545d2b2eb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358301192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1358301192
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2961721145
Short name T343
Test name
Test status
Simulation time 4826749467 ps
CPU time 12.67 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:23 PM PST 24
Peak memory 210528 kb
Host smart-a583d010-ed35-43f5-aeb4-38d9f38d61a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961721145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2961721145
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.997258613
Short name T15
Test name
Test status
Simulation time 162074043238 ps
CPU time 415.19 seconds
Started Jan 10 01:04:40 PM PST 24
Finished Jan 10 01:12:59 PM PST 24
Peak memory 237212 kb
Host smart-bcde82d3-4ac3-4473-9a9b-07e096d3c9ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997258613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.997258613
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.395819531
Short name T333
Test name
Test status
Simulation time 3076495578 ps
CPU time 27.61 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:23 PM PST 24
Peak memory 210496 kb
Host smart-07e194bb-4410-4649-bf30-68f9b672ed99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395819531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.395819531
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.2281874896
Short name T2
Test name
Test status
Simulation time 8227532584 ps
CPU time 16.65 seconds
Started Jan 10 01:04:36 PM PST 24
Finished Jan 10 01:06:26 PM PST 24
Peak memory 210952 kb
Host smart-0aecb969-efd6-43c3-a5a2-f6fb8dff1efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281874896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.2281874896
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.749569285
Short name T170
Test name
Test status
Simulation time 12173717613 ps
CPU time 33.42 seconds
Started Jan 10 01:04:59 PM PST 24
Finished Jan 10 01:07:12 PM PST 24
Peak memory 212792 kb
Host smart-449902f8-ea14-480d-96b6-6213e1c8c1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749569285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.749569285
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.363886943
Short name T21
Test name
Test status
Simulation time 103681318386 ps
CPU time 1470.19 seconds
Started Jan 10 01:04:35 PM PST 24
Finished Jan 10 01:30:23 PM PST 24
Peak memory 227380 kb
Host smart-085b8a1e-a550-45fe-98d9-18225ca618f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363886943 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.363886943
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.2562044660
Short name T154
Test name
Test status
Simulation time 88016670 ps
CPU time 4.38 seconds
Started Jan 10 01:04:31 PM PST 24
Finished Jan 10 01:05:58 PM PST 24
Peak memory 210928 kb
Host smart-8d1ecd43-2333-4ba8-8eda-aec6103a966f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562044660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.2562044660
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.2561124706
Short name T362
Test name
Test status
Simulation time 149628861761 ps
CPU time 412 seconds
Started Jan 10 01:04:34 PM PST 24
Finished Jan 10 01:12:45 PM PST 24
Peak memory 237388 kb
Host smart-d9bc08ea-e299-4406-aa83-41539a036bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561124706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.2561124706
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.404547434
Short name T358
Test name
Test status
Simulation time 2933392881 ps
CPU time 26.92 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:06:36 PM PST 24
Peak memory 211036 kb
Host smart-988160b4-1af5-4543-bac4-8c0871989b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404547434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.404547434
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.825527346
Short name T174
Test name
Test status
Simulation time 2008969558 ps
CPU time 16.81 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:06:18 PM PST 24
Peak memory 210848 kb
Host smart-fa998f1d-7d3d-43c7-83a6-25dcada22497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=825527346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.825527346
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2769436949
Short name T365
Test name
Test status
Simulation time 25758911226 ps
CPU time 40.04 seconds
Started Jan 10 01:04:21 PM PST 24
Finished Jan 10 01:06:21 PM PST 24
Peak memory 213032 kb
Host smart-869cc4c5-c1b1-4dfb-9f59-bb1ca1c6dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769436949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2769436949
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1513469321
Short name T254
Test name
Test status
Simulation time 5569972046 ps
CPU time 48.08 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:43 PM PST 24
Peak memory 212168 kb
Host smart-580fc40f-2e3a-4922-a755-397b51d60f15
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513469321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1513469321
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.276420760
Short name T146
Test name
Test status
Simulation time 78708299854 ps
CPU time 2875.09 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:53:45 PM PST 24
Peak memory 244856 kb
Host smart-0dcc843b-af64-4aba-81b0-094d1625f082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276420760 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.276420760
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1378779633
Short name T351
Test name
Test status
Simulation time 1381291451 ps
CPU time 4.51 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 210892 kb
Host smart-ed4b2b82-39c4-49f1-943d-212ca2ed321c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378779633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1378779633
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3175917125
Short name T275
Test name
Test status
Simulation time 4566702336 ps
CPU time 59.91 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:08:50 PM PST 24
Peak memory 226564 kb
Host smart-4ba87728-fd8a-47b3-9023-cccff265c553
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175917125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3175917125
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.869202019
Short name T205
Test name
Test status
Simulation time 16588361199 ps
CPU time 33.5 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:08:23 PM PST 24
Peak memory 209712 kb
Host smart-952b847e-3d28-4b41-b882-ce092846dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869202019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.869202019
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.62398022
Short name T145
Test name
Test status
Simulation time 433248416 ps
CPU time 5.37 seconds
Started Jan 10 01:04:26 PM PST 24
Finished Jan 10 01:05:47 PM PST 24
Peak memory 210896 kb
Host smart-efabcd20-c238-4258-8dd4-9d5b44ed5b14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62398022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.62398022
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.1636361041
Short name T88
Test name
Test status
Simulation time 2220021715 ps
CPU time 14.69 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:06:24 PM PST 24
Peak memory 212712 kb
Host smart-6a9a707c-7336-415f-a646-b43c87a39925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636361041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1636361041
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3614129753
Short name T330
Test name
Test status
Simulation time 18248674212 ps
CPU time 42.65 seconds
Started Jan 10 01:06:16 PM PST 24
Finished Jan 10 01:08:21 PM PST 24
Peak memory 216124 kb
Host smart-852ffbfe-1cb0-40f8-970d-86d411c9dd59
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614129753 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3614129753
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1637641916
Short name T282
Test name
Test status
Simulation time 347474459 ps
CPU time 4.46 seconds
Started Jan 10 01:04:10 PM PST 24
Finished Jan 10 01:05:40 PM PST 24
Peak memory 210932 kb
Host smart-c41fa489-0562-49ad-953c-29d07d81c933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637641916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1637641916
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1115315797
Short name T195
Test name
Test status
Simulation time 13285244270 ps
CPU time 178.17 seconds
Started Jan 10 01:04:29 PM PST 24
Finished Jan 10 01:09:00 PM PST 24
Peak memory 236424 kb
Host smart-1fd6be80-03ba-48bd-b75c-9d2a96f35922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115315797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1115315797
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3349581178
Short name T335
Test name
Test status
Simulation time 2811867406 ps
CPU time 26.34 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:43 PM PST 24
Peak memory 211028 kb
Host smart-c3a30ae5-cf70-4ff5-8d94-b200d131dfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349581178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3349581178
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3365809157
Short name T50
Test name
Test status
Simulation time 341739016 ps
CPU time 5.6 seconds
Started Jan 10 01:04:00 PM PST 24
Finished Jan 10 01:05:23 PM PST 24
Peak memory 210816 kb
Host smart-1dd19f42-df08-46a2-bcf3-d9657151fb92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3365809157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3365809157
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2697499423
Short name T37
Test name
Test status
Simulation time 283402849 ps
CPU time 57.86 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:06:30 PM PST 24
Peak memory 236400 kb
Host smart-aa7dc306-ac60-46c4-882e-d0e30c170754
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697499423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2697499423
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3103931766
Short name T359
Test name
Test status
Simulation time 3533028929 ps
CPU time 31.25 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:06:07 PM PST 24
Peak memory 213192 kb
Host smart-8cc396c2-1102-45ae-bba3-e7b301a7ccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103931766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3103931766
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.284988613
Short name T161
Test name
Test status
Simulation time 1152593194 ps
CPU time 22.7 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:48 PM PST 24
Peak memory 212920 kb
Host smart-d8315451-ef81-4c3b-9e1d-d1e38bc1317e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284988613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.284988613
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3650049557
Short name T371
Test name
Test status
Simulation time 85650772 ps
CPU time 4.48 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:06:16 PM PST 24
Peak memory 211012 kb
Host smart-6b2b7d13-456c-46dd-9862-0ab8c65566b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650049557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3650049557
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1564499938
Short name T219
Test name
Test status
Simulation time 141861400984 ps
CPU time 346.84 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:13:43 PM PST 24
Peak memory 235880 kb
Host smart-acd34aae-1347-4d86-a897-938197c6b746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564499938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1564499938
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2172874571
Short name T277
Test name
Test status
Simulation time 172094424 ps
CPU time 9.38 seconds
Started Jan 10 01:06:43 PM PST 24
Finished Jan 10 01:08:05 PM PST 24
Peak memory 210556 kb
Host smart-8f37f50e-bead-49a5-9c24-fd454572b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172874571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2172874571
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1731269714
Short name T193
Test name
Test status
Simulation time 2875693572 ps
CPU time 14.11 seconds
Started Jan 10 01:04:43 PM PST 24
Finished Jan 10 01:06:29 PM PST 24
Peak memory 210964 kb
Host smart-b9fea71f-f2e8-44e1-9fee-b70fd38ce976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1731269714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1731269714
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1329545088
Short name T160
Test name
Test status
Simulation time 13210523235 ps
CPU time 37.02 seconds
Started Jan 10 01:04:59 PM PST 24
Finished Jan 10 01:07:03 PM PST 24
Peak memory 213752 kb
Host smart-6f5e60b1-bc28-4892-8b4a-433e5c8e1ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329545088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1329545088
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2453987500
Short name T314
Test name
Test status
Simulation time 1026140365 ps
CPU time 12.97 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:06:13 PM PST 24
Peak memory 212836 kb
Host smart-69e61579-3f71-45b9-a992-134648635a29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453987500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2453987500
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2227003242
Short name T297
Test name
Test status
Simulation time 8419416418 ps
CPU time 17.3 seconds
Started Jan 10 01:04:45 PM PST 24
Finished Jan 10 01:06:24 PM PST 24
Peak memory 211008 kb
Host smart-6d7a7885-9d6c-48b0-8d14-7eabf52f8eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227003242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2227003242
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.629168100
Short name T295
Test name
Test status
Simulation time 168595182 ps
CPU time 9.78 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:06:33 PM PST 24
Peak memory 210880 kb
Host smart-81ad67fc-7d6f-4a8c-88e2-06ac852d3392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629168100 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.629168100
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2220965879
Short name T392
Test name
Test status
Simulation time 1683950912 ps
CPU time 14.91 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:35 PM PST 24
Peak memory 210820 kb
Host smart-ac6f55cc-182d-4a29-ae2d-aad9a7658794
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2220965879 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2220965879
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3293955878
Short name T166
Test name
Test status
Simulation time 1460093649 ps
CPU time 18.68 seconds
Started Jan 10 01:04:21 PM PST 24
Finished Jan 10 01:06:20 PM PST 24
Peak memory 212148 kb
Host smart-4673b12e-cb01-4ded-b5ff-fce6261dc906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293955878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3293955878
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.26577487
Short name T152
Test name
Test status
Simulation time 2865090256 ps
CPU time 31.24 seconds
Started Jan 10 01:04:43 PM PST 24
Finished Jan 10 01:06:48 PM PST 24
Peak memory 212576 kb
Host smart-78392a1f-a156-4e5c-8ce9-3783ac5f791a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26577487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 31.rom_ctrl_stress_all.26577487
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.205741028
Short name T242
Test name
Test status
Simulation time 105548902508 ps
CPU time 3122.92 seconds
Started Jan 10 01:04:49 PM PST 24
Finished Jan 10 01:58:12 PM PST 24
Peak memory 238080 kb
Host smart-416ed80c-f732-4f0c-9841-62589a480d42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205741028 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.205741028
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.3087365463
Short name T47
Test name
Test status
Simulation time 86550815 ps
CPU time 4.56 seconds
Started Jan 10 01:04:19 PM PST 24
Finished Jan 10 01:05:45 PM PST 24
Peak memory 210900 kb
Host smart-c8f3a4ae-97cc-4077-8357-df433daa81fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087365463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.3087365463
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3572362538
Short name T334
Test name
Test status
Simulation time 134786937172 ps
CPU time 364.43 seconds
Started Jan 10 01:04:25 PM PST 24
Finished Jan 10 01:11:52 PM PST 24
Peak memory 224080 kb
Host smart-1fcfaba3-1ce5-47be-9625-be4fc989a06c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572362538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3572362538
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.2660861173
Short name T311
Test name
Test status
Simulation time 4530624698 ps
CPU time 18.81 seconds
Started Jan 10 01:04:34 PM PST 24
Finished Jan 10 01:06:11 PM PST 24
Peak memory 211396 kb
Host smart-06f6df22-b0b8-40ed-98ce-b246e1be786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660861173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.2660861173
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3576815550
Short name T382
Test name
Test status
Simulation time 3335964899 ps
CPU time 10.63 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:11 PM PST 24
Peak memory 211036 kb
Host smart-4a87d428-df8e-4dea-a518-554030cdb630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576815550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3576815550
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.525152822
Short name T372
Test name
Test status
Simulation time 3239668697 ps
CPU time 28.18 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:08:18 PM PST 24
Peak memory 211568 kb
Host smart-45b5e8cf-82c3-4e75-b5f3-5e1c53ce7a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525152822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.525152822
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.1614847397
Short name T179
Test name
Test status
Simulation time 3996145650 ps
CPU time 40.98 seconds
Started Jan 10 01:04:22 PM PST 24
Finished Jan 10 01:06:25 PM PST 24
Peak memory 212796 kb
Host smart-87d05734-51f5-42c2-b5fa-97f4ab4b0ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614847397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.1614847397
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.521157270
Short name T247
Test name
Test status
Simulation time 9929049933 ps
CPU time 13.85 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:06:25 PM PST 24
Peak memory 210984 kb
Host smart-19c86f21-84af-44c6-985f-852ac306fd65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521157270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.521157270
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.250993528
Short name T287
Test name
Test status
Simulation time 27518371732 ps
CPU time 250.21 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:10:31 PM PST 24
Peak memory 211236 kb
Host smart-212a07d4-7980-4dc8-bf57-e50d12bb0e7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250993528 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_c
orrupt_sig_fatal_chk.250993528
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2746561950
Short name T364
Test name
Test status
Simulation time 6717373344 ps
CPU time 17.26 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:28 PM PST 24
Peak memory 211532 kb
Host smart-fe715cab-afd2-4126-b3fa-1da1809fed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746561950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2746561950
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.2029625039
Short name T186
Test name
Test status
Simulation time 377086029 ps
CPU time 5.42 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:27 PM PST 24
Peak memory 210820 kb
Host smart-1ee5f6d0-0082-460c-bdaa-e788afb4786e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029625039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.2029625039
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.698153757
Short name T223
Test name
Test status
Simulation time 5074038520 ps
CPU time 17.59 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:08:17 PM PST 24
Peak memory 212268 kb
Host smart-ae15072d-dd2d-4258-b9b9-aaf29d4f9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698153757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.698153757
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2605995496
Short name T49
Test name
Test status
Simulation time 21146122712 ps
CPU time 48.71 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:06:57 PM PST 24
Peak memory 213400 kb
Host smart-06abcadd-0ce7-4ca1-8c8e-7275ff93c493
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605995496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2605995496
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1280460367
Short name T407
Test name
Test status
Simulation time 26836626418 ps
CPU time 1631.9 seconds
Started Jan 10 01:04:33 PM PST 24
Finished Jan 10 01:33:08 PM PST 24
Peak memory 235320 kb
Host smart-6f7ec7a8-33be-4da5-bc08-b33c5368e889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280460367 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1280460367
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.3469408322
Short name T288
Test name
Test status
Simulation time 3135325919 ps
CPU time 9.45 seconds
Started Jan 10 01:04:47 PM PST 24
Finished Jan 10 01:06:37 PM PST 24
Peak memory 210908 kb
Host smart-b270699d-1a6f-4f2a-85a7-8af1fc98123e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469408322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.3469408322
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.172264711
Short name T327
Test name
Test status
Simulation time 258530766938 ps
CPU time 409.44 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:14:39 PM PST 24
Peak memory 211272 kb
Host smart-8dd77b78-44e1-4be1-8a01-b16476992839
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172264711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.172264711
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2776255935
Short name T5
Test name
Test status
Simulation time 35495538239 ps
CPU time 28.62 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:50 PM PST 24
Peak memory 211420 kb
Host smart-79a19890-6c7c-4464-89b0-4e5f6250d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776255935 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2776255935
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3666917664
Short name T379
Test name
Test status
Simulation time 1850562726 ps
CPU time 8.38 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:06:25 PM PST 24
Peak memory 210776 kb
Host smart-cda1f553-68d3-471a-8bf1-789b182c624a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3666917664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3666917664
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.765241897
Short name T159
Test name
Test status
Simulation time 708651213 ps
CPU time 10.33 seconds
Started Jan 10 01:04:40 PM PST 24
Finished Jan 10 01:06:34 PM PST 24
Peak memory 212416 kb
Host smart-a737bb6d-00c6-4129-af92-999bab289b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765241897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.765241897
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2949828462
Short name T22
Test name
Test status
Simulation time 119829357390 ps
CPU time 6091.77 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 02:47:53 PM PST 24
Peak memory 235604 kb
Host smart-c0cc53b7-f588-4951-ad84-eb831f7ab9f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949828462 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2949828462
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2911890138
Short name T394
Test name
Test status
Simulation time 309518222 ps
CPU time 4.23 seconds
Started Jan 10 01:05:19 PM PST 24
Finished Jan 10 01:06:52 PM PST 24
Peak memory 210872 kb
Host smart-bfec2250-7ecf-4de7-8e9d-5f07b2745da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911890138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2911890138
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.4127949954
Short name T342
Test name
Test status
Simulation time 43731367944 ps
CPU time 388.04 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:12:51 PM PST 24
Peak memory 234480 kb
Host smart-f0c1007f-6231-4311-b2a1-60595d3f25b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127949954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.4127949954
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2540668483
Short name T336
Test name
Test status
Simulation time 171913937 ps
CPU time 9.77 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:06:28 PM PST 24
Peak memory 210964 kb
Host smart-1fc79689-698e-4a2a-8f18-40095ad686c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540668483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2540668483
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.374984092
Short name T269
Test name
Test status
Simulation time 371788674 ps
CPU time 6.02 seconds
Started Jan 10 01:04:45 PM PST 24
Finished Jan 10 01:06:11 PM PST 24
Peak memory 211076 kb
Host smart-0bda2a4c-cc77-475c-be3e-9c621014274f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=374984092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.374984092
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.2707202705
Short name T409
Test name
Test status
Simulation time 8957051381 ps
CPU time 28.45 seconds
Started Jan 10 01:04:47 PM PST 24
Finished Jan 10 01:06:36 PM PST 24
Peak memory 212972 kb
Host smart-3cf65a94-f290-4b19-b770-01375d9178dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707202705 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.2707202705
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.904245628
Short name T310
Test name
Test status
Simulation time 3251098705 ps
CPU time 35.22 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:59 PM PST 24
Peak memory 213996 kb
Host smart-b18438fd-94f1-4bb0-82b5-be485a9f6f3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904245628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.rom_ctrl_stress_all.904245628
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.1087828403
Short name T352
Test name
Test status
Simulation time 2996797318 ps
CPU time 13.55 seconds
Started Jan 10 01:05:03 PM PST 24
Finished Jan 10 01:06:51 PM PST 24
Peak memory 210980 kb
Host smart-c43bdef3-05e2-4d30-b949-3c7920fdbd77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087828403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.1087828403
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.199902668
Short name T227
Test name
Test status
Simulation time 110409572402 ps
CPU time 306.92 seconds
Started Jan 10 01:05:03 PM PST 24
Finished Jan 10 01:11:42 PM PST 24
Peak memory 225184 kb
Host smart-b9fb0501-1424-4fe1-9741-af3aa96819a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199902668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.199902668
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.142807394
Short name T11
Test name
Test status
Simulation time 173905673 ps
CPU time 9.9 seconds
Started Jan 10 01:05:05 PM PST 24
Finished Jan 10 01:06:47 PM PST 24
Peak memory 211084 kb
Host smart-12ffa1a3-44ba-4ffc-bae2-eff51c0ae2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142807394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.142807394
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.1242323889
Short name T341
Test name
Test status
Simulation time 29715127180 ps
CPU time 14.77 seconds
Started Jan 10 01:05:18 PM PST 24
Finished Jan 10 01:07:12 PM PST 24
Peak memory 210788 kb
Host smart-85e225f3-2234-4616-a479-1d8375b1880b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1242323889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.1242323889
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.881383881
Short name T298
Test name
Test status
Simulation time 2133301910 ps
CPU time 25.41 seconds
Started Jan 10 01:04:52 PM PST 24
Finished Jan 10 01:06:59 PM PST 24
Peak memory 212604 kb
Host smart-dae02b4e-d5dd-4962-bae5-ef0f415e4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881383881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.881383881
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.519849418
Short name T267
Test name
Test status
Simulation time 8883162125 ps
CPU time 64.23 seconds
Started Jan 10 01:05:11 PM PST 24
Finished Jan 10 01:07:55 PM PST 24
Peak memory 214060 kb
Host smart-979bdb0e-0e1f-4aa7-a8f1-cdf4e9a8fde9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519849418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.519849418
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.421615446
Short name T102
Test name
Test status
Simulation time 4992084668 ps
CPU time 10.75 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 01:06:11 PM PST 24
Peak memory 210892 kb
Host smart-5cf6f706-f504-4214-a8c7-54c746600d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421615446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.421615446
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.3394535353
Short name T173
Test name
Test status
Simulation time 14047786501 ps
CPU time 181.58 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:09:11 PM PST 24
Peak memory 237456 kb
Host smart-d7d0e7fa-3fd6-4c7c-9dad-bf895b476c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394535353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.3394535353
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.930824961
Short name T191
Test name
Test status
Simulation time 3460977048 ps
CPU time 30.2 seconds
Started Jan 10 01:04:52 PM PST 24
Finished Jan 10 01:07:04 PM PST 24
Peak memory 210872 kb
Host smart-318f28e3-3189-4182-94aa-aa75e62ff9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930824961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.930824961
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3599061055
Short name T221
Test name
Test status
Simulation time 261593745 ps
CPU time 7.82 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:06:25 PM PST 24
Peak memory 210928 kb
Host smart-f3a6d75d-0c89-42ce-a676-bb12f82ec17d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599061055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3599061055
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.3427007837
Short name T155
Test name
Test status
Simulation time 10610451379 ps
CPU time 52.28 seconds
Started Jan 10 01:05:06 PM PST 24
Finished Jan 10 01:07:25 PM PST 24
Peak memory 216528 kb
Host smart-9fe90c1c-5722-4ed6-91e5-3d418e199ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427007837 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.3427007837
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1425529862
Short name T238
Test name
Test status
Simulation time 151930990927 ps
CPU time 969.54 seconds
Started Jan 10 01:04:49 PM PST 24
Finished Jan 10 01:22:18 PM PST 24
Peak memory 235464 kb
Host smart-281f528e-9d32-4de3-a593-805a3aaaa2aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425529862 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1425529862
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.4277019026
Short name T400
Test name
Test status
Simulation time 593519618 ps
CPU time 4.52 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:06:28 PM PST 24
Peak memory 211004 kb
Host smart-db471732-953f-4257-96b5-d8b01da357c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277019026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.4277019026
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.1757975283
Short name T348
Test name
Test status
Simulation time 379988140852 ps
CPU time 351.63 seconds
Started Jan 10 01:04:53 PM PST 24
Finished Jan 10 01:12:18 PM PST 24
Peak memory 236056 kb
Host smart-53132c43-f131-4bc3-88e8-a163f9a02a0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757975283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.1757975283
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.318165549
Short name T300
Test name
Test status
Simulation time 15637394868 ps
CPU time 33 seconds
Started Jan 10 01:05:20 PM PST 24
Finished Jan 10 01:07:18 PM PST 24
Peak memory 211316 kb
Host smart-a65b749f-b0d8-4567-a3b5-20c2597c8449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318165549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.318165549
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3065357369
Short name T289
Test name
Test status
Simulation time 14321343569 ps
CPU time 16.95 seconds
Started Jan 10 01:04:53 PM PST 24
Finished Jan 10 01:06:43 PM PST 24
Peak memory 210844 kb
Host smart-e8e58bd0-6de8-41c4-b1f9-385b441babd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065357369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3065357369
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3282521703
Short name T189
Test name
Test status
Simulation time 846930311 ps
CPU time 15.6 seconds
Started Jan 10 01:05:12 PM PST 24
Finished Jan 10 01:07:04 PM PST 24
Peak memory 211876 kb
Host smart-77361831-5356-430b-a22d-e77b0ade9ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282521703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3282521703
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.1484386286
Short name T296
Test name
Test status
Simulation time 12947698537 ps
CPU time 108.46 seconds
Started Jan 10 01:04:53 PM PST 24
Finished Jan 10 01:08:09 PM PST 24
Peak memory 219104 kb
Host smart-6b706a76-0b4a-4e49-9bea-8c2a9f540242
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484386286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.1484386286
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.1352799339
Short name T200
Test name
Test status
Simulation time 51188468826 ps
CPU time 9254.45 seconds
Started Jan 10 01:05:04 PM PST 24
Finished Jan 10 03:41:05 PM PST 24
Peak memory 237116 kb
Host smart-1074d5c2-44a4-4a4f-9602-bed39ae7d7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352799339 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.1352799339
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3034762868
Short name T397
Test name
Test status
Simulation time 1142282385 ps
CPU time 8.31 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:06:32 PM PST 24
Peak memory 210956 kb
Host smart-601b5b65-caba-4f17-abe9-53df555efd75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034762868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3034762868
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3859875881
Short name T378
Test name
Test status
Simulation time 1511391349 ps
CPU time 101.42 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:07:59 PM PST 24
Peak memory 237176 kb
Host smart-5232493c-e447-4747-8ed8-62a882e81e02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859875881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3859875881
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.3651996596
Short name T349
Test name
Test status
Simulation time 25135467340 ps
CPU time 27.54 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:06:50 PM PST 24
Peak memory 211620 kb
Host smart-549484ba-0b14-4cbb-8ce2-633337b32573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651996596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.3651996596
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3107793610
Short name T209
Test name
Test status
Simulation time 478738295 ps
CPU time 8.58 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:06:36 PM PST 24
Peak memory 210888 kb
Host smart-c7292819-888a-43c7-bd7a-29c80b321cb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3107793610 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3107793610
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4267156907
Short name T271
Test name
Test status
Simulation time 194275415 ps
CPU time 10.44 seconds
Started Jan 10 01:05:04 PM PST 24
Finished Jan 10 01:07:00 PM PST 24
Peak memory 212248 kb
Host smart-91e6e1d7-fbbf-49ff-9891-03c2e7116d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267156907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4267156907
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.3956344834
Short name T235
Test name
Test status
Simulation time 7888824324 ps
CPU time 79.11 seconds
Started Jan 10 01:04:49 PM PST 24
Finished Jan 10 01:07:32 PM PST 24
Peak memory 217376 kb
Host smart-55996ba2-86d2-4d87-afca-82cb62a3d3a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956344834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.3956344834
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.2487244187
Short name T388
Test name
Test status
Simulation time 9553004101 ps
CPU time 1740.58 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:35:10 PM PST 24
Peak memory 223028 kb
Host smart-a5a0708d-b8aa-485e-968f-c6266338e460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487244187 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.2487244187
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.1880591948
Short name T229
Test name
Test status
Simulation time 1379888354 ps
CPU time 12.45 seconds
Started Jan 10 01:04:02 PM PST 24
Finished Jan 10 01:05:32 PM PST 24
Peak memory 210948 kb
Host smart-9ff068cc-475a-417c-9175-38d844fa48c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880591948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.1880591948
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.2221838726
Short name T294
Test name
Test status
Simulation time 40465279015 ps
CPU time 247.35 seconds
Started Jan 10 01:04:10 PM PST 24
Finished Jan 10 01:09:43 PM PST 24
Peak memory 227952 kb
Host smart-09f965b1-4c76-4f4e-8ae5-3d9069264397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221838726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.2221838726
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4238182449
Short name T304
Test name
Test status
Simulation time 168793173 ps
CPU time 9.63 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:32 PM PST 24
Peak memory 210960 kb
Host smart-f7fa9191-ee02-4330-b497-504553e0ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238182449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4238182449
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.297678945
Short name T153
Test name
Test status
Simulation time 7908856637 ps
CPU time 17.31 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:05:48 PM PST 24
Peak memory 210812 kb
Host smart-7d9ab690-887c-4b83-8725-0fd2e28ceaf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=297678945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.297678945
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2053929364
Short name T45
Test name
Test status
Simulation time 469695197 ps
CPU time 59.98 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:06:26 PM PST 24
Peak memory 236288 kb
Host smart-a8d3f901-fd07-4922-915c-c31cca8ebcf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053929364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2053929364
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2140607828
Short name T177
Test name
Test status
Simulation time 13271291492 ps
CPU time 35.17 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:06:03 PM PST 24
Peak memory 213288 kb
Host smart-4e927c00-3d39-4e8c-9ebc-4f4300b66d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140607828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2140607828
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.1166912144
Short name T319
Test name
Test status
Simulation time 34577922303 ps
CPU time 35.97 seconds
Started Jan 10 01:03:56 PM PST 24
Finished Jan 10 01:05:50 PM PST 24
Peak memory 213400 kb
Host smart-97660edf-a6f2-4271-aaf1-bc6bdfde5dcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166912144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.1166912144
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1678643644
Short name T299
Test name
Test status
Simulation time 80138720728 ps
CPU time 2751.78 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:51:24 PM PST 24
Peak memory 244816 kb
Host smart-ba9d16e9-6be9-4104-9a21-c1cedcd9db81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678643644 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1678643644
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.4153817722
Short name T40
Test name
Test status
Simulation time 1674537979 ps
CPU time 9.39 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:06:14 PM PST 24
Peak memory 211008 kb
Host smart-9a1b1650-b921-4ca1-8dd2-df3c5be05ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153817722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.4153817722
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.2908513357
Short name T54
Test name
Test status
Simulation time 55136671945 ps
CPU time 186.55 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:09:41 PM PST 24
Peak memory 236376 kb
Host smart-4b26fc65-d1ce-4a4b-a64d-e39153a9c474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908513357 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.2908513357
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1375351311
Short name T376
Test name
Test status
Simulation time 2438537515 ps
CPU time 24.76 seconds
Started Jan 10 01:04:44 PM PST 24
Finished Jan 10 01:06:51 PM PST 24
Peak memory 211132 kb
Host smart-98b53eb7-0e59-4173-bf23-3f8f3c155e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375351311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1375351311
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2573238662
Short name T415
Test name
Test status
Simulation time 2735873423 ps
CPU time 16.08 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:06:21 PM PST 24
Peak memory 210944 kb
Host smart-9f01a24d-4f74-4530-9b4f-3da978a27f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2573238662 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2573238662
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.381899562
Short name T272
Test name
Test status
Simulation time 8253467707 ps
CPU time 25 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:06:43 PM PST 24
Peak memory 213000 kb
Host smart-5b20a18a-19f5-4936-8dd7-20b98657a2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381899562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.381899562
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.425760587
Short name T316
Test name
Test status
Simulation time 7362418879 ps
CPU time 17.62 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:06:44 PM PST 24
Peak memory 211400 kb
Host smart-2d86f734-13ab-4829-85c2-ffd6920cdf16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425760587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.rom_ctrl_stress_all.425760587
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.3677273223
Short name T416
Test name
Test status
Simulation time 107473869328 ps
CPU time 3257.7 seconds
Started Jan 10 01:04:41 PM PST 24
Finished Jan 10 02:00:19 PM PST 24
Peak memory 235552 kb
Host smart-77a85291-ae29-441f-8c0f-9d55ecca9da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677273223 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.3677273223
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1010750298
Short name T410
Test name
Test status
Simulation time 1519161555 ps
CPU time 13.11 seconds
Started Jan 10 01:04:55 PM PST 24
Finished Jan 10 01:06:32 PM PST 24
Peak memory 210956 kb
Host smart-8edce5e7-ff02-4d97-82d5-f61b3309c03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010750298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1010750298
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2767293664
Short name T52
Test name
Test status
Simulation time 63460496750 ps
CPU time 208.45 seconds
Started Jan 10 01:04:51 PM PST 24
Finished Jan 10 01:09:46 PM PST 24
Peak memory 233364 kb
Host smart-65a1fd29-e2da-4c1e-8927-9cd1c0bbbd43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767293664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2767293664
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1185359666
Short name T250
Test name
Test status
Simulation time 615968956 ps
CPU time 9.73 seconds
Started Jan 10 01:04:53 PM PST 24
Finished Jan 10 01:06:31 PM PST 24
Peak memory 211004 kb
Host smart-d0b07327-36ce-47e8-8daa-df9b3f1064b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185359666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1185359666
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.3133070819
Short name T232
Test name
Test status
Simulation time 2533397214 ps
CPU time 15.67 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:29 PM PST 24
Peak memory 210880 kb
Host smart-35b2f982-ae37-4504-a0e8-17ac075b91fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3133070819 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.3133070819
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.824158004
Short name T251
Test name
Test status
Simulation time 4301817558 ps
CPU time 30.8 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:44 PM PST 24
Peak memory 212212 kb
Host smart-e5975ca2-43eb-4a96-be53-d4c524c3ab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824158004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.824158004
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.2428733823
Short name T305
Test name
Test status
Simulation time 3031221500 ps
CPU time 13.34 seconds
Started Jan 10 01:05:18 PM PST 24
Finished Jan 10 01:07:10 PM PST 24
Peak memory 212516 kb
Host smart-1026a035-755d-458e-b8ab-3c2862df7dac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428733823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.2428733823
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.3591302188
Short name T237
Test name
Test status
Simulation time 92301861851 ps
CPU time 1687.21 seconds
Started Jan 10 01:04:42 PM PST 24
Finished Jan 10 01:34:24 PM PST 24
Peak memory 235576 kb
Host smart-59cc867f-f48a-4921-93e6-6f75ae645b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591302188 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.3591302188
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3569445383
Short name T374
Test name
Test status
Simulation time 1614982838 ps
CPU time 9.21 seconds
Started Jan 10 01:04:52 PM PST 24
Finished Jan 10 01:06:43 PM PST 24
Peak memory 210796 kb
Host smart-af83b07b-9ad0-4223-a859-fad1924f28ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569445383 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3569445383
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.2957038770
Short name T307
Test name
Test status
Simulation time 129108697097 ps
CPU time 212.05 seconds
Started Jan 10 01:04:52 PM PST 24
Finished Jan 10 01:09:50 PM PST 24
Peak memory 236228 kb
Host smart-607ed517-ae70-469d-8136-c557484168e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957038770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.2957038770
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2914752390
Short name T259
Test name
Test status
Simulation time 2857732500 ps
CPU time 27.11 seconds
Started Jan 10 01:05:40 PM PST 24
Finished Jan 10 01:07:35 PM PST 24
Peak memory 210960 kb
Host smart-a719bedb-2b49-4ebb-bf34-111fb1ce9b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914752390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2914752390
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3257819190
Short name T255
Test name
Test status
Simulation time 190915196 ps
CPU time 5.97 seconds
Started Jan 10 01:05:23 PM PST 24
Finished Jan 10 01:07:05 PM PST 24
Peak memory 210836 kb
Host smart-f287687c-9ba5-4a68-a146-77b8bafcc88d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3257819190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3257819190
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1529762417
Short name T302
Test name
Test status
Simulation time 8456526070 ps
CPU time 33.42 seconds
Started Jan 10 01:05:03 PM PST 24
Finished Jan 10 01:07:03 PM PST 24
Peak memory 212896 kb
Host smart-00b6f135-b031-4932-80f2-fc51a4206217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529762417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1529762417
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3075723349
Short name T309
Test name
Test status
Simulation time 4946526442 ps
CPU time 50.11 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:07:17 PM PST 24
Peak memory 215812 kb
Host smart-0605f4a5-4bf1-40e7-9661-79ee90349667
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075723349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3075723349
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3251180102
Short name T253
Test name
Test status
Simulation time 250825656382 ps
CPU time 1823.15 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:36:44 PM PST 24
Peak memory 235468 kb
Host smart-7d3df72d-9100-4b6a-ac70-ac84ed472216
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251180102 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3251180102
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3482466429
Short name T258
Test name
Test status
Simulation time 86580158 ps
CPU time 4.35 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:06:42 PM PST 24
Peak memory 210764 kb
Host smart-580676dd-53a0-4576-bd98-0d903b5f1021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482466429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3482466429
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.3162860678
Short name T291
Test name
Test status
Simulation time 116342962208 ps
CPU time 557.75 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:15:44 PM PST 24
Peak memory 227628 kb
Host smart-f87ed963-26ae-4f14-8f0f-820490d0ab5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162860678 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.3162860678
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.4048481041
Short name T257
Test name
Test status
Simulation time 5751974367 ps
CPU time 17.81 seconds
Started Jan 10 01:04:48 PM PST 24
Finished Jan 10 01:06:27 PM PST 24
Peak memory 211432 kb
Host smart-0636512b-eba7-47d9-884f-505f76b9bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048481041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.4048481041
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.2129167047
Short name T226
Test name
Test status
Simulation time 1392163948 ps
CPU time 13.17 seconds
Started Jan 10 01:04:43 PM PST 24
Finished Jan 10 01:06:33 PM PST 24
Peak memory 210856 kb
Host smart-2d7895bf-14b7-461f-8bcb-d6ffc85f88e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129167047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.2129167047
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2744829295
Short name T169
Test name
Test status
Simulation time 721546618 ps
CPU time 10.73 seconds
Started Jan 10 01:05:07 PM PST 24
Finished Jan 10 01:06:51 PM PST 24
Peak memory 212408 kb
Host smart-c1cf8b68-7b94-4b58-8d06-f6d38f980988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744829295 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2744829295
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.2698993822
Short name T329
Test name
Test status
Simulation time 2736553466 ps
CPU time 9.43 seconds
Started Jan 10 01:04:50 PM PST 24
Finished Jan 10 01:06:23 PM PST 24
Peak memory 210788 kb
Host smart-3caa5487-55a2-45b3-a530-d765836db49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698993822 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 43.rom_ctrl_stress_all.2698993822
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.2964909339
Short name T105
Test name
Test status
Simulation time 5652727889 ps
CPU time 12.68 seconds
Started Jan 10 01:05:33 PM PST 24
Finished Jan 10 01:07:16 PM PST 24
Peak memory 211056 kb
Host smart-6b5a8762-3398-43bb-b2cd-92e73fde48c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964909339 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.2964909339
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2749800278
Short name T398
Test name
Test status
Simulation time 9801420207 ps
CPU time 241.73 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:10:30 PM PST 24
Peak memory 228228 kb
Host smart-43474859-2d87-4afa-b0fb-d8183745b2ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749800278 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2749800278
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.1278639130
Short name T162
Test name
Test status
Simulation time 1380019238 ps
CPU time 18.25 seconds
Started Jan 10 01:04:54 PM PST 24
Finished Jan 10 01:06:39 PM PST 24
Peak memory 211024 kb
Host smart-ddbcd4d6-a4b0-4c32-891a-8c57bfaa8d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278639130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.1278639130
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.829266038
Short name T248
Test name
Test status
Simulation time 374002186 ps
CPU time 5.64 seconds
Started Jan 10 01:04:55 PM PST 24
Finished Jan 10 01:06:31 PM PST 24
Peak memory 210868 kb
Host smart-be4d6cea-cd51-4a6c-872c-f8e1b0faaa11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829266038 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.829266038
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1385916305
Short name T315
Test name
Test status
Simulation time 186161572 ps
CPU time 10.47 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:06:38 PM PST 24
Peak memory 212528 kb
Host smart-55cee959-6649-45a3-b360-45c0ab5ab451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385916305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1385916305
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.670614090
Short name T106
Test name
Test status
Simulation time 1968008658 ps
CPU time 24.17 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:06:52 PM PST 24
Peak memory 212920 kb
Host smart-a022296f-503d-4e22-9333-d3d1bb3f5021
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670614090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 44.rom_ctrl_stress_all.670614090
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.2497141951
Short name T273
Test name
Test status
Simulation time 192928898983 ps
CPU time 2002.53 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:39:45 PM PST 24
Peak memory 235472 kb
Host smart-bbe72a68-9048-4a7e-91fb-19de70eef714
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497141951 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.2497141951
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.549174960
Short name T51
Test name
Test status
Simulation time 106526782 ps
CPU time 4.48 seconds
Started Jan 10 01:04:56 PM PST 24
Finished Jan 10 01:06:24 PM PST 24
Peak memory 210976 kb
Host smart-3f1526b1-7126-46f4-9373-7f44d186f34e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549174960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.549174960
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.803425540
Short name T204
Test name
Test status
Simulation time 9843300914 ps
CPU time 207.3 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:10:02 PM PST 24
Peak memory 237408 kb
Host smart-d1723212-b341-4036-a1cc-18d8d27e296f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803425540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_c
orrupt_sig_fatal_chk.803425540
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1897402151
Short name T293
Test name
Test status
Simulation time 1510558862 ps
CPU time 14.51 seconds
Started Jan 10 01:04:58 PM PST 24
Finished Jan 10 01:06:37 PM PST 24
Peak memory 210868 kb
Host smart-d8c7791d-6606-46c9-8e99-a71720e52381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897402151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1897402151
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.440243315
Short name T199
Test name
Test status
Simulation time 1816882636 ps
CPU time 16.34 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:07:13 PM PST 24
Peak memory 210928 kb
Host smart-228f6900-58b6-4c9f-9103-b68083155fc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440243315 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.440243315
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.3677886747
Short name T185
Test name
Test status
Simulation time 351045818 ps
CPU time 9.89 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:06:38 PM PST 24
Peak memory 212872 kb
Host smart-19c5694a-3b5d-4f25-9429-2ccb80ae102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677886747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.3677886747
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.145527087
Short name T393
Test name
Test status
Simulation time 16850935501 ps
CPU time 73.29 seconds
Started Jan 10 01:05:05 PM PST 24
Finished Jan 10 01:07:59 PM PST 24
Peak memory 216752 kb
Host smart-ca5799f2-836e-4bf4-b79e-7162a3a57762
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145527087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.145527087
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2475420723
Short name T326
Test name
Test status
Simulation time 1869747553 ps
CPU time 7.28 seconds
Started Jan 10 01:05:11 PM PST 24
Finished Jan 10 01:06:58 PM PST 24
Peak memory 210912 kb
Host smart-a6a95ee9-550f-414e-8f58-c382ed30c279
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475420723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2475420723
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1894623293
Short name T14
Test name
Test status
Simulation time 50730374244 ps
CPU time 155.21 seconds
Started Jan 10 01:05:10 PM PST 24
Finished Jan 10 01:09:14 PM PST 24
Peak memory 240196 kb
Host smart-d523a159-df0e-4437-b021-d365b15d116e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894623293 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.1894623293
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.477653578
Short name T13
Test name
Test status
Simulation time 168351272 ps
CPU time 9.68 seconds
Started Jan 10 01:05:10 PM PST 24
Finished Jan 10 01:06:58 PM PST 24
Peak memory 210968 kb
Host smart-5ed8370a-c712-459e-abd2-e0462ab75569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477653578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.477653578
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.4067765961
Short name T331
Test name
Test status
Simulation time 10560864277 ps
CPU time 26.85 seconds
Started Jan 10 01:05:30 PM PST 24
Finished Jan 10 01:07:45 PM PST 24
Peak memory 213096 kb
Host smart-49668fae-c8be-49dd-911a-a5b47c82dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067765961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.4067765961
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.1903956396
Short name T108
Test name
Test status
Simulation time 3568001965 ps
CPU time 19.44 seconds
Started Jan 10 01:05:00 PM PST 24
Finished Jan 10 01:06:51 PM PST 24
Peak memory 211080 kb
Host smart-44bf82e2-92a7-4336-88bf-1a37cae29631
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903956396 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.1903956396
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2970398
Short name T6
Test name
Test status
Simulation time 271156427139 ps
CPU time 1439.15 seconds
Started Jan 10 01:05:11 PM PST 24
Finished Jan 10 01:30:50 PM PST 24
Peak memory 235576 kb
Host smart-69e200ed-1331-43cd-8b31-224ed9a5e0b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970398 -assert nopost
proc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2970398
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.586960686
Short name T252
Test name
Test status
Simulation time 896590445 ps
CPU time 9.6 seconds
Started Jan 10 01:05:12 PM PST 24
Finished Jan 10 01:06:47 PM PST 24
Peak memory 210892 kb
Host smart-963e9ec6-42fd-4acb-98b0-c335bb23325c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586960686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.586960686
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.1303534279
Short name T414
Test name
Test status
Simulation time 1452098671 ps
CPU time 87.27 seconds
Started Jan 10 01:05:03 PM PST 24
Finished Jan 10 01:08:07 PM PST 24
Peak memory 228148 kb
Host smart-7bcc9f69-8d3d-4f65-8144-619639044a07
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303534279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.1303534279
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1485133997
Short name T183
Test name
Test status
Simulation time 12340973090 ps
CPU time 19.53 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:06:53 PM PST 24
Peak memory 210916 kb
Host smart-d3eb11d7-23df-4ec7-a107-c7556f873102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485133997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1485133997
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.3728686227
Short name T418
Test name
Test status
Simulation time 826774890 ps
CPU time 7.04 seconds
Started Jan 10 01:04:57 PM PST 24
Finished Jan 10 01:06:30 PM PST 24
Peak memory 210756 kb
Host smart-353c311b-907d-41ac-9c11-00ec35a04386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3728686227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.3728686227
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.866532453
Short name T55
Test name
Test status
Simulation time 1703063808 ps
CPU time 13.84 seconds
Started Jan 10 01:05:07 PM PST 24
Finished Jan 10 01:06:51 PM PST 24
Peak memory 212396 kb
Host smart-46b64bcc-4802-4b60-af7b-cee013f7451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866532453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.866532453
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.618766463
Short name T236
Test name
Test status
Simulation time 406104645 ps
CPU time 24.65 seconds
Started Jan 10 01:05:31 PM PST 24
Finished Jan 10 01:07:20 PM PST 24
Peak memory 216256 kb
Host smart-f759412a-e1f9-4490-a029-0362b0779274
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618766463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.rom_ctrl_stress_all.618766463
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.1882670887
Short name T194
Test name
Test status
Simulation time 53911116623 ps
CPU time 5924 seconds
Started Jan 10 01:05:15 PM PST 24
Finished Jan 10 02:45:38 PM PST 24
Peak memory 235596 kb
Host smart-f6ed5e44-2d49-446b-baf7-27cb8bd0fa02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882670887 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.1882670887
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.3018315838
Short name T332
Test name
Test status
Simulation time 1535150126 ps
CPU time 12.99 seconds
Started Jan 10 01:05:39 PM PST 24
Finished Jan 10 01:07:20 PM PST 24
Peak memory 210872 kb
Host smart-a1ae3923-1709-4fae-a8cb-8825f638cd6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018315838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.3018315838
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2947206892
Short name T210
Test name
Test status
Simulation time 15971433573 ps
CPU time 229.07 seconds
Started Jan 10 01:05:01 PM PST 24
Finished Jan 10 01:10:41 PM PST 24
Peak memory 232276 kb
Host smart-4452c1a2-f013-4454-93fd-4ed898c52325
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947206892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2947206892
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.121031816
Short name T270
Test name
Test status
Simulation time 696289803 ps
CPU time 9.64 seconds
Started Jan 10 01:05:12 PM PST 24
Finished Jan 10 01:06:48 PM PST 24
Peak memory 211964 kb
Host smart-f7753fc6-ead7-470a-9b72-5eae78e6b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121031816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.121031816
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3260712189
Short name T192
Test name
Test status
Simulation time 4969179908 ps
CPU time 13.14 seconds
Started Jan 10 01:05:05 PM PST 24
Finished Jan 10 01:06:50 PM PST 24
Peak memory 210812 kb
Host smart-4133aa07-3bb4-4dd5-812c-e58076efb183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260712189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3260712189
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.2239836983
Short name T230
Test name
Test status
Simulation time 17097150251 ps
CPU time 46.29 seconds
Started Jan 10 01:05:10 PM PST 24
Finished Jan 10 01:07:26 PM PST 24
Peak memory 216444 kb
Host smart-6e5f2d2a-638e-497d-9b5f-f1a2d9151634
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239836983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.2239836983
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3354177546
Short name T345
Test name
Test status
Simulation time 186069718021 ps
CPU time 4784.37 seconds
Started Jan 10 01:04:56 PM PST 24
Finished Jan 10 02:26:22 PM PST 24
Peak memory 235884 kb
Host smart-bcd7e288-f78d-4276-b715-aed004bd7704
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354177546 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3354177546
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.1808149814
Short name T202
Test name
Test status
Simulation time 7283309141 ps
CPU time 14.51 seconds
Started Jan 10 01:05:02 PM PST 24
Finished Jan 10 01:06:43 PM PST 24
Peak memory 210980 kb
Host smart-a40b125b-aec4-4500-92d4-71655997df22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808149814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1808149814
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2932377668
Short name T165
Test name
Test status
Simulation time 6752733344 ps
CPU time 93.47 seconds
Started Jan 10 01:05:23 PM PST 24
Finished Jan 10 01:08:24 PM PST 24
Peak memory 235812 kb
Host smart-7641a581-700d-4af3-b31b-eeeab17835d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932377668 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2932377668
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.207052657
Short name T201
Test name
Test status
Simulation time 3697485282 ps
CPU time 31.55 seconds
Started Jan 10 01:05:05 PM PST 24
Finished Jan 10 01:07:03 PM PST 24
Peak memory 210992 kb
Host smart-b623c2bc-be45-46eb-bc0d-24dd0c225d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207052657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.207052657
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3585298051
Short name T4
Test name
Test status
Simulation time 96803345 ps
CPU time 5.72 seconds
Started Jan 10 01:05:19 PM PST 24
Finished Jan 10 01:06:53 PM PST 24
Peak memory 210892 kb
Host smart-306702c7-4b37-43b5-b56d-786fce367d59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3585298051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3585298051
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.1755775344
Short name T231
Test name
Test status
Simulation time 736992335 ps
CPU time 10.62 seconds
Started Jan 10 01:05:12 PM PST 24
Finished Jan 10 01:06:48 PM PST 24
Peak memory 212720 kb
Host smart-333b5a7c-e883-4810-af33-3ea9e118d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755775344 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.1755775344
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2962804783
Short name T377
Test name
Test status
Simulation time 28728392415 ps
CPU time 46.82 seconds
Started Jan 10 01:05:10 PM PST 24
Finished Jan 10 01:07:25 PM PST 24
Peak memory 215844 kb
Host smart-0e357210-da4c-4c47-8780-f5cbb1033870
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962804783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2962804783
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2144695986
Short name T284
Test name
Test status
Simulation time 16838088595 ps
CPU time 13.65 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 210992 kb
Host smart-5c4ec3fe-4c07-4cea-a220-c4ef28f9f0ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144695986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2144695986
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.2756269901
Short name T19
Test name
Test status
Simulation time 42293795025 ps
CPU time 192.47 seconds
Started Jan 10 01:04:32 PM PST 24
Finished Jan 10 01:09:02 PM PST 24
Peak memory 236428 kb
Host smart-6b2c0298-a51c-4673-aa46-1447646b0d8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756269901 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.2756269901
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3962806755
Short name T168
Test name
Test status
Simulation time 3125467485 ps
CPU time 14.33 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:47 PM PST 24
Peak memory 211172 kb
Host smart-3ee9798c-dd97-42db-985b-4220a92e5768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962806755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3962806755
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3000061215
Short name T225
Test name
Test status
Simulation time 667896546 ps
CPU time 9.36 seconds
Started Jan 10 01:03:54 PM PST 24
Finished Jan 10 01:05:24 PM PST 24
Peak memory 210928 kb
Host smart-9540c622-c245-45d9-8444-6a3c7c22ed10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000061215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3000061215
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2315963991
Short name T213
Test name
Test status
Simulation time 12448288009 ps
CPU time 34.97 seconds
Started Jan 10 01:03:55 PM PST 24
Finished Jan 10 01:06:07 PM PST 24
Peak memory 213676 kb
Host smart-9c595af6-5bae-42cb-9142-e72b4cdbe73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315963991 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2315963991
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.674087321
Short name T266
Test name
Test status
Simulation time 848437676 ps
CPU time 8.38 seconds
Started Jan 10 01:04:02 PM PST 24
Finished Jan 10 01:05:33 PM PST 24
Peak memory 210636 kb
Host smart-091024da-b8c5-4eca-8faa-01891a2c63d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674087321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.rom_ctrl_stress_all.674087321
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.784009535
Short name T321
Test name
Test status
Simulation time 163063350070 ps
CPU time 1769.1 seconds
Started Jan 10 01:03:52 PM PST 24
Finished Jan 10 01:34:41 PM PST 24
Peak memory 235564 kb
Host smart-bc98a738-2b7b-4793-8a33-e9cd65ffcf1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784009535 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.784009535
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.3928938473
Short name T380
Test name
Test status
Simulation time 88870462 ps
CPU time 4.47 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:28 PM PST 24
Peak memory 210912 kb
Host smart-0e408d2e-395d-4093-9505-63dc34a0ffda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928938473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.3928938473
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1112782227
Short name T325
Test name
Test status
Simulation time 157990275397 ps
CPU time 433.94 seconds
Started Jan 10 01:03:59 PM PST 24
Finished Jan 10 01:12:36 PM PST 24
Peak memory 237404 kb
Host smart-07f6bb5e-3ac6-4724-8b7a-8369863da141
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112782227 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1112782227
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3649418744
Short name T412
Test name
Test status
Simulation time 1471739941 ps
CPU time 16.12 seconds
Started Jan 10 01:03:57 PM PST 24
Finished Jan 10 01:05:30 PM PST 24
Peak memory 211056 kb
Host smart-a04bebca-c53b-495f-b307-eff3309149ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649418744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3649418744
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.965478416
Short name T318
Test name
Test status
Simulation time 1482378934 ps
CPU time 13.71 seconds
Started Jan 10 01:03:52 PM PST 24
Finished Jan 10 01:05:20 PM PST 24
Peak memory 210908 kb
Host smart-22f75388-fdef-4a7e-a675-eb125dbde2f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965478416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.965478416
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.3332282249
Short name T239
Test name
Test status
Simulation time 866109784 ps
CPU time 13.53 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:37 PM PST 24
Peak memory 212636 kb
Host smart-83019dcb-e658-484e-b445-ab2b554258a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332282249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.3332282249
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3956378338
Short name T340
Test name
Test status
Simulation time 685519969 ps
CPU time 34.6 seconds
Started Jan 10 01:03:57 PM PST 24
Finished Jan 10 01:05:49 PM PST 24
Peak memory 214736 kb
Host smart-8c9a0486-f1a7-4665-80ec-a564f034a624
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956378338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3956378338
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.1134324377
Short name T143
Test name
Test status
Simulation time 194645956378 ps
CPU time 1434.05 seconds
Started Jan 10 01:04:00 PM PST 24
Finished Jan 10 01:29:16 PM PST 24
Peak memory 229732 kb
Host smart-47861a59-45d6-480c-88df-21eea1e68e6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134324377 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.1134324377
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.923666598
Short name T246
Test name
Test status
Simulation time 333246564 ps
CPU time 4.35 seconds
Started Jan 10 01:04:03 PM PST 24
Finished Jan 10 01:05:51 PM PST 24
Peak memory 210956 kb
Host smart-b41027f2-3201-430d-bc67-b7a8a77d970e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923666598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.923666598
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.748846519
Short name T370
Test name
Test status
Simulation time 176539868353 ps
CPU time 474.46 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:13:22 PM PST 24
Peak memory 237400 kb
Host smart-d308a051-2602-4e52-ab7c-cb25ef3b23ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748846519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_co
rrupt_sig_fatal_chk.748846519
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2106648899
Short name T381
Test name
Test status
Simulation time 581430416 ps
CPU time 14.37 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:47 PM PST 24
Peak memory 210968 kb
Host smart-0aff41f4-0e4a-4926-88e9-2ccbfefbdd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106648899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2106648899
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.1759563052
Short name T338
Test name
Test status
Simulation time 2156836056 ps
CPU time 16.34 seconds
Started Jan 10 01:04:04 PM PST 24
Finished Jan 10 01:05:49 PM PST 24
Peak memory 210920 kb
Host smart-3500343e-4487-4d7b-8f2a-6c2b6ac9a223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1759563052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.1759563052
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3614261137
Short name T220
Test name
Test status
Simulation time 15452228076 ps
CPU time 32.98 seconds
Started Jan 10 01:03:57 PM PST 24
Finished Jan 10 01:05:51 PM PST 24
Peak memory 212384 kb
Host smart-ccedcdaa-3be4-4455-adce-41d12a456add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614261137 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3614261137
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3459829294
Short name T228
Test name
Test status
Simulation time 10070657239 ps
CPU time 21.84 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:38 PM PST 24
Peak memory 210844 kb
Host smart-775d4fbf-4117-4d1b-877a-bbc66bcfeeeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459829294 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3459829294
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3653743922
Short name T184
Test name
Test status
Simulation time 49451898427 ps
CPU time 4121.04 seconds
Started Jan 10 01:03:52 PM PST 24
Finished Jan 10 02:13:55 PM PST 24
Peak memory 235580 kb
Host smart-3972867c-be56-4c01-9680-cfad1dcb5dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653743922 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.3653743922
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.1825177766
Short name T41
Test name
Test status
Simulation time 943103294 ps
CPU time 6.09 seconds
Started Jan 10 01:04:11 PM PST 24
Finished Jan 10 01:05:38 PM PST 24
Peak memory 210972 kb
Host smart-e9b4a584-cb4d-4a13-9ab4-feb37d1739f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825177766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.1825177766
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3655800566
Short name T175
Test name
Test status
Simulation time 110489757705 ps
CPU time 279.37 seconds
Started Jan 10 01:03:55 PM PST 24
Finished Jan 10 01:09:54 PM PST 24
Peak memory 227160 kb
Host smart-b5f0a555-a902-4c74-bf5a-9f5fe0f60b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655800566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3655800566
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1036778095
Short name T401
Test name
Test status
Simulation time 3026128825 ps
CPU time 26.89 seconds
Started Jan 10 01:04:09 PM PST 24
Finished Jan 10 01:06:03 PM PST 24
Peak memory 211024 kb
Host smart-4db3433a-3b4c-4b02-91bb-714f191ca0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036778095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1036778095
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.251321131
Short name T164
Test name
Test status
Simulation time 2420757141 ps
CPU time 9.55 seconds
Started Jan 10 01:04:05 PM PST 24
Finished Jan 10 01:05:37 PM PST 24
Peak memory 210924 kb
Host smart-0dce4825-8e7c-4774-80fa-926331133e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251321131 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.251321131
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.1395364682
Short name T278
Test name
Test status
Simulation time 10972344487 ps
CPU time 31.22 seconds
Started Jan 10 01:03:58 PM PST 24
Finished Jan 10 01:05:47 PM PST 24
Peak memory 213228 kb
Host smart-61437f3d-3ccf-489b-8f69-7912dafa9599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395364682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.1395364682
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.484829739
Short name T346
Test name
Test status
Simulation time 2633048117 ps
CPU time 16.17 seconds
Started Jan 10 01:04:06 PM PST 24
Finished Jan 10 01:05:44 PM PST 24
Peak memory 212884 kb
Host smart-0112b7f9-a0bb-415a-af71-ec3f54ba13b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484829739 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.484829739
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.51879
Short name T344
Test name
Test status
Simulation time 41889888108 ps
CPU time 1802.38 seconds
Started Jan 10 01:04:03 PM PST 24
Finished Jan 10 01:35:30 PM PST 24
Peak memory 235336 kb
Host smart-58401003-54a8-48dc-a2b6-73f15daa6312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51879 -assert nopostpr
oc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.51879
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.4247505989
Short name T403
Test name
Test status
Simulation time 4739139775 ps
CPU time 10.47 seconds
Started Jan 10 01:04:47 PM PST 24
Finished Jan 10 01:06:38 PM PST 24
Peak memory 211008 kb
Host smart-ed92cb4e-4c7e-4e99-b371-f15596d6c222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247505989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.4247505989
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1030834390
Short name T395
Test name
Test status
Simulation time 8544195891 ps
CPU time 33.13 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:06:14 PM PST 24
Peak memory 211696 kb
Host smart-a51f0654-87b6-49e2-8438-d9ba84047664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030834390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1030834390
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.4265087335
Short name T149
Test name
Test status
Simulation time 5144672381 ps
CPU time 14.45 seconds
Started Jan 10 01:04:07 PM PST 24
Finished Jan 10 01:05:44 PM PST 24
Peak memory 210924 kb
Host smart-461fb000-57b0-4320-92f4-6d6caadccf84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265087335 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.4265087335
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1757982800
Short name T207
Test name
Test status
Simulation time 334671998 ps
CPU time 10.27 seconds
Started Jan 10 01:04:13 PM PST 24
Finished Jan 10 01:05:42 PM PST 24
Peak memory 212320 kb
Host smart-4282466a-e6f8-420b-a8a2-8a8ed6f86286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757982800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1757982800
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.2182025311
Short name T312
Test name
Test status
Simulation time 4353388944 ps
CPU time 51.66 seconds
Started Jan 10 01:03:59 PM PST 24
Finished Jan 10 01:06:09 PM PST 24
Peak memory 216656 kb
Host smart-9c9630e6-4b96-425f-a217-e2032a113866
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182025311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.2182025311
Directory /workspace/9.rom_ctrl_stress_all/latest
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