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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 97.11 92.83 97.88 100.00 98.69 98.04 98.14


Total test records in report: 481
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T268 /workspace/coverage/default/41.rom_ctrl_alert_test.3502465963 Jan 14 01:21:13 PM PST 24 Jan 14 01:21:30 PM PST 24 1967964092 ps
T269 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3720221010 Jan 14 01:20:20 PM PST 24 Jan 14 01:22:23 PM PST 24 1981780024 ps
T270 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1372884452 Jan 14 01:20:23 PM PST 24 Jan 14 01:20:41 PM PST 24 2437534300 ps
T271 /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1279236541 Jan 14 01:20:32 PM PST 24 Jan 14 01:25:31 PM PST 24 166865352484 ps
T272 /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1458704432 Jan 14 01:20:57 PM PST 24 Jan 14 01:21:04 PM PST 24 385416867 ps
T273 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3189429310 Jan 14 01:20:17 PM PST 24 Jan 14 01:28:10 PM PST 24 221702100691 ps
T274 /workspace/coverage/default/33.rom_ctrl_smoke.451957014 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:10 PM PST 24 187417011 ps
T275 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1875670688 Jan 14 01:20:35 PM PST 24 Jan 14 01:20:57 PM PST 24 1891834943 ps
T276 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2777563260 Jan 14 01:20:44 PM PST 24 Jan 14 02:08:10 PM PST 24 68533569666 ps
T277 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.737136355 Jan 14 01:20:16 PM PST 24 Jan 14 01:22:04 PM PST 24 5986746705 ps
T278 /workspace/coverage/default/30.rom_ctrl_stress_all.4011146582 Jan 14 01:20:54 PM PST 24 Jan 14 01:22:03 PM PST 24 29657957215 ps
T279 /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1152517163 Jan 14 01:21:15 PM PST 24 Jan 14 01:21:25 PM PST 24 544133635 ps
T280 /workspace/coverage/default/35.rom_ctrl_stress_all.3166942105 Jan 14 01:20:56 PM PST 24 Jan 14 01:22:08 PM PST 24 13438181911 ps
T281 /workspace/coverage/default/48.rom_ctrl_stress_all.3450547849 Jan 14 01:21:15 PM PST 24 Jan 14 01:21:35 PM PST 24 7641976851 ps
T282 /workspace/coverage/default/34.rom_ctrl_stress_all.2039824238 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:58 PM PST 24 42413390568 ps
T283 /workspace/coverage/default/23.rom_ctrl_alert_test.1658017118 Jan 14 01:20:52 PM PST 24 Jan 14 01:21:06 PM PST 24 6194618856 ps
T284 /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1301090664 Jan 14 01:20:56 PM PST 24 Jan 14 01:21:23 PM PST 24 18779912218 ps
T285 /workspace/coverage/default/47.rom_ctrl_stress_all.3177709288 Jan 14 01:21:12 PM PST 24 Jan 14 01:21:24 PM PST 24 211245376 ps
T286 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3423374827 Jan 14 01:20:12 PM PST 24 Jan 14 01:20:25 PM PST 24 101457638 ps
T287 /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.567161801 Jan 14 01:20:12 PM PST 24 Jan 14 01:20:27 PM PST 24 1671011999 ps
T288 /workspace/coverage/default/43.rom_ctrl_stress_all.761194726 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:52 PM PST 24 7116186146 ps
T289 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2347281895 Jan 14 01:20:29 PM PST 24 Jan 14 01:26:05 PM PST 24 34097774412 ps
T290 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.941082094 Jan 14 01:20:28 PM PST 24 Jan 14 01:21:02 PM PST 24 3757568056 ps
T291 /workspace/coverage/default/6.rom_ctrl_stress_all.3674501650 Jan 14 01:20:12 PM PST 24 Jan 14 01:20:37 PM PST 24 1411556561 ps
T292 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2270659694 Jan 14 01:20:34 PM PST 24 Jan 14 01:20:45 PM PST 24 333688207 ps
T293 /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.733228881 Jan 14 01:20:42 PM PST 24 Jan 14 01:25:58 PM PST 24 28968027317 ps
T294 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3355609778 Jan 14 01:21:11 PM PST 24 Jan 14 02:22:49 PM PST 24 138831306184 ps
T295 /workspace/coverage/default/21.rom_ctrl_stress_all.3172751441 Jan 14 01:20:34 PM PST 24 Jan 14 01:21:12 PM PST 24 9557445548 ps
T296 /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.576312005 Jan 14 01:20:38 PM PST 24 Jan 14 01:20:51 PM PST 24 4874910944 ps
T297 /workspace/coverage/default/5.rom_ctrl_smoke.2055966219 Jan 14 01:20:10 PM PST 24 Jan 14 01:20:51 PM PST 24 10479759112 ps
T111 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2092094051 Jan 14 01:21:04 PM PST 24 Jan 14 01:21:13 PM PST 24 598222856 ps
T298 /workspace/coverage/default/13.rom_ctrl_alert_test.3277050284 Jan 14 01:20:22 PM PST 24 Jan 14 01:20:29 PM PST 24 87179850 ps
T299 /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1479312940 Jan 14 01:21:06 PM PST 24 Jan 14 01:24:11 PM PST 24 11219179634 ps
T300 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2581823081 Jan 14 01:20:17 PM PST 24 Jan 14 01:20:41 PM PST 24 1405456445 ps
T301 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2536147115 Jan 14 01:20:08 PM PST 24 Jan 14 01:20:45 PM PST 24 11703668381 ps
T302 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1383561977 Jan 14 01:20:09 PM PST 24 Jan 14 01:20:24 PM PST 24 181058503 ps
T303 /workspace/coverage/default/21.rom_ctrl_alert_test.1421518919 Jan 14 01:20:33 PM PST 24 Jan 14 01:20:46 PM PST 24 4541075439 ps
T43 /workspace/coverage/default/1.rom_ctrl_sec_cm.2165593806 Jan 14 01:20:05 PM PST 24 Jan 14 01:22:03 PM PST 24 189215726 ps
T304 /workspace/coverage/default/12.rom_ctrl_stress_all.1941685190 Jan 14 01:20:22 PM PST 24 Jan 14 01:22:45 PM PST 24 23701666634 ps
T305 /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4071323088 Jan 14 01:21:10 PM PST 24 Jan 14 01:21:21 PM PST 24 3933351596 ps
T306 /workspace/coverage/default/40.rom_ctrl_alert_test.971762246 Jan 14 01:20:59 PM PST 24 Jan 14 01:21:11 PM PST 24 4597916946 ps
T307 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2932195538 Jan 14 01:21:00 PM PST 24 Jan 14 01:21:20 PM PST 24 2733649304 ps
T308 /workspace/coverage/default/17.rom_ctrl_smoke.3091686484 Jan 14 01:20:31 PM PST 24 Jan 14 01:20:44 PM PST 24 281300370 ps
T309 /workspace/coverage/default/42.rom_ctrl_alert_test.4000036968 Jan 14 01:21:00 PM PST 24 Jan 14 01:21:16 PM PST 24 17135577154 ps
T310 /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2051299358 Jan 14 01:21:06 PM PST 24 Jan 14 01:21:23 PM PST 24 1028709638 ps
T311 /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3291146195 Jan 14 01:20:57 PM PST 24 Jan 14 01:22:45 PM PST 24 1841244217 ps
T312 /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1937778090 Jan 14 01:20:35 PM PST 24 Jan 14 01:52:40 PM PST 24 60390200798 ps
T313 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2777264114 Jan 14 01:21:01 PM PST 24 Jan 14 01:21:15 PM PST 24 5848294673 ps
T314 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1870070290 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:13 PM PST 24 1505514780 ps
T315 /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1156835108 Jan 14 01:20:08 PM PST 24 Jan 14 01:20:41 PM PST 24 9910912686 ps
T316 /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4048757577 Jan 14 01:20:45 PM PST 24 Jan 14 01:20:57 PM PST 24 1047616424 ps
T317 /workspace/coverage/default/46.rom_ctrl_smoke.3660242646 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:16 PM PST 24 806128287 ps
T318 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.562063893 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:23 PM PST 24 9261103298 ps
T319 /workspace/coverage/default/37.rom_ctrl_alert_test.2339252350 Jan 14 01:21:02 PM PST 24 Jan 14 01:21:08 PM PST 24 594702515 ps
T320 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3438291589 Jan 14 01:20:45 PM PST 24 Jan 14 01:25:45 PM PST 24 132343274184 ps
T321 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3514208597 Jan 14 01:20:08 PM PST 24 Jan 14 01:20:51 PM PST 24 7856866250 ps
T18 /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1080969171 Jan 14 01:21:09 PM PST 24 Jan 14 02:54:16 PM PST 24 50089883303 ps
T322 /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1239365415 Jan 14 01:20:51 PM PST 24 Jan 14 01:23:27 PM PST 24 5168417697 ps
T323 /workspace/coverage/default/6.rom_ctrl_alert_test.1881315244 Jan 14 01:20:17 PM PST 24 Jan 14 01:20:37 PM PST 24 1898445732 ps
T324 /workspace/coverage/default/7.rom_ctrl_smoke.3447514771 Jan 14 01:20:11 PM PST 24 Jan 14 01:20:40 PM PST 24 1851831450 ps
T325 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3419319787 Jan 14 01:20:20 PM PST 24 Jan 14 01:20:40 PM PST 24 2006840344 ps
T326 /workspace/coverage/default/43.rom_ctrl_smoke.2786408704 Jan 14 01:21:06 PM PST 24 Jan 14 01:21:40 PM PST 24 2771492880 ps
T327 /workspace/coverage/default/39.rom_ctrl_alert_test.3771833068 Jan 14 01:20:56 PM PST 24 Jan 14 01:21:07 PM PST 24 897425106 ps
T328 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3163662256 Jan 14 01:20:31 PM PST 24 Jan 14 01:20:48 PM PST 24 3315923291 ps
T329 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.887007157 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:49 PM PST 24 15212175217 ps
T330 /workspace/coverage/default/7.rom_ctrl_alert_test.4281892540 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:40 PM PST 24 1638945106 ps
T331 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.115026328 Jan 14 01:21:12 PM PST 24 Jan 14 03:14:12 PM PST 24 51267392336 ps
T332 /workspace/coverage/default/44.rom_ctrl_stress_all.1054907402 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:18 PM PST 24 1884199618 ps
T52 /workspace/coverage/default/2.rom_ctrl_sec_cm.4028219026 Jan 14 01:20:09 PM PST 24 Jan 14 01:21:26 PM PST 24 1863442561 ps
T333 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3386281818 Jan 14 01:20:07 PM PST 24 Jan 14 01:20:23 PM PST 24 5915042492 ps
T53 /workspace/coverage/default/0.rom_ctrl_sec_cm.1488577427 Jan 14 01:20:04 PM PST 24 Jan 14 01:21:19 PM PST 24 7606970050 ps
T334 /workspace/coverage/default/23.rom_ctrl_smoke.1067755126 Jan 14 01:20:38 PM PST 24 Jan 14 01:21:06 PM PST 24 2140624067 ps
T335 /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3772373356 Jan 14 01:21:10 PM PST 24 Jan 14 01:33:16 PM PST 24 65633021252 ps
T336 /workspace/coverage/default/14.rom_ctrl_alert_test.1359995560 Jan 14 01:20:22 PM PST 24 Jan 14 01:20:40 PM PST 24 1911800758 ps
T337 /workspace/coverage/default/19.rom_ctrl_smoke.3154391606 Jan 14 01:20:34 PM PST 24 Jan 14 01:21:04 PM PST 24 6462086272 ps
T338 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1056592152 Jan 14 01:20:57 PM PST 24 Jan 14 01:21:17 PM PST 24 4393846321 ps
T339 /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3920378360 Jan 14 01:20:51 PM PST 24 Jan 14 01:27:14 PM PST 24 55340259373 ps
T340 /workspace/coverage/default/20.rom_ctrl_alert_test.1991947710 Jan 14 01:20:36 PM PST 24 Jan 14 01:20:41 PM PST 24 171731626 ps
T341 /workspace/coverage/default/49.rom_ctrl_alert_test.127454349 Jan 14 01:21:17 PM PST 24 Jan 14 01:21:31 PM PST 24 28218174594 ps
T342 /workspace/coverage/default/38.rom_ctrl_stress_all.3444475197 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:56 PM PST 24 5590451500 ps
T343 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4153766981 Jan 14 01:20:58 PM PST 24 Jan 14 02:00:11 PM PST 24 125017632600 ps
T116 /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.707487350 Jan 14 01:21:04 PM PST 24 Jan 14 01:42:12 PM PST 24 24509906610 ps
T344 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2379028015 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:16 PM PST 24 693040633 ps
T345 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3054637018 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:32 PM PST 24 97986389 ps
T346 /workspace/coverage/default/16.rom_ctrl_alert_test.1781272027 Jan 14 01:20:32 PM PST 24 Jan 14 01:20:39 PM PST 24 343163835 ps
T117 /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2796941310 Jan 14 01:20:45 PM PST 24 Jan 14 01:45:03 PM PST 24 39011511218 ps
T347 /workspace/coverage/default/28.rom_ctrl_stress_all.1223231579 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:38 PM PST 24 3498530022 ps
T348 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1102603537 Jan 14 01:21:15 PM PST 24 Jan 14 01:25:14 PM PST 24 25214612501 ps
T349 /workspace/coverage/default/12.rom_ctrl_alert_test.257419266 Jan 14 01:20:22 PM PST 24 Jan 14 01:20:38 PM PST 24 5755304302 ps
T350 /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1665924400 Jan 14 01:20:57 PM PST 24 Jan 14 01:21:08 PM PST 24 343075121 ps
T19 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.299150645 Jan 14 01:20:26 PM PST 24 Jan 14 01:53:00 PM PST 24 46210726267 ps
T351 /workspace/coverage/default/27.rom_ctrl_alert_test.2082834781 Jan 14 01:21:00 PM PST 24 Jan 14 01:21:05 PM PST 24 594022361 ps
T352 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2373454165 Jan 14 01:20:46 PM PST 24 Jan 14 01:21:18 PM PST 24 37719874230 ps
T353 /workspace/coverage/default/12.rom_ctrl_smoke.2070480297 Jan 14 01:20:21 PM PST 24 Jan 14 01:20:35 PM PST 24 1443390079 ps
T354 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4073832565 Jan 14 01:20:31 PM PST 24 Jan 14 01:25:05 PM PST 24 74335790943 ps
T355 /workspace/coverage/default/24.rom_ctrl_smoke.3694724173 Jan 14 01:20:53 PM PST 24 Jan 14 01:21:21 PM PST 24 3131648709 ps
T356 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1340408184 Jan 14 01:20:53 PM PST 24 Jan 14 01:25:17 PM PST 24 114705597121 ps
T357 /workspace/coverage/default/2.rom_ctrl_stress_all.1705413939 Jan 14 01:20:07 PM PST 24 Jan 14 01:20:50 PM PST 24 9296070701 ps
T358 /workspace/coverage/default/8.rom_ctrl_stress_all.3880386470 Jan 14 01:20:04 PM PST 24 Jan 14 01:20:25 PM PST 24 302356593 ps
T359 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2248897552 Jan 14 01:20:48 PM PST 24 Jan 14 01:20:58 PM PST 24 678694229 ps
T360 /workspace/coverage/default/15.rom_ctrl_stress_all.892576225 Jan 14 01:20:33 PM PST 24 Jan 14 01:21:16 PM PST 24 2231430690 ps
T361 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.433915734 Jan 14 01:20:24 PM PST 24 Jan 14 01:31:25 PM PST 24 262940668689 ps
T362 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2761914291 Jan 14 01:21:07 PM PST 24 Jan 14 01:25:46 PM PST 24 259925748885 ps
T363 /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3057473613 Jan 14 01:20:20 PM PST 24 Jan 14 01:27:35 PM PST 24 122406708220 ps
T364 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.411092506 Jan 14 01:20:53 PM PST 24 Jan 14 01:21:10 PM PST 24 3935980292 ps
T365 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2645158802 Jan 14 01:20:21 PM PST 24 Jan 14 01:20:41 PM PST 24 7870483980 ps
T366 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3094945866 Jan 14 01:21:10 PM PST 24 Jan 14 01:21:37 PM PST 24 2813793823 ps
T367 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.423144942 Jan 14 01:21:05 PM PST 24 Jan 14 01:21:21 PM PST 24 1044949333 ps
T368 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2669903048 Jan 14 01:21:05 PM PST 24 Jan 14 01:28:00 PM PST 24 36919553718 ps
T369 /workspace/coverage/default/37.rom_ctrl_stress_all.1136024106 Jan 14 01:20:53 PM PST 24 Jan 14 01:21:51 PM PST 24 5870095582 ps
T370 /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1424083093 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:15 PM PST 24 1780968030 ps
T371 /workspace/coverage/default/34.rom_ctrl_alert_test.1938163160 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:05 PM PST 24 688196191 ps
T372 /workspace/coverage/default/34.rom_ctrl_smoke.4287334154 Jan 14 01:20:46 PM PST 24 Jan 14 01:21:26 PM PST 24 45031926559 ps
T373 /workspace/coverage/default/20.rom_ctrl_smoke.328509898 Jan 14 01:20:42 PM PST 24 Jan 14 01:20:53 PM PST 24 743786596 ps
T374 /workspace/coverage/default/25.rom_ctrl_smoke.3486647559 Jan 14 01:20:54 PM PST 24 Jan 14 01:21:29 PM PST 24 6412669614 ps
T375 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3418444809 Jan 14 01:20:28 PM PST 24 Jan 14 01:27:55 PM PST 24 23499474154 ps
T376 /workspace/coverage/default/24.rom_ctrl_stress_all.2630257680 Jan 14 01:20:41 PM PST 24 Jan 14 01:21:34 PM PST 24 101366498899 ps
T377 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.776606637 Jan 14 01:20:30 PM PST 24 Jan 14 01:23:15 PM PST 24 5149337986 ps
T378 /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3010285681 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:33 PM PST 24 922417588 ps
T379 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2628006346 Jan 14 01:20:13 PM PST 24 Jan 14 01:20:38 PM PST 24 1488521727 ps
T380 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3395191944 Jan 14 01:20:24 PM PST 24 Jan 14 01:26:08 PM PST 24 29528628182 ps
T381 /workspace/coverage/default/11.rom_ctrl_smoke.308788667 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:51 PM PST 24 6784524286 ps
T382 /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.19502601 Jan 14 01:20:54 PM PST 24 Jan 14 01:38:07 PM PST 24 150402419333 ps
T383 /workspace/coverage/default/32.rom_ctrl_stress_all.4224397961 Jan 14 01:20:48 PM PST 24 Jan 14 01:21:10 PM PST 24 314623746 ps
T384 /workspace/coverage/default/35.rom_ctrl_smoke.3208532347 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:33 PM PST 24 8171460100 ps
T385 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.838893176 Jan 14 01:20:54 PM PST 24 Jan 14 02:02:23 PM PST 24 180460973672 ps
T386 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3239292913 Jan 14 01:20:11 PM PST 24 Jan 14 01:21:36 PM PST 24 1270504913 ps
T387 /workspace/coverage/default/16.rom_ctrl_stress_all.3300802055 Jan 14 01:20:31 PM PST 24 Jan 14 01:21:14 PM PST 24 15553250830 ps
T388 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2508789941 Jan 14 01:20:52 PM PST 24 Jan 14 02:04:02 PM PST 24 54227290658 ps
T389 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3312268984 Jan 14 01:20:25 PM PST 24 Jan 14 03:22:08 PM PST 24 47874708359 ps
T390 /workspace/coverage/default/8.rom_ctrl_smoke.3632297527 Jan 14 01:20:24 PM PST 24 Jan 14 01:20:56 PM PST 24 6330595069 ps
T391 /workspace/coverage/default/11.rom_ctrl_stress_all.3332335429 Jan 14 01:20:21 PM PST 24 Jan 14 01:20:32 PM PST 24 522371886 ps
T392 /workspace/coverage/default/22.rom_ctrl_stress_all.6551775 Jan 14 01:20:50 PM PST 24 Jan 14 01:21:26 PM PST 24 629785353 ps
T393 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2296085242 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:26 PM PST 24 6136691815 ps
T394 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4251519630 Jan 14 01:20:09 PM PST 24 Jan 14 01:26:49 PM PST 24 61618555648 ps
T395 /workspace/coverage/default/11.rom_ctrl_alert_test.1989206557 Jan 14 01:20:25 PM PST 24 Jan 14 01:20:42 PM PST 24 18807665947 ps
T396 /workspace/coverage/default/13.rom_ctrl_stress_all.171292714 Jan 14 01:20:21 PM PST 24 Jan 14 01:21:52 PM PST 24 80530709639 ps
T397 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2309729663 Jan 14 01:20:54 PM PST 24 Jan 14 01:22:55 PM PST 24 9246604824 ps
T398 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1864164448 Jan 14 01:20:28 PM PST 24 Jan 14 01:20:39 PM PST 24 363121710 ps
T399 /workspace/coverage/default/25.rom_ctrl_stress_all.79096712 Jan 14 01:20:53 PM PST 24 Jan 14 01:21:09 PM PST 24 2068347773 ps
T400 /workspace/coverage/default/29.rom_ctrl_stress_all.3278281283 Jan 14 01:20:57 PM PST 24 Jan 14 01:21:48 PM PST 24 36429414857 ps
T401 /workspace/coverage/default/6.rom_ctrl_smoke.2562637702 Jan 14 01:20:12 PM PST 24 Jan 14 01:20:55 PM PST 24 3015081929 ps
T402 /workspace/coverage/default/49.rom_ctrl_stress_all.3583257870 Jan 14 01:21:17 PM PST 24 Jan 14 01:21:27 PM PST 24 503911983 ps
T403 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2005994436 Jan 14 01:20:30 PM PST 24 Jan 14 01:20:46 PM PST 24 758160298 ps
T404 /workspace/coverage/default/1.rom_ctrl_stress_all.2368506384 Jan 14 01:20:08 PM PST 24 Jan 14 01:20:29 PM PST 24 421306410 ps
T405 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.589886603 Jan 14 01:20:34 PM PST 24 Jan 14 01:21:05 PM PST 24 3422879359 ps
T406 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2302148806 Jan 14 01:21:02 PM PST 24 Jan 14 01:21:13 PM PST 24 171831798 ps
T407 /workspace/coverage/default/17.rom_ctrl_stress_all.705862284 Jan 14 01:20:29 PM PST 24 Jan 14 01:21:58 PM PST 24 44525642361 ps
T408 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.461441168 Jan 14 01:20:54 PM PST 24 Jan 14 01:24:12 PM PST 24 3059131033 ps
T409 /workspace/coverage/default/20.rom_ctrl_stress_all.4293243979 Jan 14 01:20:35 PM PST 24 Jan 14 01:21:49 PM PST 24 31045089699 ps
T410 /workspace/coverage/default/26.rom_ctrl_alert_test.424247930 Jan 14 01:20:53 PM PST 24 Jan 14 01:21:04 PM PST 24 908406392 ps
T411 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1971544614 Jan 14 01:21:00 PM PST 24 Jan 14 01:21:28 PM PST 24 2900238547 ps
T412 /workspace/coverage/default/28.rom_ctrl_alert_test.4221780747 Jan 14 01:20:58 PM PST 24 Jan 14 01:21:05 PM PST 24 784656401 ps
T413 /workspace/coverage/default/44.rom_ctrl_alert_test.694040427 Jan 14 01:21:13 PM PST 24 Jan 14 01:21:25 PM PST 24 11437901677 ps
T414 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.328229508 Jan 14 01:20:23 PM PST 24 Jan 14 01:43:28 PM PST 24 115829721534 ps
T415 /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3171083747 Jan 14 01:21:13 PM PST 24 Jan 14 01:23:47 PM PST 24 26518282829 ps
T416 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.18640951 Jan 14 01:20:31 PM PST 24 Jan 14 01:23:38 PM PST 24 25145657757 ps
T417 /workspace/coverage/default/45.rom_ctrl_smoke.448139555 Jan 14 01:21:12 PM PST 24 Jan 14 01:21:45 PM PST 24 14860751741 ps
T418 /workspace/coverage/default/31.rom_ctrl_alert_test.2232245262 Jan 14 01:20:55 PM PST 24 Jan 14 01:21:10 PM PST 24 5878947092 ps
T419 /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3508169486 Jan 14 01:20:06 PM PST 24 Jan 14 01:20:22 PM PST 24 3688864449 ps
T420 /workspace/coverage/default/38.rom_ctrl_alert_test.3091337645 Jan 14 01:21:01 PM PST 24 Jan 14 01:21:06 PM PST 24 85688418 ps
T421 /workspace/coverage/default/41.rom_ctrl_stress_all.220619544 Jan 14 01:21:09 PM PST 24 Jan 14 01:21:47 PM PST 24 3880261062 ps
T422 /workspace/coverage/default/4.rom_ctrl_stress_all.219620569 Jan 14 01:20:09 PM PST 24 Jan 14 01:20:41 PM PST 24 16508131609 ps
T423 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4132714168 Jan 14 01:21:06 PM PST 24 Jan 14 01:21:32 PM PST 24 9857478075 ps
T424 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.816973281 Jan 14 01:20:29 PM PST 24 Jan 14 01:20:46 PM PST 24 2018015846 ps
T425 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.837267314 Jan 14 01:20:51 PM PST 24 Jan 14 02:22:48 PM PST 24 97187017744 ps
T426 /workspace/coverage/default/28.rom_ctrl_smoke.2414480312 Jan 14 01:21:00 PM PST 24 Jan 14 01:21:33 PM PST 24 7820642737 ps
T427 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2472565468 Jan 14 01:12:05 PM PST 24 Jan 14 01:12:11 PM PST 24 297528188 ps
T428 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.838755563 Jan 14 01:12:06 PM PST 24 Jan 14 01:12:12 PM PST 24 333809100 ps
T429 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.577933376 Jan 14 01:12:04 PM PST 24 Jan 14 01:12:17 PM PST 24 5119649399 ps
T430 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1864423199 Jan 14 01:12:13 PM PST 24 Jan 14 01:12:19 PM PST 24 94912091 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1979340549 Jan 14 01:12:07 PM PST 24 Jan 14 01:12:21 PM PST 24 1208964608 ps
T432 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3175120255 Jan 14 01:12:36 PM PST 24 Jan 14 01:12:54 PM PST 24 2180167507 ps
T124 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2137360738 Jan 14 01:12:10 PM PST 24 Jan 14 01:13:02 PM PST 24 7318055469 ps
T433 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.340180024 Jan 14 01:12:14 PM PST 24 Jan 14 01:13:01 PM PST 24 1360696936 ps
T434 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1327301624 Jan 14 01:12:03 PM PST 24 Jan 14 01:12:18 PM PST 24 11559161034 ps
T435 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3023415372 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:14 PM PST 24 90877805 ps
T436 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3110604926 Jan 14 01:12:12 PM PST 24 Jan 14 01:12:21 PM PST 24 2746212090 ps
T126 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1953718416 Jan 14 01:12:07 PM PST 24 Jan 14 01:13:00 PM PST 24 14527385178 ps
T437 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1364544487 Jan 14 01:12:15 PM PST 24 Jan 14 01:12:23 PM PST 24 246252070 ps
T438 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1408292741 Jan 14 01:12:24 PM PST 24 Jan 14 01:13:18 PM PST 24 7460246941 ps
T439 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.222362890 Jan 14 01:12:41 PM PST 24 Jan 14 01:14:26 PM PST 24 35891199007 ps
T93 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4062680112 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:29 PM PST 24 1866960370 ps
T95 /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3880651831 Jan 14 01:12:09 PM PST 24 Jan 14 01:15:47 PM PST 24 40688084388 ps
T440 /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3410691321 Jan 14 01:12:30 PM PST 24 Jan 14 01:12:47 PM PST 24 7347785790 ps
T441 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1240967597 Jan 14 01:12:22 PM PST 24 Jan 14 01:12:42 PM PST 24 7506966389 ps
T442 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3180671729 Jan 14 01:12:18 PM PST 24 Jan 14 01:12:40 PM PST 24 1903395143 ps
T96 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2078259475 Jan 14 01:12:32 PM PST 24 Jan 14 01:14:20 PM PST 24 7787153710 ps
T443 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.956161333 Jan 14 01:12:29 PM PST 24 Jan 14 01:12:36 PM PST 24 308077496 ps
T444 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.66988950 Jan 14 01:12:26 PM PST 24 Jan 14 01:12:44 PM PST 24 6464373298 ps
T445 /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.840976123 Jan 14 01:12:25 PM PST 24 Jan 14 01:12:37 PM PST 24 598958573 ps
T446 /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.81215194 Jan 14 01:12:15 PM PST 24 Jan 14 01:12:24 PM PST 24 468505623 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3039164884 Jan 14 01:12:15 PM PST 24 Jan 14 01:12:37 PM PST 24 2278456960 ps
T127 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3619498033 Jan 14 01:12:22 PM PST 24 Jan 14 01:13:54 PM PST 24 2669289493 ps
T448 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.710950261 Jan 14 01:12:10 PM PST 24 Jan 14 01:12:30 PM PST 24 9272062026 ps
T449 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1259863367 Jan 14 01:12:06 PM PST 24 Jan 14 01:12:11 PM PST 24 87508786 ps
T450 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4197590963 Jan 14 01:12:06 PM PST 24 Jan 14 01:12:26 PM PST 24 6665098025 ps
T451 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.478562926 Jan 14 01:12:28 PM PST 24 Jan 14 01:12:51 PM PST 24 6175610085 ps
T97 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2237676892 Jan 14 01:12:04 PM PST 24 Jan 14 01:13:53 PM PST 24 19485389965 ps
T452 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1127159049 Jan 14 01:12:03 PM PST 24 Jan 14 01:12:14 PM PST 24 3097744506 ps
T453 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.949974952 Jan 14 01:12:32 PM PST 24 Jan 14 01:12:43 PM PST 24 579780116 ps
T454 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1786032496 Jan 14 01:12:21 PM PST 24 Jan 14 01:13:45 PM PST 24 1007771852 ps
T455 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1718241872 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:16 PM PST 24 377888159 ps
T128 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3736873949 Jan 14 01:12:34 PM PST 24 Jan 14 01:13:16 PM PST 24 154016494 ps
T456 /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.218257728 Jan 14 01:12:06 PM PST 24 Jan 14 01:12:16 PM PST 24 1565025211 ps
T457 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.623156025 Jan 14 01:12:30 PM PST 24 Jan 14 01:13:23 PM PST 24 1646839226 ps
T458 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2433507222 Jan 14 01:12:32 PM PST 24 Jan 14 01:12:49 PM PST 24 6595089325 ps
T459 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.904314704 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:21 PM PST 24 5872930970 ps
T460 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1105391350 Jan 14 01:12:31 PM PST 24 Jan 14 01:12:57 PM PST 24 30782383518 ps
T461 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4275524458 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:25 PM PST 24 3837522096 ps
T98 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2102992967 Jan 14 01:12:30 PM PST 24 Jan 14 01:14:39 PM PST 24 14973826403 ps
T462 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1886530555 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:14 PM PST 24 186428563 ps
T463 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3730420636 Jan 14 01:12:08 PM PST 24 Jan 14 01:12:24 PM PST 24 8862036134 ps
T464 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.221752262 Jan 14 01:12:28 PM PST 24 Jan 14 01:12:43 PM PST 24 5480766799 ps
T465 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.136487573 Jan 14 01:12:22 PM PST 24 Jan 14 01:14:40 PM PST 24 4540429142 ps
T466 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3788971419 Jan 14 01:12:41 PM PST 24 Jan 14 01:13:00 PM PST 24 9996371035 ps
T467 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.485409257 Jan 14 01:12:29 PM PST 24 Jan 14 01:12:41 PM PST 24 1590788817 ps
T468 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2965883192 Jan 14 01:12:30 PM PST 24 Jan 14 01:12:48 PM PST 24 18685009093 ps
T469 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3853696595 Jan 14 01:12:29 PM PST 24 Jan 14 01:12:42 PM PST 24 3129789836 ps
T470 /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1639808850 Jan 14 01:12:21 PM PST 24 Jan 14 01:14:11 PM PST 24 7754405445 ps
T471 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2522847409 Jan 14 01:12:13 PM PST 24 Jan 14 01:12:54 PM PST 24 2413223692 ps
T472 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2012798731 Jan 14 01:12:13 PM PST 24 Jan 14 01:12:31 PM PST 24 8782784884 ps
T473 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.295510350 Jan 14 01:12:29 PM PST 24 Jan 14 01:12:45 PM PST 24 19086139021 ps
T474 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.462253775 Jan 14 01:12:19 PM PST 24 Jan 14 01:12:31 PM PST 24 431304575 ps
T475 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.561562324 Jan 14 01:12:09 PM PST 24 Jan 14 01:14:12 PM PST 24 47077579278 ps
T476 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2617613586 Jan 14 01:12:09 PM PST 24 Jan 14 01:12:19 PM PST 24 2625620809 ps
T477 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1296875813 Jan 14 01:12:13 PM PST 24 Jan 14 01:12:24 PM PST 24 4681660638 ps
T478 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1423446684 Jan 14 01:12:07 PM PST 24 Jan 14 01:12:25 PM PST 24 2114733329 ps
T479 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3891677094 Jan 14 01:12:28 PM PST 24 Jan 14 01:12:43 PM PST 24 952768685 ps
T480 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3482153404 Jan 14 01:12:11 PM PST 24 Jan 14 01:12:16 PM PST 24 191671374 ps
T481 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3094670639 Jan 14 01:12:14 PM PST 24 Jan 14 01:12:19 PM PST 24 346230640 ps

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.4206494627
Short name T24
Test name
Test status
Simulation time 781605728 ps
CPU time 12.79 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:20 PM PST 24
Peak memory 219320 kb
Host smart-1f281c4d-6e81-4250-affa-6f6785f10170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206494627 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.4206494627
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.4116483271
Short name T10
Test name
Test status
Simulation time 3133974516 ps
CPU time 24.14 seconds
Started Jan 14 01:20:02 PM PST 24
Finished Jan 14 01:20:32 PM PST 24
Peak memory 212748 kb
Host smart-f96d50a6-d8ef-48ca-92e7-067f50aeaa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116483271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.4116483271
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.61844172
Short name T29
Test name
Test status
Simulation time 5251785663 ps
CPU time 89.84 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:14:01 PM PST 24
Peak memory 210532 kb
Host smart-394ef1f1-af76-45d9-aba3-dd80d0dc26f9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61844172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pas
sthru_mem_tl_intg_err.61844172
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.788118168
Short name T72
Test name
Test status
Simulation time 1032944921 ps
CPU time 12.65 seconds
Started Jan 14 01:12:19 PM PST 24
Finished Jan 14 01:12:38 PM PST 24
Peak memory 219452 kb
Host smart-cd6f4e92-2bd0-4c0f-9f14-a6be9a1831d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788118168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.788118168
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.1379098185
Short name T71
Test name
Test status
Simulation time 564442808 ps
CPU time 78.43 seconds
Started Jan 14 01:12:04 PM PST 24
Finished Jan 14 01:13:23 PM PST 24
Peak memory 211404 kb
Host smart-a0c94b63-3ddf-4aa5-8d00-2bb92db4b2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379098185 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.1379098185
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.195427102
Short name T14
Test name
Test status
Simulation time 24716030202 ps
CPU time 999.32 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:37:14 PM PST 24
Peak memory 235536 kb
Host smart-06f06e6e-bb0e-44e3-8ef0-7e642b86cbef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195427102 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.195427102
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3711499670
Short name T36
Test name
Test status
Simulation time 112567512720 ps
CPU time 299.75 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 01:26:13 PM PST 24
Peak memory 228208 kb
Host smart-db2d7e94-2098-4419-9dab-5c2c30e3a690
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711499670 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.3711499670
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2778186418
Short name T45
Test name
Test status
Simulation time 1203834989 ps
CPU time 11.93 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:28 PM PST 24
Peak memory 219340 kb
Host smart-c8cde7c6-6a74-4c07-a35f-3db784b5ebd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778186418 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2778186418
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1953718416
Short name T126
Test name
Test status
Simulation time 14527385178 ps
CPU time 52.13 seconds
Started Jan 14 01:12:07 PM PST 24
Finished Jan 14 01:13:00 PM PST 24
Peak memory 212656 kb
Host smart-3c4dc29b-64c6-4c92-8d3e-4e89abf34808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953718416 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1953718416
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2126787113
Short name T41
Test name
Test status
Simulation time 4467233735 ps
CPU time 71.02 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:21:36 PM PST 24
Peak memory 236380 kb
Host smart-ad218330-bf7c-40ff-9f1d-08b46f71ddca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126787113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2126787113
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.60182827
Short name T46
Test name
Test status
Simulation time 12878544521 ps
CPU time 12.66 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:27 PM PST 24
Peak memory 219496 kb
Host smart-278c6c95-3658-4718-8a23-8c7675097f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60182827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.60182827
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.4167850187
Short name T77
Test name
Test status
Simulation time 45185531559 ps
CPU time 187.21 seconds
Started Jan 14 01:12:33 PM PST 24
Finished Jan 14 01:15:44 PM PST 24
Peak memory 211268 kb
Host smart-505b854c-27b5-4670-9f46-a89a4bd7d3a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167850187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.4167850187
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1921592613
Short name T162
Test name
Test status
Simulation time 340879645 ps
CPU time 9.93 seconds
Started Jan 14 01:20:18 PM PST 24
Finished Jan 14 01:20:33 PM PST 24
Peak memory 210968 kb
Host smart-c60655f2-67a1-4294-a50c-beb0bd785c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921592613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1921592613
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3797554598
Short name T186
Test name
Test status
Simulation time 5629568798 ps
CPU time 26.8 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:20:49 PM PST 24
Peak memory 210948 kb
Host smart-907952bc-ae55-4e7b-8955-727b86a2726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797554598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3797554598
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.4180975999
Short name T38
Test name
Test status
Simulation time 1667414581 ps
CPU time 14.82 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:33 PM PST 24
Peak memory 211208 kb
Host smart-df38d035-13cc-42d2-9151-0b39ed855d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180975999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.4180975999
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3619498033
Short name T127
Test name
Test status
Simulation time 2669289493 ps
CPU time 88.46 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:13:54 PM PST 24
Peak memory 212432 kb
Host smart-69e186ee-0557-457d-8009-5a83dbf6e062
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619498033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3619498033
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.2740601899
Short name T9
Test name
Test status
Simulation time 333348283 ps
CPU time 4.56 seconds
Started Jan 14 01:20:03 PM PST 24
Finished Jan 14 01:20:12 PM PST 24
Peak memory 210856 kb
Host smart-6b128b3d-779a-41b5-b5af-43b7b0a8b90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740601899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2740601899
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1021105156
Short name T161
Test name
Test status
Simulation time 21776500718 ps
CPU time 226.24 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:24:03 PM PST 24
Peak memory 237364 kb
Host smart-6862fd53-2683-4be5-a6cb-c3513dc14dc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021105156 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.1021105156
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.1488577427
Short name T53
Test name
Test status
Simulation time 7606970050 ps
CPU time 70.04 seconds
Started Jan 14 01:20:04 PM PST 24
Finished Jan 14 01:21:19 PM PST 24
Peak memory 236400 kb
Host smart-f44d260a-35d8-4c70-b580-d234a4ced144
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488577427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.1488577427
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.2796941310
Short name T117
Test name
Test status
Simulation time 39011511218 ps
CPU time 1456.43 seconds
Started Jan 14 01:20:45 PM PST 24
Finished Jan 14 01:45:03 PM PST 24
Peak memory 235376 kb
Host smart-5d498329-11fe-447c-9492-0c662237c222
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796941310 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.2796941310
Directory /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3046477439
Short name T30
Test name
Test status
Simulation time 735325901 ps
CPU time 9.19 seconds
Started Jan 14 01:12:20 PM PST 24
Finished Jan 14 01:12:35 PM PST 24
Peak memory 211168 kb
Host smart-b7d9caee-4f6f-410e-a2e6-4e25b39a8fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046477439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3046477439
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.2092094051
Short name T111
Test name
Test status
Simulation time 598222856 ps
CPU time 7.54 seconds
Started Jan 14 01:21:04 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 210868 kb
Host smart-607b3a34-f6b8-4591-843d-acaa5cca2be7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092094051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.2092094051
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.3312268984
Short name T389
Test name
Test status
Simulation time 47874708359 ps
CPU time 7300.93 seconds
Started Jan 14 01:20:25 PM PST 24
Finished Jan 14 03:22:08 PM PST 24
Peak memory 235608 kb
Host smart-ae54473e-080a-4e20-b25a-408c5ffe8f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312268984 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.3312268984
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2617613586
Short name T476
Test name
Test status
Simulation time 2625620809 ps
CPU time 8.64 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:19 PM PST 24
Peak memory 211268 kb
Host smart-528916a9-f54f-4625-84de-ac287c845d40
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617613586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2617613586
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.1327301624
Short name T434
Test name
Test status
Simulation time 11559161034 ps
CPU time 13.28 seconds
Started Jan 14 01:12:03 PM PST 24
Finished Jan 14 01:12:18 PM PST 24
Peak memory 211176 kb
Host smart-ae219409-0db5-4662-8457-4192bf39ff4e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327301624 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.1327301624
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3171002635
Short name T148
Test name
Test status
Simulation time 3200927614 ps
CPU time 17.01 seconds
Started Jan 14 01:12:04 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 211252 kb
Host smart-cdd84b09-519b-44df-893f-f5d0c5a35d0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171002635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3171002635
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.4115648661
Short name T76
Test name
Test status
Simulation time 378486913 ps
CPU time 5.09 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:12 PM PST 24
Peak memory 214244 kb
Host smart-99dcd9b5-2e58-4def-8bfb-bdf520bfc8f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115648661 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.4115648661
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4126405750
Short name T91
Test name
Test status
Simulation time 1288799045 ps
CPU time 12.19 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:19 PM PST 24
Peak memory 211128 kb
Host smart-9f8444ed-dd1f-405b-a84e-f963bba7043a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126405750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4126405750
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.577933376
Short name T429
Test name
Test status
Simulation time 5119649399 ps
CPU time 11.89 seconds
Started Jan 14 01:12:04 PM PST 24
Finished Jan 14 01:12:17 PM PST 24
Peak memory 211264 kb
Host smart-6a0d1d8e-b58c-45b9-8110-00414b6033e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577933376 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl
_mem_partial_access.577933376
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1127159049
Short name T452
Test name
Test status
Simulation time 3097744506 ps
CPU time 9.34 seconds
Started Jan 14 01:12:03 PM PST 24
Finished Jan 14 01:12:14 PM PST 24
Peak memory 211200 kb
Host smart-28fda5df-8f2f-4c46-b870-044a414d91a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127159049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1127159049
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2237676892
Short name T97
Test name
Test status
Simulation time 19485389965 ps
CPU time 108.14 seconds
Started Jan 14 01:12:04 PM PST 24
Finished Jan 14 01:13:53 PM PST 24
Peak memory 211280 kb
Host smart-a0b9a65d-57a6-4f18-a4e8-c02245da14d4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237676892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.2237676892
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.844330481
Short name T143
Test name
Test status
Simulation time 777324094 ps
CPU time 10.68 seconds
Started Jan 14 01:12:05 PM PST 24
Finished Jan 14 01:12:16 PM PST 24
Peak memory 211140 kb
Host smart-b2d04e74-8506-42fc-bd2a-6e4b00e102dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844330481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ct
rl_same_csr_outstanding.844330481
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.873152885
Short name T73
Test name
Test status
Simulation time 452923502 ps
CPU time 10.65 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:17 PM PST 24
Peak memory 219440 kb
Host smart-9f129cf2-b052-43bc-b608-1bd80e85f6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873152885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.873152885
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4275524458
Short name T461
Test name
Test status
Simulation time 3837522096 ps
CPU time 15.31 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:25 PM PST 24
Peak memory 211228 kb
Host smart-67390171-71aa-4f19-a95e-f3931faf74d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275524458 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4275524458
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1915287146
Short name T131
Test name
Test status
Simulation time 16284275871 ps
CPU time 15.43 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 211208 kb
Host smart-f4f00064-a589-4a6d-8c66-7225dcf09f3f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915287146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1915287146
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1979340549
Short name T431
Test name
Test status
Simulation time 1208964608 ps
CPU time 12.57 seconds
Started Jan 14 01:12:07 PM PST 24
Finished Jan 14 01:12:21 PM PST 24
Peak memory 211124 kb
Host smart-8dec3969-d3b8-4a29-ba7b-20c1ad17cca6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979340549 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1979340549
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.1423446684
Short name T478
Test name
Test status
Simulation time 2114733329 ps
CPU time 17.6 seconds
Started Jan 14 01:12:07 PM PST 24
Finished Jan 14 01:12:25 PM PST 24
Peak memory 219352 kb
Host smart-5f757e6e-b45c-4f2b-80df-adfb12f788bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423446684 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.1423446684
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.1872586661
Short name T150
Test name
Test status
Simulation time 4117313671 ps
CPU time 16.86 seconds
Started Jan 14 01:12:05 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 211272 kb
Host smart-90228965-464e-4d35-9540-8be10bd7d516
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872586661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.1872586661
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.218257728
Short name T456
Test name
Test status
Simulation time 1565025211 ps
CPU time 8.97 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:16 PM PST 24
Peak memory 211208 kb
Host smart-f7c4ddf6-2c67-450f-8af7-967a673cb6eb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218257728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.218257728
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1259863367
Short name T449
Test name
Test status
Simulation time 87508786 ps
CPU time 4.39 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:11 PM PST 24
Peak memory 211124 kb
Host smart-b7103b8e-e052-489f-96a3-0b887be4b3bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259863367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1259863367
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.3880651831
Short name T95
Test name
Test status
Simulation time 40688084388 ps
CPU time 216.81 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:15:47 PM PST 24
Peak memory 211276 kb
Host smart-89a6e08a-518b-4463-873b-5ef2558da012
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880651831 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.3880651831
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1076654665
Short name T141
Test name
Test status
Simulation time 5752683499 ps
CPU time 11.2 seconds
Started Jan 14 01:12:07 PM PST 24
Finished Jan 14 01:12:19 PM PST 24
Peak memory 211232 kb
Host smart-b81492db-31a7-4736-b7e0-e3f08230575e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076654665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1076654665
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1566629240
Short name T67
Test name
Test status
Simulation time 8610596883 ps
CPU time 51.2 seconds
Started Jan 14 01:12:10 PM PST 24
Finished Jan 14 01:13:02 PM PST 24
Peak memory 212680 kb
Host smart-e4afe8f9-0331-42fd-b076-429537375e93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566629240 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.1566629240
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.1240967597
Short name T441
Test name
Test status
Simulation time 7506966389 ps
CPU time 16.28 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:12:42 PM PST 24
Peak memory 212844 kb
Host smart-6ce236fe-da14-4fb8-9ac5-bb5ea97766ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240967597 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.1240967597
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.462253775
Short name T474
Test name
Test status
Simulation time 431304575 ps
CPU time 5.73 seconds
Started Jan 14 01:12:19 PM PST 24
Finished Jan 14 01:12:31 PM PST 24
Peak memory 211196 kb
Host smart-9dce0873-a7a5-410f-962a-4500a9e54599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462253775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.462253775
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.419801089
Short name T82
Test name
Test status
Simulation time 31490878873 ps
CPU time 304.08 seconds
Started Jan 14 01:12:19 PM PST 24
Finished Jan 14 01:17:30 PM PST 24
Peak memory 210024 kb
Host smart-19b6c9c2-96ee-4201-91bc-b35705a27f53
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419801089 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.419801089
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.924418744
Short name T153
Test name
Test status
Simulation time 1486638694 ps
CPU time 16.91 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:32 PM PST 24
Peak memory 219332 kb
Host smart-6f675078-5340-4d7e-a999-17d2dd1c3305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924418744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.924418744
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1786032496
Short name T454
Test name
Test status
Simulation time 1007771852 ps
CPU time 79.82 seconds
Started Jan 14 01:12:21 PM PST 24
Finished Jan 14 01:13:45 PM PST 24
Peak memory 211340 kb
Host smart-04156790-5289-4286-8d3f-c4e3dfcfb3a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786032496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.1786032496
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.3853696595
Short name T469
Test name
Test status
Simulation time 3129789836 ps
CPU time 10.35 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:12:42 PM PST 24
Peak memory 215040 kb
Host smart-5107e8f4-5588-421a-b9db-24a0ee52a181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853696595 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.3853696595
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.956161333
Short name T443
Test name
Test status
Simulation time 308077496 ps
CPU time 4.33 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:12:36 PM PST 24
Peak memory 211224 kb
Host smart-4269364a-1e57-4210-8490-0aac86198d29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956161333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.956161333
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.967886141
Short name T25
Test name
Test status
Simulation time 2993777228 ps
CPU time 9.54 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:12:35 PM PST 24
Peak memory 210912 kb
Host smart-5a94d466-2517-4b64-8577-46766db84c2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967886141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_c
trl_same_csr_outstanding.967886141
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3891677094
Short name T479
Test name
Test status
Simulation time 952768685 ps
CPU time 12.52 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:12:43 PM PST 24
Peak memory 219296 kb
Host smart-afa39d95-5746-4bd6-a372-9d9955b60347
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891677094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.3891677094
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1408292741
Short name T438
Test name
Test status
Simulation time 7460246941 ps
CPU time 50.06 seconds
Started Jan 14 01:12:24 PM PST 24
Finished Jan 14 01:13:18 PM PST 24
Peak memory 212256 kb
Host smart-e3d2d4f9-80ed-4133-b092-3d2af16331be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408292741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1408292741
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1483152710
Short name T132
Test name
Test status
Simulation time 313811656 ps
CPU time 6.89 seconds
Started Jan 14 01:12:21 PM PST 24
Finished Jan 14 01:12:33 PM PST 24
Peak memory 214048 kb
Host smart-72240737-3a6a-4fea-939f-f25c8726ae63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483152710 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1483152710
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.3876639142
Short name T137
Test name
Test status
Simulation time 7372369574 ps
CPU time 15.75 seconds
Started Jan 14 01:12:27 PM PST 24
Finished Jan 14 01:12:47 PM PST 24
Peak memory 211188 kb
Host smart-84679db2-e6d2-49e5-a65a-5f2ba933a471
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876639142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.3876639142
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2779000175
Short name T81
Test name
Test status
Simulation time 36825022855 ps
CPU time 191.37 seconds
Started Jan 14 01:12:26 PM PST 24
Finished Jan 14 01:15:41 PM PST 24
Peak memory 211184 kb
Host smart-17b31ce7-21b9-43c3-ba35-ec4e1bec55d9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779000175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p
assthru_mem_tl_intg_err.2779000175
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3410691321
Short name T440
Test name
Test status
Simulation time 7347785790 ps
CPU time 15.67 seconds
Started Jan 14 01:12:30 PM PST 24
Finished Jan 14 01:12:47 PM PST 24
Peak memory 211184 kb
Host smart-7aad1cfb-d431-4ef8-95d0-999f697486e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410691321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3410691321
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2059085478
Short name T85
Test name
Test status
Simulation time 217313433 ps
CPU time 8.53 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:12:34 PM PST 24
Peak memory 219408 kb
Host smart-6e2f680b-ac82-4235-bdb1-763e15476ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059085478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2059085478
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3736873949
Short name T128
Test name
Test status
Simulation time 154016494 ps
CPU time 39.48 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:13:16 PM PST 24
Peak memory 210892 kb
Host smart-185e133f-961f-41bb-ab65-ff00eec1ff94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736873949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.3736873949
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1879145365
Short name T69
Test name
Test status
Simulation time 2269251975 ps
CPU time 16.84 seconds
Started Jan 14 01:12:30 PM PST 24
Finished Jan 14 01:12:48 PM PST 24
Peak memory 214440 kb
Host smart-a044d0e4-9af3-4ee9-a569-1ad1a0d65d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879145365 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1879145365
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.657487633
Short name T84
Test name
Test status
Simulation time 3125572259 ps
CPU time 9.7 seconds
Started Jan 14 01:12:31 PM PST 24
Finished Jan 14 01:12:46 PM PST 24
Peak memory 211268 kb
Host smart-12936c46-98f9-425f-8892-e744432d8ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657487633 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.657487633
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.759853881
Short name T33
Test name
Test status
Simulation time 2321369160 ps
CPU time 10.62 seconds
Started Jan 14 01:12:23 PM PST 24
Finished Jan 14 01:12:37 PM PST 24
Peak memory 210984 kb
Host smart-4a5eb1d1-0d78-4a79-92a7-03d9b8f4f1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759853881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c
trl_same_csr_outstanding.759853881
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1316726378
Short name T134
Test name
Test status
Simulation time 9713697139 ps
CPU time 16.78 seconds
Started Jan 14 01:12:27 PM PST 24
Finished Jan 14 01:12:48 PM PST 24
Peak memory 219496 kb
Host smart-4aa898fa-040d-4f41-8d2f-f694cef9bd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316726378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1316726378
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.623156025
Short name T457
Test name
Test status
Simulation time 1646839226 ps
CPU time 47.85 seconds
Started Jan 14 01:12:30 PM PST 24
Finished Jan 14 01:13:23 PM PST 24
Peak memory 212036 kb
Host smart-1f8437a6-479a-4fb1-bc10-b4e63345d472
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623156025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_in
tg_err.623156025
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.66988950
Short name T444
Test name
Test status
Simulation time 6464373298 ps
CPU time 13.91 seconds
Started Jan 14 01:12:26 PM PST 24
Finished Jan 14 01:12:44 PM PST 24
Peak memory 216276 kb
Host smart-6a29c77c-caf9-43d9-a622-f847aae8b16c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66988950 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.66988950
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.221752262
Short name T464
Test name
Test status
Simulation time 5480766799 ps
CPU time 12.17 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:12:43 PM PST 24
Peak memory 211280 kb
Host smart-ced86ff9-f6cf-42bb-b6af-431dcfe56a6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221752262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.221752262
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3413672484
Short name T49
Test name
Test status
Simulation time 2022452443 ps
CPU time 54.68 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:13:26 PM PST 24
Peak memory 211160 kb
Host smart-2edb5ad6-9824-4dae-9ada-42871701b255
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413672484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3413672484
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1491881493
Short name T27
Test name
Test status
Simulation time 6638233828 ps
CPU time 15.56 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:12:47 PM PST 24
Peak memory 211236 kb
Host smart-70883249-550d-44a3-81a2-81584b121019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491881493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1491881493
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.485409257
Short name T467
Test name
Test status
Simulation time 1590788817 ps
CPU time 10.28 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:12:41 PM PST 24
Peak memory 219424 kb
Host smart-e076b427-0340-45c2-ae15-9a246cea05d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485409257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.485409257
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.2167999327
Short name T122
Test name
Test status
Simulation time 7427472253 ps
CPU time 84.34 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:13:56 PM PST 24
Peak memory 211828 kb
Host smart-dad446c8-673d-4e6a-ba19-69e7d5e941f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167999327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.2167999327
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.840976123
Short name T445
Test name
Test status
Simulation time 598958573 ps
CPU time 8.26 seconds
Started Jan 14 01:12:25 PM PST 24
Finished Jan 14 01:12:37 PM PST 24
Peak memory 213988 kb
Host smart-f6120258-e91d-400b-980c-97fe441bb047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840976123 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.840976123
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.2149084896
Short name T32
Test name
Test status
Simulation time 19936116441 ps
CPU time 11.55 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:12:48 PM PST 24
Peak memory 211268 kb
Host smart-56529982-7400-461d-96ab-779ffb21042b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149084896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.2149084896
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.136487573
Short name T465
Test name
Test status
Simulation time 4540429142 ps
CPU time 134.46 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:14:40 PM PST 24
Peak memory 211244 kb
Host smart-d586d74c-7255-4d61-be77-b66f1c1eb275
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136487573 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_pa
ssthru_mem_tl_intg_err.136487573
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1189005461
Short name T87
Test name
Test status
Simulation time 729222465 ps
CPU time 7.54 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:12:44 PM PST 24
Peak memory 211140 kb
Host smart-b97d1888-6688-49e1-8ffc-0bcaf76cf66f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189005461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1189005461
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.43022054
Short name T149
Test name
Test status
Simulation time 3796308229 ps
CPU time 18.58 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:12:55 PM PST 24
Peak memory 219476 kb
Host smart-4abab0a8-6f9d-4c84-8dd8-65a0c48b793a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43022054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.43022054
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2363572912
Short name T120
Test name
Test status
Simulation time 1439803913 ps
CPU time 46.85 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:13:24 PM PST 24
Peak memory 212220 kb
Host smart-1573a00b-861e-42d6-8272-d0bf93c15c36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363572912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2363572912
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.295510350
Short name T473
Test name
Test status
Simulation time 19086139021 ps
CPU time 13.49 seconds
Started Jan 14 01:12:29 PM PST 24
Finished Jan 14 01:12:45 PM PST 24
Peak memory 212960 kb
Host smart-b69e7670-8a4c-4fba-b16e-0b8324947e35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295510350 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.295510350
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.2544129422
Short name T31
Test name
Test status
Simulation time 1971483945 ps
CPU time 16.09 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:12:47 PM PST 24
Peak memory 211136 kb
Host smart-4e3b39fb-a745-46c2-bbac-a5ae2fd9a9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544129422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.2544129422
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.2078259475
Short name T96
Test name
Test status
Simulation time 7787153710 ps
CPU time 103.2 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:14:20 PM PST 24
Peak memory 210920 kb
Host smart-a7a5ebc1-e949-4a07-a2b2-f480b458f121
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078259475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.2078259475
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.949974952
Short name T453
Test name
Test status
Simulation time 579780116 ps
CPU time 6.27 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:12:43 PM PST 24
Peak memory 211168 kb
Host smart-91234839-49f2-47d4-8546-b58b97c0c5c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949974952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.949974952
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1105391350
Short name T460
Test name
Test status
Simulation time 30782383518 ps
CPU time 20.56 seconds
Started Jan 14 01:12:31 PM PST 24
Finished Jan 14 01:12:57 PM PST 24
Peak memory 219492 kb
Host smart-8ea9825f-c850-438c-99e6-067503ed7956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105391350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1105391350
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.90217101
Short name T130
Test name
Test status
Simulation time 2236456036 ps
CPU time 85.89 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:14:03 PM PST 24
Peak memory 211432 kb
Host smart-ac5c92aa-1cfc-4fb1-b5f2-71d9cf038be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90217101 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_int
g_err.90217101
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.857173692
Short name T50
Test name
Test status
Simulation time 1158751952 ps
CPU time 5.05 seconds
Started Jan 14 01:12:31 PM PST 24
Finished Jan 14 01:12:42 PM PST 24
Peak memory 214328 kb
Host smart-c657aa5f-a97e-445c-baf1-b0cb67a75c87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857173692 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.857173692
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1485530908
Short name T139
Test name
Test status
Simulation time 2068968234 ps
CPU time 15.85 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:12:53 PM PST 24
Peak memory 211080 kb
Host smart-64a821b8-3ff5-4ba7-b31a-b346f40e1c86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485530908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1485530908
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.4293054625
Short name T94
Test name
Test status
Simulation time 21286709377 ps
CPU time 115.63 seconds
Started Jan 14 01:12:33 PM PST 24
Finished Jan 14 01:14:32 PM PST 24
Peak memory 211284 kb
Host smart-7eb0f81c-e1e3-47a4-a383-713fc5b55fa6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293054625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.4293054625
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1548135875
Short name T154
Test name
Test status
Simulation time 942075353 ps
CPU time 9.43 seconds
Started Jan 14 01:12:38 PM PST 24
Finished Jan 14 01:12:49 PM PST 24
Peak memory 211204 kb
Host smart-6b61b1dd-fe1e-4ac8-9fa8-7c0225cb6372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548135875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1548135875
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2965883192
Short name T468
Test name
Test status
Simulation time 18685009093 ps
CPU time 16.78 seconds
Started Jan 14 01:12:30 PM PST 24
Finished Jan 14 01:12:48 PM PST 24
Peak memory 219444 kb
Host smart-c7dbfb65-0838-46c6-af80-00df0fdbd6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965883192 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2965883192
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.4212437731
Short name T70
Test name
Test status
Simulation time 257727717 ps
CPU time 77.36 seconds
Started Jan 14 01:12:35 PM PST 24
Finished Jan 14 01:13:54 PM PST 24
Peak memory 212628 kb
Host smart-2fce099e-b70d-47fd-9d20-7a6ae11ee3c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212437731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.4212437731
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.991892337
Short name T144
Test name
Test status
Simulation time 1600673903 ps
CPU time 9.43 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:12:46 PM PST 24
Peak memory 213584 kb
Host smart-4d0d76db-d02e-46d9-841c-aa545eb8d304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991892337 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.991892337
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3175120255
Short name T432
Test name
Test status
Simulation time 2180167507 ps
CPU time 16.71 seconds
Started Jan 14 01:12:36 PM PST 24
Finished Jan 14 01:12:54 PM PST 24
Peak memory 211272 kb
Host smart-2445702b-aff9-4506-a276-d3c20522af80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175120255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3175120255
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.2102992967
Short name T98
Test name
Test status
Simulation time 14973826403 ps
CPU time 123.81 seconds
Started Jan 14 01:12:30 PM PST 24
Finished Jan 14 01:14:39 PM PST 24
Peak memory 219384 kb
Host smart-9181a679-89cc-43eb-9b12-0acdf37a2c84
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102992967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.2102992967
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2433507222
Short name T458
Test name
Test status
Simulation time 6595089325 ps
CPU time 12.39 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:12:49 PM PST 24
Peak memory 211172 kb
Host smart-e89f5a80-a828-4dd0-993e-79e3b3362daf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433507222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2433507222
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.478562926
Short name T451
Test name
Test status
Simulation time 6175610085 ps
CPU time 19.74 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:12:51 PM PST 24
Peak memory 219500 kb
Host smart-9b3a7a8b-bb71-4cbd-8203-557a8a43ff6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478562926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.478562926
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.626478324
Short name T129
Test name
Test status
Simulation time 6696595935 ps
CPU time 77.23 seconds
Started Jan 14 01:12:42 PM PST 24
Finished Jan 14 01:14:01 PM PST 24
Peak memory 211876 kb
Host smart-af5cdb00-426b-4e2c-978d-f10645aeda51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626478324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_in
tg_err.626478324
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3175820105
Short name T68
Test name
Test status
Simulation time 2231438856 ps
CPU time 10.77 seconds
Started Jan 14 01:12:46 PM PST 24
Finished Jan 14 01:12:58 PM PST 24
Peak memory 212064 kb
Host smart-3e63c272-5453-4625-a16b-055b9118ed80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175820105 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3175820105
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.2683090452
Short name T145
Test name
Test status
Simulation time 89256112 ps
CPU time 4.72 seconds
Started Jan 14 01:12:41 PM PST 24
Finished Jan 14 01:12:47 PM PST 24
Peak memory 211208 kb
Host smart-88ea87b7-da36-4bfc-8117-bb13711efece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683090452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.2683090452
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.222362890
Short name T439
Test name
Test status
Simulation time 35891199007 ps
CPU time 103.61 seconds
Started Jan 14 01:12:41 PM PST 24
Finished Jan 14 01:14:26 PM PST 24
Peak memory 211172 kb
Host smart-41551615-0fe8-4d8f-aab9-e7953ff68f76
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222362890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_pa
ssthru_mem_tl_intg_err.222362890
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3788971419
Short name T466
Test name
Test status
Simulation time 9996371035 ps
CPU time 16.76 seconds
Started Jan 14 01:12:41 PM PST 24
Finished Jan 14 01:13:00 PM PST 24
Peak memory 211156 kb
Host smart-df079cfb-dd38-465c-b04c-2c5ef88ca80b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788971419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.3788971419
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.942060215
Short name T133
Test name
Test status
Simulation time 1680067949 ps
CPU time 17.41 seconds
Started Jan 14 01:12:34 PM PST 24
Finished Jan 14 01:12:54 PM PST 24
Peak memory 219356 kb
Host smart-83a1d20f-6a91-4226-b288-e3cc0af540aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942060215 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.942060215
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.69690718
Short name T121
Test name
Test status
Simulation time 7737335460 ps
CPU time 82.42 seconds
Started Jan 14 01:12:32 PM PST 24
Finished Jan 14 01:13:59 PM PST 24
Peak memory 211864 kb
Host smart-a8bc26d2-acf3-4f4f-8948-a5fb06ec58e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69690718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_int
g_err.69690718
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.838755563
Short name T428
Test name
Test status
Simulation time 333809100 ps
CPU time 4.44 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:12 PM PST 24
Peak memory 211164 kb
Host smart-9a7d3e47-fb52-4cd9-8f71-71ef4ea223d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838755563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias
ing.838755563
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1087693886
Short name T136
Test name
Test status
Simulation time 5921696802 ps
CPU time 12.31 seconds
Started Jan 14 01:12:05 PM PST 24
Finished Jan 14 01:12:18 PM PST 24
Peak memory 211232 kb
Host smart-4175b996-7097-4bc8-815a-0f5e41fcda74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087693886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1087693886
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.3730420636
Short name T463
Test name
Test status
Simulation time 8862036134 ps
CPU time 16.1 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:24 PM PST 24
Peak memory 211156 kb
Host smart-52e3f5c7-83f5-4082-9a49-4a064bf3cf68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730420636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.3730420636
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.1886530555
Short name T462
Test name
Test status
Simulation time 186428563 ps
CPU time 4.8 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:14 PM PST 24
Peak memory 214148 kb
Host smart-2512a2ad-cb7c-44a6-aa1d-51da16c840f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886530555 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.1886530555
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2472565468
Short name T427
Test name
Test status
Simulation time 297528188 ps
CPU time 5.1 seconds
Started Jan 14 01:12:05 PM PST 24
Finished Jan 14 01:12:11 PM PST 24
Peak memory 211108 kb
Host smart-8a6dcc1e-3b45-4c2d-9907-b811dfa0f872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472565468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2472565468
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.2747115496
Short name T146
Test name
Test status
Simulation time 5396983043 ps
CPU time 12.57 seconds
Started Jan 14 01:12:07 PM PST 24
Finished Jan 14 01:12:20 PM PST 24
Peak memory 211280 kb
Host smart-876f747e-2fbe-4742-bef2-1964504c5f6b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747115496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.2747115496
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.4239412370
Short name T135
Test name
Test status
Simulation time 4375778673 ps
CPU time 16.48 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:26 PM PST 24
Peak memory 211272 kb
Host smart-95e72efc-7481-4d5d-a214-b643aba0a940
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239412370 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.4239412370
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4108261585
Short name T78
Test name
Test status
Simulation time 1867196798 ps
CPU time 95.8 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:13:43 PM PST 24
Peak memory 211208 kb
Host smart-5b10ae50-44c7-4d0f-94e9-12e3c41beb5f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108261585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4108261585
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1718241872
Short name T455
Test name
Test status
Simulation time 377888159 ps
CPU time 6.21 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:16 PM PST 24
Peak memory 211156 kb
Host smart-56abe9c5-5512-4e5c-a40a-eb738839453c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718241872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1718241872
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4197590963
Short name T450
Test name
Test status
Simulation time 6665098025 ps
CPU time 19.51 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:26 PM PST 24
Peak memory 219364 kb
Host smart-fc16a76e-7f48-46b1-9b13-23b38acbb8e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197590963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.4197590963
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.93177028
Short name T119
Test name
Test status
Simulation time 4838544904 ps
CPU time 46.08 seconds
Started Jan 14 01:12:05 PM PST 24
Finished Jan 14 01:12:51 PM PST 24
Peak memory 212428 kb
Host smart-cc371f0a-1276-4f66-8ed1-9294293a9fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93177028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_intg
_err.93177028
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2928924667
Short name T142
Test name
Test status
Simulation time 168536449 ps
CPU time 4.35 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:13 PM PST 24
Peak memory 211180 kb
Host smart-444f922e-83d9-4186-a137-a9f7c4920e64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928924667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2928924667
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.2439814635
Short name T147
Test name
Test status
Simulation time 1239515175 ps
CPU time 11.73 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:21 PM PST 24
Peak memory 211184 kb
Host smart-dd2b6553-d484-478e-a8a9-cbaa3b3bce10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439814635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.2439814635
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.2961215698
Short name T89
Test name
Test status
Simulation time 92270970 ps
CPU time 7.95 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:17 PM PST 24
Peak memory 211228 kb
Host smart-ed17a865-15e5-48f7-867a-80617c108d51
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961215698 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.2961215698
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1548487843
Short name T66
Test name
Test status
Simulation time 2253308406 ps
CPU time 11.42 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:20 PM PST 24
Peak memory 214220 kb
Host smart-55bc95ce-9616-4567-8f25-fbd8057cca11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548487843 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1548487843
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2226582774
Short name T88
Test name
Test status
Simulation time 89793838 ps
CPU time 4.45 seconds
Started Jan 14 01:12:06 PM PST 24
Finished Jan 14 01:12:11 PM PST 24
Peak memory 211208 kb
Host smart-a12a4739-ff7d-481f-966c-8584994cd9d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226582774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2226582774
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2282583421
Short name T47
Test name
Test status
Simulation time 1330992500 ps
CPU time 12.27 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:21 PM PST 24
Peak memory 211224 kb
Host smart-1715f173-4674-47a3-b228-264f35eac220
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282583421 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2282583421
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.904314704
Short name T459
Test name
Test status
Simulation time 5872930970 ps
CPU time 11.45 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:21 PM PST 24
Peak memory 211212 kb
Host smart-aabfc1e1-d294-40d1-a815-0f702e65273d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904314704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk.
904314704
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.2922033536
Short name T83
Test name
Test status
Simulation time 93922636137 ps
CPU time 221.29 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:15:51 PM PST 24
Peak memory 211268 kb
Host smart-5cd36b8c-8612-4f8b-b8ba-ad5203d16833
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922033536 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.2922033536
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1196580608
Short name T110
Test name
Test status
Simulation time 5346244126 ps
CPU time 13.81 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:29 PM PST 24
Peak memory 210936 kb
Host smart-1942660a-8fd6-464a-bdd2-bdf09d6fb317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196580608 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1196580608
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.3319400807
Short name T65
Test name
Test status
Simulation time 6428805200 ps
CPU time 15.51 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:24 PM PST 24
Peak memory 219484 kb
Host smart-568341ee-c3f2-4aed-9bac-db77bc32f6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319400807 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.3319400807
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.4079847654
Short name T125
Test name
Test status
Simulation time 2265927656 ps
CPU time 45.11 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:55 PM PST 24
Peak memory 212132 kb
Host smart-b22291b1-ca17-491c-8b93-04a1b65db7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079847654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.4079847654
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.1296875813
Short name T477
Test name
Test status
Simulation time 4681660638 ps
CPU time 10.87 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:24 PM PST 24
Peak memory 211276 kb
Host smart-4e40d1ab-703a-43ce-b0b6-18b12ddfd9d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296875813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.1296875813
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3094670639
Short name T481
Test name
Test status
Simulation time 346230640 ps
CPU time 4.62 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:19 PM PST 24
Peak memory 211308 kb
Host smart-0bf1d7c1-9d2c-4471-a8c9-09166764c0a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094670639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3094670639
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.4062680112
Short name T93
Test name
Test status
Simulation time 1866960370 ps
CPU time 18.82 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:29 PM PST 24
Peak memory 211168 kb
Host smart-cf458c99-5cca-4c3e-af09-d8cc0bb0cb54
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062680112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.4062680112
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3715105774
Short name T51
Test name
Test status
Simulation time 2817348129 ps
CPU time 8.19 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:22 PM PST 24
Peak memory 214716 kb
Host smart-21109293-2386-4ab8-8231-bc9b88b88c3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715105774 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3715105774
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1355795171
Short name T26
Test name
Test status
Simulation time 8187691646 ps
CPU time 12.82 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:28 PM PST 24
Peak memory 210728 kb
Host smart-aa0794fc-5f58-4a0d-a383-6017b388a5e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355795171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1355795171
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.3023415372
Short name T435
Test name
Test status
Simulation time 90877805 ps
CPU time 4.39 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:12:14 PM PST 24
Peak memory 211188 kb
Host smart-5adf05a0-8121-4280-8443-0f5711c5135f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023415372 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.3023415372
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.1755518814
Short name T140
Test name
Test status
Simulation time 287971460 ps
CPU time 4.29 seconds
Started Jan 14 01:12:08 PM PST 24
Finished Jan 14 01:12:13 PM PST 24
Peak memory 211104 kb
Host smart-42018364-67e8-4fc2-b1ad-790b6ab608a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755518814 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.1755518814
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.561562324
Short name T475
Test name
Test status
Simulation time 47077579278 ps
CPU time 122.18 seconds
Started Jan 14 01:12:09 PM PST 24
Finished Jan 14 01:14:12 PM PST 24
Peak memory 211236 kb
Host smart-8b0b42d7-8d76-4592-90f9-2e523b379095
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561562324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas
sthru_mem_tl_intg_err.561562324
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3180671729
Short name T442
Test name
Test status
Simulation time 1903395143 ps
CPU time 15 seconds
Started Jan 14 01:12:18 PM PST 24
Finished Jan 14 01:12:40 PM PST 24
Peak memory 211072 kb
Host smart-9e691ad4-c4c3-4e22-be1a-5f8abff81698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180671729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3180671729
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.710950261
Short name T448
Test name
Test status
Simulation time 9272062026 ps
CPU time 19.57 seconds
Started Jan 14 01:12:10 PM PST 24
Finished Jan 14 01:12:30 PM PST 24
Peak memory 219468 kb
Host smart-c3a01f91-5741-43e3-a1c5-b922a93a349e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710950261 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.710950261
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.1864423199
Short name T430
Test name
Test status
Simulation time 94912091 ps
CPU time 4.63 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:19 PM PST 24
Peak memory 213468 kb
Host smart-dea7798d-50ec-4080-8537-e42b3c72965d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864423199 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.1864423199
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.1034142153
Short name T92
Test name
Test status
Simulation time 2401149890 ps
CPU time 8.45 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:12:34 PM PST 24
Peak memory 211264 kb
Host smart-7cb43e30-74e0-416d-a981-ba958862866e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034142153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.1034142153
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.1878839145
Short name T48
Test name
Test status
Simulation time 82969581028 ps
CPU time 184.54 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:15:19 PM PST 24
Peak memory 211364 kb
Host smart-5783434a-75e1-4454-99b7-628d88e38001
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878839145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.1878839145
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.81215194
Short name T446
Test name
Test status
Simulation time 468505623 ps
CPU time 7.32 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:24 PM PST 24
Peak memory 211144 kb
Host smart-4c2954c9-7e20-4bdc-955a-00b1f3087d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81215194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctr
l_same_csr_outstanding.81215194
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1559131625
Short name T152
Test name
Test status
Simulation time 5501216489 ps
CPU time 16.32 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:30 PM PST 24
Peak memory 219412 kb
Host smart-c890cfb9-610d-414d-8111-a0f96bbf5d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559131625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1559131625
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2522847409
Short name T471
Test name
Test status
Simulation time 2413223692 ps
CPU time 39.7 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:54 PM PST 24
Peak memory 212440 kb
Host smart-6d8e2b4e-ed14-4c6f-92ad-9278a8cfaef4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522847409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.2522847409
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.794128872
Short name T151
Test name
Test status
Simulation time 828910639 ps
CPU time 6.9 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:23 PM PST 24
Peak memory 214296 kb
Host smart-b3f2137b-98fa-4254-a8d5-f7a2957582f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794128872 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.794128872
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2012798731
Short name T472
Test name
Test status
Simulation time 8782784884 ps
CPU time 17.02 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:31 PM PST 24
Peak memory 211276 kb
Host smart-34c826ab-0646-4b0d-8b22-80cceacdd55a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012798731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2012798731
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.535030767
Short name T99
Test name
Test status
Simulation time 3883888249 ps
CPU time 97.57 seconds
Started Jan 14 01:12:19 PM PST 24
Finished Jan 14 01:14:03 PM PST 24
Peak memory 209948 kb
Host smart-9fb80d36-969e-499b-9fd6-07ce39452aec
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535030767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.535030767
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.661458790
Short name T86
Test name
Test status
Simulation time 3681051922 ps
CPU time 17.33 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:33 PM PST 24
Peak memory 211176 kb
Host smart-de110743-3285-432f-ace3-09f27d63d3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661458790 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct
rl_same_csr_outstanding.661458790
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2137360738
Short name T124
Test name
Test status
Simulation time 7318055469 ps
CPU time 50.46 seconds
Started Jan 14 01:12:10 PM PST 24
Finished Jan 14 01:13:02 PM PST 24
Peak memory 212732 kb
Host smart-0d44c9f7-eca8-4e29-b2d8-5c6fa70537c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137360738 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2137360738
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.3482153404
Short name T480
Test name
Test status
Simulation time 191671374 ps
CPU time 5.12 seconds
Started Jan 14 01:12:11 PM PST 24
Finished Jan 14 01:12:16 PM PST 24
Peak memory 214404 kb
Host smart-7e941798-a72b-4ae7-bb0d-4da297165bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482153404 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.3482153404
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1364544487
Short name T437
Test name
Test status
Simulation time 246252070 ps
CPU time 5.42 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:23 PM PST 24
Peak memory 211144 kb
Host smart-dc217e4b-e631-4f3f-83bf-a4e6b9bc5459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364544487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1364544487
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.3568371155
Short name T80
Test name
Test status
Simulation time 75956403851 ps
CPU time 166.32 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:15:12 PM PST 24
Peak memory 211200 kb
Host smart-cd378379-457d-467d-9e47-b9632760eab8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568371155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.3568371155
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3110604926
Short name T436
Test name
Test status
Simulation time 2746212090 ps
CPU time 8.64 seconds
Started Jan 14 01:12:12 PM PST 24
Finished Jan 14 01:12:21 PM PST 24
Peak memory 211276 kb
Host smart-fb9873a4-9e79-47f8-a599-a259447ffa7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110604926 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3110604926
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3039164884
Short name T447
Test name
Test status
Simulation time 2278456960 ps
CPU time 19.82 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:37 PM PST 24
Peak memory 219500 kb
Host smart-9c6ff7f0-3233-49fb-90f2-ee0997bac84b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039164884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.3039164884
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.340180024
Short name T433
Test name
Test status
Simulation time 1360696936 ps
CPU time 46.29 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:13:01 PM PST 24
Peak memory 212272 kb
Host smart-6ae5ec9f-35c7-47e3-8816-d242335be60d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340180024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_int
g_err.340180024
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3431759952
Short name T90
Test name
Test status
Simulation time 2467837869 ps
CPU time 11.39 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:27 PM PST 24
Peak memory 211288 kb
Host smart-75b2b37f-0cdc-4bc5-a1f6-c2c714df750a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431759952 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3431759952
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3103153162
Short name T79
Test name
Test status
Simulation time 2304400611 ps
CPU time 100.69 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:14:06 PM PST 24
Peak memory 211280 kb
Host smart-1c3b6683-d13a-4bce-8b29-d925072b7755
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103153162 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.3103153162
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2448796229
Short name T138
Test name
Test status
Simulation time 1626618273 ps
CPU time 13.76 seconds
Started Jan 14 01:12:28 PM PST 24
Finished Jan 14 01:12:45 PM PST 24
Peak memory 210760 kb
Host smart-0cd28985-9071-47d0-adc3-a0bf349cfa07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448796229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2448796229
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2881758285
Short name T75
Test name
Test status
Simulation time 15934759103 ps
CPU time 15.04 seconds
Started Jan 14 01:12:14 PM PST 24
Finished Jan 14 01:12:30 PM PST 24
Peak memory 219480 kb
Host smart-329e1fb0-5679-47ce-b989-9b4c968d505f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881758285 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2881758285
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.3918371346
Short name T123
Test name
Test status
Simulation time 2965021104 ps
CPU time 79.69 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:13:46 PM PST 24
Peak memory 211424 kb
Host smart-0a730fbe-29f1-417a-a9ec-3f5187f4708d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918371346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.3918371346
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.3479080704
Short name T74
Test name
Test status
Simulation time 2238413754 ps
CPU time 16.89 seconds
Started Jan 14 01:12:13 PM PST 24
Finished Jan 14 01:12:30 PM PST 24
Peak memory 214424 kb
Host smart-86373c0e-30e9-4a52-8e4b-a69c3df0621b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479080704 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.3479080704
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.436890118
Short name T115
Test name
Test status
Simulation time 2006242138 ps
CPU time 16.32 seconds
Started Jan 14 01:12:15 PM PST 24
Finished Jan 14 01:12:34 PM PST 24
Peak memory 211104 kb
Host smart-7e2f8a59-19ed-4a3a-ba18-3f0ec88d6371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436890118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.436890118
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.1639808850
Short name T470
Test name
Test status
Simulation time 7754405445 ps
CPU time 105.48 seconds
Started Jan 14 01:12:21 PM PST 24
Finished Jan 14 01:14:11 PM PST 24
Peak memory 211280 kb
Host smart-c373e22c-cfa1-470b-bd42-dd1c9bc06390
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639808850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.1639808850
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.283960863
Short name T28
Test name
Test status
Simulation time 4348109757 ps
CPU time 17.27 seconds
Started Jan 14 01:12:22 PM PST 24
Finished Jan 14 01:12:43 PM PST 24
Peak memory 211216 kb
Host smart-c9d03668-e942-4e75-a5be-a9df261ed216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283960863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.283960863
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3209241414
Short name T107
Test name
Test status
Simulation time 1820426956 ps
CPU time 7.36 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:23 PM PST 24
Peak memory 210860 kb
Host smart-278c4bb3-8e4f-4330-b956-ece9770334bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209241414 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3209241414
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.1404360585
Short name T37
Test name
Test status
Simulation time 25924850369 ps
CPU time 161.47 seconds
Started Jan 14 01:19:59 PM PST 24
Finished Jan 14 01:22:43 PM PST 24
Peak memory 236372 kb
Host smart-6f52bb1e-506b-4697-9e18-f1d00f09c175
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404360585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.1404360585
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.414360956
Short name T188
Test name
Test status
Simulation time 2905642842 ps
CPU time 19.51 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:35 PM PST 24
Peak memory 211108 kb
Host smart-8d84274a-0f75-4c75-81f4-238e13273fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414360956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.414360956
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.3018517279
Short name T101
Test name
Test status
Simulation time 1785050593 ps
CPU time 15.66 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:31 PM PST 24
Peak memory 210884 kb
Host smart-5836f86d-d9d3-4469-ba15-0128e1a0631c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3018517279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.3018517279
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2022359096
Short name T54
Test name
Test status
Simulation time 1435424705 ps
CPU time 16.22 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:34 PM PST 24
Peak memory 213008 kb
Host smart-8a6fa717-bbde-4c93-a641-c22054e61bfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022359096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2022359096
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.3088741495
Short name T263
Test name
Test status
Simulation time 47875350187 ps
CPU time 6627.61 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 03:10:44 PM PST 24
Peak memory 235472 kb
Host smart-27e4def5-f720-4fff-b671-a73e8c50305b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088741495 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.3088741495
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2536147115
Short name T301
Test name
Test status
Simulation time 11703668381 ps
CPU time 28.64 seconds
Started Jan 14 01:20:08 PM PST 24
Finished Jan 14 01:20:45 PM PST 24
Peak memory 211404 kb
Host smart-57c51924-cc77-48cd-ada9-243948a57671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536147115 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2536147115
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.3386281818
Short name T333
Test name
Test status
Simulation time 5915042492 ps
CPU time 7.69 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:23 PM PST 24
Peak memory 210856 kb
Host smart-2f2a68bc-00e4-4e8a-b15c-e836a3c50bd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386281818 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.3386281818
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2165593806
Short name T43
Test name
Test status
Simulation time 189215726 ps
CPU time 114.53 seconds
Started Jan 14 01:20:05 PM PST 24
Finished Jan 14 01:22:03 PM PST 24
Peak memory 236196 kb
Host smart-2e4877f0-ff02-4964-af34-9ddc2650666c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165593806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2165593806
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.1918266003
Short name T102
Test name
Test status
Simulation time 2009907444 ps
CPU time 24.9 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 212400 kb
Host smart-105edc61-e05f-443c-a67c-bf7fd9e8e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918266003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.1918266003
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.2368506384
Short name T404
Test name
Test status
Simulation time 421306410 ps
CPU time 12.35 seconds
Started Jan 14 01:20:08 PM PST 24
Finished Jan 14 01:20:29 PM PST 24
Peak memory 219080 kb
Host smart-48ef4680-ad01-40e3-947f-91c3d92003e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368506384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.2368506384
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.4253274418
Short name T15
Test name
Test status
Simulation time 135269174728 ps
CPU time 1413.99 seconds
Started Jan 14 01:20:05 PM PST 24
Finished Jan 14 01:43:43 PM PST 24
Peak memory 235456 kb
Host smart-c2d66fa4-38f0-4048-9126-e2e351d5ba6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253274418 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.4253274418
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2618660870
Short name T6
Test name
Test status
Simulation time 1007817523 ps
CPU time 10.63 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:20:34 PM PST 24
Peak memory 210936 kb
Host smart-3b7cb1ad-d590-4188-9957-b7948bc4763e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618660870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2618660870
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3720221010
Short name T269
Test name
Test status
Simulation time 1981780024 ps
CPU time 119.18 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:22:23 PM PST 24
Peak memory 236356 kb
Host smart-cf3baeaa-2d19-4c1a-b634-bcc17d438ad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720221010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3720221010
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3054637018
Short name T345
Test name
Test status
Simulation time 97986389 ps
CPU time 5.89 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:32 PM PST 24
Peak memory 210824 kb
Host smart-c3cf6c82-f1e7-42cd-9781-cb9b71f0ec44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054637018 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3054637018
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.1354974842
Short name T5
Test name
Test status
Simulation time 17656219718 ps
CPU time 26.46 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:20:48 PM PST 24
Peak memory 212916 kb
Host smart-889f6563-ac33-4774-ae1d-44568de6c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354974842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1354974842
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.591309165
Short name T16
Test name
Test status
Simulation time 435806039 ps
CPU time 24.88 seconds
Started Jan 14 01:20:19 PM PST 24
Finished Jan 14 01:20:48 PM PST 24
Peak memory 215588 kb
Host smart-f9eedf14-3d27-4955-9d63-eca2a652a177
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591309165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.rom_ctrl_stress_all.591309165
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.1989206557
Short name T395
Test name
Test status
Simulation time 18807665947 ps
CPU time 16.03 seconds
Started Jan 14 01:20:25 PM PST 24
Finished Jan 14 01:20:42 PM PST 24
Peak memory 210920 kb
Host smart-c0b4961f-8c4e-4ea1-8a8d-a01dcdc4e7b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989206557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.1989206557
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3057473613
Short name T363
Test name
Test status
Simulation time 122406708220 ps
CPU time 431.26 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:27:35 PM PST 24
Peak memory 233384 kb
Host smart-b3662d34-30cb-4569-b85e-55f0a596acf4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057473613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3057473613
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2581823081
Short name T300
Test name
Test status
Simulation time 1405456445 ps
CPU time 18.84 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 210944 kb
Host smart-494ced31-d495-4eb9-b7f0-65d6eaeb3040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581823081 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2581823081
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1272423786
Short name T242
Test name
Test status
Simulation time 11002295138 ps
CPU time 11.88 seconds
Started Jan 14 01:20:18 PM PST 24
Finished Jan 14 01:20:35 PM PST 24
Peak memory 210844 kb
Host smart-4caeb51d-6176-4326-b859-d5a529bde7a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272423786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1272423786
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.308788667
Short name T381
Test name
Test status
Simulation time 6784524286 ps
CPU time 24.63 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:51 PM PST 24
Peak memory 213928 kb
Host smart-8a254fb3-4c61-40f6-b4e4-f895c0228cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308788667 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.308788667
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3332335429
Short name T391
Test name
Test status
Simulation time 522371886 ps
CPU time 8.09 seconds
Started Jan 14 01:20:21 PM PST 24
Finished Jan 14 01:20:32 PM PST 24
Peak memory 211496 kb
Host smart-4359b2bf-73db-4c6f-ae52-cecd3e54d42c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332335429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3332335429
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.2741160306
Short name T243
Test name
Test status
Simulation time 75907772795 ps
CPU time 1913.06 seconds
Started Jan 14 01:20:21 PM PST 24
Finished Jan 14 01:52:17 PM PST 24
Peak memory 235596 kb
Host smart-5ad8e3d0-1819-4434-9445-c8df737bb1f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741160306 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.2741160306
Directory /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.257419266
Short name T349
Test name
Test status
Simulation time 5755304302 ps
CPU time 13.3 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:20:38 PM PST 24
Peak memory 210960 kb
Host smart-ac2347cd-24f9-46df-b928-3c3bc404a116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257419266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.257419266
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2217402468
Short name T267
Test name
Test status
Simulation time 5955519570 ps
CPU time 103.18 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:22:08 PM PST 24
Peak memory 232220 kb
Host smart-b0c98b61-6ad5-4949-8e8c-eb73cff17dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217402468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_
corrupt_sig_fatal_chk.2217402468
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.3419319787
Short name T325
Test name
Test status
Simulation time 2006840344 ps
CPU time 16.64 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 210868 kb
Host smart-59a85a79-623f-41fa-b76a-68be7fb5c132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419319787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.3419319787
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.2070480297
Short name T353
Test name
Test status
Simulation time 1443390079 ps
CPU time 10.66 seconds
Started Jan 14 01:20:21 PM PST 24
Finished Jan 14 01:20:35 PM PST 24
Peak memory 211352 kb
Host smart-0dd44a7c-bff4-40b9-a1a0-99ef5751deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070480297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.2070480297
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.1941685190
Short name T304
Test name
Test status
Simulation time 23701666634 ps
CPU time 140.76 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:22:45 PM PST 24
Peak memory 219068 kb
Host smart-6ba2b617-5ef8-4da2-97f3-212d2832d89b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941685190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.1941685190
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.3277050284
Short name T298
Test name
Test status
Simulation time 87179850 ps
CPU time 4.61 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:20:29 PM PST 24
Peak memory 210940 kb
Host smart-4f08f656-54de-45f6-b937-cde0609de8c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277050284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.3277050284
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3965252485
Short name T8
Test name
Test status
Simulation time 40624721708 ps
CPU time 248 seconds
Started Jan 14 01:20:18 PM PST 24
Finished Jan 14 01:24:31 PM PST 24
Peak memory 237552 kb
Host smart-3a35c308-acc6-4ed8-9888-3f857d325a0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965252485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3965252485
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.887007157
Short name T329
Test name
Test status
Simulation time 15212175217 ps
CPU time 23.71 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:49 PM PST 24
Peak memory 211200 kb
Host smart-ee50bc98-d1f9-44c7-9b1c-f29d7ec685ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887007157 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.887007157
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3010285681
Short name T378
Test name
Test status
Simulation time 922417588 ps
CPU time 7.27 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:33 PM PST 24
Peak memory 210848 kb
Host smart-bcc049a6-1084-4226-90e3-7f8bd72f114e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010285681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3010285681
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2745466037
Short name T165
Test name
Test status
Simulation time 3606325144 ps
CPU time 40.32 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:21:06 PM PST 24
Peak memory 211940 kb
Host smart-d180dafa-6dfd-46a9-a39e-683a20bd1968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745466037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2745466037
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.171292714
Short name T396
Test name
Test status
Simulation time 80530709639 ps
CPU time 88.02 seconds
Started Jan 14 01:20:21 PM PST 24
Finished Jan 14 01:21:52 PM PST 24
Peak memory 214552 kb
Host smart-cf15b723-07f4-4e5b-b731-e2d0e2664e90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171292714 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.rom_ctrl_stress_all.171292714
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.1359995560
Short name T336
Test name
Test status
Simulation time 1911800758 ps
CPU time 15.19 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 210824 kb
Host smart-42710778-73cc-4e53-8c07-4737163005d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359995560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1359995560
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.636700220
Short name T62
Test name
Test status
Simulation time 47992613805 ps
CPU time 349.48 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:26:19 PM PST 24
Peak memory 225364 kb
Host smart-67989a72-dcbd-437f-b513-91934ef505fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636700220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.636700220
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1864164448
Short name T398
Test name
Test status
Simulation time 363121710 ps
CPU time 9.85 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:20:39 PM PST 24
Peak memory 211076 kb
Host smart-3ae149a3-d728-4924-8888-0d4192700eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864164448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1864164448
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.3559176568
Short name T216
Test name
Test status
Simulation time 1471483424 ps
CPU time 8.49 seconds
Started Jan 14 01:20:18 PM PST 24
Finished Jan 14 01:20:31 PM PST 24
Peak memory 210872 kb
Host smart-e4352c3f-677e-41c4-923a-3d0f637e3bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559176568 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.3559176568
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.1579629540
Short name T167
Test name
Test status
Simulation time 669998100 ps
CPU time 10.85 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 212620 kb
Host smart-5422485e-db7d-40ee-bcad-ece766e6fcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579629540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.1579629540
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.2283795364
Short name T211
Test name
Test status
Simulation time 292816106 ps
CPU time 17.69 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:20:42 PM PST 24
Peak memory 215160 kb
Host smart-52f98794-cd25-4cb3-b944-bdf61745c064
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283795364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.2283795364
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.299150645
Short name T19
Test name
Test status
Simulation time 46210726267 ps
CPU time 1953.3 seconds
Started Jan 14 01:20:26 PM PST 24
Finished Jan 14 01:53:00 PM PST 24
Peak memory 232080 kb
Host smart-f7f7e799-a114-4388-8b2b-3048eb835fb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299150645 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.299150645
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.443200648
Short name T220
Test name
Test status
Simulation time 4170512533 ps
CPU time 17.29 seconds
Started Jan 14 01:20:26 PM PST 24
Finished Jan 14 01:20:44 PM PST 24
Peak memory 210900 kb
Host smart-a2271601-1063-4320-b57f-08a118c4bf67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443200648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.443200648
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1279236541
Short name T271
Test name
Test status
Simulation time 166865352484 ps
CPU time 297.46 seconds
Started Jan 14 01:20:32 PM PST 24
Finished Jan 14 01:25:31 PM PST 24
Peak memory 212040 kb
Host smart-dacaa76f-3489-4a67-b0f5-608cf4fbefa9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279236541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1279236541
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1658696120
Short name T215
Test name
Test status
Simulation time 8545800758 ps
CPU time 23.86 seconds
Started Jan 14 01:20:30 PM PST 24
Finished Jan 14 01:20:54 PM PST 24
Peak memory 211624 kb
Host smart-91b4bd43-d5ab-439e-baa4-d8a202283b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658696120 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1658696120
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1372884452
Short name T270
Test name
Test status
Simulation time 2437534300 ps
CPU time 15.72 seconds
Started Jan 14 01:20:23 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 210836 kb
Host smart-e3a311b4-6f93-4d57-b446-115537613293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372884452 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1372884452
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3362036301
Short name T259
Test name
Test status
Simulation time 7560105692 ps
CPU time 37.26 seconds
Started Jan 14 01:20:23 PM PST 24
Finished Jan 14 01:21:02 PM PST 24
Peak memory 213492 kb
Host smart-42f02cc4-57c7-4e23-a660-af8f2581b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362036301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3362036301
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.892576225
Short name T360
Test name
Test status
Simulation time 2231430690 ps
CPU time 42.15 seconds
Started Jan 14 01:20:33 PM PST 24
Finished Jan 14 01:21:16 PM PST 24
Peak memory 215260 kb
Host smart-fbf56430-2293-44de-9d5f-cf89288ed88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892576225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 15.rom_ctrl_stress_all.892576225
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3418444809
Short name T375
Test name
Test status
Simulation time 23499474154 ps
CPU time 445.28 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:27:55 PM PST 24
Peak memory 232844 kb
Host smart-aea21f6e-7473-40b0-a91c-997a46f55ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418444809 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.3418444809
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1781272027
Short name T346
Test name
Test status
Simulation time 343163835 ps
CPU time 5.62 seconds
Started Jan 14 01:20:32 PM PST 24
Finished Jan 14 01:20:39 PM PST 24
Peak memory 210800 kb
Host smart-1509cbb9-bd8a-46b0-af68-53e1b7b31d1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781272027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1781272027
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.3418075557
Short name T1
Test name
Test status
Simulation time 42911525985 ps
CPU time 228.45 seconds
Started Jan 14 01:20:25 PM PST 24
Finished Jan 14 01:24:15 PM PST 24
Peak memory 224156 kb
Host smart-dd8d3e5b-cfd0-4890-9261-c565e2e752d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418075557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.3418075557
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2270659694
Short name T292
Test name
Test status
Simulation time 333688207 ps
CPU time 9.91 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:20:45 PM PST 24
Peak memory 210968 kb
Host smart-9ae91697-d826-4c8d-90f3-cae1e522884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270659694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2270659694
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.948809859
Short name T193
Test name
Test status
Simulation time 3511623011 ps
CPU time 15.62 seconds
Started Jan 14 01:20:30 PM PST 24
Finished Jan 14 01:20:47 PM PST 24
Peak memory 210936 kb
Host smart-95a086a6-1dbd-4b7c-8e65-83bdb1ddd0dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948809859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.948809859
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.3477973808
Short name T184
Test name
Test status
Simulation time 376471839 ps
CPU time 10.64 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:36 PM PST 24
Peak memory 212520 kb
Host smart-90eba2d7-6c81-45aa-992f-8406e2769207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477973808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.3477973808
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3300802055
Short name T387
Test name
Test status
Simulation time 15553250830 ps
CPU time 41.81 seconds
Started Jan 14 01:20:31 PM PST 24
Finished Jan 14 01:21:14 PM PST 24
Peak memory 216048 kb
Host smart-f726c810-bbde-436b-9f7f-4387bad0f238
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300802055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3300802055
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1819420486
Short name T260
Test name
Test status
Simulation time 23201571886 ps
CPU time 2125.75 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:55:55 PM PST 24
Peak memory 227364 kb
Host smart-f230ca75-1139-4d7d-9ea1-b82e58be14d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819420486 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1819420486
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3629026886
Short name T223
Test name
Test status
Simulation time 18349875627 ps
CPU time 15.92 seconds
Started Jan 14 01:20:32 PM PST 24
Finished Jan 14 01:20:49 PM PST 24
Peak memory 210860 kb
Host smart-8fc8d522-9fb3-43cc-8539-4f6af2a42fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629026886 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3629026886
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.433915734
Short name T361
Test name
Test status
Simulation time 262940668689 ps
CPU time 659.08 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:31:25 PM PST 24
Peak memory 212236 kb
Host smart-d89eb7cd-889b-4695-a986-a103f0c89f2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433915734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_c
orrupt_sig_fatal_chk.433915734
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2005994436
Short name T403
Test name
Test status
Simulation time 758160298 ps
CPU time 14.99 seconds
Started Jan 14 01:20:30 PM PST 24
Finished Jan 14 01:20:46 PM PST 24
Peak memory 211176 kb
Host smart-28c0e2f1-838b-4755-815e-440380742fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005994436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2005994436
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.2645158802
Short name T365
Test name
Test status
Simulation time 7870483980 ps
CPU time 16.72 seconds
Started Jan 14 01:20:21 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 210768 kb
Host smart-03d935f4-ca3b-4264-9d5d-a770825d68c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2645158802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.2645158802
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.3091686484
Short name T308
Test name
Test status
Simulation time 281300370 ps
CPU time 11.91 seconds
Started Jan 14 01:20:31 PM PST 24
Finished Jan 14 01:20:44 PM PST 24
Peak memory 212376 kb
Host smart-456cf7ad-417c-49e0-9d2c-29af66b0f3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091686484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.3091686484
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.705862284
Short name T407
Test name
Test status
Simulation time 44525642361 ps
CPU time 87.95 seconds
Started Jan 14 01:20:29 PM PST 24
Finished Jan 14 01:21:58 PM PST 24
Peak memory 218412 kb
Host smart-b38ba974-021a-4a74-aabb-991e3e765c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705862284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.rom_ctrl_stress_all.705862284
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2332863457
Short name T236
Test name
Test status
Simulation time 606440215 ps
CPU time 8.05 seconds
Started Jan 14 01:20:29 PM PST 24
Finished Jan 14 01:20:38 PM PST 24
Peak memory 210856 kb
Host smart-ac5f61dc-0c09-4cab-8394-701f6d4e1131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332863457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2332863457
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2347281895
Short name T289
Test name
Test status
Simulation time 34097774412 ps
CPU time 335.37 seconds
Started Jan 14 01:20:29 PM PST 24
Finished Jan 14 01:26:05 PM PST 24
Peak memory 237516 kb
Host smart-ec49bb4d-0227-40b5-92b3-527e25bf66e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347281895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2347281895
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4198587531
Short name T2
Test name
Test status
Simulation time 17623515198 ps
CPU time 30.24 seconds
Started Jan 14 01:20:33 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 211144 kb
Host smart-beb18419-b08b-4382-a628-4c4f881730da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198587531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4198587531
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.816973281
Short name T424
Test name
Test status
Simulation time 2018015846 ps
CPU time 16.42 seconds
Started Jan 14 01:20:29 PM PST 24
Finished Jan 14 01:20:46 PM PST 24
Peak memory 209984 kb
Host smart-5c5e6c1e-a9d7-4330-9903-24a946a43249
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816973281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.816973281
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.1843879428
Short name T248
Test name
Test status
Simulation time 9702230543 ps
CPU time 22.12 seconds
Started Jan 14 01:20:33 PM PST 24
Finished Jan 14 01:20:56 PM PST 24
Peak memory 213116 kb
Host smart-3718d501-6a9b-4746-a341-84fa79356fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843879428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1843879428
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.3274326883
Short name T13
Test name
Test status
Simulation time 1374087498 ps
CPU time 19.33 seconds
Started Jan 14 01:20:30 PM PST 24
Finished Jan 14 01:20:50 PM PST 24
Peak memory 210780 kb
Host smart-7c3cbc9b-2c28-4ba3-b45b-2eeb7a6358d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274326883 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.3274326883
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.959670500
Short name T23
Test name
Test status
Simulation time 5550824547 ps
CPU time 13.23 seconds
Started Jan 14 01:20:35 PM PST 24
Finished Jan 14 01:20:49 PM PST 24
Peak memory 210948 kb
Host smart-9f01292a-a0d4-4694-8706-f87368bd4fca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959670500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.959670500
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.776606637
Short name T377
Test name
Test status
Simulation time 5149337986 ps
CPU time 163.95 seconds
Started Jan 14 01:20:30 PM PST 24
Finished Jan 14 01:23:15 PM PST 24
Peak memory 230460 kb
Host smart-bff7b36e-503f-429b-b58d-3954edaf86d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776606637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_c
orrupt_sig_fatal_chk.776606637
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.941082094
Short name T290
Test name
Test status
Simulation time 3757568056 ps
CPU time 32.15 seconds
Started Jan 14 01:20:28 PM PST 24
Finished Jan 14 01:21:02 PM PST 24
Peak memory 211024 kb
Host smart-8a130f0e-007f-437f-96ab-bfdda28407f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941082094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.941082094
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.3163662256
Short name T328
Test name
Test status
Simulation time 3315923291 ps
CPU time 15.87 seconds
Started Jan 14 01:20:31 PM PST 24
Finished Jan 14 01:20:48 PM PST 24
Peak memory 210928 kb
Host smart-f571ff59-762c-457b-a521-c978d8dfdc45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3163662256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.3163662256
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3154391606
Short name T337
Test name
Test status
Simulation time 6462086272 ps
CPU time 28.63 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:21:04 PM PST 24
Peak memory 213212 kb
Host smart-4039364e-9142-4c11-8c58-c3fa05e0e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154391606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3154391606
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.3905862995
Short name T17
Test name
Test status
Simulation time 291637705720 ps
CPU time 7234.21 seconds
Started Jan 14 01:20:37 PM PST 24
Finished Jan 14 03:21:12 PM PST 24
Peak memory 239824 kb
Host smart-c9d9f29a-ce1d-4199-aadc-c8365a152df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905862995 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.3905862995
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.619547039
Short name T217
Test name
Test status
Simulation time 5239836438 ps
CPU time 11.92 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:29 PM PST 24
Peak memory 210944 kb
Host smart-54f32532-a6ef-47c1-8b5c-23a0203b2d1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619547039 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.619547039
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.924380686
Short name T57
Test name
Test status
Simulation time 88519300921 ps
CPU time 240.69 seconds
Started Jan 14 01:20:05 PM PST 24
Finished Jan 14 01:24:10 PM PST 24
Peak memory 236340 kb
Host smart-42791848-a504-405c-ba99-eb1c9b5e0899
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924380686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.924380686
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.801722311
Short name T210
Test name
Test status
Simulation time 1187054039 ps
CPU time 12.71 seconds
Started Jan 14 01:20:04 PM PST 24
Finished Jan 14 01:20:22 PM PST 24
Peak memory 210820 kb
Host smart-6befc4ee-a0e1-40a2-a4f6-a7668c7d08da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801722311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.801722311
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4028219026
Short name T52
Test name
Test status
Simulation time 1863442561 ps
CPU time 67.83 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 235728 kb
Host smart-b6fe6f7f-f5c3-45fa-a441-4262ec5b9474
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028219026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4028219026
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3788782048
Short name T185
Test name
Test status
Simulation time 14253223950 ps
CPU time 37.01 seconds
Started Jan 14 01:20:04 PM PST 24
Finished Jan 14 01:20:46 PM PST 24
Peak memory 213004 kb
Host smart-7bb3bd9e-5a17-486d-930a-270ac46e6054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788782048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3788782048
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1705413939
Short name T357
Test name
Test status
Simulation time 9296070701 ps
CPU time 34.92 seconds
Started Jan 14 01:20:07 PM PST 24
Finished Jan 14 01:20:50 PM PST 24
Peak memory 213716 kb
Host smart-8b979658-620c-46d2-b78f-cc8b1a6993b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705413939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1705413939
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1991947710
Short name T340
Test name
Test status
Simulation time 171731626 ps
CPU time 4.41 seconds
Started Jan 14 01:20:36 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 210872 kb
Host smart-55d213d4-2066-4876-8efd-f207ac001416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991947710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1991947710
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.4073832565
Short name T354
Test name
Test status
Simulation time 74335790943 ps
CPU time 272.81 seconds
Started Jan 14 01:20:31 PM PST 24
Finished Jan 14 01:25:05 PM PST 24
Peak memory 236748 kb
Host smart-827af2b7-18dd-4ae8-b8ca-7e5f91fcc1e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073832565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.4073832565
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.589886603
Short name T405
Test name
Test status
Simulation time 3422879359 ps
CPU time 29.67 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 211104 kb
Host smart-4aea2b0b-0e55-4745-9c82-80364053f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589886603 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.589886603
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.4048757577
Short name T316
Test name
Test status
Simulation time 1047616424 ps
CPU time 11.54 seconds
Started Jan 14 01:20:45 PM PST 24
Finished Jan 14 01:20:57 PM PST 24
Peak memory 210896 kb
Host smart-f5d75274-3411-4987-9185-68abbc5460a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4048757577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.4048757577
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.328509898
Short name T373
Test name
Test status
Simulation time 743786596 ps
CPU time 10.63 seconds
Started Jan 14 01:20:42 PM PST 24
Finished Jan 14 01:20:53 PM PST 24
Peak memory 212840 kb
Host smart-d9576e55-0ae0-4d7c-8c67-9684baf91c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328509898 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.328509898
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.4293243979
Short name T409
Test name
Test status
Simulation time 31045089699 ps
CPU time 73.62 seconds
Started Jan 14 01:20:35 PM PST 24
Finished Jan 14 01:21:49 PM PST 24
Peak memory 219080 kb
Host smart-0f808106-09d0-43f0-b42d-f08218329d83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293243979 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.4293243979
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.1937778090
Short name T312
Test name
Test status
Simulation time 60390200798 ps
CPU time 1924.32 seconds
Started Jan 14 01:20:35 PM PST 24
Finished Jan 14 01:52:40 PM PST 24
Peak memory 235392 kb
Host smart-689ff4b7-c458-4d77-ac21-34fe953f956f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937778090 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.1937778090
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1421518919
Short name T303
Test name
Test status
Simulation time 4541075439 ps
CPU time 12.15 seconds
Started Jan 14 01:20:33 PM PST 24
Finished Jan 14 01:20:46 PM PST 24
Peak memory 211040 kb
Host smart-f21c73eb-e17c-4743-97b4-0af08e38872c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421518919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1421518919
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.18640951
Short name T416
Test name
Test status
Simulation time 25145657757 ps
CPU time 186.31 seconds
Started Jan 14 01:20:31 PM PST 24
Finished Jan 14 01:23:38 PM PST 24
Peak memory 232904 kb
Host smart-ed0f31ee-c174-4914-ab46-e0ec88db3805
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640951 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_co
rrupt_sig_fatal_chk.18640951
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1875670688
Short name T275
Test name
Test status
Simulation time 1891834943 ps
CPU time 21.23 seconds
Started Jan 14 01:20:35 PM PST 24
Finished Jan 14 01:20:57 PM PST 24
Peak memory 211068 kb
Host smart-6d91d90b-f83c-4366-a716-efa84114a356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875670688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1875670688
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1758228530
Short name T202
Test name
Test status
Simulation time 6900789641 ps
CPU time 16.69 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:20:52 PM PST 24
Peak memory 210840 kb
Host smart-0d303845-82b4-4765-8b5f-6ebdfe80778d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1758228530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1758228530
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.3379100300
Short name T169
Test name
Test status
Simulation time 23011257438 ps
CPU time 35.87 seconds
Started Jan 14 01:20:37 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 213696 kb
Host smart-aa7d9667-d258-4757-8946-7067f528c188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379100300 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3379100300
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3172751441
Short name T295
Test name
Test status
Simulation time 9557445548 ps
CPU time 37.54 seconds
Started Jan 14 01:20:34 PM PST 24
Finished Jan 14 01:21:12 PM PST 24
Peak memory 215784 kb
Host smart-abe338ac-90c6-45d9-a9dd-35783d24bc12
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172751441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3172751441
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.713093949
Short name T247
Test name
Test status
Simulation time 4141217595 ps
CPU time 16.42 seconds
Started Jan 14 01:20:52 PM PST 24
Finished Jan 14 01:21:09 PM PST 24
Peak memory 210984 kb
Host smart-b48f18d1-5809-4b69-88e8-245b4e934f46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713093949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.713093949
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.1239365415
Short name T322
Test name
Test status
Simulation time 5168417697 ps
CPU time 155.4 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 01:23:27 PM PST 24
Peak memory 237672 kb
Host smart-43cbc447-df03-48a9-9d3a-7a1aabcebaac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239365415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.1239365415
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.22651665
Short name T35
Test name
Test status
Simulation time 172505604 ps
CPU time 10.08 seconds
Started Jan 14 01:20:43 PM PST 24
Finished Jan 14 01:20:54 PM PST 24
Peak memory 211180 kb
Host smart-8c8da4d8-6132-458c-b58f-80b7f8b09da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22651665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.22651665
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3549525175
Short name T244
Test name
Test status
Simulation time 959864836 ps
CPU time 8.58 seconds
Started Jan 14 01:20:38 PM PST 24
Finished Jan 14 01:20:48 PM PST 24
Peak memory 210836 kb
Host smart-e35cbf41-c911-4e59-88b5-4b21cb07dfd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549525175 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3549525175
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3606184746
Short name T218
Test name
Test status
Simulation time 3386840343 ps
CPU time 29.98 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 212024 kb
Host smart-11e8fc03-5466-48b1-aa6b-ed4b329c4cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606184746 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3606184746
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.6551775
Short name T392
Test name
Test status
Simulation time 629785353 ps
CPU time 36.38 seconds
Started Jan 14 01:20:50 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 216496 kb
Host smart-036e4cd0-84d8-438b-91f3-81c8ce3d8ce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6551775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UV
M_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.rom_ctrl_stress_all.6551775
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.19502601
Short name T382
Test name
Test status
Simulation time 150402419333 ps
CPU time 1032.05 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:38:07 PM PST 24
Peak memory 235504 kb
Host smart-991b1691-bb93-472f-8ca3-01340c7ff8ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19502601 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.19502601
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.1658017118
Short name T283
Test name
Test status
Simulation time 6194618856 ps
CPU time 12.92 seconds
Started Jan 14 01:20:52 PM PST 24
Finished Jan 14 01:21:06 PM PST 24
Peak memory 211008 kb
Host smart-2043a662-9cbc-44f8-95c9-57dce205d2ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658017118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.1658017118
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.733228881
Short name T293
Test name
Test status
Simulation time 28968027317 ps
CPU time 314.95 seconds
Started Jan 14 01:20:42 PM PST 24
Finished Jan 14 01:25:58 PM PST 24
Peak memory 237440 kb
Host smart-cff2b79b-69eb-4a0f-9589-2974a6154313
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733228881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c
orrupt_sig_fatal_chk.733228881
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.840833689
Short name T182
Test name
Test status
Simulation time 7144407950 ps
CPU time 21.47 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:15 PM PST 24
Peak memory 211588 kb
Host smart-e833f7ca-c87b-41b0-adae-a280b5adb793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840833689 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.840833689
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.2522296002
Short name T4
Test name
Test status
Simulation time 346682095 ps
CPU time 8.3 seconds
Started Jan 14 01:20:44 PM PST 24
Finished Jan 14 01:20:53 PM PST 24
Peak memory 210864 kb
Host smart-e712b4b2-d38f-4159-8c0a-be6954720a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522296002 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.2522296002
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1067755126
Short name T334
Test name
Test status
Simulation time 2140624067 ps
CPU time 27.25 seconds
Started Jan 14 01:20:38 PM PST 24
Finished Jan 14 01:21:06 PM PST 24
Peak memory 212704 kb
Host smart-70683da5-1820-4b97-b302-1a98acc282b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067755126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1067755126
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.4283073045
Short name T174
Test name
Test status
Simulation time 11791198784 ps
CPU time 50.35 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:21:47 PM PST 24
Peak memory 216460 kb
Host smart-90303423-33fb-4b58-a102-11807694c191
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283073045 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.4283073045
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.838893176
Short name T385
Test name
Test status
Simulation time 180460973672 ps
CPU time 2487.99 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 02:02:23 PM PST 24
Peak memory 235516 kb
Host smart-f3dc2eae-6b86-4a47-85e4-1149835c2291
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838893176 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.838893176
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.2513348309
Short name T240
Test name
Test status
Simulation time 557602334 ps
CPU time 7.98 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:03 PM PST 24
Peak memory 210968 kb
Host smart-152ad015-2bae-4915-a027-ec38c007cbb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513348309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2513348309
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2747805897
Short name T55
Test name
Test status
Simulation time 3205756729 ps
CPU time 155.51 seconds
Started Jan 14 01:20:59 PM PST 24
Finished Jan 14 01:23:35 PM PST 24
Peak memory 228100 kb
Host smart-67b31f00-b136-43f5-a2a5-46508df2fd3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747805897 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2747805897
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.2670710074
Short name T164
Test name
Test status
Simulation time 3777645286 ps
CPU time 32.45 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:28 PM PST 24
Peak memory 211144 kb
Host smart-56a87de4-39df-4577-9706-36027308d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670710074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.2670710074
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.576312005
Short name T296
Test name
Test status
Simulation time 4874910944 ps
CPU time 12.27 seconds
Started Jan 14 01:20:38 PM PST 24
Finished Jan 14 01:20:51 PM PST 24
Peak memory 210880 kb
Host smart-891aeef8-fcfb-4cb0-a016-840c2afcfca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576312005 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.576312005
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.3694724173
Short name T355
Test name
Test status
Simulation time 3131648709 ps
CPU time 26.36 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:21 PM PST 24
Peak memory 212152 kb
Host smart-6470201e-a7e3-4939-a7a8-27ae70e35ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694724173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.3694724173
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.2630257680
Short name T376
Test name
Test status
Simulation time 101366498899 ps
CPU time 51.67 seconds
Started Jan 14 01:20:41 PM PST 24
Finished Jan 14 01:21:34 PM PST 24
Peak memory 216368 kb
Host smart-bc0a02d3-8c4c-447f-a5e7-f8f8213e7a62
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630257680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 24.rom_ctrl_stress_all.2630257680
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2777563260
Short name T276
Test name
Test status
Simulation time 68533569666 ps
CPU time 2844.72 seconds
Started Jan 14 01:20:44 PM PST 24
Finished Jan 14 02:08:10 PM PST 24
Peak memory 248832 kb
Host smart-29a4c249-c90b-4f4d-bce6-197a8fd62b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777563260 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2777563260
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.83676605
Short name T254
Test name
Test status
Simulation time 2227773361 ps
CPU time 11.28 seconds
Started Jan 14 01:20:40 PM PST 24
Finished Jan 14 01:20:52 PM PST 24
Peak memory 210888 kb
Host smart-dbb5b5da-352b-4c3d-b86f-545871cd831c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83676605 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.83676605
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.3438291589
Short name T320
Test name
Test status
Simulation time 132343274184 ps
CPU time 299.17 seconds
Started Jan 14 01:20:45 PM PST 24
Finished Jan 14 01:25:45 PM PST 24
Peak memory 237348 kb
Host smart-ccec1578-8961-4f85-bf5b-ccec0222f228
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438291589 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.3438291589
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3817933052
Short name T39
Test name
Test status
Simulation time 9039918263 ps
CPU time 21 seconds
Started Jan 14 01:20:55 PM PST 24
Finished Jan 14 01:21:17 PM PST 24
Peak memory 210912 kb
Host smart-7034989e-7e4d-4967-9c33-7e25f7c2f708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817933052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3817933052
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2295661677
Short name T203
Test name
Test status
Simulation time 5463065578 ps
CPU time 13.94 seconds
Started Jan 14 01:20:52 PM PST 24
Finished Jan 14 01:21:06 PM PST 24
Peak memory 210940 kb
Host smart-1d0ceeb8-6fab-4461-81d4-7ae4d0b658ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295661677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2295661677
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.3486647559
Short name T374
Test name
Test status
Simulation time 6412669614 ps
CPU time 33.56 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:29 PM PST 24
Peak memory 213776 kb
Host smart-b3a1e2dc-1c74-4941-b070-b15c4d948ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486647559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.3486647559
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.79096712
Short name T399
Test name
Test status
Simulation time 2068347773 ps
CPU time 14.89 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:09 PM PST 24
Peak memory 210768 kb
Host smart-a3bb7c8e-045b-4e0a-a3c1-f4d884f5774c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79096712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 25.rom_ctrl_stress_all.79096712
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.3920378360
Short name T339
Test name
Test status
Simulation time 55340259373 ps
CPU time 382.28 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 01:27:14 PM PST 24
Peak memory 227364 kb
Host smart-d9053e18-dbf8-4fb6-9d0e-b3ab647a4105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920378360 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.3920378360
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.424247930
Short name T410
Test name
Test status
Simulation time 908406392 ps
CPU time 10.07 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:04 PM PST 24
Peak memory 210960 kb
Host smart-5e32f724-4161-4648-a3d1-1e0cc92de4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424247930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.424247930
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.3472825237
Short name T228
Test name
Test status
Simulation time 78536515431 ps
CPU time 380.35 seconds
Started Jan 14 01:20:43 PM PST 24
Finished Jan 14 01:27:04 PM PST 24
Peak memory 224288 kb
Host smart-d39ff991-2cc7-4837-80c2-324dec74db54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472825237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.3472825237
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2795968469
Short name T262
Test name
Test status
Simulation time 15656239913 ps
CPU time 33.9 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:31 PM PST 24
Peak memory 210472 kb
Host smart-7cfc1d29-a984-4615-b788-d3ec3f9f96d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795968469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2795968469
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.3491464448
Short name T195
Test name
Test status
Simulation time 7316034618 ps
CPU time 11.53 seconds
Started Jan 14 01:20:40 PM PST 24
Finished Jan 14 01:20:53 PM PST 24
Peak memory 210812 kb
Host smart-e0966365-74ec-4e21-ab5b-68cfd7c34c14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491464448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.3491464448
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.2817936204
Short name T171
Test name
Test status
Simulation time 14954570085 ps
CPU time 32.31 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:30 PM PST 24
Peak memory 212916 kb
Host smart-8e2a65fa-b164-4498-a848-8164bd8dcad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817936204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.2817936204
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.4084279856
Short name T200
Test name
Test status
Simulation time 1232432171 ps
CPU time 20.53 seconds
Started Jan 14 01:20:47 PM PST 24
Finished Jan 14 01:21:08 PM PST 24
Peak memory 214032 kb
Host smart-72f8894f-6101-49a5-abce-52f26bf40806
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084279856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.4084279856
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.3407960902
Short name T257
Test name
Test status
Simulation time 47794488951 ps
CPU time 6824.47 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 03:14:43 PM PST 24
Peak memory 240152 kb
Host smart-ba3673c4-a885-42f9-a285-9db1d86d0cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407960902 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.3407960902
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.2082834781
Short name T351
Test name
Test status
Simulation time 594022361 ps
CPU time 4.54 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 210056 kb
Host smart-c4af760b-59c4-4814-adef-f34b99b5664a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082834781 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.2082834781
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3291146195
Short name T311
Test name
Test status
Simulation time 1841244217 ps
CPU time 107.12 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:22:45 PM PST 24
Peak memory 212096 kb
Host smart-dc4a6025-016e-45aa-ac1b-d347c4998635
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291146195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.3291146195
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.1665924400
Short name T350
Test name
Test status
Simulation time 343075121 ps
CPU time 9.99 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:08 PM PST 24
Peak memory 212084 kb
Host smart-ad472efd-d451-44cc-aff8-df08b95ad2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665924400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.1665924400
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1458704432
Short name T272
Test name
Test status
Simulation time 385416867 ps
CPU time 5.44 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:04 PM PST 24
Peak memory 210844 kb
Host smart-373d0a6b-3b7e-4b49-b1f7-65c077d0486c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458704432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1458704432
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2658085213
Short name T253
Test name
Test status
Simulation time 1098440004 ps
CPU time 11.93 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 212528 kb
Host smart-bfe20b12-9e3f-41b3-bc8c-f8e69ed9d817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658085213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2658085213
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.3121682704
Short name T176
Test name
Test status
Simulation time 444713923 ps
CPU time 14.97 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 212036 kb
Host smart-faad7a86-ac6f-44c4-8e52-1384ee619233
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121682704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.3121682704
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1377037724
Short name T172
Test name
Test status
Simulation time 73825234212 ps
CPU time 2659.68 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 02:05:18 PM PST 24
Peak memory 247216 kb
Host smart-181e7195-709e-4275-9704-f263679bb26e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377037724 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1377037724
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.4221780747
Short name T412
Test name
Test status
Simulation time 784656401 ps
CPU time 6.55 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 210860 kb
Host smart-76dd81b6-1e32-44ac-8043-c1aed5c5ca68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221780747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.4221780747
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.261122485
Short name T3
Test name
Test status
Simulation time 11420896343 ps
CPU time 130.02 seconds
Started Jan 14 01:21:03 PM PST 24
Finished Jan 14 01:23:15 PM PST 24
Peak memory 233344 kb
Host smart-5042c974-26a2-416d-87dd-6a1cb0877d69
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261122485 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.261122485
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.1452874944
Short name T239
Test name
Test status
Simulation time 829299258 ps
CPU time 12.76 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:19 PM PST 24
Peak memory 211004 kb
Host smart-f43a8b72-e554-4936-b7d6-25710e1c2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452874944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.1452874944
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3689237321
Short name T255
Test name
Test status
Simulation time 370968914 ps
CPU time 6.19 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 210816 kb
Host smart-ad0c31fa-c8f7-4584-9e8e-3df076aeb309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3689237321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3689237321
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.2414480312
Short name T426
Test name
Test status
Simulation time 7820642737 ps
CPU time 33.03 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:21:33 PM PST 24
Peak memory 213636 kb
Host smart-89088275-244a-4ad7-ad7d-5ff4e8e88464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414480312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.2414480312
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.1223231579
Short name T347
Test name
Test status
Simulation time 3498530022 ps
CPU time 39.29 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:38 PM PST 24
Peak memory 212788 kb
Host smart-d0a45cb0-0f0c-4523-a70a-f01ee8c7002b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223231579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.1223231579
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2112033146
Short name T251
Test name
Test status
Simulation time 5691590246 ps
CPU time 15.39 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 211048 kb
Host smart-784ae65a-e43d-431d-a1b6-c63346047c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112033146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2112033146
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.980703961
Short name T265
Test name
Test status
Simulation time 76004850105 ps
CPU time 347.26 seconds
Started Jan 14 01:20:55 PM PST 24
Finished Jan 14 01:26:43 PM PST 24
Peak memory 236436 kb
Host smart-9f786057-e7c8-4cab-bb7e-a587c32a15a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980703961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_c
orrupt_sig_fatal_chk.980703961
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.2212967489
Short name T207
Test name
Test status
Simulation time 8182127462 ps
CPU time 20.48 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:31 PM PST 24
Peak memory 211324 kb
Host smart-15730121-c357-4117-a638-922b9e1625b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212967489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.2212967489
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.4071323088
Short name T305
Test name
Test status
Simulation time 3933351596 ps
CPU time 10.06 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:21 PM PST 24
Peak memory 210972 kb
Host smart-31d9feda-7ffe-47ae-ac3e-c6e0d6e13149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071323088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.4071323088
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.3756320859
Short name T224
Test name
Test status
Simulation time 445171225 ps
CPU time 13.13 seconds
Started Jan 14 01:20:59 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 212100 kb
Host smart-c4cc581b-4bbd-482b-96d9-bc201da5a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756320859 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.3756320859
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.3278281283
Short name T400
Test name
Test status
Simulation time 36429414857 ps
CPU time 50.49 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:48 PM PST 24
Peak memory 216324 kb
Host smart-ca1df3af-19a2-4c3e-ab06-f4e82ef9916f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278281283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.3278281283
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1080969171
Short name T18
Test name
Test status
Simulation time 50089883303 ps
CPU time 5585.49 seconds
Started Jan 14 01:21:09 PM PST 24
Finished Jan 14 02:54:16 PM PST 24
Peak memory 235572 kb
Host smart-eca83452-b7cb-4640-a31a-8b2bbbb75e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080969171 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1080969171
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.1562701420
Short name T160
Test name
Test status
Simulation time 348327394 ps
CPU time 4.6 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:23 PM PST 24
Peak memory 210952 kb
Host smart-6db90338-cb4f-4ee7-a246-7297d392437d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562701420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.1562701420
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2113121095
Short name T106
Test name
Test status
Simulation time 7962098562 ps
CPU time 135.67 seconds
Started Jan 14 01:20:00 PM PST 24
Finished Jan 14 01:22:19 PM PST 24
Peak memory 237360 kb
Host smart-adabf258-f9c1-4178-86f9-ebcd45197625
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113121095 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2113121095
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.1791254419
Short name T227
Test name
Test status
Simulation time 13318338635 ps
CPU time 28.55 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:46 PM PST 24
Peak memory 211204 kb
Host smart-7cb8a62e-cd7d-48cc-aea6-1893b73e73f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791254419 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.1791254419
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.4172511006
Short name T189
Test name
Test status
Simulation time 2623669711 ps
CPU time 9.3 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:28 PM PST 24
Peak memory 210876 kb
Host smart-c984bff7-daa5-489d-af19-3f093606b87d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4172511006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.4172511006
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.1092995015
Short name T246
Test name
Test status
Simulation time 3528234909 ps
CPU time 31.95 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:50 PM PST 24
Peak memory 212424 kb
Host smart-ee63cd89-7b3c-4cd4-90ac-fe0b32122f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092995015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1092995015
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.3310940721
Short name T59
Test name
Test status
Simulation time 2989176217 ps
CPU time 47.44 seconds
Started Jan 14 01:20:04 PM PST 24
Finished Jan 14 01:20:56 PM PST 24
Peak memory 215812 kb
Host smart-322ce432-9ab3-41f6-a35b-04fce7cbb534
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310940721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 3.rom_ctrl_stress_all.3310940721
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1058886043
Short name T209
Test name
Test status
Simulation time 69968259629 ps
CPU time 732.46 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:32:38 PM PST 24
Peak memory 221168 kb
Host smart-9555c7f8-4e8c-4e4c-a181-6e4b12db9db9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058886043 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1058886043
Directory /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.365937494
Short name T11
Test name
Test status
Simulation time 8515398711 ps
CPU time 16.09 seconds
Started Jan 14 01:20:48 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 211092 kb
Host smart-d266f079-0601-4a50-804e-d8a173d1e8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365937494 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.365937494
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1584950681
Short name T204
Test name
Test status
Simulation time 35525516515 ps
CPU time 226.15 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:24:45 PM PST 24
Peak memory 213188 kb
Host smart-f180ce27-acca-40d0-bbda-c1db27d19014
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584950681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.1584950681
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.2373454165
Short name T352
Test name
Test status
Simulation time 37719874230 ps
CPU time 31.65 seconds
Started Jan 14 01:20:46 PM PST 24
Finished Jan 14 01:21:18 PM PST 24
Peak memory 211284 kb
Host smart-deac8f0b-708b-4fb1-a445-1284a45b18a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373454165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.2373454165
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.1959343390
Short name T261
Test name
Test status
Simulation time 8406578366 ps
CPU time 17.27 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:12 PM PST 24
Peak memory 210956 kb
Host smart-5a9eabdd-786f-4be7-a7fa-2b81080a1566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1959343390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.1959343390
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.1788695550
Short name T191
Test name
Test status
Simulation time 360892308 ps
CPU time 10.43 seconds
Started Jan 14 01:20:43 PM PST 24
Finished Jan 14 01:20:54 PM PST 24
Peak memory 212516 kb
Host smart-1661d82b-6bab-4610-ac03-2bab059671ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788695550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.1788695550
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.4011146582
Short name T278
Test name
Test status
Simulation time 29657957215 ps
CPU time 68.43 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:22:03 PM PST 24
Peak memory 218576 kb
Host smart-8ea4bc02-97a5-49ea-b314-9a9d262ad4c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011146582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.4011146582
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.2232245262
Short name T418
Test name
Test status
Simulation time 5878947092 ps
CPU time 14.5 seconds
Started Jan 14 01:20:55 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 210948 kb
Host smart-1157b30b-961d-417e-8328-e0fa41579f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232245262 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.2232245262
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.461441168
Short name T408
Test name
Test status
Simulation time 3059131033 ps
CPU time 196.52 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:24:12 PM PST 24
Peak memory 213148 kb
Host smart-52e811b3-cdab-4044-b9bf-25414644c554
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461441168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_c
orrupt_sig_fatal_chk.461441168
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.2932195538
Short name T307
Test name
Test status
Simulation time 2733649304 ps
CPU time 19.43 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:21:20 PM PST 24
Peak memory 211212 kb
Host smart-63d7a304-3969-4f8e-8550-dea02808c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932195538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.2932195538
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2248897552
Short name T359
Test name
Test status
Simulation time 678694229 ps
CPU time 9.82 seconds
Started Jan 14 01:20:48 PM PST 24
Finished Jan 14 01:20:58 PM PST 24
Peak memory 210824 kb
Host smart-98707e30-77e3-4a95-947d-e2215c40d2ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2248897552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2248897552
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.3612024238
Short name T158
Test name
Test status
Simulation time 8812684417 ps
CPU time 36.01 seconds
Started Jan 14 01:20:44 PM PST 24
Finished Jan 14 01:21:21 PM PST 24
Peak memory 213244 kb
Host smart-84ce478a-e25b-4530-b25f-aa77e73cf252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612024238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.3612024238
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.4095585444
Short name T194
Test name
Test status
Simulation time 4933078955 ps
CPU time 43.6 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 01:21:36 PM PST 24
Peak memory 216260 kb
Host smart-4c6a90b5-09a8-4ad7-ac42-afc685d8a571
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095585444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.4095585444
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.837267314
Short name T425
Test name
Test status
Simulation time 97187017744 ps
CPU time 3716.22 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 02:22:48 PM PST 24
Peak memory 235316 kb
Host smart-b9cc2c22-745c-4bc9-a764-b8d1852dd155
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837267314 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.837267314
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.943580257
Short name T173
Test name
Test status
Simulation time 3299090172 ps
CPU time 15.39 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 01:21:07 PM PST 24
Peak memory 210876 kb
Host smart-c7bdbfa0-f9b3-4196-876e-d0cbc7b05d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943580257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.943580257
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.46156058
Short name T226
Test name
Test status
Simulation time 7933891718 ps
CPU time 147.01 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:23:28 PM PST 24
Peak memory 227660 kb
Host smart-37aec861-b7b4-4922-9325-e533912bc76a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46156058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_co
rrupt_sig_fatal_chk.46156058
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.1301090664
Short name T284
Test name
Test status
Simulation time 18779912218 ps
CPU time 26.58 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 211536 kb
Host smart-6fa7cbfe-ed1a-4fe7-800e-54681514b223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301090664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.1301090664
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3155053447
Short name T225
Test name
Test status
Simulation time 1913721856 ps
CPU time 16.4 seconds
Started Jan 14 01:20:55 PM PST 24
Finished Jan 14 01:21:12 PM PST 24
Peak memory 210784 kb
Host smart-fcaab449-cadf-4091-acc5-229aba525404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155053447 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3155053447
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.1510114180
Short name T20
Test name
Test status
Simulation time 1643107288 ps
CPU time 20.22 seconds
Started Jan 14 01:20:51 PM PST 24
Finished Jan 14 01:21:11 PM PST 24
Peak memory 212260 kb
Host smart-aea3f225-946c-45a4-8731-98b20b4f9d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510114180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.1510114180
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.4224397961
Short name T383
Test name
Test status
Simulation time 314623746 ps
CPU time 21.95 seconds
Started Jan 14 01:20:48 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 215344 kb
Host smart-c9e0d686-65bf-48ad-ad94-bd1a9bfbf603
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224397961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.4224397961
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.2463828448
Short name T197
Test name
Test status
Simulation time 72187103987 ps
CPU time 802.83 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:34:17 PM PST 24
Peak memory 228908 kb
Host smart-2aa5733c-2902-4719-a8ab-b7f88df980ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463828448 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.2463828448
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.3906402690
Short name T44
Test name
Test status
Simulation time 1603837738 ps
CPU time 14.3 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 210960 kb
Host smart-7d0aecba-9b40-4b89-a654-3d3d51e30b31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906402690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.3906402690
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2309729663
Short name T397
Test name
Test status
Simulation time 9246604824 ps
CPU time 120.2 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:22:55 PM PST 24
Peak memory 233384 kb
Host smart-588bdd9e-2972-4417-bbfd-9830d6456750
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309729663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2309729663
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2296085242
Short name T393
Test name
Test status
Simulation time 6136691815 ps
CPU time 27.62 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 211588 kb
Host smart-fc9f9f53-5d72-4203-928a-eb1d7a2627dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296085242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2296085242
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1424083093
Short name T370
Test name
Test status
Simulation time 1780968030 ps
CPU time 16.34 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:15 PM PST 24
Peak memory 210856 kb
Host smart-6d94500f-af0e-431d-929e-a2b196baaae2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424083093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1424083093
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.451957014
Short name T274
Test name
Test status
Simulation time 187417011 ps
CPU time 10.9 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 212148 kb
Host smart-b80e7686-5013-40c1-8916-778969a599f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451957014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.451957014
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3515621756
Short name T105
Test name
Test status
Simulation time 1419308742 ps
CPU time 22.33 seconds
Started Jan 14 01:20:59 PM PST 24
Finished Jan 14 01:21:22 PM PST 24
Peak memory 215128 kb
Host smart-13c3a4c4-f25c-46dd-8c7d-c5ba4d57b01e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515621756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3515621756
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.1938163160
Short name T371
Test name
Test status
Simulation time 688196191 ps
CPU time 6.83 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:05 PM PST 24
Peak memory 210684 kb
Host smart-819bf147-a16c-4dab-ad10-3fda83194aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938163160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.1938163160
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.3857199774
Short name T190
Test name
Test status
Simulation time 18409151952 ps
CPU time 204.8 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:24:22 PM PST 24
Peak memory 237376 kb
Host smart-e667fb68-a2fe-45d8-91ff-917e5bd549d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857199774 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.3857199774
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.1971544614
Short name T411
Test name
Test status
Simulation time 2900238547 ps
CPU time 27.56 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:21:28 PM PST 24
Peak memory 210788 kb
Host smart-5a61bacd-4791-4d14-9012-1339a505f6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971544614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.1971544614
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.411092506
Short name T364
Test name
Test status
Simulation time 3935980292 ps
CPU time 16.59 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 210852 kb
Host smart-d02eedf2-89d7-4766-b84a-e038a3b477e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411092506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.411092506
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.4287334154
Short name T372
Test name
Test status
Simulation time 45031926559 ps
CPU time 38.93 seconds
Started Jan 14 01:20:46 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 213488 kb
Host smart-526af211-8127-428c-b7a1-a21b91715c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287334154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.4287334154
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.2039824238
Short name T282
Test name
Test status
Simulation time 42413390568 ps
CPU time 58.96 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:58 PM PST 24
Peak memory 213184 kb
Host smart-98d51af7-ea0d-4966-bdb7-08522c62de73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039824238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.2039824238
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4153766981
Short name T343
Test name
Test status
Simulation time 125017632600 ps
CPU time 2352.05 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 02:00:11 PM PST 24
Peak memory 235232 kb
Host smart-6eef4074-6995-4a1f-8df6-d8c8281ee6ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153766981 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4153766981
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.886359616
Short name T266
Test name
Test status
Simulation time 1734251191 ps
CPU time 14.65 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:12 PM PST 24
Peak memory 210788 kb
Host smart-14f0b298-ca66-4ab6-b2d0-4f6feecd627f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886359616 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.886359616
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.1340408184
Short name T356
Test name
Test status
Simulation time 114705597121 ps
CPU time 262.92 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:25:17 PM PST 24
Peak memory 228036 kb
Host smart-adf6dd31-e99b-4838-a000-4782d09d96c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340408184 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.1340408184
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.2637142023
Short name T159
Test name
Test status
Simulation time 8139951617 ps
CPU time 23.16 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:22 PM PST 24
Peak memory 210616 kb
Host smart-e88f7f5b-b147-479a-ba1e-7b16cbc1f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637142023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.2637142023
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.843721405
Short name T256
Test name
Test status
Simulation time 675695612 ps
CPU time 7.85 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:03 PM PST 24
Peak memory 210820 kb
Host smart-50a4fe3c-c5df-4cd0-8c42-13d7cc70b985
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=843721405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.843721405
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3208532347
Short name T384
Test name
Test status
Simulation time 8171460100 ps
CPU time 33.76 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:33 PM PST 24
Peak memory 213480 kb
Host smart-15d393d0-c15a-4cb3-a4ff-0e4f755f7046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208532347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3208532347
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3166942105
Short name T280
Test name
Test status
Simulation time 13438181911 ps
CPU time 71.43 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:22:08 PM PST 24
Peak memory 216300 kb
Host smart-99265c20-b538-45f5-81a7-6489ea3b35d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166942105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3166942105
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3512525732
Short name T60
Test name
Test status
Simulation time 4391279350 ps
CPU time 15.6 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 210820 kb
Host smart-5245ded7-544e-4b5d-8f1a-67ba88816afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512525732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3512525732
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1236316560
Short name T34
Test name
Test status
Simulation time 874101491 ps
CPU time 10.07 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:09 PM PST 24
Peak memory 210936 kb
Host smart-10beaecb-3bf2-44db-b151-addd2be568f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236316560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1236316560
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3519107071
Short name T229
Test name
Test status
Simulation time 194985878 ps
CPU time 5.88 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:03 PM PST 24
Peak memory 210040 kb
Host smart-b63ff916-0371-4c14-b67e-216efa05d2d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519107071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3519107071
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.3593120444
Short name T230
Test name
Test status
Simulation time 752264219 ps
CPU time 10.59 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:08 PM PST 24
Peak memory 212424 kb
Host smart-f93fc8cc-4e7d-49e4-80f3-5e9cd653ccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593120444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.3593120444
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.258552868
Short name T170
Test name
Test status
Simulation time 7752648027 ps
CPU time 27.87 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 213936 kb
Host smart-20f4e55d-67e7-407f-a5b5-c35d40399032
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258552868 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 36.rom_ctrl_stress_all.258552868
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.2927248390
Short name T178
Test name
Test status
Simulation time 145756853263 ps
CPU time 1131.26 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:39:52 PM PST 24
Peak memory 229848 kb
Host smart-fff377b7-4ec7-40a7-ad04-ac1566fbeaa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927248390 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.2927248390
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.2339252350
Short name T319
Test name
Test status
Simulation time 594702515 ps
CPU time 5.26 seconds
Started Jan 14 01:21:02 PM PST 24
Finished Jan 14 01:21:08 PM PST 24
Peak memory 210752 kb
Host smart-11e5905f-0046-4253-9983-84093099b682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339252350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.2339252350
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4208345142
Short name T63
Test name
Test status
Simulation time 31886984790 ps
CPU time 381.19 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:27:17 PM PST 24
Peak memory 225224 kb
Host smart-e782dae1-efcf-4c2d-8ac7-202eba8eb2b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208345142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_
corrupt_sig_fatal_chk.4208345142
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2302148806
Short name T406
Test name
Test status
Simulation time 171831798 ps
CPU time 9.91 seconds
Started Jan 14 01:21:02 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 211068 kb
Host smart-106ebb46-1c23-4b4c-b851-def1c2db50ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302148806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2302148806
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.1870070290
Short name T314
Test name
Test status
Simulation time 1505514780 ps
CPU time 14.86 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 210840 kb
Host smart-1e1d8d70-1fa4-40f4-88b6-39b882f7e0d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1870070290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.1870070290
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2615771648
Short name T112
Test name
Test status
Simulation time 1880322812 ps
CPU time 17.7 seconds
Started Jan 14 01:20:54 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 212268 kb
Host smart-580c678c-c59e-40b0-b948-34a10bb62871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615771648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2615771648
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1136024106
Short name T369
Test name
Test status
Simulation time 5870095582 ps
CPU time 56.66 seconds
Started Jan 14 01:20:53 PM PST 24
Finished Jan 14 01:21:51 PM PST 24
Peak memory 215516 kb
Host smart-0da2c45c-3c68-4325-b0f1-580efd2d82fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136024106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1136024106
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.2508789941
Short name T388
Test name
Test status
Simulation time 54227290658 ps
CPU time 2589.3 seconds
Started Jan 14 01:20:52 PM PST 24
Finished Jan 14 02:04:02 PM PST 24
Peak memory 234804 kb
Host smart-873aec62-237c-4c50-8f79-676e37f2e6af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508789941 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.2508789941
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.3091337645
Short name T420
Test name
Test status
Simulation time 85688418 ps
CPU time 4.5 seconds
Started Jan 14 01:21:01 PM PST 24
Finished Jan 14 01:21:06 PM PST 24
Peak memory 211000 kb
Host smart-4e785361-4080-4a3d-b872-54be6ee98663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091337645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.3091337645
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2357356945
Short name T234
Test name
Test status
Simulation time 134983629899 ps
CPU time 410.2 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:27:48 PM PST 24
Peak memory 236328 kb
Host smart-b08fd34e-c44b-439d-981d-37f735628b23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357356945 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2357356945
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1056592152
Short name T338
Test name
Test status
Simulation time 4393846321 ps
CPU time 19.11 seconds
Started Jan 14 01:20:57 PM PST 24
Finished Jan 14 01:21:17 PM PST 24
Peak memory 211268 kb
Host smart-01a00017-719b-41bc-9289-a5798cc220c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056592152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1056592152
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.2343483406
Short name T183
Test name
Test status
Simulation time 2832487523 ps
CPU time 14.4 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:21 PM PST 24
Peak memory 210884 kb
Host smart-282d9bb1-0912-4d48-9769-b5a39fe8612b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343483406 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.2343483406
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.2030607599
Short name T231
Test name
Test status
Simulation time 3590502301 ps
CPU time 30.01 seconds
Started Jan 14 01:21:02 PM PST 24
Finished Jan 14 01:21:33 PM PST 24
Peak memory 212152 kb
Host smart-f5a13f4d-f45f-414b-967b-a8bf6476e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030607599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.2030607599
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3444475197
Short name T342
Test name
Test status
Simulation time 5590451500 ps
CPU time 57.01 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:56 PM PST 24
Peak memory 212900 kb
Host smart-86c0d4d8-2387-4faa-be6c-c60a56ec3a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444475197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3444475197
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.3771833068
Short name T327
Test name
Test status
Simulation time 897425106 ps
CPU time 10.05 seconds
Started Jan 14 01:20:56 PM PST 24
Finished Jan 14 01:21:07 PM PST 24
Peak memory 210820 kb
Host smart-34b9a764-6e23-4f5f-8ebc-dbc47e4f6346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771833068 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.3771833068
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3443471725
Short name T22
Test name
Test status
Simulation time 1657767860 ps
CPU time 103.79 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:22:54 PM PST 24
Peak memory 237412 kb
Host smart-ff0d79fb-ce71-42ea-a7d9-6de3a306fd3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443471725 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3443471725
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2379028015
Short name T344
Test name
Test status
Simulation time 693040633 ps
CPU time 9.93 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:16 PM PST 24
Peak memory 211020 kb
Host smart-db794d04-d3ff-45d3-b33e-f5ebecac8ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379028015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2379028015
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2549432500
Short name T187
Test name
Test status
Simulation time 97124801 ps
CPU time 5.89 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 210880 kb
Host smart-1997d958-6424-4385-9152-89e3b04ed21d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549432500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2549432500
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.3678736924
Short name T192
Test name
Test status
Simulation time 187006939 ps
CPU time 10.38 seconds
Started Jan 14 01:21:02 PM PST 24
Finished Jan 14 01:21:13 PM PST 24
Peak memory 212608 kb
Host smart-ca8fa40b-999c-4a35-a707-76a366758631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678736924 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.3678736924
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.2337715519
Short name T163
Test name
Test status
Simulation time 1967487513 ps
CPU time 27.69 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:38 PM PST 24
Peak memory 215788 kb
Host smart-0316d29e-61b7-46a0-9995-d43755d266f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337715519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.rom_ctrl_stress_all.2337715519
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2096611001
Short name T155
Test name
Test status
Simulation time 2780023784 ps
CPU time 12.75 seconds
Started Jan 14 01:20:08 PM PST 24
Finished Jan 14 01:20:28 PM PST 24
Peak memory 210996 kb
Host smart-ae9fd66f-5b25-47d7-8677-c93894392ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096611001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2096611001
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.4251519630
Short name T394
Test name
Test status
Simulation time 61618555648 ps
CPU time 391.13 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:26:49 PM PST 24
Peak memory 228088 kb
Host smart-896fbedc-fff9-413e-8c33-c54c83981fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251519630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.4251519630
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.2628006346
Short name T379
Test name
Test status
Simulation time 1488521727 ps
CPU time 19.35 seconds
Started Jan 14 01:20:13 PM PST 24
Finished Jan 14 01:20:38 PM PST 24
Peak memory 210976 kb
Host smart-55ed888d-d0b8-4c3c-bab4-5e928eeda055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628006346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.2628006346
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.1383561977
Short name T302
Test name
Test status
Simulation time 181058503 ps
CPU time 5.73 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:24 PM PST 24
Peak memory 210856 kb
Host smart-8d00231c-3122-4fd5-9f11-9c5d74776e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383561977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.1383561977
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.2082863934
Short name T42
Test name
Test status
Simulation time 2864842989 ps
CPU time 62.08 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:21:27 PM PST 24
Peak memory 236432 kb
Host smart-eebe649d-2d3a-4320-99e8-02ab25adf870
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082863934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.2082863934
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2366673639
Short name T232
Test name
Test status
Simulation time 7806992872 ps
CPU time 30.81 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:49 PM PST 24
Peak memory 213020 kb
Host smart-4cdd70dd-6a97-4379-98aa-14849843c350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366673639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2366673639
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.219620569
Short name T422
Test name
Test status
Simulation time 16508131609 ps
CPU time 22.87 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 211556 kb
Host smart-4b41e5c7-184a-4b80-973f-92e9a217703b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219620569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.219620569
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.971762246
Short name T306
Test name
Test status
Simulation time 4597916946 ps
CPU time 11.52 seconds
Started Jan 14 01:20:59 PM PST 24
Finished Jan 14 01:21:11 PM PST 24
Peak memory 210952 kb
Host smart-91cf88fe-53f4-44d4-8edf-4c6fdc04abaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971762246 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.971762246
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.4132714168
Short name T423
Test name
Test status
Simulation time 9857478075 ps
CPU time 24.67 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:32 PM PST 24
Peak memory 211452 kb
Host smart-295eda72-1e2e-4944-9296-c5921fb494cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132714168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.4132714168
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.2322791650
Short name T206
Test name
Test status
Simulation time 803387072 ps
CPU time 10.33 seconds
Started Jan 14 01:21:04 PM PST 24
Finished Jan 14 01:21:16 PM PST 24
Peak memory 210832 kb
Host smart-fde56c22-dfe2-4d26-be33-8be2ba4e2efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322791650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.2322791650
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.406389153
Short name T198
Test name
Test status
Simulation time 4038847095 ps
CPU time 32.9 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:43 PM PST 24
Peak memory 212968 kb
Host smart-7419a13c-9301-46ba-858c-88f5999d3ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406389153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.406389153
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.2524007680
Short name T245
Test name
Test status
Simulation time 5552116532 ps
CPU time 41.17 seconds
Started Jan 14 01:20:58 PM PST 24
Finished Jan 14 01:21:40 PM PST 24
Peak memory 213272 kb
Host smart-08d4ca2c-c2bf-4500-9398-5814a3ad479d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524007680 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.2524007680
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.3502465963
Short name T268
Test name
Test status
Simulation time 1967964092 ps
CPU time 16.02 seconds
Started Jan 14 01:21:13 PM PST 24
Finished Jan 14 01:21:30 PM PST 24
Peak memory 210936 kb
Host smart-4037f38d-9561-45fa-a0d1-981887a9e16d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502465963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3502465963
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.2716876518
Short name T250
Test name
Test status
Simulation time 37314705788 ps
CPU time 229.75 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:25:06 PM PST 24
Peak memory 236528 kb
Host smart-67091436-ab32-41d6-978b-24d4b772c73e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716876518 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.2716876518
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2835693024
Short name T219
Test name
Test status
Simulation time 2403181538 ps
CPU time 24.45 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:21:40 PM PST 24
Peak memory 211120 kb
Host smart-ede4a77a-3216-4aa7-ba68-bce313141030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835693024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2835693024
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2746189489
Short name T114
Test name
Test status
Simulation time 1272190838 ps
CPU time 9.68 seconds
Started Jan 14 01:21:09 PM PST 24
Finished Jan 14 01:21:20 PM PST 24
Peak memory 210852 kb
Host smart-9bd7ea23-b3a3-49ef-b14b-0a438846e7ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746189489 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2746189489
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4226952958
Short name T21
Test name
Test status
Simulation time 9821892111 ps
CPU time 38.61 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:45 PM PST 24
Peak memory 213220 kb
Host smart-b26e2464-6cc7-4a2a-8ecf-da38c447af34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226952958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4226952958
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.220619544
Short name T421
Test name
Test status
Simulation time 3880261062 ps
CPU time 37.79 seconds
Started Jan 14 01:21:09 PM PST 24
Finished Jan 14 01:21:47 PM PST 24
Peak memory 214972 kb
Host smart-831230ee-12c3-432a-941a-93273beac819
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220619544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.rom_ctrl_stress_all.220619544
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.4000036968
Short name T309
Test name
Test status
Simulation time 17135577154 ps
CPU time 15.1 seconds
Started Jan 14 01:21:00 PM PST 24
Finished Jan 14 01:21:16 PM PST 24
Peak memory 211000 kb
Host smart-17c1e5cc-1177-4052-b5e9-17d5ef9e6e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000036968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4000036968
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1544709320
Short name T61
Test name
Test status
Simulation time 21684211849 ps
CPU time 148.61 seconds
Started Jan 14 01:21:14 PM PST 24
Finished Jan 14 01:23:43 PM PST 24
Peak memory 237248 kb
Host smart-762e6694-372b-4a6d-8797-8a3f35bf6a8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544709320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1544709320
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.4251577314
Short name T264
Test name
Test status
Simulation time 173393170 ps
CPU time 9.62 seconds
Started Jan 14 01:21:16 PM PST 24
Finished Jan 14 01:21:27 PM PST 24
Peak memory 211068 kb
Host smart-2b818389-0883-4268-9448-6662ec7dd501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251577314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.4251577314
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.842726031
Short name T241
Test name
Test status
Simulation time 387163778 ps
CPU time 5.77 seconds
Started Jan 14 01:21:08 PM PST 24
Finished Jan 14 01:21:14 PM PST 24
Peak memory 210792 kb
Host smart-f0978a11-6dc1-4fd5-826d-2d1bc1e4f04b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842726031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.842726031
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.2139078650
Short name T222
Test name
Test status
Simulation time 223929786 ps
CPU time 10.59 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:21:18 PM PST 24
Peak memory 212896 kb
Host smart-f4542f1a-5a72-4add-a12c-f1aef15aa8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139078650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.2139078650
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.2344861012
Short name T208
Test name
Test status
Simulation time 4389100590 ps
CPU time 33.63 seconds
Started Jan 14 01:21:08 PM PST 24
Finished Jan 14 01:21:42 PM PST 24
Peak memory 215272 kb
Host smart-308db25d-0596-4d97-89b5-78b0eaa7ff42
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344861012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.2344861012
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3355609778
Short name T294
Test name
Test status
Simulation time 138831306184 ps
CPU time 3697.55 seconds
Started Jan 14 01:21:11 PM PST 24
Finished Jan 14 02:22:49 PM PST 24
Peak memory 235608 kb
Host smart-e8c55810-8111-46ab-9c8c-8a20efa5685c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355609778 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3355609778
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.309113477
Short name T56
Test name
Test status
Simulation time 2059208569 ps
CPU time 8.4 seconds
Started Jan 14 01:21:01 PM PST 24
Finished Jan 14 01:21:10 PM PST 24
Peak memory 210884 kb
Host smart-2f36982b-09f5-488f-8666-dba68f4126a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309113477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.309113477
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.4075648159
Short name T109
Test name
Test status
Simulation time 62842128615 ps
CPU time 366.08 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:27:13 PM PST 24
Peak memory 237420 kb
Host smart-f411e0aa-08f0-45a8-877e-b9fbe8a8a2b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075648159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.4075648159
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.3425232975
Short name T168
Test name
Test status
Simulation time 2775207368 ps
CPU time 18.32 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:24 PM PST 24
Peak memory 211104 kb
Host smart-3e21f629-1996-4b1f-8527-0254d49b9d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425232975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.3425232975
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.562063893
Short name T318
Test name
Test status
Simulation time 9261103298 ps
CPU time 17.24 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 210876 kb
Host smart-361acc77-360e-43cd-a7cd-52544d8c6ac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562063893 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.562063893
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2786408704
Short name T326
Test name
Test status
Simulation time 2771492880 ps
CPU time 32.42 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:40 PM PST 24
Peak memory 212444 kb
Host smart-8a3a3e67-7062-4316-9bf2-6264225c948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786408704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2786408704
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.761194726
Short name T288
Test name
Test status
Simulation time 7116186146 ps
CPU time 45.97 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:52 PM PST 24
Peak memory 215920 kb
Host smart-195a1642-9fcd-4a4d-86b3-3499d9ccfee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761194726 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.761194726
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.115026328
Short name T331
Test name
Test status
Simulation time 51267392336 ps
CPU time 6777.69 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 03:14:12 PM PST 24
Peak memory 242760 kb
Host smart-67543542-aac2-4059-8291-344280aa19e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115026328 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.115026328
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.694040427
Short name T413
Test name
Test status
Simulation time 11437901677 ps
CPU time 10.77 seconds
Started Jan 14 01:21:13 PM PST 24
Finished Jan 14 01:21:25 PM PST 24
Peak memory 210880 kb
Host smart-2cc22460-b90d-4097-b0f1-a5dbddd41bac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694040427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.694040427
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2761914291
Short name T362
Test name
Test status
Simulation time 259925748885 ps
CPU time 278.82 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:25:46 PM PST 24
Peak memory 234060 kb
Host smart-cf806c3c-e726-48bc-aa49-03ee93ad2f92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761914291 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2761914291
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.423144942
Short name T367
Test name
Test status
Simulation time 1044949333 ps
CPU time 15.4 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:21 PM PST 24
Peak memory 211844 kb
Host smart-03ad4c85-b625-47cd-8e04-f6dbec6fa527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423144942 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.423144942
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.2513177817
Short name T199
Test name
Test status
Simulation time 1749967370 ps
CPU time 21.79 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:21:29 PM PST 24
Peak memory 212516 kb
Host smart-37847012-25cb-4527-a476-7aeeff11ad97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513177817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.2513177817
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.1054907402
Short name T332
Test name
Test status
Simulation time 1884199618 ps
CPU time 12.51 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:18 PM PST 24
Peak memory 213492 kb
Host smart-416f3430-45ab-47c0-85f9-beb5a60ccd81
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054907402 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.1054907402
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3772373356
Short name T335
Test name
Test status
Simulation time 65633021252 ps
CPU time 725.37 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:33:16 PM PST 24
Peak memory 227920 kb
Host smart-262f89d2-511c-40c9-ac52-2d41af0f844a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772373356 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3772373356
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.1189053444
Short name T233
Test name
Test status
Simulation time 2165101414 ps
CPU time 17.3 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 211004 kb
Host smart-6ced2e5f-476c-42d1-acc4-cd781e64c1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189053444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.1189053444
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1479312940
Short name T299
Test name
Test status
Simulation time 11219179634 ps
CPU time 184 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:24:11 PM PST 24
Peak memory 236396 kb
Host smart-9ac8589c-df34-40fe-9946-4017398eca09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479312940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1479312940
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.965815881
Short name T40
Test name
Test status
Simulation time 11828111631 ps
CPU time 22.73 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 01:21:36 PM PST 24
Peak memory 211404 kb
Host smart-e16517c4-6871-4de5-94d4-90c81c1e7c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965815881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.965815881
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.2777264114
Short name T313
Test name
Test status
Simulation time 5848294673 ps
CPU time 13.44 seconds
Started Jan 14 01:21:01 PM PST 24
Finished Jan 14 01:21:15 PM PST 24
Peak memory 210908 kb
Host smart-940f0ce6-7dcb-43f5-8a1b-7f703d8b849a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777264114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.2777264114
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.448139555
Short name T417
Test name
Test status
Simulation time 14860751741 ps
CPU time 31.84 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 01:21:45 PM PST 24
Peak memory 213312 kb
Host smart-c2eb6ca0-0a1a-4d2d-92b0-f1da87e61c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448139555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.448139555
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.948368983
Short name T104
Test name
Test status
Simulation time 6550008449 ps
CPU time 22.43 seconds
Started Jan 14 01:21:01 PM PST 24
Finished Jan 14 01:21:24 PM PST 24
Peak memory 211684 kb
Host smart-b70ab231-5c20-4ee2-be51-424f841c37c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948368983 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 45.rom_ctrl_stress_all.948368983
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.707487350
Short name T116
Test name
Test status
Simulation time 24509906610 ps
CPU time 1267.13 seconds
Started Jan 14 01:21:04 PM PST 24
Finished Jan 14 01:42:12 PM PST 24
Peak memory 233924 kb
Host smart-aa422e6c-e06e-4b9f-ace7-5c53d71b4f9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707487350 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.707487350
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.389975356
Short name T201
Test name
Test status
Simulation time 1319619658 ps
CPU time 11.81 seconds
Started Jan 14 01:21:14 PM PST 24
Finished Jan 14 01:21:26 PM PST 24
Peak memory 210972 kb
Host smart-1ade0697-54cc-42a3-8465-994de4434c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389975356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.389975356
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.3111978053
Short name T258
Test name
Test status
Simulation time 91063757992 ps
CPU time 210.36 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:24:37 PM PST 24
Peak memory 227596 kb
Host smart-4b60d56c-5443-4b0f-838a-f2bd6506a0ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111978053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.3111978053
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.2051299358
Short name T310
Test name
Test status
Simulation time 1028709638 ps
CPU time 16.33 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 211084 kb
Host smart-49d44fef-ad3c-47f8-b641-7d2a943e48da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051299358 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.2051299358
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3413149108
Short name T235
Test name
Test status
Simulation time 2706563298 ps
CPU time 8.14 seconds
Started Jan 14 01:21:13 PM PST 24
Finished Jan 14 01:21:22 PM PST 24
Peak memory 210776 kb
Host smart-5b3f4ae2-2638-44ef-9ba8-9ac1a0737144
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413149108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3413149108
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.3660242646
Short name T317
Test name
Test status
Simulation time 806128287 ps
CPU time 10.45 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:21:16 PM PST 24
Peak memory 213052 kb
Host smart-28f8cb29-2422-4ca6-871c-b18b3bb10cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660242646 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.3660242646
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3046334899
Short name T237
Test name
Test status
Simulation time 13147510128 ps
CPU time 82.04 seconds
Started Jan 14 01:21:01 PM PST 24
Finished Jan 14 01:22:24 PM PST 24
Peak memory 216584 kb
Host smart-a992578f-28b8-467c-a2be-7d320e8c638c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046334899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3046334899
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.2669903048
Short name T368
Test name
Test status
Simulation time 36919553718 ps
CPU time 413.7 seconds
Started Jan 14 01:21:05 PM PST 24
Finished Jan 14 01:28:00 PM PST 24
Peak memory 227332 kb
Host smart-f2343cc1-b305-420a-915c-960a11f60bba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669903048 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.2669903048
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3099459687
Short name T157
Test name
Test status
Simulation time 1518540644 ps
CPU time 13.95 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:25 PM PST 24
Peak memory 210928 kb
Host smart-458865d0-a511-45a4-81f8-62a067164d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099459687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3099459687
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.3171083747
Short name T415
Test name
Test status
Simulation time 26518282829 ps
CPU time 152.75 seconds
Started Jan 14 01:21:13 PM PST 24
Finished Jan 14 01:23:47 PM PST 24
Peak memory 224416 kb
Host smart-c2626be6-205b-48e3-bf18-59d2d78d233f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171083747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_
corrupt_sig_fatal_chk.3171083747
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.3094945866
Short name T366
Test name
Test status
Simulation time 2813793823 ps
CPU time 26 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:37 PM PST 24
Peak memory 211220 kb
Host smart-4e6897e4-c08a-44bf-8357-5afe0ba6d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094945866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.3094945866
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1898154558
Short name T103
Test name
Test status
Simulation time 99764275 ps
CPU time 5.77 seconds
Started Jan 14 01:21:09 PM PST 24
Finished Jan 14 01:21:15 PM PST 24
Peak memory 210812 kb
Host smart-158e8dfc-38b9-4ac9-b520-08cdf37ed8af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898154558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1898154558
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.2765712838
Short name T212
Test name
Test status
Simulation time 697408256 ps
CPU time 10.31 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:21:18 PM PST 24
Peak memory 212356 kb
Host smart-f8085892-e4f2-4ddf-8951-e66f23145f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765712838 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.2765712838
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3177709288
Short name T285
Test name
Test status
Simulation time 211245376 ps
CPU time 12.24 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 01:21:24 PM PST 24
Peak memory 212420 kb
Host smart-615f7958-dcd5-4688-a417-f1762a1c16f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177709288 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3177709288
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.2243587647
Short name T118
Test name
Test status
Simulation time 61955355570 ps
CPU time 2471.84 seconds
Started Jan 14 01:21:17 PM PST 24
Finished Jan 14 02:02:30 PM PST 24
Peak memory 251984 kb
Host smart-d08109be-23bd-48be-8818-43c63e5345dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243587647 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.2243587647
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.2166514630
Short name T213
Test name
Test status
Simulation time 362630820 ps
CPU time 4.38 seconds
Started Jan 14 01:21:17 PM PST 24
Finished Jan 14 01:21:22 PM PST 24
Peak memory 210972 kb
Host smart-3caefdc2-0409-4342-9bd3-15976528cde0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166514630 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2166514630
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.1102603537
Short name T348
Test name
Test status
Simulation time 25214612501 ps
CPU time 238.11 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:25:14 PM PST 24
Peak memory 212224 kb
Host smart-310ea9b0-15e3-4a6d-aa25-665e9c4991ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102603537 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.1102603537
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.3523732631
Short name T196
Test name
Test status
Simulation time 2369086037 ps
CPU time 10.21 seconds
Started Jan 14 01:21:06 PM PST 24
Finished Jan 14 01:21:17 PM PST 24
Peak memory 210936 kb
Host smart-a8536379-d052-4258-8c90-35785d4be03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523732631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.3523732631
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1152517163
Short name T279
Test name
Test status
Simulation time 544133635 ps
CPU time 8.85 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:21:25 PM PST 24
Peak memory 210916 kb
Host smart-0f22383d-5ca9-4e9b-ac18-6123b108cf97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1152517163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1152517163
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.568048612
Short name T181
Test name
Test status
Simulation time 5323608076 ps
CPU time 30.29 seconds
Started Jan 14 01:21:10 PM PST 24
Finished Jan 14 01:21:41 PM PST 24
Peak memory 212624 kb
Host smart-14364ba5-825a-435f-b9fc-f5a69b69cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568048612 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.568048612
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3450547849
Short name T281
Test name
Test status
Simulation time 7641976851 ps
CPU time 19.5 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:21:35 PM PST 24
Peak memory 210856 kb
Host smart-7aba9b3d-24ac-4bf6-ba9a-8996cb6c24f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450547849 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3450547849
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.127454349
Short name T341
Test name
Test status
Simulation time 28218174594 ps
CPU time 13.49 seconds
Started Jan 14 01:21:17 PM PST 24
Finished Jan 14 01:21:31 PM PST 24
Peak memory 210920 kb
Host smart-7fad504e-10cf-4335-b753-cfba2994062b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127454349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.127454349
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2300195023
Short name T64
Test name
Test status
Simulation time 7909330873 ps
CPU time 101.24 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:22:57 PM PST 24
Peak memory 233476 kb
Host smart-7356d5be-df22-447c-a9be-bed9c40400b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300195023 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2300195023
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.782411805
Short name T252
Test name
Test status
Simulation time 215340198 ps
CPU time 9.5 seconds
Started Jan 14 01:21:12 PM PST 24
Finished Jan 14 01:21:23 PM PST 24
Peak memory 211040 kb
Host smart-241a3b35-6dd1-4173-9f5c-b5b716d0eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782411805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.782411805
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1387376306
Short name T100
Test name
Test status
Simulation time 36147954259 ps
CPU time 16.88 seconds
Started Jan 14 01:21:15 PM PST 24
Finished Jan 14 01:21:33 PM PST 24
Peak memory 210980 kb
Host smart-023fbb2e-b644-48bc-a65f-b19dcbad42ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1387376306 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1387376306
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3304022371
Short name T175
Test name
Test status
Simulation time 15774913503 ps
CPU time 37.96 seconds
Started Jan 14 01:21:07 PM PST 24
Finished Jan 14 01:21:46 PM PST 24
Peak memory 213044 kb
Host smart-b5f75d9c-e3e2-4861-ac9f-5c87ee6830e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304022371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3304022371
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.3583257870
Short name T402
Test name
Test status
Simulation time 503911983 ps
CPU time 9.51 seconds
Started Jan 14 01:21:17 PM PST 24
Finished Jan 14 01:21:27 PM PST 24
Peak memory 211344 kb
Host smart-e3627d10-7e96-4fdd-87c8-bebd7849d157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583257870 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.3583257870
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all_with_rand_reset.275846960
Short name T12
Test name
Test status
Simulation time 21460142261 ps
CPU time 1509.74 seconds
Started Jan 14 01:21:18 PM PST 24
Finished Jan 14 01:46:28 PM PST 24
Peak memory 235524 kb
Host smart-a2e36537-8a5d-4d44-8df3-55603483f1a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275846960 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_stress_all_with_rand_reset.275846960
Directory /workspace/49.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.4171921687
Short name T214
Test name
Test status
Simulation time 3931874088 ps
CPU time 16.42 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:20:39 PM PST 24
Peak memory 211016 kb
Host smart-f91488f5-461b-4af7-9f4a-143235d59fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171921687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.4171921687
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3189429310
Short name T273
Test name
Test status
Simulation time 221702100691 ps
CPU time 467.36 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:28:10 PM PST 24
Peak memory 236688 kb
Host smart-229da3af-4410-49a1-822c-500a6e424f31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189429310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c
orrupt_sig_fatal_chk.3189429310
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1156835108
Short name T315
Test name
Test status
Simulation time 9910912686 ps
CPU time 24.63 seconds
Started Jan 14 01:20:08 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 211836 kb
Host smart-0ed71212-e825-4793-9cb6-1db3d6674d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156835108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1156835108
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.3508169486
Short name T419
Test name
Test status
Simulation time 3688864449 ps
CPU time 7.94 seconds
Started Jan 14 01:20:06 PM PST 24
Finished Jan 14 01:20:22 PM PST 24
Peak memory 210864 kb
Host smart-09322fdf-ed93-48f1-ac1a-55c1fe72c824
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508169486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.3508169486
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2055966219
Short name T297
Test name
Test status
Simulation time 10479759112 ps
CPU time 32.85 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:51 PM PST 24
Peak memory 213356 kb
Host smart-0e2782b6-1f5e-4aae-8be7-3fda569d4e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055966219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2055966219
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.2449969808
Short name T180
Test name
Test status
Simulation time 542409926 ps
CPU time 9.33 seconds
Started Jan 14 01:20:09 PM PST 24
Finished Jan 14 01:20:26 PM PST 24
Peak memory 210864 kb
Host smart-b5d7547e-cff8-4d35-9b41-8de5cd8dde24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449969808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.2449969808
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.1881315244
Short name T323
Test name
Test status
Simulation time 1898445732 ps
CPU time 15.56 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:20:37 PM PST 24
Peak memory 210924 kb
Host smart-5466171f-f752-4433-9eb6-b857f9ebad66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881315244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.1881315244
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3239292913
Short name T386
Test name
Test status
Simulation time 1270504913 ps
CPU time 76.8 seconds
Started Jan 14 01:20:11 PM PST 24
Finished Jan 14 01:21:36 PM PST 24
Peak memory 226948 kb
Host smart-16e21788-129c-4e58-9921-ad3113a84174
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239292913 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3239292913
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.3514208597
Short name T321
Test name
Test status
Simulation time 7856866250 ps
CPU time 34.74 seconds
Started Jan 14 01:20:08 PM PST 24
Finished Jan 14 01:20:51 PM PST 24
Peak memory 211448 kb
Host smart-68ef3d1b-5b00-4d71-b07c-7bc62ae18f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514208597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.3514208597
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.567161801
Short name T287
Test name
Test status
Simulation time 1671011999 ps
CPU time 8.2 seconds
Started Jan 14 01:20:12 PM PST 24
Finished Jan 14 01:20:27 PM PST 24
Peak memory 210848 kb
Host smart-856f2809-3df5-420b-9760-54dc3e4a8a34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567161801 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.567161801
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.2562637702
Short name T401
Test name
Test status
Simulation time 3015081929 ps
CPU time 36.07 seconds
Started Jan 14 01:20:12 PM PST 24
Finished Jan 14 01:20:55 PM PST 24
Peak memory 212428 kb
Host smart-7fe22b2a-3849-41bf-8f36-dae82b03b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562637702 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2562637702
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3674501650
Short name T291
Test name
Test status
Simulation time 1411556561 ps
CPU time 17.78 seconds
Started Jan 14 01:20:12 PM PST 24
Finished Jan 14 01:20:37 PM PST 24
Peak memory 210788 kb
Host smart-afb87f95-41fc-4b2c-bb83-6840640c2a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674501650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3674501650
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2877514701
Short name T238
Test name
Test status
Simulation time 5011230697 ps
CPU time 49.73 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:21:12 PM PST 24
Peak memory 219792 kb
Host smart-84074837-2023-4350-9c01-22ceedf9f34e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877514701 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_stress_all_with_rand_reset.2877514701
Directory /workspace/6.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.4281892540
Short name T330
Test name
Test status
Simulation time 1638945106 ps
CPU time 14.36 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 210852 kb
Host smart-7e7c878c-968c-4365-8601-6c6890de3eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281892540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.4281892540
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.3561578930
Short name T156
Test name
Test status
Simulation time 5887016918 ps
CPU time 115.41 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:22:21 PM PST 24
Peak memory 224196 kb
Host smart-c24df379-581f-441b-90b9-53e41bc4f3b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561578930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.3561578930
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.1062593141
Short name T7
Test name
Test status
Simulation time 18757132805 ps
CPU time 35.29 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:54 PM PST 24
Peak memory 211120 kb
Host smart-d2c9a405-89d4-4179-9244-02184057ba2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062593141 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.1062593141
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.3423374827
Short name T286
Test name
Test status
Simulation time 101457638 ps
CPU time 5.77 seconds
Started Jan 14 01:20:12 PM PST 24
Finished Jan 14 01:20:25 PM PST 24
Peak memory 210748 kb
Host smart-98363fb6-3a29-4d02-aa4c-fcc5eb4bb20b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423374827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.3423374827
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.3447514771
Short name T324
Test name
Test status
Simulation time 1851831450 ps
CPU time 21.43 seconds
Started Jan 14 01:20:11 PM PST 24
Finished Jan 14 01:20:40 PM PST 24
Peak memory 212420 kb
Host smart-1ce4dca2-7f40-4fc3-9fb0-d77dc93b4505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447514771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.3447514771
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.3697703885
Short name T177
Test name
Test status
Simulation time 89897584362 ps
CPU time 80.02 seconds
Started Jan 14 01:20:17 PM PST 24
Finished Jan 14 01:21:42 PM PST 24
Peak memory 219116 kb
Host smart-088ee6eb-11d4-47d9-bf34-3d4e46156dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697703885 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.3697703885
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.4047802569
Short name T179
Test name
Test status
Simulation time 111918854 ps
CPU time 4.43 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:30 PM PST 24
Peak memory 210884 kb
Host smart-868c3740-1290-4aa0-a6ae-b6cb7ec209fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047802569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.4047802569
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3395191944
Short name T380
Test name
Test status
Simulation time 29528628182 ps
CPU time 342.53 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:26:08 PM PST 24
Peak memory 235896 kb
Host smart-d3850792-eb8a-4317-ae10-c08239cb36f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395191944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.3395191944
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.3734028938
Short name T221
Test name
Test status
Simulation time 3471709355 ps
CPU time 30.68 seconds
Started Jan 14 01:20:10 PM PST 24
Finished Jan 14 01:20:50 PM PST 24
Peak memory 210920 kb
Host smart-9d3d7be8-b2cc-4fc6-8066-166bc44c8868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734028938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.3734028938
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.4182290763
Short name T113
Test name
Test status
Simulation time 322214535 ps
CPU time 5.95 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:31 PM PST 24
Peak memory 210152 kb
Host smart-d923ff42-801f-4ea9-8109-e70d7f2e1dcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182290763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.4182290763
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3632297527
Short name T390
Test name
Test status
Simulation time 6330595069 ps
CPU time 30.17 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:56 PM PST 24
Peak memory 213444 kb
Host smart-937164eb-8f8a-4b00-a107-ad3558f93f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632297527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3632297527
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.3880386470
Short name T358
Test name
Test status
Simulation time 302356593 ps
CPU time 16.01 seconds
Started Jan 14 01:20:04 PM PST 24
Finished Jan 14 01:20:25 PM PST 24
Peak memory 213940 kb
Host smart-896726ce-f6a0-482a-853c-0f3008a49f9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880386470 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.3880386470
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.1413654361
Short name T58
Test name
Test status
Simulation time 688878798 ps
CPU time 5.82 seconds
Started Jan 14 01:20:22 PM PST 24
Finished Jan 14 01:20:31 PM PST 24
Peak memory 210900 kb
Host smart-d475e25b-b06d-4f04-b629-0f8ebc7bbfdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413654361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.1413654361
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.737136355
Short name T277
Test name
Test status
Simulation time 5986746705 ps
CPU time 102.98 seconds
Started Jan 14 01:20:16 PM PST 24
Finished Jan 14 01:22:04 PM PST 24
Peak memory 233548 kb
Host smart-52a46d45-3f53-46de-8f01-97adcc775532
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737136355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co
rrupt_sig_fatal_chk.737136355
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1722784196
Short name T205
Test name
Test status
Simulation time 1771380475 ps
CPU time 15.64 seconds
Started Jan 14 01:20:24 PM PST 24
Finished Jan 14 01:20:41 PM PST 24
Peak memory 210936 kb
Host smart-0a4bd59f-6cfa-4826-94ef-be43d98c5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722784196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1722784196
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2745253555
Short name T108
Test name
Test status
Simulation time 5829953946 ps
CPU time 13.57 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:20:37 PM PST 24
Peak memory 210920 kb
Host smart-77144780-c821-4b85-9cbd-f57fe96bb22b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745253555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2745253555
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1537355053
Short name T166
Test name
Test status
Simulation time 7026615313 ps
CPU time 18.37 seconds
Started Jan 14 01:20:12 PM PST 24
Finished Jan 14 01:20:37 PM PST 24
Peak memory 213616 kb
Host smart-5cfa924e-e279-4c75-9ca3-0a51ccff9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537355053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1537355053
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.1872655554
Short name T249
Test name
Test status
Simulation time 999716423 ps
CPU time 10.21 seconds
Started Jan 14 01:20:20 PM PST 24
Finished Jan 14 01:20:34 PM PST 24
Peak memory 212832 kb
Host smart-fc581b36-fe2c-4106-a8e5-946a2b3783ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872655554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.1872655554
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.328229508
Short name T414
Test name
Test status
Simulation time 115829721534 ps
CPU time 1383.02 seconds
Started Jan 14 01:20:23 PM PST 24
Finished Jan 14 01:43:28 PM PST 24
Peak memory 235580 kb
Host smart-90fc1a3e-9b52-49ef-98c8-ed367a7afcc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328229508 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.328229508
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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