Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.57 97.11 92.68 97.88 100.00 98.37 97.89 99.07


Total test records in report: 481
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T13 /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.114852790 Jan 17 03:54:56 PM PST 24 Jan 17 04:50:47 PM PST 24 84951466374 ps
T268 /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2148241802 Jan 17 03:53:36 PM PST 24 Jan 17 04:16:45 PM PST 24 63041449156 ps
T269 /workspace/coverage/default/13.rom_ctrl_stress_all.1975647964 Jan 17 03:54:11 PM PST 24 Jan 17 03:54:47 PM PST 24 19489121891 ps
T270 /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1251170168 Jan 17 03:54:00 PM PST 24 Jan 17 03:57:17 PM PST 24 61123441523 ps
T271 /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.450992727 Jan 17 03:55:21 PM PST 24 Jan 17 03:55:37 PM PST 24 5124525978 ps
T272 /workspace/coverage/default/38.rom_ctrl_smoke.399517102 Jan 17 03:55:23 PM PST 24 Jan 17 03:55:48 PM PST 24 7215611201 ps
T273 /workspace/coverage/default/20.rom_ctrl_smoke.1189166509 Jan 17 03:54:31 PM PST 24 Jan 17 03:55:04 PM PST 24 3365791000 ps
T274 /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3450848174 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:05 PM PST 24 923796734 ps
T275 /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1322942936 Jan 17 03:55:38 PM PST 24 Jan 17 03:56:01 PM PST 24 2117939682 ps
T276 /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4220802257 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:03 PM PST 24 340494392 ps
T277 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3184707374 Jan 17 03:55:48 PM PST 24 Jan 17 04:00:05 PM PST 24 56436917596 ps
T278 /workspace/coverage/default/25.rom_ctrl_smoke.685300008 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:30 PM PST 24 3758958905 ps
T279 /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3727728916 Jan 17 03:55:27 PM PST 24 Jan 17 03:55:48 PM PST 24 915097045 ps
T280 /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1272083602 Jan 17 03:55:39 PM PST 24 Jan 17 03:56:13 PM PST 24 3918571650 ps
T281 /workspace/coverage/default/22.rom_ctrl_stress_all.2155290946 Jan 17 03:54:35 PM PST 24 Jan 17 03:55:08 PM PST 24 14483314584 ps
T282 /workspace/coverage/default/7.rom_ctrl_smoke.2389071622 Jan 17 03:53:55 PM PST 24 Jan 17 03:54:06 PM PST 24 182503949 ps
T283 /workspace/coverage/default/44.rom_ctrl_stress_all.3046653188 Jan 17 03:55:47 PM PST 24 Jan 17 03:56:49 PM PST 24 5612878297 ps
T284 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1661572944 Jan 17 03:54:29 PM PST 24 Jan 17 03:54:41 PM PST 24 101377797 ps
T285 /workspace/coverage/default/19.rom_ctrl_stress_all.868517349 Jan 17 03:54:31 PM PST 24 Jan 17 03:55:06 PM PST 24 13866088358 ps
T286 /workspace/coverage/default/5.rom_ctrl_alert_test.2062247889 Jan 17 03:53:57 PM PST 24 Jan 17 03:54:04 PM PST 24 174633655 ps
T287 /workspace/coverage/default/27.rom_ctrl_stress_all.563106026 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:18 PM PST 24 380402012 ps
T288 /workspace/coverage/default/28.rom_ctrl_alert_test.3450464189 Jan 17 03:54:59 PM PST 24 Jan 17 03:55:20 PM PST 24 6248452742 ps
T289 /workspace/coverage/default/37.rom_ctrl_alert_test.789671744 Jan 17 03:55:28 PM PST 24 Jan 17 03:55:42 PM PST 24 3463208507 ps
T290 /workspace/coverage/default/4.rom_ctrl_stress_all.528869949 Jan 17 03:53:42 PM PST 24 Jan 17 03:54:15 PM PST 24 5549630465 ps
T291 /workspace/coverage/default/6.rom_ctrl_stress_all.3638960502 Jan 17 03:53:54 PM PST 24 Jan 17 03:54:17 PM PST 24 440448071 ps
T292 /workspace/coverage/default/43.rom_ctrl_stress_all.139235321 Jan 17 03:55:46 PM PST 24 Jan 17 03:56:04 PM PST 24 3046165384 ps
T293 /workspace/coverage/default/14.rom_ctrl_stress_all.1487726629 Jan 17 03:54:22 PM PST 24 Jan 17 03:56:48 PM PST 24 69458902800 ps
T294 /workspace/coverage/default/8.rom_ctrl_alert_test.963980597 Jan 17 03:54:00 PM PST 24 Jan 17 03:54:08 PM PST 24 329889777 ps
T295 /workspace/coverage/default/17.rom_ctrl_smoke.1928294876 Jan 17 03:54:19 PM PST 24 Jan 17 03:54:58 PM PST 24 3953356760 ps
T296 /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.565766320 Jan 17 03:55:25 PM PST 24 Jan 17 03:55:40 PM PST 24 10825689359 ps
T297 /workspace/coverage/default/17.rom_ctrl_alert_test.1787710249 Jan 17 03:54:26 PM PST 24 Jan 17 03:54:41 PM PST 24 1730158664 ps
T298 /workspace/coverage/default/32.rom_ctrl_smoke.2266500364 Jan 17 03:55:05 PM PST 24 Jan 17 03:55:40 PM PST 24 13925814943 ps
T299 /workspace/coverage/default/40.rom_ctrl_alert_test.2478721069 Jan 17 03:55:43 PM PST 24 Jan 17 03:55:51 PM PST 24 748098300 ps
T300 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2803527797 Jan 17 03:54:00 PM PST 24 Jan 17 03:54:07 PM PST 24 210646677 ps
T301 /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2850056685 Jan 17 03:55:55 PM PST 24 Jan 17 03:56:05 PM PST 24 340046182 ps
T302 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2939496490 Jan 17 03:54:02 PM PST 24 Jan 17 03:54:39 PM PST 24 32005891988 ps
T303 /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3580367265 Jan 17 03:55:45 PM PST 24 Jan 17 04:20:03 PM PST 24 113699674413 ps
T304 /workspace/coverage/default/31.rom_ctrl_smoke.835798346 Jan 17 03:55:07 PM PST 24 Jan 17 03:55:36 PM PST 24 5391272207 ps
T305 /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3124661003 Jan 17 03:53:37 PM PST 24 Jan 17 05:26:48 PM PST 24 217106291679 ps
T306 /workspace/coverage/default/22.rom_ctrl_smoke.683612634 Jan 17 03:54:35 PM PST 24 Jan 17 03:54:52 PM PST 24 6679841182 ps
T307 /workspace/coverage/default/17.rom_ctrl_stress_all.1295888427 Jan 17 03:54:20 PM PST 24 Jan 17 03:54:51 PM PST 24 11183478087 ps
T308 /workspace/coverage/default/23.rom_ctrl_smoke.1224242653 Jan 17 03:54:36 PM PST 24 Jan 17 03:55:11 PM PST 24 16014101755 ps
T309 /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.16291145 Jan 17 03:55:56 PM PST 24 Jan 17 04:01:44 PM PST 24 28795312931 ps
T310 /workspace/coverage/default/12.rom_ctrl_stress_all.2998796648 Jan 17 03:54:07 PM PST 24 Jan 17 03:54:40 PM PST 24 6891159295 ps
T311 /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4068453778 Jan 17 03:54:33 PM PST 24 Jan 17 03:54:52 PM PST 24 2356115456 ps
T312 /workspace/coverage/default/27.rom_ctrl_smoke.3838922659 Jan 17 03:54:52 PM PST 24 Jan 17 03:55:28 PM PST 24 7424019224 ps
T313 /workspace/coverage/default/41.rom_ctrl_alert_test.21872384 Jan 17 03:55:42 PM PST 24 Jan 17 03:55:50 PM PST 24 878728130 ps
T314 /workspace/coverage/default/48.rom_ctrl_alert_test.1082621317 Jan 17 03:55:56 PM PST 24 Jan 17 03:56:12 PM PST 24 2052132090 ps
T315 /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1088250138 Jan 17 03:53:37 PM PST 24 Jan 17 03:53:58 PM PST 24 3869367201 ps
T316 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2838475816 Jan 17 03:54:13 PM PST 24 Jan 17 03:54:23 PM PST 24 175625224 ps
T317 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2031256915 Jan 17 03:55:52 PM PST 24 Jan 17 03:56:11 PM PST 24 5159346718 ps
T318 /workspace/coverage/default/13.rom_ctrl_smoke.271425862 Jan 17 03:54:07 PM PST 24 Jan 17 03:54:19 PM PST 24 367048040 ps
T319 /workspace/coverage/default/34.rom_ctrl_smoke.3638238595 Jan 17 03:55:21 PM PST 24 Jan 17 03:56:02 PM PST 24 7693853997 ps
T320 /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.439226929 Jan 17 03:55:48 PM PST 24 Jan 17 03:59:51 PM PST 24 18104372831 ps
T321 /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3372371085 Jan 17 03:54:00 PM PST 24 Jan 17 04:25:59 PM PST 24 65504112116 ps
T322 /workspace/coverage/default/18.rom_ctrl_stress_all.2993549923 Jan 17 03:54:29 PM PST 24 Jan 17 03:55:06 PM PST 24 25904861962 ps
T323 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2959388190 Jan 17 03:54:58 PM PST 24 Jan 17 03:55:15 PM PST 24 8013242441 ps
T324 /workspace/coverage/default/30.rom_ctrl_alert_test.2481317003 Jan 17 03:55:07 PM PST 24 Jan 17 03:55:21 PM PST 24 3052048429 ps
T325 /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.293129596 Jan 17 03:54:40 PM PST 24 Jan 17 03:54:52 PM PST 24 2488855945 ps
T326 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1631906047 Jan 17 03:53:34 PM PST 24 Jan 17 03:54:04 PM PST 24 2315145351 ps
T327 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2472560397 Jan 17 03:54:28 PM PST 24 Jan 17 03:54:51 PM PST 24 1084201550 ps
T328 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1828858292 Jan 17 03:54:35 PM PST 24 Jan 17 03:54:51 PM PST 24 3791902239 ps
T329 /workspace/coverage/default/2.rom_ctrl_alert_test.2507847244 Jan 17 03:53:43 PM PST 24 Jan 17 03:53:59 PM PST 24 1627096455 ps
T330 /workspace/coverage/default/18.rom_ctrl_alert_test.2041150887 Jan 17 03:54:25 PM PST 24 Jan 17 03:54:40 PM PST 24 2619666024 ps
T331 /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1937660151 Jan 17 03:55:39 PM PST 24 Jan 17 03:55:56 PM PST 24 991515721 ps
T332 /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1965289441 Jan 17 03:54:07 PM PST 24 Jan 17 03:54:24 PM PST 24 12358609076 ps
T333 /workspace/coverage/default/21.rom_ctrl_stress_all.1291321747 Jan 17 03:54:31 PM PST 24 Jan 17 03:55:04 PM PST 24 2455016480 ps
T334 /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.281459190 Jan 17 03:55:39 PM PST 24 Jan 17 03:55:58 PM PST 24 4377457861 ps
T335 /workspace/coverage/default/43.rom_ctrl_smoke.2665948802 Jan 17 03:55:44 PM PST 24 Jan 17 03:56:23 PM PST 24 3510996897 ps
T336 /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.838935267 Jan 17 03:55:51 PM PST 24 Jan 17 04:39:43 PM PST 24 71194875587 ps
T337 /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.327370925 Jan 17 03:54:22 PM PST 24 Jan 17 04:27:45 PM PST 24 216584789019 ps
T338 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3886206959 Jan 17 03:54:26 PM PST 24 Jan 17 03:57:55 PM PST 24 61449251492 ps
T339 /workspace/coverage/default/36.rom_ctrl_smoke.2272406361 Jan 17 03:55:21 PM PST 24 Jan 17 03:55:54 PM PST 24 15985751262 ps
T340 /workspace/coverage/default/47.rom_ctrl_alert_test.3471252135 Jan 17 03:55:50 PM PST 24 Jan 17 03:56:00 PM PST 24 994366008 ps
T341 /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2346887271 Jan 17 03:53:41 PM PST 24 Jan 17 03:56:18 PM PST 24 10527716977 ps
T342 /workspace/coverage/default/21.rom_ctrl_smoke.488701173 Jan 17 03:54:29 PM PST 24 Jan 17 03:54:44 PM PST 24 363693747 ps
T343 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4179862533 Jan 17 03:55:36 PM PST 24 Jan 17 03:55:44 PM PST 24 189003897 ps
T344 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2200872558 Jan 17 03:54:52 PM PST 24 Jan 17 03:55:08 PM PST 24 3100579537 ps
T345 /workspace/coverage/default/42.rom_ctrl_stress_all.868863735 Jan 17 03:55:36 PM PST 24 Jan 17 03:56:10 PM PST 24 3219509573 ps
T49 /workspace/coverage/default/2.rom_ctrl_sec_cm.4021917834 Jan 17 03:53:42 PM PST 24 Jan 17 03:55:36 PM PST 24 476943616 ps
T346 /workspace/coverage/default/0.rom_ctrl_alert_test.3774494769 Jan 17 03:53:39 PM PST 24 Jan 17 03:53:56 PM PST 24 7531202046 ps
T347 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1518897312 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:05 PM PST 24 971942316 ps
T348 /workspace/coverage/default/24.rom_ctrl_smoke.561731937 Jan 17 03:54:41 PM PST 24 Jan 17 03:54:53 PM PST 24 758586308 ps
T349 /workspace/coverage/default/6.rom_ctrl_alert_test.329004031 Jan 17 03:53:57 PM PST 24 Jan 17 03:54:09 PM PST 24 954179317 ps
T350 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1154670636 Jan 17 03:54:20 PM PST 24 Jan 17 03:54:48 PM PST 24 2712653845 ps
T351 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3164533441 Jan 17 03:54:31 PM PST 24 Jan 17 03:56:31 PM PST 24 1819067741 ps
T352 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1994127108 Jan 17 03:54:55 PM PST 24 Jan 17 03:55:05 PM PST 24 266677413 ps
T353 /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2584371544 Jan 17 03:54:47 PM PST 24 Jan 17 03:58:46 PM PST 24 39434910517 ps
T354 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1535184640 Jan 17 03:54:00 PM PST 24 Jan 17 03:54:11 PM PST 24 170076496 ps
T355 /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3425437892 Jan 17 03:55:22 PM PST 24 Jan 17 03:55:41 PM PST 24 7499665342 ps
T356 /workspace/coverage/default/27.rom_ctrl_alert_test.4195846270 Jan 17 03:54:54 PM PST 24 Jan 17 03:55:12 PM PST 24 2091425277 ps
T357 /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4256903912 Jan 17 03:54:15 PM PST 24 Jan 17 04:06:12 PM PST 24 26505053666 ps
T103 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1808138915 Jan 17 03:55:24 PM PST 24 Jan 17 04:39:26 PM PST 24 90885081000 ps
T358 /workspace/coverage/default/9.rom_ctrl_smoke.4147604647 Jan 17 03:53:59 PM PST 24 Jan 17 03:54:26 PM PST 24 34245978556 ps
T359 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1359118458 Jan 17 03:55:20 PM PST 24 Jan 17 04:22:38 PM PST 24 45101642846 ps
T360 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2214557451 Jan 17 03:53:35 PM PST 24 Jan 17 03:53:57 PM PST 24 1947246429 ps
T50 /workspace/coverage/default/4.rom_ctrl_sec_cm.3894270997 Jan 17 03:53:50 PM PST 24 Jan 17 03:54:59 PM PST 24 3951244172 ps
T361 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2014710710 Jan 17 03:54:07 PM PST 24 Jan 17 03:54:19 PM PST 24 913528569 ps
T362 /workspace/coverage/default/14.rom_ctrl_smoke.2785646356 Jan 17 03:54:19 PM PST 24 Jan 17 03:54:47 PM PST 24 9717651910 ps
T363 /workspace/coverage/default/21.rom_ctrl_alert_test.1352238255 Jan 17 03:54:37 PM PST 24 Jan 17 03:54:50 PM PST 24 657916644 ps
T364 /workspace/coverage/default/45.rom_ctrl_smoke.1107892473 Jan 17 03:55:49 PM PST 24 Jan 17 03:56:21 PM PST 24 6312759073 ps
T365 /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.282127970 Jan 17 03:53:41 PM PST 24 Jan 17 03:56:22 PM PST 24 10076711894 ps
T366 /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.463674932 Jan 17 03:55:06 PM PST 24 Jan 17 03:55:29 PM PST 24 1967579118 ps
T367 /workspace/coverage/default/24.rom_ctrl_alert_test.655031040 Jan 17 03:54:57 PM PST 24 Jan 17 03:55:09 PM PST 24 899420873 ps
T368 /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2649460779 Jan 17 03:55:56 PM PST 24 Jan 17 03:56:11 PM PST 24 1619731019 ps
T369 /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2713259927 Jan 17 03:55:05 PM PST 24 Jan 17 04:40:24 PM PST 24 16761790846 ps
T370 /workspace/coverage/default/31.rom_ctrl_alert_test.757899027 Jan 17 03:55:11 PM PST 24 Jan 17 03:55:19 PM PST 24 1381427400 ps
T371 /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3263108767 Jan 17 03:54:08 PM PST 24 Jan 17 03:54:30 PM PST 24 3756976444 ps
T372 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2998573336 Jan 17 03:54:39 PM PST 24 Jan 17 04:26:36 PM PST 24 95844036083 ps
T373 /workspace/coverage/default/16.rom_ctrl_stress_all.3453962721 Jan 17 03:54:21 PM PST 24 Jan 17 03:55:23 PM PST 24 14065097266 ps
T374 /workspace/coverage/default/46.rom_ctrl_alert_test.2301251010 Jan 17 03:55:54 PM PST 24 Jan 17 03:56:11 PM PST 24 1714023557 ps
T375 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1434107210 Jan 17 03:54:21 PM PST 24 Jan 17 03:54:54 PM PST 24 16377330055 ps
T14 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2736039804 Jan 17 03:55:33 PM PST 24 Jan 17 05:25:03 PM PST 24 13741103109 ps
T376 /workspace/coverage/default/40.rom_ctrl_stress_all.1395853798 Jan 17 03:55:35 PM PST 24 Jan 17 03:56:04 PM PST 24 12601473320 ps
T377 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4219645581 Jan 17 03:53:38 PM PST 24 Jan 17 03:55:56 PM PST 24 2376054488 ps
T378 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.113058570 Jan 17 03:54:46 PM PST 24 Jan 17 03:55:12 PM PST 24 2452783136 ps
T379 /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.920614328 Jan 17 03:54:20 PM PST 24 Jan 17 03:54:35 PM PST 24 6460898458 ps
T380 /workspace/coverage/default/26.rom_ctrl_smoke.1237200445 Jan 17 03:54:53 PM PST 24 Jan 17 03:55:19 PM PST 24 4580582970 ps
T381 /workspace/coverage/default/16.rom_ctrl_alert_test.4222325813 Jan 17 03:54:22 PM PST 24 Jan 17 03:54:31 PM PST 24 625838512 ps
T382 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.142698817 Jan 17 03:55:21 PM PST 24 Jan 17 03:55:43 PM PST 24 2469897643 ps
T383 /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2453595556 Jan 17 03:55:05 PM PST 24 Jan 17 04:01:57 PM PST 24 146632312302 ps
T384 /workspace/coverage/default/10.rom_ctrl_stress_all.1675936844 Jan 17 03:54:02 PM PST 24 Jan 17 03:54:39 PM PST 24 2651845236 ps
T385 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3023637281 Jan 17 03:54:08 PM PST 24 Jan 17 04:03:15 PM PST 24 419239012831 ps
T386 /workspace/coverage/default/23.rom_ctrl_stress_all.3867648795 Jan 17 03:54:41 PM PST 24 Jan 17 03:55:08 PM PST 24 2897588165 ps
T387 /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1359806710 Jan 17 03:55:59 PM PST 24 Jan 17 03:56:12 PM PST 24 723004172 ps
T388 /workspace/coverage/default/48.rom_ctrl_smoke.3679916169 Jan 17 03:55:53 PM PST 24 Jan 17 03:56:37 PM PST 24 17785265232 ps
T389 /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.37782969 Jan 17 03:55:55 PM PST 24 Jan 17 04:26:07 PM PST 24 82644216949 ps
T390 /workspace/coverage/default/29.rom_ctrl_stress_all.13313554 Jan 17 03:54:59 PM PST 24 Jan 17 03:56:00 PM PST 24 31972886941 ps
T391 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1478152321 Jan 17 03:54:30 PM PST 24 Jan 17 03:54:55 PM PST 24 1924330648 ps
T392 /workspace/coverage/default/45.rom_ctrl_stress_all.2883700577 Jan 17 03:55:45 PM PST 24 Jan 17 03:56:15 PM PST 24 10422699999 ps
T393 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3332842525 Jan 17 03:55:48 PM PST 24 Jan 17 03:55:57 PM PST 24 1189391646 ps
T394 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1041218424 Jan 17 03:55:07 PM PST 24 Jan 17 03:55:18 PM PST 24 340858337 ps
T395 /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1061654256 Jan 17 03:55:33 PM PST 24 Jan 17 04:01:29 PM PST 24 69927359962 ps
T396 /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3054130204 Jan 17 03:54:08 PM PST 24 Jan 17 04:25:24 PM PST 24 55160082137 ps
T397 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3246938513 Jan 17 03:55:06 PM PST 24 Jan 17 04:02:53 PM PST 24 43789016244 ps
T398 /workspace/coverage/default/38.rom_ctrl_alert_test.1674396211 Jan 17 03:55:34 PM PST 24 Jan 17 03:55:48 PM PST 24 2662690195 ps
T399 /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2579602160 Jan 17 03:53:40 PM PST 24 Jan 17 03:53:47 PM PST 24 368268940 ps
T400 /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3175595034 Jan 17 03:55:22 PM PST 24 Jan 17 04:02:29 PM PST 24 336582214000 ps
T401 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2640464988 Jan 17 03:53:52 PM PST 24 Jan 17 03:54:06 PM PST 24 2738754190 ps
T402 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1566719985 Jan 17 03:54:18 PM PST 24 Jan 17 03:54:34 PM PST 24 1770844148 ps
T403 /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2086446704 Jan 17 03:53:42 PM PST 24 Jan 17 03:53:53 PM PST 24 221084005 ps
T404 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3984531845 Jan 17 03:55:01 PM PST 24 Jan 17 03:58:53 PM PST 24 21099436560 ps
T405 /workspace/coverage/default/15.rom_ctrl_alert_test.1530311172 Jan 17 03:54:20 PM PST 24 Jan 17 03:54:38 PM PST 24 2122135638 ps
T406 /workspace/coverage/default/12.rom_ctrl_alert_test.1829102880 Jan 17 03:54:08 PM PST 24 Jan 17 03:54:13 PM PST 24 346718734 ps
T407 /workspace/coverage/default/26.rom_ctrl_stress_all.1352467336 Jan 17 03:54:58 PM PST 24 Jan 17 03:55:32 PM PST 24 2505657284 ps
T408 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1386189526 Jan 17 03:55:48 PM PST 24 Jan 17 03:56:21 PM PST 24 16413470238 ps
T409 /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1328258514 Jan 17 03:54:05 PM PST 24 Jan 17 03:54:26 PM PST 24 2242043161 ps
T410 /workspace/coverage/default/19.rom_ctrl_smoke.2771881027 Jan 17 03:54:31 PM PST 24 Jan 17 03:55:14 PM PST 24 3385320391 ps
T411 /workspace/coverage/default/7.rom_ctrl_alert_test.3307643070 Jan 17 03:54:05 PM PST 24 Jan 17 03:54:19 PM PST 24 1145008265 ps
T412 /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1883573569 Jan 17 03:53:55 PM PST 24 Jan 17 04:02:07 PM PST 24 54075996683 ps
T413 /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4168340382 Jan 17 03:54:22 PM PST 24 Jan 17 03:54:37 PM PST 24 5136430345 ps
T414 /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2023171425 Jan 17 03:54:24 PM PST 24 Jan 17 04:00:23 PM PST 24 95397636278 ps
T415 /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2359402084 Jan 17 03:55:57 PM PST 24 Jan 17 03:56:30 PM PST 24 15459304067 ps
T416 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1182530 Jan 17 03:54:29 PM PST 24 Jan 17 03:54:46 PM PST 24 1012016736 ps
T417 /workspace/coverage/default/11.rom_ctrl_stress_all.3152811943 Jan 17 03:54:05 PM PST 24 Jan 17 03:54:38 PM PST 24 2938190125 ps
T418 /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1078130933 Jan 17 03:54:59 PM PST 24 Jan 17 03:55:09 PM PST 24 694358971 ps
T419 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1665273919 Jan 17 03:55:19 PM PST 24 Jan 17 03:55:55 PM PST 24 17265919385 ps
T420 /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.801005496 Jan 17 03:54:32 PM PST 24 Jan 17 03:54:47 PM PST 24 1240991448 ps
T421 /workspace/coverage/default/37.rom_ctrl_stress_all.1265176311 Jan 17 03:55:24 PM PST 24 Jan 17 03:56:00 PM PST 24 15332125272 ps
T422 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2438188084 Jan 17 03:55:59 PM PST 24 Jan 17 04:34:47 PM PST 24 58161025297 ps
T423 /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1300146482 Jan 17 03:54:18 PM PST 24 Jan 17 03:54:37 PM PST 24 1161976753 ps
T424 /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1458624224 Jan 17 03:54:25 PM PST 24 Jan 17 03:58:07 PM PST 24 10711359245 ps
T425 /workspace/coverage/default/49.rom_ctrl_alert_test.2373388581 Jan 17 03:55:57 PM PST 24 Jan 17 03:56:10 PM PST 24 3269119307 ps
T426 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.639500628 Jan 17 03:55:49 PM PST 24 Jan 17 03:56:05 PM PST 24 5281386635 ps
T427 /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2869800734 Jan 17 03:55:49 PM PST 24 Jan 17 03:56:10 PM PST 24 2952696955 ps
T428 /workspace/coverage/default/34.rom_ctrl_stress_all.3364519659 Jan 17 03:55:20 PM PST 24 Jan 17 03:55:46 PM PST 24 4509597999 ps
T429 /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4216965939 Jan 17 03:53:56 PM PST 24 Jan 17 03:54:05 PM PST 24 1398540072 ps
T430 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2251049981 Jan 17 12:53:22 PM PST 24 Jan 17 12:53:38 PM PST 24 6724146961 ps
T431 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1299663199 Jan 17 12:52:48 PM PST 24 Jan 17 12:53:03 PM PST 24 6428338028 ps
T96 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2368701771 Jan 17 12:53:21 PM PST 24 Jan 17 12:53:31 PM PST 24 593874305 ps
T91 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1676472827 Jan 17 12:52:59 PM PST 24 Jan 17 12:53:17 PM PST 24 623464645 ps
T432 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1976764363 Jan 17 12:53:41 PM PST 24 Jan 17 12:53:47 PM PST 24 199940254 ps
T433 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3712367654 Jan 17 12:52:51 PM PST 24 Jan 17 12:53:08 PM PST 24 3839117212 ps
T434 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.91305054 Jan 17 12:53:15 PM PST 24 Jan 17 12:53:24 PM PST 24 643939437 ps
T435 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1995891252 Jan 17 12:52:49 PM PST 24 Jan 17 12:53:01 PM PST 24 808735077 ps
T436 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1401939666 Jan 17 12:53:38 PM PST 24 Jan 17 12:53:50 PM PST 24 653281413 ps
T437 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1682260409 Jan 17 12:53:21 PM PST 24 Jan 17 12:53:35 PM PST 24 3729402889 ps
T438 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2759682249 Jan 17 12:53:24 PM PST 24 Jan 17 12:53:42 PM PST 24 1665017239 ps
T92 /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.123535158 Jan 17 12:53:20 PM PST 24 Jan 17 12:56:12 PM PST 24 25359683460 ps
T439 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.270535347 Jan 17 12:53:09 PM PST 24 Jan 17 12:53:20 PM PST 24 1603782063 ps
T93 /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3332854722 Jan 17 12:53:25 PM PST 24 Jan 17 12:55:51 PM PST 24 16757519605 ps
T440 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2434224478 Jan 17 12:53:06 PM PST 24 Jan 17 12:53:13 PM PST 24 519348692 ps
T441 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3367215338 Jan 17 12:52:56 PM PST 24 Jan 17 12:53:02 PM PST 24 332779736 ps
T442 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1784927355 Jan 17 12:53:17 PM PST 24 Jan 17 12:53:35 PM PST 24 2124485487 ps
T443 /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1326777186 Jan 17 12:53:26 PM PST 24 Jan 17 12:56:00 PM PST 24 56849847205 ps
T444 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2132009332 Jan 17 12:53:17 PM PST 24 Jan 17 12:53:25 PM PST 24 89106530 ps
T445 /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4139095007 Jan 17 12:53:16 PM PST 24 Jan 17 12:53:29 PM PST 24 6584798421 ps
T446 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1664839572 Jan 17 12:52:51 PM PST 24 Jan 17 12:53:01 PM PST 24 2612238479 ps
T447 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1012789671 Jan 17 12:53:08 PM PST 24 Jan 17 12:53:19 PM PST 24 2070989760 ps
T448 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1595243947 Jan 17 12:53:28 PM PST 24 Jan 17 12:53:36 PM PST 24 89039157 ps
T449 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.275481880 Jan 17 12:52:50 PM PST 24 Jan 17 12:52:55 PM PST 24 1307571373 ps
T450 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1414728585 Jan 17 12:53:15 PM PST 24 Jan 17 12:53:28 PM PST 24 3238929640 ps
T451 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1602625451 Jan 17 12:52:56 PM PST 24 Jan 17 12:53:08 PM PST 24 945568611 ps
T452 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2326201436 Jan 17 12:53:09 PM PST 24 Jan 17 12:53:26 PM PST 24 1813008843 ps
T453 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.339735043 Jan 17 12:52:54 PM PST 24 Jan 17 12:53:09 PM PST 24 2566020381 ps
T95 /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1124265736 Jan 17 12:53:36 PM PST 24 Jan 17 12:59:34 PM PST 24 68372618877 ps
T454 /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3657856665 Jan 17 12:53:01 PM PST 24 Jan 17 12:55:40 PM PST 24 16689095599 ps
T455 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1838696085 Jan 17 12:53:22 PM PST 24 Jan 17 12:53:37 PM PST 24 855582211 ps
T456 /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3021104436 Jan 17 12:52:56 PM PST 24 Jan 17 12:53:07 PM PST 24 3064500444 ps
T457 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2560708863 Jan 17 12:52:56 PM PST 24 Jan 17 12:53:06 PM PST 24 2288245720 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.173835387 Jan 17 12:52:53 PM PST 24 Jan 17 12:53:01 PM PST 24 347486529 ps
T459 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3895215527 Jan 17 12:53:19 PM PST 24 Jan 17 12:55:03 PM PST 24 8482790784 ps
T460 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1176756257 Jan 17 12:53:09 PM PST 24 Jan 17 12:53:14 PM PST 24 86467684 ps
T461 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1950214997 Jan 17 12:53:37 PM PST 24 Jan 17 12:53:56 PM PST 24 3389876625 ps
T111 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1537945155 Jan 17 12:52:58 PM PST 24 Jan 17 12:54:25 PM PST 24 672001805 ps
T462 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.323208024 Jan 17 12:53:09 PM PST 24 Jan 17 12:53:23 PM PST 24 2030379438 ps
T463 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.89074812 Jan 17 12:52:59 PM PST 24 Jan 17 12:53:16 PM PST 24 5694366364 ps
T464 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1045959459 Jan 17 12:52:45 PM PST 24 Jan 17 12:53:00 PM PST 24 1881289574 ps
T97 /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.316206326 Jan 17 12:53:08 PM PST 24 Jan 17 12:54:02 PM PST 24 1021448748 ps
T465 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2122834968 Jan 17 12:53:51 PM PST 24 Jan 17 12:54:05 PM PST 24 3948446795 ps
T466 /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1353892237 Jan 17 12:53:07 PM PST 24 Jan 17 12:56:36 PM PST 24 23840828910 ps
T467 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1291884434 Jan 17 12:53:06 PM PST 24 Jan 17 12:53:12 PM PST 24 186552120 ps
T468 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2124727188 Jan 17 12:52:58 PM PST 24 Jan 17 12:53:12 PM PST 24 85596864 ps
T106 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4170172775 Jan 17 12:53:17 PM PST 24 Jan 17 12:54:38 PM PST 24 3902653419 ps
T469 /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1486951632 Jan 17 12:52:56 PM PST 24 Jan 17 12:53:47 PM PST 24 4058461071 ps
T470 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3661551199 Jan 17 12:53:09 PM PST 24 Jan 17 12:53:20 PM PST 24 4081740411 ps
T471 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.773481597 Jan 17 12:53:22 PM PST 24 Jan 17 12:53:34 PM PST 24 86241817 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2291096593 Jan 17 12:53:13 PM PST 24 Jan 17 12:54:34 PM PST 24 1271266386 ps
T98 /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3692796958 Jan 17 12:53:38 PM PST 24 Jan 17 12:55:25 PM PST 24 2327508260 ps
T472 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3121365383 Jan 17 12:53:49 PM PST 24 Jan 17 12:53:58 PM PST 24 2005362516 ps
T473 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.555948166 Jan 17 12:53:35 PM PST 24 Jan 17 12:54:25 PM PST 24 7394539840 ps
T107 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3314401792 Jan 17 12:52:53 PM PST 24 Jan 17 12:54:18 PM PST 24 8031660504 ps
T474 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.149971874 Jan 17 12:53:38 PM PST 24 Jan 17 12:53:50 PM PST 24 593035596 ps
T99 /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1313773134 Jan 17 12:53:51 PM PST 24 Jan 17 12:54:45 PM PST 24 4062723362 ps
T475 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2175305212 Jan 17 12:53:16 PM PST 24 Jan 17 12:54:09 PM PST 24 9149705756 ps
T476 /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3165212490 Jan 17 12:53:29 PM PST 24 Jan 17 12:53:42 PM PST 24 4602679140 ps
T477 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1034864896 Jan 17 12:53:51 PM PST 24 Jan 17 12:54:08 PM PST 24 8391859658 ps
T478 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1438085055 Jan 17 12:53:52 PM PST 24 Jan 17 12:54:06 PM PST 24 6163521394 ps
T479 /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3650693076 Jan 17 12:53:26 PM PST 24 Jan 17 12:53:44 PM PST 24 6844804796 ps
T480 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1289310652 Jan 17 12:53:51 PM PST 24 Jan 17 12:54:08 PM PST 24 8167908830 ps
T481 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3257995297 Jan 17 12:52:51 PM PST 24 Jan 17 12:53:11 PM PST 24 8131912259 ps

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2155090274
Short name T28
Test name
Test status
Simulation time 168369709 ps
CPU time 6.45 seconds
Started Jan 17 12:52:57 PM PST 24
Finished Jan 17 12:53:04 PM PST 24
Peak memory 219432 kb
Host smart-9b3304df-360a-4b16-b824-bf68e1bcd1a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155090274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2155090274
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all_with_rand_reset.1542626570
Short name T2
Test name
Test status
Simulation time 75290522150 ps
CPU time 4544.59 seconds
Started Jan 17 03:55:16 PM PST 24
Finished Jan 17 05:11:02 PM PST 24
Peak memory 235536 kb
Host smart-0c8c171f-7b53-4b78-a621-f00fe3f99ce8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542626570 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_stress_all_with_rand_reset.1542626570
Directory /workspace/32.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.713174043
Short name T45
Test name
Test status
Simulation time 76322799829 ps
CPU time 91.34 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:54:49 PM PST 24
Peak memory 211184 kb
Host smart-5f9a2503-0e59-4bc5-97ef-22e630e7af7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713174043 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_pa
ssthru_mem_tl_intg_err.713174043
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2430510621
Short name T66
Test name
Test status
Simulation time 855858098 ps
CPU time 74.61 seconds
Started Jan 17 12:53:29 PM PST 24
Finished Jan 17 12:54:45 PM PST 24
Peak memory 213692 kb
Host smart-d30dce48-95f8-480e-bf6d-4452ce0650d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430510621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2430510621
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.1205889713
Short name T35
Test name
Test status
Simulation time 423219520 ps
CPU time 9.4 seconds
Started Jan 17 12:53:10 PM PST 24
Finished Jan 17 12:53:21 PM PST 24
Peak memory 219428 kb
Host smart-43e9c016-b557-43d8-9249-19d6a9bd8d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205889713 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.1205889713
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1308988601
Short name T56
Test name
Test status
Simulation time 36060058203 ps
CPU time 452.06 seconds
Started Jan 17 03:55:50 PM PST 24
Finished Jan 17 04:03:24 PM PST 24
Peak memory 228032 kb
Host smart-b4da4b6c-fbac-45ea-b15e-2b3a78e6191b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308988601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.1308988601
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.181446029
Short name T11
Test name
Test status
Simulation time 95448721539 ps
CPU time 1906 seconds
Started Jan 17 03:55:41 PM PST 24
Finished Jan 17 04:27:28 PM PST 24
Peak memory 237832 kb
Host smart-22751647-738d-4709-b51e-eb8342f1bdfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181446029 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.181446029
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3370904872
Short name T33
Test name
Test status
Simulation time 5902167498 ps
CPU time 46.46 seconds
Started Jan 17 12:52:51 PM PST 24
Finished Jan 17 12:53:40 PM PST 24
Peak memory 212332 kb
Host smart-d9394178-5c37-4065-8d91-dbfc83ef16dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370904872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.3370904872
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.3768487683
Short name T39
Test name
Test status
Simulation time 327358005 ps
CPU time 57.82 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:54:39 PM PST 24
Peak memory 235968 kb
Host smart-1763f4c1-c28a-4d3b-8e13-34c88315c859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768487683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.3768487683
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.1995891252
Short name T435
Test name
Test status
Simulation time 808735077 ps
CPU time 11.05 seconds
Started Jan 17 12:52:49 PM PST 24
Finished Jan 17 12:53:01 PM PST 24
Peak memory 211208 kb
Host smart-d4ac96f9-c3cb-4874-bb32-809b216797af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995891252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_r
eset.1995891252
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.3314401792
Short name T107
Test name
Test status
Simulation time 8031660504 ps
CPU time 81.36 seconds
Started Jan 17 12:52:53 PM PST 24
Finished Jan 17 12:54:18 PM PST 24
Peak memory 211884 kb
Host smart-7f10290b-2018-45c8-ac26-ed238442196f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314401792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.3314401792
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3289959552
Short name T79
Test name
Test status
Simulation time 20068375802 ps
CPU time 264.78 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:57:45 PM PST 24
Peak memory 211268 kb
Host smart-52b5b219-8657-4f04-af5a-adcba31c3877
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289959552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3289959552
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.114852790
Short name T13
Test name
Test status
Simulation time 84951466374 ps
CPU time 3347.99 seconds
Started Jan 17 03:54:56 PM PST 24
Finished Jan 17 04:50:47 PM PST 24
Peak memory 252012 kb
Host smart-bbcee9c3-3057-479b-9867-06cb33bb5208
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114852790 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.114852790
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.1675936844
Short name T384
Test name
Test status
Simulation time 2651845236 ps
CPU time 31.16 seconds
Started Jan 17 03:54:02 PM PST 24
Finished Jan 17 03:54:39 PM PST 24
Peak memory 214776 kb
Host smart-fe7275a8-d588-491e-bc06-81bf92053095
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675936844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.1675936844
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2865121636
Short name T63
Test name
Test status
Simulation time 5742329611 ps
CPU time 16.61 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:53:36 PM PST 24
Peak memory 219476 kb
Host smart-6529ce9d-1b80-49cc-a214-76a41d23dd71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865121636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2865121636
Directory /workspace/12.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.2126923463
Short name T20
Test name
Test status
Simulation time 666876496 ps
CPU time 9.62 seconds
Started Jan 17 03:54:06 PM PST 24
Finished Jan 17 03:54:18 PM PST 24
Peak memory 211072 kb
Host smart-5e375cad-d9d8-44aa-bbd6-17fbc09a6c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126923463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.2126923463
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.3678294183
Short name T105
Test name
Test status
Simulation time 2371614354 ps
CPU time 75.77 seconds
Started Jan 17 12:53:50 PM PST 24
Finished Jan 17 12:55:08 PM PST 24
Peak memory 211556 kb
Host smart-17c523a8-1bb7-480f-bb4e-bdde70ea011f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678294183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.3678294183
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.744363205
Short name T196
Test name
Test status
Simulation time 14650112307 ps
CPU time 23.23 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:54:32 PM PST 24
Peak memory 211344 kb
Host smart-dd336e8c-d1d3-4876-83d5-6c9bb509aab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744363205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.744363205
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.4113456304
Short name T43
Test name
Test status
Simulation time 3065977467 ps
CPU time 8.41 seconds
Started Jan 17 03:54:06 PM PST 24
Finished Jan 17 03:54:17 PM PST 24
Peak memory 210956 kb
Host smart-abe9fad4-c50e-4a84-9393-dee620b7f531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113456304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.4113456304
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4174641930
Short name T102
Test name
Test status
Simulation time 19786038612 ps
CPU time 6957.31 seconds
Started Jan 17 03:54:06 PM PST 24
Finished Jan 17 05:50:06 PM PST 24
Peak memory 234088 kb
Host smart-a37873be-c895-41cb-8e07-82395a89a7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174641930 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_stress_all_with_rand_reset.4174641930
Directory /workspace/10.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3299458665
Short name T101
Test name
Test status
Simulation time 7022914305 ps
CPU time 116.3 seconds
Started Jan 17 03:53:46 PM PST 24
Finished Jan 17 03:55:44 PM PST 24
Peak memory 237424 kb
Host smart-ec6f490c-7fcb-43ac-b32c-770ef6ba1d8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299458665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_c
orrupt_sig_fatal_chk.3299458665
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.1322534863
Short name T72
Test name
Test status
Simulation time 201190982 ps
CPU time 5.12 seconds
Started Jan 17 12:53:15 PM PST 24
Finished Jan 17 12:53:22 PM PST 24
Peak memory 211212 kb
Host smart-65526cdb-c938-4d2d-aa15-cdd6643bd563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322534863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.1322534863
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2208560777
Short name T18
Test name
Test status
Simulation time 2343583134 ps
CPU time 26.05 seconds
Started Jan 17 03:53:34 PM PST 24
Finished Jan 17 03:54:06 PM PST 24
Peak memory 216972 kb
Host smart-047a86ad-00b1-48ab-8f52-a8c396077611
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208560777 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2208560777
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4248239877
Short name T32
Test name
Test status
Simulation time 3951758233 ps
CPU time 15.89 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:53:07 PM PST 24
Peak memory 211284 kb
Host smart-2980383c-a8cb-49d3-a4ec-ce97e7621219
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248239877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4248239877
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.1949013444
Short name T135
Test name
Test status
Simulation time 1874626314 ps
CPU time 15.6 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:53:06 PM PST 24
Peak memory 211184 kb
Host smart-091feb2f-3eb0-4cf1-9299-0bbef6db9048
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949013444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.1949013444
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.3257995297
Short name T481
Test name
Test status
Simulation time 8131912259 ps
CPU time 17.55 seconds
Started Jan 17 12:52:51 PM PST 24
Finished Jan 17 12:53:11 PM PST 24
Peak memory 211188 kb
Host smart-12bdb782-c406-4a3d-bdf4-f7885f182006
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257995297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r
eset.3257995297
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.275481880
Short name T449
Test name
Test status
Simulation time 1307571373 ps
CPU time 4.76 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:52:55 PM PST 24
Peak memory 213560 kb
Host smart-e593aa8a-594c-4abb-bdd2-ac4a49e823cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275481880 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.275481880
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.4190188842
Short name T94
Test name
Test status
Simulation time 1317224363 ps
CPU time 6.41 seconds
Started Jan 17 12:52:47 PM PST 24
Finished Jan 17 12:52:54 PM PST 24
Peak memory 211116 kb
Host smart-7f7322f7-06a5-4369-b28f-2d9f5e95006e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190188842 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.4190188842
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.4154033086
Short name T130
Test name
Test status
Simulation time 918185738 ps
CPU time 9.45 seconds
Started Jan 17 12:52:47 PM PST 24
Finished Jan 17 12:52:57 PM PST 24
Peak memory 211192 kb
Host smart-817cc343-5bfa-43d8-b7e4-7865c52384e1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154033086 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.4154033086
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1045959459
Short name T464
Test name
Test status
Simulation time 1881289574 ps
CPU time 15.21 seconds
Started Jan 17 12:52:45 PM PST 24
Finished Jan 17 12:53:00 PM PST 24
Peak memory 211220 kb
Host smart-80689e05-80d8-4303-8f23-d588ec9a8f39
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045959459 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1045959459
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1755210222
Short name T47
Test name
Test status
Simulation time 5022231704 ps
CPU time 90.5 seconds
Started Jan 17 12:52:48 PM PST 24
Finished Jan 17 12:54:19 PM PST 24
Peak memory 211252 kb
Host smart-c88b8bdf-71cc-4d83-bf01-35a536090238
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755210222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1755210222
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.3452104265
Short name T37
Test name
Test status
Simulation time 747860451 ps
CPU time 6.28 seconds
Started Jan 17 12:52:49 PM PST 24
Finished Jan 17 12:52:56 PM PST 24
Peak memory 211172 kb
Host smart-9647fc15-b41c-49b1-b5ca-3b1a8af9df20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452104265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.3452104265
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3485693995
Short name T123
Test name
Test status
Simulation time 460318765 ps
CPU time 10.3 seconds
Started Jan 17 12:52:45 PM PST 24
Finished Jan 17 12:52:56 PM PST 24
Peak memory 219424 kb
Host smart-37bf1e80-c378-469d-a6ab-2ff9c56c2f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485693995 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3485693995
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2439005046
Short name T108
Test name
Test status
Simulation time 4371988667 ps
CPU time 44.42 seconds
Started Jan 17 12:52:47 PM PST 24
Finished Jan 17 12:53:32 PM PST 24
Peak memory 212664 kb
Host smart-07ab2f14-1718-4f07-82f3-e2b67ebf3965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439005046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2439005046
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.1664839572
Short name T446
Test name
Test status
Simulation time 2612238479 ps
CPU time 8.58 seconds
Started Jan 17 12:52:51 PM PST 24
Finished Jan 17 12:53:01 PM PST 24
Peak memory 211256 kb
Host smart-96594702-45f4-414a-abbd-2499ea7060e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664839572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.1664839572
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.1299663199
Short name T431
Test name
Test status
Simulation time 6428338028 ps
CPU time 14.23 seconds
Started Jan 17 12:52:48 PM PST 24
Finished Jan 17 12:53:03 PM PST 24
Peak memory 211236 kb
Host smart-46013493-df10-4aba-be9a-4909b5667463
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299663199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.1299663199
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.339735043
Short name T453
Test name
Test status
Simulation time 2566020381 ps
CPU time 12.17 seconds
Started Jan 17 12:52:54 PM PST 24
Finished Jan 17 12:53:09 PM PST 24
Peak memory 213788 kb
Host smart-7a85d80e-f574-4df3-a2f4-11783f9bf2b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339735043 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.339735043
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.173835387
Short name T458
Test name
Test status
Simulation time 347486529 ps
CPU time 4.32 seconds
Started Jan 17 12:52:53 PM PST 24
Finished Jan 17 12:53:01 PM PST 24
Peak memory 211200 kb
Host smart-14a9e215-fa97-4705-93c5-1f9a62a36345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173835387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.173835387
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.409310506
Short name T136
Test name
Test status
Simulation time 88047627 ps
CPU time 4.34 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:52:56 PM PST 24
Peak memory 211388 kb
Host smart-420db866-52ef-408a-952e-97df413ff30e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409310506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl
_mem_partial_access.409310506
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1617698263
Short name T29
Test name
Test status
Simulation time 3597195112 ps
CPU time 9.75 seconds
Started Jan 17 12:52:49 PM PST 24
Finished Jan 17 12:52:59 PM PST 24
Peak memory 211188 kb
Host smart-73040d5e-b9e3-4791-bb59-71d429dfec7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617698263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1617698263
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1696520669
Short name T77
Test name
Test status
Simulation time 16903184268 ps
CPU time 96.95 seconds
Started Jan 17 12:52:49 PM PST 24
Finished Jan 17 12:54:27 PM PST 24
Peak memory 211208 kb
Host smart-bcdc80c2-9bf7-4288-a16a-2582238e0207
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696520669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1696520669
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.1001280811
Short name T142
Test name
Test status
Simulation time 4236296971 ps
CPU time 11.38 seconds
Started Jan 17 12:52:52 PM PST 24
Finished Jan 17 12:53:05 PM PST 24
Peak memory 211208 kb
Host smart-c12bf687-9900-4575-b62e-b07b591b35c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001280811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c
trl_same_csr_outstanding.1001280811
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3712367654
Short name T433
Test name
Test status
Simulation time 3839117212 ps
CPU time 14.24 seconds
Started Jan 17 12:52:51 PM PST 24
Finished Jan 17 12:53:08 PM PST 24
Peak memory 219440 kb
Host smart-b6017516-622f-4463-a4d4-f17f62fd788e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712367654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3712367654
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.2627935151
Short name T114
Test name
Test status
Simulation time 198614465 ps
CPU time 5.16 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:53:32 PM PST 24
Peak memory 214820 kb
Host smart-989c2fac-9ea6-4b1b-bf36-32474630e018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627935151 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.2627935151
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.843146467
Short name T129
Test name
Test status
Simulation time 3764092741 ps
CPU time 10.32 seconds
Started Jan 17 12:53:28 PM PST 24
Finished Jan 17 12:53:39 PM PST 24
Peak memory 211280 kb
Host smart-07eece35-b553-4322-b8a5-dae6ddd9eb46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843146467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.843146467
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.3738950596
Short name T124
Test name
Test status
Simulation time 169010815 ps
CPU time 5.55 seconds
Started Jan 17 12:53:20 PM PST 24
Finished Jan 17 12:53:31 PM PST 24
Peak memory 211100 kb
Host smart-2cbf6921-fd7b-4f4e-9f52-0bf2195c05dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738950596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_
ctrl_same_csr_outstanding.3738950596
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1414728585
Short name T450
Test name
Test status
Simulation time 3238929640 ps
CPU time 11.88 seconds
Started Jan 17 12:53:15 PM PST 24
Finished Jan 17 12:53:28 PM PST 24
Peak memory 219484 kb
Host smart-c4bd21cb-a409-4a89-a11a-2dbf075fbc86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414728585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.1414728585
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.4170172775
Short name T106
Test name
Test status
Simulation time 3902653419 ps
CPU time 79.59 seconds
Started Jan 17 12:53:17 PM PST 24
Finished Jan 17 12:54:38 PM PST 24
Peak memory 211428 kb
Host smart-144a9890-c03a-4715-8980-9f5c457de40c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170172775 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.4170172775
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.1046961779
Short name T48
Test name
Test status
Simulation time 8409338893 ps
CPU time 16.05 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:53:36 PM PST 24
Peak memory 213132 kb
Host smart-adb7e773-71ce-49d8-b540-ad53b2360b8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046961779 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.1046961779
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2251049981
Short name T430
Test name
Test status
Simulation time 6724146961 ps
CPU time 10.79 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:53:38 PM PST 24
Peak memory 211332 kb
Host smart-a5f90948-3a37-4428-b71f-bfea05395fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251049981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2251049981
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.3895215527
Short name T459
Test name
Test status
Simulation time 8482790784 ps
CPU time 101.47 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:55:03 PM PST 24
Peak memory 211220 kb
Host smart-fdd872a2-418f-46b4-b059-ce63e05d85cb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895215527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p
assthru_mem_tl_intg_err.3895215527
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.612986063
Short name T144
Test name
Test status
Simulation time 515589077 ps
CPU time 11.65 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:53:32 PM PST 24
Peak memory 219432 kb
Host smart-ecb82f0f-9d34-460d-91a2-43831c2ceeac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612986063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.612986063
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1193833659
Short name T110
Test name
Test status
Simulation time 2530303850 ps
CPU time 80.88 seconds
Started Jan 17 12:53:18 PM PST 24
Finished Jan 17 12:54:40 PM PST 24
Peak memory 211372 kb
Host smart-7a476065-4506-4ef7-9f59-f9ebcfbd7bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193833659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1193833659
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1385849027
Short name T34
Test name
Test status
Simulation time 1216719284 ps
CPU time 4.68 seconds
Started Jan 17 12:53:17 PM PST 24
Finished Jan 17 12:53:23 PM PST 24
Peak memory 211764 kb
Host smart-87816df4-7c53-4dce-bd30-c282e11c108a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385849027 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1385849027
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2759682249
Short name T438
Test name
Test status
Simulation time 1665017239 ps
CPU time 14.34 seconds
Started Jan 17 12:53:24 PM PST 24
Finished Jan 17 12:53:42 PM PST 24
Peak memory 211184 kb
Host smart-72222ffd-da9b-4d2e-bd79-0452e1104299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759682249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2759682249
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.123535158
Short name T92
Test name
Test status
Simulation time 25359683460 ps
CPU time 167.12 seconds
Started Jan 17 12:53:20 PM PST 24
Finished Jan 17 12:56:12 PM PST 24
Peak memory 211168 kb
Host smart-77baa8a1-40ab-4d47-9757-ab89ad93d22b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123535158 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.123535158
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3973069088
Short name T127
Test name
Test status
Simulation time 132253782 ps
CPU time 5.12 seconds
Started Jan 17 12:53:19 PM PST 24
Finished Jan 17 12:53:25 PM PST 24
Peak memory 211208 kb
Host smart-be0f281d-8cb9-43cf-bdf0-0bc4e81e8513
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973069088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3973069088
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2514097355
Short name T64
Test name
Test status
Simulation time 310052765 ps
CPU time 78.94 seconds
Started Jan 17 12:53:20 PM PST 24
Finished Jan 17 12:54:41 PM PST 24
Peak memory 212732 kb
Host smart-785d8ed4-908e-4fd8-ab88-fbc15b80fa54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514097355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2514097355
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.1838696085
Short name T455
Test name
Test status
Simulation time 855582211 ps
CPU time 10.26 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:53:37 PM PST 24
Peak memory 215272 kb
Host smart-b24a1841-3d30-4e03-9a47-0b322259d9a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838696085 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.1838696085
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.2368701771
Short name T96
Test name
Test status
Simulation time 593874305 ps
CPU time 4.38 seconds
Started Jan 17 12:53:21 PM PST 24
Finished Jan 17 12:53:31 PM PST 24
Peak memory 211140 kb
Host smart-5f905d51-89d6-47af-a6b6-7f6c496e6681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368701771 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.2368701771
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.3067354014
Short name T78
Test name
Test status
Simulation time 35052058594 ps
CPU time 297.15 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:58:24 PM PST 24
Peak memory 211332 kb
Host smart-9e089549-7de2-4451-936e-7cb509b21314
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067354014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.3067354014
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.3418845809
Short name T143
Test name
Test status
Simulation time 2448072573 ps
CPU time 11.34 seconds
Started Jan 17 12:53:21 PM PST 24
Finished Jan 17 12:53:38 PM PST 24
Peak memory 211132 kb
Host smart-ec9ca281-5cbf-4e39-b5bd-bc061da19d4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418845809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.3418845809
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1682260409
Short name T437
Test name
Test status
Simulation time 3729402889 ps
CPU time 8.96 seconds
Started Jan 17 12:53:21 PM PST 24
Finished Jan 17 12:53:35 PM PST 24
Peak memory 219436 kb
Host smart-d76e11bd-60e8-4a43-a6ab-a410cb413e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682260409 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.1682260409
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1507342307
Short name T82
Test name
Test status
Simulation time 1454907912 ps
CPU time 81.98 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:54:49 PM PST 24
Peak memory 211232 kb
Host smart-3a86123c-6466-4fbe-9ae3-97443bfe4cdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507342307 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.1507342307
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.4007002970
Short name T115
Test name
Test status
Simulation time 646106682 ps
CPU time 6.26 seconds
Started Jan 17 12:53:27 PM PST 24
Finished Jan 17 12:53:34 PM PST 24
Peak memory 215520 kb
Host smart-5a94481f-c231-4ec2-92c3-4195183ccc39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007002970 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.4007002970
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1114494907
Short name T121
Test name
Test status
Simulation time 171230211 ps
CPU time 4.37 seconds
Started Jan 17 12:53:28 PM PST 24
Finished Jan 17 12:53:33 PM PST 24
Peak memory 211228 kb
Host smart-e3263cc1-e601-45a7-a143-9084b9214407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114494907 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1114494907
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.3000325533
Short name T138
Test name
Test status
Simulation time 175348044 ps
CPU time 4.38 seconds
Started Jan 17 12:53:26 PM PST 24
Finished Jan 17 12:53:32 PM PST 24
Peak memory 211212 kb
Host smart-a97b6856-aa95-4875-8f1a-25a986b20d29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000325533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.3000325533
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.773481597
Short name T471
Test name
Test status
Simulation time 86241817 ps
CPU time 6.86 seconds
Started Jan 17 12:53:22 PM PST 24
Finished Jan 17 12:53:34 PM PST 24
Peak memory 219384 kb
Host smart-3fe0bb5e-efd8-4b32-9e2d-690289e7a623
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773481597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.773481597
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3152801766
Short name T85
Test name
Test status
Simulation time 12886701239 ps
CPU time 50.05 seconds
Started Jan 17 12:53:21 PM PST 24
Finished Jan 17 12:54:17 PM PST 24
Peak memory 212632 kb
Host smart-143cb2e2-b942-41c1-8b64-0af95212bed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152801766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3152801766
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.439374842
Short name T65
Test name
Test status
Simulation time 643891415 ps
CPU time 8.37 seconds
Started Jan 17 12:53:26 PM PST 24
Finished Jan 17 12:53:36 PM PST 24
Peak memory 211344 kb
Host smart-97dd06d9-7076-4557-a620-bb1c83bb1cec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439374842 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.439374842
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.3488281685
Short name T31
Test name
Test status
Simulation time 4178466761 ps
CPU time 16.88 seconds
Started Jan 17 12:53:28 PM PST 24
Finished Jan 17 12:53:46 PM PST 24
Peak memory 211256 kb
Host smart-29b3ce95-ce57-4139-bdef-efa2c448d42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488281685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.3488281685
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1326777186
Short name T443
Test name
Test status
Simulation time 56849847205 ps
CPU time 152.28 seconds
Started Jan 17 12:53:26 PM PST 24
Finished Jan 17 12:56:00 PM PST 24
Peak memory 211256 kb
Host smart-59deaaad-5e1b-4fd2-aee3-21087197278d
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326777186 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1326777186
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.3165212490
Short name T476
Test name
Test status
Simulation time 4602679140 ps
CPU time 11.24 seconds
Started Jan 17 12:53:29 PM PST 24
Finished Jan 17 12:53:42 PM PST 24
Peak memory 211244 kb
Host smart-13adc917-b388-40bc-ab31-4bc26fb2e019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165212490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.3165212490
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.1595243947
Short name T448
Test name
Test status
Simulation time 89039157 ps
CPU time 7.1 seconds
Started Jan 17 12:53:28 PM PST 24
Finished Jan 17 12:53:36 PM PST 24
Peak memory 219432 kb
Host smart-a75f6d5a-3cca-4ebd-a8f5-e1b8afe6adc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595243947 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.1595243947
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.1904063193
Short name T117
Test name
Test status
Simulation time 1715624145 ps
CPU time 8.15 seconds
Started Jan 17 12:53:37 PM PST 24
Finished Jan 17 12:53:49 PM PST 24
Peak memory 214340 kb
Host smart-fa8060f7-a59e-43a4-b38d-e4e0b1f84aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904063193 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.1904063193
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.1976764363
Short name T432
Test name
Test status
Simulation time 199940254 ps
CPU time 4.38 seconds
Started Jan 17 12:53:41 PM PST 24
Finished Jan 17 12:53:47 PM PST 24
Peak memory 211136 kb
Host smart-5ce92db2-4b16-42c8-a1db-c9067608e460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976764363 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.1976764363
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.3332854722
Short name T93
Test name
Test status
Simulation time 16757519605 ps
CPU time 143 seconds
Started Jan 17 12:53:25 PM PST 24
Finished Jan 17 12:55:51 PM PST 24
Peak memory 211256 kb
Host smart-b69b5335-a2de-4699-81b4-3fb50483e4cd
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332854722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_p
assthru_mem_tl_intg_err.3332854722
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.124010560
Short name T139
Test name
Test status
Simulation time 1322167852 ps
CPU time 8.81 seconds
Started Jan 17 12:53:36 PM PST 24
Finished Jan 17 12:53:49 PM PST 24
Peak memory 211196 kb
Host smart-47204927-1905-4cbd-bf23-266fe89f46da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124010560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_c
trl_same_csr_outstanding.124010560
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.3650693076
Short name T479
Test name
Test status
Simulation time 6844804796 ps
CPU time 16.24 seconds
Started Jan 17 12:53:26 PM PST 24
Finished Jan 17 12:53:44 PM PST 24
Peak memory 219392 kb
Host smart-53bb3c1d-151a-40bc-8bab-3b6835b80d03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650693076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.3650693076
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.3824196709
Short name T61
Test name
Test status
Simulation time 1728959264 ps
CPU time 42.02 seconds
Started Jan 17 12:53:27 PM PST 24
Finished Jan 17 12:54:10 PM PST 24
Peak memory 212244 kb
Host smart-79285cc9-8b84-4c00-91c1-1853389692b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824196709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_i
ntg_err.3824196709
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.877169458
Short name T141
Test name
Test status
Simulation time 1948216396 ps
CPU time 11.31 seconds
Started Jan 17 12:53:35 PM PST 24
Finished Jan 17 12:53:48 PM PST 24
Peak memory 219440 kb
Host smart-ef2ae2aa-11c2-468c-a772-9ed6830b283e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877169458 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.877169458
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.1401939666
Short name T436
Test name
Test status
Simulation time 653281413 ps
CPU time 8.49 seconds
Started Jan 17 12:53:38 PM PST 24
Finished Jan 17 12:53:50 PM PST 24
Peak memory 211196 kb
Host smart-19433b61-5ca4-4467-864a-df7e70ed9130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401939666 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.1401939666
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.3692796958
Short name T98
Test name
Test status
Simulation time 2327508260 ps
CPU time 103.06 seconds
Started Jan 17 12:53:38 PM PST 24
Finished Jan 17 12:55:25 PM PST 24
Peak memory 211268 kb
Host smart-14d01072-4052-4377-bdeb-98e2d0995a38
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692796958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_p
assthru_mem_tl_intg_err.3692796958
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.149971874
Short name T474
Test name
Test status
Simulation time 593035596 ps
CPU time 8.29 seconds
Started Jan 17 12:53:38 PM PST 24
Finished Jan 17 12:53:50 PM PST 24
Peak memory 211256 kb
Host smart-1b6b3fc0-d547-4720-8605-c237de144b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149971874 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_c
trl_same_csr_outstanding.149971874
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1950214997
Short name T461
Test name
Test status
Simulation time 3389876625 ps
CPU time 16.54 seconds
Started Jan 17 12:53:37 PM PST 24
Finished Jan 17 12:53:56 PM PST 24
Peak memory 219388 kb
Host smart-e11a49af-6a27-42ab-9d2e-a1ddaa9653c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950214997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1950214997
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.555948166
Short name T473
Test name
Test status
Simulation time 7394539840 ps
CPU time 48.5 seconds
Started Jan 17 12:53:35 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 212328 kb
Host smart-1c7f1785-418b-4751-8edf-9231b256864e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555948166 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in
tg_err.555948166
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.860894768
Short name T126
Test name
Test status
Simulation time 390884036 ps
CPU time 4.89 seconds
Started Jan 17 12:53:49 PM PST 24
Finished Jan 17 12:53:56 PM PST 24
Peak memory 214204 kb
Host smart-ff15fcac-f883-41a9-adca-9e3ea60fc17c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860894768 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.860894768
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.1289310652
Short name T480
Test name
Test status
Simulation time 8167908830 ps
CPU time 15.73 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:54:08 PM PST 24
Peak memory 211212 kb
Host smart-9874a01d-062c-4605-8f31-81f9664179d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289310652 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.1289310652
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1124265736
Short name T95
Test name
Test status
Simulation time 68372618877 ps
CPU time 354.37 seconds
Started Jan 17 12:53:36 PM PST 24
Finished Jan 17 12:59:34 PM PST 24
Peak memory 211272 kb
Host smart-4594283f-c03b-4a6e-b4a2-bbb60937f9b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124265736 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.1124265736
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.4132314268
Short name T81
Test name
Test status
Simulation time 2016444606 ps
CPU time 17.2 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:54:10 PM PST 24
Peak memory 211156 kb
Host smart-d01223bd-08ae-4fe4-8bc8-687881822fa1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132314268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.4132314268
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1482262915
Short name T83
Test name
Test status
Simulation time 1096300277 ps
CPU time 13.25 seconds
Started Jan 17 12:53:52 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 219436 kb
Host smart-45c21133-230f-4c82-a395-4c0ff097501f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482262915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1482262915
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3121365383
Short name T472
Test name
Test status
Simulation time 2005362516 ps
CPU time 6.82 seconds
Started Jan 17 12:53:49 PM PST 24
Finished Jan 17 12:53:58 PM PST 24
Peak memory 214704 kb
Host smart-8de27d4f-92b2-46d4-8cd9-32fb79dafa8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121365383 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3121365383
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1034864896
Short name T477
Test name
Test status
Simulation time 8391859658 ps
CPU time 15.82 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:54:08 PM PST 24
Peak memory 211244 kb
Host smart-b5fcb5be-c0d1-4bdc-9bf2-0a47725cbb21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034864896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1034864896
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1313773134
Short name T99
Test name
Test status
Simulation time 4062723362 ps
CPU time 52.57 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:54:45 PM PST 24
Peak memory 211240 kb
Host smart-a90bfff7-0193-45e1-9940-14a33ed5eff4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313773134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1313773134
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1438085055
Short name T478
Test name
Test status
Simulation time 6163521394 ps
CPU time 12.94 seconds
Started Jan 17 12:53:52 PM PST 24
Finished Jan 17 12:54:06 PM PST 24
Peak memory 211256 kb
Host smart-c9af51b8-d3c3-472e-8f3c-1d3afba54378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438085055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1438085055
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2122834968
Short name T465
Test name
Test status
Simulation time 3948446795 ps
CPU time 12.36 seconds
Started Jan 17 12:53:51 PM PST 24
Finished Jan 17 12:54:05 PM PST 24
Peak memory 219504 kb
Host smart-b91a0a8e-70a8-4b16-8bd8-bba0b18d4910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122834968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2122834968
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1629893550
Short name T104
Test name
Test status
Simulation time 1961623707 ps
CPU time 74.14 seconds
Started Jan 17 12:53:50 PM PST 24
Finished Jan 17 12:55:06 PM PST 24
Peak memory 213628 kb
Host smart-3178c400-5a60-4655-b477-f0e20eed1c36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629893550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.1629893550
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.37107712
Short name T71
Test name
Test status
Simulation time 203916720 ps
CPU time 5.6 seconds
Started Jan 17 12:52:52 PM PST 24
Finished Jan 17 12:53:00 PM PST 24
Peak memory 211184 kb
Host smart-7c684b6a-e25e-415c-b46e-2b7611bd7322
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107712 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_aliasi
ng.37107712
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.3634031277
Short name T36
Test name
Test status
Simulation time 8101593083 ps
CPU time 14.98 seconds
Started Jan 17 12:52:53 PM PST 24
Finished Jan 17 12:53:12 PM PST 24
Peak memory 211284 kb
Host smart-6798d07b-daf2-472a-854f-edb3a2b31927
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634031277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.3634031277
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.2151806243
Short name T118
Test name
Test status
Simulation time 326054494 ps
CPU time 7.76 seconds
Started Jan 17 12:52:52 PM PST 24
Finished Jan 17 12:53:02 PM PST 24
Peak memory 211148 kb
Host smart-eee70114-3bcd-437b-973c-e062b8077c8a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151806243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.2151806243
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3970568853
Short name T116
Test name
Test status
Simulation time 505130846 ps
CPU time 7.88 seconds
Started Jan 17 12:52:54 PM PST 24
Finished Jan 17 12:53:05 PM PST 24
Peak memory 213140 kb
Host smart-57528f9b-f481-4dcc-9b3e-4b210fe1f31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970568853 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.3970568853
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.590795422
Short name T122
Test name
Test status
Simulation time 1276336134 ps
CPU time 6.95 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:52:57 PM PST 24
Peak memory 211280 kb
Host smart-2d8a4599-b6b7-4de4-8003-85a7542482d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590795422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.590795422
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3286228805
Short name T119
Test name
Test status
Simulation time 4204368994 ps
CPU time 14.72 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:53:06 PM PST 24
Peak memory 211240 kb
Host smart-3bc28ad5-78a0-4b37-9706-952f4c034fb2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286228805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.3286228805
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.2761716540
Short name T80
Test name
Test status
Simulation time 7945444463 ps
CPU time 15.99 seconds
Started Jan 17 12:52:52 PM PST 24
Finished Jan 17 12:53:13 PM PST 24
Peak memory 211200 kb
Host smart-ddd943eb-85fe-4bd9-b176-769588f5d156
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761716540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.2761716540
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2055438719
Short name T74
Test name
Test status
Simulation time 100260686529 ps
CPU time 187.08 seconds
Started Jan 17 12:52:49 PM PST 24
Finished Jan 17 12:55:57 PM PST 24
Peak memory 211268 kb
Host smart-bd5eae40-bfe3-4e02-9df9-f45daa39d03e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055438719 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.2055438719
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.3015935090
Short name T137
Test name
Test status
Simulation time 2706009739 ps
CPU time 14.11 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:53:04 PM PST 24
Peak memory 211268 kb
Host smart-eac4df9c-ec07-4d8f-9aa7-a5667e2ab134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015935090 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.3015935090
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.1597134980
Short name T30
Test name
Test status
Simulation time 10493688684 ps
CPU time 19.85 seconds
Started Jan 17 12:52:50 PM PST 24
Finished Jan 17 12:53:10 PM PST 24
Peak memory 219536 kb
Host smart-0d979a0c-0953-4f23-ac49-bce410c0d692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597134980 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.1597134980
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.2560708863
Short name T457
Test name
Test status
Simulation time 2288245720 ps
CPU time 8.2 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:06 PM PST 24
Peak memory 211272 kb
Host smart-1b5f7921-4e62-4cf1-a628-8e7103d3976b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560708863 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.2560708863
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3661551199
Short name T470
Test name
Test status
Simulation time 4081740411 ps
CPU time 10.67 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:20 PM PST 24
Peak memory 211272 kb
Host smart-1eca7540-85f0-4b20-b7f8-d35a2b6323df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661551199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_
bash.3661551199
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.1676472827
Short name T91
Test name
Test status
Simulation time 623464645 ps
CPU time 9.34 seconds
Started Jan 17 12:52:59 PM PST 24
Finished Jan 17 12:53:17 PM PST 24
Peak memory 211140 kb
Host smart-3d666032-57d7-4d30-b3d0-ca238335379d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676472827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.1676472827
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.1216853673
Short name T120
Test name
Test status
Simulation time 1935360888 ps
CPU time 15.04 seconds
Started Jan 17 12:53:01 PM PST 24
Finished Jan 17 12:53:23 PM PST 24
Peak memory 214476 kb
Host smart-66491124-bf8e-4469-b12e-242715ad27db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216853673 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.1216853673
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.89074812
Short name T463
Test name
Test status
Simulation time 5694366364 ps
CPU time 8.73 seconds
Started Jan 17 12:52:59 PM PST 24
Finished Jan 17 12:53:16 PM PST 24
Peak memory 211172 kb
Host smart-45760a82-affe-4389-9052-4d6d61210503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89074812 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.89074812
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.3367215338
Short name T441
Test name
Test status
Simulation time 332779736 ps
CPU time 4.25 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:02 PM PST 24
Peak memory 211212 kb
Host smart-3df23f23-ecec-4adc-8238-3f2582fe6dbc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367215338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.3367215338
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1176756257
Short name T460
Test name
Test status
Simulation time 86467684 ps
CPU time 4.4 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:14 PM PST 24
Peak memory 211208 kb
Host smart-94dbb347-2062-48b5-880a-c0da718d0a29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176756257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1176756257
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.1295299748
Short name T76
Test name
Test status
Simulation time 23470042379 ps
CPU time 250.8 seconds
Started Jan 17 12:52:57 PM PST 24
Finished Jan 17 12:57:17 PM PST 24
Peak memory 211264 kb
Host smart-2e84e24b-7568-4b01-a5e1-58584736ba20
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295299748 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa
ssthru_mem_tl_intg_err.1295299748
Directory /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1555318894
Short name T86
Test name
Test status
Simulation time 1577502615 ps
CPU time 15.35 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:25 PM PST 24
Peak memory 211212 kb
Host smart-914e3954-e8b3-408b-b10b-44f1c265b868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555318894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1555318894
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.323208024
Short name T462
Test name
Test status
Simulation time 2030379438 ps
CPU time 12.91 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:23 PM PST 24
Peak memory 219412 kb
Host smart-623ab0aa-32d2-4ac8-b722-8660db18c6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323208024 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.323208024
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1537945155
Short name T111
Test name
Test status
Simulation time 672001805 ps
CPU time 78.25 seconds
Started Jan 17 12:52:58 PM PST 24
Finished Jan 17 12:54:25 PM PST 24
Peak memory 212384 kb
Host smart-8818f3af-c08e-4824-ab25-2bf2a2dbd556
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537945155 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.1537945155
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3437790445
Short name T89
Test name
Test status
Simulation time 2170349289 ps
CPU time 16.47 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:14 PM PST 24
Peak memory 211284 kb
Host smart-19e6fba8-177b-4423-80d4-54bc996dc34d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437790445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3437790445
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.3815468379
Short name T128
Test name
Test status
Simulation time 508384493 ps
CPU time 7.91 seconds
Started Jan 17 12:52:55 PM PST 24
Finished Jan 17 12:53:05 PM PST 24
Peak memory 211148 kb
Host smart-22d78526-d112-4d1a-85e1-bf01c71975a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815468379 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.3815468379
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.2326201436
Short name T452
Test name
Test status
Simulation time 1813008843 ps
CPU time 16.39 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:26 PM PST 24
Peak memory 211212 kb
Host smart-d12d2245-f560-4c46-90c9-6e703d681966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326201436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.2326201436
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.1214230796
Short name T132
Test name
Test status
Simulation time 26087958492 ps
CPU time 16.47 seconds
Started Jan 17 12:52:55 PM PST 24
Finished Jan 17 12:53:14 PM PST 24
Peak memory 219472 kb
Host smart-f61439c3-f165-482e-95d4-d35ea7cf03e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214230796 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.1214230796
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.3488713914
Short name T131
Test name
Test status
Simulation time 929843188 ps
CPU time 7.27 seconds
Started Jan 17 12:52:58 PM PST 24
Finished Jan 17 12:53:14 PM PST 24
Peak memory 211192 kb
Host smart-ea764ea0-5cd4-457e-90aa-32d6ef8dd8d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488713914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.3488713914
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.1602625451
Short name T451
Test name
Test status
Simulation time 945568611 ps
CPU time 10.33 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:08 PM PST 24
Peak memory 211160 kb
Host smart-4d72841e-0229-42c8-9c1c-02d1cc9b1139
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602625451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.1602625451
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2124727188
Short name T468
Test name
Test status
Simulation time 85596864 ps
CPU time 4.37 seconds
Started Jan 17 12:52:58 PM PST 24
Finished Jan 17 12:53:12 PM PST 24
Peak memory 211204 kb
Host smart-870e868b-1fdc-4372-b942-e1e965defbb8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124727188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.2124727188
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.3657856665
Short name T454
Test name
Test status
Simulation time 16689095599 ps
CPU time 152.88 seconds
Started Jan 17 12:53:01 PM PST 24
Finished Jan 17 12:55:40 PM PST 24
Peak memory 211196 kb
Host smart-53defea3-b9c7-44d3-b446-ba544aac7ed7
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657856665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pa
ssthru_mem_tl_intg_err.3657856665
Directory /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3021104436
Short name T456
Test name
Test status
Simulation time 3064500444 ps
CPU time 9.23 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:07 PM PST 24
Peak memory 211284 kb
Host smart-42e04ce4-b84e-4fd1-8384-5269f4beb065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021104436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c
trl_same_csr_outstanding.3021104436
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.1486951632
Short name T469
Test name
Test status
Simulation time 4058461071 ps
CPU time 49.1 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:47 PM PST 24
Peak memory 212100 kb
Host smart-fafb0304-6596-4c72-9c8a-b0aa379037d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486951632 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.1486951632
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.270535347
Short name T439
Test name
Test status
Simulation time 1603782063 ps
CPU time 10.15 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:20 PM PST 24
Peak memory 219428 kb
Host smart-1835f145-71c2-4e1f-8110-367d0f17a26d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270535347 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.270535347
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.278585405
Short name T88
Test name
Test status
Simulation time 4955083376 ps
CPU time 12.81 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:23 PM PST 24
Peak memory 211292 kb
Host smart-46dafe9e-abbe-4e14-bafe-daa530c94f52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278585405 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.278585405
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.316206326
Short name T97
Test name
Test status
Simulation time 1021448748 ps
CPU time 53.09 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:54:02 PM PST 24
Peak memory 211192 kb
Host smart-231893de-b7d0-4de0-939c-bf7a75d6c15e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316206326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pas
sthru_mem_tl_intg_err.316206326
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.1011123722
Short name T133
Test name
Test status
Simulation time 2657972619 ps
CPU time 8.39 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:53:18 PM PST 24
Peak memory 211268 kb
Host smart-eb2bb40d-4802-4906-bb50-2bd6b28da08a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011123722 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.1011123722
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.1574799800
Short name T68
Test name
Test status
Simulation time 3060216220 ps
CPU time 18.15 seconds
Started Jan 17 12:52:56 PM PST 24
Finished Jan 17 12:53:16 PM PST 24
Peak memory 219492 kb
Host smart-39c1e343-b27c-4590-9763-b976a86bc1ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574799800 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.1574799800
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.3167736795
Short name T125
Test name
Test status
Simulation time 227259602 ps
CPU time 41.74 seconds
Started Jan 17 12:52:58 PM PST 24
Finished Jan 17 12:53:49 PM PST 24
Peak memory 212240 kb
Host smart-dfaccc14-b34b-4356-b18e-64da145a8098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167736795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.3167736795
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1990123549
Short name T62
Test name
Test status
Simulation time 8576087230 ps
CPU time 16.49 seconds
Started Jan 17 12:53:10 PM PST 24
Finished Jan 17 12:53:28 PM PST 24
Peak memory 215032 kb
Host smart-b6627676-0f6f-4140-ad90-583f5b445090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990123549 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1990123549
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.2434224478
Short name T440
Test name
Test status
Simulation time 519348692 ps
CPU time 5.08 seconds
Started Jan 17 12:53:06 PM PST 24
Finished Jan 17 12:53:13 PM PST 24
Peak memory 211196 kb
Host smart-06cf2e89-f54b-4b19-9724-f93a3c4f92c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434224478 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.2434224478
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.722247069
Short name T75
Test name
Test status
Simulation time 3976652655 ps
CPU time 103.15 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:54:52 PM PST 24
Peak memory 211252 kb
Host smart-262fa5d3-ee7d-48ae-af34-efb732fa80b9
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722247069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas
sthru_mem_tl_intg_err.722247069
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.1702036674
Short name T70
Test name
Test status
Simulation time 1875948671 ps
CPU time 14.72 seconds
Started Jan 17 12:53:09 PM PST 24
Finished Jan 17 12:53:24 PM PST 24
Peak memory 211212 kb
Host smart-46d61e7c-1098-465f-9458-ae38fb21e82c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702036674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.1702036674
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1012789671
Short name T447
Test name
Test status
Simulation time 2070989760 ps
CPU time 9.9 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:53:19 PM PST 24
Peak memory 213832 kb
Host smart-668bd60c-1479-4d41-a6f4-419b3f76654a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012789671 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1012789671
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.141426933
Short name T84
Test name
Test status
Simulation time 7836713235 ps
CPU time 83.44 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:54:32 PM PST 24
Peak memory 211908 kb
Host smart-47719ae6-e4d0-44b0-a8a3-33ede40c30c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141426933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_int
g_err.141426933
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.4139095007
Short name T445
Test name
Test status
Simulation time 6584798421 ps
CPU time 11.55 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:53:29 PM PST 24
Peak memory 215948 kb
Host smart-38aa4e07-8f40-49c9-a8a5-48e738d473b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139095007 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.4139095007
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.606296125
Short name T90
Test name
Test status
Simulation time 1970612003 ps
CPU time 10.63 seconds
Started Jan 17 12:53:08 PM PST 24
Finished Jan 17 12:53:19 PM PST 24
Peak memory 211280 kb
Host smart-4bafc860-2603-47b2-ad58-2864e80589c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606296125 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.606296125
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1353892237
Short name T466
Test name
Test status
Simulation time 23840828910 ps
CPU time 207.71 seconds
Started Jan 17 12:53:07 PM PST 24
Finished Jan 17 12:56:36 PM PST 24
Peak memory 211240 kb
Host smart-884eb6b2-2fbf-4869-9351-4edc1b5b76a2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353892237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1353892237
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.1291884434
Short name T467
Test name
Test status
Simulation time 186552120 ps
CPU time 4.43 seconds
Started Jan 17 12:53:06 PM PST 24
Finished Jan 17 12:53:12 PM PST 24
Peak memory 211184 kb
Host smart-0514005a-1349-4361-8ba6-af7dfdd25072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291884434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.1291884434
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.2291096593
Short name T109
Test name
Test status
Simulation time 1271266386 ps
CPU time 79.97 seconds
Started Jan 17 12:53:13 PM PST 24
Finished Jan 17 12:54:34 PM PST 24
Peak memory 211400 kb
Host smart-4fd0abf9-dacb-45eb-b50b-2d9911513543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291096593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.2291096593
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.2779749525
Short name T60
Test name
Test status
Simulation time 1344438088 ps
CPU time 12.24 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:53:29 PM PST 24
Peak memory 213876 kb
Host smart-b24ed6cd-d9c0-4102-abcb-ab56c90ff28b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779749525 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.2779749525
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.476133572
Short name T134
Test name
Test status
Simulation time 1158560274 ps
CPU time 11.37 seconds
Started Jan 17 12:53:14 PM PST 24
Finished Jan 17 12:53:26 PM PST 24
Peak memory 211216 kb
Host smart-0c8f2c6d-fae2-4cf1-bf04-66cb153d89d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476133572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.476133572
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.2381899244
Short name T46
Test name
Test status
Simulation time 3707966708 ps
CPU time 127.35 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:55:25 PM PST 24
Peak memory 210196 kb
Host smart-aad92d1c-35a4-4357-acf1-5848a0573e5e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381899244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa
ssthru_mem_tl_intg_err.2381899244
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2035022350
Short name T87
Test name
Test status
Simulation time 418189819 ps
CPU time 6.62 seconds
Started Jan 17 12:53:15 PM PST 24
Finished Jan 17 12:53:22 PM PST 24
Peak memory 211224 kb
Host smart-d1b64e98-7666-4aaa-823f-a0fde3528584
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035022350 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2035022350
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2132009332
Short name T444
Test name
Test status
Simulation time 89106530 ps
CPU time 6.98 seconds
Started Jan 17 12:53:17 PM PST 24
Finished Jan 17 12:53:25 PM PST 24
Peak memory 219428 kb
Host smart-d8127f45-5bdc-4c58-b77a-0a83742bd0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132009332 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.2132009332
Directory /workspace/8.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2175305212
Short name T475
Test name
Test status
Simulation time 9149705756 ps
CPU time 51.82 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:54:09 PM PST 24
Peak memory 212436 kb
Host smart-07c3079e-373b-4f6c-b82d-85f1762c81ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175305212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.2175305212
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.1338969164
Short name T140
Test name
Test status
Simulation time 383040746 ps
CPU time 6.11 seconds
Started Jan 17 12:53:18 PM PST 24
Finished Jan 17 12:53:25 PM PST 24
Peak memory 212588 kb
Host smart-a3ff9b5a-a3a4-4506-98e7-af2f21749387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338969164 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.1338969164
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.1784927355
Short name T442
Test name
Test status
Simulation time 2124485487 ps
CPU time 16.66 seconds
Started Jan 17 12:53:17 PM PST 24
Finished Jan 17 12:53:35 PM PST 24
Peak memory 211216 kb
Host smart-e3a15e5c-193e-4a24-ad1f-0b8282a76c33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784927355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.1784927355
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2546313029
Short name T73
Test name
Test status
Simulation time 34887799523 ps
CPU time 97.06 seconds
Started Jan 17 12:53:14 PM PST 24
Finished Jan 17 12:54:52 PM PST 24
Peak memory 211268 kb
Host smart-a2829ae6-da0a-4633-9fce-6c26dc2c3135
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546313029 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.2546313029
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.91305054
Short name T434
Test name
Test status
Simulation time 643939437 ps
CPU time 8.65 seconds
Started Jan 17 12:53:15 PM PST 24
Finished Jan 17 12:53:24 PM PST 24
Peak memory 211200 kb
Host smart-c17cd144-3b68-4543-930d-58de657b22ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91305054 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctr
l_same_csr_outstanding.91305054
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.447743621
Short name T67
Test name
Test status
Simulation time 4640615744 ps
CPU time 14.65 seconds
Started Jan 17 12:53:16 PM PST 24
Finished Jan 17 12:53:32 PM PST 24
Peak memory 218544 kb
Host smart-98bbc659-c8a7-49f3-bd3c-8f52bb374b87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447743621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.447743621
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.3509303527
Short name T69
Test name
Test status
Simulation time 10871293719 ps
CPU time 84.67 seconds
Started Jan 17 12:53:18 PM PST 24
Finished Jan 17 12:54:44 PM PST 24
Peak memory 211892 kb
Host smart-b8242c98-0830-45a2-a5a4-a0eedc47a28d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509303527 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.3509303527
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.3774494769
Short name T346
Test name
Test status
Simulation time 7531202046 ps
CPU time 15.23 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:53:56 PM PST 24
Peak memory 211000 kb
Host smart-259e4f91-2b9f-4963-9ba8-9f6533fa07eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774494769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.3774494769
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.580823148
Short name T187
Test name
Test status
Simulation time 45198175228 ps
CPU time 259.56 seconds
Started Jan 17 03:53:33 PM PST 24
Finished Jan 17 03:57:54 PM PST 24
Peak memory 233368 kb
Host smart-9be6c3ac-9f9e-4797-8f07-f6d598db8e97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580823148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_co
rrupt_sig_fatal_chk.580823148
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.1631906047
Short name T326
Test name
Test status
Simulation time 2315145351 ps
CPU time 23.24 seconds
Started Jan 17 03:53:34 PM PST 24
Finished Jan 17 03:54:04 PM PST 24
Peak memory 211644 kb
Host smart-b302490c-6ee9-48f9-9d32-362125bd212e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631906047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.1631906047
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.2214557451
Short name T360
Test name
Test status
Simulation time 1947246429 ps
CPU time 16.46 seconds
Started Jan 17 03:53:35 PM PST 24
Finished Jan 17 03:53:57 PM PST 24
Peak memory 210836 kb
Host smart-a4247cf7-68f1-4250-beb8-e1a327313510
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2214557451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.2214557451
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.2193663389
Short name T175
Test name
Test status
Simulation time 11219618831 ps
CPU time 39.53 seconds
Started Jan 17 03:53:34 PM PST 24
Finished Jan 17 03:54:18 PM PST 24
Peak memory 213552 kb
Host smart-acbedf39-6589-45df-b5e1-fa207402c921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193663389 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.2193663389
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.3880503946
Short name T243
Test name
Test status
Simulation time 2017487144 ps
CPU time 15.51 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:53:57 PM PST 24
Peak memory 210904 kb
Host smart-30162e6e-8f70-41dc-b5e3-227d075e6b71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880503946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.3880503946
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.4219645581
Short name T377
Test name
Test status
Simulation time 2376054488 ps
CPU time 134.61 seconds
Started Jan 17 03:53:38 PM PST 24
Finished Jan 17 03:55:56 PM PST 24
Peak memory 236620 kb
Host smart-22a11329-c810-403e-8d3e-4232e055d1b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219645581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.4219645581
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.2086446704
Short name T403
Test name
Test status
Simulation time 221084005 ps
CPU time 9.87 seconds
Started Jan 17 03:53:42 PM PST 24
Finished Jan 17 03:53:53 PM PST 24
Peak memory 210988 kb
Host smart-3cc88946-c537-4c1f-b475-a5ba4bf149f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086446704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.2086446704
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.1088250138
Short name T315
Test name
Test status
Simulation time 3869367201 ps
CPU time 17.14 seconds
Started Jan 17 03:53:37 PM PST 24
Finished Jan 17 03:53:58 PM PST 24
Peak memory 210928 kb
Host smart-084ff1ae-dc68-41a9-ba23-a71dedaabcae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088250138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.1088250138
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.1518098017
Short name T38
Test name
Test status
Simulation time 2240811111 ps
CPU time 67.32 seconds
Started Jan 17 03:53:40 PM PST 24
Finished Jan 17 03:54:49 PM PST 24
Peak memory 236476 kb
Host smart-44fe403e-db68-4394-aae0-e092ad394029
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518098017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.1518098017
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3602354786
Short name T179
Test name
Test status
Simulation time 359337640 ps
CPU time 10.18 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:53:51 PM PST 24
Peak memory 210820 kb
Host smart-7ee08039-3df7-4c14-8d76-931f5a703e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602354786 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3602354786
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.4184550751
Short name T236
Test name
Test status
Simulation time 530091301 ps
CPU time 9.05 seconds
Started Jan 17 03:53:40 PM PST 24
Finished Jan 17 03:53:50 PM PST 24
Peak memory 210680 kb
Host smart-fe44e932-51cc-49e3-8c2c-c7ecd138723c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184550751 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.rom_ctrl_stress_all.4184550751
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3124661003
Short name T305
Test name
Test status
Simulation time 217106291679 ps
CPU time 5586.33 seconds
Started Jan 17 03:53:37 PM PST 24
Finished Jan 17 05:26:48 PM PST 24
Peak memory 250400 kb
Host smart-81c2bb40-beed-4215-9386-cc419f0c066f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124661003 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3124661003
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3023637281
Short name T385
Test name
Test status
Simulation time 419239012831 ps
CPU time 546.41 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 04:03:15 PM PST 24
Peak memory 237408 kb
Host smart-b75a81e2-14d9-42b7-a891-8635f8316249
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023637281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.3023637281
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.2803527797
Short name T300
Test name
Test status
Simulation time 210646677 ps
CPU time 5.55 seconds
Started Jan 17 03:54:00 PM PST 24
Finished Jan 17 03:54:07 PM PST 24
Peak memory 210808 kb
Host smart-1f2ae21d-9838-4e5f-86a5-a56415a970be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803527797 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.2803527797
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2444979711
Short name T221
Test name
Test status
Simulation time 3248278367 ps
CPU time 34.49 seconds
Started Jan 17 03:54:01 PM PST 24
Finished Jan 17 03:54:36 PM PST 24
Peak memory 212288 kb
Host smart-baeb0012-fa01-45dd-be2c-3cbb74d30f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444979711 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2444979711
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.335072324
Short name T244
Test name
Test status
Simulation time 127243439 ps
CPU time 5.3 seconds
Started Jan 17 03:54:06 PM PST 24
Finished Jan 17 03:54:13 PM PST 24
Peak memory 210940 kb
Host smart-a984840a-b15e-49d2-b148-f24fd8190f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335072324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.335072324
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.2434446846
Short name T181
Test name
Test status
Simulation time 17356537176 ps
CPU time 183.97 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:57:12 PM PST 24
Peak memory 236572 kb
Host smart-3609b693-67a6-47b5-9dbe-5d714fd7910f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434446846 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.2434446846
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.3263108767
Short name T371
Test name
Test status
Simulation time 3756976444 ps
CPU time 21.23 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 03:54:30 PM PST 24
Peak memory 211076 kb
Host smart-0b54218c-b26e-4f44-bdee-ccaf77289037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263108767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.3263108767
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.2014710710
Short name T361
Test name
Test status
Simulation time 913528569 ps
CPU time 10.66 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:54:19 PM PST 24
Peak memory 210804 kb
Host smart-27cd46af-2733-47ed-848d-97295cf577f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014710710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.2014710710
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.3028724431
Short name T195
Test name
Test status
Simulation time 6405270309 ps
CPU time 29.06 seconds
Started Jan 17 03:54:06 PM PST 24
Finished Jan 17 03:54:37 PM PST 24
Peak memory 213724 kb
Host smart-a41b7899-de9b-4a10-a0aa-51769842285d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028724431 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3028724431
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.3152811943
Short name T417
Test name
Test status
Simulation time 2938190125 ps
CPU time 29.74 seconds
Started Jan 17 03:54:05 PM PST 24
Finished Jan 17 03:54:38 PM PST 24
Peak memory 214308 kb
Host smart-a63f8b22-4480-4885-a79a-cf867141cc31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152811943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.rom_ctrl_stress_all.3152811943
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1829102880
Short name T406
Test name
Test status
Simulation time 346718734 ps
CPU time 4.6 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 03:54:13 PM PST 24
Peak memory 211216 kb
Host smart-aa9ba23e-a859-4a72-9ef9-94e7a958dc5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829102880 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1829102880
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.1965289441
Short name T332
Test name
Test status
Simulation time 12358609076 ps
CPU time 15.6 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:54:24 PM PST 24
Peak memory 211016 kb
Host smart-2456a5ea-961c-435c-a5c9-2c9793ce05ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965289441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.1965289441
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.3048748369
Short name T230
Test name
Test status
Simulation time 718796417 ps
CPU time 10.18 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 03:54:19 PM PST 24
Peak memory 212396 kb
Host smart-c176ceac-229f-43f5-9b02-186ea17a83aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048748369 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.3048748369
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.2998796648
Short name T310
Test name
Test status
Simulation time 6891159295 ps
CPU time 32 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:54:40 PM PST 24
Peak memory 215960 kb
Host smart-66d18a9b-dc9f-45c3-b911-64b4701c87d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998796648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.rom_ctrl_stress_all.2998796648
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.3054130204
Short name T396
Test name
Test status
Simulation time 55160082137 ps
CPU time 1874.71 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 04:25:24 PM PST 24
Peak memory 232640 kb
Host smart-40f569b0-d96f-4672-b18f-df5957b95629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054130204 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.3054130204
Directory /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.625829490
Short name T203
Test name
Test status
Simulation time 340834033 ps
CPU time 6.56 seconds
Started Jan 17 03:54:08 PM PST 24
Finished Jan 17 03:54:15 PM PST 24
Peak memory 210948 kb
Host smart-258eb133-b4ca-4629-bc59-54dbba011716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625829490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.625829490
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.516136552
Short name T59
Test name
Test status
Simulation time 45561793872 ps
CPU time 415.98 seconds
Started Jan 17 03:54:18 PM PST 24
Finished Jan 17 04:01:15 PM PST 24
Peak memory 237340 kb
Host smart-fcc7fc49-a834-401c-872e-6b0615148d99
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516136552 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_c
orrupt_sig_fatal_chk.516136552
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.2838475816
Short name T316
Test name
Test status
Simulation time 175625224 ps
CPU time 9.57 seconds
Started Jan 17 03:54:13 PM PST 24
Finished Jan 17 03:54:23 PM PST 24
Peak memory 211288 kb
Host smart-e11ec202-d694-4c27-9e91-ac06807ddf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838475816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.2838475816
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.1914032729
Short name T192
Test name
Test status
Simulation time 268227275 ps
CPU time 6.08 seconds
Started Jan 17 03:54:21 PM PST 24
Finished Jan 17 03:54:28 PM PST 24
Peak memory 210820 kb
Host smart-c57d5285-7c34-4b33-aa39-9e2c8012a0a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914032729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.1914032729
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.271425862
Short name T318
Test name
Test status
Simulation time 367048040 ps
CPU time 10.69 seconds
Started Jan 17 03:54:07 PM PST 24
Finished Jan 17 03:54:19 PM PST 24
Peak memory 212564 kb
Host smart-6ee894fc-d048-49c5-98a1-5eaf55d72e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271425862 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.271425862
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.1975647964
Short name T269
Test name
Test status
Simulation time 19489121891 ps
CPU time 35.19 seconds
Started Jan 17 03:54:11 PM PST 24
Finished Jan 17 03:54:47 PM PST 24
Peak memory 214532 kb
Host smart-e1378759-689f-4d58-9910-fb926084ddd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975647964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.1975647964
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4256903912
Short name T357
Test name
Test status
Simulation time 26505053666 ps
CPU time 716.62 seconds
Started Jan 17 03:54:15 PM PST 24
Finished Jan 17 04:06:12 PM PST 24
Peak memory 223280 kb
Host smart-c1609620-8149-4fb6-b11a-d9ec4a73b420
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256903912 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_stress_all_with_rand_reset.4256903912
Directory /workspace/13.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2807541168
Short name T42
Test name
Test status
Simulation time 476215869 ps
CPU time 7.53 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:28 PM PST 24
Peak memory 210880 kb
Host smart-fcce8af2-059a-456c-94a7-ff300ed8217b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807541168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2807541168
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.689845737
Short name T17
Test name
Test status
Simulation time 3253461416 ps
CPU time 199.44 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:57:40 PM PST 24
Peak memory 237384 kb
Host smart-091e4243-3e31-447d-ad35-a7685bb43a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689845737 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_c
orrupt_sig_fatal_chk.689845737
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1434107210
Short name T375
Test name
Test status
Simulation time 16377330055 ps
CPU time 33.24 seconds
Started Jan 17 03:54:21 PM PST 24
Finished Jan 17 03:54:54 PM PST 24
Peak memory 211356 kb
Host smart-61cfb955-dd23-42c3-a86c-9962f3d6c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434107210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1434107210
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.920614328
Short name T379
Test name
Test status
Simulation time 6460898458 ps
CPU time 15.04 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:35 PM PST 24
Peak memory 210920 kb
Host smart-866a569e-9e3c-4702-8383-52ae0bc4ea89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920614328 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.920614328
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.2785646356
Short name T362
Test name
Test status
Simulation time 9717651910 ps
CPU time 26.96 seconds
Started Jan 17 03:54:19 PM PST 24
Finished Jan 17 03:54:47 PM PST 24
Peak memory 212908 kb
Host smart-fe044e5a-2b4a-47e8-bda7-2f0bba5e0294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785646356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.2785646356
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.1487726629
Short name T293
Test name
Test status
Simulation time 69458902800 ps
CPU time 145.45 seconds
Started Jan 17 03:54:22 PM PST 24
Finished Jan 17 03:56:48 PM PST 24
Peak memory 219068 kb
Host smart-dbdcd0a7-b772-474d-9483-69cd8603da2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487726629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.1487726629
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.422612103
Short name T147
Test name
Test status
Simulation time 165545956085 ps
CPU time 1971.72 seconds
Started Jan 17 03:54:23 PM PST 24
Finished Jan 17 04:27:17 PM PST 24
Peak memory 235584 kb
Host smart-7bdcb50d-db63-4abd-a892-f922c2885036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422612103 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.422612103
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.1530311172
Short name T405
Test name
Test status
Simulation time 2122135638 ps
CPU time 16.7 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:38 PM PST 24
Peak memory 210908 kb
Host smart-f0c6f573-d99e-4171-91d1-c4609cf77e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530311172 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.1530311172
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1481390464
Short name T146
Test name
Test status
Simulation time 147916801244 ps
CPU time 186.94 seconds
Started Jan 17 03:54:23 PM PST 24
Finished Jan 17 03:57:32 PM PST 24
Peak memory 233460 kb
Host smart-f8f7c853-7cc1-4ef2-be5b-202348d338c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481390464 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1481390464
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.1154670636
Short name T350
Test name
Test status
Simulation time 2712653845 ps
CPU time 27.05 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:48 PM PST 24
Peak memory 211084 kb
Host smart-2e3b1baa-c17f-47ee-9adc-b3931853faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154670636 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.1154670636
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.751380338
Short name T267
Test name
Test status
Simulation time 3084372349 ps
CPU time 9.6 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:30 PM PST 24
Peak memory 210844 kb
Host smart-2a7fa2e3-ed14-4db4-97f2-214a470f0dea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751380338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.751380338
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.3000716088
Short name T145
Test name
Test status
Simulation time 186661563 ps
CPU time 10.51 seconds
Started Jan 17 03:54:18 PM PST 24
Finished Jan 17 03:54:29 PM PST 24
Peak memory 212704 kb
Host smart-2fec6ea0-d684-43aa-9a4d-36a8d7054fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000716088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.3000716088
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.1371840316
Short name T190
Test name
Test status
Simulation time 12458428955 ps
CPU time 47.99 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:55:08 PM PST 24
Peak memory 216196 kb
Host smart-e1c76463-c5f1-4d99-bb18-63b322b077dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371840316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.1371840316
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.327370925
Short name T337
Test name
Test status
Simulation time 216584789019 ps
CPU time 2001.05 seconds
Started Jan 17 03:54:22 PM PST 24
Finished Jan 17 04:27:45 PM PST 24
Peak memory 236656 kb
Host smart-33d8d2a8-121f-44d7-a1b2-34dd88bd51e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327370925 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.327370925
Directory /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.4222325813
Short name T381
Test name
Test status
Simulation time 625838512 ps
CPU time 8.74 seconds
Started Jan 17 03:54:22 PM PST 24
Finished Jan 17 03:54:31 PM PST 24
Peak memory 210876 kb
Host smart-32e869bb-f52d-4b29-9157-1f8fabe743ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222325813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.4222325813
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2693803193
Short name T253
Test name
Test status
Simulation time 12050593862 ps
CPU time 153.67 seconds
Started Jan 17 03:54:21 PM PST 24
Finished Jan 17 03:56:55 PM PST 24
Peak memory 216388 kb
Host smart-cba1b242-4f78-4f83-a9ef-31efa8dc1a88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693803193 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2693803193
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.2911396271
Short name T249
Test name
Test status
Simulation time 334939435 ps
CPU time 9.86 seconds
Started Jan 17 03:54:21 PM PST 24
Finished Jan 17 03:54:31 PM PST 24
Peak memory 211136 kb
Host smart-df4314af-7da6-4754-9b91-806259a91053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911396271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.2911396271
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.4168340382
Short name T413
Test name
Test status
Simulation time 5136430345 ps
CPU time 13.93 seconds
Started Jan 17 03:54:22 PM PST 24
Finished Jan 17 03:54:37 PM PST 24
Peak memory 211204 kb
Host smart-51ee4e7f-a1a2-4899-a469-fea06b619464
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168340382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.4168340382
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2151647197
Short name T186
Test name
Test status
Simulation time 1211528306 ps
CPU time 18.34 seconds
Started Jan 17 03:54:22 PM PST 24
Finished Jan 17 03:54:41 PM PST 24
Peak memory 212292 kb
Host smart-a2acf2e1-3c21-4a3c-8524-ff74299b32d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151647197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2151647197
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.3453962721
Short name T373
Test name
Test status
Simulation time 14065097266 ps
CPU time 61.57 seconds
Started Jan 17 03:54:21 PM PST 24
Finished Jan 17 03:55:23 PM PST 24
Peak memory 216044 kb
Host smart-f5c09dca-6351-496f-bbf0-970be94ffcba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453962721 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 16.rom_ctrl_stress_all.3453962721
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2358970832
Short name T189
Test name
Test status
Simulation time 25362321352 ps
CPU time 358.9 seconds
Started Jan 17 03:54:19 PM PST 24
Finished Jan 17 04:00:19 PM PST 24
Peak memory 228768 kb
Host smart-575f240f-5f04-40c0-88e5-3964742e17bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358970832 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.2358970832
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.1787710249
Short name T297
Test name
Test status
Simulation time 1730158664 ps
CPU time 14.27 seconds
Started Jan 17 03:54:26 PM PST 24
Finished Jan 17 03:54:41 PM PST 24
Peak memory 210908 kb
Host smart-efe704be-289b-4784-9a8a-fea50b319ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787710249 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.1787710249
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2023171425
Short name T414
Test name
Test status
Simulation time 95397636278 ps
CPU time 356.83 seconds
Started Jan 17 03:54:24 PM PST 24
Finished Jan 17 04:00:23 PM PST 24
Peak memory 237472 kb
Host smart-ab965b00-5ec1-47b8-bdf0-aa1d7bc6e6df
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023171425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.2023171425
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2472560397
Short name T327
Test name
Test status
Simulation time 1084201550 ps
CPU time 16.94 seconds
Started Jan 17 03:54:28 PM PST 24
Finished Jan 17 03:54:51 PM PST 24
Peak memory 210900 kb
Host smart-bda9996a-594d-4648-8961-180b48e92513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472560397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2472560397
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1661572944
Short name T284
Test name
Test status
Simulation time 101377797 ps
CPU time 6.42 seconds
Started Jan 17 03:54:29 PM PST 24
Finished Jan 17 03:54:41 PM PST 24
Peak memory 210920 kb
Host smart-0347a88b-b421-421a-9a15-57addcff30aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1661572944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1661572944
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.1928294876
Short name T295
Test name
Test status
Simulation time 3953356760 ps
CPU time 38.32 seconds
Started Jan 17 03:54:19 PM PST 24
Finished Jan 17 03:54:58 PM PST 24
Peak memory 212516 kb
Host smart-b3f7e303-8f8c-4d65-89cb-20487539ef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928294876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.1928294876
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.1295888427
Short name T307
Test name
Test status
Simulation time 11183478087 ps
CPU time 30.64 seconds
Started Jan 17 03:54:20 PM PST 24
Finished Jan 17 03:54:51 PM PST 24
Peak memory 216828 kb
Host smart-36c2c01e-4aef-4642-898d-385975fa92f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295888427 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.1295888427
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.2041150887
Short name T330
Test name
Test status
Simulation time 2619666024 ps
CPU time 12.89 seconds
Started Jan 17 03:54:25 PM PST 24
Finished Jan 17 03:54:40 PM PST 24
Peak memory 210956 kb
Host smart-ab6d45c3-123c-46ef-85ed-68b92e7c52be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041150887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.2041150887
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3886206959
Short name T338
Test name
Test status
Simulation time 61449251492 ps
CPU time 207.26 seconds
Started Jan 17 03:54:26 PM PST 24
Finished Jan 17 03:57:55 PM PST 24
Peak memory 224352 kb
Host smart-ca26f67e-460f-4a63-ae63-6472a913842d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886206959 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.3886206959
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.4068453778
Short name T311
Test name
Test status
Simulation time 2356115456 ps
CPU time 17.66 seconds
Started Jan 17 03:54:33 PM PST 24
Finished Jan 17 03:54:52 PM PST 24
Peak memory 210140 kb
Host smart-8a5999ec-f7a4-4c66-b3b4-d5eec1a5b3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068453778 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.4068453778
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.801005496
Short name T420
Test name
Test status
Simulation time 1240991448 ps
CPU time 12.61 seconds
Started Jan 17 03:54:32 PM PST 24
Finished Jan 17 03:54:47 PM PST 24
Peak memory 210876 kb
Host smart-52d05a8b-5d1f-44c7-b40b-2633173a8783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=801005496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.801005496
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2045021303
Short name T54
Test name
Test status
Simulation time 6095389576 ps
CPU time 34.87 seconds
Started Jan 17 03:54:24 PM PST 24
Finished Jan 17 03:55:01 PM PST 24
Peak memory 212612 kb
Host smart-a5b0b829-b2f9-497b-845c-35c00a3e1cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045021303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2045021303
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.2993549923
Short name T322
Test name
Test status
Simulation time 25904861962 ps
CPU time 31.37 seconds
Started Jan 17 03:54:29 PM PST 24
Finished Jan 17 03:55:06 PM PST 24
Peak memory 213840 kb
Host smart-83f1a38c-7c0f-4f01-a136-b280b8c689f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993549923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.2993549923
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2935612528
Short name T245
Test name
Test status
Simulation time 36691711936 ps
CPU time 2303.94 seconds
Started Jan 17 03:54:28 PM PST 24
Finished Jan 17 04:32:58 PM PST 24
Peak memory 229628 kb
Host smart-4d2ad4af-a0f1-480b-b7ee-874dbf47b318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935612528 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2935612528
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.93849390
Short name T170
Test name
Test status
Simulation time 1740052484 ps
CPU time 9.77 seconds
Started Jan 17 03:54:26 PM PST 24
Finished Jan 17 03:54:37 PM PST 24
Peak memory 210992 kb
Host smart-a289f145-161f-40d5-9787-399ea1e9816f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93849390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.93849390
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1458624224
Short name T424
Test name
Test status
Simulation time 10711359245 ps
CPU time 219.54 seconds
Started Jan 17 03:54:25 PM PST 24
Finished Jan 17 03:58:07 PM PST 24
Peak memory 228120 kb
Host smart-3013f758-17e2-486a-86a1-b698dab044f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458624224 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.1458624224
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1478152321
Short name T391
Test name
Test status
Simulation time 1924330648 ps
CPU time 20.44 seconds
Started Jan 17 03:54:30 PM PST 24
Finished Jan 17 03:54:55 PM PST 24
Peak memory 211604 kb
Host smart-7abe15e8-4a11-4eb7-8f92-ba23c28cd572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478152321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1478152321
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1774982547
Short name T167
Test name
Test status
Simulation time 180849478 ps
CPU time 5.41 seconds
Started Jan 17 03:54:24 PM PST 24
Finished Jan 17 03:54:32 PM PST 24
Peak memory 210876 kb
Host smart-b1afa312-305a-4fbc-80bf-e69f48e63dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774982547 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1774982547
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.2771881027
Short name T410
Test name
Test status
Simulation time 3385320391 ps
CPU time 39.44 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:55:14 PM PST 24
Peak memory 212280 kb
Host smart-39a17cf4-c312-4f89-b118-0c7de415b2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771881027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.2771881027
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.868517349
Short name T285
Test name
Test status
Simulation time 13866088358 ps
CPU time 32.1 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:55:06 PM PST 24
Peak memory 216304 kb
Host smart-67c98012-c2dc-442d-aade-f38c21034d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868517349 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.rom_ctrl_stress_all.868517349
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.2507847244
Short name T329
Test name
Test status
Simulation time 1627096455 ps
CPU time 13.92 seconds
Started Jan 17 03:53:43 PM PST 24
Finished Jan 17 03:53:59 PM PST 24
Peak memory 210872 kb
Host smart-fbfc4655-61ed-4ad8-bc65-29cf5e76e9b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507847244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2507847244
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.282127970
Short name T365
Test name
Test status
Simulation time 10076711894 ps
CPU time 160.3 seconds
Started Jan 17 03:53:41 PM PST 24
Finished Jan 17 03:56:22 PM PST 24
Peak memory 224168 kb
Host smart-1ab20e86-b3b8-4299-82f4-834564736979
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282127970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_co
rrupt_sig_fatal_chk.282127970
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.3607683709
Short name T256
Test name
Test status
Simulation time 450353922 ps
CPU time 9.82 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:53:51 PM PST 24
Peak memory 211060 kb
Host smart-1585a890-2b75-4b7f-a32a-0ef1e9c24c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607683709 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.3607683709
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2579602160
Short name T399
Test name
Test status
Simulation time 368268940 ps
CPU time 5.56 seconds
Started Jan 17 03:53:40 PM PST 24
Finished Jan 17 03:53:47 PM PST 24
Peak memory 210916 kb
Host smart-01858372-5035-458e-8868-cc0a413340ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579602160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2579602160
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.4021917834
Short name T49
Test name
Test status
Simulation time 476943616 ps
CPU time 113.02 seconds
Started Jan 17 03:53:42 PM PST 24
Finished Jan 17 03:55:36 PM PST 24
Peak memory 236380 kb
Host smart-b4967d90-b8b0-40e3-b68c-360a31b6e0c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021917834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.4021917834
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3677259588
Short name T200
Test name
Test status
Simulation time 4789207602 ps
CPU time 30.09 seconds
Started Jan 17 03:53:41 PM PST 24
Finished Jan 17 03:54:12 PM PST 24
Peak memory 213240 kb
Host smart-2f3073e5-1eb0-4fb5-8fef-35d93e8eb41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677259588 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3677259588
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1958280950
Short name T240
Test name
Test status
Simulation time 1376550593 ps
CPU time 14.81 seconds
Started Jan 17 03:53:39 PM PST 24
Finished Jan 17 03:53:56 PM PST 24
Peak memory 211288 kb
Host smart-34de37dc-ec5a-42cc-ad53-0c8443981e92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958280950 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1958280950
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2148241802
Short name T268
Test name
Test status
Simulation time 63041449156 ps
CPU time 1383.52 seconds
Started Jan 17 03:53:36 PM PST 24
Finished Jan 17 04:16:45 PM PST 24
Peak memory 228796 kb
Host smart-d185a87c-2091-4db7-aa68-f2f603db2fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148241802 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.2148241802
Directory /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.1730402565
Short name T216
Test name
Test status
Simulation time 918889795 ps
CPU time 4.43 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:54:39 PM PST 24
Peak memory 210908 kb
Host smart-7c1e0a66-7d6d-4bde-8d51-8ccf2eb504d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730402565 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.1730402565
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3164533441
Short name T351
Test name
Test status
Simulation time 1819067741 ps
CPU time 117.23 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:56:31 PM PST 24
Peak memory 228124 kb
Host smart-cc263e24-a4cb-4e01-9acf-01427dd74e32
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164533441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3164533441
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.427915359
Short name T19
Test name
Test status
Simulation time 168815194 ps
CPU time 10.21 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:54:44 PM PST 24
Peak memory 210928 kb
Host smart-598492cf-12c1-477f-b365-4d4225049e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427915359 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.427915359
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.867977135
Short name T259
Test name
Test status
Simulation time 2700255629 ps
CPU time 14.48 seconds
Started Jan 17 03:54:30 PM PST 24
Finished Jan 17 03:54:49 PM PST 24
Peak memory 210944 kb
Host smart-91fb8ef1-8f56-4b5c-900b-e3f7745156ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867977135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.867977135
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1189166509
Short name T273
Test name
Test status
Simulation time 3365791000 ps
CPU time 29.54 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:55:04 PM PST 24
Peak memory 212264 kb
Host smart-3cebe95d-545d-4996-a2dc-ea41692cfab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189166509 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1189166509
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.3685287071
Short name T193
Test name
Test status
Simulation time 4202238592 ps
CPU time 36.61 seconds
Started Jan 17 03:54:32 PM PST 24
Finished Jan 17 03:55:11 PM PST 24
Peak memory 212068 kb
Host smart-f65a6090-1a82-4e1e-a28b-1925357b02f6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685287071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.3685287071
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1352238255
Short name T363
Test name
Test status
Simulation time 657916644 ps
CPU time 8.45 seconds
Started Jan 17 03:54:37 PM PST 24
Finished Jan 17 03:54:50 PM PST 24
Peak memory 210888 kb
Host smart-c4d4e86c-6c29-4121-a09b-e79a720f4088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352238255 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1352238255
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.324599410
Short name T234
Test name
Test status
Simulation time 6511009302 ps
CPU time 154.67 seconds
Started Jan 17 03:54:32 PM PST 24
Finished Jan 17 03:57:09 PM PST 24
Peak memory 212200 kb
Host smart-f5457235-efb9-4044-ae8d-22dc74f0bf8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324599410 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.324599410
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1828858292
Short name T328
Test name
Test status
Simulation time 3791902239 ps
CPU time 16.16 seconds
Started Jan 17 03:54:35 PM PST 24
Finished Jan 17 03:54:51 PM PST 24
Peak memory 211096 kb
Host smart-427be7d6-8c94-4918-9efe-1fe3af84a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828858292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1828858292
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.1182530
Short name T416
Test name
Test status
Simulation time 1012016736 ps
CPU time 11.48 seconds
Started Jan 17 03:54:29 PM PST 24
Finished Jan 17 03:54:46 PM PST 24
Peak memory 210828 kb
Host smart-1bf23919-9145-47ff-80dc-b91f3957226a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1182530 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.1182530
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.488701173
Short name T342
Test name
Test status
Simulation time 363693747 ps
CPU time 10.21 seconds
Started Jan 17 03:54:29 PM PST 24
Finished Jan 17 03:54:44 PM PST 24
Peak memory 212516 kb
Host smart-b81f521e-a0b1-4600-b91a-21c0750ca66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488701173 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.488701173
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.1291321747
Short name T333
Test name
Test status
Simulation time 2455016480 ps
CPU time 30.11 seconds
Started Jan 17 03:54:31 PM PST 24
Finished Jan 17 03:55:04 PM PST 24
Peak memory 213660 kb
Host smart-060bc99c-fbe8-4edd-b6a4-e6e9fb1ec778
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291321747 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.1291321747
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.183075865
Short name T41
Test name
Test status
Simulation time 5118181727 ps
CPU time 12.77 seconds
Started Jan 17 03:54:36 PM PST 24
Finished Jan 17 03:54:51 PM PST 24
Peak memory 210956 kb
Host smart-992ce4d7-a707-47f2-a6ae-dbea57329a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183075865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.183075865
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.355531069
Short name T217
Test name
Test status
Simulation time 38311311696 ps
CPU time 166.56 seconds
Started Jan 17 03:54:35 PM PST 24
Finished Jan 17 03:57:22 PM PST 24
Peak memory 213512 kb
Host smart-24208358-3926-471d-9739-1587b4526802
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355531069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c
orrupt_sig_fatal_chk.355531069
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.325377057
Short name T26
Test name
Test status
Simulation time 7526580933 ps
CPU time 21.19 seconds
Started Jan 17 03:54:33 PM PST 24
Finished Jan 17 03:54:56 PM PST 24
Peak memory 211576 kb
Host smart-2cd12e10-f40a-44b4-9471-f9598852c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325377057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.325377057
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.3103537911
Short name T100
Test name
Test status
Simulation time 5515582138 ps
CPU time 13.17 seconds
Started Jan 17 03:54:37 PM PST 24
Finished Jan 17 03:54:54 PM PST 24
Peak memory 210916 kb
Host smart-fb1ce7df-1f1b-4743-a4cc-71623ebee3d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103537911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.3103537911
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.683612634
Short name T306
Test name
Test status
Simulation time 6679841182 ps
CPU time 16.99 seconds
Started Jan 17 03:54:35 PM PST 24
Finished Jan 17 03:54:52 PM PST 24
Peak memory 213244 kb
Host smart-6c5e4554-7e8b-4870-90ab-0e2a49224224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683612634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.683612634
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.2155290946
Short name T281
Test name
Test status
Simulation time 14483314584 ps
CPU time 32.04 seconds
Started Jan 17 03:54:35 PM PST 24
Finished Jan 17 03:55:08 PM PST 24
Peak memory 213572 kb
Host smart-ebff1ec7-5b88-4cae-8be1-05e52a4fb830
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155290946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.2155290946
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all_with_rand_reset.4241952181
Short name T12
Test name
Test status
Simulation time 55209354911 ps
CPU time 3718.18 seconds
Started Jan 17 03:54:35 PM PST 24
Finished Jan 17 04:56:34 PM PST 24
Peak memory 235564 kb
Host smart-b31798f6-6b50-49ae-9d8f-39065db036cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241952181 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_stress_all_with_rand_reset.4241952181
Directory /workspace/22.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.3978131930
Short name T44
Test name
Test status
Simulation time 16810594136 ps
CPU time 14.73 seconds
Started Jan 17 03:54:40 PM PST 24
Finished Jan 17 03:54:57 PM PST 24
Peak memory 210968 kb
Host smart-f79babb4-ba8e-4233-b0e8-607b94c2ace3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978131930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3978131930
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.4264203841
Short name T55
Test name
Test status
Simulation time 105392719368 ps
CPU time 292.49 seconds
Started Jan 17 03:54:41 PM PST 24
Finished Jan 17 03:59:35 PM PST 24
Peak memory 228164 kb
Host smart-30a38971-771f-4629-9301-647bf811102b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264203841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.4264203841
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.2772146895
Short name T24
Test name
Test status
Simulation time 9654197202 ps
CPU time 20.63 seconds
Started Jan 17 03:54:38 PM PST 24
Finished Jan 17 03:55:02 PM PST 24
Peak memory 210888 kb
Host smart-b069be3d-fa1b-4a4e-9d1b-ca14e94d31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772146895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.2772146895
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.293129596
Short name T325
Test name
Test status
Simulation time 2488855945 ps
CPU time 9.61 seconds
Started Jan 17 03:54:40 PM PST 24
Finished Jan 17 03:54:52 PM PST 24
Peak memory 211020 kb
Host smart-9e976b0b-0ff4-4aa1-a149-a11dc9b0f291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293129596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.293129596
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.1224242653
Short name T308
Test name
Test status
Simulation time 16014101755 ps
CPU time 31.74 seconds
Started Jan 17 03:54:36 PM PST 24
Finished Jan 17 03:55:11 PM PST 24
Peak memory 213352 kb
Host smart-3c6deab7-c6c6-4a2c-ba6c-2b8d4ad039d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224242653 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1224242653
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.3867648795
Short name T386
Test name
Test status
Simulation time 2897588165 ps
CPU time 25.78 seconds
Started Jan 17 03:54:41 PM PST 24
Finished Jan 17 03:55:08 PM PST 24
Peak memory 215460 kb
Host smart-fad28161-09ef-4cc2-9ede-61b96ad6a2db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867648795 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.3867648795
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.2998573336
Short name T372
Test name
Test status
Simulation time 95844036083 ps
CPU time 1914.05 seconds
Started Jan 17 03:54:39 PM PST 24
Finished Jan 17 04:26:36 PM PST 24
Peak memory 243776 kb
Host smart-f9f3223b-727d-4497-9e23-5c5b69d98017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998573336 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.2998573336
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.655031040
Short name T367
Test name
Test status
Simulation time 899420873 ps
CPU time 9.71 seconds
Started Jan 17 03:54:57 PM PST 24
Finished Jan 17 03:55:09 PM PST 24
Peak memory 210896 kb
Host smart-a6b6743f-7552-4db6-a438-7e3b937582a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655031040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.655031040
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.2584371544
Short name T353
Test name
Test status
Simulation time 39434910517 ps
CPU time 238.5 seconds
Started Jan 17 03:54:47 PM PST 24
Finished Jan 17 03:58:46 PM PST 24
Peak memory 228216 kb
Host smart-88508485-f3d2-4db1-baa2-65ef38584944
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584371544 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_
corrupt_sig_fatal_chk.2584371544
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.113058570
Short name T378
Test name
Test status
Simulation time 2452783136 ps
CPU time 25.57 seconds
Started Jan 17 03:54:46 PM PST 24
Finished Jan 17 03:55:12 PM PST 24
Peak memory 211032 kb
Host smart-f4e20f57-f11a-42ec-b2c4-341b3bb07e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113058570 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.113058570
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.4101075955
Short name T160
Test name
Test status
Simulation time 2968308784 ps
CPU time 13.86 seconds
Started Jan 17 03:54:40 PM PST 24
Finished Jan 17 03:54:56 PM PST 24
Peak memory 210828 kb
Host smart-2d9936f3-33fc-4b3e-b9a5-b4dfd9ce04b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101075955 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.4101075955
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.561731937
Short name T348
Test name
Test status
Simulation time 758586308 ps
CPU time 10.53 seconds
Started Jan 17 03:54:41 PM PST 24
Finished Jan 17 03:54:53 PM PST 24
Peak memory 212568 kb
Host smart-28b1ccf2-e19a-4494-a534-1d203bbc00f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561731937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.561731937
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.508894872
Short name T15
Test name
Test status
Simulation time 110797861 ps
CPU time 6.22 seconds
Started Jan 17 03:54:42 PM PST 24
Finished Jan 17 03:54:49 PM PST 24
Peak memory 210812 kb
Host smart-d94e3545-3586-4bf3-9e05-8df80012f05e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508894872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.508894872
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.3032022265
Short name T223
Test name
Test status
Simulation time 346910095 ps
CPU time 4.44 seconds
Started Jan 17 03:54:56 PM PST 24
Finished Jan 17 03:55:03 PM PST 24
Peak memory 210916 kb
Host smart-1f691dc5-0a34-440a-836a-fe1b0e818ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032022265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.3032022265
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.2871909400
Short name T251
Test name
Test status
Simulation time 4419837183 ps
CPU time 148.35 seconds
Started Jan 17 03:54:54 PM PST 24
Finished Jan 17 03:57:24 PM PST 24
Peak memory 224460 kb
Host smart-4dc30504-1457-47a4-be6d-cd828bdb831c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871909400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_
corrupt_sig_fatal_chk.2871909400
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.3450848174
Short name T274
Test name
Test status
Simulation time 923796734 ps
CPU time 9.91 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:05 PM PST 24
Peak memory 210968 kb
Host smart-8163a5bc-a711-4744-9056-e4b5a4e1d257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450848174 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.3450848174
Directory /workspace/25.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.1518897312
Short name T347
Test name
Test status
Simulation time 971942316 ps
CPU time 11.31 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:05 PM PST 24
Peak memory 210860 kb
Host smart-32e95afb-de6e-42fc-ac6b-328af5236825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1518897312 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.1518897312
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.685300008
Short name T278
Test name
Test status
Simulation time 3758958905 ps
CPU time 36.14 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:30 PM PST 24
Peak memory 212432 kb
Host smart-81be3553-670b-49be-a7e4-7ef6914a0ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685300008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.685300008
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.3625726007
Short name T226
Test name
Test status
Simulation time 1474877049 ps
CPU time 17.3 seconds
Started Jan 17 03:54:58 PM PST 24
Finished Jan 17 03:55:17 PM PST 24
Peak memory 213080 kb
Host smart-c475bdf1-a046-42b5-9d87-607460c9d08f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625726007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.3625726007
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1678659495
Short name T177
Test name
Test status
Simulation time 249462562010 ps
CPU time 8719.81 seconds
Started Jan 17 03:54:56 PM PST 24
Finished Jan 17 06:20:20 PM PST 24
Peak memory 237356 kb
Host smart-87614d83-37ca-46aa-a8e3-56918890b96a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678659495 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1678659495
Directory /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.878764012
Short name T178
Test name
Test status
Simulation time 794642428 ps
CPU time 9.47 seconds
Started Jan 17 03:54:52 PM PST 24
Finished Jan 17 03:55:02 PM PST 24
Peak memory 210912 kb
Host smart-fffb4b85-1d9c-4601-908f-120f6e4bb605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878764012 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.878764012
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.4139165374
Short name T194
Test name
Test status
Simulation time 71700120243 ps
CPU time 246.88 seconds
Started Jan 17 03:54:55 PM PST 24
Finished Jan 17 03:59:05 PM PST 24
Peak memory 236396 kb
Host smart-b61377d6-2c8b-40f4-97e8-9a50727a624b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139165374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.4139165374
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4220802257
Short name T276
Test name
Test status
Simulation time 340494392 ps
CPU time 9.83 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:03 PM PST 24
Peak memory 211072 kb
Host smart-5ac03ad8-4985-4b93-81e9-255ddd536ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220802257 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4220802257
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1994127108
Short name T352
Test name
Test status
Simulation time 266677413 ps
CPU time 7.17 seconds
Started Jan 17 03:54:55 PM PST 24
Finished Jan 17 03:55:05 PM PST 24
Peak memory 210872 kb
Host smart-f41eeac9-8d0d-42f8-8d22-9d3686e9aeed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994127108 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1994127108
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.1237200445
Short name T380
Test name
Test status
Simulation time 4580582970 ps
CPU time 24.1 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:19 PM PST 24
Peak memory 213552 kb
Host smart-a0c64a5c-a838-4f45-b1ac-8421a6a9eac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237200445 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.1237200445
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.1352467336
Short name T407
Test name
Test status
Simulation time 2505657284 ps
CPU time 32.3 seconds
Started Jan 17 03:54:58 PM PST 24
Finished Jan 17 03:55:32 PM PST 24
Peak memory 215632 kb
Host smart-1384493b-3b09-4af7-8e3e-0a097befbc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352467336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.1352467336
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.4195846270
Short name T356
Test name
Test status
Simulation time 2091425277 ps
CPU time 15.56 seconds
Started Jan 17 03:54:54 PM PST 24
Finished Jan 17 03:55:12 PM PST 24
Peak memory 210932 kb
Host smart-79b64936-2307-4285-9e2d-66266a6432fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195846270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.4195846270
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.2995857134
Short name T7
Test name
Test status
Simulation time 149156167352 ps
CPU time 364.26 seconds
Started Jan 17 03:54:52 PM PST 24
Finished Jan 17 04:00:57 PM PST 24
Peak memory 227420 kb
Host smart-e0aaa4ad-b255-4fee-a298-1bfb7315f6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995857134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_
corrupt_sig_fatal_chk.2995857134
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.2013360438
Short name T215
Test name
Test status
Simulation time 693675781 ps
CPU time 9.94 seconds
Started Jan 17 03:54:56 PM PST 24
Finished Jan 17 03:55:09 PM PST 24
Peak memory 210992 kb
Host smart-21db04ec-2b3d-4929-a3c3-dbff0fcf0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013360438 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.2013360438
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1158702960
Short name T241
Test name
Test status
Simulation time 5273899948 ps
CPU time 14.01 seconds
Started Jan 17 03:54:54 PM PST 24
Finished Jan 17 03:55:10 PM PST 24
Peak memory 210920 kb
Host smart-645f6912-887f-46e3-885d-7c9064efa62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158702960 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1158702960
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.3838922659
Short name T312
Test name
Test status
Simulation time 7424019224 ps
CPU time 35.45 seconds
Started Jan 17 03:54:52 PM PST 24
Finished Jan 17 03:55:28 PM PST 24
Peak memory 213700 kb
Host smart-73df0888-5723-4510-90e9-503fcbf46032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838922659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.3838922659
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.563106026
Short name T287
Test name
Test status
Simulation time 380402012 ps
CPU time 25.07 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:18 PM PST 24
Peak memory 215432 kb
Host smart-d212ed27-4940-402e-add2-b69d2a298767
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563106026 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.rom_ctrl_stress_all.563106026
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1946410372
Short name T225
Test name
Test status
Simulation time 17199541794 ps
CPU time 77.22 seconds
Started Jan 17 03:54:54 PM PST 24
Finished Jan 17 03:56:14 PM PST 24
Peak memory 220888 kb
Host smart-1c9edbbf-908d-4a74-930b-43abb6abeb70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946410372 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1946410372
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.3450464189
Short name T288
Test name
Test status
Simulation time 6248452742 ps
CPU time 14.46 seconds
Started Jan 17 03:54:59 PM PST 24
Finished Jan 17 03:55:20 PM PST 24
Peak memory 211172 kb
Host smart-0b84f82c-6de4-4fbf-b65b-5b07db6d079b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450464189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3450464189
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.920079625
Short name T57
Test name
Test status
Simulation time 9461129424 ps
CPU time 147.34 seconds
Started Jan 17 03:54:58 PM PST 24
Finished Jan 17 03:57:27 PM PST 24
Peak memory 233288 kb
Host smart-55d4874b-a865-432d-9a4b-166588e9eb11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920079625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_c
orrupt_sig_fatal_chk.920079625
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.2200872558
Short name T344
Test name
Test status
Simulation time 3100579537 ps
CPU time 14.84 seconds
Started Jan 17 03:54:52 PM PST 24
Finished Jan 17 03:55:08 PM PST 24
Peak memory 211180 kb
Host smart-1dda3f78-eed5-433d-939d-0a61e474279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200872558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.2200872558
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.1197676189
Short name T8
Test name
Test status
Simulation time 3772472893 ps
CPU time 15.66 seconds
Started Jan 17 03:54:53 PM PST 24
Finished Jan 17 03:55:10 PM PST 24
Peak memory 210936 kb
Host smart-1eee16cf-8d9d-481d-a62f-95ed077539b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1197676189 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.1197676189
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1881709658
Short name T209
Test name
Test status
Simulation time 2553182045 ps
CPU time 28.42 seconds
Started Jan 17 03:54:52 PM PST 24
Finished Jan 17 03:55:21 PM PST 24
Peak memory 212440 kb
Host smart-3bfc728d-321c-45b6-ad7f-18cb7834a320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881709658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1881709658
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.4205671850
Short name T265
Test name
Test status
Simulation time 5590542227 ps
CPU time 32.72 seconds
Started Jan 17 03:54:55 PM PST 24
Finished Jan 17 03:55:31 PM PST 24
Peak memory 212776 kb
Host smart-9f1c6214-1619-413f-af31-a9d882b068da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205671850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.4205671850
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.1946163742
Short name T185
Test name
Test status
Simulation time 575638791 ps
CPU time 8.66 seconds
Started Jan 17 03:54:59 PM PST 24
Finished Jan 17 03:55:15 PM PST 24
Peak memory 210912 kb
Host smart-153b1b8c-6b8b-4fde-855f-7ada4ea1d37f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946163742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.1946163742
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.3984531845
Short name T404
Test name
Test status
Simulation time 21099436560 ps
CPU time 226.14 seconds
Started Jan 17 03:55:01 PM PST 24
Finished Jan 17 03:58:53 PM PST 24
Peak memory 229232 kb
Host smart-ea9fa3c0-c139-4f1c-b23e-ca3b866f529a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984531845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.3984531845
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1078130933
Short name T418
Test name
Test status
Simulation time 694358971 ps
CPU time 9.64 seconds
Started Jan 17 03:54:59 PM PST 24
Finished Jan 17 03:55:09 PM PST 24
Peak memory 210924 kb
Host smart-10665d74-347a-4438-a984-b44b79487c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078130933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1078130933
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.3660094823
Short name T159
Test name
Test status
Simulation time 1290478867 ps
CPU time 13.13 seconds
Started Jan 17 03:55:00 PM PST 24
Finished Jan 17 03:55:19 PM PST 24
Peak memory 210868 kb
Host smart-b706af5e-9cc0-4ef6-acb1-1eab3c8bcd5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3660094823 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.3660094823
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.2658398650
Short name T16
Test name
Test status
Simulation time 16846039283 ps
CPU time 36.51 seconds
Started Jan 17 03:54:57 PM PST 24
Finished Jan 17 03:55:36 PM PST 24
Peak memory 213312 kb
Host smart-28a61054-9342-4f67-831b-49b97856f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658398650 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.2658398650
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.13313554
Short name T390
Test name
Test status
Simulation time 31972886941 ps
CPU time 53.66 seconds
Started Jan 17 03:54:59 PM PST 24
Finished Jan 17 03:56:00 PM PST 24
Peak memory 216696 kb
Host smart-3b69cbc4-e169-4da4-be59-e57acf33b3cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13313554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +U
VM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 29.rom_ctrl_stress_all.13313554
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.2997619038
Short name T173
Test name
Test status
Simulation time 435747888987 ps
CPU time 4247.3 seconds
Started Jan 17 03:54:58 PM PST 24
Finished Jan 17 05:05:47 PM PST 24
Peak memory 252640 kb
Host smart-930d72a7-44ba-448b-8d77-854e5549cda9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997619038 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.2997619038
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2886794046
Short name T164
Test name
Test status
Simulation time 1427058523 ps
CPU time 13.18 seconds
Started Jan 17 03:53:52 PM PST 24
Finished Jan 17 03:54:06 PM PST 24
Peak memory 210912 kb
Host smart-4c292657-1e56-4c26-b8bc-65c13e5a435f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886794046 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2886794046
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.2346887271
Short name T341
Test name
Test status
Simulation time 10527716977 ps
CPU time 156.63 seconds
Started Jan 17 03:53:41 PM PST 24
Finished Jan 17 03:56:18 PM PST 24
Peak memory 212152 kb
Host smart-7bb70eb8-f786-4697-b05e-1a8081418b47
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346887271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.2346887271
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.245939733
Short name T155
Test name
Test status
Simulation time 665578728 ps
CPU time 9.98 seconds
Started Jan 17 03:53:46 PM PST 24
Finished Jan 17 03:53:58 PM PST 24
Peak memory 211044 kb
Host smart-d6edd29d-12d7-44b4-9864-649d3c6a76e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245939733 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.245939733
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2039136500
Short name T157
Test name
Test status
Simulation time 530927028 ps
CPU time 6.48 seconds
Started Jan 17 03:53:44 PM PST 24
Finished Jan 17 03:53:53 PM PST 24
Peak memory 210884 kb
Host smart-091bfdda-3920-4c01-b828-68414d550627
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039136500 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2039136500
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.3234967914
Short name T40
Test name
Test status
Simulation time 1131173200 ps
CPU time 61.44 seconds
Started Jan 17 03:53:52 PM PST 24
Finished Jan 17 03:54:54 PM PST 24
Peak memory 236412 kb
Host smart-58da9107-ac4c-4cd0-bcc1-083b683d253c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234967914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3234967914
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.2327343529
Short name T263
Test name
Test status
Simulation time 2302852275 ps
CPU time 24.14 seconds
Started Jan 17 03:53:43 PM PST 24
Finished Jan 17 03:54:10 PM PST 24
Peak memory 212308 kb
Host smart-d974d9f7-1f54-42d7-bd3d-c639d37e0bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327343529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.2327343529
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.936386580
Short name T197
Test name
Test status
Simulation time 99066692727 ps
CPU time 74.76 seconds
Started Jan 17 03:53:43 PM PST 24
Finished Jan 17 03:55:00 PM PST 24
Peak memory 214456 kb
Host smart-c5631204-917a-4d0d-a7b4-b5142461ce6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936386580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.936386580
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.2481317003
Short name T324
Test name
Test status
Simulation time 3052048429 ps
CPU time 13.64 seconds
Started Jan 17 03:55:07 PM PST 24
Finished Jan 17 03:55:21 PM PST 24
Peak memory 211000 kb
Host smart-a8822df3-4c13-46e0-8b30-bfa857909321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481317003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.2481317003
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.2453595556
Short name T383
Test name
Test status
Simulation time 146632312302 ps
CPU time 410.09 seconds
Started Jan 17 03:55:05 PM PST 24
Finished Jan 17 04:01:57 PM PST 24
Peak memory 236588 kb
Host smart-82585fe5-9a2f-4451-899c-ea639418bd93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453595556 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.2453595556
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.463674932
Short name T366
Test name
Test status
Simulation time 1967579118 ps
CPU time 22.16 seconds
Started Jan 17 03:55:06 PM PST 24
Finished Jan 17 03:55:29 PM PST 24
Peak memory 211032 kb
Host smart-2389a5dd-7809-46eb-8fec-895b5c24b5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463674932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.463674932
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2959388190
Short name T323
Test name
Test status
Simulation time 8013242441 ps
CPU time 16.28 seconds
Started Jan 17 03:54:58 PM PST 24
Finished Jan 17 03:55:15 PM PST 24
Peak memory 211172 kb
Host smart-aebcf6aa-1e62-436c-b434-30ddd2ec0255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959388190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2959388190
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.2774082902
Short name T228
Test name
Test status
Simulation time 5293849227 ps
CPU time 25.39 seconds
Started Jan 17 03:54:59 PM PST 24
Finished Jan 17 03:55:31 PM PST 24
Peak memory 212996 kb
Host smart-e6599a7d-f7bb-49d7-a837-76fab0075428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774082902 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2774082902
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.2204678978
Short name T261
Test name
Test status
Simulation time 14161942210 ps
CPU time 69.04 seconds
Started Jan 17 03:55:00 PM PST 24
Finished Jan 17 03:56:16 PM PST 24
Peak memory 219064 kb
Host smart-e5b09415-5cd2-45af-84b8-bf25c646fb0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204678978 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.2204678978
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1360275840
Short name T52
Test name
Test status
Simulation time 38678068656 ps
CPU time 1924.69 seconds
Started Jan 17 03:55:12 PM PST 24
Finished Jan 17 04:27:18 PM PST 24
Peak memory 235568 kb
Host smart-d39baad9-7507-4abd-b6db-e46ad1c923ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360275840 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1360275840
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.757899027
Short name T370
Test name
Test status
Simulation time 1381427400 ps
CPU time 6.84 seconds
Started Jan 17 03:55:11 PM PST 24
Finished Jan 17 03:55:19 PM PST 24
Peak memory 211004 kb
Host smart-51b9a9c5-de39-404e-be07-b197d7d58bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757899027 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.757899027
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.3246938513
Short name T397
Test name
Test status
Simulation time 43789016244 ps
CPU time 466.09 seconds
Started Jan 17 03:55:06 PM PST 24
Finished Jan 17 04:02:53 PM PST 24
Peak memory 213476 kb
Host smart-7388075a-46f5-452e-9d6f-c4594ef2dda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246938513 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.3246938513
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1041218424
Short name T394
Test name
Test status
Simulation time 340858337 ps
CPU time 9.86 seconds
Started Jan 17 03:55:07 PM PST 24
Finished Jan 17 03:55:18 PM PST 24
Peak memory 211040 kb
Host smart-c3675349-b6a2-4be6-9a51-480dd3f5912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041218424 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1041218424
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.3231332322
Short name T3
Test name
Test status
Simulation time 1467492472 ps
CPU time 10.3 seconds
Started Jan 17 03:55:05 PM PST 24
Finished Jan 17 03:55:17 PM PST 24
Peak memory 210788 kb
Host smart-69fe0be5-3f9e-415a-9ba7-0f27ddb9bd09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3231332322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.3231332322
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.835798346
Short name T304
Test name
Test status
Simulation time 5391272207 ps
CPU time 27.45 seconds
Started Jan 17 03:55:07 PM PST 24
Finished Jan 17 03:55:36 PM PST 24
Peak memory 212928 kb
Host smart-10863e52-4101-4848-af10-6c410aeac4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835798346 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.835798346
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.1169549492
Short name T182
Test name
Test status
Simulation time 1334139359 ps
CPU time 21.13 seconds
Started Jan 17 03:55:10 PM PST 24
Finished Jan 17 03:55:33 PM PST 24
Peak memory 212680 kb
Host smart-ce89d7b7-58d3-4c32-8b29-61fddab63495
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169549492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.1169549492
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2713259927
Short name T369
Test name
Test status
Simulation time 16761790846 ps
CPU time 2716.82 seconds
Started Jan 17 03:55:05 PM PST 24
Finished Jan 17 04:40:24 PM PST 24
Peak memory 228152 kb
Host smart-01f74ce5-3937-4f35-b70f-10291c5ca7f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713259927 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2713259927
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2998530488
Short name T219
Test name
Test status
Simulation time 4684721137 ps
CPU time 6.89 seconds
Started Jan 17 03:55:13 PM PST 24
Finished Jan 17 03:55:21 PM PST 24
Peak memory 210560 kb
Host smart-5ce181eb-d2e6-44c2-83e1-a81578fcd188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998530488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2998530488
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.438599533
Short name T231
Test name
Test status
Simulation time 23177799954 ps
CPU time 217.21 seconds
Started Jan 17 03:55:17 PM PST 24
Finished Jan 17 03:58:55 PM PST 24
Peak memory 228188 kb
Host smart-00cac734-c62b-45db-ae28-3659e475332b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438599533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c
orrupt_sig_fatal_chk.438599533
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.520612614
Short name T250
Test name
Test status
Simulation time 341446741 ps
CPU time 9.71 seconds
Started Jan 17 03:55:17 PM PST 24
Finished Jan 17 03:55:27 PM PST 24
Peak memory 211316 kb
Host smart-9525d840-0c34-4cb1-b669-eeff22193791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520612614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.520612614
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3302308750
Short name T1
Test name
Test status
Simulation time 3423938755 ps
CPU time 10.67 seconds
Started Jan 17 03:55:13 PM PST 24
Finished Jan 17 03:55:25 PM PST 24
Peak memory 210636 kb
Host smart-ac5e3bc9-ce2d-4c2e-9e97-e972ffaddc27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302308750 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3302308750
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.2266500364
Short name T298
Test name
Test status
Simulation time 13925814943 ps
CPU time 32.79 seconds
Started Jan 17 03:55:05 PM PST 24
Finished Jan 17 03:55:40 PM PST 24
Peak memory 213304 kb
Host smart-2cc015b6-9086-4682-91a2-c6e4858b6e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266500364 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.2266500364
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3977670444
Short name T171
Test name
Test status
Simulation time 545066029 ps
CPU time 33.4 seconds
Started Jan 17 03:55:08 PM PST 24
Finished Jan 17 03:55:42 PM PST 24
Peak memory 216508 kb
Host smart-f45b4fe1-da9d-48dc-b51e-293d74dd80f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977670444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3977670444
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.2896939840
Short name T233
Test name
Test status
Simulation time 1296531422 ps
CPU time 12.43 seconds
Started Jan 17 03:55:23 PM PST 24
Finished Jan 17 03:55:38 PM PST 24
Peak memory 210812 kb
Host smart-66f04b39-cbde-4271-9184-e5dd01feb5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896939840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2896939840
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.3334751793
Short name T191
Test name
Test status
Simulation time 80447603041 ps
CPU time 327.44 seconds
Started Jan 17 03:55:18 PM PST 24
Finished Jan 17 04:00:46 PM PST 24
Peak memory 234452 kb
Host smart-1f89a466-1e86-423f-97f9-42d61cbbdfcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334751793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.3334751793
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1229526397
Short name T25
Test name
Test status
Simulation time 16081519357 ps
CPU time 33.32 seconds
Started Jan 17 03:55:20 PM PST 24
Finished Jan 17 03:55:57 PM PST 24
Peak memory 211416 kb
Host smart-cd6b8f21-b375-417f-a8cc-26f4426b56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229526397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1229526397
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.1483838923
Short name T9
Test name
Test status
Simulation time 7573006168 ps
CPU time 15.64 seconds
Started Jan 17 03:55:13 PM PST 24
Finished Jan 17 03:55:29 PM PST 24
Peak memory 210940 kb
Host smart-29a2346e-7f35-4136-b3be-7fddd62d0429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1483838923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.1483838923
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.3498140923
Short name T183
Test name
Test status
Simulation time 4080082324 ps
CPU time 32.19 seconds
Started Jan 17 03:55:12 PM PST 24
Finished Jan 17 03:55:45 PM PST 24
Peak memory 212524 kb
Host smart-9e74a6ae-fff7-47d9-9671-1985299c19d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498140923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.3498140923
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.3807564635
Short name T4
Test name
Test status
Simulation time 3580437473 ps
CPU time 32.88 seconds
Started Jan 17 03:55:13 PM PST 24
Finished Jan 17 03:55:46 PM PST 24
Peak memory 215880 kb
Host smart-8000994d-df2c-4d6a-bf69-f3e62a9a10da
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807564635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.3807564635
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4048571219
Short name T165
Test name
Test status
Simulation time 5788269021 ps
CPU time 13.17 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:55:37 PM PST 24
Peak memory 211008 kb
Host smart-e77529b9-c7d1-4661-8a23-beb67a44ded8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048571219 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4048571219
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.1936173415
Short name T204
Test name
Test status
Simulation time 9221762340 ps
CPU time 93.68 seconds
Started Jan 17 03:55:23 PM PST 24
Finished Jan 17 03:56:59 PM PST 24
Peak memory 236520 kb
Host smart-5d4288f7-1477-4f24-9917-15b97e11cc8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936173415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_
corrupt_sig_fatal_chk.1936173415
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.142698817
Short name T382
Test name
Test status
Simulation time 2469897643 ps
CPU time 18.1 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:55:43 PM PST 24
Peak memory 211000 kb
Host smart-978b53a0-6ae9-4d4a-9e76-e08b24a8d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142698817 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.142698817
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.531400371
Short name T255
Test name
Test status
Simulation time 1542219028 ps
CPU time 13.86 seconds
Started Jan 17 03:55:19 PM PST 24
Finished Jan 17 03:55:35 PM PST 24
Peak memory 210876 kb
Host smart-243cbf95-c15e-44b3-b541-4de1b73db66b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531400371 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.531400371
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3638238595
Short name T319
Test name
Test status
Simulation time 7693853997 ps
CPU time 37.87 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:56:02 PM PST 24
Peak memory 213204 kb
Host smart-4ee7ff70-a941-4a0a-8cb0-ec7f78fc4003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638238595 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3638238595
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all.3364519659
Short name T428
Test name
Test status
Simulation time 4509597999 ps
CPU time 23.54 seconds
Started Jan 17 03:55:20 PM PST 24
Finished Jan 17 03:55:46 PM PST 24
Peak memory 213856 kb
Host smart-3ff7af06-9b30-42c4-b44f-bce3e870d0ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364519659 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.rom_ctrl_stress_all.3364519659
Directory /workspace/34.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.3040938690
Short name T201
Test name
Test status
Simulation time 47159458532 ps
CPU time 2022.6 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 04:29:07 PM PST 24
Peak memory 232804 kb
Host smart-35f1822c-abea-4daf-a602-b333204309e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040938690 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.3040938690
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.4243188170
Short name T212
Test name
Test status
Simulation time 85857087 ps
CPU time 4.42 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:55:29 PM PST 24
Peak memory 210944 kb
Host smart-ff2874ea-ae47-4dd8-81ee-7ba6663ed02d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243188170 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.4243188170
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.3279938325
Short name T58
Test name
Test status
Simulation time 45398405117 ps
CPU time 282.93 seconds
Started Jan 17 03:55:23 PM PST 24
Finished Jan 17 04:00:08 PM PST 24
Peak memory 233484 kb
Host smart-c3c0dfc3-e1f6-413e-8a3f-a9570449f053
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279938325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.3279938325
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1665273919
Short name T419
Test name
Test status
Simulation time 17265919385 ps
CPU time 33.33 seconds
Started Jan 17 03:55:19 PM PST 24
Finished Jan 17 03:55:55 PM PST 24
Peak memory 211368 kb
Host smart-4cff08d5-4058-4553-8b9c-143a5ff39e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665273919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1665273919
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.3425437892
Short name T355
Test name
Test status
Simulation time 7499665342 ps
CPU time 16.44 seconds
Started Jan 17 03:55:22 PM PST 24
Finished Jan 17 03:55:41 PM PST 24
Peak memory 210956 kb
Host smart-2a92f9e8-676f-410a-83e7-3804b9e66b3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425437892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.3425437892
Directory /workspace/35.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.3719740505
Short name T198
Test name
Test status
Simulation time 49173698600 ps
CPU time 34.96 seconds
Started Jan 17 03:55:17 PM PST 24
Finished Jan 17 03:55:53 PM PST 24
Peak memory 213244 kb
Host smart-a2db5b63-9b11-48ce-9c26-fc9633464f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719740505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3719740505
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.3523080585
Short name T162
Test name
Test status
Simulation time 9614422209 ps
CPU time 46.8 seconds
Started Jan 17 03:55:18 PM PST 24
Finished Jan 17 03:56:05 PM PST 24
Peak memory 213716 kb
Host smart-ddb8e45a-6445-49a5-80ad-1b8724278155
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523080585 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.3523080585
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.1359118458
Short name T359
Test name
Test status
Simulation time 45101642846 ps
CPU time 1636.16 seconds
Started Jan 17 03:55:20 PM PST 24
Finished Jan 17 04:22:38 PM PST 24
Peak memory 232612 kb
Host smart-4899e134-3caf-4f1b-8f73-e555cf08a771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359118458 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.1359118458
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.3887021384
Short name T208
Test name
Test status
Simulation time 6042457611 ps
CPU time 15.29 seconds
Started Jan 17 03:55:20 PM PST 24
Finished Jan 17 03:55:38 PM PST 24
Peak memory 210992 kb
Host smart-6092eafe-ee24-43b3-82d8-fbc9bd9b6c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887021384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.3887021384
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.3175595034
Short name T400
Test name
Test status
Simulation time 336582214000 ps
CPU time 424.54 seconds
Started Jan 17 03:55:22 PM PST 24
Finished Jan 17 04:02:29 PM PST 24
Peak memory 211144 kb
Host smart-3bcfde2a-6010-43f2-b559-00566ae2c439
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175595034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_
corrupt_sig_fatal_chk.3175595034
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2358473933
Short name T242
Test name
Test status
Simulation time 14672211474 ps
CPU time 30.35 seconds
Started Jan 17 03:55:18 PM PST 24
Finished Jan 17 03:55:49 PM PST 24
Peak memory 214076 kb
Host smart-6a0b213b-58f6-4be7-a934-9dd76155fa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358473933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2358473933
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.450992727
Short name T271
Test name
Test status
Simulation time 5124525978 ps
CPU time 13 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:55:37 PM PST 24
Peak memory 210888 kb
Host smart-c47c7930-2839-4b76-b4ee-405789c4ccb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450992727 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.450992727
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2272406361
Short name T339
Test name
Test status
Simulation time 15985751262 ps
CPU time 30.64 seconds
Started Jan 17 03:55:21 PM PST 24
Finished Jan 17 03:55:54 PM PST 24
Peak memory 213108 kb
Host smart-d3d1df79-9411-4b02-a23d-4284c5dcc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272406361 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2272406361
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.3320144310
Short name T229
Test name
Test status
Simulation time 207906986 ps
CPU time 12.48 seconds
Started Jan 17 03:55:22 PM PST 24
Finished Jan 17 03:55:38 PM PST 24
Peak memory 212728 kb
Host smart-1840f16e-d19f-4bf5-8322-7495b8be8fde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320144310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.3320144310
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all_with_rand_reset.418544612
Short name T112
Test name
Test status
Simulation time 428519772288 ps
CPU time 3252.85 seconds
Started Jan 17 03:55:18 PM PST 24
Finished Jan 17 04:49:32 PM PST 24
Peak memory 251920 kb
Host smart-e5fbef19-16e1-4d1b-968b-1ba2ec0fa09d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418544612 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_stress_all_with_rand_reset.418544612
Directory /workspace/36.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.789671744
Short name T289
Test name
Test status
Simulation time 3463208507 ps
CPU time 10.06 seconds
Started Jan 17 03:55:28 PM PST 24
Finished Jan 17 03:55:42 PM PST 24
Peak memory 211020 kb
Host smart-34609962-2952-48e3-b0d6-59556baad2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789671744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.789671744
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.4125330480
Short name T158
Test name
Test status
Simulation time 5133466928 ps
CPU time 18.04 seconds
Started Jan 17 03:55:27 PM PST 24
Finished Jan 17 03:55:50 PM PST 24
Peak memory 211396 kb
Host smart-50bb7147-0e93-4d1d-aebb-69b97d35bed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125330480 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.4125330480
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.565766320
Short name T296
Test name
Test status
Simulation time 10825689359 ps
CPU time 14.84 seconds
Started Jan 17 03:55:25 PM PST 24
Finished Jan 17 03:55:40 PM PST 24
Peak memory 210912 kb
Host smart-bc1922a6-a6de-4103-8ecf-f9b1fa1e9cea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565766320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.565766320
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.2789110235
Short name T260
Test name
Test status
Simulation time 785244826 ps
CPU time 16.1 seconds
Started Jan 17 03:55:22 PM PST 24
Finished Jan 17 03:55:41 PM PST 24
Peak memory 212864 kb
Host smart-efcab6bd-8d45-4301-bd6c-8c45cc5c87da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789110235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.2789110235
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.1265176311
Short name T421
Test name
Test status
Simulation time 15332125272 ps
CPU time 34.39 seconds
Started Jan 17 03:55:24 PM PST 24
Finished Jan 17 03:56:00 PM PST 24
Peak memory 216548 kb
Host smart-13d0cf6a-5f46-4d35-b89f-1abdf0ee13a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265176311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 37.rom_ctrl_stress_all.1265176311
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1808138915
Short name T103
Test name
Test status
Simulation time 90885081000 ps
CPU time 2640.4 seconds
Started Jan 17 03:55:24 PM PST 24
Finished Jan 17 04:39:26 PM PST 24
Peak memory 235536 kb
Host smart-fbec29c2-ebfe-4e23-9e5d-9e92f2b06bbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808138915 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1808138915
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1674396211
Short name T398
Test name
Test status
Simulation time 2662690195 ps
CPU time 11.13 seconds
Started Jan 17 03:55:34 PM PST 24
Finished Jan 17 03:55:48 PM PST 24
Peak memory 210960 kb
Host smart-523a4857-c15c-4711-a143-f41132037ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674396211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1674396211
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.3659189387
Short name T264
Test name
Test status
Simulation time 10168178299 ps
CPU time 147.08 seconds
Started Jan 17 03:55:27 PM PST 24
Finished Jan 17 03:57:59 PM PST 24
Peak memory 236860 kb
Host smart-00833313-d13b-4ac4-88c7-7e1058a3f8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659189387 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.3659189387
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.3727728916
Short name T279
Test name
Test status
Simulation time 915097045 ps
CPU time 16.1 seconds
Started Jan 17 03:55:27 PM PST 24
Finished Jan 17 03:55:48 PM PST 24
Peak memory 210976 kb
Host smart-42f535d9-36c8-4c5c-bcec-cf1d7c0d69f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727728916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.3727728916
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.1799187338
Short name T166
Test name
Test status
Simulation time 1222620798 ps
CPU time 6.75 seconds
Started Jan 17 03:55:24 PM PST 24
Finished Jan 17 03:55:32 PM PST 24
Peak memory 211112 kb
Host smart-e1b8b35e-8fc4-4865-bfd9-2dba10a815c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799187338 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.1799187338
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.399517102
Short name T272
Test name
Test status
Simulation time 7215611201 ps
CPU time 22.82 seconds
Started Jan 17 03:55:23 PM PST 24
Finished Jan 17 03:55:48 PM PST 24
Peak memory 213564 kb
Host smart-a5543ac8-2fc2-42ce-adb8-3380bcf22320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399517102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.399517102
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.3593729116
Short name T51
Test name
Test status
Simulation time 8364615846 ps
CPU time 78.63 seconds
Started Jan 17 03:55:25 PM PST 24
Finished Jan 17 03:56:50 PM PST 24
Peak memory 216116 kb
Host smart-3c1ec0cd-de6b-4cfa-be49-902e9e0fed3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593729116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 38.rom_ctrl_stress_all.3593729116
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.2184525070
Short name T6
Test name
Test status
Simulation time 134468326994 ps
CPU time 10496 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 06:50:35 PM PST 24
Peak memory 238224 kb
Host smart-bfc63232-cda4-48d5-891a-3200fab96f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184525070 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.2184525070
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.2285640047
Short name T156
Test name
Test status
Simulation time 6220250381 ps
CPU time 14.48 seconds
Started Jan 17 03:55:36 PM PST 24
Finished Jan 17 03:55:52 PM PST 24
Peak memory 210948 kb
Host smart-2493a032-2021-43ce-a813-2da8f02275f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285640047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.2285640047
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3622709112
Short name T184
Test name
Test status
Simulation time 51244910902 ps
CPU time 220.95 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 03:59:18 PM PST 24
Peak memory 233688 kb
Host smart-014754da-6d3b-42a2-bd47-027bd17bae22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622709112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.3622709112
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.1937660151
Short name T331
Test name
Test status
Simulation time 991515721 ps
CPU time 16.9 seconds
Started Jan 17 03:55:39 PM PST 24
Finished Jan 17 03:55:56 PM PST 24
Peak memory 210964 kb
Host smart-97d41826-43de-4829-9964-289a24642e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937660151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.1937660151
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.281459190
Short name T334
Test name
Test status
Simulation time 4377457861 ps
CPU time 18.2 seconds
Started Jan 17 03:55:39 PM PST 24
Finished Jan 17 03:55:58 PM PST 24
Peak memory 210924 kb
Host smart-448c8120-787a-415e-9376-0b702dc78dd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281459190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.281459190
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.4232395451
Short name T153
Test name
Test status
Simulation time 1579782264 ps
CPU time 16.27 seconds
Started Jan 17 03:55:37 PM PST 24
Finished Jan 17 03:55:54 PM PST 24
Peak memory 212512 kb
Host smart-301f5ad9-a869-468e-a101-b961c6d4a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232395451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4232395451
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.687876448
Short name T214
Test name
Test status
Simulation time 9442305509 ps
CPU time 48.1 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 03:56:26 PM PST 24
Peak memory 215904 kb
Host smart-2fdc7f7f-0c66-4b35-9559-5b7338ba6967
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687876448 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.687876448
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.1248833515
Short name T257
Test name
Test status
Simulation time 92111006802 ps
CPU time 2699.37 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 04:40:37 PM PST 24
Peak memory 235548 kb
Host smart-b069811c-ea18-470a-aac8-f0e07a02d3d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248833515 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.1248833515
Directory /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.554497165
Short name T237
Test name
Test status
Simulation time 918716734 ps
CPU time 4.41 seconds
Started Jan 17 03:53:52 PM PST 24
Finished Jan 17 03:53:57 PM PST 24
Peak memory 210844 kb
Host smart-3ec8d7ba-3fcb-4102-a5fa-373b897dd291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554497165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.554497165
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.391329658
Short name T232
Test name
Test status
Simulation time 1041812396 ps
CPU time 15.91 seconds
Started Jan 17 03:53:49 PM PST 24
Finished Jan 17 03:54:05 PM PST 24
Peak memory 211048 kb
Host smart-e993c77e-d6e1-4f6a-b591-1931cc0f0610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391329658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.391329658
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.2640464988
Short name T401
Test name
Test status
Simulation time 2738754190 ps
CPU time 13.05 seconds
Started Jan 17 03:53:52 PM PST 24
Finished Jan 17 03:54:06 PM PST 24
Peak memory 210928 kb
Host smart-a4db9207-36fe-4a09-b3b4-b165795db834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640464988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.2640464988
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.3894270997
Short name T50
Test name
Test status
Simulation time 3951244172 ps
CPU time 68.36 seconds
Started Jan 17 03:53:50 PM PST 24
Finished Jan 17 03:54:59 PM PST 24
Peak memory 236892 kb
Host smart-fefe8de4-f272-4143-a784-7ead4f4ba12f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894270997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.3894270997
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.2379231197
Short name T151
Test name
Test status
Simulation time 510059880 ps
CPU time 10.57 seconds
Started Jan 17 03:53:53 PM PST 24
Finished Jan 17 03:54:04 PM PST 24
Peak memory 212100 kb
Host smart-14a94f0f-2d43-4038-8d56-4f780f090767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379231197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.2379231197
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.528869949
Short name T290
Test name
Test status
Simulation time 5549630465 ps
CPU time 32.28 seconds
Started Jan 17 03:53:42 PM PST 24
Finished Jan 17 03:54:15 PM PST 24
Peak memory 214700 kb
Host smart-b38ad53b-41c9-475b-a5c4-adc68fdb3fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528869949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.rom_ctrl_stress_all.528869949
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.2478721069
Short name T299
Test name
Test status
Simulation time 748098300 ps
CPU time 6.94 seconds
Started Jan 17 03:55:43 PM PST 24
Finished Jan 17 03:55:51 PM PST 24
Peak memory 210824 kb
Host smart-edbed3d9-9b40-4129-83e6-b88e4106eabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478721069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2478721069
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1061654256
Short name T395
Test name
Test status
Simulation time 69927359962 ps
CPU time 352.93 seconds
Started Jan 17 03:55:33 PM PST 24
Finished Jan 17 04:01:29 PM PST 24
Peak memory 234476 kb
Host smart-db11bb3e-d99c-442d-959a-cb876609edaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061654256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1061654256
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.1322942936
Short name T275
Test name
Test status
Simulation time 2117939682 ps
CPU time 22.53 seconds
Started Jan 17 03:55:38 PM PST 24
Finished Jan 17 03:56:01 PM PST 24
Peak memory 211192 kb
Host smart-442af88b-e92d-41df-abf2-817b140b8c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322942936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.1322942936
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.3352244061
Short name T150
Test name
Test status
Simulation time 375394624 ps
CPU time 5.72 seconds
Started Jan 17 03:55:36 PM PST 24
Finished Jan 17 03:55:44 PM PST 24
Peak memory 210860 kb
Host smart-5e76a3dd-3bd6-456d-8291-d90f573ba46d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3352244061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.3352244061
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.504152274
Short name T235
Test name
Test status
Simulation time 13944328027 ps
CPU time 28.09 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 03:56:06 PM PST 24
Peak memory 213008 kb
Host smart-4e7e3ed0-b3ef-42d9-b844-0859e93d2bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504152274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.504152274
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1395853798
Short name T376
Test name
Test status
Simulation time 12601473320 ps
CPU time 26.23 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 03:56:04 PM PST 24
Peak memory 216452 kb
Host smart-745432cc-9142-4e16-9a62-d6b263602cc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395853798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1395853798
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.21872384
Short name T313
Test name
Test status
Simulation time 878728130 ps
CPU time 7.82 seconds
Started Jan 17 03:55:42 PM PST 24
Finished Jan 17 03:55:50 PM PST 24
Peak memory 210884 kb
Host smart-7a437b91-e0ab-4dd9-8451-388a102ccac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.21872384
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.439226929
Short name T320
Test name
Test status
Simulation time 18104372831 ps
CPU time 242.58 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 03:59:51 PM PST 24
Peak memory 224344 kb
Host smart-eac864ea-19bd-4812-852c-ffbfb3f64293
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439226929 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_c
orrupt_sig_fatal_chk.439226929
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1272083602
Short name T280
Test name
Test status
Simulation time 3918571650 ps
CPU time 32.84 seconds
Started Jan 17 03:55:39 PM PST 24
Finished Jan 17 03:56:13 PM PST 24
Peak memory 211092 kb
Host smart-a4f038bd-3896-4e92-a575-f404d3cbc580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272083602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1272083602
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.1405795974
Short name T154
Test name
Test status
Simulation time 1849578889 ps
CPU time 10.87 seconds
Started Jan 17 03:55:36 PM PST 24
Finished Jan 17 03:55:49 PM PST 24
Peak memory 210836 kb
Host smart-c511dbe5-128d-462b-8a71-7034f250d9fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405795974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.1405795974
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.4063171216
Short name T188
Test name
Test status
Simulation time 19883262097 ps
CPU time 25.22 seconds
Started Jan 17 03:55:41 PM PST 24
Finished Jan 17 03:56:06 PM PST 24
Peak memory 213120 kb
Host smart-e90c81c3-9988-43ec-891d-fc89486c920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063171216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.4063171216
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1011592927
Short name T252
Test name
Test status
Simulation time 4507505928 ps
CPU time 55.45 seconds
Started Jan 17 03:55:35 PM PST 24
Finished Jan 17 03:56:33 PM PST 24
Peak memory 215760 kb
Host smart-3e0f6a94-5a25-4ed5-b50d-b10a91fe7490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011592927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1011592927
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.3062125882
Short name T180
Test name
Test status
Simulation time 8506605738 ps
CPU time 15.16 seconds
Started Jan 17 03:55:46 PM PST 24
Finished Jan 17 03:56:01 PM PST 24
Peak memory 211036 kb
Host smart-fbc1bce6-e455-4d05-a25d-a50fdbaeb076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062125882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.3062125882
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.42723703
Short name T21
Test name
Test status
Simulation time 35404225177 ps
CPU time 288.35 seconds
Started Jan 17 03:55:43 PM PST 24
Finished Jan 17 04:00:32 PM PST 24
Peak memory 233708 kb
Host smart-fbc59ace-eab4-4845-afc1-fe661c09d937
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723703 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_co
rrupt_sig_fatal_chk.42723703
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.2300060809
Short name T149
Test name
Test status
Simulation time 3985727330 ps
CPU time 34.4 seconds
Started Jan 17 03:55:38 PM PST 24
Finished Jan 17 03:56:13 PM PST 24
Peak memory 210996 kb
Host smart-a7b885e9-4d60-4e79-8830-37db42892c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300060809 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.2300060809
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.4179862533
Short name T343
Test name
Test status
Simulation time 189003897 ps
CPU time 5.84 seconds
Started Jan 17 03:55:36 PM PST 24
Finished Jan 17 03:55:44 PM PST 24
Peak memory 210764 kb
Host smart-b0cb2cb4-d842-4a45-9e7a-90dced2356a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4179862533 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.4179862533
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1276002495
Short name T10
Test name
Test status
Simulation time 247656167 ps
CPU time 10.92 seconds
Started Jan 17 03:55:37 PM PST 24
Finished Jan 17 03:55:49 PM PST 24
Peak memory 212772 kb
Host smart-190d4a7f-2284-42d7-bcc6-fe3110551c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276002495 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1276002495
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.868863735
Short name T345
Test name
Test status
Simulation time 3219509573 ps
CPU time 32.64 seconds
Started Jan 17 03:55:36 PM PST 24
Finished Jan 17 03:56:10 PM PST 24
Peak memory 212688 kb
Host smart-f0bf10d2-a69f-4671-be97-09d6bae46fe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868863735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.rom_ctrl_stress_all.868863735
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.2736039804
Short name T14
Test name
Test status
Simulation time 13741103109 ps
CPU time 5366.42 seconds
Started Jan 17 03:55:33 PM PST 24
Finished Jan 17 05:25:03 PM PST 24
Peak memory 232124 kb
Host smart-b3c88cfe-0117-435c-b841-ee498fe24743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736039804 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.2736039804
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.1496796062
Short name T262
Test name
Test status
Simulation time 182693760 ps
CPU time 4.55 seconds
Started Jan 17 03:55:45 PM PST 24
Finished Jan 17 03:55:51 PM PST 24
Peak memory 210908 kb
Host smart-f133877d-59d9-4f4f-afba-0158ff6d943d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496796062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.1496796062
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.787751816
Short name T113
Test name
Test status
Simulation time 143512830068 ps
CPU time 351.33 seconds
Started Jan 17 03:55:43 PM PST 24
Finished Jan 17 04:01:35 PM PST 24
Peak memory 228120 kb
Host smart-431da327-fed5-47a4-bf46-49569dd11da5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787751816 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_c
orrupt_sig_fatal_chk.787751816
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2850056685
Short name T301
Test name
Test status
Simulation time 340046182 ps
CPU time 9.8 seconds
Started Jan 17 03:55:55 PM PST 24
Finished Jan 17 03:56:05 PM PST 24
Peak memory 211072 kb
Host smart-9c5dba3b-1833-4c81-b224-1ff3ee88489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850056685 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2850056685
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3397612390
Short name T207
Test name
Test status
Simulation time 377521058 ps
CPU time 5.54 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 03:55:54 PM PST 24
Peak memory 210852 kb
Host smart-803a4e0e-f1dc-4989-a0cc-940e9e037a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397612390 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3397612390
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.2665948802
Short name T335
Test name
Test status
Simulation time 3510996897 ps
CPU time 38.96 seconds
Started Jan 17 03:55:44 PM PST 24
Finished Jan 17 03:56:23 PM PST 24
Peak memory 212616 kb
Host smart-54535f59-5382-48f7-8e02-687774d40237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665948802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.2665948802
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all.139235321
Short name T292
Test name
Test status
Simulation time 3046165384 ps
CPU time 17.42 seconds
Started Jan 17 03:55:46 PM PST 24
Finished Jan 17 03:56:04 PM PST 24
Peak memory 213804 kb
Host smart-2e106ab1-f6b5-436c-a684-ac5a0cc37e31
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139235321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.rom_ctrl_stress_all.139235321
Directory /workspace/43.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.3580367265
Short name T303
Test name
Test status
Simulation time 113699674413 ps
CPU time 1457.31 seconds
Started Jan 17 03:55:45 PM PST 24
Finished Jan 17 04:20:03 PM PST 24
Peak memory 235568 kb
Host smart-8d48ba56-f27e-41fd-baf5-3537e6275215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580367265 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.3580367265
Directory /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.3103404635
Short name T246
Test name
Test status
Simulation time 1365395419 ps
CPU time 12.26 seconds
Started Jan 17 03:55:47 PM PST 24
Finished Jan 17 03:55:59 PM PST 24
Peak memory 210908 kb
Host smart-61daf146-c046-454f-b503-2a9781fbb540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103404635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.3103404635
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.3184707374
Short name T277
Test name
Test status
Simulation time 56436917596 ps
CPU time 256.39 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 04:00:05 PM PST 24
Peak memory 212232 kb
Host smart-b2a8cef7-11e4-4b26-8062-b9ebf1b649cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184707374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.3184707374
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.2869800734
Short name T427
Test name
Test status
Simulation time 2952696955 ps
CPU time 19.4 seconds
Started Jan 17 03:55:49 PM PST 24
Finished Jan 17 03:56:10 PM PST 24
Peak memory 211300 kb
Host smart-0802a657-f4a2-4154-ae8a-1c87bde4195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869800734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.2869800734
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3332842525
Short name T393
Test name
Test status
Simulation time 1189391646 ps
CPU time 7.85 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 03:55:57 PM PST 24
Peak memory 210912 kb
Host smart-3e8dc5d4-73cd-4297-9407-c0449378304b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332842525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3332842525
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.4016510631
Short name T238
Test name
Test status
Simulation time 1145009519 ps
CPU time 17.4 seconds
Started Jan 17 03:55:44 PM PST 24
Finished Jan 17 03:56:02 PM PST 24
Peak memory 212228 kb
Host smart-20c9f72b-4f59-4ea9-a37d-ff31c96269bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016510631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.4016510631
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3046653188
Short name T283
Test name
Test status
Simulation time 5612878297 ps
CPU time 60.74 seconds
Started Jan 17 03:55:47 PM PST 24
Finished Jan 17 03:56:49 PM PST 24
Peak memory 216216 kb
Host smart-d4d2680e-2383-4ac0-b96b-32e0c6c78131
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046653188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3046653188
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.86496999
Short name T22
Test name
Test status
Simulation time 121019644170 ps
CPU time 2979.01 seconds
Started Jan 17 03:55:47 PM PST 24
Finished Jan 17 04:45:27 PM PST 24
Peak memory 235504 kb
Host smart-f3bee061-0928-42de-8aaa-538a3c03c113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86496999 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.86496999
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.3884076525
Short name T199
Test name
Test status
Simulation time 2131999589 ps
CPU time 16.48 seconds
Started Jan 17 03:55:47 PM PST 24
Finished Jan 17 03:56:04 PM PST 24
Peak memory 210900 kb
Host smart-9604459c-b5ef-491b-ac38-0a48eca49714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884076525 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.3884076525
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.1386189526
Short name T408
Test name
Test status
Simulation time 16413470238 ps
CPU time 33.1 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 03:56:21 PM PST 24
Peak memory 211316 kb
Host smart-87e61c89-9935-4c8b-b7e0-81f5a1a06e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386189526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.1386189526
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.3742852290
Short name T258
Test name
Test status
Simulation time 777105604 ps
CPU time 5.9 seconds
Started Jan 17 03:55:52 PM PST 24
Finished Jan 17 03:56:01 PM PST 24
Peak memory 210868 kb
Host smart-1ccc6758-8f4c-4363-bc13-9904a5cb9bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742852290 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.3742852290
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1107892473
Short name T364
Test name
Test status
Simulation time 6312759073 ps
CPU time 31.75 seconds
Started Jan 17 03:55:49 PM PST 24
Finished Jan 17 03:56:21 PM PST 24
Peak memory 212840 kb
Host smart-1284cff0-70de-45e7-823e-f0d6f7d98fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107892473 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1107892473
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.2883700577
Short name T392
Test name
Test status
Simulation time 10422699999 ps
CPU time 29.55 seconds
Started Jan 17 03:55:45 PM PST 24
Finished Jan 17 03:56:15 PM PST 24
Peak memory 216064 kb
Host smart-277d10b9-324b-43ee-a7a8-7450c9a4d0b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883700577 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.2883700577
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.2301251010
Short name T374
Test name
Test status
Simulation time 1714023557 ps
CPU time 15.18 seconds
Started Jan 17 03:55:54 PM PST 24
Finished Jan 17 03:56:11 PM PST 24
Peak memory 210828 kb
Host smart-d3070fc8-fd3f-4a88-9855-83cf37bb8a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301251010 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.2301251010
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.4198608377
Short name T168
Test name
Test status
Simulation time 18113953300 ps
CPU time 183.58 seconds
Started Jan 17 03:55:53 PM PST 24
Finished Jan 17 03:58:59 PM PST 24
Peak memory 237360 kb
Host smart-4a07da54-fd7f-4158-bd38-1c1a7309fed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198608377 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.4198608377
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1403248105
Short name T254
Test name
Test status
Simulation time 16315641944 ps
CPU time 32.81 seconds
Started Jan 17 03:55:57 PM PST 24
Finished Jan 17 03:56:35 PM PST 24
Peak memory 211220 kb
Host smart-d4ada383-2554-4edd-ae36-555c89050798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403248105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1403248105
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.2649460779
Short name T368
Test name
Test status
Simulation time 1619731019 ps
CPU time 9.19 seconds
Started Jan 17 03:55:56 PM PST 24
Finished Jan 17 03:56:11 PM PST 24
Peak memory 210796 kb
Host smart-00a4c74b-aab1-4a79-be63-e6f062c514e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649460779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.2649460779
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.2269877899
Short name T224
Test name
Test status
Simulation time 3048115055 ps
CPU time 26.52 seconds
Started Jan 17 03:55:46 PM PST 24
Finished Jan 17 03:56:13 PM PST 24
Peak memory 212368 kb
Host smart-4d10b48f-2882-4c52-9ac4-f82d94b68870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269877899 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2269877899
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.3739535657
Short name T161
Test name
Test status
Simulation time 5008216298 ps
CPU time 30.85 seconds
Started Jan 17 03:55:48 PM PST 24
Finished Jan 17 03:56:19 PM PST 24
Peak memory 212464 kb
Host smart-801899e1-5ee3-4db7-929d-0df3961e816c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739535657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 46.rom_ctrl_stress_all.3739535657
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.37782969
Short name T389
Test name
Test status
Simulation time 82644216949 ps
CPU time 1806.6 seconds
Started Jan 17 03:55:55 PM PST 24
Finished Jan 17 04:26:07 PM PST 24
Peak memory 243788 kb
Host smart-44bff251-7c57-48c1-bab5-96c514d9802f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37782969 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.37782969
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.3471252135
Short name T340
Test name
Test status
Simulation time 994366008 ps
CPU time 7.91 seconds
Started Jan 17 03:55:50 PM PST 24
Finished Jan 17 03:56:00 PM PST 24
Peak memory 210876 kb
Host smart-c9e0999c-b61b-41fe-8bf6-766e1fc32b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471252135 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.3471252135
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.231743196
Short name T206
Test name
Test status
Simulation time 75338003258 ps
CPU time 178.17 seconds
Started Jan 17 03:55:51 PM PST 24
Finished Jan 17 03:58:52 PM PST 24
Peak memory 212228 kb
Host smart-45b271af-b0b7-4c6e-8df2-a6d2f7e9dc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231743196 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.231743196
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2031256915
Short name T317
Test name
Test status
Simulation time 5159346718 ps
CPU time 17.4 seconds
Started Jan 17 03:55:52 PM PST 24
Finished Jan 17 03:56:11 PM PST 24
Peak memory 211432 kb
Host smart-cc41652f-7475-4be8-b260-a3333072f152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031256915 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2031256915
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.639500628
Short name T426
Test name
Test status
Simulation time 5281386635 ps
CPU time 13.25 seconds
Started Jan 17 03:55:49 PM PST 24
Finished Jan 17 03:56:05 PM PST 24
Peak memory 210836 kb
Host smart-8d893d17-3ead-4213-80c2-92eaffb3c4a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=639500628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.639500628
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.787341673
Short name T248
Test name
Test status
Simulation time 735168447 ps
CPU time 10.14 seconds
Started Jan 17 03:55:51 PM PST 24
Finished Jan 17 03:56:04 PM PST 24
Peak memory 212540 kb
Host smart-4639718b-8316-4dd2-858e-479365e2ff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787341673 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.787341673
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3123112124
Short name T211
Test name
Test status
Simulation time 10780607286 ps
CPU time 17.25 seconds
Started Jan 17 03:55:51 PM PST 24
Finished Jan 17 03:56:11 PM PST 24
Peak memory 211768 kb
Host smart-53b73635-81e2-42d8-aa2e-0e6e6bb5cc60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123112124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3123112124
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.838935267
Short name T336
Test name
Test status
Simulation time 71194875587 ps
CPU time 2628.33 seconds
Started Jan 17 03:55:51 PM PST 24
Finished Jan 17 04:39:43 PM PST 24
Peak memory 250516 kb
Host smart-83b841a2-b002-409f-b52d-39c2988f8233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838935267 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.838935267
Directory /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.1082621317
Short name T314
Test name
Test status
Simulation time 2052132090 ps
CPU time 10.22 seconds
Started Jan 17 03:55:56 PM PST 24
Finished Jan 17 03:56:12 PM PST 24
Peak memory 211080 kb
Host smart-5f959082-4766-46a3-a023-370c11be4d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082621317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.1082621317
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4279574791
Short name T213
Test name
Test status
Simulation time 3146719951 ps
CPU time 221.46 seconds
Started Jan 17 03:55:53 PM PST 24
Finished Jan 17 03:59:37 PM PST 24
Peak memory 220652 kb
Host smart-83a07c9c-fb68-417a-928b-ab92181ac03e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279574791 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.4279574791
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1359806710
Short name T387
Test name
Test status
Simulation time 723004172 ps
CPU time 9.89 seconds
Started Jan 17 03:55:59 PM PST 24
Finished Jan 17 03:56:12 PM PST 24
Peak memory 211000 kb
Host smart-27195ddc-74bd-4fd5-8b15-eec998914cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359806710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1359806710
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.419907634
Short name T152
Test name
Test status
Simulation time 21670744753 ps
CPU time 17.44 seconds
Started Jan 17 03:55:51 PM PST 24
Finished Jan 17 03:56:11 PM PST 24
Peak memory 210856 kb
Host smart-1aebf28c-8aa1-4407-8781-e59132a43c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=419907634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.419907634
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.3679916169
Short name T388
Test name
Test status
Simulation time 17785265232 ps
CPU time 41.74 seconds
Started Jan 17 03:55:53 PM PST 24
Finished Jan 17 03:56:37 PM PST 24
Peak memory 213468 kb
Host smart-595b038c-fe85-4972-9398-de8d49d0729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679916169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.3679916169
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.3622171606
Short name T202
Test name
Test status
Simulation time 20507554719 ps
CPU time 30.99 seconds
Started Jan 17 03:55:57 PM PST 24
Finished Jan 17 03:56:33 PM PST 24
Peak memory 213628 kb
Host smart-ca5e0a73-7d75-4dd5-b26b-55d859fbd2b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622171606 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.3622171606
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2438188084
Short name T422
Test name
Test status
Simulation time 58161025297 ps
CPU time 2324.56 seconds
Started Jan 17 03:55:59 PM PST 24
Finished Jan 17 04:34:47 PM PST 24
Peak memory 238848 kb
Host smart-b5dee202-9565-48bb-a8c7-2b3b259225e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438188084 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2438188084
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.2373388581
Short name T425
Test name
Test status
Simulation time 3269119307 ps
CPU time 7.93 seconds
Started Jan 17 03:55:57 PM PST 24
Finished Jan 17 03:56:10 PM PST 24
Peak memory 211032 kb
Host smart-b3c907d3-8fa2-4691-8b7c-9cf41b218719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373388581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.2373388581
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.16291145
Short name T309
Test name
Test status
Simulation time 28795312931 ps
CPU time 341.56 seconds
Started Jan 17 03:55:56 PM PST 24
Finished Jan 17 04:01:44 PM PST 24
Peak memory 237388 kb
Host smart-b11a0df8-8606-4c88-852c-f92d3beed673
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16291145 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_co
rrupt_sig_fatal_chk.16291145
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2359402084
Short name T415
Test name
Test status
Simulation time 15459304067 ps
CPU time 27.67 seconds
Started Jan 17 03:55:57 PM PST 24
Finished Jan 17 03:56:30 PM PST 24
Peak memory 210932 kb
Host smart-cef3e360-06d7-4f95-b165-d6e83622644b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359402084 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2359402084
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.519559274
Short name T169
Test name
Test status
Simulation time 468539434 ps
CPU time 5.82 seconds
Started Jan 17 03:55:57 PM PST 24
Finished Jan 17 03:56:08 PM PST 24
Peak memory 210844 kb
Host smart-d984e9b0-c2a4-4046-a3d3-3d14980d0489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=519559274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.519559274
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.3446809541
Short name T220
Test name
Test status
Simulation time 191904472 ps
CPU time 10.87 seconds
Started Jan 17 03:56:00 PM PST 24
Finished Jan 17 03:56:13 PM PST 24
Peak memory 212380 kb
Host smart-64dbe45c-9c1e-4efb-a813-e37c4d82dbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446809541 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.3446809541
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/49.rom_ctrl_stress_all.2779048347
Short name T239
Test name
Test status
Simulation time 1628551564 ps
CPU time 24.8 seconds
Started Jan 17 03:55:59 PM PST 24
Finished Jan 17 03:56:27 PM PST 24
Peak memory 215428 kb
Host smart-3f281e0a-362d-4113-abf8-86beb3f0fddb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779048347 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 49.rom_ctrl_stress_all.2779048347
Directory /workspace/49.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.2062247889
Short name T286
Test name
Test status
Simulation time 174633655 ps
CPU time 4.44 seconds
Started Jan 17 03:53:57 PM PST 24
Finished Jan 17 03:54:04 PM PST 24
Peak memory 210968 kb
Host smart-6aa80e65-2b87-4442-93c7-691fd6d11714
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062247889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.2062247889
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.890474316
Short name T23
Test name
Test status
Simulation time 12596680022 ps
CPU time 172.91 seconds
Started Jan 17 03:53:55 PM PST 24
Finished Jan 17 03:56:48 PM PST 24
Peak memory 234488 kb
Host smart-ae0e5361-2fca-4dc3-8b3d-f1ed2d745ebd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890474316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.890474316
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.597190176
Short name T266
Test name
Test status
Simulation time 758619992 ps
CPU time 9.9 seconds
Started Jan 17 03:53:56 PM PST 24
Finished Jan 17 03:54:08 PM PST 24
Peak memory 211824 kb
Host smart-9824035e-12e8-443c-a1b4-45b4b724fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597190176 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.597190176
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.2284528710
Short name T247
Test name
Test status
Simulation time 2995965908 ps
CPU time 16.49 seconds
Started Jan 17 03:53:54 PM PST 24
Finished Jan 17 03:54:11 PM PST 24
Peak memory 210692 kb
Host smart-6c16bbae-c521-45cf-a678-881791cec40c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284528710 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.2284528710
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.2805086878
Short name T172
Test name
Test status
Simulation time 9225170349 ps
CPU time 28.68 seconds
Started Jan 17 03:53:58 PM PST 24
Finished Jan 17 03:54:28 PM PST 24
Peak memory 213088 kb
Host smart-d2eee306-0855-45c6-a03d-ea9fce3c0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805086878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2805086878
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3609150242
Short name T53
Test name
Test status
Simulation time 472405802 ps
CPU time 8.22 seconds
Started Jan 17 03:53:58 PM PST 24
Finished Jan 17 03:54:08 PM PST 24
Peak memory 210880 kb
Host smart-4d3d757c-2f11-40c3-9124-e0afd05a81f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609150242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3609150242
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.329004031
Short name T349
Test name
Test status
Simulation time 954179317 ps
CPU time 10.28 seconds
Started Jan 17 03:53:57 PM PST 24
Finished Jan 17 03:54:09 PM PST 24
Peak memory 210932 kb
Host smart-c3af043f-d1d4-409c-b7d5-941a9d5072b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329004031 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.329004031
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.1883573569
Short name T412
Test name
Test status
Simulation time 54075996683 ps
CPU time 491.67 seconds
Started Jan 17 03:53:55 PM PST 24
Finished Jan 17 04:02:07 PM PST 24
Peak memory 212584 kb
Host smart-7472f362-7c7c-4d8e-83e9-652d00d25bae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883573569 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.1883573569
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.2939496490
Short name T302
Test name
Test status
Simulation time 32005891988 ps
CPU time 30.74 seconds
Started Jan 17 03:54:02 PM PST 24
Finished Jan 17 03:54:39 PM PST 24
Peak memory 214524 kb
Host smart-d0b49206-8973-4342-b104-7a8f86b72842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939496490 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.2939496490
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3161842561
Short name T176
Test name
Test status
Simulation time 188107593 ps
CPU time 5.59 seconds
Started Jan 17 03:53:55 PM PST 24
Finished Jan 17 03:54:01 PM PST 24
Peak memory 210816 kb
Host smart-14d0df17-610f-42ac-bab0-b095a2244022
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161842561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3161842561
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.1183077033
Short name T210
Test name
Test status
Simulation time 2153527289 ps
CPU time 23.21 seconds
Started Jan 17 03:53:55 PM PST 24
Finished Jan 17 03:54:20 PM PST 24
Peak memory 212752 kb
Host smart-eaf1e037-ad33-4f1b-9e74-cd9890e6fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183077033 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.1183077033
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.3638960502
Short name T291
Test name
Test status
Simulation time 440448071 ps
CPU time 22.13 seconds
Started Jan 17 03:53:54 PM PST 24
Finished Jan 17 03:54:17 PM PST 24
Peak memory 215256 kb
Host smart-8d7abcca-9c76-4b7b-9767-88d74c9ac290
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638960502 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.rom_ctrl_stress_all.3638960502
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.3307643070
Short name T411
Test name
Test status
Simulation time 1145008265 ps
CPU time 11.46 seconds
Started Jan 17 03:54:05 PM PST 24
Finished Jan 17 03:54:19 PM PST 24
Peak memory 210964 kb
Host smart-27b68b7a-bc1e-45b9-937f-bd7cb87a0180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307643070 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.3307643070
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1251170168
Short name T270
Test name
Test status
Simulation time 61123441523 ps
CPU time 195.67 seconds
Started Jan 17 03:54:00 PM PST 24
Finished Jan 17 03:57:17 PM PST 24
Peak memory 236328 kb
Host smart-b5265f4b-58b4-4c46-b763-fc9797b4630e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251170168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.1251170168
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3299496407
Short name T5
Test name
Test status
Simulation time 340470063 ps
CPU time 9.83 seconds
Started Jan 17 03:53:58 PM PST 24
Finished Jan 17 03:54:09 PM PST 24
Peak memory 211144 kb
Host smart-a3bce055-772b-4a0c-abac-6921b879ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299496407 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3299496407
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.4216965939
Short name T429
Test name
Test status
Simulation time 1398540072 ps
CPU time 7.76 seconds
Started Jan 17 03:53:56 PM PST 24
Finished Jan 17 03:54:05 PM PST 24
Peak memory 210836 kb
Host smart-c198632f-e7a4-4e16-8494-98b7481bfaf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216965939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.4216965939
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.2389071622
Short name T282
Test name
Test status
Simulation time 182503949 ps
CPU time 10.28 seconds
Started Jan 17 03:53:55 PM PST 24
Finished Jan 17 03:54:06 PM PST 24
Peak memory 212156 kb
Host smart-82cad734-809e-4c59-ad45-e6d67fa5cd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389071622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.2389071622
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.753741063
Short name T163
Test name
Test status
Simulation time 37096390003 ps
CPU time 89.47 seconds
Started Jan 17 03:53:54 PM PST 24
Finished Jan 17 03:55:24 PM PST 24
Peak memory 217064 kb
Host smart-07de5ab2-a504-4836-a784-490556001f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753741063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.rom_ctrl_stress_all.753741063
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.4010245596
Short name T174
Test name
Test status
Simulation time 3224274876 ps
CPU time 194.66 seconds
Started Jan 17 03:54:01 PM PST 24
Finished Jan 17 03:57:22 PM PST 24
Peak memory 220060 kb
Host smart-f47f4d6a-cfa2-42c5-8754-eec226f57666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010245596 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.4010245596
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.963980597
Short name T294
Test name
Test status
Simulation time 329889777 ps
CPU time 6.89 seconds
Started Jan 17 03:54:00 PM PST 24
Finished Jan 17 03:54:08 PM PST 24
Peak memory 210812 kb
Host smart-861525e7-c5fd-45ab-a830-c7c168032fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963980597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.963980597
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2827363695
Short name T218
Test name
Test status
Simulation time 110374530794 ps
CPU time 285.36 seconds
Started Jan 17 03:53:59 PM PST 24
Finished Jan 17 03:58:46 PM PST 24
Peak memory 234472 kb
Host smart-c45239d7-425e-43f1-a799-a83d25fc6f75
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827363695 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2827363695
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.1300146482
Short name T423
Test name
Test status
Simulation time 1161976753 ps
CPU time 17.57 seconds
Started Jan 17 03:54:18 PM PST 24
Finished Jan 17 03:54:37 PM PST 24
Peak memory 210984 kb
Host smart-127515e1-8edf-4e6b-859e-cfba84befc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300146482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.1300146482
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.1566719985
Short name T402
Test name
Test status
Simulation time 1770844148 ps
CPU time 15.61 seconds
Started Jan 17 03:54:18 PM PST 24
Finished Jan 17 03:54:34 PM PST 24
Peak memory 210880 kb
Host smart-92333867-becb-4668-92fc-ad1c8a2cb55e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1566719985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.1566719985
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.3453875805
Short name T205
Test name
Test status
Simulation time 1119982013 ps
CPU time 17.88 seconds
Started Jan 17 03:54:04 PM PST 24
Finished Jan 17 03:54:26 PM PST 24
Peak memory 212696 kb
Host smart-71285169-3468-45fa-bdf9-2534eba2348a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453875805 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3453875805
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.136125365
Short name T222
Test name
Test status
Simulation time 3894879026 ps
CPU time 50.38 seconds
Started Jan 17 03:54:01 PM PST 24
Finished Jan 17 03:54:52 PM PST 24
Peak memory 216008 kb
Host smart-ad6d9d0f-03f1-434e-a44d-4b1392c0cd9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136125365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.rom_ctrl_stress_all.136125365
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.3194877197
Short name T227
Test name
Test status
Simulation time 565694024 ps
CPU time 6.52 seconds
Started Jan 17 03:53:58 PM PST 24
Finished Jan 17 03:54:06 PM PST 24
Peak memory 210912 kb
Host smart-b0ae2635-df38-44cb-ac09-cbd40fa1162d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194877197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3194877197
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2835286867
Short name T27
Test name
Test status
Simulation time 6788308055 ps
CPU time 99.84 seconds
Started Jan 17 03:54:02 PM PST 24
Finished Jan 17 03:55:48 PM PST 24
Peak memory 228176 kb
Host smart-3fd591bb-44be-46c9-82e4-51a2ae8faa7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835286867 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.2835286867
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.1535184640
Short name T354
Test name
Test status
Simulation time 170076496 ps
CPU time 9.9 seconds
Started Jan 17 03:54:00 PM PST 24
Finished Jan 17 03:54:11 PM PST 24
Peak memory 211260 kb
Host smart-530db284-fe8f-4845-abec-cb0432578a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535184640 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.1535184640
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.1328258514
Short name T409
Test name
Test status
Simulation time 2242043161 ps
CPU time 18.04 seconds
Started Jan 17 03:54:05 PM PST 24
Finished Jan 17 03:54:26 PM PST 24
Peak memory 210976 kb
Host smart-38ec89cb-ed5a-426a-aebe-cca802ce06ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1328258514 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.1328258514
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.4147604647
Short name T358
Test name
Test status
Simulation time 34245978556 ps
CPU time 24.91 seconds
Started Jan 17 03:53:59 PM PST 24
Finished Jan 17 03:54:26 PM PST 24
Peak memory 213272 kb
Host smart-e68dc710-de72-4801-b3c1-ec44a014a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147604647 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.4147604647
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.331789016
Short name T148
Test name
Test status
Simulation time 1850419469 ps
CPU time 16.48 seconds
Started Jan 17 03:53:59 PM PST 24
Finished Jan 17 03:54:17 PM PST 24
Peak memory 210832 kb
Host smart-c9dec38d-24fa-450e-a4d6-555b776b9522
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331789016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.rom_ctrl_stress_all.331789016
Directory /workspace/9.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.3372371085
Short name T321
Test name
Test status
Simulation time 65504112116 ps
CPU time 1918 seconds
Started Jan 17 03:54:00 PM PST 24
Finished Jan 17 04:25:59 PM PST 24
Peak memory 233820 kb
Host smart-d7a0894e-4f31-4dfc-804c-5716c9b0bc8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372371085 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.3372371085
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest
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