| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.55 | 97.04 | 92.80 | 97.88 | 100.00 | 98.69 | 98.04 | 98.38 |
| T58 | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1482305856 | Jan 21 09:06:50 PM PST 24 | Jan 21 09:14:15 PM PST 24 | 85965732995 ps | ||
| T272 | /workspace/coverage/default/34.rom_ctrl_stress_all.1509388182 | Jan 21 09:09:05 PM PST 24 | Jan 21 09:09:28 PM PST 24 | 2423754917 ps | ||
| T273 | /workspace/coverage/default/1.rom_ctrl_alert_test.2410918199 | Jan 21 09:06:15 PM PST 24 | Jan 21 09:07:00 PM PST 24 | 6425958826 ps | ||
| T274 | /workspace/coverage/default/36.rom_ctrl_smoke.1037665160 | Jan 21 09:09:17 PM PST 24 | Jan 21 09:09:48 PM PST 24 | 23023914607 ps | ||
| T275 | /workspace/coverage/default/32.rom_ctrl_smoke.3960864889 | Jan 21 09:08:49 PM PST 24 | Jan 21 09:09:11 PM PST 24 | 2015282941 ps | ||
| T276 | /workspace/coverage/default/6.rom_ctrl_smoke.2374019729 | Jan 21 09:06:47 PM PST 24 | Jan 21 09:07:40 PM PST 24 | 3338598223 ps | ||
| T277 | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.806458281 | Jan 21 09:10:08 PM PST 24 | Jan 21 09:10:41 PM PST 24 | 1658850187 ps | ||
| T278 | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2676385348 | Jan 21 09:07:01 PM PST 24 | Jan 21 09:07:22 PM PST 24 | 611541456 ps | ||
| T279 | /workspace/coverage/default/25.rom_ctrl_alert_test.2349937302 | Jan 21 09:47:18 PM PST 24 | Jan 21 09:47:38 PM PST 24 | 4112369001 ps | ||
| T280 | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1568422877 | Jan 21 10:34:29 PM PST 24 | Jan 21 10:42:39 PM PST 24 | 45974340623 ps | ||
| T281 | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2993226103 | Jan 21 09:08:33 PM PST 24 | Jan 21 09:12:56 PM PST 24 | 103434206170 ps | ||
| T282 | /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1547570277 | Jan 21 09:09:49 PM PST 24 | Jan 21 11:16:35 PM PST 24 | 78138384456 ps | ||
| T283 | /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1141117523 | Jan 21 09:07:34 PM PST 24 | Jan 21 09:25:23 PM PST 24 | 20111861042 ps | ||
| T284 | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3882863581 | Jan 21 09:08:43 PM PST 24 | Jan 21 09:09:28 PM PST 24 | 3304316943 ps | ||
| T285 | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3072499128 | Jan 21 09:08:20 PM PST 24 | Jan 21 09:09:00 PM PST 24 | 2739876884 ps | ||
| T286 | /workspace/coverage/default/22.rom_ctrl_stress_all.3173901305 | Jan 21 09:08:09 PM PST 24 | Jan 21 09:09:36 PM PST 24 | 7422702850 ps | ||
| T287 | /workspace/coverage/default/29.rom_ctrl_smoke.1905850453 | Jan 21 09:08:42 PM PST 24 | Jan 21 09:09:10 PM PST 24 | 3789794445 ps | ||
| T288 | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.220927441 | Jan 21 09:07:34 PM PST 24 | Jan 21 09:08:06 PM PST 24 | 3737668296 ps | ||
| T289 | /workspace/coverage/default/24.rom_ctrl_stress_all.3851940824 | Jan 21 09:08:17 PM PST 24 | Jan 21 09:09:03 PM PST 24 | 2524075631 ps | ||
| T290 | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1184562625 | Jan 21 09:10:03 PM PST 24 | Jan 21 09:14:18 PM PST 24 | 40107727316 ps | ||
| T291 | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3842959852 | Jan 21 09:06:35 PM PST 24 | Jan 21 09:07:14 PM PST 24 | 1158168951 ps | ||
| T292 | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2950174794 | Jan 21 09:07:30 PM PST 24 | Jan 21 09:11:09 PM PST 24 | 52628507391 ps | ||
| T293 | /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2852862745 | Jan 21 09:10:08 PM PST 24 | Jan 21 09:52:15 PM PST 24 | 63722836615 ps | ||
| T294 | /workspace/coverage/default/8.rom_ctrl_smoke.3266978792 | Jan 21 09:06:57 PM PST 24 | Jan 21 09:07:45 PM PST 24 | 6092328272 ps | ||
| T295 | /workspace/coverage/default/24.rom_ctrl_alert_test.2940839107 | Jan 21 09:08:25 PM PST 24 | Jan 21 09:08:54 PM PST 24 | 2220511272 ps | ||
| T296 | /workspace/coverage/default/31.rom_ctrl_stress_all.1631342940 | Jan 21 09:08:51 PM PST 24 | Jan 21 09:09:37 PM PST 24 | 2303029188 ps | ||
| T297 | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4155064148 | Jan 21 09:08:30 PM PST 24 | Jan 21 09:09:00 PM PST 24 | 1106000846 ps | ||
| T298 | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3353241147 | Jan 21 09:08:20 PM PST 24 | Jan 21 09:08:51 PM PST 24 | 94643557 ps | ||
| T299 | /workspace/coverage/default/44.rom_ctrl_smoke.1682145035 | Jan 21 09:10:06 PM PST 24 | Jan 21 09:10:41 PM PST 24 | 3640022878 ps | ||
| T300 | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1494098932 | Jan 21 10:05:32 PM PST 24 | Jan 21 10:10:23 PM PST 24 | 259125915015 ps | ||
| T301 | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1078471472 | Jan 21 09:32:20 PM PST 24 | Jan 21 09:37:22 PM PST 24 | 31038336507 ps | ||
| T302 | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3143470075 | Jan 21 09:08:49 PM PST 24 | Jan 21 09:09:15 PM PST 24 | 1003313408 ps | ||
| T303 | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3916237683 | Jan 21 09:07:22 PM PST 24 | Jan 21 09:10:20 PM PST 24 | 10072352800 ps | ||
| T304 | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2373015299 | Jan 21 09:09:49 PM PST 24 | Jan 21 09:10:11 PM PST 24 | 1725924313 ps | ||
| T305 | /workspace/coverage/default/15.rom_ctrl_alert_test.2299981554 | Jan 21 09:07:33 PM PST 24 | Jan 21 09:07:58 PM PST 24 | 3340080611 ps | ||
| T306 | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.157523903 | Jan 21 09:08:18 PM PST 24 | Jan 21 09:09:10 PM PST 24 | 5381509599 ps | ||
| T307 | /workspace/coverage/default/11.rom_ctrl_smoke.3018943634 | Jan 21 09:07:20 PM PST 24 | Jan 21 09:07:48 PM PST 24 | 4916970905 ps | ||
| T308 | /workspace/coverage/default/47.rom_ctrl_smoke.370779450 | Jan 21 09:10:13 PM PST 24 | Jan 21 09:10:41 PM PST 24 | 190985605 ps | ||
| T43 | /workspace/coverage/default/1.rom_ctrl_sec_cm.2689119195 | Jan 21 09:06:18 PM PST 24 | Jan 21 09:07:45 PM PST 24 | 1731678798 ps | ||
| T309 | /workspace/coverage/default/41.rom_ctrl_stress_all.3146731548 | Jan 21 09:09:49 PM PST 24 | Jan 21 09:11:58 PM PST 24 | 49469725532 ps | ||
| T310 | /workspace/coverage/default/22.rom_ctrl_smoke.4038444209 | Jan 21 09:08:10 PM PST 24 | Jan 21 09:09:08 PM PST 24 | 20962613452 ps | ||
| T311 | /workspace/coverage/default/42.rom_ctrl_alert_test.4279765505 | Jan 21 09:10:04 PM PST 24 | Jan 21 09:10:37 PM PST 24 | 1640364290 ps | ||
| T312 | /workspace/coverage/default/33.rom_ctrl_alert_test.2051683479 | Jan 21 09:09:09 PM PST 24 | Jan 21 09:09:29 PM PST 24 | 5184124626 ps | ||
| T313 | /workspace/coverage/default/38.rom_ctrl_stress_all.2808545639 | Jan 21 09:09:27 PM PST 24 | Jan 21 09:09:50 PM PST 24 | 6430403801 ps | ||
| T314 | /workspace/coverage/default/30.rom_ctrl_smoke.2560395638 | Jan 21 09:38:51 PM PST 24 | Jan 21 09:39:19 PM PST 24 | 3037962402 ps | ||
| T315 | /workspace/coverage/default/26.rom_ctrl_stress_all.1450429657 | Jan 21 09:44:13 PM PST 24 | Jan 21 09:45:11 PM PST 24 | 1715653709 ps | ||
| T316 | /workspace/coverage/default/30.rom_ctrl_alert_test.753660188 | Jan 21 09:08:48 PM PST 24 | Jan 21 09:09:10 PM PST 24 | 1849452772 ps | ||
| T317 | /workspace/coverage/default/35.rom_ctrl_stress_all.447325728 | Jan 21 09:09:13 PM PST 24 | Jan 21 09:09:51 PM PST 24 | 2201518835 ps | ||
| T318 | /workspace/coverage/default/23.rom_ctrl_stress_all.3209866106 | Jan 21 09:08:11 PM PST 24 | Jan 21 09:09:21 PM PST 24 | 21856688008 ps | ||
| T16 | /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2654394685 | Jan 21 09:07:48 PM PST 24 | Jan 21 11:23:20 PM PST 24 | 70652697706 ps | ||
| T319 | /workspace/coverage/default/20.rom_ctrl_alert_test.2884362077 | Jan 21 09:08:09 PM PST 24 | Jan 21 09:08:41 PM PST 24 | 1650838856 ps | ||
| T320 | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1545266425 | Jan 21 09:06:50 PM PST 24 | Jan 21 09:07:32 PM PST 24 | 2411711687 ps | ||
| T321 | /workspace/coverage/default/2.rom_ctrl_alert_test.2225885876 | Jan 21 09:06:17 PM PST 24 | Jan 21 09:07:00 PM PST 24 | 9403726795 ps | ||
| T322 | /workspace/coverage/default/49.rom_ctrl_smoke.2830522882 | Jan 21 09:10:25 PM PST 24 | Jan 21 09:11:12 PM PST 24 | 9947629218 ps | ||
| T323 | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4146585132 | Jan 21 09:07:31 PM PST 24 | Jan 21 09:07:51 PM PST 24 | 693606729 ps | ||
| T324 | /workspace/coverage/default/20.rom_ctrl_stress_all.1641214253 | Jan 21 09:08:01 PM PST 24 | Jan 21 09:09:05 PM PST 24 | 17230840771 ps | ||
| T325 | /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2068533607 | Jan 21 09:10:17 PM PST 24 | Jan 21 10:36:56 PM PST 24 | 147181951308 ps | ||
| T326 | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2000054866 | Jan 21 09:08:48 PM PST 24 | Jan 21 09:09:08 PM PST 24 | 1416741674 ps | ||
| T327 | /workspace/coverage/default/35.rom_ctrl_smoke.3847929735 | Jan 21 09:09:14 PM PST 24 | Jan 21 09:09:46 PM PST 24 | 2394034462 ps | ||
| T328 | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2039638256 | Jan 21 09:06:48 PM PST 24 | Jan 21 09:09:24 PM PST 24 | 14335592221 ps | ||
| T329 | /workspace/coverage/default/19.rom_ctrl_alert_test.1976665451 | Jan 21 09:07:49 PM PST 24 | Jan 21 09:08:11 PM PST 24 | 172077352 ps | ||
| T330 | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1626332591 | Jan 21 09:08:51 PM PST 24 | Jan 21 09:09:29 PM PST 24 | 6182140316 ps | ||
| T331 | /workspace/coverage/default/48.rom_ctrl_alert_test.2372650700 | Jan 21 09:10:24 PM PST 24 | Jan 21 09:10:50 PM PST 24 | 90119642 ps | ||
| T332 | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3111632875 | Jan 21 09:08:33 PM PST 24 | Jan 21 09:08:57 PM PST 24 | 98199472 ps | ||
| T333 | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4180815834 | Jan 21 09:07:12 PM PST 24 | Jan 21 09:07:55 PM PST 24 | 3635190341 ps | ||
| T334 | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3824543074 | Jan 21 09:08:43 PM PST 24 | Jan 21 09:09:25 PM PST 24 | 11605222972 ps | ||
| T335 | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.760040559 | Jan 21 09:36:12 PM PST 24 | Jan 21 09:36:26 PM PST 24 | 1805216533 ps | ||
| T336 | /workspace/coverage/default/47.rom_ctrl_stress_all.3303205676 | Jan 21 09:10:20 PM PST 24 | Jan 21 09:11:25 PM PST 24 | 9305418244 ps | ||
| T337 | /workspace/coverage/default/42.rom_ctrl_stress_all.1027266477 | Jan 21 09:10:07 PM PST 24 | Jan 21 09:11:08 PM PST 24 | 31686399206 ps | ||
| T338 | /workspace/coverage/default/42.rom_ctrl_smoke.3772046977 | Jan 21 09:10:05 PM PST 24 | Jan 21 09:10:52 PM PST 24 | 6718262648 ps | ||
| T339 | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1894019487 | Jan 21 09:06:41 PM PST 24 | Jan 21 09:07:17 PM PST 24 | 1816472248 ps | ||
| T340 | /workspace/coverage/default/43.rom_ctrl_smoke.403108411 | Jan 21 09:10:08 PM PST 24 | Jan 21 09:10:49 PM PST 24 | 1817400551 ps | ||
| T341 | /workspace/coverage/default/9.rom_ctrl_smoke.152343336 | Jan 21 09:06:58 PM PST 24 | Jan 21 09:07:24 PM PST 24 | 183068701 ps | ||
| T342 | /workspace/coverage/default/33.rom_ctrl_smoke.2289863252 | Jan 21 09:09:00 PM PST 24 | Jan 21 09:09:35 PM PST 24 | 2088516430 ps | ||
| T343 | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1599253560 | Jan 21 09:07:31 PM PST 24 | Jan 21 09:08:00 PM PST 24 | 1382052328 ps | ||
| T344 | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4196325271 | Jan 21 09:10:26 PM PST 24 | Jan 21 09:13:16 PM PST 24 | 14177300026 ps | ||
| T345 | /workspace/coverage/default/5.rom_ctrl_smoke.2029169582 | Jan 21 09:06:43 PM PST 24 | Jan 21 09:07:36 PM PST 24 | 4080284675 ps | ||
| T49 | /workspace/coverage/default/3.rom_ctrl_sec_cm.3671677060 | Jan 21 09:06:33 PM PST 24 | Jan 21 09:08:34 PM PST 24 | 1082867151 ps | ||
| T346 | /workspace/coverage/default/11.rom_ctrl_stress_all.1926017148 | Jan 21 09:07:25 PM PST 24 | Jan 21 09:08:18 PM PST 24 | 3699592384 ps | ||
| T347 | /workspace/coverage/default/1.rom_ctrl_smoke.2873993922 | Jan 21 09:06:16 PM PST 24 | Jan 21 09:07:05 PM PST 24 | 2157824661 ps | ||
| T348 | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.639032216 | Jan 21 09:10:16 PM PST 24 | Jan 21 09:10:50 PM PST 24 | 1520650487 ps | ||
| T349 | /workspace/coverage/default/17.rom_ctrl_alert_test.2718786881 | Jan 21 09:07:40 PM PST 24 | Jan 21 09:08:08 PM PST 24 | 1873704495 ps | ||
| T350 | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3425309062 | Jan 21 09:07:42 PM PST 24 | Jan 21 09:14:31 PM PST 24 | 60990036849 ps | ||
| T351 | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2039988860 | Jan 21 09:06:15 PM PST 24 | Jan 21 09:07:02 PM PST 24 | 20343899910 ps | ||
| T352 | /workspace/coverage/default/5.rom_ctrl_stress_all.3986309329 | Jan 21 09:06:41 PM PST 24 | Jan 21 09:07:29 PM PST 24 | 6289770564 ps | ||
| T353 | /workspace/coverage/default/47.rom_ctrl_alert_test.1030275247 | Jan 21 09:46:05 PM PST 24 | Jan 21 09:46:31 PM PST 24 | 5119569273 ps | ||
| T354 | /workspace/coverage/default/28.rom_ctrl_stress_all.613748793 | Jan 21 09:08:44 PM PST 24 | Jan 21 09:09:31 PM PST 24 | 22418820750 ps | ||
| T355 | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2353259128 | Jan 21 09:07:36 PM PST 24 | Jan 21 09:17:40 PM PST 24 | 112265841375 ps | ||
| T356 | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1999949780 | Jan 21 09:07:52 PM PST 24 | Jan 21 09:11:46 PM PST 24 | 71191492961 ps | ||
| T357 | /workspace/coverage/default/18.rom_ctrl_alert_test.4002685820 | Jan 21 09:07:54 PM PST 24 | Jan 21 09:08:24 PM PST 24 | 3730152734 ps | ||
| T358 | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2511136239 | Jan 21 09:07:35 PM PST 24 | Jan 21 09:16:54 PM PST 24 | 206690834275 ps | ||
| T359 | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.678229217 | Jan 21 09:06:29 PM PST 24 | Jan 21 09:10:03 PM PST 24 | 35557342471 ps | ||
| T360 | /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3838454220 | Jan 21 09:08:49 PM PST 24 | Jan 21 09:28:57 PM PST 24 | 18965152906 ps | ||
| T361 | /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1980996269 | Jan 21 09:55:13 PM PST 24 | Jan 22 12:49:10 AM PST 24 | 144571309650 ps | ||
| T362 | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1068567975 | Jan 21 09:06:15 PM PST 24 | Jan 21 09:10:12 PM PST 24 | 93345723302 ps | ||
| T363 | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4102424532 | Jan 21 09:08:49 PM PST 24 | Jan 21 09:09:20 PM PST 24 | 4867049837 ps | ||
| T364 | /workspace/coverage/default/37.rom_ctrl_stress_all.3883689418 | Jan 21 09:09:19 PM PST 24 | Jan 21 09:10:14 PM PST 24 | 4744285693 ps | ||
| T365 | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4030084856 | Jan 21 09:07:25 PM PST 24 | Jan 21 09:07:50 PM PST 24 | 5186133127 ps | ||
| T366 | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2599567877 | Jan 21 09:06:53 PM PST 24 | Jan 21 09:07:36 PM PST 24 | 11001159326 ps | ||
| T367 | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3052735078 | Jan 21 10:22:27 PM PST 24 | Jan 21 10:28:14 PM PST 24 | 76899795490 ps | ||
| T368 | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2238177635 | Jan 21 09:09:35 PM PST 24 | Jan 21 09:10:00 PM PST 24 | 2396696034 ps | ||
| T369 | /workspace/coverage/default/37.rom_ctrl_smoke.1373599191 | Jan 21 09:09:18 PM PST 24 | Jan 21 09:09:39 PM PST 24 | 620341124 ps | ||
| T370 | /workspace/coverage/default/14.rom_ctrl_stress_all.3479872953 | Jan 21 09:07:28 PM PST 24 | Jan 21 09:08:58 PM PST 24 | 85032577719 ps | ||
| T371 | /workspace/coverage/default/25.rom_ctrl_stress_all.3847204330 | Jan 21 09:08:23 PM PST 24 | Jan 21 09:09:50 PM PST 24 | 6206061036 ps | ||
| T372 | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.567505230 | Jan 21 09:10:06 PM PST 24 | Jan 21 09:10:34 PM PST 24 | 755235192 ps | ||
| T373 | /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.937448739 | Jan 21 09:09:39 PM PST 24 | Jan 21 09:24:20 PM PST 24 | 76763474006 ps | ||
| T374 | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.611540112 | Jan 21 09:59:06 PM PST 24 | Jan 21 10:03:52 PM PST 24 | 105888175295 ps | ||
| T375 | /workspace/coverage/default/39.rom_ctrl_smoke.4081869614 | Jan 21 09:09:24 PM PST 24 | Jan 21 09:09:52 PM PST 24 | 2567512977 ps | ||
| T376 | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1476523661 | Jan 21 09:07:47 PM PST 24 | Jan 21 09:11:01 PM PST 24 | 13422054852 ps | ||
| T377 | /workspace/coverage/default/13.rom_ctrl_alert_test.224592474 | Jan 21 09:07:33 PM PST 24 | Jan 21 09:07:48 PM PST 24 | 488299864 ps | ||
| T378 | /workspace/coverage/default/7.rom_ctrl_smoke.1136859875 | Jan 21 09:06:47 PM PST 24 | Jan 21 09:07:25 PM PST 24 | 1395937203 ps | ||
| T379 | /workspace/coverage/default/30.rom_ctrl_stress_all.451026756 | Jan 21 09:08:51 PM PST 24 | Jan 21 09:09:15 PM PST 24 | 3813622019 ps | ||
| T380 | /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.602147806 | Jan 21 09:07:33 PM PST 24 | Jan 21 09:33:51 PM PST 24 | 36278056046 ps | ||
| T381 | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2932350658 | Jan 21 09:07:33 PM PST 24 | Jan 21 09:10:04 PM PST 24 | 39134212202 ps | ||
| T382 | /workspace/coverage/default/48.rom_ctrl_smoke.594047056 | Jan 21 09:10:16 PM PST 24 | Jan 21 09:10:46 PM PST 24 | 181180641 ps | ||
| T383 | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3341374482 | Jan 21 09:07:19 PM PST 24 | Jan 21 09:11:42 PM PST 24 | 120518578115 ps | ||
| T384 | /workspace/coverage/default/21.rom_ctrl_alert_test.2039374850 | Jan 21 09:08:14 PM PST 24 | Jan 21 09:08:47 PM PST 24 | 1441571563 ps | ||
| T385 | /workspace/coverage/default/34.rom_ctrl_smoke.2280375067 | Jan 21 09:09:06 PM PST 24 | Jan 21 09:09:38 PM PST 24 | 8586967648 ps | ||
| T386 | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1381395454 | Jan 21 09:51:03 PM PST 24 | Jan 21 09:56:28 PM PST 24 | 388545768610 ps | ||
| T387 | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1870051914 | Jan 21 09:09:08 PM PST 24 | Jan 21 09:09:38 PM PST 24 | 20925443314 ps | ||
| T388 | /workspace/coverage/default/15.rom_ctrl_stress_all.3265925063 | Jan 21 09:07:30 PM PST 24 | Jan 21 09:08:02 PM PST 24 | 391764158 ps | ||
| T389 | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4169650317 | Jan 21 09:07:36 PM PST 24 | Jan 21 09:08:03 PM PST 24 | 3614326547 ps | ||
| T390 | /workspace/coverage/default/23.rom_ctrl_smoke.1962631493 | Jan 21 09:08:13 PM PST 24 | Jan 21 09:09:06 PM PST 24 | 9228958299 ps | ||
| T391 | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1294481908 | Jan 21 09:07:57 PM PST 24 | Jan 21 09:08:32 PM PST 24 | 1686454519 ps | ||
| T392 | /workspace/coverage/default/34.rom_ctrl_alert_test.2413379682 | Jan 21 09:09:13 PM PST 24 | Jan 21 09:09:30 PM PST 24 | 940450969 ps | ||
| T393 | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.403576281 | Jan 21 09:08:01 PM PST 24 | Jan 21 09:08:30 PM PST 24 | 102974402 ps | ||
| T394 | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.247571487 | Jan 21 09:07:33 PM PST 24 | Jan 21 09:08:10 PM PST 24 | 12248405675 ps | ||
| T395 | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2523860504 | Jan 21 09:07:29 PM PST 24 | Jan 21 09:07:46 PM PST 24 | 99355699 ps | ||
| T396 | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2694065681 | Jan 21 09:08:09 PM PST 24 | Jan 21 09:10:13 PM PST 24 | 3185416440 ps | ||
| T397 | /workspace/coverage/default/49.rom_ctrl_stress_all.2124965253 | Jan 21 09:10:24 PM PST 24 | Jan 21 09:11:49 PM PST 24 | 24774413257 ps | ||
| T398 | /workspace/coverage/default/39.rom_ctrl_stress_all.2028246375 | Jan 21 10:02:53 PM PST 24 | Jan 21 10:04:28 PM PST 24 | 14305719180 ps | ||
| T399 | /workspace/coverage/default/24.rom_ctrl_smoke.821433592 | Jan 21 09:08:17 PM PST 24 | Jan 21 09:08:53 PM PST 24 | 188877597 ps | ||
| T400 | /workspace/coverage/default/33.rom_ctrl_stress_all.1043833126 | Jan 21 09:09:04 PM PST 24 | Jan 21 09:09:36 PM PST 24 | 421921865 ps | ||
| T401 | /workspace/coverage/default/15.rom_ctrl_smoke.2064444919 | Jan 21 09:07:35 PM PST 24 | Jan 21 09:08:00 PM PST 24 | 594410553 ps | ||
| T402 | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1179757878 | Jan 21 09:09:02 PM PST 24 | Jan 21 09:15:35 PM PST 24 | 137371301733 ps | ||
| T403 | /workspace/coverage/default/26.rom_ctrl_alert_test.4199455855 | Jan 21 09:08:38 PM PST 24 | Jan 21 09:09:00 PM PST 24 | 489881220 ps | ||
| T404 | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3016663811 | Jan 21 09:10:20 PM PST 24 | Jan 21 09:11:10 PM PST 24 | 12333411436 ps | ||
| T405 | /workspace/coverage/default/7.rom_ctrl_alert_test.1802080744 | Jan 21 09:07:01 PM PST 24 | Jan 21 09:07:24 PM PST 24 | 4823112631 ps | ||
| T406 | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1080088153 | Jan 21 09:09:18 PM PST 24 | Jan 21 09:13:25 PM PST 24 | 90540049603 ps | ||
| T407 | /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3783907443 | Jan 21 09:06:16 PM PST 24 | Jan 21 09:31:28 PM PST 24 | 104148994463 ps | ||
| T408 | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1569264557 | Jan 21 09:10:14 PM PST 24 | Jan 21 09:13:38 PM PST 24 | 13423854402 ps | ||
| T409 | /workspace/coverage/default/41.rom_ctrl_alert_test.3283548048 | Jan 21 09:10:04 PM PST 24 | Jan 21 09:10:39 PM PST 24 | 8694364422 ps | ||
| T410 | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.373620621 | Jan 21 10:35:06 PM PST 24 | Jan 21 10:37:34 PM PST 24 | 7830502548 ps | ||
| T50 | /workspace/coverage/default/4.rom_ctrl_sec_cm.1470202788 | Jan 21 09:06:40 PM PST 24 | Jan 21 09:08:40 PM PST 24 | 856019898 ps | ||
| T411 | /workspace/coverage/default/45.rom_ctrl_alert_test.2639881779 | Jan 21 09:10:14 PM PST 24 | Jan 21 09:10:40 PM PST 24 | 856962555 ps | ||
| T412 | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2972781201 | Jan 21 09:09:48 PM PST 24 | Jan 21 09:10:15 PM PST 24 | 4578091301 ps | ||
| T413 | /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1254168278 | Jan 21 09:07:31 PM PST 24 | Jan 21 09:36:22 PM PST 24 | 49153445460 ps | ||
| T105 | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1387128629 | Jan 21 09:10:25 PM PST 24 | Jan 21 09:10:53 PM PST 24 | 100828494 ps | ||
| T106 | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1983450665 | Jan 21 09:07:32 PM PST 24 | Jan 21 09:07:54 PM PST 24 | 4489936547 ps | ||
| T107 | /workspace/coverage/default/48.rom_ctrl_stress_all.4119334301 | Jan 21 09:10:18 PM PST 24 | Jan 21 09:11:11 PM PST 24 | 19797978074 ps | ||
| T108 | /workspace/coverage/default/27.rom_ctrl_alert_test.1678538832 | Jan 21 09:08:46 PM PST 24 | Jan 21 09:09:09 PM PST 24 | 1636085901 ps | ||
| T109 | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1777756937 | Jan 21 09:06:27 PM PST 24 | Jan 21 09:08:43 PM PST 24 | 1931594530 ps | ||
| T414 | /workspace/coverage/default/44.rom_ctrl_alert_test.367791442 | Jan 21 09:10:14 PM PST 24 | Jan 21 09:10:50 PM PST 24 | 8023562523 ps | ||
| T415 | /workspace/coverage/default/13.rom_ctrl_smoke.91534828 | Jan 21 09:07:34 PM PST 24 | Jan 21 09:07:55 PM PST 24 | 719515818 ps | ||
| T416 | /workspace/coverage/default/8.rom_ctrl_alert_test.72229417 | Jan 21 09:07:00 PM PST 24 | Jan 21 09:07:28 PM PST 24 | 4529658598 ps | ||
| T417 | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1842430745 | Jan 21 09:09:40 PM PST 24 | Jan 21 09:09:53 PM PST 24 | 1283559089 ps | ||
| T418 | /workspace/coverage/default/10.rom_ctrl_alert_test.1404476976 | Jan 21 09:07:21 PM PST 24 | Jan 21 09:07:47 PM PST 24 | 9746449982 ps | ||
| T419 | /workspace/coverage/default/31.rom_ctrl_alert_test.1311293692 | Jan 21 09:08:50 PM PST 24 | Jan 21 09:09:09 PM PST 24 | 2986156661 ps | ||
| T420 | /workspace/coverage/default/31.rom_ctrl_smoke.377349242 | Jan 21 09:08:48 PM PST 24 | Jan 21 09:09:49 PM PST 24 | 17705789514 ps | ||
| T421 | /workspace/coverage/default/22.rom_ctrl_alert_test.1632410961 | Jan 21 09:08:11 PM PST 24 | Jan 21 09:08:52 PM PST 24 | 8075671130 ps | ||
| T422 | /workspace/coverage/default/20.rom_ctrl_smoke.4104590522 | Jan 21 09:07:54 PM PST 24 | Jan 21 09:08:36 PM PST 24 | 1621206080 ps | ||
| T423 | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.229606119 | Jan 21 09:10:17 PM PST 24 | Jan 21 09:13:04 PM PST 24 | 3149160088 ps | ||
| T424 | /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3717989831 | Jan 21 09:10:02 PM PST 24 | Jan 21 09:35:41 PM PST 24 | 76465909496 ps | ||
| T425 | /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1752719580 | Jan 21 09:06:46 PM PST 24 | Jan 21 09:29:25 PM PST 24 | 74128640162 ps | ||
| T426 | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3550180305 | Jan 21 09:08:57 PM PST 24 | Jan 21 09:09:24 PM PST 24 | 6989983992 ps | ||
| T427 | /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3629579795 | Jan 21 10:27:24 PM PST 24 | Jan 21 10:57:22 PM PST 24 | 202403236199 ps | ||
| T428 | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2516144309 | Jan 21 09:06:58 PM PST 24 | Jan 21 09:07:43 PM PST 24 | 6024380653 ps | ||
| T429 | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3188344289 | Jan 21 09:09:36 PM PST 24 | Jan 21 09:09:56 PM PST 24 | 28524220714 ps | ||
| T430 | /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3463250907 | Jan 21 09:09:25 PM PST 24 | Jan 22 12:04:26 AM PST 24 | 342357117221 ps | ||
| T431 | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3808231558 | Jan 21 09:10:03 PM PST 24 | Jan 21 09:10:32 PM PST 24 | 692790989 ps | ||
| T432 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4123015970 | Jan 21 03:02:32 PM PST 24 | Jan 21 03:02:38 PM PST 24 | 377596258 ps | ||
| T433 | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.640919755 | Jan 21 03:02:16 PM PST 24 | Jan 21 03:02:33 PM PST 24 | 901184908 ps | ||
| T434 | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.390952895 | Jan 21 04:00:29 PM PST 24 | Jan 21 04:00:42 PM PST 24 | 5678932568 ps | ||
| T435 | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3939297099 | Jan 21 03:02:55 PM PST 24 | Jan 21 03:03:01 PM PST 24 | 191378216 ps | ||
| T119 | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1441232663 | Jan 21 03:23:12 PM PST 24 | Jan 21 03:24:34 PM PST 24 | 2383440252 ps | ||
| T102 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1174240571 | Jan 21 03:01:45 PM PST 24 | Jan 21 03:02:00 PM PST 24 | 1669017510 ps | ||
| T436 | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.394137545 | Jan 21 03:02:14 PM PST 24 | Jan 21 03:02:33 PM PST 24 | 14164021570 ps | ||
| T437 | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2732404105 | Jan 21 03:01:34 PM PST 24 | Jan 21 03:01:50 PM PST 24 | 6539418253 ps | ||
| T438 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2802918215 | Jan 21 03:02:14 PM PST 24 | Jan 21 03:02:30 PM PST 24 | 2624447468 ps | ||
| T120 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3157602461 | Jan 21 03:02:13 PM PST 24 | Jan 21 03:03:23 PM PST 24 | 309016609 ps | ||
| T439 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1200245835 | Jan 21 03:02:14 PM PST 24 | Jan 21 03:02:33 PM PST 24 | 2987647472 ps | ||
| T98 | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.836471114 | Jan 21 03:02:05 PM PST 24 | Jan 21 03:03:44 PM PST 24 | 7144119193 ps | ||
| T440 | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2318890792 | Jan 21 03:02:34 PM PST 24 | Jan 21 03:02:47 PM PST 24 | 1201918470 ps | ||
| T441 | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1713589618 | Jan 21 03:02:04 PM PST 24 | Jan 21 03:02:12 PM PST 24 | 87419286 ps | ||
| T99 | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.149411214 | Jan 21 03:02:15 PM PST 24 | Jan 21 03:02:30 PM PST 24 | 2772059029 ps | ||
| T121 | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3590708397 | Jan 21 03:01:18 PM PST 24 | Jan 21 03:02:39 PM PST 24 | 1731873127 ps | ||
| T442 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.767708032 | Jan 21 03:01:29 PM PST 24 | Jan 21 03:01:35 PM PST 24 | 252164738 ps | ||
| T443 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.721068322 | Jan 21 03:02:10 PM PST 24 | Jan 21 03:02:17 PM PST 24 | 1099592157 ps | ||
| T122 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1721435982 | Jan 21 03:14:46 PM PST 24 | Jan 21 03:15:29 PM PST 24 | 1018477375 ps | ||
| T103 | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.824977664 | Jan 21 03:02:15 PM PST 24 | Jan 21 03:09:19 PM PST 24 | 41378773529 ps | ||
| T118 | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2068217466 | Jan 21 03:02:10 PM PST 24 | Jan 21 03:02:54 PM PST 24 | 2607141855 ps | ||
| T444 | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1618307352 | Jan 21 03:02:12 PM PST 24 | Jan 21 03:02:20 PM PST 24 | 91409707 ps | ||
| T445 | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4087675161 | Jan 21 03:02:14 PM PST 24 | Jan 21 03:02:22 PM PST 24 | 165408425 ps | ||
| T446 | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.104280075 | Jan 21 03:02:29 PM PST 24 | Jan 21 03:02:45 PM PST 24 | 1735604113 ps | ||
| T447 | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1685639654 | Jan 21 03:01:08 PM PST 24 | Jan 21 03:01:18 PM PST 24 | 127769593 ps | ||
| T448 | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3360138519 | Jan 21 03:01:55 PM PST 24 | Jan 21 03:02:02 PM PST 24 | 175087060 ps | ||
| T449 | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2618552000 | Jan 21 03:02:16 PM PST 24 | Jan 21 03:02:25 PM PST 24 | 87119690 ps | ||
| T117 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.700686483 | Jan 21 03:01:04 PM PST 24 | Jan 21 03:02:30 PM PST 24 | 1842348020 ps | ||
| T450 | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.690735188 | Jan 21 03:01:32 PM PST 24 | Jan 21 03:01:43 PM PST 24 | 6574693134 ps | ||
| T451 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3000438077 | Jan 21 03:01:33 PM PST 24 | Jan 21 03:01:40 PM PST 24 | 1193508810 ps | ||
| T452 | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4205492049 | Jan 21 03:01:34 PM PST 24 | Jan 21 03:01:52 PM PST 24 | 7443950449 ps | ||
| T453 | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4063812704 | Jan 21 03:01:50 PM PST 24 | Jan 21 03:03:12 PM PST 24 | 1687594820 ps | ||
| T104 | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2057941804 | Jan 21 03:02:02 PM PST 24 | Jan 21 03:04:17 PM PST 24 | 74117661587 ps | ||
| T454 | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.628301119 | Jan 21 03:02:02 PM PST 24 | Jan 21 03:02:12 PM PST 24 | 587217584 ps | ||
| T455 | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1617846171 | Jan 21 03:44:31 PM PST 24 | Jan 21 03:44:42 PM PST 24 | 7463651096 ps | ||
| T456 | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2955604686 | Jan 21 03:01:59 PM PST 24 | Jan 21 03:02:15 PM PST 24 | 6814793955 ps | ||
| T457 | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2087914958 | Jan 21 03:02:14 PM PST 24 | Jan 21 03:05:05 PM PST 24 | 137303618260 ps | ||
| T458 | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1600498212 | Jan 21 03:01:59 PM PST 24 | Jan 21 03:02:18 PM PST 24 | 3843612479 ps | ||
| T459 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1673896526 | Jan 21 03:02:21 PM PST 24 | Jan 21 03:02:35 PM PST 24 | 5274142174 ps | ||
| T460 | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3478155941 | Jan 21 03:01:34 PM PST 24 | Jan 21 03:04:25 PM PST 24 | 12184373998 ps | ||
| T461 | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2243019436 | Jan 21 03:01:04 PM PST 24 | Jan 21 03:05:23 PM PST 24 | 110808244633 ps | ||
| T462 | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2976945613 | Jan 21 03:02:00 PM PST 24 | Jan 21 03:02:15 PM PST 24 | 4438924513 ps | ||
| T463 | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1110802968 | Jan 21 03:02:03 PM PST 24 | Jan 21 03:03:53 PM PST 24 | 41653823263 ps | ||
| T464 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.436538772 | Jan 21 03:02:39 PM PST 24 | Jan 21 03:03:24 PM PST 24 | 7172261698 ps | ||
| T465 | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1235237340 | Jan 21 03:02:22 PM PST 24 | Jan 21 03:02:40 PM PST 24 | 4692476813 ps | ||
| T466 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.898297699 | Jan 21 03:01:46 PM PST 24 | Jan 21 03:02:00 PM PST 24 | 92340366 ps | ||
| T467 | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.261384531 | Jan 21 03:01:42 PM PST 24 | Jan 21 03:02:01 PM PST 24 | 473236794 ps | ||
| T468 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.821777304 | Jan 21 03:02:58 PM PST 24 | Jan 21 03:03:11 PM PST 24 | 3903919125 ps | ||
| T469 | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3517473326 | Jan 21 03:02:04 PM PST 24 | Jan 21 03:02:19 PM PST 24 | 1734324890 ps | ||
| T470 | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.660780071 | Jan 21 03:01:16 PM PST 24 | Jan 21 03:04:28 PM PST 24 | 30178921018 ps | ||
| T471 | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.761095834 | Jan 21 03:01:36 PM PST 24 | Jan 21 03:01:42 PM PST 24 | 161838470 ps | ||
| T472 | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3016938073 | Jan 21 03:02:02 PM PST 24 | Jan 21 03:04:44 PM PST 24 | 29257912018 ps | ||
| T473 | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2837479057 | Jan 21 03:02:12 PM PST 24 | Jan 21 03:03:33 PM PST 24 | 4122187249 ps | ||
| T474 | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1701950123 | Jan 21 03:02:48 PM PST 24 | Jan 21 03:03:07 PM PST 24 | 25831168388 ps | ||
| T475 | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2624656107 | Jan 21 03:02:18 PM PST 24 | Jan 21 03:02:33 PM PST 24 | 1347708522 ps | ||
| T476 | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3165984408 | Jan 21 03:02:38 PM PST 24 | Jan 21 03:02:50 PM PST 24 | 1213149372 ps | ||
| T477 | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1510389772 | Jan 21 03:02:20 PM PST 24 | Jan 21 03:02:28 PM PST 24 | 463264148 ps | ||
| T478 | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1624773988 | Jan 21 03:02:40 PM PST 24 | Jan 21 03:03:25 PM PST 24 | 5858360025 ps | ||
| T479 | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4116177806 | Jan 21 03:02:48 PM PST 24 | Jan 21 03:03:05 PM PST 24 | 3438687656 ps | ||
| T480 | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1976142848 | Jan 21 03:01:01 PM PST 24 | Jan 21 03:01:21 PM PST 24 | 5815505646 ps | ||
| T481 | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3788548001 | Jan 21 03:02:38 PM PST 24 | Jan 21 03:02:50 PM PST 24 | 2463908500 ps | ||
| T482 | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4237699932 | Jan 21 03:01:34 PM PST 24 | Jan 21 03:01:43 PM PST 24 | 2123387025 ps |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.544993953 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 389251695 ps |
| CPU time | 4.72 seconds |
| Started | Jan 21 03:01:43 PM PST 24 |
| Finished | Jan 21 03:01:57 PM PST 24 |
| Peak memory | 218864 kb |
| Host | smart-3e03905d-50fb-46ab-a22b-e28d738f6e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544993953 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.544993953 |
| Directory | /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all.1450171384 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1493591190 ps |
| CPU time | 42.51 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:11:16 PM PST 24 |
| Peak memory | 215036 kb |
| Host | smart-1bfc387a-c64a-413a-bce1-ad880b6fa058 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450171384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.rom_ctrl_stress_all.1450171384 |
| Directory | /workspace/46.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.515715770 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 92150472168 ps |
| CPU time | 383.59 seconds |
| Started | Jan 21 03:18:33 PM PST 24 |
| Finished | Jan 21 03:25:01 PM PST 24 |
| Peak memory | 210516 kb |
| Host | smart-6fbe7ce7-095a-4311-86ce-9ee4167cae85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515715770 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pas sthru_mem_tl_intg_err.515715770 |
| Directory | /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2026047158 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 88920392037 ps |
| CPU time | 3645.71 seconds |
| Started | Jan 21 09:30:51 PM PST 24 |
| Finished | Jan 21 10:31:55 PM PST 24 |
| Peak memory | 252432 kb |
| Host | smart-0525dfd7-8b29-4d90-bc88-43ca31496b00 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026047158 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.2026047158 |
| Directory | /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_errors.1175019041 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 4213008130 ps |
| CPU time | 20.83 seconds |
| Started | Jan 21 03:02:03 PM PST 24 |
| Finished | Jan 21 03:02:25 PM PST 24 |
| Peak memory | 218880 kb |
| Host | smart-3cc566c3-1b6b-4703-96eb-85a742affdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175019041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_errors.1175019041 |
| Directory | /workspace/8.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2743783014 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 810088501 ps |
| CPU time | 72.45 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:02:26 PM PST 24 |
| Peak memory | 218728 kb |
| Host | smart-f005bc1f-acc2-4c10-81ca-7f24e29f1e9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743783014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in tg_err.2743783014 |
| Directory | /workspace/1.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.1058028496 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 57357338875 ps |
| CPU time | 183.09 seconds |
| Started | Jan 21 09:41:31 PM PST 24 |
| Finished | Jan 21 09:44:35 PM PST 24 |
| Peak memory | 239572 kb |
| Host | smart-80fb06bf-de3d-425b-a451-a22f84e43acb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058028496 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_ corrupt_sig_fatal_chk.1058028496 |
| Directory | /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_smoke.4283173094 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 3122453809 ps |
| CPU time | 28.21 seconds |
| Started | Jan 21 11:03:58 PM PST 24 |
| Finished | Jan 21 11:04:30 PM PST 24 |
| Peak memory | 213056 kb |
| Host | smart-ca70b176-f9e3-4f73-8711-e608b5a64ea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283173094 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.4283173094 |
| Directory | /workspace/25.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.3157602461 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 309016609 ps |
| CPU time | 67.37 seconds |
| Started | Jan 21 03:02:13 PM PST 24 |
| Finished | Jan 21 03:03:23 PM PST 24 |
| Peak memory | 218132 kb |
| Host | smart-f0aaed7d-d14d-4412-88d7-224d6c847faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157602461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i ntg_err.3157602461 |
| Directory | /workspace/12.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_sec_cm.1703294934 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 203702128 ps |
| CPU time | 99.7 seconds |
| Started | Jan 21 09:06:15 PM PST 24 |
| Finished | Jan 21 09:08:26 PM PST 24 |
| Peak memory | 235852 kb |
| Host | smart-f56384f7-bf6c-4bac-a6f1-d4a543cdb97e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703294934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.1703294934 |
| Directory | /workspace/2.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.629537228 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2808256701 ps |
| CPU time | 66.5 seconds |
| Started | Jan 21 03:02:27 PM PST 24 |
| Finished | Jan 21 03:03:34 PM PST 24 |
| Peak memory | 210696 kb |
| Host | smart-617a8b92-843d-44c8-a95e-894567bd4678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629537228 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa ssthru_mem_tl_intg_err.629537228 |
| Directory | /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.109239622 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4651438293 ps |
| CPU time | 121.83 seconds |
| Started | Jan 21 09:08:18 PM PST 24 |
| Finished | Jan 21 09:10:46 PM PST 24 |
| Peak memory | 228468 kb |
| Host | smart-02f5ce5a-ebf7-4865-9bea-58bcd52c10e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109239622 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_c orrupt_sig_fatal_chk.109239622 |
| Directory | /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1976744783 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2119828581 ps |
| CPU time | 47.21 seconds |
| Started | Jan 21 03:02:05 PM PST 24 |
| Finished | Jan 21 03:02:54 PM PST 24 |
| Peak memory | 218768 kb |
| Host | smart-2355a04b-d3bb-463e-b8a7-a9f940fb0115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976744783 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in tg_err.1976744783 |
| Directory | /workspace/8.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.700686483 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1842348020 ps |
| CPU time | 77.55 seconds |
| Started | Jan 21 03:01:04 PM PST 24 |
| Finished | Jan 21 03:02:30 PM PST 24 |
| Peak memory | 218732 kb |
| Host | smart-594bba15-252d-484c-84cc-8e1439261863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700686483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_int g_err.700686483 |
| Directory | /workspace/0.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3328141443 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1984263906 ps |
| CPU time | 50.14 seconds |
| Started | Jan 21 03:01:23 PM PST 24 |
| Finished | Jan 21 03:02:15 PM PST 24 |
| Peak memory | 218644 kb |
| Host | smart-1304ba77-4fcd-4bdb-b4d0-66cbd5a3c099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328141443 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa ssthru_mem_tl_intg_err.3328141443 |
| Directory | /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.3895498380 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4293866747 ps |
| CPU time | 32.81 seconds |
| Started | Jan 21 09:23:32 PM PST 24 |
| Finished | Jan 21 09:24:16 PM PST 24 |
| Peak memory | 211492 kb |
| Host | smart-fd925d06-9e1f-41c2-8324-009920bc2a19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895498380 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.3895498380 |
| Directory | /workspace/0.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.3561085001 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 184922065 ps |
| CPU time | 9.75 seconds |
| Started | Jan 21 09:07:21 PM PST 24 |
| Finished | Jan 21 09:07:43 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-22279642-f5f6-4549-859e-8a3e28be733a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561085001 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.3561085001 |
| Directory | /workspace/10.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.3342697996 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 8528939201 ps |
| CPU time | 22.02 seconds |
| Started | Jan 21 09:08:00 PM PST 24 |
| Finished | Jan 21 09:08:45 PM PST 24 |
| Peak memory | 211992 kb |
| Host | smart-68f3b743-9ba6-4657-9e8c-225d8b170ff4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3342697996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.3342697996 |
| Directory | /workspace/20.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2399891230 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3280384731 ps |
| CPU time | 14.39 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:49 PM PST 24 |
| Peak memory | 218944 kb |
| Host | smart-3efe7b4d-ad97-45c9-bf82-cf088f6b57df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399891230 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2399891230 |
| Directory | /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_alert_test.1227031840 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 555765288 ps |
| CPU time | 7.73 seconds |
| Started | Jan 21 11:38:44 PM PST 24 |
| Finished | Jan 21 11:38:56 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-3403a953-631c-42d4-a02c-1005f116e6c1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227031840 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.1227031840 |
| Directory | /workspace/0.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2068217466 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2607141855 ps |
| CPU time | 42.88 seconds |
| Started | Jan 21 03:02:10 PM PST 24 |
| Finished | Jan 21 03:02:54 PM PST 24 |
| Peak memory | 218844 kb |
| Host | smart-0134a286-06d5-4c85-bbfc-c5f8884b95d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068217466 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i ntg_err.2068217466 |
| Directory | /workspace/11.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2561648052 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1233626968 ps |
| CPU time | 11.45 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:02:29 PM PST 24 |
| Peak memory | 217496 kb |
| Host | smart-ac5e6242-d09c-4811-b3b6-2bcda4b09ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561648052 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ ctrl_same_csr_outstanding.2561648052 |
| Directory | /workspace/11.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.1387128629 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 100828494 ps |
| CPU time | 5.51 seconds |
| Started | Jan 21 09:10:25 PM PST 24 |
| Finished | Jan 21 09:10:53 PM PST 24 |
| Peak memory | 211528 kb |
| Host | smart-a09cf584-7fd6-40c5-ab77-793078133b4f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1387128629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.1387128629 |
| Directory | /workspace/49.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.2654394685 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 70652697706 ps |
| CPU time | 8114.13 seconds |
| Started | Jan 21 09:07:48 PM PST 24 |
| Finished | Jan 21 11:23:20 PM PST 24 |
| Peak memory | 238552 kb |
| Host | smart-5bda893b-39d5-4e11-8e14-91c9b976085b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654394685 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.2654394685 |
| Directory | /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.3624521723 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 116268993 ps |
| CPU time | 4.26 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:01:18 PM PST 24 |
| Peak memory | 216080 kb |
| Host | smart-bc3731a7-2cd6-4209-bd9b-08c27ba48654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624521723 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia sing.3624521723 |
| Directory | /workspace/0.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.3665036956 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 209233652 ps |
| CPU time | 4.65 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:01:18 PM PST 24 |
| Peak memory | 210552 kb |
| Host | smart-9a53702f-fead-4d20-bc60-37e91a824517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665036956 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_ bash.3665036956 |
| Directory | /workspace/0.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.1528903299 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1069401704 ps |
| CPU time | 9.23 seconds |
| Started | Jan 21 03:01:13 PM PST 24 |
| Finished | Jan 21 03:01:30 PM PST 24 |
| Peak memory | 210552 kb |
| Host | smart-5db350a1-1b15-4888-aac8-b4a7359ac4b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528903299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_r eset.1528903299 |
| Directory | /workspace/0.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.690735188 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 6574693134 ps |
| CPU time | 10.23 seconds |
| Started | Jan 21 03:01:32 PM PST 24 |
| Finished | Jan 21 03:01:43 PM PST 24 |
| Peak memory | 218892 kb |
| Host | smart-86b6902b-17c4-41ba-be51-becbc82062b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690735188 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.690735188 |
| Directory | /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.536652982 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 8533673804 ps |
| CPU time | 10.17 seconds |
| Started | Jan 21 03:01:12 PM PST 24 |
| Finished | Jan 21 03:01:31 PM PST 24 |
| Peak memory | 210608 kb |
| Host | smart-236f1920-5dbb-4714-b54a-f32e089735f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536652982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.536652982 |
| Directory | /workspace/0.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1685639654 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 127769593 ps |
| CPU time | 4.9 seconds |
| Started | Jan 21 03:01:08 PM PST 24 |
| Finished | Jan 21 03:01:18 PM PST 24 |
| Peak memory | 210568 kb |
| Host | smart-6f9f3e00-c595-4593-ad02-b88574016c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685639654 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr l_mem_partial_access.1685639654 |
| Directory | /workspace/0.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2293989909 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 6981712087 ps |
| CPU time | 13.77 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:01:27 PM PST 24 |
| Peak memory | 210580 kb |
| Host | smart-680dd883-0b18-474d-8e73-3b36304631c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293989909 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk .2293989909 |
| Directory | /workspace/0.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.2243019436 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 110808244633 ps |
| CPU time | 251.63 seconds |
| Started | Jan 21 03:01:04 PM PST 24 |
| Finished | Jan 21 03:05:23 PM PST 24 |
| Peak memory | 218724 kb |
| Host | smart-2492ee72-24a9-427f-87d3-11e49af23e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243019436 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa ssthru_mem_tl_intg_err.2243019436 |
| Directory | /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.4110780110 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 671956033 ps |
| CPU time | 10.34 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:01:24 PM PST 24 |
| Peak memory | 210552 kb |
| Host | smart-fa04c02e-9604-45b1-bb86-79f71af0277d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110780110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c trl_same_csr_outstanding.4110780110 |
| Directory | /workspace/0.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1976142848 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 5815505646 ps |
| CPU time | 16.53 seconds |
| Started | Jan 21 03:01:01 PM PST 24 |
| Finished | Jan 21 03:01:21 PM PST 24 |
| Peak memory | 218844 kb |
| Host | smart-9f00d3e2-1f17-4da0-aa20-b86bb5e2b9fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976142848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.1976142848 |
| Directory | /workspace/0.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.2655404987 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 3992240121 ps |
| CPU time | 15.94 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:51 PM PST 24 |
| Peak memory | 210644 kb |
| Host | smart-9e6b394c-c4bf-4f27-b979-87a7a5fbdbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655404987 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia sing.2655404987 |
| Directory | /workspace/1.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3626474825 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 316957655 ps |
| CPU time | 6.29 seconds |
| Started | Jan 21 03:01:22 PM PST 24 |
| Finished | Jan 21 03:01:31 PM PST 24 |
| Peak memory | 210580 kb |
| Host | smart-f3f56f7f-0da6-4ac7-9f17-099d6d8e19f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626474825 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_ bash.3626474825 |
| Directory | /workspace/1.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.581768637 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1995763725 ps |
| CPU time | 10.4 seconds |
| Started | Jan 21 03:01:21 PM PST 24 |
| Finished | Jan 21 03:01:33 PM PST 24 |
| Peak memory | 210580 kb |
| Host | smart-ab3d901b-9ad0-4454-8db1-8c3785dab030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581768637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re set.581768637 |
| Directory | /workspace/1.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.201901032 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 85427129 ps |
| CPU time | 4.3 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:39 PM PST 24 |
| Peak memory | 215824 kb |
| Host | smart-9594ed5f-9dd4-4d6a-a562-5301b71e597d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201901032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.201901032 |
| Directory | /workspace/1.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.4205492049 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 7443950449 ps |
| CPU time | 16.42 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:52 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-128e8173-48ee-4410-aaef-6a2e908be205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205492049 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr l_mem_partial_access.4205492049 |
| Directory | /workspace/1.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.3000438077 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 1193508810 ps |
| CPU time | 5.21 seconds |
| Started | Jan 21 03:01:33 PM PST 24 |
| Finished | Jan 21 03:01:40 PM PST 24 |
| Peak memory | 210464 kb |
| Host | smart-7e3bfbbb-ffd2-44e5-b31d-0d1b305d3d88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000438077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk .3000438077 |
| Directory | /workspace/1.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.660780071 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 30178921018 ps |
| CPU time | 186.92 seconds |
| Started | Jan 21 03:01:16 PM PST 24 |
| Finished | Jan 21 03:04:28 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-a5c47848-4233-4ea8-9bb2-8fd6f9443717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660780071 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pas sthru_mem_tl_intg_err.660780071 |
| Directory | /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.2732404105 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 6539418253 ps |
| CPU time | 14.27 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:50 PM PST 24 |
| Peak memory | 217548 kb |
| Host | smart-e1c5d476-d679-453b-8338-1dc1e45ed2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732404105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_c trl_same_csr_outstanding.2732404105 |
| Directory | /workspace/1.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3677840243 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 2845472065 ps |
| CPU time | 14.89 seconds |
| Started | Jan 21 03:01:09 PM PST 24 |
| Finished | Jan 21 03:01:28 PM PST 24 |
| Peak memory | 218932 kb |
| Host | smart-389c6769-e117-4410-a76d-4cbe2e5dcfc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677840243 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.3677840243 |
| Directory | /workspace/1.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.721068322 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1099592157 ps |
| CPU time | 5.74 seconds |
| Started | Jan 21 03:02:10 PM PST 24 |
| Finished | Jan 21 03:02:17 PM PST 24 |
| Peak memory | 218776 kb |
| Host | smart-fec95242-5d91-4b15-bd75-83f7554a7add |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721068322 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.721068322 |
| Directory | /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.4087675161 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 165408425 ps |
| CPU time | 4.41 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:02:22 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-f4da5b47-2ef8-4cb5-9bb5-5eb4988ac9cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087675161 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.4087675161 |
| Directory | /workspace/10.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.1110802968 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 41653823263 ps |
| CPU time | 109.77 seconds |
| Started | Jan 21 03:02:03 PM PST 24 |
| Finished | Jan 21 03:03:53 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-d97e9cb0-ada6-4fff-881b-9e0e5799fa27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110802968 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p assthru_mem_tl_intg_err.1110802968 |
| Directory | /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.1115730061 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 6363497103 ps |
| CPU time | 14.15 seconds |
| Started | Jan 21 03:02:11 PM PST 24 |
| Finished | Jan 21 03:02:26 PM PST 24 |
| Peak memory | 217944 kb |
| Host | smart-8a0512d6-7af2-4831-a8c1-3640a29839a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115730061 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ ctrl_same_csr_outstanding.1115730061 |
| Directory | /workspace/10.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.2624656107 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1347708522 ps |
| CPU time | 13.01 seconds |
| Started | Jan 21 03:02:18 PM PST 24 |
| Finished | Jan 21 03:02:33 PM PST 24 |
| Peak memory | 218876 kb |
| Host | smart-3bacf67c-0e01-4c7e-8a88-b8d9d3677cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624656107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.2624656107 |
| Directory | /workspace/10.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.122500415 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1704993348 ps |
| CPU time | 45.48 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:03:03 PM PST 24 |
| Peak memory | 218732 kb |
| Host | smart-750f455f-1e0a-4459-8997-fe2cdedd3e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122500415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_in tg_err.122500415 |
| Directory | /workspace/10.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.394137545 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 14164021570 ps |
| CPU time | 15.67 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:02:33 PM PST 24 |
| Peak memory | 218940 kb |
| Host | smart-0ea653d4-0482-47be-b28f-98fbcab36e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394137545 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.394137545 |
| Directory | /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.2324734238 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 211719667 ps |
| CPU time | 5.64 seconds |
| Started | Jan 21 03:02:16 PM PST 24 |
| Finished | Jan 21 03:02:25 PM PST 24 |
| Peak memory | 215904 kb |
| Host | smart-937ecefb-ba25-4789-b9a9-92a305d85024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324734238 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.2324734238 |
| Directory | /workspace/11.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.1858601953 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13205308022 ps |
| CPU time | 138.17 seconds |
| Started | Jan 21 03:02:20 PM PST 24 |
| Finished | Jan 21 03:04:39 PM PST 24 |
| Peak memory | 210516 kb |
| Host | smart-a3e97efc-c771-41b1-8607-ffd52cc83d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858601953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_p assthru_mem_tl_intg_err.1858601953 |
| Directory | /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1200245835 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2987647472 ps |
| CPU time | 15.73 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:02:33 PM PST 24 |
| Peak memory | 218772 kb |
| Host | smart-ed185e41-3438-4f40-a7e6-4f5a50658254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200245835 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1200245835 |
| Directory | /workspace/11.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.1618307352 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 91409707 ps |
| CPU time | 5.11 seconds |
| Started | Jan 21 03:02:12 PM PST 24 |
| Finished | Jan 21 03:02:20 PM PST 24 |
| Peak memory | 218740 kb |
| Host | smart-9e094cdb-33d0-4b5c-b8ac-55f7010cee53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618307352 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.1618307352 |
| Directory | /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.1549886314 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4804588948 ps |
| CPU time | 12.47 seconds |
| Started | Jan 21 03:02:11 PM PST 24 |
| Finished | Jan 21 03:02:25 PM PST 24 |
| Peak memory | 210560 kb |
| Host | smart-c7794f2b-dd90-4edd-b05f-4a3e7a93d3e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549886314 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.1549886314 |
| Directory | /workspace/12.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.2837479057 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 4122187249 ps |
| CPU time | 78.23 seconds |
| Started | Jan 21 03:02:12 PM PST 24 |
| Finished | Jan 21 03:03:33 PM PST 24 |
| Peak memory | 210648 kb |
| Host | smart-6ee6c4d5-5390-4a2f-a761-863031d27b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837479057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_p assthru_mem_tl_intg_err.2837479057 |
| Directory | /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3065182292 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 93143710 ps |
| CPU time | 6 seconds |
| Started | Jan 21 03:02:15 PM PST 24 |
| Finished | Jan 21 03:02:25 PM PST 24 |
| Peak memory | 216612 kb |
| Host | smart-2c55ce80-176d-4640-8602-774765e1e6e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065182292 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ ctrl_same_csr_outstanding.3065182292 |
| Directory | /workspace/12.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2618552000 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 87119690 ps |
| CPU time | 6.44 seconds |
| Started | Jan 21 03:02:16 PM PST 24 |
| Finished | Jan 21 03:02:25 PM PST 24 |
| Peak memory | 213220 kb |
| Host | smart-93f7f12f-5b25-4609-80c2-29885ac65ff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618552000 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_errors.2618552000 |
| Directory | /workspace/12.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.2802918215 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2624447468 ps |
| CPU time | 12.23 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:02:30 PM PST 24 |
| Peak memory | 218756 kb |
| Host | smart-5a3c73f5-3e61-4bf9-8ecf-f82f26df232b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802918215 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.2802918215 |
| Directory | /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.149411214 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2772059029 ps |
| CPU time | 12.58 seconds |
| Started | Jan 21 03:02:15 PM PST 24 |
| Finished | Jan 21 03:02:30 PM PST 24 |
| Peak memory | 210548 kb |
| Host | smart-f1a4c407-b392-4078-b293-9235705ea60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149411214 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.149411214 |
| Directory | /workspace/13.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2087914958 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 137303618260 ps |
| CPU time | 167.72 seconds |
| Started | Jan 21 03:02:14 PM PST 24 |
| Finished | Jan 21 03:05:05 PM PST 24 |
| Peak memory | 210624 kb |
| Host | smart-8bd71df1-0a3a-4f81-9ee5-8cdf532d0eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087914958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p assthru_mem_tl_intg_err.2087914958 |
| Directory | /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.730898999 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1202275661 ps |
| CPU time | 12.09 seconds |
| Started | Jan 21 03:02:20 PM PST 24 |
| Finished | Jan 21 03:02:33 PM PST 24 |
| Peak memory | 217116 kb |
| Host | smart-89b9f885-1318-4529-bdbd-f2ccd4b267a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730898999 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_c trl_same_csr_outstanding.730898999 |
| Directory | /workspace/13.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.640919755 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 901184908 ps |
| CPU time | 13.98 seconds |
| Started | Jan 21 03:02:16 PM PST 24 |
| Finished | Jan 21 03:02:33 PM PST 24 |
| Peak memory | 218860 kb |
| Host | smart-57b52d0a-9a4e-4612-82fe-a4636241d8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640919755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.640919755 |
| Directory | /workspace/13.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.1637494810 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2109371328 ps |
| CPU time | 41.76 seconds |
| Started | Jan 21 03:02:13 PM PST 24 |
| Finished | Jan 21 03:02:58 PM PST 24 |
| Peak memory | 218704 kb |
| Host | smart-7a834374-c9ea-4a11-9c7a-b4af882ea08b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637494810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i ntg_err.1637494810 |
| Directory | /workspace/13.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1235237340 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4692476813 ps |
| CPU time | 16.82 seconds |
| Started | Jan 21 03:02:22 PM PST 24 |
| Finished | Jan 21 03:02:40 PM PST 24 |
| Peak memory | 218952 kb |
| Host | smart-e3abfa73-19e2-46ba-90d4-1cd398655858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235237340 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1235237340 |
| Directory | /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1673896526 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 5274142174 ps |
| CPU time | 11.83 seconds |
| Started | Jan 21 03:02:21 PM PST 24 |
| Finished | Jan 21 03:02:35 PM PST 24 |
| Peak memory | 210480 kb |
| Host | smart-76f0f194-0eff-4a95-9dc8-493c228cf95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673896526 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1673896526 |
| Directory | /workspace/14.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.824977664 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 41378773529 ps |
| CPU time | 419.74 seconds |
| Started | Jan 21 03:02:15 PM PST 24 |
| Finished | Jan 21 03:09:19 PM PST 24 |
| Peak memory | 210672 kb |
| Host | smart-e9e002d0-71f9-42ad-8ba6-3fcf22386dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824977664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_pa ssthru_mem_tl_intg_err.824977664 |
| Directory | /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1617846171 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 7463651096 ps |
| CPU time | 10.19 seconds |
| Started | Jan 21 03:44:31 PM PST 24 |
| Finished | Jan 21 03:44:42 PM PST 24 |
| Peak memory | 217580 kb |
| Host | smart-b94468dd-32d1-43da-8c01-5a21b49aaf16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617846171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ ctrl_same_csr_outstanding.1617846171 |
| Directory | /workspace/14.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1510389772 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 463264148 ps |
| CPU time | 6.36 seconds |
| Started | Jan 21 03:02:20 PM PST 24 |
| Finished | Jan 21 03:02:28 PM PST 24 |
| Peak memory | 218744 kb |
| Host | smart-0686cc05-f8cb-4e82-af59-7bd9e6a63d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510389772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.1510389772 |
| Directory | /workspace/14.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.727079254 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 347760468 ps |
| CPU time | 71.67 seconds |
| Started | Jan 21 03:02:18 PM PST 24 |
| Finished | Jan 21 03:03:32 PM PST 24 |
| Peak memory | 218124 kb |
| Host | smart-f5d755a1-9791-497b-8d39-0eb084443ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727079254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_in tg_err.727079254 |
| Directory | /workspace/14.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.104280075 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1735604113 ps |
| CPU time | 15.6 seconds |
| Started | Jan 21 03:02:29 PM PST 24 |
| Finished | Jan 21 03:02:45 PM PST 24 |
| Peak memory | 218848 kb |
| Host | smart-a9a91b41-9c2b-485b-81b1-a34077bd17c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104280075 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.104280075 |
| Directory | /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.975916028 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1834426045 ps |
| CPU time | 10.06 seconds |
| Started | Jan 21 03:02:17 PM PST 24 |
| Finished | Jan 21 03:02:30 PM PST 24 |
| Peak memory | 217064 kb |
| Host | smart-aeb154f8-0662-4a1d-9fdb-9ae758bc59c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975916028 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.975916028 |
| Directory | /workspace/15.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.697520401 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1413809136 ps |
| CPU time | 14.42 seconds |
| Started | Jan 21 03:02:29 PM PST 24 |
| Finished | Jan 21 03:02:44 PM PST 24 |
| Peak memory | 217624 kb |
| Host | smart-233d4366-10bd-4ada-9d45-ba56b678cb88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697520401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_c trl_same_csr_outstanding.697520401 |
| Directory | /workspace/15.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.256472642 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4389985967 ps |
| CPU time | 19.13 seconds |
| Started | Jan 21 03:02:21 PM PST 24 |
| Finished | Jan 21 03:02:42 PM PST 24 |
| Peak memory | 218812 kb |
| Host | smart-1bcd2445-71cf-40ea-bfdb-439af970be73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256472642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.256472642 |
| Directory | /workspace/15.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1441232663 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2383440252 ps |
| CPU time | 80.98 seconds |
| Started | Jan 21 03:23:12 PM PST 24 |
| Finished | Jan 21 03:24:34 PM PST 24 |
| Peak memory | 218836 kb |
| Host | smart-d62a89a7-1055-4052-b5d3-a29d6413d10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441232663 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i ntg_err.1441232663 |
| Directory | /workspace/15.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.3788548001 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2463908500 ps |
| CPU time | 11.96 seconds |
| Started | Jan 21 03:02:38 PM PST 24 |
| Finished | Jan 21 03:02:50 PM PST 24 |
| Peak memory | 218932 kb |
| Host | smart-a0d31d88-3e0e-4437-b3ea-fb8f752296d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788548001 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.3788548001 |
| Directory | /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.4123015970 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 377596258 ps |
| CPU time | 4.16 seconds |
| Started | Jan 21 03:02:32 PM PST 24 |
| Finished | Jan 21 03:02:38 PM PST 24 |
| Peak memory | 215996 kb |
| Host | smart-cfe45ff6-51de-40fb-95c1-d9eadc1b7477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123015970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.4123015970 |
| Directory | /workspace/16.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.2454901887 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 97881030 ps |
| CPU time | 4.37 seconds |
| Started | Jan 21 03:21:50 PM PST 24 |
| Finished | Jan 21 03:22:02 PM PST 24 |
| Peak memory | 216548 kb |
| Host | smart-d762a20e-e638-4a05-8cb1-2ec24370c6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454901887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ ctrl_same_csr_outstanding.2454901887 |
| Directory | /workspace/16.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.332696887 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 377694608 ps |
| CPU time | 7.18 seconds |
| Started | Jan 21 03:02:28 PM PST 24 |
| Finished | Jan 21 03:02:36 PM PST 24 |
| Peak memory | 218864 kb |
| Host | smart-b64b505a-ca9e-498b-9603-2888f28fe042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332696887 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.332696887 |
| Directory | /workspace/16.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.11729690 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2454518722 ps |
| CPU time | 42.85 seconds |
| Started | Jan 21 03:15:55 PM PST 24 |
| Finished | Jan 21 03:16:42 PM PST 24 |
| Peak memory | 218804 kb |
| Host | smart-7123eed3-b734-47fb-a12b-7d492df28b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11729690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_int g_err.11729690 |
| Directory | /workspace/16.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.4116177806 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3438687656 ps |
| CPU time | 15.42 seconds |
| Started | Jan 21 03:02:48 PM PST 24 |
| Finished | Jan 21 03:03:05 PM PST 24 |
| Peak memory | 218828 kb |
| Host | smart-6cc7da83-5ddf-4d1e-95bb-b58a44014aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116177806 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.4116177806 |
| Directory | /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.3998009281 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4263303729 ps |
| CPU time | 15.74 seconds |
| Started | Jan 21 03:02:37 PM PST 24 |
| Finished | Jan 21 03:02:53 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-47ec9df1-d95f-4f17-8c5d-2450afaa44ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998009281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.3998009281 |
| Directory | /workspace/17.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.451790053 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 19108104040 ps |
| CPU time | 80.29 seconds |
| Started | Jan 21 03:02:48 PM PST 24 |
| Finished | Jan 21 03:04:08 PM PST 24 |
| Peak memory | 218676 kb |
| Host | smart-243111d1-e983-4672-b2b5-8fd8fe15d1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451790053 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa ssthru_mem_tl_intg_err.451790053 |
| Directory | /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.3165984408 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1213149372 ps |
| CPU time | 11.64 seconds |
| Started | Jan 21 03:02:38 PM PST 24 |
| Finished | Jan 21 03:02:50 PM PST 24 |
| Peak memory | 210576 kb |
| Host | smart-abe72244-159f-4343-aaaa-9f388f4519f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165984408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ ctrl_same_csr_outstanding.3165984408 |
| Directory | /workspace/17.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1701950123 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 25831168388 ps |
| CPU time | 18.08 seconds |
| Started | Jan 21 03:02:48 PM PST 24 |
| Finished | Jan 21 03:03:07 PM PST 24 |
| Peak memory | 218820 kb |
| Host | smart-2e15f4ad-607c-4e08-af14-238b5fbb19bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701950123 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.1701950123 |
| Directory | /workspace/17.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.436538772 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 7172261698 ps |
| CPU time | 45.12 seconds |
| Started | Jan 21 03:02:39 PM PST 24 |
| Finished | Jan 21 03:03:24 PM PST 24 |
| Peak memory | 218872 kb |
| Host | smart-a3f800db-2a4c-4d4a-a252-572ae30e9671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436538772 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_in tg_err.436538772 |
| Directory | /workspace/17.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.3081817557 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1569418138 ps |
| CPU time | 7.01 seconds |
| Started | Jan 21 03:02:36 PM PST 24 |
| Finished | Jan 21 03:02:44 PM PST 24 |
| Peak memory | 218740 kb |
| Host | smart-143fc4f4-7034-4852-be40-fc16d643cb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081817557 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.3081817557 |
| Directory | /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.3966356827 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 789681636 ps |
| CPU time | 9.12 seconds |
| Started | Jan 21 03:02:37 PM PST 24 |
| Finished | Jan 21 03:02:47 PM PST 24 |
| Peak memory | 216960 kb |
| Host | smart-98d78d43-ad0f-41c9-830d-3e44c55a1f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966356827 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.3966356827 |
| Directory | /workspace/18.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.1448722425 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 35226255866 ps |
| CPU time | 363.18 seconds |
| Started | Jan 21 03:02:37 PM PST 24 |
| Finished | Jan 21 03:08:41 PM PST 24 |
| Peak memory | 218624 kb |
| Host | smart-801069eb-965a-4c88-923d-8579d96bdbcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448722425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p assthru_mem_tl_intg_err.1448722425 |
| Directory | /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2318890792 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1201918470 ps |
| CPU time | 11.58 seconds |
| Started | Jan 21 03:02:34 PM PST 24 |
| Finished | Jan 21 03:02:47 PM PST 24 |
| Peak memory | 210612 kb |
| Host | smart-4f880d35-ec34-4350-91b2-078fd6103be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318890792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ ctrl_same_csr_outstanding.2318890792 |
| Directory | /workspace/18.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.821777304 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3903919125 ps |
| CPU time | 12.79 seconds |
| Started | Jan 21 03:02:58 PM PST 24 |
| Finished | Jan 21 03:03:11 PM PST 24 |
| Peak memory | 218892 kb |
| Host | smart-10c26de0-c29b-44eb-b1a1-2631f70ff932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821777304 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.821777304 |
| Directory | /workspace/18.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1624773988 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 5858360025 ps |
| CPU time | 44.4 seconds |
| Started | Jan 21 03:02:40 PM PST 24 |
| Finished | Jan 21 03:03:25 PM PST 24 |
| Peak memory | 218780 kb |
| Host | smart-dc8e1ad7-545a-42d7-994a-990f32c03cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624773988 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i ntg_err.1624773988 |
| Directory | /workspace/18.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.3939297099 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 191378216 ps |
| CPU time | 4.88 seconds |
| Started | Jan 21 03:02:55 PM PST 24 |
| Finished | Jan 21 03:03:01 PM PST 24 |
| Peak memory | 218796 kb |
| Host | smart-82b6a270-45f4-431f-907b-003bd2e31729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939297099 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.3939297099 |
| Directory | /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.3138715082 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 7231187049 ps |
| CPU time | 15.96 seconds |
| Started | Jan 21 04:26:21 PM PST 24 |
| Finished | Jan 21 04:26:40 PM PST 24 |
| Peak memory | 217468 kb |
| Host | smart-7dd10f80-e7dd-4e34-8052-6f7dcedb2a3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138715082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.3138715082 |
| Directory | /workspace/19.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.2363047940 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 19931211368 ps |
| CPU time | 127.77 seconds |
| Started | Jan 21 03:02:45 PM PST 24 |
| Finished | Jan 21 03:04:53 PM PST 24 |
| Peak memory | 218672 kb |
| Host | smart-cdb3f7e9-d448-42be-a877-8de9f7373838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363047940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p assthru_mem_tl_intg_err.2363047940 |
| Directory | /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.3880966997 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 1158442431 ps |
| CPU time | 13.03 seconds |
| Started | Jan 21 03:02:55 PM PST 24 |
| Finished | Jan 21 03:03:08 PM PST 24 |
| Peak memory | 210632 kb |
| Host | smart-e13bd84a-48f3-4472-9149-61333399c38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880966997 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ ctrl_same_csr_outstanding.3880966997 |
| Directory | /workspace/19.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.1061773337 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1808348344 ps |
| CPU time | 16.94 seconds |
| Started | Jan 21 03:02:58 PM PST 24 |
| Finished | Jan 21 03:03:16 PM PST 24 |
| Peak memory | 218824 kb |
| Host | smart-78938100-f606-4b95-ab9a-b0059114acce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061773337 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.1061773337 |
| Directory | /workspace/19.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1615901150 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 909669748 ps |
| CPU time | 40.9 seconds |
| Started | Jan 21 03:02:50 PM PST 24 |
| Finished | Jan 21 03:03:32 PM PST 24 |
| Peak memory | 210976 kb |
| Host | smart-b7ad5222-af1b-472a-bd76-c2630c62b784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615901150 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i ntg_err.1615901150 |
| Directory | /workspace/19.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.767708032 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 252164738 ps |
| CPU time | 5.95 seconds |
| Started | Jan 21 03:01:29 PM PST 24 |
| Finished | Jan 21 03:01:35 PM PST 24 |
| Peak memory | 216588 kb |
| Host | smart-35614d3b-8e1e-4807-9eaa-262771e6948f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767708032 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alias ing.767708032 |
| Directory | /workspace/2.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.761095834 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 161838470 ps |
| CPU time | 4.41 seconds |
| Started | Jan 21 03:01:36 PM PST 24 |
| Finished | Jan 21 03:01:42 PM PST 24 |
| Peak memory | 210584 kb |
| Host | smart-d77a9734-d5ae-4a5d-aee1-dfd1871be1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761095834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_b ash.761095834 |
| Directory | /workspace/2.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1174240571 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1669017510 ps |
| CPU time | 6.76 seconds |
| Started | Jan 21 03:01:45 PM PST 24 |
| Finished | Jan 21 03:02:00 PM PST 24 |
| Peak memory | 210500 kb |
| Host | smart-9f38ffef-927c-432f-ac1f-619b6c58e778 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174240571 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r eset.1174240571 |
| Directory | /workspace/2.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2006602453 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 175453679 ps |
| CPU time | 4.19 seconds |
| Started | Jan 21 03:13:31 PM PST 24 |
| Finished | Jan 21 03:13:36 PM PST 24 |
| Peak memory | 215708 kb |
| Host | smart-c409d901-f444-4952-8d79-89049617949e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006602453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.2006602453 |
| Directory | /workspace/2.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.3664464657 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 892504051 ps |
| CPU time | 4.93 seconds |
| Started | Jan 21 03:01:29 PM PST 24 |
| Finished | Jan 21 03:01:34 PM PST 24 |
| Peak memory | 210540 kb |
| Host | smart-6a05a8ca-834f-425d-832c-fe534de4b686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664464657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr l_mem_partial_access.3664464657 |
| Directory | /workspace/2.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3780807755 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1276820957 ps |
| CPU time | 11.44 seconds |
| Started | Jan 21 03:01:23 PM PST 24 |
| Finished | Jan 21 03:01:36 PM PST 24 |
| Peak memory | 210400 kb |
| Host | smart-0a1c5699-1d50-46e6-a817-efe975bf0a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780807755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk .3780807755 |
| Directory | /workspace/2.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1139121853 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1221769251 ps |
| CPU time | 11.31 seconds |
| Started | Jan 21 03:01:36 PM PST 24 |
| Finished | Jan 21 03:01:49 PM PST 24 |
| Peak memory | 210640 kb |
| Host | smart-ac5739cb-0fb5-471e-aa45-ca4fe85f0f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139121853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c trl_same_csr_outstanding.1139121853 |
| Directory | /workspace/2.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.2237664934 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 1090428206 ps |
| CPU time | 12.46 seconds |
| Started | Jan 21 03:01:23 PM PST 24 |
| Finished | Jan 21 03:01:37 PM PST 24 |
| Peak memory | 218756 kb |
| Host | smart-96f2289b-c0c1-46c4-9a14-af21f0c2b9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237664934 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.2237664934 |
| Directory | /workspace/2.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.3590708397 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 1731873127 ps |
| CPU time | 77.52 seconds |
| Started | Jan 21 03:01:18 PM PST 24 |
| Finished | Jan 21 03:02:39 PM PST 24 |
| Peak memory | 218748 kb |
| Host | smart-5998ad8b-d332-424a-b181-edc412259e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590708397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in tg_err.3590708397 |
| Directory | /workspace/2.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.4237699932 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2123387025 ps |
| CPU time | 7.98 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:01:43 PM PST 24 |
| Peak memory | 210568 kb |
| Host | smart-47aba8a4-c698-460a-9672-e3ccc457dd3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237699932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia sing.4237699932 |
| Directory | /workspace/3.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.3077693269 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 515587179 ps |
| CPU time | 6.23 seconds |
| Started | Jan 21 03:01:36 PM PST 24 |
| Finished | Jan 21 03:01:44 PM PST 24 |
| Peak memory | 210580 kb |
| Host | smart-bc501e5f-f02a-47ea-b6ca-cb4e81279ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077693269 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_ bash.3077693269 |
| Directory | /workspace/3.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.898297699 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 92340366 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 03:01:46 PM PST 24 |
| Finished | Jan 21 03:02:00 PM PST 24 |
| Peak memory | 210556 kb |
| Host | smart-45e09ab1-7dae-48b8-98fe-0ca85058d1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898297699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_re set.898297699 |
| Directory | /workspace/3.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.952148964 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1869650034 ps |
| CPU time | 15.51 seconds |
| Started | Jan 21 03:01:32 PM PST 24 |
| Finished | Jan 21 03:01:49 PM PST 24 |
| Peak memory | 218852 kb |
| Host | smart-3f1c1d62-e515-49c0-8519-624e80786774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952148964 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.952148964 |
| Directory | /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.1183553213 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 463327026 ps |
| CPU time | 7.18 seconds |
| Started | Jan 21 03:01:35 PM PST 24 |
| Finished | Jan 21 03:01:43 PM PST 24 |
| Peak memory | 210424 kb |
| Host | smart-158a306f-c5a2-4c1e-9dbe-479833eae6dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183553213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.1183553213 |
| Directory | /workspace/3.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.1084250305 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 171710894 ps |
| CPU time | 4.08 seconds |
| Started | Jan 21 03:15:52 PM PST 24 |
| Finished | Jan 21 03:16:02 PM PST 24 |
| Peak memory | 210528 kb |
| Host | smart-0751eb64-2e73-4c21-8458-9793a989590d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084250305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr l_mem_partial_access.1084250305 |
| Directory | /workspace/3.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.2310328587 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1296578394 ps |
| CPU time | 12.19 seconds |
| Started | Jan 21 03:01:46 PM PST 24 |
| Finished | Jan 21 03:02:05 PM PST 24 |
| Peak memory | 210484 kb |
| Host | smart-811051dd-d7ce-4050-9374-54e8b1d95c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310328587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk .2310328587 |
| Directory | /workspace/3.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3478155941 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 12184373998 ps |
| CPU time | 170.31 seconds |
| Started | Jan 21 03:01:34 PM PST 24 |
| Finished | Jan 21 03:04:25 PM PST 24 |
| Peak memory | 218704 kb |
| Host | smart-af603279-2bb1-4b5c-a9e5-ff1a8fb67e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478155941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_pa ssthru_mem_tl_intg_err.3478155941 |
| Directory | /workspace/3.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1028821423 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5586636977 ps |
| CPU time | 14.52 seconds |
| Started | Jan 21 03:01:37 PM PST 24 |
| Finished | Jan 21 03:01:52 PM PST 24 |
| Peak memory | 217784 kb |
| Host | smart-6721f8a3-e9f0-4251-a905-c4e2229ca725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028821423 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c trl_same_csr_outstanding.1028821423 |
| Directory | /workspace/3.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.261384531 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 473236794 ps |
| CPU time | 8.61 seconds |
| Started | Jan 21 03:01:42 PM PST 24 |
| Finished | Jan 21 03:02:01 PM PST 24 |
| Peak memory | 218864 kb |
| Host | smart-801e656d-7452-457b-a5e4-0a366a001d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261384531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.261384531 |
| Directory | /workspace/3.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.1721435982 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1018477375 ps |
| CPU time | 42.23 seconds |
| Started | Jan 21 03:14:46 PM PST 24 |
| Finished | Jan 21 03:15:29 PM PST 24 |
| Peak memory | 217924 kb |
| Host | smart-175d317a-96ec-45d3-a1f8-8bcdb3e734ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721435982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in tg_err.1721435982 |
| Directory | /workspace/3.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.2179051789 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 332661478 ps |
| CPU time | 4.22 seconds |
| Started | Jan 21 03:09:43 PM PST 24 |
| Finished | Jan 21 03:09:48 PM PST 24 |
| Peak memory | 210764 kb |
| Host | smart-c0ef6631-4e27-4a7c-8486-4195c3a4efae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179051789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia sing.2179051789 |
| Directory | /workspace/4.rom_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.2989797701 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 334708841 ps |
| CPU time | 6.78 seconds |
| Started | Jan 21 03:01:54 PM PST 24 |
| Finished | Jan 21 03:02:04 PM PST 24 |
| Peak memory | 210468 kb |
| Host | smart-81aa3a22-1e38-44b5-99b5-dc7c21262352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989797701 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_ bash.2989797701 |
| Directory | /workspace/4.rom_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1600498212 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3843612479 ps |
| CPU time | 17.01 seconds |
| Started | Jan 21 03:01:59 PM PST 24 |
| Finished | Jan 21 03:02:18 PM PST 24 |
| Peak memory | 210644 kb |
| Host | smart-c70db0e1-3202-44df-83dd-3a1b79a2d642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600498212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r eset.1600498212 |
| Directory | /workspace/4.rom_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3381046709 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2733960747 ps |
| CPU time | 15.34 seconds |
| Started | Jan 21 03:01:45 PM PST 24 |
| Finished | Jan 21 03:02:08 PM PST 24 |
| Peak memory | 218952 kb |
| Host | smart-17d3e7c1-657c-4757-89ad-dfd015906d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381046709 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.3381046709 |
| Directory | /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.1313457055 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 204413152 ps |
| CPU time | 4.27 seconds |
| Started | Jan 21 03:17:24 PM PST 24 |
| Finished | Jan 21 03:17:29 PM PST 24 |
| Peak memory | 215732 kb |
| Host | smart-79be5a40-47fb-4aab-a08d-a1a7b04e4439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313457055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.1313457055 |
| Directory | /workspace/4.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.718627769 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6790376158 ps |
| CPU time | 15.08 seconds |
| Started | Jan 21 03:01:55 PM PST 24 |
| Finished | Jan 21 03:02:13 PM PST 24 |
| Peak memory | 210532 kb |
| Host | smart-f4772de4-8166-4680-b23a-41f84b88392c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718627769 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl _mem_partial_access.718627769 |
| Directory | /workspace/4.rom_ctrl_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.2976945613 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 4438924513 ps |
| CPU time | 12.87 seconds |
| Started | Jan 21 03:02:00 PM PST 24 |
| Finished | Jan 21 03:02:15 PM PST 24 |
| Peak memory | 210576 kb |
| Host | smart-005c318c-b65c-4352-a101-431ef05e511e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976945613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk .2976945613 |
| Directory | /workspace/4.rom_ctrl_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.754691072 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 21657363534 ps |
| CPU time | 235.75 seconds |
| Started | Jan 21 03:01:37 PM PST 24 |
| Finished | Jan 21 03:05:34 PM PST 24 |
| Peak memory | 210600 kb |
| Host | smart-6aecfd47-3a03-4b3c-9d21-737d1b9ee77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754691072 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_pas sthru_mem_tl_intg_err.754691072 |
| Directory | /workspace/4.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.2955604686 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6814793955 ps |
| CPU time | 14.04 seconds |
| Started | Jan 21 03:01:59 PM PST 24 |
| Finished | Jan 21 03:02:15 PM PST 24 |
| Peak memory | 217808 kb |
| Host | smart-0d19b12b-4ef8-48f1-b1e4-ed0a516c724d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955604686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_c trl_same_csr_outstanding.2955604686 |
| Directory | /workspace/4.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.1534720587 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3918101098 ps |
| CPU time | 14.82 seconds |
| Started | Jan 21 03:01:55 PM PST 24 |
| Finished | Jan 21 03:02:13 PM PST 24 |
| Peak memory | 218828 kb |
| Host | smart-451410c2-8775-493d-b9a9-33f88e4a97ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534720587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.1534720587 |
| Directory | /workspace/4.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.4110919938 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 4803979781 ps |
| CPU time | 42.49 seconds |
| Started | Jan 21 03:01:42 PM PST 24 |
| Finished | Jan 21 03:02:32 PM PST 24 |
| Peak memory | 210748 kb |
| Host | smart-d46a733d-3f62-40f2-b49e-3ee71af0107c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110919938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in tg_err.4110919938 |
| Directory | /workspace/4.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.2089060991 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3527752018 ps |
| CPU time | 15.06 seconds |
| Started | Jan 21 03:01:52 PM PST 24 |
| Finished | Jan 21 03:02:12 PM PST 24 |
| Peak memory | 218936 kb |
| Host | smart-b727aa19-3b7d-45a7-b282-f777e8a1abfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089060991 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.2089060991 |
| Directory | /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3360138519 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 175087060 ps |
| CPU time | 4.2 seconds |
| Started | Jan 21 03:01:55 PM PST 24 |
| Finished | Jan 21 03:02:02 PM PST 24 |
| Peak memory | 210460 kb |
| Host | smart-11d0260d-7c90-4476-9694-95b07f71bf04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360138519 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3360138519 |
| Directory | /workspace/5.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.2463389418 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9582069029 ps |
| CPU time | 156.04 seconds |
| Started | Jan 21 03:01:41 PM PST 24 |
| Finished | Jan 21 03:04:23 PM PST 24 |
| Peak memory | 218672 kb |
| Host | smart-5b56a358-5d2d-4692-88f4-d657426bb599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463389418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa ssthru_mem_tl_intg_err.2463389418 |
| Directory | /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.2373080931 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 4084246523 ps |
| CPU time | 16.87 seconds |
| Started | Jan 21 03:26:10 PM PST 24 |
| Finished | Jan 21 03:26:28 PM PST 24 |
| Peak memory | 210684 kb |
| Host | smart-b63086d4-e619-4b93-8663-e13fa886ab21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373080931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c trl_same_csr_outstanding.2373080931 |
| Directory | /workspace/5.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.2918607065 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1400661385 ps |
| CPU time | 16.48 seconds |
| Started | Jan 21 03:01:39 PM PST 24 |
| Finished | Jan 21 03:01:58 PM PST 24 |
| Peak memory | 218868 kb |
| Host | smart-82a006d7-738b-4f83-9c6a-acc68b104d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918607065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.2918607065 |
| Directory | /workspace/5.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.586323841 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 4554827701 ps |
| CPU time | 48.76 seconds |
| Started | Jan 21 03:02:00 PM PST 24 |
| Finished | Jan 21 03:02:50 PM PST 24 |
| Peak memory | 218884 kb |
| Host | smart-e940db0e-1709-419e-91cb-5fb585b203a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586323841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_int g_err.586323841 |
| Directory | /workspace/5.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.3911759123 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 848042760 ps |
| CPU time | 10.69 seconds |
| Started | Jan 21 03:01:50 PM PST 24 |
| Finished | Jan 21 03:02:07 PM PST 24 |
| Peak memory | 218764 kb |
| Host | smart-c9447d1a-2b6f-475c-9668-84940ccf3753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911759123 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.3911759123 |
| Directory | /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.1531953858 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1391331514 ps |
| CPU time | 11.75 seconds |
| Started | Jan 21 03:28:00 PM PST 24 |
| Finished | Jan 21 03:28:13 PM PST 24 |
| Peak memory | 210552 kb |
| Host | smart-29b23510-a9ee-4348-9050-3951edefafe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531953858 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.1531953858 |
| Directory | /workspace/6.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.390952895 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 5678932568 ps |
| CPU time | 12.13 seconds |
| Started | Jan 21 04:00:29 PM PST 24 |
| Finished | Jan 21 04:00:42 PM PST 24 |
| Peak memory | 210716 kb |
| Host | smart-391e8d1f-d12b-474a-9fe1-0ee0f5442eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390952895 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ct rl_same_csr_outstanding.390952895 |
| Directory | /workspace/6.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1515462637 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 917909319 ps |
| CPU time | 11.73 seconds |
| Started | Jan 21 03:01:49 PM PST 24 |
| Finished | Jan 21 03:02:08 PM PST 24 |
| Peak memory | 218836 kb |
| Host | smart-b97ca862-31eb-4df1-b399-8109d4e920d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515462637 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1515462637 |
| Directory | /workspace/6.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.4063812704 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1687594820 ps |
| CPU time | 75.76 seconds |
| Started | Jan 21 03:01:50 PM PST 24 |
| Finished | Jan 21 03:03:12 PM PST 24 |
| Peak memory | 218728 kb |
| Host | smart-519d9a33-bd76-4d02-9319-d88533218fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063812704 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in tg_err.4063812704 |
| Directory | /workspace/6.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.847640586 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 760492874 ps |
| CPU time | 6.47 seconds |
| Started | Jan 21 03:02:05 PM PST 24 |
| Finished | Jan 21 03:02:13 PM PST 24 |
| Peak memory | 218872 kb |
| Host | smart-6284af42-1351-4f97-8e6e-7b4b7050e50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847640586 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.847640586 |
| Directory | /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.3502397333 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2774220361 ps |
| CPU time | 12.79 seconds |
| Started | Jan 21 03:02:04 PM PST 24 |
| Finished | Jan 21 03:02:18 PM PST 24 |
| Peak memory | 210484 kb |
| Host | smart-7bdd7cd5-c44f-43a6-a682-a55efbca76ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502397333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.3502397333 |
| Directory | /workspace/7.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.836471114 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 7144119193 ps |
| CPU time | 98.02 seconds |
| Started | Jan 21 03:02:05 PM PST 24 |
| Finished | Jan 21 03:03:44 PM PST 24 |
| Peak memory | 210628 kb |
| Host | smart-bc21e5b8-e08e-421a-9020-f1868c59b4d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836471114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pas sthru_mem_tl_intg_err.836471114 |
| Directory | /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.2251674833 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 88043242 ps |
| CPU time | 4.31 seconds |
| Started | Jan 21 03:02:05 PM PST 24 |
| Finished | Jan 21 03:02:10 PM PST 24 |
| Peak memory | 216576 kb |
| Host | smart-11bfdb3b-2789-4b1c-93c2-ae67e66f60db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251674833 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c trl_same_csr_outstanding.2251674833 |
| Directory | /workspace/7.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.628301119 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 587217584 ps |
| CPU time | 8.58 seconds |
| Started | Jan 21 03:02:02 PM PST 24 |
| Finished | Jan 21 03:02:12 PM PST 24 |
| Peak memory | 218872 kb |
| Host | smart-a1047749-5f02-4276-aa12-308c249231a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628301119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.628301119 |
| Directory | /workspace/7.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.4209274944 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7392838218 ps |
| CPU time | 77.35 seconds |
| Started | Jan 21 03:02:01 PM PST 24 |
| Finished | Jan 21 03:03:20 PM PST 24 |
| Peak memory | 219064 kb |
| Host | smart-70661b51-7a97-4747-a61b-566207571cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209274944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in tg_err.4209274944 |
| Directory | /workspace/7.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.456985579 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 613129643 ps |
| CPU time | 4.74 seconds |
| Started | Jan 21 03:02:08 PM PST 24 |
| Finished | Jan 21 03:02:13 PM PST 24 |
| Peak memory | 218848 kb |
| Host | smart-688491ff-9bca-4fc5-a612-e6b3fb9ec3de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456985579 -assert nopostproc +UVM_TESTNAME= rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.456985579 |
| Directory | /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.3517473326 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1734324890 ps |
| CPU time | 13.65 seconds |
| Started | Jan 21 03:02:04 PM PST 24 |
| Finished | Jan 21 03:02:19 PM PST 24 |
| Peak memory | 216936 kb |
| Host | smart-7b96fb4c-42e3-453f-9349-c93affd2a4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517473326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.3517473326 |
| Directory | /workspace/8.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.3016938073 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 29257912018 ps |
| CPU time | 160.15 seconds |
| Started | Jan 21 03:02:02 PM PST 24 |
| Finished | Jan 21 03:04:44 PM PST 24 |
| Peak memory | 210560 kb |
| Host | smart-4fc250a6-13c9-4464-9f33-b5616ee79302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016938073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pa ssthru_mem_tl_intg_err.3016938073 |
| Directory | /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2738107756 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 85769999 ps |
| CPU time | 4.35 seconds |
| Started | Jan 21 03:02:11 PM PST 24 |
| Finished | Jan 21 03:02:17 PM PST 24 |
| Peak memory | 210588 kb |
| Host | smart-c01ee779-235c-465c-ac02-a15ad97dcdb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738107756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c trl_same_csr_outstanding.2738107756 |
| Directory | /workspace/8.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2993622078 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1652663074 ps |
| CPU time | 13.51 seconds |
| Started | Jan 21 03:02:11 PM PST 24 |
| Finished | Jan 21 03:02:26 PM PST 24 |
| Peak memory | 218816 kb |
| Host | smart-f47fb84f-7d07-459c-9324-0d35504b3900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993622078 -assert nopostproc +UVM_TESTNAME =rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2993622078 |
| Directory | /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.486426091 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 652262879 ps |
| CPU time | 6.39 seconds |
| Started | Jan 21 03:02:07 PM PST 24 |
| Finished | Jan 21 03:02:14 PM PST 24 |
| Peak memory | 215924 kb |
| Host | smart-00f1a785-a9e6-4bdd-a085-f93d6526630e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486426091 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.486426091 |
| Directory | /workspace/9.rom_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.2057941804 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 74117661587 ps |
| CPU time | 133.9 seconds |
| Started | Jan 21 03:02:02 PM PST 24 |
| Finished | Jan 21 03:04:17 PM PST 24 |
| Peak memory | 218660 kb |
| Host | smart-14a80911-7160-4796-9f1a-3711b2149424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057941804 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa ssthru_mem_tl_intg_err.2057941804 |
| Directory | /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.2320717282 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2558145623 ps |
| CPU time | 12.49 seconds |
| Started | Jan 21 03:02:02 PM PST 24 |
| Finished | Jan 21 03:02:16 PM PST 24 |
| Peak memory | 210656 kb |
| Host | smart-91257864-0f26-4e77-81b6-1e4f19ffb890 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320717282 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_c trl_same_csr_outstanding.2320717282 |
| Directory | /workspace/9.rom_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1713589618 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 87419286 ps |
| CPU time | 6.34 seconds |
| Started | Jan 21 03:02:04 PM PST 24 |
| Finished | Jan 21 03:02:12 PM PST 24 |
| Peak memory | 218760 kb |
| Host | smart-86106508-08d4-4232-9a11-ff39c3305acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713589618 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.1713589618 |
| Directory | /workspace/9.rom_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1569482017 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3414125568 ps |
| CPU time | 70.9 seconds |
| Started | Jan 21 03:02:02 PM PST 24 |
| Finished | Jan 21 03:03:14 PM PST 24 |
| Peak memory | 211744 kb |
| Host | smart-ab2cedf6-0e86-401c-8af3-674f16e1dcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569482017 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in tg_err.1569482017 |
| Directory | /workspace/9.rom_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.3543178946 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 115163396421 ps |
| CPU time | 363.55 seconds |
| Started | Jan 21 09:53:37 PM PST 24 |
| Finished | Jan 21 09:59:41 PM PST 24 |
| Peak memory | 233836 kb |
| Host | smart-87798417-d954-48cb-883f-9e3106f7f20c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543178946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c orrupt_sig_fatal_chk.3543178946 |
| Directory | /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.288961996 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4652184987 ps |
| CPU time | 12.08 seconds |
| Started | Jan 21 09:30:10 PM PST 24 |
| Finished | Jan 21 09:30:42 PM PST 24 |
| Peak memory | 211384 kb |
| Host | smart-417dee26-9748-4c34-9c38-24feb09dae61 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=288961996 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.288961996 |
| Directory | /workspace/0.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_sec_cm.2846561153 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1697183183 ps |
| CPU time | 53.77 seconds |
| Started | Jan 21 09:06:08 PM PST 24 |
| Finished | Jan 21 09:07:37 PM PST 24 |
| Peak memory | 231404 kb |
| Host | smart-6aae7fb7-2405-46c2-8151-d2e6e2399229 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846561153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.2846561153 |
| Directory | /workspace/0.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_smoke.552220806 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 37233276501 ps |
| CPU time | 26.38 seconds |
| Started | Jan 21 09:06:00 PM PST 24 |
| Finished | Jan 21 09:07:00 PM PST 24 |
| Peak memory | 213948 kb |
| Host | smart-6e147f9e-d25c-485c-b3ca-69244367ea66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=552220806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.552220806 |
| Directory | /workspace/0.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_ctrl_stress_all.1738101551 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 1643228120 ps |
| CPU time | 10.7 seconds |
| Started | Jan 21 10:13:01 PM PST 24 |
| Finished | Jan 21 10:13:13 PM PST 24 |
| Peak memory | 211976 kb |
| Host | smart-e6e09453-547d-42b1-8f66-03610ce3dfeb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738101551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.rom_ctrl_stress_all.1738101551 |
| Directory | /workspace/0.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_alert_test.2410918199 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 6425958826 ps |
| CPU time | 13.64 seconds |
| Started | Jan 21 09:06:15 PM PST 24 |
| Finished | Jan 21 09:07:00 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-ba8328af-f6c2-439f-be65-29fb5a56a476 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410918199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.2410918199 |
| Directory | /workspace/1.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.1568422877 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 45974340623 ps |
| CPU time | 488.47 seconds |
| Started | Jan 21 10:34:29 PM PST 24 |
| Finished | Jan 21 10:42:39 PM PST 24 |
| Peak memory | 236844 kb |
| Host | smart-ae9934d4-fc34-40cf-bdee-6074a7238515 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568422877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c orrupt_sig_fatal_chk.1568422877 |
| Directory | /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.3069355501 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 13860850859 ps |
| CPU time | 28.5 seconds |
| Started | Jan 21 09:06:17 PM PST 24 |
| Finished | Jan 21 09:07:16 PM PST 24 |
| Peak memory | 211780 kb |
| Host | smart-a4986179-53a9-4b5d-a43a-464d3ce63faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069355501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.3069355501 |
| Directory | /workspace/1.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.206248749 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 4953346676 ps |
| CPU time | 13.01 seconds |
| Started | Jan 21 09:06:17 PM PST 24 |
| Finished | Jan 21 09:07:00 PM PST 24 |
| Peak memory | 211416 kb |
| Host | smart-02616fc1-04a8-4c30-a40d-1e28be30d872 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=206248749 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.206248749 |
| Directory | /workspace/1.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_sec_cm.2689119195 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1731678798 ps |
| CPU time | 56.66 seconds |
| Started | Jan 21 09:06:18 PM PST 24 |
| Finished | Jan 21 09:07:45 PM PST 24 |
| Peak memory | 233364 kb |
| Host | smart-d27c4a2e-80fc-4b46-9cdd-6973e72bc96a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689119195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2689119195 |
| Directory | /workspace/1.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_smoke.2873993922 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2157824661 ps |
| CPU time | 17.68 seconds |
| Started | Jan 21 09:06:16 PM PST 24 |
| Finished | Jan 21 09:07:05 PM PST 24 |
| Peak memory | 212952 kb |
| Host | smart-4e77b00f-b31a-4fd9-a256-5239b1bacfc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873993922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.2873993922 |
| Directory | /workspace/1.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all.2061867055 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2070119226 ps |
| CPU time | 22.2 seconds |
| Started | Jan 21 09:06:18 PM PST 24 |
| Finished | Jan 21 09:07:11 PM PST 24 |
| Peak memory | 215800 kb |
| Host | smart-5c10235d-bdca-4af1-944e-4d11d1b8c8aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061867055 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.rom_ctrl_stress_all.2061867055 |
| Directory | /workspace/1.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3783907443 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 104148994463 ps |
| CPU time | 1481.19 seconds |
| Started | Jan 21 09:06:16 PM PST 24 |
| Finished | Jan 21 09:31:28 PM PST 24 |
| Peak memory | 235928 kb |
| Host | smart-91c8893b-20f6-4cfe-ab0d-d82ee8124f2c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783907443 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.3783907443 |
| Directory | /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_alert_test.1404476976 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 9746449982 ps |
| CPU time | 13.66 seconds |
| Started | Jan 21 09:07:21 PM PST 24 |
| Finished | Jan 21 09:07:47 PM PST 24 |
| Peak memory | 211308 kb |
| Host | smart-77d68941-649f-4b76-a400-e0c6ff9c31a7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404476976 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.1404476976 |
| Directory | /workspace/10.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.3341374482 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 120518578115 ps |
| CPU time | 251.4 seconds |
| Started | Jan 21 09:07:19 PM PST 24 |
| Finished | Jan 21 09:11:42 PM PST 24 |
| Peak memory | 236524 kb |
| Host | smart-670d7e60-018d-474c-89c5-06644a40ea08 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341374482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_ corrupt_sig_fatal_chk.3341374482 |
| Directory | /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.4030084856 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 5186133127 ps |
| CPU time | 13.43 seconds |
| Started | Jan 21 09:07:25 PM PST 24 |
| Finished | Jan 21 09:07:50 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-79e4055d-1a5f-4090-8509-fa5f5671b0fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4030084856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.4030084856 |
| Directory | /workspace/10.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_smoke.1237806181 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2696617724 ps |
| CPU time | 31.6 seconds |
| Started | Jan 21 09:07:10 PM PST 24 |
| Finished | Jan 21 09:07:56 PM PST 24 |
| Peak memory | 212696 kb |
| Host | smart-65398aa7-76ba-42e5-8eef-77d3e4226375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1237806181 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.1237806181 |
| Directory | /workspace/10.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.rom_ctrl_stress_all.2526003102 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 1170655601 ps |
| CPU time | 13.54 seconds |
| Started | Jan 21 09:07:21 PM PST 24 |
| Finished | Jan 21 09:07:47 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-72630e42-7b16-4ead-b3d8-7e869477a7b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526003102 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 10.rom_ctrl_stress_all.2526003102 |
| Directory | /workspace/10.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_alert_test.3705531517 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1946993756 ps |
| CPU time | 15.45 seconds |
| Started | Jan 21 09:07:30 PM PST 24 |
| Finished | Jan 21 09:07:56 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-f2d17f44-d395-4f29-aa84-fccf1cdb45ef |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705531517 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.3705531517 |
| Directory | /workspace/11.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3916237683 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10072352800 ps |
| CPU time | 165.01 seconds |
| Started | Jan 21 09:07:22 PM PST 24 |
| Finished | Jan 21 09:10:20 PM PST 24 |
| Peak memory | 239252 kb |
| Host | smart-0ebdd0f0-2852-4537-82b4-59c47e902cb5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916237683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_ corrupt_sig_fatal_chk.3916237683 |
| Directory | /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.793294280 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 667324475 ps |
| CPU time | 9.65 seconds |
| Started | Jan 21 09:07:20 PM PST 24 |
| Finished | Jan 21 09:07:42 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-a390cc19-5d35-4192-819d-6c7469cddc70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793294280 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.793294280 |
| Directory | /workspace/11.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.506727482 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1290343535 ps |
| CPU time | 13.11 seconds |
| Started | Jan 21 09:07:20 PM PST 24 |
| Finished | Jan 21 09:07:46 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-797e7bce-31a4-49ff-9749-f51f881b143c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=506727482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.506727482 |
| Directory | /workspace/11.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_smoke.3018943634 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4916970905 ps |
| CPU time | 15.49 seconds |
| Started | Jan 21 09:07:20 PM PST 24 |
| Finished | Jan 21 09:07:48 PM PST 24 |
| Peak memory | 213592 kb |
| Host | smart-bac2b52a-a82a-4867-a119-bcaf6331146a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018943634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.3018943634 |
| Directory | /workspace/11.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all.1926017148 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3699592384 ps |
| CPU time | 41.35 seconds |
| Started | Jan 21 09:07:25 PM PST 24 |
| Finished | Jan 21 09:08:18 PM PST 24 |
| Peak memory | 218644 kb |
| Host | smart-fb5f03a0-a330-4d4a-9e51-e62ced63f5c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926017148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 11.rom_ctrl_stress_all.1926017148 |
| Directory | /workspace/11.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.465137656 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 47251267408 ps |
| CPU time | 5494.69 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 10:39:19 PM PST 24 |
| Peak memory | 235924 kb |
| Host | smart-146f6a24-dc3c-4704-a0f5-d449516f7d52 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465137656 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_stress_all_with_rand_reset.465137656 |
| Directory | /workspace/11.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_alert_test.1734603004 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 333285580 ps |
| CPU time | 4.28 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:07:48 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-10d9029e-ab95-4d01-8e77-bb7f61fd03ad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734603004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1734603004 |
| Directory | /workspace/12.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2950174794 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 52628507391 ps |
| CPU time | 208.23 seconds |
| Started | Jan 21 09:07:30 PM PST 24 |
| Finished | Jan 21 09:11:09 PM PST 24 |
| Peak memory | 212016 kb |
| Host | smart-b9b862d2-300f-49d3-880a-131082a84a1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950174794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_ corrupt_sig_fatal_chk.2950174794 |
| Directory | /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.247571487 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 12248405675 ps |
| CPU time | 26.16 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:08:10 PM PST 24 |
| Peak memory | 211996 kb |
| Host | smart-b0156d77-fa08-48f1-99c2-0f1d6e842af8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=247571487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.247571487 |
| Directory | /workspace/12.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.2523860504 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 99355699 ps |
| CPU time | 5.87 seconds |
| Started | Jan 21 09:07:29 PM PST 24 |
| Finished | Jan 21 09:07:46 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-ffb9fa19-cec0-4750-b268-e8d6c2dcdbd3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2523860504 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.2523860504 |
| Directory | /workspace/12.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_smoke.315967437 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3653764944 ps |
| CPU time | 31.32 seconds |
| Started | Jan 21 09:07:34 PM PST 24 |
| Finished | Jan 21 09:08:16 PM PST 24 |
| Peak memory | 212876 kb |
| Host | smart-a8b3ac6b-02dc-41d6-9e21-e97bd195cf6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315967437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.315967437 |
| Directory | /workspace/12.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all.651788298 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 191026264 ps |
| CPU time | 10.25 seconds |
| Started | Jan 21 09:07:29 PM PST 24 |
| Finished | Jan 21 09:07:50 PM PST 24 |
| Peak memory | 213600 kb |
| Host | smart-abbaa502-fdad-4de6-94f4-eed256066339 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651788298 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.rom_ctrl_stress_all.651788298 |
| Directory | /workspace/12.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1141117523 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 20111861042 ps |
| CPU time | 1058.19 seconds |
| Started | Jan 21 09:07:34 PM PST 24 |
| Finished | Jan 21 09:25:23 PM PST 24 |
| Peak memory | 227840 kb |
| Host | smart-b3ad273f-f91b-4b35-b078-b623f1c7b688 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141117523 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_stress_all_with_rand_reset.1141117523 |
| Directory | /workspace/12.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_alert_test.224592474 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 488299864 ps |
| CPU time | 4.3 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:07:48 PM PST 24 |
| Peak memory | 211192 kb |
| Host | smart-fe5938c2-1c18-4fb0-a07b-da4b750cb022 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224592474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.224592474 |
| Directory | /workspace/13.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.2331142066 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 44889690346 ps |
| CPU time | 354.78 seconds |
| Started | Jan 21 09:07:28 PM PST 24 |
| Finished | Jan 21 09:13:35 PM PST 24 |
| Peak memory | 238500 kb |
| Host | smart-9d906699-1d4b-4188-b056-08f76b846674 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331142066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_ corrupt_sig_fatal_chk.2331142066 |
| Directory | /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4146585132 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 693606729 ps |
| CPU time | 9.39 seconds |
| Started | Jan 21 09:07:31 PM PST 24 |
| Finished | Jan 21 09:07:51 PM PST 24 |
| Peak memory | 211544 kb |
| Host | smart-4d87c0cf-8393-4423-88ee-307420482e98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146585132 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4146585132 |
| Directory | /workspace/13.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.114568984 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 26950731081 ps |
| CPU time | 15.24 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:08:00 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-ba5a0012-fa0b-48c9-b077-9c5ceaaac385 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=114568984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.114568984 |
| Directory | /workspace/13.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_smoke.91534828 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 719515818 ps |
| CPU time | 10.35 seconds |
| Started | Jan 21 09:07:34 PM PST 24 |
| Finished | Jan 21 09:07:55 PM PST 24 |
| Peak memory | 213240 kb |
| Host | smart-33c0bf82-7d07-4396-b02c-1e6b4405d2b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=91534828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.91534828 |
| Directory | /workspace/13.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.rom_ctrl_stress_all.2534171892 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 581984978 ps |
| CPU time | 33.51 seconds |
| Started | Jan 21 09:07:31 PM PST 24 |
| Finished | Jan 21 09:08:15 PM PST 24 |
| Peak memory | 216324 kb |
| Host | smart-ea1e2bfc-07d2-480d-a999-ae7e272f8197 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534171892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 13.rom_ctrl_stress_all.2534171892 |
| Directory | /workspace/13.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_alert_test.1561275432 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 1110184928 ps |
| CPU time | 10.82 seconds |
| Started | Jan 21 09:07:36 PM PST 24 |
| Finished | Jan 21 09:07:58 PM PST 24 |
| Peak memory | 211260 kb |
| Host | smart-7a7f3e94-bfc7-433f-8d6e-761427f37ff8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561275432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.1561275432 |
| Directory | /workspace/14.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.2932350658 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 39134212202 ps |
| CPU time | 138.96 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:10:04 PM PST 24 |
| Peak memory | 213540 kb |
| Host | smart-bb874a1e-0aba-49f4-b923-7e6f47b9b1a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932350658 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_ corrupt_sig_fatal_chk.2932350658 |
| Directory | /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.1599253560 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1382052328 ps |
| CPU time | 18.12 seconds |
| Started | Jan 21 09:07:31 PM PST 24 |
| Finished | Jan 21 09:08:00 PM PST 24 |
| Peak memory | 211668 kb |
| Host | smart-659feec6-f9a5-4d6f-9f40-e50eaf11f09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1599253560 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.1599253560 |
| Directory | /workspace/14.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.4281834210 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2591044979 ps |
| CPU time | 13.07 seconds |
| Started | Jan 21 09:07:30 PM PST 24 |
| Finished | Jan 21 09:07:54 PM PST 24 |
| Peak memory | 211364 kb |
| Host | smart-f2c588c2-8a4f-469d-8983-3ddbbda29a2f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4281834210 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.4281834210 |
| Directory | /workspace/14.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_smoke.310672381 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 2553981639 ps |
| CPU time | 29.32 seconds |
| Started | Jan 21 09:07:34 PM PST 24 |
| Finished | Jan 21 09:08:14 PM PST 24 |
| Peak memory | 213296 kb |
| Host | smart-8d3d120a-d3f9-495d-a90e-ce638d16fd2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310672381 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.310672381 |
| Directory | /workspace/14.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all.3479872953 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 85032577719 ps |
| CPU time | 78.26 seconds |
| Started | Jan 21 09:07:28 PM PST 24 |
| Finished | Jan 21 09:08:58 PM PST 24 |
| Peak memory | 219588 kb |
| Host | smart-d36bc76a-6961-4157-a7ed-9e2f735bb2ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479872953 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 14.rom_ctrl_stress_all.3479872953 |
| Directory | /workspace/14.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.602147806 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 36278056046 ps |
| CPU time | 1566.48 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:33:51 PM PST 24 |
| Peak memory | 234368 kb |
| Host | smart-9d0d750e-9be2-453b-83fd-f8d9bfb59ac8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602147806 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.602147806 |
| Directory | /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_alert_test.2299981554 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3340080611 ps |
| CPU time | 13.65 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:07:58 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-6af9129d-0399-4f4b-94aa-6ee24564ca86 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299981554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.2299981554 |
| Directory | /workspace/15.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2511136239 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 206690834275 ps |
| CPU time | 548.13 seconds |
| Started | Jan 21 09:07:35 PM PST 24 |
| Finished | Jan 21 09:16:54 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-d5cdbbff-49d7-40b7-aa6d-775938337b0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511136239 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_ corrupt_sig_fatal_chk.2511136239 |
| Directory | /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.220927441 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3737668296 ps |
| CPU time | 20.84 seconds |
| Started | Jan 21 09:07:34 PM PST 24 |
| Finished | Jan 21 09:08:06 PM PST 24 |
| Peak memory | 211540 kb |
| Host | smart-b21d201a-e04d-4660-8d13-f65b1620810e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220927441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.220927441 |
| Directory | /workspace/15.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.1240858015 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 1335424424 ps |
| CPU time | 12.75 seconds |
| Started | Jan 21 09:07:35 PM PST 24 |
| Finished | Jan 21 09:07:59 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-215ffafb-8976-4abc-8716-d5358d70bb8b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1240858015 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.1240858015 |
| Directory | /workspace/15.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_smoke.2064444919 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 594410553 ps |
| CPU time | 14.67 seconds |
| Started | Jan 21 09:07:35 PM PST 24 |
| Finished | Jan 21 09:08:00 PM PST 24 |
| Peak memory | 213380 kb |
| Host | smart-3d06fd8e-c5dc-4a51-bc01-6846f1bc4ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2064444919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.2064444919 |
| Directory | /workspace/15.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all.3265925063 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 391764158 ps |
| CPU time | 21.3 seconds |
| Started | Jan 21 09:07:30 PM PST 24 |
| Finished | Jan 21 09:08:02 PM PST 24 |
| Peak memory | 215948 kb |
| Host | smart-eb525cf8-51d1-441f-9871-b7f82d329bf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265925063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 15.rom_ctrl_stress_all.3265925063 |
| Directory | /workspace/15.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1254168278 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 49153445460 ps |
| CPU time | 1719.45 seconds |
| Started | Jan 21 09:07:31 PM PST 24 |
| Finished | Jan 21 09:36:22 PM PST 24 |
| Peak memory | 236032 kb |
| Host | smart-493954f7-e7d3-497e-aa8f-e544bcf610a0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254168278 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_stress_all_with_rand_reset.1254168278 |
| Directory | /workspace/15.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_alert_test.1366969985 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2360072273 ps |
| CPU time | 5.36 seconds |
| Started | Jan 21 09:07:37 PM PST 24 |
| Finished | Jan 21 09:07:56 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-fc16e52e-03d0-4a27-a7b2-46c541c488e9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366969985 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1366969985 |
| Directory | /workspace/16.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2353259128 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 112265841375 ps |
| CPU time | 592.85 seconds |
| Started | Jan 21 09:07:36 PM PST 24 |
| Finished | Jan 21 09:17:40 PM PST 24 |
| Peak memory | 228444 kb |
| Host | smart-d535a270-2d6a-4d22-8e66-0891f9c73f80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353259128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_ corrupt_sig_fatal_chk.2353259128 |
| Directory | /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.4169650317 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3614326547 ps |
| CPU time | 15.54 seconds |
| Started | Jan 21 09:07:36 PM PST 24 |
| Finished | Jan 21 09:08:03 PM PST 24 |
| Peak memory | 211480 kb |
| Host | smart-281edf76-ff7c-4cae-a200-84e1eed3037e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169650317 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.4169650317 |
| Directory | /workspace/16.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.1983450665 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4489936547 ps |
| CPU time | 11.68 seconds |
| Started | Jan 21 09:07:32 PM PST 24 |
| Finished | Jan 21 09:07:54 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-de007547-9395-4916-af64-32e626924d7c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1983450665 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.1983450665 |
| Directory | /workspace/16.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_smoke.2337882457 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 239408899 ps |
| CPU time | 10.02 seconds |
| Started | Jan 21 09:07:38 PM PST 24 |
| Finished | Jan 21 09:08:01 PM PST 24 |
| Peak memory | 212764 kb |
| Host | smart-13937301-8a15-4f61-924e-20fe11eddf18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2337882457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2337882457 |
| Directory | /workspace/16.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.rom_ctrl_stress_all.1061639287 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 706054702 ps |
| CPU time | 26.58 seconds |
| Started | Jan 21 09:07:33 PM PST 24 |
| Finished | Jan 21 09:08:11 PM PST 24 |
| Peak memory | 214764 kb |
| Host | smart-8240b6bb-5dd2-4ccf-8bf3-ea16d0bbe45e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061639287 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 16.rom_ctrl_stress_all.1061639287 |
| Directory | /workspace/16.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_alert_test.2718786881 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1873704495 ps |
| CPU time | 14.58 seconds |
| Started | Jan 21 09:07:40 PM PST 24 |
| Finished | Jan 21 09:08:08 PM PST 24 |
| Peak memory | 211228 kb |
| Host | smart-ff17fc6a-e664-4894-be4b-c19ad9817808 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718786881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.2718786881 |
| Directory | /workspace/17.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.3425309062 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 60990036849 ps |
| CPU time | 394.39 seconds |
| Started | Jan 21 09:07:42 PM PST 24 |
| Finished | Jan 21 09:14:31 PM PST 24 |
| Peak memory | 232760 kb |
| Host | smart-11a46336-7a2f-4425-a13b-4789ab6456d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425309062 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_ corrupt_sig_fatal_chk.3425309062 |
| Directory | /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.2384430742 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 168745854 ps |
| CPU time | 9.52 seconds |
| Started | Jan 21 09:07:42 PM PST 24 |
| Finished | Jan 21 09:08:06 PM PST 24 |
| Peak memory | 211592 kb |
| Host | smart-e561c307-5a79-46c2-88f1-61d3f1d4bd3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384430742 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.2384430742 |
| Directory | /workspace/17.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.275220900 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1949781740 ps |
| CPU time | 16.75 seconds |
| Started | Jan 21 09:07:42 PM PST 24 |
| Finished | Jan 21 09:08:13 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-f567c6d9-9307-459b-878b-71bc5f780858 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=275220900 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.275220900 |
| Directory | /workspace/17.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_smoke.354836756 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 18263177347 ps |
| CPU time | 40.89 seconds |
| Started | Jan 21 09:07:40 PM PST 24 |
| Finished | Jan 21 09:08:34 PM PST 24 |
| Peak memory | 213868 kb |
| Host | smart-fa6869fd-9319-4eb5-a933-4eb7396ffcff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=354836756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.354836756 |
| Directory | /workspace/17.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all.3179040103 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 316878870 ps |
| CPU time | 16.2 seconds |
| Started | Jan 21 09:07:39 PM PST 24 |
| Finished | Jan 21 09:08:09 PM PST 24 |
| Peak memory | 214552 kb |
| Host | smart-d23f14e1-2ea7-4cc2-aece-92900aaafbcb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179040103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.rom_ctrl_stress_all.3179040103 |
| Directory | /workspace/17.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3937527405 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 16752793702 ps |
| CPU time | 482.66 seconds |
| Started | Jan 21 09:07:49 PM PST 24 |
| Finished | Jan 21 09:16:09 PM PST 24 |
| Peak memory | 228300 kb |
| Host | smart-9c732902-268a-4799-a108-992aca7c033d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937527405 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_stress_all_with_rand_reset.3937527405 |
| Directory | /workspace/17.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_alert_test.4002685820 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3730152734 ps |
| CPU time | 10.32 seconds |
| Started | Jan 21 09:07:54 PM PST 24 |
| Finished | Jan 21 09:08:24 PM PST 24 |
| Peak memory | 211524 kb |
| Host | smart-3811ef4b-1451-4253-ba96-d424ec710b8d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002685820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.4002685820 |
| Directory | /workspace/18.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.1476523661 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 13422054852 ps |
| CPU time | 176.16 seconds |
| Started | Jan 21 09:07:47 PM PST 24 |
| Finished | Jan 21 09:11:01 PM PST 24 |
| Peak memory | 212472 kb |
| Host | smart-de52f92e-5bb2-4bda-9264-3572aafd49f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476523661 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_ corrupt_sig_fatal_chk.1476523661 |
| Directory | /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.384448820 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1910367902 ps |
| CPU time | 18.56 seconds |
| Started | Jan 21 09:07:48 PM PST 24 |
| Finished | Jan 21 09:08:24 PM PST 24 |
| Peak memory | 211416 kb |
| Host | smart-0ee699b0-b3ff-4621-807c-e1dc290da9e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384448820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.384448820 |
| Directory | /workspace/18.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.2140267785 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 3155603425 ps |
| CPU time | 14.26 seconds |
| Started | Jan 21 09:07:39 PM PST 24 |
| Finished | Jan 21 09:08:06 PM PST 24 |
| Peak memory | 211424 kb |
| Host | smart-f7d22923-6876-4db4-b812-06a739164f2b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2140267785 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.2140267785 |
| Directory | /workspace/18.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_smoke.1277231507 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 272309608 ps |
| CPU time | 12.31 seconds |
| Started | Jan 21 09:07:42 PM PST 24 |
| Finished | Jan 21 09:08:08 PM PST 24 |
| Peak memory | 213592 kb |
| Host | smart-e93fc86b-ef25-4a03-8dba-9f3cafa0b50d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277231507 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.1277231507 |
| Directory | /workspace/18.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.rom_ctrl_stress_all.2738107686 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 7422539420 ps |
| CPU time | 16.46 seconds |
| Started | Jan 21 09:07:39 PM PST 24 |
| Finished | Jan 21 09:08:09 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-d0144f0f-b0f5-4537-bcbb-757d4c8432b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738107686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.rom_ctrl_stress_all.2738107686 |
| Directory | /workspace/18.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_alert_test.1976665451 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 172077352 ps |
| CPU time | 4.46 seconds |
| Started | Jan 21 09:07:49 PM PST 24 |
| Finished | Jan 21 09:08:11 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-a4b19c30-8e26-46d1-beb6-8c845b4982af |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976665451 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.1976665451 |
| Directory | /workspace/19.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1999949780 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 71191492961 ps |
| CPU time | 215.67 seconds |
| Started | Jan 21 09:07:52 PM PST 24 |
| Finished | Jan 21 09:11:46 PM PST 24 |
| Peak memory | 228628 kb |
| Host | smart-cc4bac23-81a9-491c-9c47-d153dd828836 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999949780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_ corrupt_sig_fatal_chk.1999949780 |
| Directory | /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.1117345884 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1472853634 ps |
| CPU time | 18.24 seconds |
| Started | Jan 21 09:07:52 PM PST 24 |
| Finished | Jan 21 09:08:29 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-015da5db-8f13-4f91-8058-3ed044d9c888 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117345884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.1117345884 |
| Directory | /workspace/19.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.1294481908 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 1686454519 ps |
| CPU time | 14.47 seconds |
| Started | Jan 21 09:07:57 PM PST 24 |
| Finished | Jan 21 09:08:32 PM PST 24 |
| Peak memory | 211200 kb |
| Host | smart-999a37af-4cd3-4b92-87d4-372551267f15 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1294481908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.1294481908 |
| Directory | /workspace/19.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_smoke.468079301 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6031534578 ps |
| CPU time | 27.52 seconds |
| Started | Jan 21 09:07:53 PM PST 24 |
| Finished | Jan 21 09:08:40 PM PST 24 |
| Peak memory | 213124 kb |
| Host | smart-18038165-03a1-4203-9ff5-9bf46a10b00b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468079301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.468079301 |
| Directory | /workspace/19.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.rom_ctrl_stress_all.1352018148 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2850673144 ps |
| CPU time | 25.81 seconds |
| Started | Jan 21 09:07:57 PM PST 24 |
| Finished | Jan 21 09:08:44 PM PST 24 |
| Peak memory | 213828 kb |
| Host | smart-ffc39b0d-5bae-45c2-965f-b0a50f276d1e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352018148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 19.rom_ctrl_stress_all.1352018148 |
| Directory | /workspace/19.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_alert_test.2225885876 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 9403726795 ps |
| CPU time | 11.96 seconds |
| Started | Jan 21 09:06:17 PM PST 24 |
| Finished | Jan 21 09:07:00 PM PST 24 |
| Peak memory | 211340 kb |
| Host | smart-af21b307-c0d0-41b8-a230-74379aeef8f6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225885876 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.2225885876 |
| Directory | /workspace/2.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.1068567975 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 93345723302 ps |
| CPU time | 205.9 seconds |
| Started | Jan 21 09:06:15 PM PST 24 |
| Finished | Jan 21 09:10:12 PM PST 24 |
| Peak memory | 228448 kb |
| Host | smart-f6cd6e20-c9e8-4dd2-a1f7-0124abf127d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068567975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c orrupt_sig_fatal_chk.1068567975 |
| Directory | /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.349452104 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4396790296 ps |
| CPU time | 22.16 seconds |
| Started | Jan 21 09:06:17 PM PST 24 |
| Finished | Jan 21 09:07:10 PM PST 24 |
| Peak memory | 211736 kb |
| Host | smart-c357e92a-774b-4751-a95c-6bb61102933c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349452104 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.349452104 |
| Directory | /workspace/2.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.2039988860 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 20343899910 ps |
| CPU time | 15.64 seconds |
| Started | Jan 21 09:06:15 PM PST 24 |
| Finished | Jan 21 09:07:02 PM PST 24 |
| Peak memory | 211376 kb |
| Host | smart-20af443f-13be-48a1-88c8-f6aa917a826a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2039988860 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.2039988860 |
| Directory | /workspace/2.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_smoke.1422168321 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 353270084 ps |
| CPU time | 11.19 seconds |
| Started | Jan 21 09:06:18 PM PST 24 |
| Finished | Jan 21 09:06:59 PM PST 24 |
| Peak memory | 212628 kb |
| Host | smart-530fed28-fb5e-47c2-872a-23c251270a1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1422168321 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.1422168321 |
| Directory | /workspace/2.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all.108350069 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2717802467 ps |
| CPU time | 27.8 seconds |
| Started | Jan 21 09:06:13 PM PST 24 |
| Finished | Jan 21 09:07:14 PM PST 24 |
| Peak memory | 212836 kb |
| Host | smart-f1c26756-16da-40c4-8e12-ee1dd69aa8b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108350069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_ctrl_stress_all.108350069 |
| Directory | /workspace/2.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.450148556 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 52470256002 ps |
| CPU time | 2087.44 seconds |
| Started | Jan 21 09:06:18 PM PST 24 |
| Finished | Jan 21 09:41:35 PM PST 24 |
| Peak memory | 238756 kb |
| Host | smart-365971d2-04a8-43bc-af35-e42aa83bd3df |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450148556 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_stress_all_with_rand_reset.450148556 |
| Directory | /workspace/2.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_alert_test.2884362077 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1650838856 ps |
| CPU time | 7.09 seconds |
| Started | Jan 21 09:08:09 PM PST 24 |
| Finished | Jan 21 09:08:41 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-bb6bc3a8-0987-460a-b767-410a0eb9f530 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884362077 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.2884362077 |
| Directory | /workspace/20.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.1343984134 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3229869097 ps |
| CPU time | 138.4 seconds |
| Started | Jan 21 09:08:07 PM PST 24 |
| Finished | Jan 21 09:10:49 PM PST 24 |
| Peak memory | 237168 kb |
| Host | smart-48a6efd6-6d74-404d-82fc-3798f1ad2121 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343984134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_ corrupt_sig_fatal_chk.1343984134 |
| Directory | /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.403576281 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 102974402 ps |
| CPU time | 5.52 seconds |
| Started | Jan 21 09:08:01 PM PST 24 |
| Finished | Jan 21 09:08:30 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-94a77f07-c0ba-41be-bab3-87bdbabce77d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=403576281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.403576281 |
| Directory | /workspace/20.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_smoke.4104590522 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1621206080 ps |
| CPU time | 21.87 seconds |
| Started | Jan 21 09:07:54 PM PST 24 |
| Finished | Jan 21 09:08:36 PM PST 24 |
| Peak memory | 213008 kb |
| Host | smart-0aa3d78d-533d-4087-8ea9-a909bae90b38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4104590522 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.4104590522 |
| Directory | /workspace/20.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all.1641214253 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 17230840771 ps |
| CPU time | 39.74 seconds |
| Started | Jan 21 09:08:01 PM PST 24 |
| Finished | Jan 21 09:09:05 PM PST 24 |
| Peak memory | 214816 kb |
| Host | smart-b6d4383b-8660-4cb4-afd2-a5bf1733a298 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641214253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 20.rom_ctrl_stress_all.1641214253 |
| Directory | /workspace/20.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.868971361 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 179527466241 ps |
| CPU time | 4413.42 seconds |
| Started | Jan 21 09:08:02 PM PST 24 |
| Finished | Jan 21 10:21:59 PM PST 24 |
| Peak memory | 238888 kb |
| Host | smart-9cd0a16e-007d-4bf3-9788-087bd3258d89 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868971361 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.868971361 |
| Directory | /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_alert_test.2039374850 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1441571563 ps |
| CPU time | 7.74 seconds |
| Started | Jan 21 09:08:14 PM PST 24 |
| Finished | Jan 21 09:08:47 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-0e4032ae-75a6-48a3-859c-072d1a10739b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039374850 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.2039374850 |
| Directory | /workspace/21.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.2694065681 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3185416440 ps |
| CPU time | 98.64 seconds |
| Started | Jan 21 09:08:09 PM PST 24 |
| Finished | Jan 21 09:10:13 PM PST 24 |
| Peak memory | 237004 kb |
| Host | smart-beb9001c-2c78-49ed-bdf5-4e0753908989 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694065681 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_ corrupt_sig_fatal_chk.2694065681 |
| Directory | /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.432502336 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 1561204688 ps |
| CPU time | 20.09 seconds |
| Started | Jan 21 09:08:12 PM PST 24 |
| Finished | Jan 21 09:08:57 PM PST 24 |
| Peak memory | 211492 kb |
| Host | smart-23ac9375-dc32-405a-9112-a1d4f5aaede9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=432502336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.432502336 |
| Directory | /workspace/21.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.4002108325 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 402684627 ps |
| CPU time | 5.72 seconds |
| Started | Jan 21 09:08:01 PM PST 24 |
| Finished | Jan 21 09:08:30 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-c84cb5c0-76cf-4dc0-8c4f-9cf63a8b419c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4002108325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.4002108325 |
| Directory | /workspace/21.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_smoke.3766927984 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2301021748 ps |
| CPU time | 23.72 seconds |
| Started | Jan 21 09:08:02 PM PST 24 |
| Finished | Jan 21 09:08:49 PM PST 24 |
| Peak memory | 213412 kb |
| Host | smart-3f8586c8-d0ab-4982-a650-b273d52b527f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766927984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.3766927984 |
| Directory | /workspace/21.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all.1329263587 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 29996161682 ps |
| CPU time | 58.29 seconds |
| Started | Jan 21 09:08:03 PM PST 24 |
| Finished | Jan 21 09:09:24 PM PST 24 |
| Peak memory | 219572 kb |
| Host | smart-01cc28a2-6e64-4789-a1e7-639b45607843 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329263587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 21.rom_ctrl_stress_all.1329263587 |
| Directory | /workspace/21.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.2039727388 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 51114447799 ps |
| CPU time | 1929.2 seconds |
| Started | Jan 21 09:08:10 PM PST 24 |
| Finished | Jan 21 09:40:44 PM PST 24 |
| Peak memory | 236492 kb |
| Host | smart-e1e395d0-d81e-40c5-905c-067fd53eb9e8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039727388 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.2039727388 |
| Directory | /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_alert_test.1632410961 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 8075671130 ps |
| CPU time | 16.24 seconds |
| Started | Jan 21 09:08:11 PM PST 24 |
| Finished | Jan 21 09:08:52 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-8772f0b0-7981-42d3-a47d-8f6ec3e47cbb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632410961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.1632410961 |
| Directory | /workspace/22.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.3072499128 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2739876884 ps |
| CPU time | 14.38 seconds |
| Started | Jan 21 09:08:20 PM PST 24 |
| Finished | Jan 21 09:09:00 PM PST 24 |
| Peak memory | 211364 kb |
| Host | smart-05377eb2-01c6-4341-82ee-fb2ff9ebb44c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072499128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.3072499128 |
| Directory | /workspace/22.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.2982908144 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 241122785 ps |
| CPU time | 5.75 seconds |
| Started | Jan 21 09:08:20 PM PST 24 |
| Finished | Jan 21 09:08:51 PM PST 24 |
| Peak memory | 211200 kb |
| Host | smart-92e214d3-4c06-497d-983d-bffecf713b7b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2982908144 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.2982908144 |
| Directory | /workspace/22.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_smoke.4038444209 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 20962613452 ps |
| CPU time | 32.19 seconds |
| Started | Jan 21 09:08:10 PM PST 24 |
| Finished | Jan 21 09:09:08 PM PST 24 |
| Peak memory | 213800 kb |
| Host | smart-9c31d634-d09c-40ad-ab92-885294fc869a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038444209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.4038444209 |
| Directory | /workspace/22.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.rom_ctrl_stress_all.3173901305 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 7422702850 ps |
| CPU time | 61.92 seconds |
| Started | Jan 21 09:08:09 PM PST 24 |
| Finished | Jan 21 09:09:36 PM PST 24 |
| Peak memory | 216320 kb |
| Host | smart-d91f67fd-1ad4-4214-8539-8fb78508ee52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173901305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.rom_ctrl_stress_all.3173901305 |
| Directory | /workspace/22.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_alert_test.3869172099 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 88919682 ps |
| CPU time | 4.17 seconds |
| Started | Jan 21 09:08:13 PM PST 24 |
| Finished | Jan 21 09:08:42 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-a12ad6f7-e8f4-4571-8c09-7b785a480713 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869172099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.3869172099 |
| Directory | /workspace/23.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.429792481 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 54652321430 ps |
| CPU time | 195.26 seconds |
| Started | Jan 21 09:08:18 PM PST 24 |
| Finished | Jan 21 09:11:58 PM PST 24 |
| Peak memory | 233836 kb |
| Host | smart-c70e9665-33cc-4ccc-9cd0-3af2a25ad07a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429792481 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_c orrupt_sig_fatal_chk.429792481 |
| Directory | /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.157523903 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5381509599 ps |
| CPU time | 25.8 seconds |
| Started | Jan 21 09:08:18 PM PST 24 |
| Finished | Jan 21 09:09:10 PM PST 24 |
| Peak memory | 219528 kb |
| Host | smart-863d42a1-b1f7-4481-8fd8-37e9542ed3ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=157523903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.157523903 |
| Directory | /workspace/23.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3353241147 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 94643557 ps |
| CPU time | 5.45 seconds |
| Started | Jan 21 09:08:20 PM PST 24 |
| Finished | Jan 21 09:08:51 PM PST 24 |
| Peak memory | 211200 kb |
| Host | smart-d072f284-5b46-4745-8509-387ee81b2810 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3353241147 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3353241147 |
| Directory | /workspace/23.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_smoke.1962631493 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 9228958299 ps |
| CPU time | 27.36 seconds |
| Started | Jan 21 09:08:13 PM PST 24 |
| Finished | Jan 21 09:09:06 PM PST 24 |
| Peak memory | 213440 kb |
| Host | smart-11ec5c64-973a-4c0b-bee6-a586ba27758b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1962631493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.1962631493 |
| Directory | /workspace/23.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.rom_ctrl_stress_all.3209866106 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 21856688008 ps |
| CPU time | 44.92 seconds |
| Started | Jan 21 09:08:11 PM PST 24 |
| Finished | Jan 21 09:09:21 PM PST 24 |
| Peak memory | 216260 kb |
| Host | smart-4063a4bc-f633-43f8-8227-659f2c148c94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209866106 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 23.rom_ctrl_stress_all.3209866106 |
| Directory | /workspace/23.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_alert_test.2940839107 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2220511272 ps |
| CPU time | 7.63 seconds |
| Started | Jan 21 09:08:25 PM PST 24 |
| Finished | Jan 21 09:08:54 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-d0f06d78-b81f-44eb-89db-34a9dff5a16a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940839107 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.2940839107 |
| Directory | /workspace/24.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.3519229780 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 12891786599 ps |
| CPU time | 144 seconds |
| Started | Jan 21 09:08:20 PM PST 24 |
| Finished | Jan 21 09:11:09 PM PST 24 |
| Peak memory | 236868 kb |
| Host | smart-84870ff0-f695-40f9-9ea7-cc80fd4bc513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519229780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_ corrupt_sig_fatal_chk.3519229780 |
| Directory | /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.4187656286 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 692950631 ps |
| CPU time | 9.38 seconds |
| Started | Jan 21 10:50:34 PM PST 24 |
| Finished | Jan 21 10:50:45 PM PST 24 |
| Peak memory | 211612 kb |
| Host | smart-27a25a2c-8dc7-4580-94cf-430ee4a9a35f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187656286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.4187656286 |
| Directory | /workspace/24.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2281267281 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5794508327 ps |
| CPU time | 13.34 seconds |
| Started | Jan 21 09:08:19 PM PST 24 |
| Finished | Jan 21 09:08:58 PM PST 24 |
| Peak memory | 211260 kb |
| Host | smart-fcb1cc13-ca9c-4ddb-ad51-f7e370568696 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2281267281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2281267281 |
| Directory | /workspace/24.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_smoke.821433592 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 188877597 ps |
| CPU time | 10.08 seconds |
| Started | Jan 21 09:08:17 PM PST 24 |
| Finished | Jan 21 09:08:53 PM PST 24 |
| Peak memory | 213340 kb |
| Host | smart-3e20039c-b3ce-4422-b342-85b2af849063 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821433592 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.821433592 |
| Directory | /workspace/24.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all.3851940824 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2524075631 ps |
| CPU time | 20.58 seconds |
| Started | Jan 21 09:08:17 PM PST 24 |
| Finished | Jan 21 09:09:03 PM PST 24 |
| Peak memory | 211424 kb |
| Host | smart-d04dcc95-8483-40e7-b7f3-bbde0314ac3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851940824 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 24.rom_ctrl_stress_all.3851940824 |
| Directory | /workspace/24.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.2948574708 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 99873226011 ps |
| CPU time | 1101.92 seconds |
| Started | Jan 21 09:08:21 PM PST 24 |
| Finished | Jan 21 09:27:08 PM PST 24 |
| Peak memory | 236004 kb |
| Host | smart-74a857b8-7169-4572-95e6-ab23eacc4914 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948574708 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.2948574708 |
| Directory | /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_alert_test.2349937302 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4112369001 ps |
| CPU time | 9.85 seconds |
| Started | Jan 21 09:47:18 PM PST 24 |
| Finished | Jan 21 09:47:38 PM PST 24 |
| Peak memory | 211336 kb |
| Host | smart-e2668c62-d126-4a67-a7ac-97127c2ee00c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349937302 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.2349937302 |
| Directory | /workspace/25.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_kmac_err_chk.4252406392 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3825256075 ps |
| CPU time | 30.99 seconds |
| Started | Jan 21 09:08:38 PM PST 24 |
| Finished | Jan 21 09:09:26 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-8a40a52a-b02f-4d2f-ab85-4a34ffad163f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4252406392 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_kmac_err_chk.4252406392 |
| Directory | /workspace/25.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.760040559 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1805216533 ps |
| CPU time | 11.03 seconds |
| Started | Jan 21 09:36:12 PM PST 24 |
| Finished | Jan 21 09:36:26 PM PST 24 |
| Peak memory | 211260 kb |
| Host | smart-e819812a-ad3f-4ae5-bab3-d3d713d12735 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=760040559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.760040559 |
| Directory | /workspace/25.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all.3847204330 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 6206061036 ps |
| CPU time | 63.78 seconds |
| Started | Jan 21 09:08:23 PM PST 24 |
| Finished | Jan 21 09:09:50 PM PST 24 |
| Peak memory | 219536 kb |
| Host | smart-1344ec41-8811-41ba-bbd0-3e4719ce5d14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847204330 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 25.rom_ctrl_stress_all.3847204330 |
| Directory | /workspace/25.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.rom_ctrl_stress_all_with_rand_reset.1773688727 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 167192281163 ps |
| CPU time | 3172.9 seconds |
| Started | Jan 21 09:08:32 PM PST 24 |
| Finished | Jan 21 10:01:45 PM PST 24 |
| Peak memory | 252360 kb |
| Host | smart-e4b240d8-9120-4427-af30-429117e7f797 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773688727 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_stress_all_with_rand_reset.1773688727 |
| Directory | /workspace/25.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_alert_test.4199455855 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 489881220 ps |
| CPU time | 4.27 seconds |
| Started | Jan 21 09:08:38 PM PST 24 |
| Finished | Jan 21 09:09:00 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-72e58ec2-6f2b-4278-9d34-c558e17d9e31 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199455855 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.4199455855 |
| Directory | /workspace/26.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.2993226103 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 103434206170 ps |
| CPU time | 244.14 seconds |
| Started | Jan 21 09:08:33 PM PST 24 |
| Finished | Jan 21 09:12:56 PM PST 24 |
| Peak memory | 237212 kb |
| Host | smart-a4b0cc25-91a9-4678-9afa-e15874d4b8f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993226103 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_ corrupt_sig_fatal_chk.2993226103 |
| Directory | /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.4155064148 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 1106000846 ps |
| CPU time | 9.46 seconds |
| Started | Jan 21 09:08:30 PM PST 24 |
| Finished | Jan 21 09:09:00 PM PST 24 |
| Peak memory | 211712 kb |
| Host | smart-cb81a97e-57cc-45e3-8fb6-f71b3fa84f50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155064148 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.4155064148 |
| Directory | /workspace/26.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.152752563 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8081259425 ps |
| CPU time | 17.34 seconds |
| Started | Jan 21 09:08:38 PM PST 24 |
| Finished | Jan 21 09:09:13 PM PST 24 |
| Peak memory | 211100 kb |
| Host | smart-37107960-e06b-4f60-90e5-81835dbed7d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=152752563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.152752563 |
| Directory | /workspace/26.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_smoke.138266760 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2481458240 ps |
| CPU time | 17.66 seconds |
| Started | Jan 21 09:53:48 PM PST 24 |
| Finished | Jan 21 09:54:10 PM PST 24 |
| Peak memory | 213712 kb |
| Host | smart-88548092-9e1c-4342-abb2-15df8b19aff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=138266760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.138266760 |
| Directory | /workspace/26.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.rom_ctrl_stress_all.1450429657 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1715653709 ps |
| CPU time | 53.59 seconds |
| Started | Jan 21 09:44:13 PM PST 24 |
| Finished | Jan 21 09:45:11 PM PST 24 |
| Peak memory | 216004 kb |
| Host | smart-f12a8d0b-967f-44ff-a9e2-35683c596f2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450429657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 26.rom_ctrl_stress_all.1450429657 |
| Directory | /workspace/26.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_alert_test.1678538832 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 1636085901 ps |
| CPU time | 9.84 seconds |
| Started | Jan 21 09:08:46 PM PST 24 |
| Finished | Jan 21 09:09:09 PM PST 24 |
| Peak memory | 211208 kb |
| Host | smart-39fc3d69-d682-4454-9858-e1e4c4e99e36 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678538832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.1678538832 |
| Directory | /workspace/27.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.3380084437 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 106319868935 ps |
| CPU time | 553.64 seconds |
| Started | Jan 21 09:08:43 PM PST 24 |
| Finished | Jan 21 09:18:12 PM PST 24 |
| Peak memory | 233976 kb |
| Host | smart-90e3e9ee-b420-4ae8-90b8-5bdac9e96eec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380084437 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_ corrupt_sig_fatal_chk.3380084437 |
| Directory | /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.3824543074 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 11605222972 ps |
| CPU time | 26.52 seconds |
| Started | Jan 21 09:08:43 PM PST 24 |
| Finished | Jan 21 09:09:25 PM PST 24 |
| Peak memory | 211756 kb |
| Host | smart-30005f3b-dc85-4038-b8be-d5a4ec3cd033 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824543074 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.3824543074 |
| Directory | /workspace/27.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.3111632875 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 98199472 ps |
| CPU time | 5.54 seconds |
| Started | Jan 21 09:08:33 PM PST 24 |
| Finished | Jan 21 09:08:57 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-a197026e-22d2-4bb6-9938-d2239aa16824 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3111632875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.3111632875 |
| Directory | /workspace/27.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_smoke.2515616631 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 11174688077 ps |
| CPU time | 28.33 seconds |
| Started | Jan 21 09:08:29 PM PST 24 |
| Finished | Jan 21 09:09:18 PM PST 24 |
| Peak memory | 213444 kb |
| Host | smart-64e67266-ffcd-44b8-a725-2be9153aa251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515616631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2515616631 |
| Directory | /workspace/27.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.rom_ctrl_stress_all.2828858845 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3895573319 ps |
| CPU time | 42.51 seconds |
| Started | Jan 21 10:20:57 PM PST 24 |
| Finished | Jan 21 10:21:56 PM PST 24 |
| Peak memory | 213392 kb |
| Host | smart-3617d524-85d7-4ff4-8b84-cc4a32290c31 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828858845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 27.rom_ctrl_stress_all.2828858845 |
| Directory | /workspace/27.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_alert_test.3088516969 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 7194303643 ps |
| CPU time | 15.74 seconds |
| Started | Jan 21 09:08:44 PM PST 24 |
| Finished | Jan 21 09:09:14 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-2db923ed-07c6-4586-a1c0-5fd18fc724f5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088516969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.3088516969 |
| Directory | /workspace/28.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.1963947821 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 15509007289 ps |
| CPU time | 244.76 seconds |
| Started | Jan 21 09:08:43 PM PST 24 |
| Finished | Jan 21 09:13:03 PM PST 24 |
| Peak memory | 236868 kb |
| Host | smart-fbecf9fd-e740-401c-89f1-4140daf3733b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963947821 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_ corrupt_sig_fatal_chk.1963947821 |
| Directory | /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.3882863581 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3304316943 ps |
| CPU time | 29.34 seconds |
| Started | Jan 21 09:08:43 PM PST 24 |
| Finished | Jan 21 09:09:28 PM PST 24 |
| Peak memory | 211416 kb |
| Host | smart-eaecc1fc-8e8c-420e-bcff-253c0ba9f5f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882863581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.3882863581 |
| Directory | /workspace/28.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.2168339040 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1087360408 ps |
| CPU time | 10.66 seconds |
| Started | Jan 21 09:08:42 PM PST 24 |
| Finished | Jan 21 09:09:09 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-0ae193b9-417e-433a-8560-46d6488d5ca2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2168339040 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.2168339040 |
| Directory | /workspace/28.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_smoke.3880401324 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 8966494617 ps |
| CPU time | 19.36 seconds |
| Started | Jan 21 09:08:44 PM PST 24 |
| Finished | Jan 21 09:09:18 PM PST 24 |
| Peak memory | 213992 kb |
| Host | smart-0d881b25-4dcd-4353-86b3-d8b98260e7c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880401324 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.3880401324 |
| Directory | /workspace/28.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all.613748793 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 22418820750 ps |
| CPU time | 32.43 seconds |
| Started | Jan 21 09:08:44 PM PST 24 |
| Finished | Jan 21 09:09:31 PM PST 24 |
| Peak memory | 212664 kb |
| Host | smart-8cd03b93-3059-4f44-88fb-277351ff401a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613748793 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 28.rom_ctrl_stress_all.613748793 |
| Directory | /workspace/28.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2653361202 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 35695782268 ps |
| CPU time | 517.25 seconds |
| Started | Jan 21 09:08:45 PM PST 24 |
| Finished | Jan 21 09:17:36 PM PST 24 |
| Peak memory | 232472 kb |
| Host | smart-a7210a58-6ff0-47ef-a4f7-161df798051f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653361202 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2653361202 |
| Directory | /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_alert_test.209588813 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1901616899 ps |
| CPU time | 14.9 seconds |
| Started | Jan 21 09:08:51 PM PST 24 |
| Finished | Jan 21 09:09:17 PM PST 24 |
| Peak memory | 211312 kb |
| Host | smart-3000ddb1-ad4b-4ee4-87a0-dad9d25b24c2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209588813 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.209588813 |
| Directory | /workspace/29.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2858330183 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 79780133368 ps |
| CPU time | 255.75 seconds |
| Started | Jan 21 09:08:42 PM PST 24 |
| Finished | Jan 21 09:13:14 PM PST 24 |
| Peak memory | 228680 kb |
| Host | smart-a30f5047-b85c-443b-8fe7-09ee3f9c1ca7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858330183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_ corrupt_sig_fatal_chk.2858330183 |
| Directory | /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.1626332591 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6182140316 ps |
| CPU time | 27.01 seconds |
| Started | Jan 21 09:08:51 PM PST 24 |
| Finished | Jan 21 09:09:29 PM PST 24 |
| Peak memory | 213800 kb |
| Host | smart-8f5fdaae-ebab-4432-b410-eb98979eaf28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626332591 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.1626332591 |
| Directory | /workspace/29.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1664617393 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 11168885908 ps |
| CPU time | 11.95 seconds |
| Started | Jan 21 09:08:46 PM PST 24 |
| Finished | Jan 21 09:09:11 PM PST 24 |
| Peak memory | 211420 kb |
| Host | smart-c7fb05c4-c49d-44b9-a1ff-b1ef902d2a2a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1664617393 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1664617393 |
| Directory | /workspace/29.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_smoke.1905850453 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3789794445 ps |
| CPU time | 12.05 seconds |
| Started | Jan 21 09:08:42 PM PST 24 |
| Finished | Jan 21 09:09:10 PM PST 24 |
| Peak memory | 213640 kb |
| Host | smart-b4dc990e-fa27-4089-ae9d-010741b191ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905850453 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.1905850453 |
| Directory | /workspace/29.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all.3825694301 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 9776444322 ps |
| CPU time | 49.72 seconds |
| Started | Jan 21 09:08:45 PM PST 24 |
| Finished | Jan 21 09:09:49 PM PST 24 |
| Peak memory | 219532 kb |
| Host | smart-77bd882f-5015-48b3-8e52-035383b51639 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825694301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 29.rom_ctrl_stress_all.3825694301 |
| Directory | /workspace/29.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.3838454220 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 18965152906 ps |
| CPU time | 1195.56 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:28:57 PM PST 24 |
| Peak memory | 232788 kb |
| Host | smart-1f4b7584-71f2-41ee-b9f1-45847568d5bf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838454220 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.3838454220 |
| Directory | /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_alert_test.2420370984 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 86326522 ps |
| CPU time | 4.4 seconds |
| Started | Jan 21 09:06:32 PM PST 24 |
| Finished | Jan 21 09:06:59 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-df10b63a-da8b-42b3-a6ff-1af42d8ad590 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420370984 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2420370984 |
| Directory | /workspace/3.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1777756937 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1931594530 ps |
| CPU time | 111.64 seconds |
| Started | Jan 21 09:06:27 PM PST 24 |
| Finished | Jan 21 09:08:43 PM PST 24 |
| Peak memory | 211400 kb |
| Host | smart-7d87cff4-84f8-4145-a3fd-ff266229c8ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777756937 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c orrupt_sig_fatal_chk.1777756937 |
| Directory | /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.3842959852 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1158168951 ps |
| CPU time | 17.57 seconds |
| Started | Jan 21 09:06:35 PM PST 24 |
| Finished | Jan 21 09:07:14 PM PST 24 |
| Peak memory | 211472 kb |
| Host | smart-22d75b73-9fa1-43b2-93d2-2c97e4b264da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842959852 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.3842959852 |
| Directory | /workspace/3.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.3909384265 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 197726343 ps |
| CPU time | 5.81 seconds |
| Started | Jan 21 09:06:40 PM PST 24 |
| Finished | Jan 21 09:07:07 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-594c2994-be9f-46f0-b283-d3e8c4bdbb56 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3909384265 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.3909384265 |
| Directory | /workspace/3.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_sec_cm.3671677060 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1082867151 ps |
| CPU time | 98.54 seconds |
| Started | Jan 21 09:06:33 PM PST 24 |
| Finished | Jan 21 09:08:34 PM PST 24 |
| Peak memory | 237012 kb |
| Host | smart-0040d562-77b3-4f48-bfdc-edb16a016e4e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671677060 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.3671677060 |
| Directory | /workspace/3.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_smoke.1889477520 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 288737118 ps |
| CPU time | 11.97 seconds |
| Started | Jan 21 09:06:19 PM PST 24 |
| Finished | Jan 21 09:07:00 PM PST 24 |
| Peak memory | 213708 kb |
| Host | smart-2110124c-5ed0-4ccb-8350-aff897c1497b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1889477520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.1889477520 |
| Directory | /workspace/3.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all.145299044 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 77931495726 ps |
| CPU time | 91.51 seconds |
| Started | Jan 21 09:06:36 PM PST 24 |
| Finished | Jan 21 09:08:29 PM PST 24 |
| Peak memory | 216392 kb |
| Host | smart-573be7d0-2aed-4a5c-ba8c-5fdcea20eabb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145299044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.rom_ctrl_stress_all.145299044 |
| Directory | /workspace/3.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.1678787918 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 160379553808 ps |
| CPU time | 3592.15 seconds |
| Started | Jan 21 09:06:31 PM PST 24 |
| Finished | Jan 21 10:06:47 PM PST 24 |
| Peak memory | 235996 kb |
| Host | smart-24094fcd-b388-413f-8c60-fbb8f9c6b539 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678787918 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_stress_all_with_rand_reset.1678787918 |
| Directory | /workspace/3.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_alert_test.753660188 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1849452772 ps |
| CPU time | 9.9 seconds |
| Started | Jan 21 09:08:48 PM PST 24 |
| Finished | Jan 21 09:09:10 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-58fcd91d-8c60-46b1-a7f7-83f84f6da856 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753660188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.753660188 |
| Directory | /workspace/30.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.1849225731 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 16217848758 ps |
| CPU time | 200.31 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:12:21 PM PST 24 |
| Peak memory | 228600 kb |
| Host | smart-40677de2-3703-4962-8598-fbee765b1172 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849225731 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_ corrupt_sig_fatal_chk.1849225731 |
| Directory | /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.4102424532 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 4867049837 ps |
| CPU time | 18.65 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:09:20 PM PST 24 |
| Peak memory | 211772 kb |
| Host | smart-773cede4-b8fb-41b8-a4a9-1fe04720dafb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4102424532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.4102424532 |
| Directory | /workspace/30.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.2174989073 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4912423575 ps |
| CPU time | 12.53 seconds |
| Started | Jan 21 09:41:32 PM PST 24 |
| Finished | Jan 21 09:41:46 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-f2e72a11-b361-4c04-8270-bb94c42bd9ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2174989073 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.2174989073 |
| Directory | /workspace/30.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_smoke.2560395638 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3037962402 ps |
| CPU time | 27.05 seconds |
| Started | Jan 21 09:38:51 PM PST 24 |
| Finished | Jan 21 09:39:19 PM PST 24 |
| Peak memory | 219596 kb |
| Host | smart-c18b5e7a-00be-4296-8c02-68ca7f196f57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560395638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.2560395638 |
| Directory | /workspace/30.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.rom_ctrl_stress_all.451026756 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3813622019 ps |
| CPU time | 13.11 seconds |
| Started | Jan 21 09:08:51 PM PST 24 |
| Finished | Jan 21 09:09:15 PM PST 24 |
| Peak memory | 211192 kb |
| Host | smart-d816e458-75c8-47fd-8f24-46016845b98e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451026756 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.rom_ctrl_stress_all.451026756 |
| Directory | /workspace/30.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_alert_test.1311293692 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2986156661 ps |
| CPU time | 7.82 seconds |
| Started | Jan 21 09:08:50 PM PST 24 |
| Finished | Jan 21 09:09:09 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-dddd0203-354b-4dca-acb7-2e5c11945038 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311293692 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1311293692 |
| Directory | /workspace/31.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.1381395454 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 388545768610 ps |
| CPU time | 323.48 seconds |
| Started | Jan 21 09:51:03 PM PST 24 |
| Finished | Jan 21 09:56:28 PM PST 24 |
| Peak memory | 240884 kb |
| Host | smart-040f7e3d-b620-4f7f-833c-5e939fbb5ffe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381395454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_ corrupt_sig_fatal_chk.1381395454 |
| Directory | /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.3143470075 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 1003313408 ps |
| CPU time | 13.94 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:09:15 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-4d4d21a4-ebfa-4f6f-844e-c330904007c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143470075 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.3143470075 |
| Directory | /workspace/31.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2000054866 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1416741674 ps |
| CPU time | 8.11 seconds |
| Started | Jan 21 09:08:48 PM PST 24 |
| Finished | Jan 21 09:09:08 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-77d0efd3-b195-4c1e-8129-d60770d36f74 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2000054866 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2000054866 |
| Directory | /workspace/31.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_smoke.377349242 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 17705789514 ps |
| CPU time | 48.92 seconds |
| Started | Jan 21 09:08:48 PM PST 24 |
| Finished | Jan 21 09:09:49 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-21e3aee2-7c58-446f-82cb-c2ad870e6ffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377349242 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.377349242 |
| Directory | /workspace/31.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all.1631342940 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2303029188 ps |
| CPU time | 34.65 seconds |
| Started | Jan 21 09:08:51 PM PST 24 |
| Finished | Jan 21 09:09:37 PM PST 24 |
| Peak memory | 216632 kb |
| Host | smart-d2a38f4b-8751-41ad-aa7d-3f058c8e7e39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631342940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 31.rom_ctrl_stress_all.1631342940 |
| Directory | /workspace/31.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.72902479 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 32551049607 ps |
| CPU time | 2182.28 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:45:24 PM PST 24 |
| Peak memory | 235980 kb |
| Host | smart-62ee7d7f-1c36-4404-9843-d07775faffc4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72902479 -assert nopos tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.72902479 |
| Directory | /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_alert_test.894943058 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 8555760630 ps |
| CPU time | 16.13 seconds |
| Started | Jan 21 09:09:04 PM PST 24 |
| Finished | Jan 21 09:09:28 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-23422555-a9bf-45e6-b608-85c3fe6887eb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894943058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.894943058 |
| Directory | /workspace/32.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.259469014 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 23470483209 ps |
| CPU time | 243.29 seconds |
| Started | Jan 21 09:08:59 PM PST 24 |
| Finished | Jan 21 09:13:12 PM PST 24 |
| Peak memory | 212532 kb |
| Host | smart-97e5a524-5eff-4dbb-8c61-4ea1fac23935 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259469014 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_c orrupt_sig_fatal_chk.259469014 |
| Directory | /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3403625962 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3455926930 ps |
| CPU time | 30.2 seconds |
| Started | Jan 21 09:08:59 PM PST 24 |
| Finished | Jan 21 09:09:38 PM PST 24 |
| Peak memory | 211504 kb |
| Host | smart-88cb00b2-4028-45fd-96e9-711a53d492e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403625962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3403625962 |
| Directory | /workspace/32.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.3550180305 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6989983992 ps |
| CPU time | 16.39 seconds |
| Started | Jan 21 09:08:57 PM PST 24 |
| Finished | Jan 21 09:09:24 PM PST 24 |
| Peak memory | 211392 kb |
| Host | smart-aa7e206e-e274-4d02-8052-433afa35dab9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3550180305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.3550180305 |
| Directory | /workspace/32.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_smoke.3960864889 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2015282941 ps |
| CPU time | 10.17 seconds |
| Started | Jan 21 09:08:49 PM PST 24 |
| Finished | Jan 21 09:09:11 PM PST 24 |
| Peak memory | 213276 kb |
| Host | smart-c9a3f4b9-c6f0-4d52-9820-162f337d509e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960864889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.3960864889 |
| Directory | /workspace/32.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.rom_ctrl_stress_all.513880229 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 6138546278 ps |
| CPU time | 20.67 seconds |
| Started | Jan 21 09:08:58 PM PST 24 |
| Finished | Jan 21 09:09:28 PM PST 24 |
| Peak memory | 211192 kb |
| Host | smart-657c92d8-1f68-4432-816f-41371688df75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513880229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 32.rom_ctrl_stress_all.513880229 |
| Directory | /workspace/32.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_alert_test.2051683479 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 5184124626 ps |
| CPU time | 12.05 seconds |
| Started | Jan 21 09:09:09 PM PST 24 |
| Finished | Jan 21 09:09:29 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-3d7b720c-102d-4214-8ac1-5bd31bd8f03e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051683479 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.2051683479 |
| Directory | /workspace/33.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.1179757878 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 137371301733 ps |
| CPU time | 383.98 seconds |
| Started | Jan 21 09:09:02 PM PST 24 |
| Finished | Jan 21 09:15:35 PM PST 24 |
| Peak memory | 237912 kb |
| Host | smart-76802497-6a36-4898-826c-c069f4cf1a83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179757878 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_ corrupt_sig_fatal_chk.1179757878 |
| Directory | /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.1669901163 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2821393137 ps |
| CPU time | 25.64 seconds |
| Started | Jan 21 09:09:01 PM PST 24 |
| Finished | Jan 21 09:09:36 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-770564e2-3985-4902-9ffa-f4047a842e35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1669901163 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.1669901163 |
| Directory | /workspace/33.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.3244281213 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 467056101 ps |
| CPU time | 5.62 seconds |
| Started | Jan 21 09:08:57 PM PST 24 |
| Finished | Jan 21 09:09:12 PM PST 24 |
| Peak memory | 211560 kb |
| Host | smart-6cb3d112-6f5e-437d-9659-825478257158 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3244281213 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.3244281213 |
| Directory | /workspace/33.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_smoke.2289863252 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 2088516430 ps |
| CPU time | 25.61 seconds |
| Started | Jan 21 09:09:00 PM PST 24 |
| Finished | Jan 21 09:09:35 PM PST 24 |
| Peak memory | 212712 kb |
| Host | smart-db19f13e-7ae9-4185-8e1d-92ca281c36b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289863252 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.2289863252 |
| Directory | /workspace/33.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all.1043833126 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 421921865 ps |
| CPU time | 23.73 seconds |
| Started | Jan 21 09:09:04 PM PST 24 |
| Finished | Jan 21 09:09:36 PM PST 24 |
| Peak memory | 214764 kb |
| Host | smart-c00fb4f2-67af-45db-940c-1452f9d85650 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043833126 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.rom_ctrl_stress_all.1043833126 |
| Directory | /workspace/33.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.rom_ctrl_stress_all_with_rand_reset.1980996269 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 144571309650 ps |
| CPU time | 10426.1 seconds |
| Started | Jan 21 09:55:13 PM PST 24 |
| Finished | Jan 22 12:49:10 AM PST 24 |
| Peak memory | 236096 kb |
| Host | smart-9496ba06-a31f-4764-8db4-dd97533ff5dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980996269 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_stress_all_with_rand_reset.1980996269 |
| Directory | /workspace/33.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_alert_test.2413379682 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 940450969 ps |
| CPU time | 9.87 seconds |
| Started | Jan 21 09:09:13 PM PST 24 |
| Finished | Jan 21 09:09:30 PM PST 24 |
| Peak memory | 211304 kb |
| Host | smart-c8ff1b47-049f-430b-b8b8-4360588424aa |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413379682 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.2413379682 |
| Directory | /workspace/34.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.2105268351 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 52455897466 ps |
| CPU time | 142.58 seconds |
| Started | Jan 21 09:09:08 PM PST 24 |
| Finished | Jan 21 09:11:38 PM PST 24 |
| Peak memory | 212048 kb |
| Host | smart-26f2c0ea-3bbe-47b8-89b9-42ac724041d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105268351 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_ corrupt_sig_fatal_chk.2105268351 |
| Directory | /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2896531065 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 15426315699 ps |
| CPU time | 33.04 seconds |
| Started | Jan 21 09:09:03 PM PST 24 |
| Finished | Jan 21 09:09:45 PM PST 24 |
| Peak memory | 211756 kb |
| Host | smart-b1ffde7d-57cd-492e-b8d2-cf3995189bfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896531065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2896531065 |
| Directory | /workspace/34.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.3200332563 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 7012200876 ps |
| CPU time | 12.7 seconds |
| Started | Jan 21 09:09:04 PM PST 24 |
| Finished | Jan 21 09:09:25 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-6d053a8a-6b75-4936-b91b-27e1cd953e83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3200332563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.3200332563 |
| Directory | /workspace/34.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_smoke.2280375067 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 8586967648 ps |
| CPU time | 24.73 seconds |
| Started | Jan 21 09:09:06 PM PST 24 |
| Finished | Jan 21 09:09:38 PM PST 24 |
| Peak memory | 213144 kb |
| Host | smart-e66e046e-d468-4047-b10e-81b649bfb538 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280375067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.2280375067 |
| Directory | /workspace/34.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all.1509388182 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 2423754917 ps |
| CPU time | 15.55 seconds |
| Started | Jan 21 09:09:05 PM PST 24 |
| Finished | Jan 21 09:09:28 PM PST 24 |
| Peak memory | 214856 kb |
| Host | smart-0d2b0fde-0719-45c5-ae14-7431723ddff0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509388182 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.rom_ctrl_stress_all.1509388182 |
| Directory | /workspace/34.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.2782341862 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 93366172425 ps |
| CPU time | 9178.07 seconds |
| Started | Jan 21 09:09:07 PM PST 24 |
| Finished | Jan 21 11:42:13 PM PST 24 |
| Peak memory | 232328 kb |
| Host | smart-951baa15-47ce-4b62-a095-5435af1d0002 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782341862 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.2782341862 |
| Directory | /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_alert_test.1641038319 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1553796690 ps |
| CPU time | 10.13 seconds |
| Started | Jan 21 09:09:18 PM PST 24 |
| Finished | Jan 21 09:09:35 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-2d126377-2fd6-48b7-95b3-681864fe4687 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641038319 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.1641038319 |
| Directory | /workspace/35.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.611540112 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 105888175295 ps |
| CPU time | 283.52 seconds |
| Started | Jan 21 09:59:06 PM PST 24 |
| Finished | Jan 21 10:03:52 PM PST 24 |
| Peak memory | 232708 kb |
| Host | smart-7432a047-a67b-4fda-b464-1104aada2b48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611540112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_c orrupt_sig_fatal_chk.611540112 |
| Directory | /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.1870051914 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 20925443314 ps |
| CPU time | 21.72 seconds |
| Started | Jan 21 09:09:08 PM PST 24 |
| Finished | Jan 21 09:09:38 PM PST 24 |
| Peak memory | 211804 kb |
| Host | smart-626eb73f-66e0-4657-afb0-9cab7192fd92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1870051914 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.1870051914 |
| Directory | /workspace/35.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_max_throughput_chk.1125293820 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3435011708 ps |
| CPU time | 10.4 seconds |
| Started | Jan 21 09:09:13 PM PST 24 |
| Finished | Jan 21 09:09:31 PM PST 24 |
| Peak memory | 211436 kb |
| Host | smart-416509af-33b2-407c-ae96-3f8ee6c53f1e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1125293820 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_max_throughput_chk.1125293820 |
| Directory | /workspace/35.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_smoke.3847929735 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2394034462 ps |
| CPU time | 24.93 seconds |
| Started | Jan 21 09:09:14 PM PST 24 |
| Finished | Jan 21 09:09:46 PM PST 24 |
| Peak memory | 212568 kb |
| Host | smart-905c78a6-c65c-4589-bc83-207a75fda488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847929735 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.3847929735 |
| Directory | /workspace/35.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.rom_ctrl_stress_all.447325728 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2201518835 ps |
| CPU time | 30.47 seconds |
| Started | Jan 21 09:09:13 PM PST 24 |
| Finished | Jan 21 09:09:51 PM PST 24 |
| Peak memory | 215132 kb |
| Host | smart-bd669ce2-4175-4ac2-9827-0befe3bef0f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447325728 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.rom_ctrl_stress_all.447325728 |
| Directory | /workspace/35.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_alert_test.41660639 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1984093572 ps |
| CPU time | 15.98 seconds |
| Started | Jan 21 09:46:45 PM PST 24 |
| Finished | Jan 21 09:47:05 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-6a0c3db6-457e-4aed-8e59-545ec7dc8133 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41660639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.41660639 |
| Directory | /workspace/36.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.1080088153 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 90540049603 ps |
| CPU time | 240.55 seconds |
| Started | Jan 21 09:09:18 PM PST 24 |
| Finished | Jan 21 09:13:25 PM PST 24 |
| Peak memory | 233788 kb |
| Host | smart-efb97b78-9918-43ed-afe0-522a5b1bc77a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080088153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_ corrupt_sig_fatal_chk.1080088153 |
| Directory | /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.1744876153 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7372938206 ps |
| CPU time | 30.86 seconds |
| Started | Jan 21 09:09:16 PM PST 24 |
| Finished | Jan 21 09:09:54 PM PST 24 |
| Peak memory | 212404 kb |
| Host | smart-a915e96d-9a79-42d8-bed4-ab1a92008a7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744876153 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.1744876153 |
| Directory | /workspace/36.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.664057195 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 358980274 ps |
| CPU time | 5.27 seconds |
| Started | Jan 21 09:42:09 PM PST 24 |
| Finished | Jan 21 09:42:19 PM PST 24 |
| Peak memory | 211292 kb |
| Host | smart-4bc0d03e-57d8-44d4-badf-85fef91b0526 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=664057195 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.664057195 |
| Directory | /workspace/36.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_smoke.1037665160 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 23023914607 ps |
| CPU time | 24.63 seconds |
| Started | Jan 21 09:09:17 PM PST 24 |
| Finished | Jan 21 09:09:48 PM PST 24 |
| Peak memory | 213372 kb |
| Host | smart-576ab7e8-a60a-4e5b-98c1-1e37462798df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037665160 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.1037665160 |
| Directory | /workspace/36.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.rom_ctrl_stress_all.546079241 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5940290294 ps |
| CPU time | 45.5 seconds |
| Started | Jan 21 09:09:17 PM PST 24 |
| Finished | Jan 21 09:10:09 PM PST 24 |
| Peak memory | 215684 kb |
| Host | smart-5ae3a4c8-5a4f-4c36-9fa6-55aedaa6dd15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546079241 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 36.rom_ctrl_stress_all.546079241 |
| Directory | /workspace/36.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_alert_test.660831683 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2157425260 ps |
| CPU time | 16.31 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 21 09:09:46 PM PST 24 |
| Peak memory | 211344 kb |
| Host | smart-41a55f36-03c3-44ff-a1bf-356e9b0e0ee0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660831683 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.660831683 |
| Directory | /workspace/37.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.4286824432 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 104490942889 ps |
| CPU time | 471.34 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 21 09:17:21 PM PST 24 |
| Peak memory | 237900 kb |
| Host | smart-fe6cfa1a-a81c-4bdd-a764-dfdf07925fa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286824432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_ corrupt_sig_fatal_chk.4286824432 |
| Directory | /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.2020693674 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 168735338 ps |
| CPU time | 9.47 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 21 09:09:39 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-dce5dd99-24dc-4243-a86f-18599a8b197f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020693674 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.2020693674 |
| Directory | /workspace/37.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.3950160554 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3993837188 ps |
| CPU time | 11.66 seconds |
| Started | Jan 21 09:09:17 PM PST 24 |
| Finished | Jan 21 09:09:35 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-d0630520-f346-496c-a8ea-0f4ed30b8989 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3950160554 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.3950160554 |
| Directory | /workspace/37.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_smoke.1373599191 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 620341124 ps |
| CPU time | 14.24 seconds |
| Started | Jan 21 09:09:18 PM PST 24 |
| Finished | Jan 21 09:09:39 PM PST 24 |
| Peak memory | 213168 kb |
| Host | smart-a8140b3d-6bbd-4557-aebb-292888985b0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1373599191 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.1373599191 |
| Directory | /workspace/37.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all.3883689418 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4744285693 ps |
| CPU time | 48.98 seconds |
| Started | Jan 21 09:09:19 PM PST 24 |
| Finished | Jan 21 09:10:14 PM PST 24 |
| Peak memory | 212720 kb |
| Host | smart-77aa2a3a-9c5f-457a-9793-3a04487c7fd9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883689418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 37.rom_ctrl_stress_all.3883689418 |
| Directory | /workspace/37.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1984619207 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 10215008690 ps |
| CPU time | 920.41 seconds |
| Started | Jan 21 09:27:02 PM PST 24 |
| Finished | Jan 21 09:42:33 PM PST 24 |
| Peak memory | 227784 kb |
| Host | smart-e7216a18-1517-476b-b181-1b23f7424379 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984619207 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1984619207 |
| Directory | /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_alert_test.2458656992 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 87271814 ps |
| CPU time | 4.21 seconds |
| Started | Jan 21 09:09:24 PM PST 24 |
| Finished | Jan 21 09:09:33 PM PST 24 |
| Peak memory | 211148 kb |
| Host | smart-27fa876d-d335-4e16-bbee-25b4a8433778 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458656992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.2458656992 |
| Directory | /workspace/38.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.373620621 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 7830502548 ps |
| CPU time | 144.09 seconds |
| Started | Jan 21 10:35:06 PM PST 24 |
| Finished | Jan 21 10:37:34 PM PST 24 |
| Peak memory | 228620 kb |
| Host | smart-ce31f3a0-6aa3-4d14-b161-379164e65008 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373620621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_c orrupt_sig_fatal_chk.373620621 |
| Directory | /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1196700664 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 21182423327 ps |
| CPU time | 25.12 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 21 09:09:55 PM PST 24 |
| Peak memory | 211800 kb |
| Host | smart-f36a6fba-52e3-4506-9df8-b37be7523cb9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196700664 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1196700664 |
| Directory | /workspace/38.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.4089373461 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 7522618883 ps |
| CPU time | 13.49 seconds |
| Started | Jan 21 09:09:26 PM PST 24 |
| Finished | Jan 21 09:09:45 PM PST 24 |
| Peak memory | 211412 kb |
| Host | smart-e171546a-e35e-4e2f-896f-562e2629fc6a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4089373461 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.4089373461 |
| Directory | /workspace/38.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_smoke.3899278428 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 2490274762 ps |
| CPU time | 23.71 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 21 09:09:53 PM PST 24 |
| Peak memory | 213096 kb |
| Host | smart-d371ed5a-2b52-484f-baf3-986b2b7e9808 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899278428 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3899278428 |
| Directory | /workspace/38.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all.2808545639 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 6430403801 ps |
| CPU time | 17.4 seconds |
| Started | Jan 21 09:09:27 PM PST 24 |
| Finished | Jan 21 09:09:50 PM PST 24 |
| Peak memory | 211900 kb |
| Host | smart-da776481-b93c-4b86-b79c-1d05ad2db21c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808545639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 38.rom_ctrl_stress_all.2808545639 |
| Directory | /workspace/38.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3463250907 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 342357117221 ps |
| CPU time | 10495.2 seconds |
| Started | Jan 21 09:09:25 PM PST 24 |
| Finished | Jan 22 12:04:26 AM PST 24 |
| Peak memory | 245620 kb |
| Host | smart-0110faa8-c92b-4516-a8e5-f1b4b5181a76 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463250907 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3463250907 |
| Directory | /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_alert_test.979183110 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 212764631 ps |
| CPU time | 5.79 seconds |
| Started | Jan 21 09:09:36 PM PST 24 |
| Finished | Jan 21 09:09:44 PM PST 24 |
| Peak memory | 211232 kb |
| Host | smart-f94e25e5-5ea7-4947-8f2a-6cc7373b7809 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979183110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.979183110 |
| Directory | /workspace/39.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.3557209506 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2581859491 ps |
| CPU time | 161.13 seconds |
| Started | Jan 21 09:09:34 PM PST 24 |
| Finished | Jan 21 09:12:19 PM PST 24 |
| Peak memory | 224800 kb |
| Host | smart-13bb6721-650f-42b9-b6db-25d631a2f178 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557209506 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_ corrupt_sig_fatal_chk.3557209506 |
| Directory | /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.2238177635 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2396696034 ps |
| CPU time | 22.24 seconds |
| Started | Jan 21 09:09:35 PM PST 24 |
| Finished | Jan 21 09:10:00 PM PST 24 |
| Peak memory | 211528 kb |
| Host | smart-6d744448-5a53-4553-a617-147075f4b575 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2238177635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.2238177635 |
| Directory | /workspace/39.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.3188344289 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 28524220714 ps |
| CPU time | 16.81 seconds |
| Started | Jan 21 09:09:36 PM PST 24 |
| Finished | Jan 21 09:09:56 PM PST 24 |
| Peak memory | 211388 kb |
| Host | smart-d7b21a96-19a5-49eb-bb62-e83c92004025 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3188344289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.3188344289 |
| Directory | /workspace/39.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_smoke.4081869614 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2567512977 ps |
| CPU time | 23.68 seconds |
| Started | Jan 21 09:09:24 PM PST 24 |
| Finished | Jan 21 09:09:52 PM PST 24 |
| Peak memory | 211456 kb |
| Host | smart-3e0a4d17-9c25-43f1-9239-09e93a3e2e13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081869614 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.4081869614 |
| Directory | /workspace/39.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all.2028246375 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 14305719180 ps |
| CPU time | 90.74 seconds |
| Started | Jan 21 10:02:53 PM PST 24 |
| Finished | Jan 21 10:04:28 PM PST 24 |
| Peak memory | 217616 kb |
| Host | smart-ed86d8c4-cd4b-4d0c-9f2c-05d720819abe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028246375 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 39.rom_ctrl_stress_all.2028246375 |
| Directory | /workspace/39.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.rom_ctrl_stress_all_with_rand_reset.937448739 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 76763474006 ps |
| CPU time | 878.08 seconds |
| Started | Jan 21 09:09:39 PM PST 24 |
| Finished | Jan 21 09:24:20 PM PST 24 |
| Peak memory | 235432 kb |
| Host | smart-53cab0dc-f44f-4931-bb42-f904db3e6011 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937448739 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_stress_all_with_rand_reset.937448739 |
| Directory | /workspace/39.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_alert_test.531290003 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2306961505 ps |
| CPU time | 8.04 seconds |
| Started | Jan 21 09:06:41 PM PST 24 |
| Finished | Jan 21 09:07:10 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-338df86c-3a93-4197-ae36-3a08124e269a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531290003 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.531290003 |
| Directory | /workspace/4.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.678229217 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 35557342471 ps |
| CPU time | 190.69 seconds |
| Started | Jan 21 09:06:29 PM PST 24 |
| Finished | Jan 21 09:10:03 PM PST 24 |
| Peak memory | 225156 kb |
| Host | smart-53056b3e-b0a7-41c5-83d1-fca6fe9c49a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678229217 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co rrupt_sig_fatal_chk.678229217 |
| Directory | /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.3013174326 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 4023724284 ps |
| CPU time | 27.68 seconds |
| Started | Jan 21 09:06:32 PM PST 24 |
| Finished | Jan 21 09:07:23 PM PST 24 |
| Peak memory | 211512 kb |
| Host | smart-b71fc954-f8e0-4047-b30a-351651c9609b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3013174326 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.3013174326 |
| Directory | /workspace/4.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.112459574 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 7520447893 ps |
| CPU time | 16.39 seconds |
| Started | Jan 21 09:06:31 PM PST 24 |
| Finished | Jan 21 09:07:11 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-bfe023a4-75d9-45f4-a3fe-7a4e14f278b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=112459574 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.112459574 |
| Directory | /workspace/4.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_sec_cm.1470202788 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 856019898 ps |
| CPU time | 98.21 seconds |
| Started | Jan 21 09:06:40 PM PST 24 |
| Finished | Jan 21 09:08:40 PM PST 24 |
| Peak memory | 235780 kb |
| Host | smart-5a4bf5c9-05f0-4502-8138-b1b9d16e2175 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470202788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.1470202788 |
| Directory | /workspace/4.rom_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_smoke.1398009087 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 185688123 ps |
| CPU time | 10.32 seconds |
| Started | Jan 21 09:06:30 PM PST 24 |
| Finished | Jan 21 09:07:04 PM PST 24 |
| Peak memory | 213420 kb |
| Host | smart-6c3b38b8-9977-4645-8b43-1fb8260cd862 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398009087 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1398009087 |
| Directory | /workspace/4.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all.547578872 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1177390572 ps |
| CPU time | 24.89 seconds |
| Started | Jan 21 09:06:27 PM PST 24 |
| Finished | Jan 21 09:07:16 PM PST 24 |
| Peak memory | 215788 kb |
| Host | smart-43d52f3c-5714-4265-9baf-bd9c4cd8eefc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547578872 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.rom_ctrl_stress_all.547578872 |
| Directory | /workspace/4.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1274364393 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6829960049 ps |
| CPU time | 892.84 seconds |
| Started | Jan 21 09:06:40 PM PST 24 |
| Finished | Jan 21 09:21:54 PM PST 24 |
| Peak memory | 228064 kb |
| Host | smart-d6691b20-a41a-4b77-a09b-a6462e507e05 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274364393 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.1274364393 |
| Directory | /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_alert_test.2735249435 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 6546812040 ps |
| CPU time | 13.69 seconds |
| Started | Jan 21 09:09:51 PM PST 24 |
| Finished | Jan 21 09:10:06 PM PST 24 |
| Peak memory | 211252 kb |
| Host | smart-f0f26304-e108-40f4-a1ae-d4b88997a1f6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735249435 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.2735249435 |
| Directory | /workspace/40.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.3047729599 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 216344705607 ps |
| CPU time | 315.75 seconds |
| Started | Jan 21 09:09:52 PM PST 24 |
| Finished | Jan 21 09:15:10 PM PST 24 |
| Peak memory | 236860 kb |
| Host | smart-1f333edf-4524-4da9-856f-70aaf073c41d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047729599 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_ corrupt_sig_fatal_chk.3047729599 |
| Directory | /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.2972781201 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4578091301 ps |
| CPU time | 23.8 seconds |
| Started | Jan 21 09:09:48 PM PST 24 |
| Finished | Jan 21 09:10:15 PM PST 24 |
| Peak memory | 211888 kb |
| Host | smart-8bdd1b6c-818f-44ff-a0c9-6b9bfbaafa74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2972781201 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.2972781201 |
| Directory | /workspace/40.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1842430745 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1283559089 ps |
| CPU time | 9.62 seconds |
| Started | Jan 21 09:09:40 PM PST 24 |
| Finished | Jan 21 09:09:53 PM PST 24 |
| Peak memory | 211528 kb |
| Host | smart-ba98302c-2e02-4874-9aca-80b0c6714760 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1842430745 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1842430745 |
| Directory | /workspace/40.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_smoke.3619681143 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 78817849203 ps |
| CPU time | 32.84 seconds |
| Started | Jan 21 09:09:35 PM PST 24 |
| Finished | Jan 21 09:10:10 PM PST 24 |
| Peak memory | 212996 kb |
| Host | smart-6d00578d-5e4c-47b2-af1e-a3028cf0f02a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619681143 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.3619681143 |
| Directory | /workspace/40.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all.592248865 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 1707906190 ps |
| CPU time | 15.38 seconds |
| Started | Jan 21 09:09:40 PM PST 24 |
| Finished | Jan 21 09:09:58 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-2ab56978-c4d1-4247-b306-4c52ebaf041e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592248865 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 40.rom_ctrl_stress_all.592248865 |
| Directory | /workspace/40.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1547570277 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 78138384456 ps |
| CPU time | 7603.43 seconds |
| Started | Jan 21 09:09:49 PM PST 24 |
| Finished | Jan 21 11:16:35 PM PST 24 |
| Peak memory | 233192 kb |
| Host | smart-efa24efa-d716-4560-8acc-38785d1e446e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547570277 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1547570277 |
| Directory | /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_alert_test.3283548048 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8694364422 ps |
| CPU time | 16.15 seconds |
| Started | Jan 21 09:10:04 PM PST 24 |
| Finished | Jan 21 09:10:39 PM PST 24 |
| Peak memory | 211520 kb |
| Host | smart-14d7d021-970f-4bbc-9752-df16bdd6a54c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283548048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.3283548048 |
| Directory | /workspace/41.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1660286958 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 41633498220 ps |
| CPU time | 366.49 seconds |
| Started | Jan 21 09:09:50 PM PST 24 |
| Finished | Jan 21 09:15:58 PM PST 24 |
| Peak memory | 228656 kb |
| Host | smart-f5179abb-65b5-4043-8541-b60a13c5c6ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660286958 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_ corrupt_sig_fatal_chk.1660286958 |
| Directory | /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.2373015299 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 1725924313 ps |
| CPU time | 19.83 seconds |
| Started | Jan 21 09:09:49 PM PST 24 |
| Finished | Jan 21 09:10:11 PM PST 24 |
| Peak memory | 211504 kb |
| Host | smart-027017f1-fc81-41b2-ae65-c21c7ac12626 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2373015299 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.2373015299 |
| Directory | /workspace/41.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.630637677 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 95346095 ps |
| CPU time | 5.44 seconds |
| Started | Jan 21 09:09:48 PM PST 24 |
| Finished | Jan 21 09:09:56 PM PST 24 |
| Peak memory | 211348 kb |
| Host | smart-0060e55c-47e2-4d03-9813-ecd613435ce0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=630637677 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.630637677 |
| Directory | /workspace/41.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_smoke.1871985853 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5923957920 ps |
| CPU time | 23.24 seconds |
| Started | Jan 21 09:09:50 PM PST 24 |
| Finished | Jan 21 09:10:15 PM PST 24 |
| Peak memory | 213928 kb |
| Host | smart-7ad102bb-ca64-41a0-9583-51417e135e6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871985853 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.1871985853 |
| Directory | /workspace/41.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.rom_ctrl_stress_all.3146731548 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 49469725532 ps |
| CPU time | 126.55 seconds |
| Started | Jan 21 09:09:49 PM PST 24 |
| Finished | Jan 21 09:11:58 PM PST 24 |
| Peak memory | 219564 kb |
| Host | smart-223dc88a-06e0-4bf7-8e2f-01cba97d46cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146731548 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 41.rom_ctrl_stress_all.3146731548 |
| Directory | /workspace/41.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_alert_test.4279765505 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1640364290 ps |
| CPU time | 14.17 seconds |
| Started | Jan 21 09:10:04 PM PST 24 |
| Finished | Jan 21 09:10:37 PM PST 24 |
| Peak memory | 211440 kb |
| Host | smart-270ff7ef-85c0-4214-8534-7ad9e829f1b4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279765505 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.4279765505 |
| Directory | /workspace/42.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.3182425531 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4588651173 ps |
| CPU time | 189.31 seconds |
| Started | Jan 21 09:10:02 PM PST 24 |
| Finished | Jan 21 09:13:32 PM PST 24 |
| Peak memory | 237804 kb |
| Host | smart-5a8674e4-0c50-4cdf-bfca-aa700bf4cd3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182425531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_ corrupt_sig_fatal_chk.3182425531 |
| Directory | /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.3808231558 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 692790989 ps |
| CPU time | 9.48 seconds |
| Started | Jan 21 09:10:03 PM PST 24 |
| Finished | Jan 21 09:10:32 PM PST 24 |
| Peak memory | 211396 kb |
| Host | smart-bd94e7e7-c56b-4330-85d0-686d07d8cda0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808231558 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.3808231558 |
| Directory | /workspace/42.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.913481691 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1627393313 ps |
| CPU time | 14.84 seconds |
| Started | Jan 21 09:10:06 PM PST 24 |
| Finished | Jan 21 09:10:39 PM PST 24 |
| Peak memory | 211288 kb |
| Host | smart-0c7083d7-0e33-4504-b61f-69392912bd99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=913481691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.913481691 |
| Directory | /workspace/42.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_smoke.3772046977 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 6718262648 ps |
| CPU time | 27.86 seconds |
| Started | Jan 21 09:10:05 PM PST 24 |
| Finished | Jan 21 09:10:52 PM PST 24 |
| Peak memory | 213936 kb |
| Host | smart-f71ef05b-009f-446e-8acb-733d2a3acab5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3772046977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.3772046977 |
| Directory | /workspace/42.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.rom_ctrl_stress_all.1027266477 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 31686399206 ps |
| CPU time | 41.8 seconds |
| Started | Jan 21 09:10:07 PM PST 24 |
| Finished | Jan 21 09:11:08 PM PST 24 |
| Peak memory | 217104 kb |
| Host | smart-183da54e-3291-404f-a50a-2605783d8aa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027266477 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 42.rom_ctrl_stress_all.1027266477 |
| Directory | /workspace/42.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_alert_test.3734833635 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4615385105 ps |
| CPU time | 11.27 seconds |
| Started | Jan 21 09:10:04 PM PST 24 |
| Finished | Jan 21 09:10:35 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-6121530c-626f-453d-85f9-898ec9a5f204 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734833635 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3734833635 |
| Directory | /workspace/43.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1184562625 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 40107727316 ps |
| CPU time | 235.05 seconds |
| Started | Jan 21 09:10:03 PM PST 24 |
| Finished | Jan 21 09:14:18 PM PST 24 |
| Peak memory | 237848 kb |
| Host | smart-211aba55-26be-4425-a0e5-e43d4f0a4f9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184562625 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_ corrupt_sig_fatal_chk.1184562625 |
| Directory | /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.567505230 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 755235192 ps |
| CPU time | 9.5 seconds |
| Started | Jan 21 09:10:06 PM PST 24 |
| Finished | Jan 21 09:10:34 PM PST 24 |
| Peak memory | 211516 kb |
| Host | smart-0f854436-affb-4c37-93a8-f3c33cf65855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567505230 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.567505230 |
| Directory | /workspace/43.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.3922756706 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1329265980 ps |
| CPU time | 12.76 seconds |
| Started | Jan 21 09:10:02 PM PST 24 |
| Finished | Jan 21 09:10:35 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-04dd993d-a095-49da-956a-8028296cf285 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3922756706 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.3922756706 |
| Directory | /workspace/43.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_smoke.403108411 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1817400551 ps |
| CPU time | 22.75 seconds |
| Started | Jan 21 09:10:08 PM PST 24 |
| Finished | Jan 21 09:10:49 PM PST 24 |
| Peak memory | 212444 kb |
| Host | smart-03bc3b2a-8c71-410b-8523-62b6b1a63575 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403108411 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.403108411 |
| Directory | /workspace/43.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all.1401088848 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 98741288 ps |
| CPU time | 6.95 seconds |
| Started | Jan 21 09:10:04 PM PST 24 |
| Finished | Jan 21 09:10:30 PM PST 24 |
| Peak memory | 211176 kb |
| Host | smart-f819086c-d160-4b53-b49c-f1934d90e51d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401088848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 43.rom_ctrl_stress_all.1401088848 |
| Directory | /workspace/43.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.rom_ctrl_stress_all_with_rand_reset.2852862745 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 63722836615 ps |
| CPU time | 2508.22 seconds |
| Started | Jan 21 09:10:08 PM PST 24 |
| Finished | Jan 21 09:52:15 PM PST 24 |
| Peak memory | 235968 kb |
| Host | smart-addae884-25c8-4d76-8f93-c674feb43f0a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852862745 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_stress_all_with_rand_reset.2852862745 |
| Directory | /workspace/43.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_alert_test.367791442 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 8023562523 ps |
| CPU time | 16.22 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:10:50 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-fb1723b2-afd8-4b3d-8e9c-0c23ad5d4003 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367791442 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.367791442 |
| Directory | /workspace/44.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.1494098932 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 259125915015 ps |
| CPU time | 283.16 seconds |
| Started | Jan 21 10:05:32 PM PST 24 |
| Finished | Jan 21 10:10:23 PM PST 24 |
| Peak memory | 224708 kb |
| Host | smart-6e92eaa7-8304-4416-a842-4a3f87b5af24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494098932 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_ corrupt_sig_fatal_chk.1494098932 |
| Directory | /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3130132207 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1537101739 ps |
| CPU time | 14.73 seconds |
| Started | Jan 21 09:10:04 PM PST 24 |
| Finished | Jan 21 09:10:37 PM PST 24 |
| Peak memory | 211752 kb |
| Host | smart-0181f7f9-fde4-442c-93e4-060a95d0ba9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130132207 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3130132207 |
| Directory | /workspace/44.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.806458281 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1658850187 ps |
| CPU time | 14.68 seconds |
| Started | Jan 21 09:10:08 PM PST 24 |
| Finished | Jan 21 09:10:41 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-ba33be44-7a1f-4191-9d9d-cbb27b18d7b0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=806458281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.806458281 |
| Directory | /workspace/44.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_smoke.1682145035 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3640022878 ps |
| CPU time | 16.93 seconds |
| Started | Jan 21 09:10:06 PM PST 24 |
| Finished | Jan 21 09:10:41 PM PST 24 |
| Peak memory | 213064 kb |
| Host | smart-be7a895b-4aea-4f58-a1d4-8a4078bfa59b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1682145035 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1682145035 |
| Directory | /workspace/44.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all.1744731798 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4402896869 ps |
| CPU time | 19.3 seconds |
| Started | Jan 21 09:10:03 PM PST 24 |
| Finished | Jan 21 09:10:42 PM PST 24 |
| Peak memory | 214320 kb |
| Host | smart-20c02c32-259e-4104-9a4c-3234c3ab0ddf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744731798 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 44.rom_ctrl_stress_all.1744731798 |
| Directory | /workspace/44.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3717989831 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 76465909496 ps |
| CPU time | 1518.6 seconds |
| Started | Jan 21 09:10:02 PM PST 24 |
| Finished | Jan 21 09:35:41 PM PST 24 |
| Peak memory | 234184 kb |
| Host | smart-bd31a232-2061-405c-a4d5-c6777a25d2a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717989831 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3717989831 |
| Directory | /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_alert_test.2639881779 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 856962555 ps |
| CPU time | 5.71 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:10:40 PM PST 24 |
| Peak memory | 211240 kb |
| Host | smart-dd841bbe-db03-46a1-ac25-4508ad0cf72f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639881779 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2639881779 |
| Directory | /workspace/45.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.1078471472 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 31038336507 ps |
| CPU time | 280.53 seconds |
| Started | Jan 21 09:32:20 PM PST 24 |
| Finished | Jan 21 09:37:22 PM PST 24 |
| Peak memory | 212500 kb |
| Host | smart-4c30ab60-3f29-4e34-8ae5-4ff525b5c97e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078471472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_ corrupt_sig_fatal_chk.1078471472 |
| Directory | /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3831188286 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 615625475 ps |
| CPU time | 9.47 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:10:52 PM PST 24 |
| Peak memory | 211412 kb |
| Host | smart-2cfc8070-0183-4bae-8ea4-2ce7c90a4bb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831188286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3831188286 |
| Directory | /workspace/45.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.639032216 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 1520650487 ps |
| CPU time | 13.76 seconds |
| Started | Jan 21 09:10:16 PM PST 24 |
| Finished | Jan 21 09:10:50 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-749deeca-7ed1-4e22-8f35-1ad967dc0bf0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=639032216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.639032216 |
| Directory | /workspace/45.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_smoke.4074360763 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3389539865 ps |
| CPU time | 33.68 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:11:16 PM PST 24 |
| Peak memory | 213300 kb |
| Host | smart-d53c5821-d61c-4a09-a639-6bce53092d5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074360763 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.4074360763 |
| Directory | /workspace/45.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.rom_ctrl_stress_all.2238257403 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 5916817576 ps |
| CPU time | 16.26 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:10:59 PM PST 24 |
| Peak memory | 211380 kb |
| Host | smart-228f666b-0068-4185-a53d-ff6a344bad18 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238257403 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.rom_ctrl_stress_all.2238257403 |
| Directory | /workspace/45.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_alert_test.273355587 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2034887660 ps |
| CPU time | 16.67 seconds |
| Started | Jan 21 09:10:19 PM PST 24 |
| Finished | Jan 21 09:10:59 PM PST 24 |
| Peak memory | 211276 kb |
| Host | smart-0935faf2-eeb9-4be7-a0ac-163c2d81a372 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273355587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.273355587 |
| Directory | /workspace/46.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.1569264557 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 13423854402 ps |
| CPU time | 184.3 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:13:38 PM PST 24 |
| Peak memory | 212520 kb |
| Host | smart-05f5864e-7a13-4120-b5d9-8bf51f4bdaf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569264557 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_ corrupt_sig_fatal_chk.1569264557 |
| Directory | /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.3016663811 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 12333411436 ps |
| CPU time | 27.09 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:11:10 PM PST 24 |
| Peak memory | 211796 kb |
| Host | smart-64576c42-c501-4dfb-a8fb-02ccc4a177a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016663811 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.3016663811 |
| Directory | /workspace/46.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.3630412167 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 435632933 ps |
| CPU time | 7.07 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:10:40 PM PST 24 |
| Peak memory | 211272 kb |
| Host | smart-7c577627-9bcb-4185-8cb5-8f6d73805eca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3630412167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.3630412167 |
| Directory | /workspace/46.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_smoke.2391366604 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5310741365 ps |
| CPU time | 20.18 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:11:03 PM PST 24 |
| Peak memory | 213028 kb |
| Host | smart-9967b8f7-a72c-44c4-a4db-abb615986fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391366604 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.2391366604 |
| Directory | /workspace/46.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.3629579795 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 202403236199 ps |
| CPU time | 1778.35 seconds |
| Started | Jan 21 10:27:24 PM PST 24 |
| Finished | Jan 21 10:57:22 PM PST 24 |
| Peak memory | 252424 kb |
| Host | smart-82ae267b-450d-4474-a3ab-f4db9da50656 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629579795 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.3629579795 |
| Directory | /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_alert_test.1030275247 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5119569273 ps |
| CPU time | 11.73 seconds |
| Started | Jan 21 09:46:05 PM PST 24 |
| Finished | Jan 21 09:46:31 PM PST 24 |
| Peak memory | 211280 kb |
| Host | smart-5306969b-afde-44c1-a349-649f387da770 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030275247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.1030275247 |
| Directory | /workspace/47.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.229606119 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3149160088 ps |
| CPU time | 144.78 seconds |
| Started | Jan 21 09:10:17 PM PST 24 |
| Finished | Jan 21 09:13:04 PM PST 24 |
| Peak memory | 237884 kb |
| Host | smart-210d5b7b-aa22-439b-ab94-d8e624728390 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229606119 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c orrupt_sig_fatal_chk.229606119 |
| Directory | /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.2068648717 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2372396094 ps |
| CPU time | 9.48 seconds |
| Started | Jan 21 09:10:15 PM PST 24 |
| Finished | Jan 21 09:10:44 PM PST 24 |
| Peak memory | 211564 kb |
| Host | smart-85902d7b-a890-44a3-bfff-dcb04e0fa3bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068648717 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.2068648717 |
| Directory | /workspace/47.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.1827847366 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 186930263 ps |
| CPU time | 5.38 seconds |
| Started | Jan 21 09:10:17 PM PST 24 |
| Finished | Jan 21 09:10:44 PM PST 24 |
| Peak memory | 211284 kb |
| Host | smart-ca153af9-912f-4df2-a866-6d3d9d277af7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1827847366 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.1827847366 |
| Directory | /workspace/47.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_smoke.370779450 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 190985605 ps |
| CPU time | 10.07 seconds |
| Started | Jan 21 09:10:13 PM PST 24 |
| Finished | Jan 21 09:10:41 PM PST 24 |
| Peak memory | 212728 kb |
| Host | smart-abfdca44-d500-46d2-87c3-c0cd8fcc3f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=370779450 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.370779450 |
| Directory | /workspace/47.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all.3303205676 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 9305418244 ps |
| CPU time | 42.6 seconds |
| Started | Jan 21 09:10:20 PM PST 24 |
| Finished | Jan 21 09:11:25 PM PST 24 |
| Peak memory | 214412 kb |
| Host | smart-d9c1c4a2-2c69-4275-a0bb-dbffaf577968 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303205676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.rom_ctrl_stress_all.3303205676 |
| Directory | /workspace/47.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/47.rom_ctrl_stress_all_with_rand_reset.3759135226 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 95297214336 ps |
| CPU time | 2793.1 seconds |
| Started | Jan 21 09:10:16 PM PST 24 |
| Finished | Jan 21 09:57:09 PM PST 24 |
| Peak memory | 236036 kb |
| Host | smart-7813a791-cab7-4d33-8440-245f5fe28ad4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759135226 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_stress_all_with_rand_reset.3759135226 |
| Directory | /workspace/47.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_alert_test.2372650700 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 90119642 ps |
| CPU time | 4.27 seconds |
| Started | Jan 21 09:10:24 PM PST 24 |
| Finished | Jan 21 09:10:50 PM PST 24 |
| Peak memory | 211264 kb |
| Host | smart-74dd1f32-09f9-4a98-9188-981da900e797 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372650700 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.2372650700 |
| Directory | /workspace/48.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.4013466940 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 35992253476 ps |
| CPU time | 252.81 seconds |
| Started | Jan 21 09:10:19 PM PST 24 |
| Finished | Jan 21 09:14:53 PM PST 24 |
| Peak memory | 228444 kb |
| Host | smart-bf5b63c2-91f1-4353-af15-e3f383d8c5dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013466940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_ corrupt_sig_fatal_chk.4013466940 |
| Directory | /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.1311586303 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4629280637 ps |
| CPU time | 17.17 seconds |
| Started | Jan 21 11:18:53 PM PST 24 |
| Finished | Jan 21 11:19:17 PM PST 24 |
| Peak memory | 211880 kb |
| Host | smart-484f8cd3-4908-4f25-856c-faf393d400fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311586303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.1311586303 |
| Directory | /workspace/48.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.1980468063 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4492358522 ps |
| CPU time | 11.52 seconds |
| Started | Jan 21 09:10:14 PM PST 24 |
| Finished | Jan 21 09:10:45 PM PST 24 |
| Peak memory | 211320 kb |
| Host | smart-bc01a354-4e66-4378-b7a7-54ab2c6bd401 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1980468063 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.1980468063 |
| Directory | /workspace/48.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_smoke.594047056 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 181180641 ps |
| CPU time | 9.86 seconds |
| Started | Jan 21 09:10:16 PM PST 24 |
| Finished | Jan 21 09:10:46 PM PST 24 |
| Peak memory | 212524 kb |
| Host | smart-eccec5f0-9d8c-47bf-b850-fb1606c05aba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594047056 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.594047056 |
| Directory | /workspace/48.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all.4119334301 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 19797978074 ps |
| CPU time | 32.07 seconds |
| Started | Jan 21 09:10:18 PM PST 24 |
| Finished | Jan 21 09:11:11 PM PST 24 |
| Peak memory | 215364 kb |
| Host | smart-67dfd2b8-7494-4983-9e90-68f6343f012b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119334301 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.rom_ctrl_stress_all.4119334301 |
| Directory | /workspace/48.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.2068533607 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 147181951308 ps |
| CPU time | 5176.66 seconds |
| Started | Jan 21 09:10:17 PM PST 24 |
| Finished | Jan 21 10:36:56 PM PST 24 |
| Peak memory | 244212 kb |
| Host | smart-c182de3c-df31-47f0-8fc2-0e47f4a74fc1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068533607 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.2068533607 |
| Directory | /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_alert_test.1173050578 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 1458054764 ps |
| CPU time | 12.53 seconds |
| Started | Jan 21 09:10:25 PM PST 24 |
| Finished | Jan 21 09:11:00 PM PST 24 |
| Peak memory | 211220 kb |
| Host | smart-4fbdadc0-7a22-4c56-a66c-0b18046b0b01 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173050578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.1173050578 |
| Directory | /workspace/49.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.4196325271 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 14177300026 ps |
| CPU time | 147.81 seconds |
| Started | Jan 21 09:10:26 PM PST 24 |
| Finished | Jan 21 09:13:16 PM PST 24 |
| Peak memory | 236748 kb |
| Host | smart-95d576c0-ba76-4de4-9c62-d47d28ed7f17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196325271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_ corrupt_sig_fatal_chk.4196325271 |
| Directory | /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.3769070964 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1372509062 ps |
| CPU time | 12.05 seconds |
| Started | Jan 21 09:10:28 PM PST 24 |
| Finished | Jan 21 09:11:01 PM PST 24 |
| Peak memory | 211444 kb |
| Host | smart-07e6b0d8-3d30-4f7a-8090-3ba75c837b04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769070964 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.3769070964 |
| Directory | /workspace/49.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_smoke.2830522882 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9947629218 ps |
| CPU time | 24.69 seconds |
| Started | Jan 21 09:10:25 PM PST 24 |
| Finished | Jan 21 09:11:12 PM PST 24 |
| Peak memory | 213732 kb |
| Host | smart-67417ca7-9316-4a61-a644-99321ae017b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2830522882 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.2830522882 |
| Directory | /workspace/49.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.rom_ctrl_stress_all.2124965253 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 24774413257 ps |
| CPU time | 62.19 seconds |
| Started | Jan 21 09:10:24 PM PST 24 |
| Finished | Jan 21 09:11:49 PM PST 24 |
| Peak memory | 219540 kb |
| Host | smart-a02d2792-9043-4905-82f8-4f5a6e24b99f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124965253 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 49.rom_ctrl_stress_all.2124965253 |
| Directory | /workspace/49.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_alert_test.3002013617 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 378393191 ps |
| CPU time | 4.28 seconds |
| Started | Jan 21 09:06:46 PM PST 24 |
| Finished | Jan 21 09:07:09 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-d875ec54-559c-4e49-a48a-ee62093ed4fc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002013617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3002013617 |
| Directory | /workspace/5.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.3144192810 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2147927119 ps |
| CPU time | 70.24 seconds |
| Started | Jan 21 09:06:47 PM PST 24 |
| Finished | Jan 21 09:08:17 PM PST 24 |
| Peak memory | 236588 kb |
| Host | smart-2e62f54c-35fb-46d4-bd10-958d10a39ca3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144192810 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_c orrupt_sig_fatal_chk.3144192810 |
| Directory | /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.3501419806 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 5806977704 ps |
| CPU time | 18.79 seconds |
| Started | Jan 21 09:06:53 PM PST 24 |
| Finished | Jan 21 09:07:29 PM PST 24 |
| Peak memory | 212064 kb |
| Host | smart-c199ff34-2aef-4c88-b53d-b59e5608c24b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501419806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.3501419806 |
| Directory | /workspace/5.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1894019487 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 1816472248 ps |
| CPU time | 15.26 seconds |
| Started | Jan 21 09:06:41 PM PST 24 |
| Finished | Jan 21 09:07:17 PM PST 24 |
| Peak memory | 211352 kb |
| Host | smart-cc044c70-d529-4b7f-9cb9-964f7e37584c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1894019487 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1894019487 |
| Directory | /workspace/5.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_smoke.2029169582 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4080284675 ps |
| CPU time | 33.51 seconds |
| Started | Jan 21 09:06:43 PM PST 24 |
| Finished | Jan 21 09:07:36 PM PST 24 |
| Peak memory | 213040 kb |
| Host | smart-9f389f5a-7fa7-41c9-84dd-2beb322fe5ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029169582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.2029169582 |
| Directory | /workspace/5.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_stress_all.3986309329 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 6289770564 ps |
| CPU time | 26.76 seconds |
| Started | Jan 21 09:06:41 PM PST 24 |
| Finished | Jan 21 09:07:29 PM PST 24 |
| Peak memory | 213896 kb |
| Host | smart-65d25b5d-ddcc-4c96-ab59-090bf0eaaf29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986309329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 5.rom_ctrl_stress_all.3986309329 |
| Directory | /workspace/5.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1752719580 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 74128640162 ps |
| CPU time | 1339.59 seconds |
| Started | Jan 21 09:06:46 PM PST 24 |
| Finished | Jan 21 09:29:25 PM PST 24 |
| Peak memory | 235956 kb |
| Host | smart-056cbc85-e2fb-433a-9858-45ae24b73b58 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752719580 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1752719580 |
| Directory | /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_alert_test.2459792384 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4938685636 ps |
| CPU time | 9.07 seconds |
| Started | Jan 21 09:06:50 PM PST 24 |
| Finished | Jan 21 09:07:17 PM PST 24 |
| Peak memory | 211316 kb |
| Host | smart-6b035702-598d-425b-967d-e52b5534a6a0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459792384 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2459792384 |
| Directory | /workspace/6.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2039638256 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 14335592221 ps |
| CPU time | 136.94 seconds |
| Started | Jan 21 09:06:48 PM PST 24 |
| Finished | Jan 21 09:09:24 PM PST 24 |
| Peak memory | 228296 kb |
| Host | smart-14d1509d-7740-4987-aaca-7ea8a969f7c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039638256 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c orrupt_sig_fatal_chk.2039638256 |
| Directory | /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.1545266425 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 2411711687 ps |
| CPU time | 23.41 seconds |
| Started | Jan 21 09:06:50 PM PST 24 |
| Finished | Jan 21 09:07:32 PM PST 24 |
| Peak memory | 211424 kb |
| Host | smart-669b1465-597b-4f19-84f2-8903e6948f17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545266425 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.1545266425 |
| Directory | /workspace/6.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.293695938 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2035922346 ps |
| CPU time | 17.04 seconds |
| Started | Jan 21 09:06:47 PM PST 24 |
| Finished | Jan 21 09:07:24 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-c37b90e4-02fc-4682-bb03-2b960e33b317 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=293695938 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.293695938 |
| Directory | /workspace/6.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_smoke.2374019729 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3338598223 ps |
| CPU time | 33.67 seconds |
| Started | Jan 21 09:06:47 PM PST 24 |
| Finished | Jan 21 09:07:40 PM PST 24 |
| Peak memory | 212644 kb |
| Host | smart-d7b61039-233e-4bd2-931f-1d1a7faa792a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2374019729 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.2374019729 |
| Directory | /workspace/6.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.rom_ctrl_stress_all.3476688503 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 56149264752 ps |
| CPU time | 116.23 seconds |
| Started | Jan 21 09:06:50 PM PST 24 |
| Finished | Jan 21 09:09:05 PM PST 24 |
| Peak memory | 219048 kb |
| Host | smart-786c1391-7d52-4dc9-b88a-ba920ee6a2f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476688503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.rom_ctrl_stress_all.3476688503 |
| Directory | /workspace/6.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_alert_test.1802080744 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4823112631 ps |
| CPU time | 7.95 seconds |
| Started | Jan 21 09:07:01 PM PST 24 |
| Finished | Jan 21 09:07:24 PM PST 24 |
| Peak memory | 211268 kb |
| Host | smart-32ab894a-4304-4044-85e1-8ed9c4719c3b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802080744 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.1802080744 |
| Directory | /workspace/7.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1482305856 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 85965732995 ps |
| CPU time | 426.92 seconds |
| Started | Jan 21 09:06:50 PM PST 24 |
| Finished | Jan 21 09:14:15 PM PST 24 |
| Peak memory | 233860 kb |
| Host | smart-b0b7c491-2ed6-445f-9a00-eaf53260924a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482305856 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c orrupt_sig_fatal_chk.1482305856 |
| Directory | /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.2599567877 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 11001159326 ps |
| CPU time | 26.4 seconds |
| Started | Jan 21 09:06:53 PM PST 24 |
| Finished | Jan 21 09:07:36 PM PST 24 |
| Peak memory | 211768 kb |
| Host | smart-76cd5bcc-c47f-4f0a-930e-6be372b9622a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599567877 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.2599567877 |
| Directory | /workspace/7.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.629701493 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 97579398 ps |
| CPU time | 5.55 seconds |
| Started | Jan 21 09:06:47 PM PST 24 |
| Finished | Jan 21 09:07:12 PM PST 24 |
| Peak memory | 211332 kb |
| Host | smart-a18a3100-1233-47bc-b476-3e3590adaf6c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=629701493 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.629701493 |
| Directory | /workspace/7.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_smoke.1136859875 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1395937203 ps |
| CPU time | 18.17 seconds |
| Started | Jan 21 09:06:47 PM PST 24 |
| Finished | Jan 21 09:07:25 PM PST 24 |
| Peak memory | 212760 kb |
| Host | smart-22bfb450-a3a2-4241-9813-1618ecb8dad9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136859875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1136859875 |
| Directory | /workspace/7.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all.423911434 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 6461225851 ps |
| CPU time | 38.71 seconds |
| Started | Jan 21 09:06:48 PM PST 24 |
| Finished | Jan 21 09:07:46 PM PST 24 |
| Peak memory | 216024 kb |
| Host | smart-7256163a-85e1-44e1-951f-52bc305e2976 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423911434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.rom_ctrl_stress_all.423911434 |
| Directory | /workspace/7.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.1496707894 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 44234695870 ps |
| CPU time | 2267.27 seconds |
| Started | Jan 21 09:06:57 PM PST 24 |
| Finished | Jan 21 09:45:00 PM PST 24 |
| Peak memory | 236020 kb |
| Host | smart-85a21524-2772-4b2b-beee-3f481fed23f4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496707894 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.1496707894 |
| Directory | /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_alert_test.72229417 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4529658598 ps |
| CPU time | 12.63 seconds |
| Started | Jan 21 09:07:00 PM PST 24 |
| Finished | Jan 21 09:07:28 PM PST 24 |
| Peak memory | 211328 kb |
| Host | smart-413950a9-1a38-4c1d-9e6b-da502caa1d3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72229417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.72229417 |
| Directory | /workspace/8.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3052735078 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 76899795490 ps |
| CPU time | 337.32 seconds |
| Started | Jan 21 10:22:27 PM PST 24 |
| Finished | Jan 21 10:28:14 PM PST 24 |
| Peak memory | 228552 kb |
| Host | smart-506bbecd-e884-4bb6-8882-aae68645b5b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052735078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c orrupt_sig_fatal_chk.3052735078 |
| Directory | /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2516144309 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 6024380653 ps |
| CPU time | 29.16 seconds |
| Started | Jan 21 09:06:58 PM PST 24 |
| Finished | Jan 21 09:07:43 PM PST 24 |
| Peak memory | 211820 kb |
| Host | smart-ea2968c1-fd7e-4688-bde6-bcf67dc3c9b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516144309 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2516144309 |
| Directory | /workspace/8.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.2676385348 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 611541456 ps |
| CPU time | 5.51 seconds |
| Started | Jan 21 09:07:01 PM PST 24 |
| Finished | Jan 21 09:07:22 PM PST 24 |
| Peak memory | 211324 kb |
| Host | smart-29c1d6a8-2dda-4003-a88a-1ffc414ebbd5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2676385348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.2676385348 |
| Directory | /workspace/8.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_smoke.3266978792 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 6092328272 ps |
| CPU time | 32.07 seconds |
| Started | Jan 21 09:06:57 PM PST 24 |
| Finished | Jan 21 09:07:45 PM PST 24 |
| Peak memory | 213892 kb |
| Host | smart-f03e2e78-42e6-4cc4-9a53-5720b0a2d600 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266978792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.3266978792 |
| Directory | /workspace/8.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all.2432748961 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 15213372546 ps |
| CPU time | 20.6 seconds |
| Started | Jan 21 09:07:01 PM PST 24 |
| Finished | Jan 21 09:07:37 PM PST 24 |
| Peak memory | 214884 kb |
| Host | smart-62c9b5b2-1381-4cbb-ab94-e69598c028ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432748961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.rom_ctrl_stress_all.2432748961 |
| Directory | /workspace/8.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.1790699144 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 155995191956 ps |
| CPU time | 1319.21 seconds |
| Started | Jan 21 09:22:59 PM PST 24 |
| Finished | Jan 21 09:44:59 PM PST 24 |
| Peak memory | 236008 kb |
| Host | smart-3b5de50d-fc82-485d-923a-9f806d2b4c11 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790699144 -assert nop ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.1790699144 |
| Directory | /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_alert_test.3552363355 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 501430172 ps |
| CPU time | 5.03 seconds |
| Started | Jan 21 09:07:15 PM PST 24 |
| Finished | Jan 21 09:07:33 PM PST 24 |
| Peak memory | 211244 kb |
| Host | smart-862bacf5-4e26-4021-b0db-07719b4ec121 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552363355 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.3552363355 |
| Directory | /workspace/9.rom_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.742373394 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 31731801653 ps |
| CPU time | 178.24 seconds |
| Started | Jan 21 09:07:08 PM PST 24 |
| Finished | Jan 21 09:10:21 PM PST 24 |
| Peak memory | 228648 kb |
| Host | smart-7577dfe3-4af4-4c4f-8d94-bddc94971618 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742373394 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt _sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_co rrupt_sig_fatal_chk.742373394 |
| Directory | /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.4180815834 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 3635190341 ps |
| CPU time | 29.77 seconds |
| Started | Jan 21 09:07:12 PM PST 24 |
| Finished | Jan 21 09:07:55 PM PST 24 |
| Peak memory | 211508 kb |
| Host | smart-cfb8794e-6064-4a37-a4ba-c04a822a161f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180815834 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.4180815834 |
| Directory | /workspace/9.rom_ctrl_kmac_err_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.3696354531 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3665910546 ps |
| CPU time | 16.98 seconds |
| Started | Jan 21 09:07:14 PM PST 24 |
| Finished | Jan 21 09:07:44 PM PST 24 |
| Peak memory | 211368 kb |
| Host | smart-11b86ac2-d55a-4e24-9628-8164278fe935 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3696354531 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.3696354531 |
| Directory | /workspace/9.rom_ctrl_max_throughput_chk/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_smoke.152343336 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 183068701 ps |
| CPU time | 10.42 seconds |
| Started | Jan 21 09:06:58 PM PST 24 |
| Finished | Jan 21 09:07:24 PM PST 24 |
| Peak memory | 213192 kb |
| Host | smart-7295c389-228d-447c-b758-fa77450d218a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152343336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.152343336 |
| Directory | /workspace/9.rom_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all.598527989 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2501917760 ps |
| CPU time | 25.65 seconds |
| Started | Jan 21 09:07:09 PM PST 24 |
| Finished | Jan 21 09:07:50 PM PST 24 |
| Peak memory | 213432 kb |
| Host | smart-c088e89e-b993-4641-8b83-f132737888e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598527989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test + UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.rom_ctrl_stress_all.598527989 |
| Directory | /workspace/9.rom_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.774940743 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 335078432916 ps |
| CPU time | 4168.84 seconds |
| Started | Jan 21 09:07:13 PM PST 24 |
| Finished | Jan 21 10:16:55 PM PST 24 |
| Peak memory | 263304 kb |
| Host | smart-4f2f4a19-f56a-4d41-b67a-24a5c8dd5425 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774940743 -assert nopo stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.774940743 |
| Directory | /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest |
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