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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.59 97.04 92.65 97.88 100.00 98.37 97.89 99.30


Total test records in report: 473
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T265 /workspace/coverage/default/29.rom_ctrl_stress_all.1627755611 Jan 24 02:58:10 PM PST 24 Jan 24 02:59:40 PM PST 24 36810899164 ps
T13 /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.164531967 Jan 24 02:55:27 PM PST 24 Jan 24 03:17:23 PM PST 24 33914546118 ps
T266 /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.886582991 Jan 24 02:32:03 PM PST 24 Jan 24 03:16:47 PM PST 24 25378976798 ps
T267 /workspace/coverage/default/32.rom_ctrl_smoke.33806412 Jan 24 02:51:16 PM PST 24 Jan 24 02:52:03 PM PST 24 3871733845 ps
T268 /workspace/coverage/default/13.rom_ctrl_stress_all.2259006561 Jan 24 02:30:54 PM PST 24 Jan 24 02:31:42 PM PST 24 81683703135 ps
T269 /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.797040159 Jan 24 02:31:08 PM PST 24 Jan 24 02:31:35 PM PST 24 7327276113 ps
T270 /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2510016676 Jan 24 02:33:24 PM PST 24 Jan 24 02:35:46 PM PST 24 3846494872 ps
T271 /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2451476617 Jan 24 02:30:50 PM PST 24 Jan 24 02:31:23 PM PST 24 5146182027 ps
T272 /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.626010303 Jan 24 02:46:08 PM PST 24 Jan 24 02:46:32 PM PST 24 4213436213 ps
T273 /workspace/coverage/default/20.rom_ctrl_stress_all.1988750923 Jan 24 02:31:53 PM PST 24 Jan 24 02:32:55 PM PST 24 3857731643 ps
T274 /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.691800142 Jan 24 02:31:38 PM PST 24 Jan 24 02:32:08 PM PST 24 423049361 ps
T275 /workspace/coverage/default/10.rom_ctrl_smoke.2520169694 Jan 24 02:30:48 PM PST 24 Jan 24 02:31:05 PM PST 24 192936700 ps
T276 /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.423340966 Jan 24 02:59:55 PM PST 24 Jan 24 03:00:21 PM PST 24 98114637 ps
T277 /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2758687088 Jan 24 02:31:49 PM PST 24 Jan 24 02:32:33 PM PST 24 1824700667 ps
T278 /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4150170843 Jan 24 02:30:24 PM PST 24 Jan 24 02:30:59 PM PST 24 2251096454 ps
T279 /workspace/coverage/default/46.rom_ctrl_smoke.175595430 Jan 24 02:54:30 PM PST 24 Jan 24 02:55:26 PM PST 24 9826413104 ps
T280 /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2399630869 Jan 24 02:33:21 PM PST 24 Jan 24 02:33:54 PM PST 24 185192797 ps
T281 /workspace/coverage/default/31.rom_ctrl_alert_test.1383653248 Jan 24 03:03:41 PM PST 24 Jan 24 03:04:16 PM PST 24 1384002637 ps
T282 /workspace/coverage/default/6.rom_ctrl_alert_test.2178215310 Jan 24 02:30:36 PM PST 24 Jan 24 02:30:51 PM PST 24 87481717 ps
T283 /workspace/coverage/default/13.rom_ctrl_smoke.2758994065 Jan 24 03:31:18 PM PST 24 Jan 24 03:31:34 PM PST 24 730395328 ps
T284 /workspace/coverage/default/15.rom_ctrl_alert_test.3202243845 Jan 24 02:31:20 PM PST 24 Jan 24 02:31:43 PM PST 24 7794166870 ps
T285 /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3012908516 Jan 24 03:13:36 PM PST 24 Jan 24 03:13:49 PM PST 24 3628414573 ps
T286 /workspace/coverage/default/23.rom_ctrl_alert_test.588110093 Jan 24 02:32:01 PM PST 24 Jan 24 02:32:53 PM PST 24 6389006880 ps
T287 /workspace/coverage/default/16.rom_ctrl_smoke.2677579051 Jan 24 02:31:16 PM PST 24 Jan 24 02:31:41 PM PST 24 18098740021 ps
T288 /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3774420559 Jan 24 02:35:00 PM PST 24 Jan 24 02:35:34 PM PST 24 7042642609 ps
T289 /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2037631113 Jan 24 02:34:26 PM PST 24 Jan 24 02:34:51 PM PST 24 8072738072 ps
T290 /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3415248889 Jan 24 02:31:02 PM PST 24 Jan 24 02:32:42 PM PST 24 3675460795 ps
T14 /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.835901573 Jan 24 02:30:38 PM PST 24 Jan 24 02:47:38 PM PST 24 17057567840 ps
T291 /workspace/coverage/default/43.rom_ctrl_smoke.1396649277 Jan 24 02:34:33 PM PST 24 Jan 24 02:34:49 PM PST 24 378409351 ps
T292 /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.504083444 Jan 24 02:31:52 PM PST 24 Jan 24 02:35:48 PM PST 24 5317912165 ps
T293 /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.784828188 Jan 24 02:32:17 PM PST 24 Jan 24 02:33:03 PM PST 24 2064406488 ps
T294 /workspace/coverage/default/24.rom_ctrl_alert_test.575719578 Jan 24 02:32:11 PM PST 24 Jan 24 02:32:54 PM PST 24 1463805177 ps
T295 /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2979289356 Jan 24 02:29:50 PM PST 24 Jan 24 02:32:23 PM PST 24 2112006466 ps
T296 /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.539093251 Jan 24 02:33:51 PM PST 24 Jan 24 04:48:55 PM PST 24 22933934986 ps
T297 /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1706710458 Jan 24 02:32:42 PM PST 24 Jan 24 03:36:31 PM PST 24 14940768299 ps
T298 /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3489114843 Jan 24 02:34:29 PM PST 24 Jan 24 02:34:48 PM PST 24 8330084168 ps
T299 /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1021151105 Jan 24 02:34:08 PM PST 24 Jan 24 03:15:48 PM PST 24 63749678624 ps
T300 /workspace/coverage/default/23.rom_ctrl_stress_all.2824728967 Jan 24 02:32:05 PM PST 24 Jan 24 02:32:55 PM PST 24 295150391 ps
T301 /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2724955694 Jan 24 02:32:12 PM PST 24 Jan 24 02:32:59 PM PST 24 5517562090 ps
T302 /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2345488244 Jan 24 02:36:40 PM PST 24 Jan 24 02:40:33 PM PST 24 23337288106 ps
T303 /workspace/coverage/default/45.rom_ctrl_stress_all.4096323034 Jan 24 02:35:01 PM PST 24 Jan 24 02:35:42 PM PST 24 3686545219 ps
T304 /workspace/coverage/default/41.rom_ctrl_alert_test.1754149467 Jan 24 02:34:24 PM PST 24 Jan 24 02:34:44 PM PST 24 1350822911 ps
T305 /workspace/coverage/default/27.rom_ctrl_stress_all.1430386857 Jan 24 02:32:22 PM PST 24 Jan 24 02:35:37 PM PST 24 52194029821 ps
T306 /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2367641271 Jan 24 02:31:31 PM PST 24 Jan 24 02:35:03 PM PST 24 235427359552 ps
T307 /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1864174142 Jan 24 02:32:24 PM PST 24 Jan 24 02:37:00 PM PST 24 19853658528 ps
T308 /workspace/coverage/default/14.rom_ctrl_stress_all.3048858828 Jan 24 02:31:05 PM PST 24 Jan 24 02:31:44 PM PST 24 670031394 ps
T309 /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2300431499 Jan 24 02:35:21 PM PST 24 Jan 24 02:42:25 PM PST 24 43634663302 ps
T310 /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.583172657 Jan 24 02:44:18 PM PST 24 Jan 24 02:49:56 PM PST 24 28536376485 ps
T311 /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2007770005 Jan 24 02:30:25 PM PST 24 Jan 24 03:03:55 PM PST 24 139469074335 ps
T312 /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2216467832 Jan 24 02:57:15 PM PST 24 Jan 24 02:57:36 PM PST 24 191814470 ps
T313 /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3038904652 Jan 24 02:35:24 PM PST 24 Jan 24 03:01:58 PM PST 24 132201533559 ps
T314 /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.418175587 Jan 24 02:30:40 PM PST 24 Jan 24 02:31:04 PM PST 24 602554214 ps
T315 /workspace/coverage/default/4.rom_ctrl_stress_all.3386508892 Jan 24 02:30:26 PM PST 24 Jan 24 02:30:54 PM PST 24 2491431619 ps
T316 /workspace/coverage/default/45.rom_ctrl_alert_test.2902353019 Jan 24 02:34:57 PM PST 24 Jan 24 02:35:13 PM PST 24 5585020653 ps
T317 /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2347449943 Jan 24 02:31:49 PM PST 24 Jan 24 02:32:38 PM PST 24 3167283440 ps
T318 /workspace/coverage/default/9.rom_ctrl_alert_test.2277742491 Jan 24 02:30:50 PM PST 24 Jan 24 02:31:14 PM PST 24 8615543898 ps
T319 /workspace/coverage/default/42.rom_ctrl_stress_all.3000698631 Jan 24 02:54:18 PM PST 24 Jan 24 02:55:19 PM PST 24 3717849046 ps
T320 /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4219654204 Jan 24 02:31:40 PM PST 24 Jan 24 02:32:35 PM PST 24 3559122436 ps
T41 /workspace/coverage/default/1.rom_ctrl_sec_cm.2797942415 Jan 24 02:30:05 PM PST 24 Jan 24 02:32:07 PM PST 24 3397498375 ps
T321 /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2651416223 Jan 24 02:30:48 PM PST 24 Jan 24 02:36:30 PM PST 24 84219553734 ps
T322 /workspace/coverage/default/29.rom_ctrl_alert_test.2128864686 Jan 24 02:32:43 PM PST 24 Jan 24 02:33:37 PM PST 24 1547208099 ps
T323 /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2696531004 Jan 24 02:33:47 PM PST 24 Jan 24 02:34:32 PM PST 24 17579476631 ps
T324 /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2335485348 Jan 24 02:29:50 PM PST 24 Jan 24 02:32:21 PM PST 24 2938463674 ps
T325 /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1172046841 Jan 24 02:31:29 PM PST 24 Jan 24 02:31:57 PM PST 24 4392287848 ps
T326 /workspace/coverage/default/48.rom_ctrl_stress_all.1776983890 Jan 24 02:35:17 PM PST 24 Jan 24 02:36:55 PM PST 24 33065717510 ps
T327 /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3825223755 Jan 24 02:34:41 PM PST 24 Jan 24 02:34:52 PM PST 24 95818538 ps
T25 /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.298815009 Jan 24 02:30:40 PM PST 24 Jan 24 02:35:23 PM PST 24 23387923652 ps
T328 /workspace/coverage/default/0.rom_ctrl_smoke.823448041 Jan 24 02:29:51 PM PST 24 Jan 24 02:30:15 PM PST 24 1391930738 ps
T329 /workspace/coverage/default/47.rom_ctrl_alert_test.440458365 Jan 24 02:35:12 PM PST 24 Jan 24 02:35:26 PM PST 24 1018465088 ps
T330 /workspace/coverage/default/33.rom_ctrl_smoke.751021316 Jan 24 02:33:13 PM PST 24 Jan 24 02:34:05 PM PST 24 10089238480 ps
T331 /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3585011293 Jan 24 02:41:44 PM PST 24 Jan 24 03:14:22 PM PST 24 39886508752 ps
T332 /workspace/coverage/default/36.rom_ctrl_alert_test.952294864 Jan 24 02:33:46 PM PST 24 Jan 24 02:34:03 PM PST 24 362335937 ps
T333 /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2773523420 Jan 24 02:34:38 PM PST 24 Jan 24 02:38:37 PM PST 24 55153331743 ps
T334 /workspace/coverage/default/33.rom_ctrl_stress_all.2039059576 Jan 24 02:33:26 PM PST 24 Jan 24 02:35:14 PM PST 24 8787099897 ps
T335 /workspace/coverage/default/7.rom_ctrl_smoke.1779126225 Jan 24 02:30:40 PM PST 24 Jan 24 02:31:15 PM PST 24 9274977308 ps
T336 /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3802279508 Jan 24 02:37:46 PM PST 24 Jan 24 02:38:36 PM PST 24 12646209762 ps
T337 /workspace/coverage/default/5.rom_ctrl_stress_all.3450465057 Jan 24 02:30:40 PM PST 24 Jan 24 02:31:50 PM PST 24 9946547328 ps
T338 /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.461442069 Jan 24 04:34:21 PM PST 24 Jan 24 04:34:43 PM PST 24 2639115653 ps
T339 /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1218246807 Jan 24 02:31:31 PM PST 24 Jan 24 03:15:45 PM PST 24 131387961566 ps
T340 /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1384953187 Jan 24 02:31:51 PM PST 24 Jan 24 02:32:33 PM PST 24 417580323 ps
T341 /workspace/coverage/default/17.rom_ctrl_stress_all.2010590579 Jan 24 02:31:29 PM PST 24 Jan 24 02:32:11 PM PST 24 4542505047 ps
T342 /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2020789297 Jan 24 02:49:34 PM PST 24 Jan 24 02:55:14 PM PST 24 34340781341 ps
T343 /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1901278572 Jan 24 02:34:32 PM PST 24 Jan 24 02:41:01 PM PST 24 88328064176 ps
T344 /workspace/coverage/default/24.rom_ctrl_stress_all.241480808 Jan 24 02:32:17 PM PST 24 Jan 24 02:33:23 PM PST 24 2969209414 ps
T345 /workspace/coverage/default/34.rom_ctrl_alert_test.4251498621 Jan 24 02:33:46 PM PST 24 Jan 24 02:34:06 PM PST 24 385910007 ps
T346 /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1028607857 Jan 24 02:30:50 PM PST 24 Jan 24 02:31:05 PM PST 24 1583357111 ps
T347 /workspace/coverage/default/35.rom_ctrl_alert_test.2599178078 Jan 24 02:33:45 PM PST 24 Jan 24 02:34:10 PM PST 24 1336929111 ps
T348 /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.396196904 Jan 24 02:45:32 PM PST 24 Jan 24 02:46:00 PM PST 24 1706749650 ps
T349 /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4097780742 Jan 24 02:33:47 PM PST 24 Jan 24 03:14:59 PM PST 24 62582267805 ps
T350 /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3616581025 Jan 24 02:30:25 PM PST 24 Jan 24 02:30:42 PM PST 24 198483501 ps
T351 /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4126053484 Jan 24 02:31:08 PM PST 24 Jan 24 02:31:34 PM PST 24 8531860321 ps
T352 /workspace/coverage/default/26.rom_ctrl_smoke.3986574327 Jan 24 02:32:22 PM PST 24 Jan 24 02:33:15 PM PST 24 5831714339 ps
T353 /workspace/coverage/default/40.rom_ctrl_stress_all.1395884922 Jan 24 02:34:11 PM PST 24 Jan 24 02:34:51 PM PST 24 11867109353 ps
T354 /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.799156345 Jan 24 02:34:30 PM PST 24 Jan 24 02:35:08 PM PST 24 15413504591 ps
T355 /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3636229391 Jan 24 02:38:51 PM PST 24 Jan 24 02:39:11 PM PST 24 2656840658 ps
T356 /workspace/coverage/default/23.rom_ctrl_smoke.996279180 Jan 24 02:32:01 PM PST 24 Jan 24 02:33:12 PM PST 24 21912375776 ps
T26 /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1809901948 Jan 24 02:30:50 PM PST 24 Jan 24 02:33:51 PM PST 24 47974588855 ps
T357 /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1281137417 Jan 24 02:32:50 PM PST 24 Jan 24 02:33:50 PM PST 24 2362932721 ps
T358 /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3287794634 Jan 24 02:46:20 PM PST 24 Jan 24 02:46:32 PM PST 24 670947716 ps
T359 /workspace/coverage/default/12.rom_ctrl_smoke.4011292741 Jan 24 02:30:54 PM PST 24 Jan 24 02:31:25 PM PST 24 9291521339 ps
T360 /workspace/coverage/default/38.rom_ctrl_stress_all.105184992 Jan 24 02:34:03 PM PST 24 Jan 24 02:34:53 PM PST 24 8417939245 ps
T361 /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.512309211 Jan 24 02:31:28 PM PST 24 Jan 24 02:32:07 PM PST 24 21562160461 ps
T362 /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3629605076 Jan 24 02:32:41 PM PST 24 Jan 24 02:33:33 PM PST 24 7067768291 ps
T363 /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1290265150 Jan 24 04:00:35 PM PST 24 Jan 24 04:22:51 PM PST 24 17303832768 ps
T364 /workspace/coverage/default/1.rom_ctrl_smoke.3198972597 Jan 24 02:29:53 PM PST 24 Jan 24 02:30:37 PM PST 24 5425091459 ps
T365 /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.660592341 Jan 24 02:48:45 PM PST 24 Jan 24 03:03:16 PM PST 24 42960953026 ps
T366 /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3042136591 Jan 24 02:34:29 PM PST 24 Jan 24 03:48:33 PM PST 24 761369753909 ps
T367 /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1271404486 Jan 24 02:33:26 PM PST 24 Jan 24 02:34:03 PM PST 24 7860360704 ps
T50 /workspace/coverage/default/0.rom_ctrl_sec_cm.860255521 Jan 24 02:29:52 PM PST 24 Jan 24 02:31:56 PM PST 24 1674191470 ps
T368 /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4265928908 Jan 24 02:39:57 PM PST 24 Jan 24 02:40:35 PM PST 24 2716112170 ps
T369 /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3433685066 Jan 24 02:30:38 PM PST 24 Jan 24 02:30:58 PM PST 24 664844816 ps
T370 /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2592179266 Jan 24 02:34:03 PM PST 24 Jan 24 02:40:53 PM PST 24 178113690525 ps
T371 /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.674915869 Jan 24 02:49:27 PM PST 24 Jan 24 02:50:03 PM PST 24 2358226673 ps
T372 /workspace/coverage/default/9.rom_ctrl_stress_all.3066492378 Jan 24 03:54:22 PM PST 24 Jan 24 03:55:01 PM PST 24 2120575524 ps
T373 /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1444951596 Jan 24 03:03:42 PM PST 24 Jan 24 03:09:33 PM PST 24 52993446717 ps
T374 /workspace/coverage/default/13.rom_ctrl_alert_test.601422946 Jan 24 04:02:22 PM PST 24 Jan 24 04:02:36 PM PST 24 5261204730 ps
T375 /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.76030957 Jan 24 02:31:40 PM PST 24 Jan 24 02:46:26 PM PST 24 8361113493 ps
T376 /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.453842203 Jan 24 02:29:50 PM PST 24 Jan 24 02:30:35 PM PST 24 3438726381 ps
T377 /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1533965142 Jan 24 02:30:38 PM PST 24 Jan 24 02:41:07 PM PST 24 68635538296 ps
T378 /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3329756941 Jan 24 02:45:30 PM PST 24 Jan 24 02:49:13 PM PST 24 99087927116 ps
T379 /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.39863844 Jan 24 02:32:14 PM PST 24 Jan 24 02:34:39 PM PST 24 4471017934 ps
T380 /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1999602766 Jan 24 04:17:59 PM PST 24 Jan 24 04:18:15 PM PST 24 1326607134 ps
T381 /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3354612488 Jan 24 02:31:52 PM PST 24 Jan 24 02:35:27 PM PST 24 39670691413 ps
T382 /workspace/coverage/default/26.rom_ctrl_stress_all.2607389432 Jan 24 02:32:24 PM PST 24 Jan 24 02:33:06 PM PST 24 549362580 ps
T383 /workspace/coverage/default/44.rom_ctrl_stress_all.3930520124 Jan 24 02:34:43 PM PST 24 Jan 24 02:35:24 PM PST 24 32730191303 ps
T384 /workspace/coverage/default/5.rom_ctrl_alert_test.3747416521 Jan 24 02:49:52 PM PST 24 Jan 24 02:50:28 PM PST 24 1405867489 ps
T51 /workspace/coverage/default/3.rom_ctrl_sec_cm.2786477740 Jan 24 02:30:24 PM PST 24 Jan 24 02:31:34 PM PST 24 886131540 ps
T385 /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2513535894 Jan 24 04:22:17 PM PST 24 Jan 24 04:25:19 PM PST 24 4862540107 ps
T386 /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3602689418 Jan 24 02:32:37 PM PST 24 Jan 24 02:36:14 PM PST 24 18003449397 ps
T387 /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.901307114 Jan 24 04:26:45 PM PST 24 Jan 24 04:46:59 PM PST 24 24183383300 ps
T388 /workspace/coverage/default/15.rom_ctrl_smoke.1630599367 Jan 24 02:31:07 PM PST 24 Jan 24 02:31:40 PM PST 24 2920952983 ps
T389 /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1002649463 Jan 24 02:32:07 PM PST 24 Jan 24 02:32:44 PM PST 24 94472085 ps
T390 /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4148483794 Jan 24 02:34:30 PM PST 24 Jan 24 02:34:47 PM PST 24 3634621440 ps
T391 /workspace/coverage/default/21.rom_ctrl_smoke.208548642 Jan 24 02:31:51 PM PST 24 Jan 24 02:32:33 PM PST 24 4291300470 ps
T392 /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2199102688 Jan 24 02:33:48 PM PST 24 Jan 24 02:36:20 PM PST 24 9789637166 ps
T106 /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1371246899 Jan 24 02:37:46 PM PST 24 Jan 24 03:59:50 PM PST 24 335852638269 ps
T393 /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2351215648 Jan 24 02:30:22 PM PST 24 Jan 24 02:30:59 PM PST 24 12483329589 ps
T394 /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1609549855 Jan 24 03:39:34 PM PST 24 Jan 24 06:18:47 PM PST 24 200034695480 ps
T395 /workspace/coverage/default/42.rom_ctrl_alert_test.1858876124 Jan 24 02:34:28 PM PST 24 Jan 24 02:34:44 PM PST 24 3573959950 ps
T396 /workspace/coverage/default/28.rom_ctrl_stress_all.3311002699 Jan 24 02:46:49 PM PST 24 Jan 24 02:47:23 PM PST 24 482642735 ps
T397 /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.749465768 Jan 24 02:30:25 PM PST 24 Jan 24 02:31:38 PM PST 24 1860483179 ps
T398 /workspace/coverage/default/19.rom_ctrl_stress_all.2345469986 Jan 24 03:11:01 PM PST 24 Jan 24 03:11:37 PM PST 24 1924383175 ps
T399 /workspace/coverage/default/38.rom_ctrl_smoke.3791950456 Jan 24 02:34:02 PM PST 24 Jan 24 02:34:58 PM PST 24 4129127995 ps
T400 /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1595222007 Jan 24 02:35:10 PM PST 24 Jan 24 02:35:23 PM PST 24 1281551009 ps
T401 /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.53600483 Jan 24 02:30:48 PM PST 24 Jan 24 02:31:10 PM PST 24 20549030193 ps
T402 /workspace/coverage/default/31.rom_ctrl_stress_all.3595369931 Jan 24 02:32:58 PM PST 24 Jan 24 02:34:28 PM PST 24 12899995503 ps
T403 /workspace/coverage/default/21.rom_ctrl_alert_test.1943596639 Jan 24 02:42:37 PM PST 24 Jan 24 02:43:17 PM PST 24 2187549359 ps
T404 /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2480937434 Jan 24 02:33:49 PM PST 24 Jan 24 02:34:14 PM PST 24 793785716 ps
T405 /workspace/coverage/default/22.rom_ctrl_smoke.3146534989 Jan 24 02:32:05 PM PST 24 Jan 24 02:32:58 PM PST 24 5153016213 ps
T406 /workspace/coverage/default/40.rom_ctrl_smoke.2660136930 Jan 24 02:34:06 PM PST 24 Jan 24 02:34:30 PM PST 24 380297581 ps
T407 /workspace/coverage/default/28.rom_ctrl_smoke.1277639903 Jan 24 02:32:37 PM PST 24 Jan 24 02:33:42 PM PST 24 12404009376 ps
T408 /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.58991408 Jan 24 03:25:53 PM PST 24 Jan 24 03:26:24 PM PST 24 1051376725 ps
T409 /workspace/coverage/default/22.rom_ctrl_stress_all.1787941455 Jan 24 02:32:08 PM PST 24 Jan 24 02:33:14 PM PST 24 7028759351 ps
T410 /workspace/coverage/default/3.rom_ctrl_smoke.3473213397 Jan 24 02:30:12 PM PST 24 Jan 24 02:30:38 PM PST 24 193330552 ps
T411 /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3970799933 Jan 24 02:32:45 PM PST 24 Jan 24 02:33:40 PM PST 24 1608674382 ps
T412 /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1908249310 Jan 24 02:04:09 PM PST 24 Jan 24 02:09:35 PM PST 24 122680859795 ps
T413 /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1636362354 Jan 24 02:27:21 PM PST 24 Jan 24 02:28:04 PM PST 24 560745348 ps
T111 /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2907391454 Jan 24 02:10:18 PM PST 24 Jan 24 02:12:26 PM PST 24 1111221689 ps
T414 /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2769484919 Jan 24 02:07:56 PM PST 24 Jan 24 02:08:40 PM PST 24 333695733 ps
T107 /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4152509465 Jan 24 02:05:52 PM PST 24 Jan 24 02:07:19 PM PST 24 371673144 ps
T415 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3399840538 Jan 24 02:05:07 PM PST 24 Jan 24 02:06:12 PM PST 24 1677938575 ps
T416 /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1851956832 Jan 24 02:05:38 PM PST 24 Jan 24 02:06:41 PM PST 24 2267297579 ps
T112 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2755706881 Jan 24 02:05:35 PM PST 24 Jan 24 02:07:40 PM PST 24 718048102 ps
T417 /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.381811092 Jan 24 02:06:25 PM PST 24 Jan 24 02:07:21 PM PST 24 186146519 ps
T418 /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.345236784 Jan 24 02:31:26 PM PST 24 Jan 24 02:31:44 PM PST 24 3595071304 ps
T108 /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2136293520 Jan 24 02:06:40 PM PST 24 Jan 24 02:08:47 PM PST 24 2399965165 ps
T419 /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4032100116 Jan 24 02:20:10 PM PST 24 Jan 24 02:21:43 PM PST 24 5314842259 ps
T420 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3752000190 Jan 24 02:05:53 PM PST 24 Jan 24 02:06:55 PM PST 24 6054901530 ps
T109 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1703673529 Jan 24 02:06:13 PM PST 24 Jan 24 02:08:14 PM PST 24 741323705 ps
T421 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3236034540 Jan 24 02:05:19 PM PST 24 Jan 24 02:06:22 PM PST 24 18707895662 ps
T422 /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2857306474 Jan 24 02:40:02 PM PST 24 Jan 24 02:40:26 PM PST 24 1966474322 ps
T423 /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.401050930 Jan 24 02:48:11 PM PST 24 Jan 24 02:48:51 PM PST 24 2526533722 ps
T424 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.102011319 Jan 24 02:05:54 PM PST 24 Jan 24 02:06:58 PM PST 24 2143680658 ps
T425 /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3888785896 Jan 24 02:14:04 PM PST 24 Jan 24 02:14:34 PM PST 24 15261214729 ps
T426 /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2362614130 Jan 24 02:07:59 PM PST 24 Jan 24 02:08:54 PM PST 24 8943883045 ps
T427 /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1574181283 Jan 24 02:08:00 PM PST 24 Jan 24 02:08:53 PM PST 24 7883556305 ps
T428 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1592950051 Jan 24 02:05:53 PM PST 24 Jan 24 02:07:02 PM PST 24 2908974716 ps
T429 /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1541139920 Jan 24 02:34:53 PM PST 24 Jan 24 02:35:08 PM PST 24 4085781791 ps
T430 /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.389989732 Jan 24 02:36:38 PM PST 24 Jan 24 02:37:24 PM PST 24 1022250196 ps
T431 /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3415808294 Jan 24 02:21:34 PM PST 24 Jan 24 02:22:44 PM PST 24 5772975897 ps
T432 /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.450673382 Jan 24 02:06:23 PM PST 24 Jan 24 02:07:22 PM PST 24 303050342 ps
T433 /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.706768628 Jan 24 02:06:23 PM PST 24 Jan 24 02:07:31 PM PST 24 3655941778 ps
T434 /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2854311484 Jan 24 02:06:16 PM PST 24 Jan 24 02:07:13 PM PST 24 422395355 ps
T435 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1197626268 Jan 24 02:05:37 PM PST 24 Jan 24 02:06:47 PM PST 24 9604769827 ps
T436 /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.726322204 Jan 24 02:41:45 PM PST 24 Jan 24 02:42:08 PM PST 24 1782678333 ps
T437 /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3948077688 Jan 24 02:06:24 PM PST 24 Jan 24 02:07:22 PM PST 24 424526810 ps
T438 /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1890487322 Jan 24 03:12:52 PM PST 24 Jan 24 03:13:15 PM PST 24 8901917355 ps
T439 /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.109887112 Jan 24 02:05:36 PM PST 24 Jan 24 02:06:46 PM PST 24 4443688373 ps
T440 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1864952994 Jan 24 04:34:12 PM PST 24 Jan 24 04:34:29 PM PST 24 4232246051 ps
T441 /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3663716780 Jan 24 02:07:43 PM PST 24 Jan 24 02:08:35 PM PST 24 11775514640 ps
T442 /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3894239918 Jan 24 02:37:40 PM PST 24 Jan 24 02:38:10 PM PST 24 1208133393 ps
T443 /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3804498651 Jan 24 02:09:15 PM PST 24 Jan 24 02:09:31 PM PST 24 1171270749 ps
T444 /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.309271868 Jan 24 02:32:58 PM PST 24 Jan 24 02:33:44 PM PST 24 1510010765 ps
T445 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3664655758 Jan 24 02:06:23 PM PST 24 Jan 24 02:07:25 PM PST 24 232217508 ps
T446 /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1700174492 Jan 24 02:57:13 PM PST 24 Jan 24 02:58:13 PM PST 24 1576132291 ps
T447 /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.452560688 Jan 24 02:06:17 PM PST 24 Jan 24 02:07:21 PM PST 24 546371277 ps
T448 /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4172254972 Jan 24 02:23:41 PM PST 24 Jan 24 02:24:01 PM PST 24 89334961 ps
T449 /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1950715974 Jan 24 02:22:02 PM PST 24 Jan 24 02:23:03 PM PST 24 93242329 ps
T450 /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3130876582 Jan 24 04:42:34 PM PST 24 Jan 24 04:42:46 PM PST 24 88864644 ps
T451 /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1406461690 Jan 24 02:08:00 PM PST 24 Jan 24 02:08:42 PM PST 24 96908843 ps
T452 /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.6061518 Jan 24 02:32:35 PM PST 24 Jan 24 02:33:12 PM PST 24 739511360 ps
T453 /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2359491649 Jan 24 02:22:28 PM PST 24 Jan 24 02:23:14 PM PST 24 2064703722 ps
T454 /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1387250082 Jan 24 02:07:58 PM PST 24 Jan 24 02:08:41 PM PST 24 263197666 ps
T455 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2733995628 Jan 24 02:05:56 PM PST 24 Jan 24 02:07:00 PM PST 24 2083134799 ps
T456 /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2574645401 Jan 24 02:04:32 PM PST 24 Jan 24 02:05:30 PM PST 24 95602318 ps
T457 /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2341980165 Jan 24 02:07:41 PM PST 24 Jan 24 02:08:36 PM PST 24 3620624183 ps
T458 /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2262496152 Jan 24 02:04:27 PM PST 24 Jan 24 02:05:35 PM PST 24 2754050840 ps
T459 /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3169539475 Jan 24 02:07:43 PM PST 24 Jan 24 02:08:34 PM PST 24 3355627123 ps
T460 /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1851418494 Jan 24 02:07:12 PM PST 24 Jan 24 02:08:06 PM PST 24 7713152597 ps
T461 /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3223835914 Jan 24 04:06:50 PM PST 24 Jan 24 04:07:08 PM PST 24 1453832857 ps
T462 /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.286923532 Jan 24 03:15:29 PM PST 24 Jan 24 03:17:07 PM PST 24 9518413496 ps
T463 /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2804884195 Jan 24 02:32:27 PM PST 24 Jan 24 02:33:15 PM PST 24 1931206439 ps
T464 /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2692492787 Jan 24 02:10:08 PM PST 24 Jan 24 02:10:45 PM PST 24 4970971610 ps
T465 /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3976669323 Jan 24 02:05:10 PM PST 24 Jan 24 02:06:06 PM PST 24 162081858 ps
T466 /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.115141080 Jan 24 02:05:37 PM PST 24 Jan 24 02:06:36 PM PST 24 770337412 ps
T467 /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1160227154 Jan 24 02:05:36 PM PST 24 Jan 24 02:06:43 PM PST 24 7265757752 ps
T468 /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4074386305 Jan 24 02:07:41 PM PST 24 Jan 24 02:08:25 PM PST 24 434399573 ps
T469 /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1577457551 Jan 24 04:18:00 PM PST 24 Jan 24 04:18:09 PM PST 24 382063025 ps
T470 /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3728864732 Jan 24 02:05:54 PM PST 24 Jan 24 02:06:53 PM PST 24 4276490385 ps
T471 /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2882883222 Jan 24 02:29:27 PM PST 24 Jan 24 02:30:54 PM PST 24 6602343491 ps
T472 /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2871325965 Jan 24 02:05:53 PM PST 24 Jan 24 02:07:27 PM PST 24 7490285595 ps
T114 /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1279057931 Jan 24 02:06:17 PM PST 24 Jan 24 02:08:29 PM PST 24 15476819357 ps
T473 /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.181271696 Jan 24 02:07:56 PM PST 24 Jan 24 02:08:39 PM PST 24 285721943 ps

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_errors.1409625686
Short name T39
Test name
Test status
Simulation time 396543596 ps
CPU time 6.77 seconds
Started Jan 24 02:06:19 PM PST 24
Finished Jan 24 02:07:18 PM PST 24
Peak memory 219192 kb
Host smart-252c10c0-f2ac-44aa-ba4d-7ae33fcc58f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409625686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_errors.1409625686
Directory /workspace/11.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.21098027
Short name T4
Test name
Test status
Simulation time 71469206928 ps
CPU time 6119.79 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 04:12:03 PM PST 24
Peak memory 227836 kb
Host smart-e1ac802d-3dbf-411e-bdd5-b3b065831942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098027 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_stress_all_with_rand_reset.21098027
Directory /workspace/1.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_walk.1219486815
Short name T30
Test name
Test status
Simulation time 466911925 ps
CPU time 6.73 seconds
Started Jan 24 02:25:08 PM PST 24
Finished Jan 24 02:25:29 PM PST 24
Peak memory 210824 kb
Host smart-5b5997ee-bbd1-4474-a78e-a7f857a337e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219486815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_mem_walk
.1219486815
Directory /workspace/1.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_passthru_mem_tl_intg_err.1369951374
Short name T64
Test name
Test status
Simulation time 30479330892 ps
CPU time 263.14 seconds
Started Jan 24 02:07:10 PM PST 24
Finished Jan 24 02:12:10 PM PST 24
Peak memory 219152 kb
Host smart-f2127ddd-8ee2-4011-8d25-82f39b504109
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369951374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_p
assthru_mem_tl_intg_err.1369951374
Directory /workspace/15.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2246597216
Short name T48
Test name
Test status
Simulation time 1428375673 ps
CPU time 38.89 seconds
Started Jan 24 02:07:12 PM PST 24
Finished Jan 24 02:08:28 PM PST 24
Peak memory 217956 kb
Host smart-b1307462-9e0c-4aeb-bd78-aad45c71228b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246597216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_i
ntg_err.2246597216
Directory /workspace/15.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.rom_ctrl_corrupt_sig_fatal_chk.1396883171
Short name T18
Test name
Test status
Simulation time 170426742295 ps
CPU time 424.39 seconds
Started Jan 24 02:34:25 PM PST 24
Finished Jan 24 02:41:37 PM PST 24
Peak memory 212264 kb
Host smart-be3cd2a3-f852-480d-9b08-00f6236d0ba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396883171 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_
corrupt_sig_fatal_chk.1396883171
Directory /workspace/41.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1316928686
Short name T60
Test name
Test status
Simulation time 130729183 ps
CPU time 8.95 seconds
Started Jan 24 02:07:41 PM PST 24
Finished Jan 24 02:08:29 PM PST 24
Peak memory 219160 kb
Host smart-5c668c04-6ab9-42a1-9dde-b5e09d14f496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316928686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_errors.1316928686
Directory /workspace/16.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2136293520
Short name T108
Test name
Test status
Simulation time 2399965165 ps
CPU time 81.44 seconds
Started Jan 24 02:06:40 PM PST 24
Finished Jan 24 02:08:47 PM PST 24
Peak memory 218468 kb
Host smart-d4e61fc6-406d-447d-a370-7a8494c31fd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136293520 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_tl_i
ntg_err.2136293520
Directory /workspace/12.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_passthru_mem_tl_intg_err.3355840336
Short name T46
Test name
Test status
Simulation time 21749370759 ps
CPU time 168.96 seconds
Started Jan 24 02:05:51 PM PST 24
Finished Jan 24 02:09:30 PM PST 24
Peak memory 211000 kb
Host smart-8ed50392-ae51-44d2-bff6-20a30a1793b2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355840336 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_pa
ssthru_mem_tl_intg_err.3355840336
Directory /workspace/5.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/4.rom_ctrl_sec_cm.281127109
Short name T2
Test name
Test status
Simulation time 23599772636 ps
CPU time 111.76 seconds
Started Jan 24 02:30:36 PM PST 24
Finished Jan 24 02:32:39 PM PST 24
Peak memory 235096 kb
Host smart-57b93467-d9e6-4a90-aa6f-581268c1c1b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281127109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_sec_cm.281127109
Directory /workspace/4.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3276594247
Short name T113
Test name
Test status
Simulation time 2450821225 ps
CPU time 71.47 seconds
Started Jan 24 02:05:57 PM PST 24
Finished Jan 24 02:07:55 PM PST 24
Peak memory 218868 kb
Host smart-a17434bd-8620-480f-aa93-66abc411ee1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276594247 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_in
tg_err.3276594247
Directory /workspace/4.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_same_csr_outstanding.3341149550
Short name T72
Test name
Test status
Simulation time 4124332477 ps
CPU time 9.99 seconds
Started Jan 24 02:05:53 PM PST 24
Finished Jan 24 02:06:51 PM PST 24
Peak memory 210968 kb
Host smart-e296fb95-f37e-43ca-b6b5-04c181598fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341149550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_c
trl_same_csr_outstanding.3341149550
Directory /workspace/6.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1809901948
Short name T26
Test name
Test status
Simulation time 47974588855 ps
CPU time 173.69 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:33:51 PM PST 24
Peak memory 212220 kb
Host smart-3ce98f76-9b5e-4254-a513-f2fb4c357777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809901948 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_
corrupt_sig_fatal_chk.1809901948
Directory /workspace/10.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1951716027
Short name T116
Test name
Test status
Simulation time 74394012369 ps
CPU time 1404.54 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:54:21 PM PST 24
Peak memory 235704 kb
Host smart-285b348f-1e78-44ca-974c-c2e6a5d35afc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951716027 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_stress_all_with_rand_reset.1951716027
Directory /workspace/9.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.1244435167
Short name T55
Test name
Test status
Simulation time 8537525449 ps
CPU time 150.38 seconds
Started Jan 24 02:31:19 PM PST 24
Finished Jan 24 02:33:59 PM PST 24
Peak memory 236468 kb
Host smart-5a063805-7b0b-4526-a8ed-b4472b08e135
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244435167 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_
corrupt_sig_fatal_chk.1244435167
Directory /workspace/15.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_kmac_err_chk.1800325034
Short name T143
Test name
Test status
Simulation time 1850610955 ps
CPU time 18.38 seconds
Started Jan 24 02:30:51 PM PST 24
Finished Jan 24 02:31:16 PM PST 24
Peak memory 211196 kb
Host smart-725e2d9f-e09e-40f5-bb72-05aacc1fdce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800325034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_kmac_err_chk.1800325034
Directory /workspace/10.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_kmac_err_chk.2347054279
Short name T22
Test name
Test status
Simulation time 5561875927 ps
CPU time 18.82 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:15 PM PST 24
Peak memory 211644 kb
Host smart-473be048-8990-4785-8170-d8e85913e081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347054279 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_kmac_err_chk.2347054279
Directory /workspace/11.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_alert_test.2586459688
Short name T137
Test name
Test status
Simulation time 339630862 ps
CPU time 5.62 seconds
Started Jan 24 03:46:51 PM PST 24
Finished Jan 24 03:47:00 PM PST 24
Peak memory 211008 kb
Host smart-f6cce56e-d675-471f-b3bb-2d0c1c86b71e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586459688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_alert_test.2586459688
Directory /workspace/10.rom_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2195065270
Short name T66
Test name
Test status
Simulation time 4261402392 ps
CPU time 39.88 seconds
Started Jan 24 02:08:00 PM PST 24
Finished Jan 24 02:09:17 PM PST 24
Peak memory 219224 kb
Host smart-69b5f03a-f664-47b8-acc9-112b9700d5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195065270 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_i
ntg_err.2195065270
Directory /workspace/18.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all_with_rand_reset.1371246899
Short name T106
Test name
Test status
Simulation time 335852638269 ps
CPU time 4901.58 seconds
Started Jan 24 02:37:46 PM PST 24
Finished Jan 24 03:59:50 PM PST 24
Peak memory 269328 kb
Host smart-04806ccc-8653-4743-9290-146424f291ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371246899 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_stress_all_with_rand_reset.1371246899
Directory /workspace/26.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all_with_rand_reset.3206570311
Short name T104
Test name
Test status
Simulation time 266088814917 ps
CPU time 2574.04 seconds
Started Jan 24 03:09:50 PM PST 24
Finished Jan 24 03:53:07 PM PST 24
Peak memory 250164 kb
Host smart-96b075fe-809b-43f7-b697-01482ee81285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206570311 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_stress_all_with_rand_reset.3206570311
Directory /workspace/38.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3628964229
Short name T34
Test name
Test status
Simulation time 2043900194 ps
CPU time 17.46 seconds
Started Jan 24 02:04:26 PM PST 24
Finished Jan 24 02:05:40 PM PST 24
Peak memory 219168 kb
Host smart-9a1c75e3-8253-4970-9c93-778901e5578d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628964229 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_errors.3628964229
Directory /workspace/0.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.rom_ctrl_max_throughput_chk.2211500432
Short name T16
Test name
Test status
Simulation time 25337919188 ps
CPU time 15.73 seconds
Started Jan 24 02:29:53 PM PST 24
Finished Jan 24 02:30:23 PM PST 24
Peak memory 211072 kb
Host smart-b02475f3-1a7f-4e35-b1d4-f86fdc4e50a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211500432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_max_throughput_chk.2211500432
Directory /workspace/1.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all_with_rand_reset.164531967
Short name T13
Test name
Test status
Simulation time 33914546118 ps
CPU time 1304.12 seconds
Started Jan 24 02:55:27 PM PST 24
Finished Jan 24 03:17:23 PM PST 24
Peak memory 235756 kb
Host smart-9ce83106-f8a1-4b73-a790-8beb4d7d792a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164531967 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_stress_all_with_rand_reset.164531967
Directory /workspace/41.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2246508044
Short name T130
Test name
Test status
Simulation time 346995538 ps
CPU time 4.24 seconds
Started Jan 24 02:04:27 PM PST 24
Finished Jan 24 02:05:28 PM PST 24
Peak memory 216336 kb
Host smart-899c83df-59f5-41d4-9bee-640e2803c073
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246508044 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_alia
sing.2246508044
Directory /workspace/0.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.4061367202
Short name T97
Test name
Test status
Simulation time 1510270619 ps
CPU time 12.97 seconds
Started Jan 24 02:21:53 PM PST 24
Finished Jan 24 02:22:56 PM PST 24
Peak memory 210932 kb
Host smart-ae2987da-63de-49ac-9a96-0381bfe939ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061367202 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_bit_
bash.4061367202
Directory /workspace/0.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.248029220
Short name T79
Test name
Test status
Simulation time 1303907995 ps
CPU time 15.16 seconds
Started Jan 24 02:56:00 PM PST 24
Finished Jan 24 02:56:19 PM PST 24
Peak memory 210988 kb
Host smart-117e3a6d-0cde-4f24-a207-69f1ad56019c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248029220 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_hw_re
set.248029220
Directory /workspace/0.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.1188457349
Short name T70
Test name
Test status
Simulation time 17418317964 ps
CPU time 11.77 seconds
Started Jan 24 02:11:48 PM PST 24
Finished Jan 24 02:12:37 PM PST 24
Peak memory 219284 kb
Host smart-dc930c5a-1d1d-4c8b-ba70-46e389dfb0e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188457349 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rom_ctrl_csr_mem_rw_with_rand_reset.1188457349
Directory /workspace/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_csr_rw.401050930
Short name T423
Test name
Test status
Simulation time 2526533722 ps
CPU time 11.69 seconds
Started Jan 24 02:48:11 PM PST 24
Finished Jan 24 02:48:51 PM PST 24
Peak memory 211008 kb
Host smart-ea5db419-b6a5-4404-bfe1-772cab04796c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401050930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_csr_rw.401050930
Directory /workspace/0.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1577457551
Short name T469
Test name
Test status
Simulation time 382063025 ps
CPU time 6.76 seconds
Started Jan 24 04:18:00 PM PST 24
Finished Jan 24 04:18:09 PM PST 24
Peak memory 210848 kb
Host smart-b9d8f31f-ce1c-4aa5-81d2-0ed7198d9c35
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577457551 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctr
l_mem_partial_access.1577457551
Directory /workspace/0.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_mem_walk.1864952994
Short name T440
Test name
Test status
Simulation time 4232246051 ps
CPU time 10.48 seconds
Started Jan 24 04:34:12 PM PST 24
Finished Jan 24 04:34:29 PM PST 24
Peak memory 210920 kb
Host smart-e8f2cf49-f2b5-4dad-9d40-04794bee9784
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864952994 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_mem_walk
.1864952994
Directory /workspace/0.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1908249310
Short name T412
Test name
Test status
Simulation time 122680859795 ps
CPU time 277.48 seconds
Started Jan 24 02:04:09 PM PST 24
Finished Jan 24 02:09:35 PM PST 24
Peak memory 210996 kb
Host smart-7f7a8f0c-d8ee-491d-a1e9-25bfda5c0f91
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908249310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_pa
ssthru_mem_tl_intg_err.1908249310
Directory /workspace/0.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2574645401
Short name T456
Test name
Test status
Simulation time 95602318 ps
CPU time 4.22 seconds
Started Jan 24 02:04:32 PM PST 24
Finished Jan 24 02:05:30 PM PST 24
Peak memory 210920 kb
Host smart-4c06dbdf-c799-4cab-90ec-6ce6645ac922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574645401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_c
trl_same_csr_outstanding.2574645401
Directory /workspace/0.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.2907391454
Short name T111
Test name
Test status
Simulation time 1111221689 ps
CPU time 75.36 seconds
Started Jan 24 02:10:18 PM PST 24
Finished Jan 24 02:12:26 PM PST 24
Peak memory 219184 kb
Host smart-690bc572-b340-4961-9a7c-8e212c7a923b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907391454 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_tl_in
tg_err.2907391454
Directory /workspace/0.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_aliasing.4229015969
Short name T62
Test name
Test status
Simulation time 1591316881 ps
CPU time 14.09 seconds
Started Jan 24 02:15:08 PM PST 24
Finished Jan 24 02:16:02 PM PST 24
Peak memory 210868 kb
Host smart-253b1947-304c-479e-9a16-4d9a6b08d4c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229015969 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_alia
sing.4229015969
Directory /workspace/1.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_bit_bash.3399840538
Short name T415
Test name
Test status
Simulation time 1677938575 ps
CPU time 14.27 seconds
Started Jan 24 02:05:07 PM PST 24
Finished Jan 24 02:06:12 PM PST 24
Peak memory 210940 kb
Host smart-4161c45a-01fc-4023-861e-62c3adc98fd6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399840538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_bit_
bash.3399840538
Directory /workspace/1.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_hw_reset.612157593
Short name T98
Test name
Test status
Simulation time 4276146002 ps
CPU time 13.88 seconds
Started Jan 24 02:14:04 PM PST 24
Finished Jan 24 02:14:28 PM PST 24
Peak memory 210996 kb
Host smart-44a44869-f4d9-44b0-a37f-c2c22cade8be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612157593 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_hw_re
set.612157593
Directory /workspace/1.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2804884195
Short name T463
Test name
Test status
Simulation time 1931206439 ps
CPU time 16.06 seconds
Started Jan 24 02:32:27 PM PST 24
Finished Jan 24 02:33:15 PM PST 24
Peak memory 219240 kb
Host smart-be3b6728-c883-4fe8-a079-c3d7ec252fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804884195 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rom_ctrl_csr_mem_rw_with_rand_reset.2804884195
Directory /workspace/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3310866491
Short name T71
Test name
Test status
Simulation time 12266791019 ps
CPU time 14.59 seconds
Started Jan 24 02:05:09 PM PST 24
Finished Jan 24 02:06:16 PM PST 24
Peak memory 210896 kb
Host smart-6db81595-9569-4dbc-9de9-26cafe08b069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310866491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_csr_rw.3310866491
Directory /workspace/1.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_mem_partial_access.1154151550
Short name T80
Test name
Test status
Simulation time 7999616334 ps
CPU time 14.23 seconds
Started Jan 24 02:12:48 PM PST 24
Finished Jan 24 02:13:25 PM PST 24
Peak memory 210860 kb
Host smart-0aa8b8f6-4078-4435-98c1-ce9b1089396b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154151550 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctr
l_mem_partial_access.1154151550
Directory /workspace/1.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1621516067
Short name T74
Test name
Test status
Simulation time 73038897314 ps
CPU time 179.26 seconds
Started Jan 24 02:08:53 PM PST 24
Finished Jan 24 02:12:07 PM PST 24
Peak memory 211224 kb
Host smart-a5b25ab4-e478-45c4-8836-69128c6ad44e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621516067 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_pa
ssthru_mem_tl_intg_err.1621516067
Directory /workspace/1.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.699894626
Short name T126
Test name
Test status
Simulation time 3950090081 ps
CPU time 10.75 seconds
Started Jan 24 02:53:33 PM PST 24
Finished Jan 24 02:54:17 PM PST 24
Peak memory 217812 kb
Host smart-1a9af1af-7ee7-4ad1-83a3-a7ccb2af40f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699894626 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ct
rl_same_csr_outstanding.699894626
Directory /workspace/1.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_errors.2262496152
Short name T458
Test name
Test status
Simulation time 2754050840 ps
CPU time 10.7 seconds
Started Jan 24 02:04:27 PM PST 24
Finished Jan 24 02:05:35 PM PST 24
Peak memory 219192 kb
Host smart-02703a2b-8c60-4d9e-a205-3eabb266c10f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262496152 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_errors.2262496152
Directory /workspace/1.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2344514449
Short name T61
Test name
Test status
Simulation time 5576038731 ps
CPU time 72.49 seconds
Started Jan 24 02:04:32 PM PST 24
Finished Jan 24 02:06:39 PM PST 24
Peak memory 211232 kb
Host smart-941bb708-9a53-4fc2-990e-4873ec012910
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344514449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_tl_in
tg_err.2344514449
Directory /workspace/1.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_mem_rw_with_rand_reset.381811092
Short name T417
Test name
Test status
Simulation time 186146519 ps
CPU time 4.55 seconds
Started Jan 24 02:06:25 PM PST 24
Finished Jan 24 02:07:21 PM PST 24
Peak memory 219076 kb
Host smart-8c2f5fa3-3701-444a-8b14-13965a8eade7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381811092 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rom_ctrl_csr_mem_rw_with_rand_reset.381811092
Directory /workspace/10.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_csr_rw.3943153472
Short name T32
Test name
Test status
Simulation time 1919268773 ps
CPU time 14.98 seconds
Started Jan 24 02:06:24 PM PST 24
Finished Jan 24 02:07:30 PM PST 24
Peak memory 217480 kb
Host smart-0f1c0b00-9fd6-44de-939b-1b7858d8c6b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943153472 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_csr_rw.3943153472
Directory /workspace/10.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_passthru_mem_tl_intg_err.3868024325
Short name T89
Test name
Test status
Simulation time 47219777001 ps
CPU time 177.51 seconds
Started Jan 24 02:06:25 PM PST 24
Finished Jan 24 02:10:14 PM PST 24
Peak memory 210944 kb
Host smart-c77cdb9b-4591-45d7-a211-fb50d1c59e43
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868024325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_p
assthru_mem_tl_intg_err.3868024325
Directory /workspace/10.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_same_csr_outstanding.726322204
Short name T436
Test name
Test status
Simulation time 1782678333 ps
CPU time 15.49 seconds
Started Jan 24 02:41:45 PM PST 24
Finished Jan 24 02:42:08 PM PST 24
Peak memory 211040 kb
Host smart-e34997b4-ab19-496c-a2f2-9e27c296ffa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726322204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_c
trl_same_csr_outstanding.726322204
Directory /workspace/10.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_errors.706768628
Short name T433
Test name
Test status
Simulation time 3655941778 ps
CPU time 15.36 seconds
Started Jan 24 02:06:23 PM PST 24
Finished Jan 24 02:07:31 PM PST 24
Peak memory 219220 kb
Host smart-26925a7b-ee64-4d94-93be-53dc2258299a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706768628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_errors.706768628
Directory /workspace/10.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2738578752
Short name T69
Test name
Test status
Simulation time 2580266168 ps
CPU time 39.76 seconds
Started Jan 24 02:06:24 PM PST 24
Finished Jan 24 02:07:55 PM PST 24
Peak memory 219224 kb
Host smart-7726874e-57cc-4ba4-9a1a-7164ef20d598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738578752 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_tl_i
ntg_err.2738578752
Directory /workspace/10.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_mem_rw_with_rand_reset.6061518
Short name T452
Test name
Test status
Simulation time 739511360 ps
CPU time 5.49 seconds
Started Jan 24 02:32:35 PM PST 24
Finished Jan 24 02:33:12 PM PST 24
Peak memory 219172 kb
Host smart-635b50d9-2cbb-4f5d-8122-f733e89e3e06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6061518 -assert nopostproc +UVM_TESTNAME=ro
m_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.rom_ctrl_csr_mem_rw_with_rand_reset.6061518
Directory /workspace/11.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_csr_rw.117677691
Short name T123
Test name
Test status
Simulation time 221044939 ps
CPU time 4.21 seconds
Started Jan 24 02:06:37 PM PST 24
Finished Jan 24 02:07:28 PM PST 24
Peak memory 210876 kb
Host smart-2fcfee10-2d1d-4482-bcb0-d21f0a19b8cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117677691 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_csr_rw.117677691
Directory /workspace/11.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_passthru_mem_tl_intg_err.286923532
Short name T462
Test name
Test status
Simulation time 9518413496 ps
CPU time 93.45 seconds
Started Jan 24 03:15:29 PM PST 24
Finished Jan 24 03:17:07 PM PST 24
Peak memory 211064 kb
Host smart-b8bbcb5d-658b-40c1-b15c-1a6a6cda707f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286923532 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_pa
ssthru_mem_tl_intg_err.286923532
Directory /workspace/11.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_same_csr_outstanding.2692492787
Short name T464
Test name
Test status
Simulation time 4970971610 ps
CPU time 7.64 seconds
Started Jan 24 02:10:08 PM PST 24
Finished Jan 24 02:10:45 PM PST 24
Peak memory 211056 kb
Host smart-df2ebe6f-5c6f-4c4f-b4f6-37055fb3edbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692492787 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_
ctrl_same_csr_outstanding.2692492787
Directory /workspace/11.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.1700174492
Short name T446
Test name
Test status
Simulation time 1576132291 ps
CPU time 44.47 seconds
Started Jan 24 02:57:13 PM PST 24
Finished Jan 24 02:58:13 PM PST 24
Peak memory 211196 kb
Host smart-c28479fb-d789-4e7d-90c3-a5d65e4db085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700174492 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_tl_i
ntg_err.1700174492
Directory /workspace/11.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_mem_rw_with_rand_reset.3415808294
Short name T431
Test name
Test status
Simulation time 5772975897 ps
CPU time 14.51 seconds
Started Jan 24 02:21:34 PM PST 24
Finished Jan 24 02:22:44 PM PST 24
Peak memory 219288 kb
Host smart-209f80d1-a0ab-447f-bdae-b00dd5f0617d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415808294 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rom_ctrl_csr_mem_rw_with_rand_reset.3415808294
Directory /workspace/12.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_csr_rw.2480618011
Short name T122
Test name
Test status
Simulation time 11842424268 ps
CPU time 14.31 seconds
Started Jan 24 02:06:39 PM PST 24
Finished Jan 24 02:07:40 PM PST 24
Peak memory 210900 kb
Host smart-603f5b02-1e31-423d-b4a4-3e8d68b1ef85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480618011 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_csr_rw.2480618011
Directory /workspace/12.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_passthru_mem_tl_intg_err.581359441
Short name T45
Test name
Test status
Simulation time 38142696433 ps
CPU time 290.9 seconds
Started Jan 24 02:06:38 PM PST 24
Finished Jan 24 02:12:15 PM PST 24
Peak memory 219048 kb
Host smart-18d72351-4206-4e04-bcad-3ca3b48eadd4
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581359441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_pa
ssthru_mem_tl_intg_err.581359441
Directory /workspace/12.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rom_ctrl_same_csr_outstanding.3897147169
Short name T37
Test name
Test status
Simulation time 362375641 ps
CPU time 6.14 seconds
Started Jan 24 02:06:57 PM PST 24
Finished Jan 24 02:07:41 PM PST 24
Peak memory 211012 kb
Host smart-10aede66-d23f-495e-b09e-63f57dafb02d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897147169 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rom_
ctrl_same_csr_outstanding.3897147169
Directory /workspace/12.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_mem_rw_with_rand_reset.391332752
Short name T58
Test name
Test status
Simulation time 138967844 ps
CPU time 4.72 seconds
Started Jan 24 02:07:11 PM PST 24
Finished Jan 24 02:07:51 PM PST 24
Peak memory 219168 kb
Host smart-ff9d121e-becf-4d8a-8ecb-6285d3686f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391332752 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rom_ctrl_csr_mem_rw_with_rand_reset.391332752
Directory /workspace/13.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_csr_rw.345236784
Short name T418
Test name
Test status
Simulation time 3595071304 ps
CPU time 9.9 seconds
Started Jan 24 02:31:26 PM PST 24
Finished Jan 24 02:31:44 PM PST 24
Peak memory 211004 kb
Host smart-c6d02607-d8ae-408f-aba1-dbb63e5e8149
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345236784 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_csr_rw.345236784
Directory /workspace/13.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_passthru_mem_tl_intg_err.2882883222
Short name T471
Test name
Test status
Simulation time 6602343491 ps
CPU time 74.16 seconds
Started Jan 24 02:29:27 PM PST 24
Finished Jan 24 02:30:54 PM PST 24
Peak memory 211000 kb
Host smart-a266c1f9-63e8-4136-a1b5-83dc07a3df7a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882883222 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_p
assthru_mem_tl_intg_err.2882883222
Directory /workspace/13.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_same_csr_outstanding.4172254972
Short name T448
Test name
Test status
Simulation time 89334961 ps
CPU time 4.35 seconds
Started Jan 24 02:23:41 PM PST 24
Finished Jan 24 02:24:01 PM PST 24
Peak memory 216952 kb
Host smart-eb378f4f-c2b6-4934-84ce-f84a4e588b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172254972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_
ctrl_same_csr_outstanding.4172254972
Directory /workspace/13.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_errors.3130876582
Short name T450
Test name
Test status
Simulation time 88864644 ps
CPU time 6.64 seconds
Started Jan 24 04:42:34 PM PST 24
Finished Jan 24 04:42:46 PM PST 24
Peak memory 219228 kb
Host smart-47a09d1c-d49a-45a9-8630-1f95e6e3c925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130876582 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_errors.3130876582
Directory /workspace/13.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.3209773806
Short name T57
Test name
Test status
Simulation time 1052262810 ps
CPU time 70.57 seconds
Started Jan 24 02:07:02 PM PST 24
Finished Jan 24 02:08:50 PM PST 24
Peak memory 219172 kb
Host smart-f2e0c9c8-b8a2-4bdc-8b3c-65cc546269ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209773806 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_tl_i
ntg_err.3209773806
Directory /workspace/13.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_mem_rw_with_rand_reset.1851418494
Short name T460
Test name
Test status
Simulation time 7713152597 ps
CPU time 16.55 seconds
Started Jan 24 02:07:12 PM PST 24
Finished Jan 24 02:08:06 PM PST 24
Peak memory 219176 kb
Host smart-73f72fae-1779-4f2f-ad97-5afd460c983c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851418494 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rom_ctrl_csr_mem_rw_with_rand_reset.1851418494
Directory /workspace/14.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_csr_rw.1968852501
Short name T96
Test name
Test status
Simulation time 692018366 ps
CPU time 8.27 seconds
Started Jan 24 02:07:11 PM PST 24
Finished Jan 24 02:07:55 PM PST 24
Peak memory 217296 kb
Host smart-3cc93c0b-4712-42be-b92f-25ecbce9623c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968852501 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_csr_rw.1968852501
Directory /workspace/14.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_passthru_mem_tl_intg_err.3633985178
Short name T76
Test name
Test status
Simulation time 122344241633 ps
CPU time 289.48 seconds
Started Jan 24 02:34:11 PM PST 24
Finished Jan 24 02:39:12 PM PST 24
Peak memory 219020 kb
Host smart-6d993317-f017-47ec-aadb-de7a345e74e6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633985178 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_p
assthru_mem_tl_intg_err.3633985178
Directory /workspace/14.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_same_csr_outstanding.1636362354
Short name T413
Test name
Test status
Simulation time 560745348 ps
CPU time 7.98 seconds
Started Jan 24 02:27:21 PM PST 24
Finished Jan 24 02:28:04 PM PST 24
Peak memory 210988 kb
Host smart-d65836a1-fcb6-4dd9-a015-7763b4e9795a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636362354 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_
ctrl_same_csr_outstanding.1636362354
Directory /workspace/14.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_errors.3888785896
Short name T425
Test name
Test status
Simulation time 15261214729 ps
CPU time 19.09 seconds
Started Jan 24 02:14:04 PM PST 24
Finished Jan 24 02:14:34 PM PST 24
Peak memory 219240 kb
Host smart-5f44a1ad-4294-43c4-b497-64d30edb6044
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888785896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_errors.3888785896
Directory /workspace/14.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3423592884
Short name T110
Test name
Test status
Simulation time 851374489 ps
CPU time 36.42 seconds
Started Jan 24 02:07:10 PM PST 24
Finished Jan 24 02:08:23 PM PST 24
Peak memory 219176 kb
Host smart-afa69600-88e6-430d-a503-6b258e3101c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423592884 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_tl_i
ntg_err.3423592884
Directory /workspace/14.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_mem_rw_with_rand_reset.14795715
Short name T118
Test name
Test status
Simulation time 4278954374 ps
CPU time 17.95 seconds
Started Jan 24 02:07:28 PM PST 24
Finished Jan 24 02:08:27 PM PST 24
Peak memory 219304 kb
Host smart-682ab7a5-102e-46cb-b4ca-f5a286557bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14795715 -assert nopostproc +UVM_TESTNAME=r
om_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.rom_ctrl_csr_mem_rw_with_rand_reset.14795715
Directory /workspace/15.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_csr_rw.4092882975
Short name T119
Test name
Test status
Simulation time 1375893697 ps
CPU time 12.8 seconds
Started Jan 24 02:07:27 PM PST 24
Finished Jan 24 02:08:21 PM PST 24
Peak memory 210932 kb
Host smart-67f1e763-fce7-446c-972d-5f360df1fa5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092882975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_csr_rw.4092882975
Directory /workspace/15.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_same_csr_outstanding.1355932159
Short name T81
Test name
Test status
Simulation time 4970162205 ps
CPU time 11.24 seconds
Started Jan 24 02:07:27 PM PST 24
Finished Jan 24 02:08:19 PM PST 24
Peak memory 218208 kb
Host smart-50348436-f620-474d-9f42-2d788d89a856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355932159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_
ctrl_same_csr_outstanding.1355932159
Directory /workspace/15.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rom_ctrl_tl_errors.2359491649
Short name T453
Test name
Test status
Simulation time 2064703722 ps
CPU time 10.75 seconds
Started Jan 24 02:22:28 PM PST 24
Finished Jan 24 02:23:14 PM PST 24
Peak memory 219172 kb
Host smart-af83c1ec-2f7b-4bbf-8f05-196ae94e0691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359491649 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_tl_errors.2359491649
Directory /workspace/15.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_mem_rw_with_rand_reset.2218304133
Short name T36
Test name
Test status
Simulation time 6896913181 ps
CPU time 14.79 seconds
Started Jan 24 02:07:42 PM PST 24
Finished Jan 24 02:08:35 PM PST 24
Peak memory 219288 kb
Host smart-06e9ceec-ebae-491f-925e-b95c9868c454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218304133 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rom_ctrl_csr_mem_rw_with_rand_reset.2218304133
Directory /workspace/16.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_csr_rw.3169539475
Short name T459
Test name
Test status
Simulation time 3355627123 ps
CPU time 13.95 seconds
Started Jan 24 02:07:43 PM PST 24
Finished Jan 24 02:08:34 PM PST 24
Peak memory 217472 kb
Host smart-1ea20772-6eb4-4d43-9493-69be47995ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169539475 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_csr_rw.3169539475
Directory /workspace/16.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_passthru_mem_tl_intg_err.149748110
Short name T94
Test name
Test status
Simulation time 7208409494 ps
CPU time 93.69 seconds
Started Jan 24 02:07:44 PM PST 24
Finished Jan 24 02:09:55 PM PST 24
Peak memory 210988 kb
Host smart-548dd707-f4a8-4f8b-9d4e-788c204c5bb5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149748110 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_pa
ssthru_mem_tl_intg_err.149748110
Directory /workspace/16.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_same_csr_outstanding.3663716780
Short name T441
Test name
Test status
Simulation time 11775514640 ps
CPU time 14.72 seconds
Started Jan 24 02:07:43 PM PST 24
Finished Jan 24 02:08:35 PM PST 24
Peak memory 211012 kb
Host smart-e6f8ca06-55dd-4bb8-b63a-2fdb61501a9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663716780 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_
ctrl_same_csr_outstanding.3663716780
Directory /workspace/16.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.737972134
Short name T83
Test name
Test status
Simulation time 1244374503 ps
CPU time 72.59 seconds
Started Jan 24 02:07:43 PM PST 24
Finished Jan 24 02:09:33 PM PST 24
Peak memory 219104 kb
Host smart-8a80b322-fd12-472c-a083-62efdac17204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737972134 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_tl_in
tg_err.737972134
Directory /workspace/16.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_mem_rw_with_rand_reset.1133734534
Short name T49
Test name
Test status
Simulation time 3498335477 ps
CPU time 10.57 seconds
Started Jan 24 02:07:57 PM PST 24
Finished Jan 24 02:08:45 PM PST 24
Peak memory 219232 kb
Host smart-751a25c6-d681-4e33-8b10-1fbe3c87c44c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133734534 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rom_ctrl_csr_mem_rw_with_rand_reset.1133734534
Directory /workspace/17.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_csr_rw.4074386305
Short name T468
Test name
Test status
Simulation time 434399573 ps
CPU time 5.72 seconds
Started Jan 24 02:07:41 PM PST 24
Finished Jan 24 02:08:25 PM PST 24
Peak memory 216484 kb
Host smart-812e96cc-adf6-428e-96fb-1f3f21bd7d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074386305 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_csr_rw.4074386305
Directory /workspace/17.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_passthru_mem_tl_intg_err.285014891
Short name T77
Test name
Test status
Simulation time 47185624071 ps
CPU time 130.79 seconds
Started Jan 24 02:07:43 PM PST 24
Finished Jan 24 02:10:32 PM PST 24
Peak memory 211016 kb
Host smart-2c56e86d-3eef-412a-b611-bec6932099cc
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285014891 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_pa
ssthru_mem_tl_intg_err.285014891
Directory /workspace/17.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_same_csr_outstanding.1387250082
Short name T454
Test name
Test status
Simulation time 263197666 ps
CPU time 5.95 seconds
Started Jan 24 02:07:58 PM PST 24
Finished Jan 24 02:08:41 PM PST 24
Peak memory 216788 kb
Host smart-1eba9ecc-dea3-4532-8375-1a97c6ea0602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387250082 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_
ctrl_same_csr_outstanding.1387250082
Directory /workspace/17.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_errors.2341980165
Short name T457
Test name
Test status
Simulation time 3620624183 ps
CPU time 16.49 seconds
Started Jan 24 02:07:41 PM PST 24
Finished Jan 24 02:08:36 PM PST 24
Peak memory 219268 kb
Host smart-44c7acd2-ecab-481a-b61c-996cf9d9861e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341980165 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_errors.2341980165
Directory /workspace/17.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1720523374
Short name T82
Test name
Test status
Simulation time 1717407255 ps
CPU time 45.19 seconds
Started Jan 24 02:07:45 PM PST 24
Finished Jan 24 02:09:07 PM PST 24
Peak memory 219144 kb
Host smart-2d7d9a79-34c4-4718-b817-82bc4fc781ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720523374 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_tl_i
ntg_err.1720523374
Directory /workspace/17.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_mem_rw_with_rand_reset.309271868
Short name T444
Test name
Test status
Simulation time 1510010765 ps
CPU time 9.42 seconds
Started Jan 24 02:32:58 PM PST 24
Finished Jan 24 02:33:44 PM PST 24
Peak memory 219168 kb
Host smart-ec6e96f3-d0e0-4e50-a793-99a693e2260f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309271868 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rom_ctrl_csr_mem_rw_with_rand_reset.309271868
Directory /workspace/18.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_csr_rw.4090073869
Short name T63
Test name
Test status
Simulation time 2232050525 ps
CPU time 5.9 seconds
Started Jan 24 02:07:55 PM PST 24
Finished Jan 24 02:08:38 PM PST 24
Peak memory 211028 kb
Host smart-71595de5-196f-4e0f-84d9-7bea0d108717
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090073869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_csr_rw.4090073869
Directory /workspace/18.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_passthru_mem_tl_intg_err.3393520555
Short name T65
Test name
Test status
Simulation time 15853103258 ps
CPU time 172.73 seconds
Started Jan 24 02:24:34 PM PST 24
Finished Jan 24 02:27:33 PM PST 24
Peak memory 211036 kb
Host smart-19ed812e-11c8-4eb4-9d58-a926026f5c05
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393520555 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_p
assthru_mem_tl_intg_err.3393520555
Directory /workspace/18.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_same_csr_outstanding.2769484919
Short name T414
Test name
Test status
Simulation time 333695733 ps
CPU time 6.73 seconds
Started Jan 24 02:07:56 PM PST 24
Finished Jan 24 02:08:40 PM PST 24
Peak memory 211004 kb
Host smart-afc7fda0-ea49-4a61-8a73-d3a29ea44300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769484919 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_
ctrl_same_csr_outstanding.2769484919
Directory /workspace/18.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rom_ctrl_tl_errors.1574181283
Short name T427
Test name
Test status
Simulation time 7883556305 ps
CPU time 17.19 seconds
Started Jan 24 02:08:00 PM PST 24
Finished Jan 24 02:08:53 PM PST 24
Peak memory 219248 kb
Host smart-d88ee918-370e-46ce-864c-0d1fb5235f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574181283 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_tl_errors.1574181283
Directory /workspace/18.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_mem_rw_with_rand_reset.181271696
Short name T473
Test name
Test status
Simulation time 285721943 ps
CPU time 5.7 seconds
Started Jan 24 02:07:56 PM PST 24
Finished Jan 24 02:08:39 PM PST 24
Peak memory 219252 kb
Host smart-4c144b4b-2b97-4110-95eb-d892d411802f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181271696 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rom_ctrl_csr_mem_rw_with_rand_reset.181271696
Directory /workspace/19.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_csr_rw.1261465037
Short name T124
Test name
Test status
Simulation time 2325098036 ps
CPU time 11.34 seconds
Started Jan 24 02:32:23 PM PST 24
Finished Jan 24 02:33:08 PM PST 24
Peak memory 211024 kb
Host smart-92281bb0-5899-4210-949a-ba3b17694aad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261465037 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_csr_rw.1261465037
Directory /workspace/19.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_passthru_mem_tl_intg_err.1554850734
Short name T73
Test name
Test status
Simulation time 48751779638 ps
CPU time 171.71 seconds
Started Jan 24 02:07:58 PM PST 24
Finished Jan 24 02:11:27 PM PST 24
Peak memory 211160 kb
Host smart-ced10e17-13e8-419e-bd33-1e365344535f
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554850734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_p
assthru_mem_tl_intg_err.1554850734
Directory /workspace/19.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_same_csr_outstanding.1406461690
Short name T451
Test name
Test status
Simulation time 96908843 ps
CPU time 6.24 seconds
Started Jan 24 02:08:00 PM PST 24
Finished Jan 24 02:08:42 PM PST 24
Peak memory 211016 kb
Host smart-f5a335bf-9861-430c-830c-267238b94d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406461690 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_
ctrl_same_csr_outstanding.1406461690
Directory /workspace/19.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_errors.2362614130
Short name T426
Test name
Test status
Simulation time 8943883045 ps
CPU time 18.28 seconds
Started Jan 24 02:07:59 PM PST 24
Finished Jan 24 02:08:54 PM PST 24
Peak memory 219224 kb
Host smart-2932de10-f892-4b25-bc6d-12242c470b16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362614130 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_errors.2362614130
Directory /workspace/19.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.4150412598
Short name T84
Test name
Test status
Simulation time 3486534854 ps
CPU time 43.13 seconds
Started Jan 24 02:07:56 PM PST 24
Finished Jan 24 02:09:16 PM PST 24
Peak memory 219216 kb
Host smart-03d9f1c2-9d3a-45f5-b161-588f3211c595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150412598 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_tl_i
ntg_err.4150412598
Directory /workspace/19.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_aliasing.3236034540
Short name T421
Test name
Test status
Simulation time 18707895662 ps
CPU time 12.69 seconds
Started Jan 24 02:05:19 PM PST 24
Finished Jan 24 02:06:22 PM PST 24
Peak memory 217676 kb
Host smart-beac4573-d501-42f7-a447-0c4e4f035203
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236034540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_alia
sing.3236034540
Directory /workspace/2.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_bit_bash.1110269765
Short name T127
Test name
Test status
Simulation time 2256424618 ps
CPU time 11.63 seconds
Started Jan 24 02:15:48 PM PST 24
Finished Jan 24 02:16:39 PM PST 24
Peak memory 211024 kb
Host smart-dfa20885-1c62-4ea7-9438-d4b17058fbc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110269765 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_bit_
bash.1110269765
Directory /workspace/2.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_hw_reset.1925091832
Short name T87
Test name
Test status
Simulation time 1057926112 ps
CPU time 13.56 seconds
Started Jan 24 02:05:08 PM PST 24
Finished Jan 24 02:06:13 PM PST 24
Peak memory 210940 kb
Host smart-e8091faa-295c-41e7-93f1-d608d0698b0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925091832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_hw_r
eset.1925091832
Directory /workspace/2.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.115141080
Short name T466
Test name
Test status
Simulation time 770337412 ps
CPU time 5.77 seconds
Started Jan 24 02:05:37 PM PST 24
Finished Jan 24 02:06:36 PM PST 24
Peak memory 219156 kb
Host smart-f201b34f-b3a2-4470-b3ae-1d993827a67c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115141080 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rom_ctrl_csr_mem_rw_with_rand_reset.115141080
Directory /workspace/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_csr_rw.146194138
Short name T129
Test name
Test status
Simulation time 89219228 ps
CPU time 4.26 seconds
Started Jan 24 02:05:05 PM PST 24
Finished Jan 24 02:06:00 PM PST 24
Peak memory 216540 kb
Host smart-a9dab939-d6e2-464a-87bd-3b69262cbae2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146194138 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_csr_rw.146194138
Directory /workspace/2.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_partial_access.1899705378
Short name T125
Test name
Test status
Simulation time 10040285756 ps
CPU time 12.37 seconds
Started Jan 24 02:05:04 PM PST 24
Finished Jan 24 02:06:07 PM PST 24
Peak memory 210852 kb
Host smart-6942d4eb-c903-4f74-9a08-7d3719055627
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899705378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctr
l_mem_partial_access.1899705378
Directory /workspace/2.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_mem_walk.3976669323
Short name T465
Test name
Test status
Simulation time 162081858 ps
CPU time 4.21 seconds
Started Jan 24 02:05:10 PM PST 24
Finished Jan 24 02:06:06 PM PST 24
Peak memory 210756 kb
Host smart-43320dbd-9428-484a-9994-c611b41eeb2d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976669323 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_mem_walk
.3976669323
Directory /workspace/2.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.4193062021
Short name T88
Test name
Test status
Simulation time 94227893356 ps
CPU time 252.74 seconds
Started Jan 24 02:14:14 PM PST 24
Finished Jan 24 02:18:42 PM PST 24
Peak memory 211044 kb
Host smart-68223218-d9eb-4ea2-8c88-3cafd71ff548
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193062021 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_pa
ssthru_mem_tl_intg_err.4193062021
Directory /workspace/2.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.1890487322
Short name T438
Test name
Test status
Simulation time 8901917355 ps
CPU time 15.34 seconds
Started Jan 24 03:12:52 PM PST 24
Finished Jan 24 03:13:15 PM PST 24
Peak memory 218344 kb
Host smart-3a61f1c1-f96d-4a68-8fa9-fa19db098f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890487322 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_c
trl_same_csr_outstanding.1890487322
Directory /workspace/2.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_errors.389989732
Short name T430
Test name
Test status
Simulation time 1022250196 ps
CPU time 14.6 seconds
Started Jan 24 02:36:38 PM PST 24
Finished Jan 24 02:37:24 PM PST 24
Peak memory 219196 kb
Host smart-d221d68b-a0c3-4948-80ac-b4127d5379eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389989732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_errors.389989732
Directory /workspace/2.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.1238460036
Short name T115
Test name
Test status
Simulation time 3594252269 ps
CPU time 46.67 seconds
Started Jan 24 02:41:08 PM PST 24
Finished Jan 24 02:42:07 PM PST 24
Peak memory 217396 kb
Host smart-1a7f64fd-292e-4014-8246-a6ba7cde514e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238460036 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_tl_in
tg_err.1238460036
Directory /workspace/2.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_aliasing.1197626268
Short name T435
Test name
Test status
Simulation time 9604769827 ps
CPU time 16.98 seconds
Started Jan 24 02:05:37 PM PST 24
Finished Jan 24 02:06:47 PM PST 24
Peak memory 217680 kb
Host smart-446f3d3a-b0f9-429b-b7a8-33af46acd09a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197626268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_alia
sing.1197626268
Directory /workspace/3.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_bit_bash.882236254
Short name T78
Test name
Test status
Simulation time 2085977736 ps
CPU time 16.88 seconds
Started Jan 24 02:05:38 PM PST 24
Finished Jan 24 02:06:47 PM PST 24
Peak memory 210956 kb
Host smart-5c23d3e4-8021-479d-8a6b-3eef7aca41a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882236254 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_bit_b
ash.882236254
Directory /workspace/3.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_hw_reset.3804498651
Short name T443
Test name
Test status
Simulation time 1171270749 ps
CPU time 9.26 seconds
Started Jan 24 02:09:15 PM PST 24
Finished Jan 24 02:09:31 PM PST 24
Peak memory 210948 kb
Host smart-50597936-223e-48a9-aa6e-c0ea781977ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804498651 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_hw_r
eset.3804498651
Directory /workspace/3.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.102011319
Short name T424
Test name
Test status
Simulation time 2143680658 ps
CPU time 16.39 seconds
Started Jan 24 02:05:54 PM PST 24
Finished Jan 24 02:06:58 PM PST 24
Peak memory 219212 kb
Host smart-5552e556-0bff-480b-9051-846281db560a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102011319 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rom_ctrl_csr_mem_rw_with_rand_reset.102011319
Directory /workspace/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_csr_rw.2921505643
Short name T33
Test name
Test status
Simulation time 8378034261 ps
CPU time 16.22 seconds
Started Jan 24 02:05:35 PM PST 24
Finished Jan 24 02:06:45 PM PST 24
Peak memory 210876 kb
Host smart-e2e0d4ec-08cf-421c-a38b-5089dd09fb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921505643 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_csr_rw.2921505643
Directory /workspace/3.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_partial_access.2855257845
Short name T35
Test name
Test status
Simulation time 8805844751 ps
CPU time 16.31 seconds
Started Jan 24 03:38:39 PM PST 24
Finished Jan 24 03:38:57 PM PST 24
Peak memory 210928 kb
Host smart-af0c650d-f8cc-478d-b36e-7854fb8dca89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855257845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctr
l_mem_partial_access.2855257845
Directory /workspace/3.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_mem_walk.1851956832
Short name T416
Test name
Test status
Simulation time 2267297579 ps
CPU time 10.33 seconds
Started Jan 24 02:05:38 PM PST 24
Finished Jan 24 02:06:41 PM PST 24
Peak memory 210888 kb
Host smart-2147e2af-eeaf-40d5-aeb3-4ffc6c98cc42
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851956832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_mem_walk
.1851956832
Directory /workspace/3.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.1160227154
Short name T467
Test name
Test status
Simulation time 7265757752 ps
CPU time 13.06 seconds
Started Jan 24 02:05:36 PM PST 24
Finished Jan 24 02:06:43 PM PST 24
Peak memory 211044 kb
Host smart-41d6b55b-5c23-4c5f-9b1f-561429dcbae2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160227154 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_c
trl_same_csr_outstanding.1160227154
Directory /workspace/3.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_errors.109887112
Short name T439
Test name
Test status
Simulation time 4443688373 ps
CPU time 15.96 seconds
Started Jan 24 02:05:36 PM PST 24
Finished Jan 24 02:06:46 PM PST 24
Peak memory 219248 kb
Host smart-d68cd56f-b980-475d-80ba-9cd312fbbe9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109887112 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_errors.109887112
Directory /workspace/3.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2755706881
Short name T112
Test name
Test status
Simulation time 718048102 ps
CPU time 71.92 seconds
Started Jan 24 02:05:35 PM PST 24
Finished Jan 24 02:07:40 PM PST 24
Peak memory 219176 kb
Host smart-f3a740be-7aea-4294-a0dd-63b20598c75e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755706881 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_tl_in
tg_err.2755706881
Directory /workspace/3.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_aliasing.3752000190
Short name T420
Test name
Test status
Simulation time 6054901530 ps
CPU time 13.3 seconds
Started Jan 24 02:05:53 PM PST 24
Finished Jan 24 02:06:55 PM PST 24
Peak memory 217652 kb
Host smart-67c57d57-c1e2-4168-812d-889900b3cf9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752000190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_alia
sing.3752000190
Directory /workspace/4.rom_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_bit_bash.1188121400
Short name T86
Test name
Test status
Simulation time 11776167255 ps
CPU time 16.47 seconds
Started Jan 24 02:05:54 PM PST 24
Finished Jan 24 02:06:58 PM PST 24
Peak memory 211000 kb
Host smart-4f83662d-a439-4548-9bb6-27c4b7c5ba47
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188121400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_bit_
bash.1188121400
Directory /workspace/4.rom_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_hw_reset.1950715974
Short name T449
Test name
Test status
Simulation time 93242329 ps
CPU time 5.82 seconds
Started Jan 24 02:22:02 PM PST 24
Finished Jan 24 02:23:03 PM PST 24
Peak memory 217224 kb
Host smart-02af7159-d94e-41f5-9fe0-a764d110d7ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950715974 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_hw_r
eset.1950715974
Directory /workspace/4.rom_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.2873486722
Short name T128
Test name
Test status
Simulation time 3024614927 ps
CPU time 13.27 seconds
Started Jan 24 02:05:57 PM PST 24
Finished Jan 24 02:06:57 PM PST 24
Peak memory 219188 kb
Host smart-a0acb8ee-42d7-4be2-8cfd-1873147119cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873486722 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rom_ctrl_csr_mem_rw_with_rand_reset.2873486722
Directory /workspace/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_csr_rw.292423613
Short name T121
Test name
Test status
Simulation time 1710607567 ps
CPU time 7 seconds
Started Jan 24 02:24:28 PM PST 24
Finished Jan 24 02:24:43 PM PST 24
Peak memory 210872 kb
Host smart-6b1efe4f-3d03-4522-9902-81695aa7c2d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292423613 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_csr_rw.292423613
Directory /workspace/4.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_partial_access.2733995628
Short name T455
Test name
Test status
Simulation time 2083134799 ps
CPU time 16.16 seconds
Started Jan 24 02:05:56 PM PST 24
Finished Jan 24 02:07:00 PM PST 24
Peak memory 210796 kb
Host smart-d3666f6c-0b29-4a68-a86a-8740571a02e8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733995628 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctr
l_mem_partial_access.2733995628
Directory /workspace/4.rom_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_mem_walk.3728864732
Short name T470
Test name
Test status
Simulation time 4276490385 ps
CPU time 10.81 seconds
Started Jan 24 02:05:54 PM PST 24
Finished Jan 24 02:06:53 PM PST 24
Peak memory 210876 kb
Host smart-21825901-6cee-4219-a2cb-0acd02f579c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728864732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_mem_walk
.3728864732
Directory /workspace/4.rom_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.130120815
Short name T31
Test name
Test status
Simulation time 334862718 ps
CPU time 5.38 seconds
Started Jan 24 02:05:55 PM PST 24
Finished Jan 24 02:06:48 PM PST 24
Peak memory 217028 kb
Host smart-18b851e5-c71e-4551-8ff4-dd1a59aae785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130120815 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ct
rl_same_csr_outstanding.130120815
Directory /workspace/4.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2359848128
Short name T85
Test name
Test status
Simulation time 13899025146 ps
CPU time 15.12 seconds
Started Jan 24 02:05:53 PM PST 24
Finished Jan 24 02:06:57 PM PST 24
Peak memory 219260 kb
Host smart-5e9d7343-71c9-47bb-afcf-e77151710d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359848128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_tl_errors.2359848128
Directory /workspace/4.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_mem_rw_with_rand_reset.3223835914
Short name T461
Test name
Test status
Simulation time 1453832857 ps
CPU time 8.49 seconds
Started Jan 24 04:06:50 PM PST 24
Finished Jan 24 04:07:08 PM PST 24
Peak memory 219284 kb
Host smart-20ee44ae-d168-4998-94dd-f316d3553e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223835914 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rom_ctrl_csr_mem_rw_with_rand_reset.3223835914
Directory /workspace/5.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_csr_rw.3101074563
Short name T92
Test name
Test status
Simulation time 89246179 ps
CPU time 4.26 seconds
Started Jan 24 02:33:18 PM PST 24
Finished Jan 24 02:33:49 PM PST 24
Peak memory 217172 kb
Host smart-998de009-cda8-4f9f-a8c5-195e23cbd457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101074563 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_csr_rw.3101074563
Directory /workspace/5.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_same_csr_outstanding.3878437981
Short name T99
Test name
Test status
Simulation time 819032801 ps
CPU time 6.57 seconds
Started Jan 24 02:05:56 PM PST 24
Finished Jan 24 02:06:50 PM PST 24
Peak memory 211016 kb
Host smart-478c1580-af0d-4c5c-8bd3-b2873c86528e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878437981 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_c
trl_same_csr_outstanding.3878437981
Directory /workspace/5.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_errors.929067439
Short name T67
Test name
Test status
Simulation time 275130833 ps
CPU time 10.67 seconds
Started Jan 24 02:05:54 PM PST 24
Finished Jan 24 02:06:53 PM PST 24
Peak memory 219160 kb
Host smart-1429ecaa-4753-4130-8637-1cfd6dbc7e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929067439 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_errors.929067439
Directory /workspace/5.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.4152509465
Short name T107
Test name
Test status
Simulation time 371673144 ps
CPU time 37.74 seconds
Started Jan 24 02:05:52 PM PST 24
Finished Jan 24 02:07:19 PM PST 24
Peak memory 219168 kb
Host smart-e3f94a87-bd25-4417-85df-b96b6603830b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152509465 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_tl_in
tg_err.4152509465
Directory /workspace/5.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_mem_rw_with_rand_reset.1541139920
Short name T429
Test name
Test status
Simulation time 4085781791 ps
CPU time 10.49 seconds
Started Jan 24 02:34:53 PM PST 24
Finished Jan 24 02:35:08 PM PST 24
Peak memory 219224 kb
Host smart-77949c07-934e-47f9-ac93-cc6cd08a6ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541139920 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rom_ctrl_csr_mem_rw_with_rand_reset.1541139920
Directory /workspace/6.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_csr_rw.4224515468
Short name T38
Test name
Test status
Simulation time 297352530 ps
CPU time 4.2 seconds
Started Jan 24 02:05:55 PM PST 24
Finished Jan 24 02:06:47 PM PST 24
Peak memory 216292 kb
Host smart-a9883c15-0204-4450-97e5-eba06b6918b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224515468 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_csr_rw.4224515468
Directory /workspace/6.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_passthru_mem_tl_intg_err.3791804274
Short name T47
Test name
Test status
Simulation time 1953482294 ps
CPU time 51.46 seconds
Started Jan 24 02:05:57 PM PST 24
Finished Jan 24 02:07:35 PM PST 24
Peak memory 210552 kb
Host smart-d4517dbd-a0cb-4944-af7d-028d8569015a
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791804274 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_pa
ssthru_mem_tl_intg_err.3791804274
Directory /workspace/6.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1592950051
Short name T428
Test name
Test status
Simulation time 2908974716 ps
CPU time 20.37 seconds
Started Jan 24 02:05:53 PM PST 24
Finished Jan 24 02:07:02 PM PST 24
Peak memory 219272 kb
Host smart-2399426c-7571-44a3-bfc3-5595f2970f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592950051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_errors.1592950051
Directory /workspace/6.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2871325965
Short name T472
Test name
Test status
Simulation time 7490285595 ps
CPU time 44.95 seconds
Started Jan 24 02:05:53 PM PST 24
Finished Jan 24 02:07:27 PM PST 24
Peak memory 219128 kb
Host smart-bb40ede3-535a-4e1f-ae5d-5dac1ad0e00a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871325965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_tl_in
tg_err.2871325965
Directory /workspace/6.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_mem_rw_with_rand_reset.723961193
Short name T117
Test name
Test status
Simulation time 2646443264 ps
CPU time 11.97 seconds
Started Jan 24 02:06:16 PM PST 24
Finished Jan 24 02:07:20 PM PST 24
Peak memory 219260 kb
Host smart-a8f3808e-9a95-4d7f-8611-21ba31b80b35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723961193 -assert nopostproc +UVM_TESTNAME=
rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rom_ctrl_csr_mem_rw_with_rand_reset.723961193
Directory /workspace/7.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_csr_rw.1308020760
Short name T120
Test name
Test status
Simulation time 6477542458 ps
CPU time 14.06 seconds
Started Jan 24 02:24:24 PM PST 24
Finished Jan 24 02:24:48 PM PST 24
Peak memory 211008 kb
Host smart-c00bf92d-d2e4-42dc-b6c5-42b951e71ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308020760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_csr_rw.1308020760
Directory /workspace/7.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_passthru_mem_tl_intg_err.1542208016
Short name T75
Test name
Test status
Simulation time 1948872018 ps
CPU time 50.37 seconds
Started Jan 24 02:56:40 PM PST 24
Finished Jan 24 02:57:32 PM PST 24
Peak memory 211008 kb
Host smart-fd082446-71bc-46d3-b018-c74001562591
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542208016 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_pa
ssthru_mem_tl_intg_err.1542208016
Directory /workspace/7.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_same_csr_outstanding.3894239918
Short name T442
Test name
Test status
Simulation time 1208133393 ps
CPU time 5.87 seconds
Started Jan 24 02:37:40 PM PST 24
Finished Jan 24 02:38:10 PM PST 24
Peak memory 210988 kb
Host smart-e2baa018-10d9-4505-a345-831eace0271a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894239918 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_c
trl_same_csr_outstanding.3894239918
Directory /workspace/7.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_errors.452560688
Short name T447
Test name
Test status
Simulation time 546371277 ps
CPU time 9.7 seconds
Started Jan 24 02:06:17 PM PST 24
Finished Jan 24 02:07:21 PM PST 24
Peak memory 219028 kb
Host smart-aed597d4-7f38-4f98-97de-467442a97e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452560688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_errors.452560688
Directory /workspace/7.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.1703673529
Short name T109
Test name
Test status
Simulation time 741323705 ps
CPU time 70.14 seconds
Started Jan 24 02:06:13 PM PST 24
Finished Jan 24 02:08:14 PM PST 24
Peak memory 212156 kb
Host smart-9879832a-8976-47ef-8cb8-025266ca7530
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703673529 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_tl_in
tg_err.1703673529
Directory /workspace/7.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_mem_rw_with_rand_reset.3866375798
Short name T68
Test name
Test status
Simulation time 2062702504 ps
CPU time 8.09 seconds
Started Jan 24 02:19:57 PM PST 24
Finished Jan 24 02:20:12 PM PST 24
Peak memory 219284 kb
Host smart-7de70b08-cca7-41e8-bfaa-c74f35a6eda7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866375798 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rom_ctrl_csr_mem_rw_with_rand_reset.3866375798
Directory /workspace/8.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_csr_rw.2854311484
Short name T434
Test name
Test status
Simulation time 422395355 ps
CPU time 5.66 seconds
Started Jan 24 02:06:16 PM PST 24
Finished Jan 24 02:07:13 PM PST 24
Peak memory 210936 kb
Host smart-3876d1a6-3293-4c7f-b7c4-8f053b73f80e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854311484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_csr_rw.2854311484
Directory /workspace/8.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_passthru_mem_tl_intg_err.582411395
Short name T95
Test name
Test status
Simulation time 989686491 ps
CPU time 50.66 seconds
Started Jan 24 02:06:19 PM PST 24
Finished Jan 24 02:08:02 PM PST 24
Peak memory 218984 kb
Host smart-328d3236-bccd-41c3-9723-edc1b82a46ef
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582411395 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_pas
sthru_mem_tl_intg_err.582411395
Directory /workspace/8.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_same_csr_outstanding.2857306474
Short name T422
Test name
Test status
Simulation time 1966474322 ps
CPU time 7.34 seconds
Started Jan 24 02:40:02 PM PST 24
Finished Jan 24 02:40:26 PM PST 24
Peak memory 211056 kb
Host smart-3d408fe5-ae72-498a-9c95-8cf0865a7398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857306474 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=r
om_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_c
trl_same_csr_outstanding.2857306474
Directory /workspace/8.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.4032100116
Short name T419
Test name
Test status
Simulation time 5314842259 ps
CPU time 74.82 seconds
Started Jan 24 02:20:10 PM PST 24
Finished Jan 24 02:21:43 PM PST 24
Peak memory 211456 kb
Host smart-d8086fb5-9729-48c7-8d2e-53c6de49b434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032100116 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_tl_in
tg_err.4032100116
Directory /workspace/8.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_mem_rw_with_rand_reset.2347583740
Short name T59
Test name
Test status
Simulation time 168729122 ps
CPU time 5.46 seconds
Started Jan 24 02:06:23 PM PST 24
Finished Jan 24 02:07:21 PM PST 24
Peak memory 219212 kb
Host smart-e0b5e888-899e-4466-b81d-a8db9ebec4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347583740 -assert nopostproc +UVM_TESTNAME
=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rom_ctrl_csr_mem_rw_with_rand_reset.2347583740
Directory /workspace/9.rom_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_csr_rw.3948077688
Short name T437
Test name
Test status
Simulation time 424526810 ps
CPU time 6.92 seconds
Started Jan 24 02:06:24 PM PST 24
Finished Jan 24 02:07:22 PM PST 24
Peak memory 216284 kb
Host smart-522e89b1-3035-45d7-9ee1-33a05c4b938b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948077688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_csr_rw.3948077688
Directory /workspace/9.rom_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_passthru_mem_tl_intg_err.4147180586
Short name T93
Test name
Test status
Simulation time 77848337992 ps
CPU time 321.68 seconds
Started Jan 24 02:44:09 PM PST 24
Finished Jan 24 02:49:43 PM PST 24
Peak memory 211080 kb
Host smart-07ae940e-31a7-4156-87a0-82b2599590f5
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147180586 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_pa
ssthru_mem_tl_intg_err.4147180586
Directory /workspace/9.rom_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_same_csr_outstanding.450673382
Short name T432
Test name
Test status
Simulation time 303050342 ps
CPU time 6.39 seconds
Started Jan 24 02:06:23 PM PST 24
Finished Jan 24 02:07:22 PM PST 24
Peak memory 210984 kb
Host smart-b44f8df7-0bfc-4d46-93ee-a474514d5148
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450673382 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=ro
m_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ct
rl_same_csr_outstanding.450673382
Directory /workspace/9.rom_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_errors.3664655758
Short name T445
Test name
Test status
Simulation time 232217508 ps
CPU time 9.75 seconds
Started Jan 24 02:06:23 PM PST 24
Finished Jan 24 02:07:25 PM PST 24
Peak memory 219164 kb
Host smart-459b530f-b777-48db-afc1-8588a7d6c94e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664655758 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_errors.3664655758
Directory /workspace/9.rom_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.1279057931
Short name T114
Test name
Test status
Simulation time 15476819357 ps
CPU time 78.14 seconds
Started Jan 24 02:06:17 PM PST 24
Finished Jan 24 02:08:29 PM PST 24
Peak memory 211464 kb
Host smart-a392cbea-4945-41ab-a48c-fd5ffa63604f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279057931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_tl_in
tg_err.1279057931
Directory /workspace/9.rom_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.rom_ctrl_alert_test.4135149962
Short name T218
Test name
Test status
Simulation time 334230452 ps
CPU time 4.27 seconds
Started Jan 24 03:04:06 PM PST 24
Finished Jan 24 03:04:25 PM PST 24
Peak memory 211004 kb
Host smart-de70b831-c830-4ae0-b1dc-932abdef9c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135149962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_alert_test.4135149962
Directory /workspace/0.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2335485348
Short name T324
Test name
Test status
Simulation time 2938463674 ps
CPU time 137.93 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:32:21 PM PST 24
Peak memory 236380 kb
Host smart-1a03b461-e05b-45fa-8df3-1f6bce360d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335485348 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_c
orrupt_sig_fatal_chk.2335485348
Directory /workspace/0.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_kmac_err_chk.453842203
Short name T376
Test name
Test status
Simulation time 3438726381 ps
CPU time 31.2 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:30:35 PM PST 24
Peak memory 211240 kb
Host smart-946e1135-88e6-44a3-861b-943b293637e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453842203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_kmac_err_chk.453842203
Directory /workspace/0.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_max_throughput_chk.58991408
Short name T408
Test name
Test status
Simulation time 1051376725 ps
CPU time 11.08 seconds
Started Jan 24 03:25:53 PM PST 24
Finished Jan 24 03:26:24 PM PST 24
Peak memory 211008 kb
Host smart-fb08dc7d-bee1-48da-a899-dda3d4d40076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58991408 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_max_throughput_chk.58991408
Directory /workspace/0.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/0.rom_ctrl_sec_cm.860255521
Short name T50
Test name
Test status
Simulation time 1674191470 ps
CPU time 109.85 seconds
Started Jan 24 02:29:52 PM PST 24
Finished Jan 24 02:31:56 PM PST 24
Peak memory 235344 kb
Host smart-b781ad89-1834-4d8c-a995-5d2837d86bbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860255521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_sec_cm.860255521
Directory /workspace/0.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.rom_ctrl_smoke.823448041
Short name T328
Test name
Test status
Simulation time 1391930738 ps
CPU time 10.29 seconds
Started Jan 24 02:29:51 PM PST 24
Finished Jan 24 02:30:15 PM PST 24
Peak memory 212804 kb
Host smart-8abd5a7d-d83a-49c3-b171-4c049ac549df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823448041 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_smoke.823448041
Directory /workspace/0.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all.2460380602
Short name T186
Test name
Test status
Simulation time 1574096584 ps
CPU time 17.42 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:30:21 PM PST 24
Peak memory 214444 kb
Host smart-9b8a9552-9d01-4d89-a628-c4d96fee3e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460380602 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.rom_ctrl_stress_all.2460380602
Directory /workspace/0.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.254595272
Short name T6
Test name
Test status
Simulation time 11497725785 ps
CPU time 515.06 seconds
Started Jan 24 02:29:52 PM PST 24
Finished Jan 24 02:38:42 PM PST 24
Peak memory 222948 kb
Host smart-e020af8e-2e7e-4307-9429-2af6f7d27f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254595272 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rom_ctrl_stress_all_with_rand_reset.254595272
Directory /workspace/0.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rom_ctrl_alert_test.912995311
Short name T205
Test name
Test status
Simulation time 2920076540 ps
CPU time 12.94 seconds
Started Jan 24 02:30:02 PM PST 24
Finished Jan 24 02:30:32 PM PST 24
Peak memory 211060 kb
Host smart-93af144f-fafa-4c9c-a173-2a6a7b8b211b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912995311 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_alert_test.912995311
Directory /workspace/1.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2979289356
Short name T295
Test name
Test status
Simulation time 2112006466 ps
CPU time 140.12 seconds
Started Jan 24 02:29:50 PM PST 24
Finished Jan 24 02:32:23 PM PST 24
Peak memory 227320 kb
Host smart-aeba0cb1-8a75-4be5-9fb5-14451338635a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979289356 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_c
orrupt_sig_fatal_chk.2979289356
Directory /workspace/1.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_kmac_err_chk.143910755
Short name T180
Test name
Test status
Simulation time 1650065145 ps
CPU time 18.51 seconds
Started Jan 24 02:29:53 PM PST 24
Finished Jan 24 02:30:26 PM PST 24
Peak memory 211192 kb
Host smart-ce72096c-13b4-48ca-95e4-8cd76a07bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143910755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_kmac_err_chk.143910755
Directory /workspace/1.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/1.rom_ctrl_sec_cm.2797942415
Short name T41
Test name
Test status
Simulation time 3397498375 ps
CPU time 106.74 seconds
Started Jan 24 02:30:05 PM PST 24
Finished Jan 24 02:32:07 PM PST 24
Peak memory 236520 kb
Host smart-3da73265-d6ca-4c3c-b2ec-b8470ff63680
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797942415 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_sec_cm.2797942415
Directory /workspace/1.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.rom_ctrl_smoke.3198972597
Short name T364
Test name
Test status
Simulation time 5425091459 ps
CPU time 30.11 seconds
Started Jan 24 02:29:53 PM PST 24
Finished Jan 24 02:30:37 PM PST 24
Peak memory 212872 kb
Host smart-0f11d1b3-740f-4ec2-8c71-1a922b2aea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198972597 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_ctrl_smoke.3198972597
Directory /workspace/1.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/1.rom_ctrl_stress_all.777538022
Short name T240
Test name
Test status
Simulation time 26127104840 ps
CPU time 69.59 seconds
Started Jan 24 02:46:17 PM PST 24
Finished Jan 24 02:47:29 PM PST 24
Peak memory 219336 kb
Host smart-47745ce8-7511-4b18-b8fe-2ce821fe4d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777538022 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.rom_ctrl_stress_all.777538022
Directory /workspace/1.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.rom_ctrl_max_throughput_chk.3012908516
Short name T285
Test name
Test status
Simulation time 3628414573 ps
CPU time 12.17 seconds
Started Jan 24 03:13:36 PM PST 24
Finished Jan 24 03:13:49 PM PST 24
Peak memory 211144 kb
Host smart-d0647a7c-ba75-4f90-82d9-07c3a392bd0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012908516 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_max_throughput_chk.3012908516
Directory /workspace/10.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/10.rom_ctrl_smoke.2520169694
Short name T275
Test name
Test status
Simulation time 192936700 ps
CPU time 10.13 seconds
Started Jan 24 02:30:48 PM PST 24
Finished Jan 24 02:31:05 PM PST 24
Peak memory 211672 kb
Host smart-89128021-1cad-4cec-9fff-70c07049fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520169694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rom_ctrl_smoke.2520169694
Directory /workspace/10.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/10.rom_ctrl_stress_all.3192267792
Short name T101
Test name
Test status
Simulation time 105335485 ps
CPU time 5.55 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:02 PM PST 24
Peak memory 210972 kb
Host smart-59c055fa-908d-4638-aad2-1f29075e729d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192267792 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.rom_ctrl_stress_all.3192267792
Directory /workspace/10.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.rom_ctrl_alert_test.4067001645
Short name T255
Test name
Test status
Simulation time 2126413302 ps
CPU time 16.01 seconds
Started Jan 24 05:56:00 PM PST 24
Finished Jan 24 05:56:16 PM PST 24
Peak memory 210980 kb
Host smart-dbf74422-af78-4caf-8caf-149baac24929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067001645 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_alert_test.4067001645
Directory /workspace/11.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.3060209491
Short name T197
Test name
Test status
Simulation time 70509376840 ps
CPU time 332.06 seconds
Started Jan 24 04:16:40 PM PST 24
Finished Jan 24 04:22:13 PM PST 24
Peak memory 236660 kb
Host smart-9892e603-9dc7-416d-b994-b48ad9814632
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060209491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_
corrupt_sig_fatal_chk.3060209491
Directory /workspace/11.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_max_throughput_chk.1028607857
Short name T346
Test name
Test status
Simulation time 1583357111 ps
CPU time 7.98 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:05 PM PST 24
Peak memory 210984 kb
Host smart-56eea73b-295f-4656-a961-0ad3dcf6853f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028607857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_max_throughput_chk.1028607857
Directory /workspace/11.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/11.rom_ctrl_smoke.4005506092
Short name T158
Test name
Test status
Simulation time 4266266137 ps
CPU time 33.93 seconds
Started Jan 24 04:16:37 PM PST 24
Finished Jan 24 04:17:12 PM PST 24
Peak memory 212244 kb
Host smart-2516fa87-328e-450e-afe0-4b1dcda8e03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005506092 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rom_ctrl_smoke.4005506092
Directory /workspace/11.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/11.rom_ctrl_stress_all.916401482
Short name T231
Test name
Test status
Simulation time 625549674 ps
CPU time 18.91 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:15 PM PST 24
Peak memory 213608 kb
Host smart-388ad021-1937-4012-86bc-ffe930e6996a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916401482 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.rom_ctrl_stress_all.916401482
Directory /workspace/11.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.rom_ctrl_alert_test.1481670128
Short name T156
Test name
Test status
Simulation time 397106140 ps
CPU time 4.41 seconds
Started Jan 24 02:30:55 PM PST 24
Finished Jan 24 02:31:04 PM PST 24
Peak memory 211004 kb
Host smart-216773f1-99c1-4b48-90e2-bb2d664ff037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481670128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_alert_test.1481670128
Directory /workspace/12.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.583172657
Short name T310
Test name
Test status
Simulation time 28536376485 ps
CPU time 317.24 seconds
Started Jan 24 02:44:18 PM PST 24
Finished Jan 24 02:49:56 PM PST 24
Peak memory 228252 kb
Host smart-dd30408e-c9d3-45d3-b807-7f7eb3764a28
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583172657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_c
orrupt_sig_fatal_chk.583172657
Directory /workspace/12.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_kmac_err_chk.1175484096
Short name T182
Test name
Test status
Simulation time 7306297302 ps
CPU time 31.3 seconds
Started Jan 24 02:30:53 PM PST 24
Finished Jan 24 02:31:29 PM PST 24
Peak memory 211600 kb
Host smart-22037fb7-d528-4f10-a247-2d6ef5a7cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175484096 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_kmac_err_chk.1175484096
Directory /workspace/12.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_max_throughput_chk.417220128
Short name T220
Test name
Test status
Simulation time 3971280334 ps
CPU time 11.99 seconds
Started Jan 24 02:30:56 PM PST 24
Finished Jan 24 02:31:12 PM PST 24
Peak memory 211068 kb
Host smart-88c5755b-ed8c-4723-b126-74d4f6542b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=417220128 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_max_throughput_chk.417220128
Directory /workspace/12.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/12.rom_ctrl_smoke.4011292741
Short name T359
Test name
Test status
Simulation time 9291521339 ps
CPU time 26.4 seconds
Started Jan 24 02:30:54 PM PST 24
Finished Jan 24 02:31:25 PM PST 24
Peak memory 212216 kb
Host smart-c0ce9f75-970e-4e78-86b4-32c6309af0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011292741 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rom_ctrl_smoke.4011292741
Directory /workspace/12.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/12.rom_ctrl_stress_all.872863911
Short name T131
Test name
Test status
Simulation time 9361329003 ps
CPU time 69.82 seconds
Started Jan 24 03:24:51 PM PST 24
Finished Jan 24 03:26:21 PM PST 24
Peak memory 215952 kb
Host smart-3e3ae49d-d878-4ea3-890b-e34f363b8d29
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872863911 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.rom_ctrl_stress_all.872863911
Directory /workspace/12.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.rom_ctrl_alert_test.601422946
Short name T374
Test name
Test status
Simulation time 5261204730 ps
CPU time 12.17 seconds
Started Jan 24 04:02:22 PM PST 24
Finished Jan 24 04:02:36 PM PST 24
Peak memory 211164 kb
Host smart-f558b11e-29b9-4329-ad03-417ef0313f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601422946 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_alert_test.601422946
Directory /workspace/13.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3415248889
Short name T290
Test name
Test status
Simulation time 3675460795 ps
CPU time 94.69 seconds
Started Jan 24 02:31:02 PM PST 24
Finished Jan 24 02:32:42 PM PST 24
Peak memory 232500 kb
Host smart-024b1c6b-95e4-4c77-b525-abc81c492800
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415248889 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_
corrupt_sig_fatal_chk.3415248889
Directory /workspace/13.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_kmac_err_chk.4126053484
Short name T351
Test name
Test status
Simulation time 8531860321 ps
CPU time 21.52 seconds
Started Jan 24 02:31:08 PM PST 24
Finished Jan 24 02:31:34 PM PST 24
Peak memory 211988 kb
Host smart-1f233dce-827f-4c95-826d-725d72769bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126053484 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_kmac_err_chk.4126053484
Directory /workspace/13.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_max_throughput_chk.3561244936
Short name T211
Test name
Test status
Simulation time 3770159165 ps
CPU time 12.87 seconds
Started Jan 24 03:53:22 PM PST 24
Finished Jan 24 03:53:47 PM PST 24
Peak memory 211148 kb
Host smart-815812fa-f828-4831-8916-e87ef3b54462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561244936 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_max_throughput_chk.3561244936
Directory /workspace/13.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/13.rom_ctrl_smoke.2758994065
Short name T283
Test name
Test status
Simulation time 730395328 ps
CPU time 9.77 seconds
Started Jan 24 03:31:18 PM PST 24
Finished Jan 24 03:31:34 PM PST 24
Peak memory 212920 kb
Host smart-010dd5c5-4b06-4990-ba01-7089d38032bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758994065 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rom_ctrl_smoke.2758994065
Directory /workspace/13.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/13.rom_ctrl_stress_all.2259006561
Short name T268
Test name
Test status
Simulation time 81683703135 ps
CPU time 43.47 seconds
Started Jan 24 02:30:54 PM PST 24
Finished Jan 24 02:31:42 PM PST 24
Peak memory 214884 kb
Host smart-93f5a890-bc28-44f1-a6e5-515af5b1ce5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259006561 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 13.rom_ctrl_stress_all.2259006561
Directory /workspace/13.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_alert_test.2062118538
Short name T252
Test name
Test status
Simulation time 3832528875 ps
CPU time 15.71 seconds
Started Jan 24 03:23:18 PM PST 24
Finished Jan 24 03:23:37 PM PST 24
Peak memory 211132 kb
Host smart-29f3dcd6-d154-4fb3-9ac3-c73ff9914a3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062118538 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_alert_test.2062118538
Directory /workspace/14.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1406874136
Short name T200
Test name
Test status
Simulation time 13486584905 ps
CPU time 223.29 seconds
Started Jan 24 04:35:34 PM PST 24
Finished Jan 24 04:39:28 PM PST 24
Peak memory 237692 kb
Host smart-2fa761b2-541d-4919-a0bf-e120130a6938
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406874136 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_
corrupt_sig_fatal_chk.1406874136
Directory /workspace/14.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_kmac_err_chk.797040159
Short name T269
Test name
Test status
Simulation time 7327276113 ps
CPU time 21.93 seconds
Started Jan 24 02:31:08 PM PST 24
Finished Jan 24 02:31:35 PM PST 24
Peak memory 211916 kb
Host smart-85667363-26bd-4530-8ffd-2f4889c40010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797040159 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_kmac_err_chk.797040159
Directory /workspace/14.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_max_throughput_chk.2832053286
Short name T174
Test name
Test status
Simulation time 740461592 ps
CPU time 9.77 seconds
Started Jan 24 02:31:07 PM PST 24
Finished Jan 24 02:31:22 PM PST 24
Peak memory 211016 kb
Host smart-ae92675e-07ec-4509-9d13-5c071bd83bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832053286 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_max_throughput_chk.2832053286
Directory /workspace/14.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/14.rom_ctrl_smoke.344008559
Short name T262
Test name
Test status
Simulation time 725706536 ps
CPU time 10.26 seconds
Started Jan 24 02:31:11 PM PST 24
Finished Jan 24 02:31:25 PM PST 24
Peak memory 213260 kb
Host smart-8b7c59ae-582b-4c37-9060-23a2266ca36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344008559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_smoke.344008559
Directory /workspace/14.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all.3048858828
Short name T308
Test name
Test status
Simulation time 670031394 ps
CPU time 34.67 seconds
Started Jan 24 02:31:05 PM PST 24
Finished Jan 24 02:31:44 PM PST 24
Peak memory 214920 kb
Host smart-fce8ed11-0083-44b8-bb91-f6bfea3ba60b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048858828 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 14.rom_ctrl_stress_all.3048858828
Directory /workspace/14.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3585011293
Short name T331
Test name
Test status
Simulation time 39886508752 ps
CPU time 1951.37 seconds
Started Jan 24 02:41:44 PM PST 24
Finished Jan 24 03:14:22 PM PST 24
Peak memory 235752 kb
Host smart-44f937c2-1c81-4a52-a439-59c9083c6ff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585011293 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rom_ctrl_stress_all_with_rand_reset.3585011293
Directory /workspace/14.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rom_ctrl_alert_test.3202243845
Short name T284
Test name
Test status
Simulation time 7794166870 ps
CPU time 13.98 seconds
Started Jan 24 02:31:20 PM PST 24
Finished Jan 24 02:31:43 PM PST 24
Peak memory 211080 kb
Host smart-01f4098a-548c-4fba-99ee-e6d5f6d496ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202243845 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_alert_test.3202243845
Directory /workspace/15.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.rom_ctrl_kmac_err_chk.4265928908
Short name T368
Test name
Test status
Simulation time 2716112170 ps
CPU time 26.7 seconds
Started Jan 24 02:39:57 PM PST 24
Finished Jan 24 02:40:35 PM PST 24
Peak memory 211336 kb
Host smart-71a49640-4c94-44d5-a0cb-aef255d2e176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265928908 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_kmac_err_chk.4265928908
Directory /workspace/15.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_max_throughput_chk.3287794634
Short name T358
Test name
Test status
Simulation time 670947716 ps
CPU time 9.71 seconds
Started Jan 24 02:46:20 PM PST 24
Finished Jan 24 02:46:32 PM PST 24
Peak memory 211036 kb
Host smart-4c49e072-265a-4be3-88ec-865469b052a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3287794634 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_max_throughput_chk.3287794634
Directory /workspace/15.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/15.rom_ctrl_smoke.1630599367
Short name T388
Test name
Test status
Simulation time 2920952983 ps
CPU time 27.53 seconds
Started Jan 24 02:31:07 PM PST 24
Finished Jan 24 02:31:40 PM PST 24
Peak memory 212268 kb
Host smart-773f89a3-0bc7-45b1-9caa-a4b88add285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630599367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rom_ctrl_smoke.1630599367
Directory /workspace/15.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/15.rom_ctrl_stress_all.2724379580
Short name T8
Test name
Test status
Simulation time 1590782296 ps
CPU time 15.16 seconds
Started Jan 24 02:31:16 PM PST 24
Finished Jan 24 02:31:33 PM PST 24
Peak memory 210880 kb
Host smart-ebe83f4d-7df4-49f2-91f0-30e0eeabd28d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724379580 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 15.rom_ctrl_stress_all.2724379580
Directory /workspace/15.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_alert_test.1185953990
Short name T43
Test name
Test status
Simulation time 1533185969 ps
CPU time 6.89 seconds
Started Jan 24 02:31:30 PM PST 24
Finished Jan 24 02:31:57 PM PST 24
Peak memory 210920 kb
Host smart-0b1b68d1-571d-4f8a-89e3-e3fa8e9ddd80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185953990 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_alert_test.1185953990
Directory /workspace/16.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2367641271
Short name T306
Test name
Test status
Simulation time 235427359552 ps
CPU time 190.02 seconds
Started Jan 24 02:31:31 PM PST 24
Finished Jan 24 02:35:03 PM PST 24
Peak memory 211320 kb
Host smart-ef91c43a-0eeb-4eb8-8c8d-018ed02abb56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367641271 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_
corrupt_sig_fatal_chk.2367641271
Directory /workspace/16.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_kmac_err_chk.3636229391
Short name T355
Test name
Test status
Simulation time 2656840658 ps
CPU time 15.24 seconds
Started Jan 24 02:38:51 PM PST 24
Finished Jan 24 02:39:11 PM PST 24
Peak memory 211268 kb
Host smart-93c1082b-209e-485d-a890-73cd8d14e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636229391 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_kmac_err_chk.3636229391
Directory /workspace/16.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_max_throughput_chk.148149944
Short name T179
Test name
Test status
Simulation time 2042239284 ps
CPU time 16.57 seconds
Started Jan 24 04:14:10 PM PST 24
Finished Jan 24 04:14:35 PM PST 24
Peak memory 210984 kb
Host smart-fbce06fd-088c-477f-b6f1-88ce8782c403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=148149944 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_max_throughput_chk.148149944
Directory /workspace/16.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/16.rom_ctrl_smoke.2677579051
Short name T287
Test name
Test status
Simulation time 18098740021 ps
CPU time 23.67 seconds
Started Jan 24 02:31:16 PM PST 24
Finished Jan 24 02:31:41 PM PST 24
Peak memory 213448 kb
Host smart-4aaedc7b-8bef-436e-8699-77b32ee13dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677579051 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_smoke.2677579051
Directory /workspace/16.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all.425623922
Short name T90
Test name
Test status
Simulation time 585622129 ps
CPU time 9.21 seconds
Started Jan 24 02:31:16 PM PST 24
Finished Jan 24 02:31:27 PM PST 24
Peak memory 211028 kb
Host smart-d22eecbc-44e0-4da8-a5ee-4b9d1f829b64
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425623922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.rom_ctrl_stress_all.425623922
Directory /workspace/16.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.1218246807
Short name T339
Test name
Test status
Simulation time 131387961566 ps
CPU time 2631.51 seconds
Started Jan 24 02:31:31 PM PST 24
Finished Jan 24 03:15:45 PM PST 24
Peak memory 232136 kb
Host smart-0ff600c9-4dd9-479b-9920-5a37f2511aed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218246807 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rom_ctrl_stress_all_with_rand_reset.1218246807
Directory /workspace/16.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rom_ctrl_alert_test.3452075562
Short name T229
Test name
Test status
Simulation time 6857839771 ps
CPU time 14.72 seconds
Started Jan 24 02:31:38 PM PST 24
Finished Jan 24 02:32:15 PM PST 24
Peak memory 211068 kb
Host smart-4797a6bc-e48b-404a-b91b-d5b9148aba84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452075562 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_alert_test.3452075562
Directory /workspace/17.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1354818197
Short name T28
Test name
Test status
Simulation time 68720354910 ps
CPU time 312.59 seconds
Started Jan 24 04:21:17 PM PST 24
Finished Jan 24 04:26:39 PM PST 24
Peak memory 237628 kb
Host smart-a0630e5b-9508-44f7-89bf-34ffbfc59e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354818197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_
corrupt_sig_fatal_chk.1354818197
Directory /workspace/17.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_kmac_err_chk.512309211
Short name T361
Test name
Test status
Simulation time 21562160461 ps
CPU time 26.59 seconds
Started Jan 24 02:31:28 PM PST 24
Finished Jan 24 02:32:07 PM PST 24
Peak memory 211972 kb
Host smart-84a4cf8a-269f-4977-903e-edfb7b4bc732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512309211 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_kmac_err_chk.512309211
Directory /workspace/17.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_max_throughput_chk.1172046841
Short name T325
Test name
Test status
Simulation time 4392287848 ps
CPU time 12.89 seconds
Started Jan 24 02:31:29 PM PST 24
Finished Jan 24 02:31:57 PM PST 24
Peak memory 211100 kb
Host smart-704dc7be-cbc5-4b20-b25b-c9535b9d12cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172046841 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_max_throughput_chk.1172046841
Directory /workspace/17.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/17.rom_ctrl_smoke.2420847724
Short name T212
Test name
Test status
Simulation time 1103009822 ps
CPU time 12.18 seconds
Started Jan 24 02:48:00 PM PST 24
Finished Jan 24 02:48:40 PM PST 24
Peak memory 213320 kb
Host smart-d05829a5-fbf4-4a78-942d-4d4a2db9c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420847724 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rom_ctrl_smoke.2420847724
Directory /workspace/17.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/17.rom_ctrl_stress_all.2010590579
Short name T341
Test name
Test status
Simulation time 4542505047 ps
CPU time 25.74 seconds
Started Jan 24 02:31:29 PM PST 24
Finished Jan 24 02:32:11 PM PST 24
Peak memory 213072 kb
Host smart-2156e29d-b986-48e9-b29e-55fc9d982fd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010590579 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.rom_ctrl_stress_all.2010590579
Directory /workspace/17.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_alert_test.791845457
Short name T194
Test name
Test status
Simulation time 8534469907 ps
CPU time 15.8 seconds
Started Jan 24 02:31:41 PM PST 24
Finished Jan 24 02:32:20 PM PST 24
Peak memory 211104 kb
Host smart-a94b7475-9b95-4814-ac6d-1d4b19961773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791845457 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_alert_test.791845457
Directory /workspace/18.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.2345488244
Short name T302
Test name
Test status
Simulation time 23337288106 ps
CPU time 202.09 seconds
Started Jan 24 02:36:40 PM PST 24
Finished Jan 24 02:40:33 PM PST 24
Peak memory 236656 kb
Host smart-c925c906-9c6b-48c9-b2c7-263ffc7efd74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345488244 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_
corrupt_sig_fatal_chk.2345488244
Directory /workspace/18.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_kmac_err_chk.2298753194
Short name T153
Test name
Test status
Simulation time 8502894967 ps
CPU time 22.55 seconds
Started Jan 24 04:26:09 PM PST 24
Finished Jan 24 04:26:33 PM PST 24
Peak memory 212144 kb
Host smart-c548c249-f90e-4f2d-8997-d59187a26a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298753194 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_kmac_err_chk.2298753194
Directory /workspace/18.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_max_throughput_chk.1800867114
Short name T138
Test name
Test status
Simulation time 3367369158 ps
CPU time 8.77 seconds
Started Jan 24 02:50:28 PM PST 24
Finished Jan 24 02:50:49 PM PST 24
Peak memory 211140 kb
Host smart-a5b6b9da-aeb0-4bb5-a9a3-43128d801eaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800867114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_max_throughput_chk.1800867114
Directory /workspace/18.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/18.rom_ctrl_smoke.2011676540
Short name T17
Test name
Test status
Simulation time 13852388350 ps
CPU time 31.34 seconds
Started Jan 24 02:31:39 PM PST 24
Finished Jan 24 02:32:33 PM PST 24
Peak memory 213108 kb
Host smart-cc41ec66-ea3e-49e0-be44-1f80558867b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011676540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_smoke.2011676540
Directory /workspace/18.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all.4191794687
Short name T154
Test name
Test status
Simulation time 25394981187 ps
CPU time 50.54 seconds
Started Jan 24 02:31:39 PM PST 24
Finished Jan 24 02:32:52 PM PST 24
Peak memory 216340 kb
Host smart-74d8395b-576f-482e-aff2-991cc108376d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191794687 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 18.rom_ctrl_stress_all.4191794687
Directory /workspace/18.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.76030957
Short name T375
Test name
Test status
Simulation time 8361113493 ps
CPU time 862.23 seconds
Started Jan 24 02:31:40 PM PST 24
Finished Jan 24 02:46:26 PM PST 24
Peak memory 227452 kb
Host smart-6099f61c-19de-477a-b2db-8b51c34b6c97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76030957 -assert nopos
tproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 18.rom_ctrl_stress_all_with_rand_reset.76030957
Directory /workspace/18.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rom_ctrl_alert_test.2395979896
Short name T148
Test name
Test status
Simulation time 685953676 ps
CPU time 6.59 seconds
Started Jan 24 02:31:49 PM PST 24
Finished Jan 24 02:32:25 PM PST 24
Peak memory 211016 kb
Host smart-79dc06ba-e52c-47c6-91fe-816ba2463f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395979896 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_alert_test.2395979896
Directory /workspace/19.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.2930464890
Short name T207
Test name
Test status
Simulation time 3754985713 ps
CPU time 129.31 seconds
Started Jan 24 02:31:39 PM PST 24
Finished Jan 24 02:34:11 PM PST 24
Peak memory 228404 kb
Host smart-a79166ed-7dcb-4c4b-b6f4-a76256c77058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930464890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_
corrupt_sig_fatal_chk.2930464890
Directory /workspace/19.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_kmac_err_chk.4219654204
Short name T320
Test name
Test status
Simulation time 3559122436 ps
CPU time 30.98 seconds
Started Jan 24 02:31:40 PM PST 24
Finished Jan 24 02:32:35 PM PST 24
Peak memory 211028 kb
Host smart-5c6f4d20-7535-4c7d-955b-dc70ddf3eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219654204 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_kmac_err_chk.4219654204
Directory /workspace/19.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_max_throughput_chk.691800142
Short name T274
Test name
Test status
Simulation time 423049361 ps
CPU time 7.29 seconds
Started Jan 24 02:31:38 PM PST 24
Finished Jan 24 02:32:08 PM PST 24
Peak memory 210948 kb
Host smart-52b60b1e-b554-4514-95a8-e06bbe72ae82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691800142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_max_throughput_chk.691800142
Directory /workspace/19.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/19.rom_ctrl_smoke.3456520716
Short name T191
Test name
Test status
Simulation time 182248409 ps
CPU time 10.32 seconds
Started Jan 24 02:31:46 PM PST 24
Finished Jan 24 02:32:26 PM PST 24
Peak memory 212592 kb
Host smart-e73ca43f-1f29-4379-80fa-bd18be24470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456520716 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_smoke.3456520716
Directory /workspace/19.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all.2345469986
Short name T398
Test name
Test status
Simulation time 1924383175 ps
CPU time 31.96 seconds
Started Jan 24 03:11:01 PM PST 24
Finished Jan 24 03:11:37 PM PST 24
Peak memory 215616 kb
Host smart-cd4ca7f1-ecb1-47c8-94a1-7d02611b6884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345469986 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 19.rom_ctrl_stress_all.2345469986
Directory /workspace/19.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.660592341
Short name T365
Test name
Test status
Simulation time 42960953026 ps
CPU time 849.64 seconds
Started Jan 24 02:48:45 PM PST 24
Finished Jan 24 03:03:16 PM PST 24
Peak memory 227576 kb
Host smart-fa41f9f5-e19e-4540-8337-f720ee147f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660592341 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rom_ctrl_stress_all_with_rand_reset.660592341
Directory /workspace/19.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rom_ctrl_alert_test.1648238954
Short name T144
Test name
Test status
Simulation time 4448525356 ps
CPU time 10.82 seconds
Started Jan 24 02:30:12 PM PST 24
Finished Jan 24 02:30:38 PM PST 24
Peak memory 211068 kb
Host smart-43e2aabb-4cc6-4be5-a61f-49d3be470374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648238954 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_alert_test.1648238954
Directory /workspace/2.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2335343146
Short name T53
Test name
Test status
Simulation time 34713552502 ps
CPU time 282.22 seconds
Started Jan 24 02:30:12 PM PST 24
Finished Jan 24 02:35:09 PM PST 24
Peak memory 224628 kb
Host smart-f81ad2fa-a164-4c5c-bc1e-af197e70966a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335343146 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_c
orrupt_sig_fatal_chk.2335343146
Directory /workspace/2.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_kmac_err_chk.2994131584
Short name T141
Test name
Test status
Simulation time 2135762301 ps
CPU time 16.9 seconds
Started Jan 24 02:30:12 PM PST 24
Finished Jan 24 02:30:44 PM PST 24
Peak memory 211228 kb
Host smart-f3ec0bb4-e1f4-48fd-b969-f32cf17816a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994131584 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_kmac_err_chk.2994131584
Directory /workspace/2.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_max_throughput_chk.3302221058
Short name T245
Test name
Test status
Simulation time 1482344493 ps
CPU time 13.19 seconds
Started Jan 24 02:30:18 PM PST 24
Finished Jan 24 02:30:46 PM PST 24
Peak memory 211012 kb
Host smart-c1bb7c77-be85-406a-8b71-5a5e2f23095e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302221058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_max_throughput_chk.3302221058
Directory /workspace/2.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/2.rom_ctrl_sec_cm.2437707085
Short name T40
Test name
Test status
Simulation time 2300577339 ps
CPU time 55.95 seconds
Started Jan 24 02:30:10 PM PST 24
Finished Jan 24 02:31:21 PM PST 24
Peak memory 236696 kb
Host smart-5ae50fa9-8c73-478c-bca4-8e31ad4010e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437707085 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_sec_cm.2437707085
Directory /workspace/2.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.rom_ctrl_smoke.3816675114
Short name T5
Test name
Test status
Simulation time 3097974950 ps
CPU time 36.07 seconds
Started Jan 24 03:52:01 PM PST 24
Finished Jan 24 03:52:38 PM PST 24
Peak memory 212804 kb
Host smart-777c80f6-1c60-43dd-9549-107ea9147742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816675114 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_ctrl_smoke.3816675114
Directory /workspace/2.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/2.rom_ctrl_stress_all.1219236755
Short name T219
Test name
Test status
Simulation time 212721486 ps
CPU time 8.49 seconds
Started Jan 24 02:37:21 PM PST 24
Finished Jan 24 02:38:00 PM PST 24
Peak memory 210848 kb
Host smart-2ad4ca9d-0b5c-47b0-b58a-9c1d67018267
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219236755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 2.rom_ctrl_stress_all.1219236755
Directory /workspace/2.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_alert_test.750978353
Short name T42
Test name
Test status
Simulation time 690767917 ps
CPU time 5.42 seconds
Started Jan 24 02:31:50 PM PST 24
Finished Jan 24 02:32:24 PM PST 24
Peak memory 210984 kb
Host smart-cba2b5ee-23c6-410e-830b-68d833fc4f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750978353 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_alert_test.750978353
Directory /workspace/20.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.rom_ctrl_corrupt_sig_fatal_chk.3354612488
Short name T381
Test name
Test status
Simulation time 39670691413 ps
CPU time 185.1 seconds
Started Jan 24 02:31:52 PM PST 24
Finished Jan 24 02:35:27 PM PST 24
Peak memory 237496 kb
Host smart-5243528c-1df4-477b-afc5-81f5b9ddbeca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354612488 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_
corrupt_sig_fatal_chk.3354612488
Directory /workspace/20.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_kmac_err_chk.2347449943
Short name T317
Test name
Test status
Simulation time 3167283440 ps
CPU time 20.2 seconds
Started Jan 24 02:31:49 PM PST 24
Finished Jan 24 02:32:38 PM PST 24
Peak memory 211296 kb
Host smart-f016d4bd-474c-400b-847f-c219e2cafcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347449943 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_kmac_err_chk.2347449943
Directory /workspace/20.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_max_throughput_chk.1057462508
Short name T221
Test name
Test status
Simulation time 6027727368 ps
CPU time 13.9 seconds
Started Jan 24 02:31:49 PM PST 24
Finished Jan 24 02:32:32 PM PST 24
Peak memory 211100 kb
Host smart-c2a5b64c-120b-4eae-a923-64898b437da7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057462508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_max_throughput_chk.1057462508
Directory /workspace/20.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/20.rom_ctrl_smoke.1343021941
Short name T210
Test name
Test status
Simulation time 11848558075 ps
CPU time 27.53 seconds
Started Jan 24 02:31:47 PM PST 24
Finished Jan 24 02:32:44 PM PST 24
Peak memory 213404 kb
Host smart-f9df0a0f-47e3-4564-bf12-822fb8dbffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343021941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_smoke.1343021941
Directory /workspace/20.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all.1988750923
Short name T273
Test name
Test status
Simulation time 3857731643 ps
CPU time 32.43 seconds
Started Jan 24 02:31:53 PM PST 24
Finished Jan 24 02:32:55 PM PST 24
Peak memory 213132 kb
Host smart-bc1453a6-aed4-4f4a-b61c-3c9b03a9466f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988750923 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.rom_ctrl_stress_all.1988750923
Directory /workspace/20.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.rom_ctrl_stress_all_with_rand_reset.2523244587
Short name T254
Test name
Test status
Simulation time 54223558768 ps
CPU time 504.97 seconds
Started Jan 24 02:31:47 PM PST 24
Finished Jan 24 02:40:42 PM PST 24
Peak memory 233588 kb
Host smart-210e7c31-1da7-41d9-bdea-746d2c8c2b38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523244587 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rom_ctrl_stress_all_with_rand_reset.2523244587
Directory /workspace/20.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rom_ctrl_alert_test.1943596639
Short name T403
Test name
Test status
Simulation time 2187549359 ps
CPU time 16.38 seconds
Started Jan 24 02:42:37 PM PST 24
Finished Jan 24 02:43:17 PM PST 24
Peak memory 211104 kb
Host smart-40f74c7a-b40e-4ec3-b7b1-029c39b03934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943596639 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_alert_test.1943596639
Directory /workspace/21.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.rom_ctrl_corrupt_sig_fatal_chk.504083444
Short name T292
Test name
Test status
Simulation time 5317912165 ps
CPU time 206.6 seconds
Started Jan 24 02:31:52 PM PST 24
Finished Jan 24 02:35:48 PM PST 24
Peak memory 237596 kb
Host smart-c2c433ed-1d30-4dce-8107-60d74164013a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504083444 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_c
orrupt_sig_fatal_chk.504083444
Directory /workspace/21.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_kmac_err_chk.1384953187
Short name T340
Test name
Test status
Simulation time 417580323 ps
CPU time 12.57 seconds
Started Jan 24 02:31:51 PM PST 24
Finished Jan 24 02:32:33 PM PST 24
Peak memory 211136 kb
Host smart-1bf7e453-28f7-4ecd-a6c8-7b36e9ac3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384953187 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_kmac_err_chk.1384953187
Directory /workspace/21.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_max_throughput_chk.2758687088
Short name T277
Test name
Test status
Simulation time 1824700667 ps
CPU time 15.84 seconds
Started Jan 24 02:31:49 PM PST 24
Finished Jan 24 02:32:33 PM PST 24
Peak memory 210968 kb
Host smart-f50b79d0-be97-4096-b177-766577e9bf77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2758687088 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_max_throughput_chk.2758687088
Directory /workspace/21.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/21.rom_ctrl_smoke.208548642
Short name T391
Test name
Test status
Simulation time 4291300470 ps
CPU time 13.19 seconds
Started Jan 24 02:31:51 PM PST 24
Finished Jan 24 02:32:33 PM PST 24
Peak memory 212976 kb
Host smart-d6c1994d-c847-4152-bef2-864869ce2159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208548642 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_smoke.208548642
Directory /workspace/21.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all.3076797203
Short name T100
Test name
Test status
Simulation time 7600596930 ps
CPU time 16.24 seconds
Started Jan 24 02:31:52 PM PST 24
Finished Jan 24 02:32:38 PM PST 24
Peak memory 211700 kb
Host smart-3b685aff-c4dc-47f0-ad4f-ff07f13cb1ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076797203 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 21.rom_ctrl_stress_all.3076797203
Directory /workspace/21.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.rom_ctrl_stress_all_with_rand_reset.1792842980
Short name T11
Test name
Test status
Simulation time 28513415522 ps
CPU time 2014.66 seconds
Started Jan 24 02:31:50 PM PST 24
Finished Jan 24 03:05:53 PM PST 24
Peak memory 235776 kb
Host smart-32038a80-e1cc-4561-b4f0-feee22dddbca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792842980 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rom_ctrl_stress_all_with_rand_reset.1792842980
Directory /workspace/21.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rom_ctrl_alert_test.2047049401
Short name T216
Test name
Test status
Simulation time 12251010537 ps
CPU time 8.52 seconds
Started Jan 24 02:32:08 PM PST 24
Finished Jan 24 02:32:49 PM PST 24
Peak memory 211164 kb
Host smart-2922f81a-7edf-43f0-972a-c3e4d36d6b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047049401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_alert_test.2047049401
Directory /workspace/22.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.rom_ctrl_corrupt_sig_fatal_chk.3025890048
Short name T52
Test name
Test status
Simulation time 1685087931 ps
CPU time 99.66 seconds
Started Jan 24 02:32:03 PM PST 24
Finished Jan 24 02:34:17 PM PST 24
Peak memory 224316 kb
Host smart-0736f287-0686-4400-9f96-8ad8e75dc5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025890048 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_
corrupt_sig_fatal_chk.3025890048
Directory /workspace/22.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_kmac_err_chk.2851309977
Short name T21
Test name
Test status
Simulation time 721760779 ps
CPU time 9.23 seconds
Started Jan 24 03:38:31 PM PST 24
Finished Jan 24 03:38:41 PM PST 24
Peak memory 211236 kb
Host smart-6d9b6f87-ca95-4fa2-b0ce-785cf03cbf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851309977 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_kmac_err_chk.2851309977
Directory /workspace/22.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_max_throughput_chk.1002649463
Short name T389
Test name
Test status
Simulation time 94472085 ps
CPU time 5.33 seconds
Started Jan 24 02:32:07 PM PST 24
Finished Jan 24 02:32:44 PM PST 24
Peak memory 210984 kb
Host smart-0326db84-c880-4be2-a8a6-a84f0dc544ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1002649463 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_max_throughput_chk.1002649463
Directory /workspace/22.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/22.rom_ctrl_smoke.3146534989
Short name T405
Test name
Test status
Simulation time 5153016213 ps
CPU time 20.49 seconds
Started Jan 24 02:32:05 PM PST 24
Finished Jan 24 02:32:58 PM PST 24
Peak memory 213096 kb
Host smart-976bc360-4644-4443-b970-b36d8323f92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146534989 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rom_ctrl_smoke.3146534989
Directory /workspace/22.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/22.rom_ctrl_stress_all.1787941455
Short name T409
Test name
Test status
Simulation time 7028759351 ps
CPU time 33.97 seconds
Started Jan 24 02:32:08 PM PST 24
Finished Jan 24 02:33:14 PM PST 24
Peak memory 216832 kb
Host smart-18f6099e-8fb1-4dbb-8c69-c195a9977308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787941455 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 22.rom_ctrl_stress_all.1787941455
Directory /workspace/22.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_alert_test.588110093
Short name T286
Test name
Test status
Simulation time 6389006880 ps
CPU time 16.3 seconds
Started Jan 24 02:32:01 PM PST 24
Finished Jan 24 02:32:53 PM PST 24
Peak memory 211060 kb
Host smart-0ebd94fd-e224-4c60-8e43-07a36b94ef25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588110093 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_alert_test.588110093
Directory /workspace/23.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.rom_ctrl_corrupt_sig_fatal_chk.2708366183
Short name T259
Test name
Test status
Simulation time 25629628514 ps
CPU time 294.78 seconds
Started Jan 24 02:32:04 PM PST 24
Finished Jan 24 02:37:32 PM PST 24
Peak memory 232752 kb
Host smart-506b30a8-37b1-4252-a615-897a1df90243
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708366183 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_
corrupt_sig_fatal_chk.2708366183
Directory /workspace/23.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_kmac_err_chk.1243063400
Short name T185
Test name
Test status
Simulation time 594702934 ps
CPU time 11.72 seconds
Started Jan 24 02:32:08 PM PST 24
Finished Jan 24 02:32:52 PM PST 24
Peak memory 211312 kb
Host smart-ba4d7ac2-80c0-4f09-865c-ec71e18d3c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243063400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_kmac_err_chk.1243063400
Directory /workspace/23.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_max_throughput_chk.3387072099
Short name T189
Test name
Test status
Simulation time 370486408 ps
CPU time 5.45 seconds
Started Jan 24 02:32:08 PM PST 24
Finished Jan 24 02:32:45 PM PST 24
Peak memory 211040 kb
Host smart-33d33ab3-1398-4be7-9050-6dd07edae4b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387072099 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_max_throughput_chk.3387072099
Directory /workspace/23.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/23.rom_ctrl_smoke.996279180
Short name T356
Test name
Test status
Simulation time 21912375776 ps
CPU time 37.4 seconds
Started Jan 24 02:32:01 PM PST 24
Finished Jan 24 02:33:12 PM PST 24
Peak memory 213484 kb
Host smart-98684a23-d34f-4df8-aa84-a6fb549617fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996279180 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_smoke.996279180
Directory /workspace/23.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all.2824728967
Short name T300
Test name
Test status
Simulation time 295150391 ps
CPU time 17.13 seconds
Started Jan 24 02:32:05 PM PST 24
Finished Jan 24 02:32:55 PM PST 24
Peak memory 214904 kb
Host smart-e5b048e6-ea07-421c-b1c3-2d23a91c32db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824728967 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 23.rom_ctrl_stress_all.2824728967
Directory /workspace/23.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.rom_ctrl_stress_all_with_rand_reset.886582991
Short name T266
Test name
Test status
Simulation time 25378976798 ps
CPU time 2649.92 seconds
Started Jan 24 02:32:03 PM PST 24
Finished Jan 24 03:16:47 PM PST 24
Peak memory 235756 kb
Host smart-d19a398c-5900-4ee5-9432-026d1dff49ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886582991 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rom_ctrl_stress_all_with_rand_reset.886582991
Directory /workspace/23.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rom_ctrl_alert_test.575719578
Short name T294
Test name
Test status
Simulation time 1463805177 ps
CPU time 13.37 seconds
Started Jan 24 02:32:11 PM PST 24
Finished Jan 24 02:32:54 PM PST 24
Peak memory 211004 kb
Host smart-8140ff11-4025-43b1-b2e2-a80c9c30de3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575719578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_alert_test.575719578
Directory /workspace/24.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.rom_ctrl_corrupt_sig_fatal_chk.762462190
Short name T224
Test name
Test status
Simulation time 7833955516 ps
CPU time 102 seconds
Started Jan 24 02:32:15 PM PST 24
Finished Jan 24 02:34:28 PM PST 24
Peak memory 236984 kb
Host smart-9522675b-0817-49a4-85c8-8fa5ee201167
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762462190 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_c
orrupt_sig_fatal_chk.762462190
Directory /workspace/24.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_kmac_err_chk.784828188
Short name T293
Test name
Test status
Simulation time 2064406488 ps
CPU time 12.87 seconds
Started Jan 24 02:32:17 PM PST 24
Finished Jan 24 02:33:03 PM PST 24
Peak memory 211244 kb
Host smart-4d36f9ff-378d-4549-9202-64f3bfe321fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784828188 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_kmac_err_chk.784828188
Directory /workspace/24.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_max_throughput_chk.2104169875
Short name T236
Test name
Test status
Simulation time 10099363635 ps
CPU time 15.68 seconds
Started Jan 24 02:49:27 PM PST 24
Finished Jan 24 02:49:55 PM PST 24
Peak memory 211132 kb
Host smart-0241f6a3-22eb-430f-9c6c-88075c56c918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104169875 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_max_throughput_chk.2104169875
Directory /workspace/24.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/24.rom_ctrl_smoke.2494242105
Short name T168
Test name
Test status
Simulation time 2611489606 ps
CPU time 26.17 seconds
Started Jan 24 02:32:14 PM PST 24
Finished Jan 24 02:33:11 PM PST 24
Peak memory 212764 kb
Host smart-c5782f6b-d2b7-4592-8dab-fb092c15a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494242105 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_smoke.2494242105
Directory /workspace/24.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all.241480808
Short name T344
Test name
Test status
Simulation time 2969209414 ps
CPU time 32.82 seconds
Started Jan 24 02:32:17 PM PST 24
Finished Jan 24 02:33:23 PM PST 24
Peak memory 213200 kb
Host smart-4268df7e-7cd4-4b86-8a21-f84a2dffd81f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241480808 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 24.rom_ctrl_stress_all.241480808
Directory /workspace/24.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.rom_ctrl_stress_all_with_rand_reset.901307114
Short name T387
Test name
Test status
Simulation time 24183383300 ps
CPU time 1207.12 seconds
Started Jan 24 04:26:45 PM PST 24
Finished Jan 24 04:46:59 PM PST 24
Peak memory 234004 kb
Host smart-613af8d9-4601-4cd7-9c35-98ddf39ed024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901307114 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rom_ctrl_stress_all_with_rand_reset.901307114
Directory /workspace/24.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rom_ctrl_alert_test.275615669
Short name T164
Test name
Test status
Simulation time 85834034 ps
CPU time 4.32 seconds
Started Jan 24 02:32:14 PM PST 24
Finished Jan 24 02:32:50 PM PST 24
Peak memory 210964 kb
Host smart-5f7bd8ec-2ee9-45e0-923f-238ad06cbae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275615669 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_alert_test.275615669
Directory /workspace/25.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.rom_ctrl_corrupt_sig_fatal_chk.39863844
Short name T379
Test name
Test status
Simulation time 4471017934 ps
CPU time 113.85 seconds
Started Jan 24 02:32:14 PM PST 24
Finished Jan 24 02:34:39 PM PST 24
Peak memory 239052 kb
Host smart-13c93191-6a29-4063-ac23-84c86bbddf05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39863844 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_
sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_co
rrupt_sig_fatal_chk.39863844
Directory /workspace/25.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_max_throughput_chk.2724955694
Short name T301
Test name
Test status
Simulation time 5517562090 ps
CPU time 14.37 seconds
Started Jan 24 02:32:12 PM PST 24
Finished Jan 24 02:32:59 PM PST 24
Peak memory 211108 kb
Host smart-8b384302-a60e-4ce4-8961-d733f13e4d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2724955694 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_max_throughput_chk.2724955694
Directory /workspace/25.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/25.rom_ctrl_smoke.1046884644
Short name T235
Test name
Test status
Simulation time 4432885642 ps
CPU time 34.19 seconds
Started Jan 24 02:32:18 PM PST 24
Finished Jan 24 02:33:25 PM PST 24
Peak memory 213096 kb
Host smart-259c21d9-9b92-41b2-9a56-0e5e36cc7156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046884644 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rom_ctrl_smoke.1046884644
Directory /workspace/25.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/25.rom_ctrl_stress_all.1071327385
Short name T171
Test name
Test status
Simulation time 1479185172 ps
CPU time 10.03 seconds
Started Jan 24 02:32:11 PM PST 24
Finished Jan 24 02:32:51 PM PST 24
Peak memory 210868 kb
Host smart-d712a29e-eac6-481f-ae64-f6490d1e1186
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071327385 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 25.rom_ctrl_stress_all.1071327385
Directory /workspace/25.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.rom_ctrl_alert_test.1304992848
Short name T136
Test name
Test status
Simulation time 6550197881 ps
CPU time 8.89 seconds
Started Jan 24 02:54:29 PM PST 24
Finished Jan 24 02:55:01 PM PST 24
Peak memory 211132 kb
Host smart-7da5bdce-6e09-4158-ba82-0444be022e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304992848 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_alert_test.1304992848
Directory /workspace/26.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.rom_ctrl_corrupt_sig_fatal_chk.1864174142
Short name T307
Test name
Test status
Simulation time 19853658528 ps
CPU time 244.55 seconds
Started Jan 24 02:32:24 PM PST 24
Finished Jan 24 02:37:00 PM PST 24
Peak memory 227972 kb
Host smart-23541c16-850c-448a-b0d5-470421fc5314
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864174142 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_
corrupt_sig_fatal_chk.1864174142
Directory /workspace/26.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_kmac_err_chk.2825312221
Short name T190
Test name
Test status
Simulation time 3563234126 ps
CPU time 29.04 seconds
Started Jan 24 02:32:22 PM PST 24
Finished Jan 24 02:33:25 PM PST 24
Peak memory 211612 kb
Host smart-1e10c5f3-6fde-4d6c-a790-9e5e9d9ffd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825312221 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_kmac_err_chk.2825312221
Directory /workspace/26.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_max_throughput_chk.1999602766
Short name T380
Test name
Test status
Simulation time 1326607134 ps
CPU time 12.79 seconds
Started Jan 24 04:17:59 PM PST 24
Finished Jan 24 04:18:15 PM PST 24
Peak memory 211020 kb
Host smart-760d2e3a-99fa-4cb3-9273-d70fd3424121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1999602766 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_max_throughput_chk.1999602766
Directory /workspace/26.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/26.rom_ctrl_smoke.3986574327
Short name T352
Test name
Test status
Simulation time 5831714339 ps
CPU time 19.71 seconds
Started Jan 24 02:32:22 PM PST 24
Finished Jan 24 02:33:15 PM PST 24
Peak memory 213048 kb
Host smart-e6a9c054-ea43-477a-9cf9-bc244a0818bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986574327 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rom_ctrl_smoke.3986574327
Directory /workspace/26.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/26.rom_ctrl_stress_all.2607389432
Short name T382
Test name
Test status
Simulation time 549362580 ps
CPU time 10.53 seconds
Started Jan 24 02:32:24 PM PST 24
Finished Jan 24 02:33:06 PM PST 24
Peak memory 210852 kb
Host smart-ca3053a9-c4aa-451b-88c5-89330d3832d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607389432 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 26.rom_ctrl_stress_all.2607389432
Directory /workspace/26.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_alert_test.570922916
Short name T1
Test name
Test status
Simulation time 3019038075 ps
CPU time 13.41 seconds
Started Jan 24 02:32:34 PM PST 24
Finished Jan 24 02:33:20 PM PST 24
Peak memory 211128 kb
Host smart-bd110f13-8ae8-4bcb-b3ef-c3d202f3ccf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570922916 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_alert_test.570922916
Directory /workspace/27.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.rom_ctrl_corrupt_sig_fatal_chk.696304401
Short name T193
Test name
Test status
Simulation time 41023023756 ps
CPU time 420.87 seconds
Started Jan 24 03:03:10 PM PST 24
Finished Jan 24 03:10:45 PM PST 24
Peak memory 237640 kb
Host smart-51df55d5-c7c9-453e-a487-3c2f23215aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696304401 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_c
orrupt_sig_fatal_chk.696304401
Directory /workspace/27.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_kmac_err_chk.780799209
Short name T7
Test name
Test status
Simulation time 4480677036 ps
CPU time 15.93 seconds
Started Jan 24 02:32:21 PM PST 24
Finished Jan 24 02:33:10 PM PST 24
Peak memory 211728 kb
Host smart-8b908092-358e-4c8e-ab85-c7f92257866e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780799209 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_kmac_err_chk.780799209
Directory /workspace/27.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_max_throughput_chk.1535089333
Short name T150
Test name
Test status
Simulation time 101351232 ps
CPU time 5.57 seconds
Started Jan 24 02:32:23 PM PST 24
Finished Jan 24 02:33:01 PM PST 24
Peak memory 210972 kb
Host smart-e2223218-523d-4777-aa36-466f7b5d4f5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535089333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_max_throughput_chk.1535089333
Directory /workspace/27.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/27.rom_ctrl_smoke.2068504503
Short name T209
Test name
Test status
Simulation time 1974841920 ps
CPU time 21.5 seconds
Started Jan 24 02:32:23 PM PST 24
Finished Jan 24 02:33:17 PM PST 24
Peak memory 212760 kb
Host smart-1b879b99-338e-4fe8-8f0c-9c25b28fcadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068504503 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_smoke.2068504503
Directory /workspace/27.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all.1430386857
Short name T305
Test name
Test status
Simulation time 52194029821 ps
CPU time 161.67 seconds
Started Jan 24 02:32:22 PM PST 24
Finished Jan 24 02:35:37 PM PST 24
Peak memory 219272 kb
Host smart-191f50fc-75e3-41d9-b3a7-9ea003c760d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430386857 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.rom_ctrl_stress_all.1430386857
Directory /workspace/27.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.rom_ctrl_stress_all_with_rand_reset.1290265150
Short name T363
Test name
Test status
Simulation time 17303832768 ps
CPU time 1334.24 seconds
Started Jan 24 04:00:35 PM PST 24
Finished Jan 24 04:22:51 PM PST 24
Peak memory 232220 kb
Host smart-cf5abec8-8b7e-4950-b17f-f7a4fcdaf1c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290265150 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rom_ctrl_stress_all_with_rand_reset.1290265150
Directory /workspace/27.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rom_ctrl_alert_test.1118989497
Short name T159
Test name
Test status
Simulation time 212887690 ps
CPU time 5.84 seconds
Started Jan 24 02:32:47 PM PST 24
Finished Jan 24 02:33:32 PM PST 24
Peak memory 210944 kb
Host smart-89a4e083-9e5b-4bb2-b300-61c4b3346f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118989497 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_alert_test.1118989497
Directory /workspace/28.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.rom_ctrl_corrupt_sig_fatal_chk.3602689418
Short name T386
Test name
Test status
Simulation time 18003449397 ps
CPU time 186.47 seconds
Started Jan 24 02:32:37 PM PST 24
Finished Jan 24 02:36:14 PM PST 24
Peak memory 236668 kb
Host smart-bfc0ec07-71c9-42e8-8b89-bf56fb7ec8c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602689418 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_
corrupt_sig_fatal_chk.3602689418
Directory /workspace/28.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_kmac_err_chk.461442069
Short name T338
Test name
Test status
Simulation time 2639115653 ps
CPU time 18.16 seconds
Started Jan 24 04:34:21 PM PST 24
Finished Jan 24 04:34:43 PM PST 24
Peak memory 211432 kb
Host smart-ecb843b7-6272-4a9b-b8f0-ce48b48ca792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461442069 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_kmac_err_chk.461442069
Directory /workspace/28.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_max_throughput_chk.3629605076
Short name T362
Test name
Test status
Simulation time 7067768291 ps
CPU time 10.34 seconds
Started Jan 24 02:32:41 PM PST 24
Finished Jan 24 02:33:33 PM PST 24
Peak memory 211072 kb
Host smart-b6bce145-f124-4423-9f94-ba7c4bb6e295
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629605076 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_max_throughput_chk.3629605076
Directory /workspace/28.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/28.rom_ctrl_smoke.1277639903
Short name T407
Test name
Test status
Simulation time 12404009376 ps
CPU time 34.43 seconds
Started Jan 24 02:32:37 PM PST 24
Finished Jan 24 02:33:42 PM PST 24
Peak memory 213420 kb
Host smart-958e24d8-ddad-4af9-b07f-9955643acd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277639903 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_smoke.1277639903
Directory /workspace/28.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all.3311002699
Short name T396
Test name
Test status
Simulation time 482642735 ps
CPU time 26.08 seconds
Started Jan 24 02:46:49 PM PST 24
Finished Jan 24 02:47:23 PM PST 24
Peak memory 214920 kb
Host smart-c003c056-fdba-4714-846f-49e4ac8a7e65
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311002699 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.rom_ctrl_stress_all.3311002699
Directory /workspace/28.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.rom_ctrl_stress_all_with_rand_reset.2943654175
Short name T227
Test name
Test status
Simulation time 27027213956 ps
CPU time 2197.42 seconds
Started Jan 24 02:32:43 PM PST 24
Finished Jan 24 03:10:01 PM PST 24
Peak memory 235500 kb
Host smart-db9171c6-6296-47bb-b561-297f63a0a4c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943654175 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rom_ctrl_stress_all_with_rand_reset.2943654175
Directory /workspace/28.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rom_ctrl_alert_test.2128864686
Short name T322
Test name
Test status
Simulation time 1547208099 ps
CPU time 13.74 seconds
Started Jan 24 02:32:43 PM PST 24
Finished Jan 24 02:33:37 PM PST 24
Peak memory 211024 kb
Host smart-b87ad7d9-c1a3-4ff6-b3bc-608017961a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128864686 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_alert_test.2128864686
Directory /workspace/29.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.rom_ctrl_corrupt_sig_fatal_chk.2513535894
Short name T385
Test name
Test status
Simulation time 4862540107 ps
CPU time 180.91 seconds
Started Jan 24 04:22:17 PM PST 24
Finished Jan 24 04:25:19 PM PST 24
Peak memory 232860 kb
Host smart-a98e8c32-004c-408e-81b8-a0cad6953c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513535894 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_
corrupt_sig_fatal_chk.2513535894
Directory /workspace/29.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_kmac_err_chk.893320970
Short name T213
Test name
Test status
Simulation time 20467852634 ps
CPU time 30.75 seconds
Started Jan 24 04:41:20 PM PST 24
Finished Jan 24 04:41:54 PM PST 24
Peak memory 211640 kb
Host smart-c2c80152-96ae-499d-9dca-284c55761243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893320970 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_kmac_err_chk.893320970
Directory /workspace/29.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_max_throughput_chk.1699359449
Short name T181
Test name
Test status
Simulation time 609349295 ps
CPU time 7.67 seconds
Started Jan 24 02:46:55 PM PST 24
Finished Jan 24 02:47:21 PM PST 24
Peak memory 210980 kb
Host smart-d857c31a-7ca6-4b51-89e2-9684f307bf3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699359449 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_max_throughput_chk.1699359449
Directory /workspace/29.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/29.rom_ctrl_smoke.4154770830
Short name T234
Test name
Test status
Simulation time 180935629 ps
CPU time 10.27 seconds
Started Jan 24 03:59:23 PM PST 24
Finished Jan 24 03:59:34 PM PST 24
Peak memory 212300 kb
Host smart-cc71d963-6851-4264-a67b-7f6c7351242b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154770830 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_smoke.4154770830
Directory /workspace/29.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all.1627755611
Short name T265
Test name
Test status
Simulation time 36810899164 ps
CPU time 81.17 seconds
Started Jan 24 02:58:10 PM PST 24
Finished Jan 24 02:59:40 PM PST 24
Peak memory 215020 kb
Host smart-c337d7b1-8e90-41e2-a586-a72119abc1f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627755611 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.rom_ctrl_stress_all.1627755611
Directory /workspace/29.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.rom_ctrl_stress_all_with_rand_reset.1312029739
Short name T239
Test name
Test status
Simulation time 133283964364 ps
CPU time 1445.07 seconds
Started Jan 24 02:32:45 PM PST 24
Finished Jan 24 02:57:30 PM PST 24
Peak memory 231448 kb
Host smart-e80b2492-ec85-4471-983a-4ffb2359a20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312029739 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rom_ctrl_stress_all_with_rand_reset.1312029739
Directory /workspace/29.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rom_ctrl_alert_test.2017671320
Short name T135
Test name
Test status
Simulation time 461109115 ps
CPU time 4.18 seconds
Started Jan 24 02:30:23 PM PST 24
Finished Jan 24 02:30:39 PM PST 24
Peak memory 210860 kb
Host smart-d052c511-3077-4d91-9077-ed777ddf6d82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017671320 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_alert_test.2017671320
Directory /workspace/3.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1364608025
Short name T228
Test name
Test status
Simulation time 27085871833 ps
CPU time 288.76 seconds
Started Jan 24 02:30:22 PM PST 24
Finished Jan 24 02:35:23 PM PST 24
Peak memory 236812 kb
Host smart-3b46613c-1a9d-4c09-9344-3037c1a3ed3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364608025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_c
orrupt_sig_fatal_chk.1364608025
Directory /workspace/3.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_kmac_err_chk.2351215648
Short name T393
Test name
Test status
Simulation time 12483329589 ps
CPU time 25.6 seconds
Started Jan 24 02:30:22 PM PST 24
Finished Jan 24 02:30:59 PM PST 24
Peak memory 211672 kb
Host smart-c4f442d9-3d97-4316-8be5-0e7ee5a2d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351215648 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_kmac_err_chk.2351215648
Directory /workspace/3.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_max_throughput_chk.2224321422
Short name T249
Test name
Test status
Simulation time 375803174 ps
CPU time 5.39 seconds
Started Jan 24 02:30:11 PM PST 24
Finished Jan 24 02:30:32 PM PST 24
Peak memory 210960 kb
Host smart-f0739f4a-3cd1-4c2e-8acf-dc93038d0378
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224321422 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_max_throughput_chk.2224321422
Directory /workspace/3.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/3.rom_ctrl_sec_cm.2786477740
Short name T51
Test name
Test status
Simulation time 886131540 ps
CPU time 57.7 seconds
Started Jan 24 02:30:24 PM PST 24
Finished Jan 24 02:31:34 PM PST 24
Peak memory 233512 kb
Host smart-a800315d-0b8a-4a4b-a035-3872dcbe3d60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786477740 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_sec_cm.2786477740
Directory /workspace/3.rom_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.rom_ctrl_smoke.3473213397
Short name T410
Test name
Test status
Simulation time 193330552 ps
CPU time 10.38 seconds
Started Jan 24 02:30:12 PM PST 24
Finished Jan 24 02:30:38 PM PST 24
Peak memory 212620 kb
Host smart-e1edac48-bbcc-4959-88c0-529d6671c14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473213397 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rom_ctrl_smoke.3473213397
Directory /workspace/3.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/3.rom_ctrl_stress_all.416641462
Short name T201
Test name
Test status
Simulation time 1490437522 ps
CPU time 12.86 seconds
Started Jan 24 02:30:16 PM PST 24
Finished Jan 24 02:30:43 PM PST 24
Peak memory 214512 kb
Host smart-49499883-7846-4185-a84b-40113e3df5fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416641462 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.rom_ctrl_stress_all.416641462
Directory /workspace/3.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_alert_test.3764287446
Short name T134
Test name
Test status
Simulation time 2475546245 ps
CPU time 11.21 seconds
Started Jan 24 02:32:44 PM PST 24
Finished Jan 24 02:33:35 PM PST 24
Peak memory 211168 kb
Host smart-e179ee5d-62be-45bb-88bb-9bbbedf712b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764287446 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_alert_test.3764287446
Directory /workspace/30.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.rom_ctrl_corrupt_sig_fatal_chk.3872438732
Short name T198
Test name
Test status
Simulation time 105275511377 ps
CPU time 292.68 seconds
Started Jan 24 02:32:44 PM PST 24
Finished Jan 24 02:38:16 PM PST 24
Peak memory 236552 kb
Host smart-fa8dfd9f-b322-483f-b168-5744d91ec958
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872438732 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_
corrupt_sig_fatal_chk.3872438732
Directory /workspace/30.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_kmac_err_chk.1494164961
Short name T146
Test name
Test status
Simulation time 7866603102 ps
CPU time 31.41 seconds
Started Jan 24 02:32:46 PM PST 24
Finished Jan 24 02:33:57 PM PST 24
Peak memory 211100 kb
Host smart-272f7828-469c-4c69-88fb-8906f3b07ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494164961 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_kmac_err_chk.1494164961
Directory /workspace/30.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_max_throughput_chk.3970799933
Short name T411
Test name
Test status
Simulation time 1608674382 ps
CPU time 14.9 seconds
Started Jan 24 02:32:45 PM PST 24
Finished Jan 24 02:33:40 PM PST 24
Peak memory 210980 kb
Host smart-41275ebd-39b2-4dd2-85b7-f8ad1a9f2789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3970799933 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_max_throughput_chk.3970799933
Directory /workspace/30.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/30.rom_ctrl_smoke.3659548972
Short name T192
Test name
Test status
Simulation time 12053236726 ps
CPU time 33.77 seconds
Started Jan 24 02:32:45 PM PST 24
Finished Jan 24 02:33:59 PM PST 24
Peak memory 213816 kb
Host smart-79395014-ef53-4d49-8412-95db26445a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659548972 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_smoke.3659548972
Directory /workspace/30.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all.1375908284
Short name T222
Test name
Test status
Simulation time 5580386524 ps
CPU time 32.84 seconds
Started Jan 24 02:32:45 PM PST 24
Finished Jan 24 02:33:58 PM PST 24
Peak memory 215528 kb
Host smart-b406a9d1-972c-4c03-bf77-380a238075d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375908284 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.rom_ctrl_stress_all.1375908284
Directory /workspace/30.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.rom_ctrl_stress_all_with_rand_reset.1706710458
Short name T297
Test name
Test status
Simulation time 14940768299 ps
CPU time 3787.23 seconds
Started Jan 24 02:32:42 PM PST 24
Finished Jan 24 03:36:31 PM PST 24
Peak memory 234172 kb
Host smart-d991e1d0-298a-4f0f-b16d-7f1adec634e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706710458 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rom_ctrl_stress_all_with_rand_reset.1706710458
Directory /workspace/30.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rom_ctrl_alert_test.1383653248
Short name T281
Test name
Test status
Simulation time 1384002637 ps
CPU time 12.15 seconds
Started Jan 24 03:03:41 PM PST 24
Finished Jan 24 03:04:16 PM PST 24
Peak memory 211024 kb
Host smart-a2bb238f-e932-4cfe-a32b-57bcc4c63708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383653248 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_alert_test.1383653248
Directory /workspace/31.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.rom_ctrl_corrupt_sig_fatal_chk.2020789297
Short name T342
Test name
Test status
Simulation time 34340781341 ps
CPU time 323.97 seconds
Started Jan 24 02:49:34 PM PST 24
Finished Jan 24 02:55:14 PM PST 24
Peak memory 236612 kb
Host smart-eed90567-8e2b-4f78-89ed-0bd3c2393e14
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020789297 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_
corrupt_sig_fatal_chk.2020789297
Directory /workspace/31.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_kmac_err_chk.1281137417
Short name T357
Test name
Test status
Simulation time 2362932721 ps
CPU time 23.46 seconds
Started Jan 24 02:32:50 PM PST 24
Finished Jan 24 02:33:50 PM PST 24
Peak memory 211204 kb
Host smart-a0f7330f-d289-4283-9f75-be55a703f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281137417 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_kmac_err_chk.1281137417
Directory /workspace/31.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_max_throughput_chk.2216467832
Short name T312
Test name
Test status
Simulation time 191814470 ps
CPU time 5.44 seconds
Started Jan 24 02:57:15 PM PST 24
Finished Jan 24 02:57:36 PM PST 24
Peak memory 211024 kb
Host smart-fc14b786-0a65-47c0-8f0f-1f6e6907db0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2216467832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_max_throughput_chk.2216467832
Directory /workspace/31.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/31.rom_ctrl_smoke.1324849572
Short name T257
Test name
Test status
Simulation time 36382443859 ps
CPU time 30.53 seconds
Started Jan 24 02:32:44 PM PST 24
Finished Jan 24 02:33:54 PM PST 24
Peak memory 213616 kb
Host smart-0c54c13c-4e61-48f7-9b45-0577ed9a3fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324849572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_smoke.1324849572
Directory /workspace/31.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all.3595369931
Short name T402
Test name
Test status
Simulation time 12899995503 ps
CPU time 53.77 seconds
Started Jan 24 02:32:58 PM PST 24
Finished Jan 24 02:34:28 PM PST 24
Peak memory 215916 kb
Host smart-127164ba-92a0-40b7-b7a7-427ac3585fbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595369931 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 31.rom_ctrl_stress_all.3595369931
Directory /workspace/31.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.rom_ctrl_stress_all_with_rand_reset.2311746012
Short name T260
Test name
Test status
Simulation time 40678403737 ps
CPU time 873.17 seconds
Started Jan 24 02:33:05 PM PST 24
Finished Jan 24 02:48:12 PM PST 24
Peak memory 227528 kb
Host smart-481f4cfd-5768-43d2-bbc8-07f024b370a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311746012 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rom_ctrl_stress_all_with_rand_reset.2311746012
Directory /workspace/31.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rom_ctrl_alert_test.2305063760
Short name T196
Test name
Test status
Simulation time 1773217300 ps
CPU time 14.15 seconds
Started Jan 24 02:33:16 PM PST 24
Finished Jan 24 02:33:56 PM PST 24
Peak memory 210936 kb
Host smart-1c5dfe0c-7dc7-4514-b0d2-7551947f192b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305063760 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_alert_test.2305063760
Directory /workspace/32.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.rom_ctrl_corrupt_sig_fatal_chk.3329756941
Short name T378
Test name
Test status
Simulation time 99087927116 ps
CPU time 207.91 seconds
Started Jan 24 02:45:30 PM PST 24
Finished Jan 24 02:49:13 PM PST 24
Peak memory 228404 kb
Host smart-65918a30-6401-4e5f-a8ac-235d68f5a0dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329756941 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_
corrupt_sig_fatal_chk.3329756941
Directory /workspace/32.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_kmac_err_chk.3665937313
Short name T140
Test name
Test status
Simulation time 12143911828 ps
CPU time 31.87 seconds
Started Jan 24 02:33:12 PM PST 24
Finished Jan 24 02:34:14 PM PST 24
Peak memory 211632 kb
Host smart-c86e867f-3dc2-4724-a840-896033dc1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665937313 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_kmac_err_chk.3665937313
Directory /workspace/32.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_max_throughput_chk.423340966
Short name T276
Test name
Test status
Simulation time 98114637 ps
CPU time 5.79 seconds
Started Jan 24 02:59:55 PM PST 24
Finished Jan 24 03:00:21 PM PST 24
Peak memory 211024 kb
Host smart-3e74104b-4b53-4f7d-9d90-c86796ff75b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=423340966 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_max_throughput_chk.423340966
Directory /workspace/32.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/32.rom_ctrl_smoke.33806412
Short name T267
Test name
Test status
Simulation time 3871733845 ps
CPU time 37.43 seconds
Started Jan 24 02:51:16 PM PST 24
Finished Jan 24 02:52:03 PM PST 24
Peak memory 212804 kb
Host smart-add1320c-767a-47f6-bd85-971fb0ae6635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33806412 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rom_ctrl_smoke.33806412
Directory /workspace/32.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/32.rom_ctrl_stress_all.3527581208
Short name T230
Test name
Test status
Simulation time 55432381141 ps
CPU time 122.71 seconds
Started Jan 24 02:35:42 PM PST 24
Finished Jan 24 02:37:59 PM PST 24
Peak memory 219284 kb
Host smart-77fa6048-169e-4196-b6cf-bde390a5ebad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527581208 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 32.rom_ctrl_stress_all.3527581208
Directory /workspace/32.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.rom_ctrl_alert_test.1138972578
Short name T217
Test name
Test status
Simulation time 801698541 ps
CPU time 8.83 seconds
Started Jan 24 02:33:22 PM PST 24
Finished Jan 24 02:33:54 PM PST 24
Peak memory 210968 kb
Host smart-abf5a49a-7b9d-4d62-bb0e-852b2fc1bd88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138972578 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_alert_test.1138972578
Directory /workspace/33.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.rom_ctrl_corrupt_sig_fatal_chk.2510016676
Short name T270
Test name
Test status
Simulation time 3846494872 ps
CPU time 119.59 seconds
Started Jan 24 02:33:24 PM PST 24
Finished Jan 24 02:35:46 PM PST 24
Peak memory 238380 kb
Host smart-146e65c6-41bd-4e54-bdd2-cca2f805431f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510016676 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_
corrupt_sig_fatal_chk.2510016676
Directory /workspace/33.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_kmac_err_chk.2399630869
Short name T280
Test name
Test status
Simulation time 185192797 ps
CPU time 9.38 seconds
Started Jan 24 02:33:21 PM PST 24
Finished Jan 24 02:33:54 PM PST 24
Peak memory 211236 kb
Host smart-c66d737d-0407-418a-b3dd-46ebb26474a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399630869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_kmac_err_chk.2399630869
Directory /workspace/33.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_max_throughput_chk.469112754
Short name T176
Test name
Test status
Simulation time 14913048531 ps
CPU time 17.33 seconds
Started Jan 24 02:33:24 PM PST 24
Finished Jan 24 02:34:04 PM PST 24
Peak memory 210764 kb
Host smart-b235e2cd-aaef-480d-b9d3-8b26d96c8a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469112754 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_max_throughput_chk.469112754
Directory /workspace/33.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/33.rom_ctrl_smoke.751021316
Short name T330
Test name
Test status
Simulation time 10089238480 ps
CPU time 23.1 seconds
Started Jan 24 02:33:13 PM PST 24
Finished Jan 24 02:34:05 PM PST 24
Peak memory 212608 kb
Host smart-06c96dec-d59d-4054-9113-60399a661fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751021316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rom_ctrl_smoke.751021316
Directory /workspace/33.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/33.rom_ctrl_stress_all.2039059576
Short name T334
Test name
Test status
Simulation time 8787099897 ps
CPU time 87.11 seconds
Started Jan 24 02:33:26 PM PST 24
Finished Jan 24 02:35:14 PM PST 24
Peak memory 215848 kb
Host smart-3b23c7d9-48d7-411c-9355-a80750d0c472
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039059576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 33.rom_ctrl_stress_all.2039059576
Directory /workspace/33.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.rom_ctrl_alert_test.4251498621
Short name T345
Test name
Test status
Simulation time 385910007 ps
CPU time 7.03 seconds
Started Jan 24 02:33:46 PM PST 24
Finished Jan 24 02:34:06 PM PST 24
Peak memory 211012 kb
Host smart-500a4361-b602-4a79-8765-6b7cd65f489b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251498621 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_alert_test.4251498621
Directory /workspace/34.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.rom_ctrl_corrupt_sig_fatal_chk.557641600
Short name T27
Test name
Test status
Simulation time 2433011311 ps
CPU time 156.44 seconds
Started Jan 24 02:33:41 PM PST 24
Finished Jan 24 02:36:33 PM PST 24
Peak memory 240696 kb
Host smart-09932f95-deb3-44f5-8771-b3ab06704a84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557641600 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_c
orrupt_sig_fatal_chk.557641600
Directory /workspace/34.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_kmac_err_chk.2696531004
Short name T323
Test name
Test status
Simulation time 17579476631 ps
CPU time 31.86 seconds
Started Jan 24 02:33:47 PM PST 24
Finished Jan 24 02:34:32 PM PST 24
Peak memory 211532 kb
Host smart-71cf5806-5ccb-4d75-98b7-87397a561a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696531004 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_kmac_err_chk.2696531004
Directory /workspace/34.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_max_throughput_chk.1271404486
Short name T367
Test name
Test status
Simulation time 7860360704 ps
CPU time 16.08 seconds
Started Jan 24 02:33:26 PM PST 24
Finished Jan 24 02:34:03 PM PST 24
Peak memory 211060 kb
Host smart-2d9d1b24-3117-415b-8de1-30e9d9a02251
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271404486 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_max_throughput_chk.1271404486
Directory /workspace/34.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/34.rom_ctrl_smoke.3128624266
Short name T195
Test name
Test status
Simulation time 4121440982 ps
CPU time 43.96 seconds
Started Jan 24 02:33:24 PM PST 24
Finished Jan 24 02:34:30 PM PST 24
Peak memory 212596 kb
Host smart-1834801a-593d-4abd-aa6c-08589275866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128624266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_smoke.3128624266
Directory /workspace/34.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/34.rom_ctrl_stress_all_with_rand_reset.4097780742
Short name T349
Test name
Test status
Simulation time 62582267805 ps
CPU time 2457.88 seconds
Started Jan 24 02:33:47 PM PST 24
Finished Jan 24 03:14:59 PM PST 24
Peak memory 243948 kb
Host smart-b7ed8156-fb4c-4466-a5bb-d4eeead4540c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097780742 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rom_ctrl_stress_all_with_rand_reset.4097780742
Directory /workspace/34.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rom_ctrl_alert_test.2599178078
Short name T347
Test name
Test status
Simulation time 1336929111 ps
CPU time 11.81 seconds
Started Jan 24 02:33:45 PM PST 24
Finished Jan 24 02:34:10 PM PST 24
Peak memory 210980 kb
Host smart-b5b7397f-bd6a-41c3-9b5e-d9cd75797ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599178078 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_alert_test.2599178078
Directory /workspace/35.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.rom_ctrl_corrupt_sig_fatal_chk.2199102688
Short name T392
Test name
Test status
Simulation time 9789637166 ps
CPU time 138.86 seconds
Started Jan 24 02:33:48 PM PST 24
Finished Jan 24 02:36:20 PM PST 24
Peak memory 236584 kb
Host smart-f473b561-8079-443e-b8ce-d0d78c91b66c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199102688 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_
corrupt_sig_fatal_chk.2199102688
Directory /workspace/35.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_kmac_err_chk.674915869
Short name T371
Test name
Test status
Simulation time 2358226673 ps
CPU time 23.35 seconds
Started Jan 24 02:49:27 PM PST 24
Finished Jan 24 02:50:03 PM PST 24
Peak memory 211344 kb
Host smart-3bac4fd3-4229-476b-a794-debc8e6777d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674915869 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_kmac_err_chk.674915869
Directory /workspace/35.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/35.rom_ctrl_smoke.920326281
Short name T248
Test name
Test status
Simulation time 2508431614 ps
CPU time 27.41 seconds
Started Jan 24 02:33:49 PM PST 24
Finished Jan 24 02:34:29 PM PST 24
Peak memory 211500 kb
Host smart-61ead547-eaea-4981-9554-42c6710682dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920326281 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_smoke.920326281
Directory /workspace/35.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all.1398571367
Short name T142
Test name
Test status
Simulation time 3226612679 ps
CPU time 23.99 seconds
Started Jan 24 02:33:39 PM PST 24
Finished Jan 24 02:34:18 PM PST 24
Peak memory 213392 kb
Host smart-f36a76a7-6ea9-4e1c-84fa-b450dedf3361
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398571367 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 35.rom_ctrl_stress_all.1398571367
Directory /workspace/35.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.rom_ctrl_stress_all_with_rand_reset.539093251
Short name T296
Test name
Test status
Simulation time 22933934986 ps
CPU time 8088.7 seconds
Started Jan 24 02:33:51 PM PST 24
Finished Jan 24 04:48:55 PM PST 24
Peak memory 232828 kb
Host smart-2e4d46a4-d733-4a1e-9bae-dcac2a905f67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539093251 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rom_ctrl_stress_all_with_rand_reset.539093251
Directory /workspace/35.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rom_ctrl_alert_test.952294864
Short name T332
Test name
Test status
Simulation time 362335937 ps
CPU time 4.35 seconds
Started Jan 24 02:33:46 PM PST 24
Finished Jan 24 02:34:03 PM PST 24
Peak memory 211016 kb
Host smart-cb0d9290-fddc-46c6-94ba-1ba4be828271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952294864 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_alert_test.952294864
Directory /workspace/36.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.rom_ctrl_corrupt_sig_fatal_chk.946747009
Short name T199
Test name
Test status
Simulation time 50661867839 ps
CPU time 253.91 seconds
Started Jan 24 03:16:09 PM PST 24
Finished Jan 24 03:20:31 PM PST 24
Peak memory 227896 kb
Host smart-14096aa3-319f-4197-8ac5-5b2f10397eba
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946747009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_c
orrupt_sig_fatal_chk.946747009
Directory /workspace/36.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_kmac_err_chk.2480937434
Short name T404
Test name
Test status
Simulation time 793785716 ps
CPU time 12.31 seconds
Started Jan 24 02:33:49 PM PST 24
Finished Jan 24 02:34:14 PM PST 24
Peak memory 210948 kb
Host smart-4470b521-bd3d-4f98-beb2-3549af5c282c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480937434 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_kmac_err_chk.2480937434
Directory /workspace/36.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_max_throughput_chk.3437622962
Short name T19
Test name
Test status
Simulation time 198059518 ps
CPU time 5.78 seconds
Started Jan 24 02:33:49 PM PST 24
Finished Jan 24 02:34:08 PM PST 24
Peak memory 211012 kb
Host smart-79b85ee6-5ce7-4426-84d5-a7093cfddf5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437622962 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_max_throughput_chk.3437622962
Directory /workspace/36.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/36.rom_ctrl_smoke.2005602657
Short name T243
Test name
Test status
Simulation time 184908926 ps
CPU time 10.57 seconds
Started Jan 24 03:50:22 PM PST 24
Finished Jan 24 03:50:35 PM PST 24
Peak memory 212776 kb
Host smart-e924b6fd-8dc5-4874-9c98-2e94b2cfcea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005602657 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rom_ctrl_smoke.2005602657
Directory /workspace/36.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/36.rom_ctrl_stress_all.1915077789
Short name T165
Test name
Test status
Simulation time 1251214022 ps
CPU time 17.22 seconds
Started Jan 24 02:33:51 PM PST 24
Finished Jan 24 02:34:24 PM PST 24
Peak memory 213320 kb
Host smart-6107cec2-30b4-4c3f-9421-269a7f7bcebf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915077789 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 36.rom_ctrl_stress_all.1915077789
Directory /workspace/36.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_alert_test.4245599601
Short name T263
Test name
Test status
Simulation time 552871522 ps
CPU time 4.18 seconds
Started Jan 24 02:34:01 PM PST 24
Finished Jan 24 02:34:22 PM PST 24
Peak memory 210944 kb
Host smart-9b09beab-4e78-4fb8-91dc-caad66225d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245599601 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_alert_test.4245599601
Directory /workspace/37.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.rom_ctrl_corrupt_sig_fatal_chk.415547333
Short name T251
Test name
Test status
Simulation time 52580767488 ps
CPU time 152.27 seconds
Started Jan 24 02:33:50 PM PST 24
Finished Jan 24 02:36:37 PM PST 24
Peak memory 212268 kb
Host smart-3f4bc73b-05c8-4084-9db6-877377844d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415547333 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_c
orrupt_sig_fatal_chk.415547333
Directory /workspace/37.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_kmac_err_chk.3802279508
Short name T336
Test name
Test status
Simulation time 12646209762 ps
CPU time 27.99 seconds
Started Jan 24 02:37:46 PM PST 24
Finished Jan 24 02:38:36 PM PST 24
Peak memory 211600 kb
Host smart-42a04012-3b9d-40d8-b8cb-a5e7ffded340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802279508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_kmac_err_chk.3802279508
Directory /workspace/37.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_max_throughput_chk.2134801197
Short name T24
Test name
Test status
Simulation time 1022370998 ps
CPU time 7.26 seconds
Started Jan 24 04:48:52 PM PST 24
Finished Jan 24 04:49:01 PM PST 24
Peak memory 211008 kb
Host smart-58c0609b-f984-4e5f-a42b-ad650f8d9fd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134801197 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_max_throughput_chk.2134801197
Directory /workspace/37.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/37.rom_ctrl_smoke.367330629
Short name T161
Test name
Test status
Simulation time 36365817656 ps
CPU time 25.11 seconds
Started Jan 24 02:33:47 PM PST 24
Finished Jan 24 02:34:26 PM PST 24
Peak memory 213648 kb
Host smart-299c77c0-e23b-4aa6-8845-59b65db00609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367330629 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_smoke.367330629
Directory /workspace/37.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all.603382660
Short name T91
Test name
Test status
Simulation time 2717331326 ps
CPU time 11.55 seconds
Started Jan 24 02:45:46 PM PST 24
Finished Jan 24 02:46:03 PM PST 24
Peak memory 211892 kb
Host smart-2ca0c65e-605e-48ae-9bc9-40e389d4247f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603382660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.rom_ctrl_stress_all.603382660
Directory /workspace/37.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.rom_ctrl_stress_all_with_rand_reset.1609549855
Short name T394
Test name
Test status
Simulation time 200034695480 ps
CPU time 9548.58 seconds
Started Jan 24 03:39:34 PM PST 24
Finished Jan 24 06:18:47 PM PST 24
Peak memory 235756 kb
Host smart-f5f89934-9bec-4238-9c35-f173d5c51b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609549855 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rom_ctrl_stress_all_with_rand_reset.1609549855
Directory /workspace/37.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rom_ctrl_alert_test.1383850491
Short name T203
Test name
Test status
Simulation time 17111402290 ps
CPU time 10.03 seconds
Started Jan 24 02:33:59 PM PST 24
Finished Jan 24 02:34:27 PM PST 24
Peak memory 211124 kb
Host smart-fc39f000-3e96-4d77-a685-8fd887eb0515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383850491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_alert_test.1383850491
Directory /workspace/38.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.rom_ctrl_corrupt_sig_fatal_chk.2592179266
Short name T370
Test name
Test status
Simulation time 178113690525 ps
CPU time 394.99 seconds
Started Jan 24 02:34:03 PM PST 24
Finished Jan 24 02:40:53 PM PST 24
Peak memory 225480 kb
Host smart-c26ecd95-c486-42b3-ac62-d0d41a096668
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592179266 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_
corrupt_sig_fatal_chk.2592179266
Directory /workspace/38.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_kmac_err_chk.1973873121
Short name T20
Test name
Test status
Simulation time 30165355933 ps
CPU time 33.3 seconds
Started Jan 24 02:33:57 PM PST 24
Finished Jan 24 02:34:50 PM PST 24
Peak memory 211576 kb
Host smart-bca35e4b-0f41-4702-95fd-3b86f7d25868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973873121 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_kmac_err_chk.1973873121
Directory /workspace/38.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_max_throughput_chk.3630850199
Short name T145
Test name
Test status
Simulation time 16382013078 ps
CPU time 17.74 seconds
Started Jan 24 02:51:16 PM PST 24
Finished Jan 24 02:51:44 PM PST 24
Peak memory 211128 kb
Host smart-5a5e13d3-6a3d-44c6-9241-948f3e6af65a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630850199 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_max_throughput_chk.3630850199
Directory /workspace/38.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/38.rom_ctrl_smoke.3791950456
Short name T399
Test name
Test status
Simulation time 4129127995 ps
CPU time 40.33 seconds
Started Jan 24 02:34:02 PM PST 24
Finished Jan 24 02:34:58 PM PST 24
Peak memory 212828 kb
Host smart-69bf1721-df05-49ae-ab9b-495429b21b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791950456 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rom_ctrl_smoke.3791950456
Directory /workspace/38.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/38.rom_ctrl_stress_all.105184992
Short name T360
Test name
Test status
Simulation time 8417939245 ps
CPU time 35.08 seconds
Started Jan 24 02:34:03 PM PST 24
Finished Jan 24 02:34:53 PM PST 24
Peak memory 216476 kb
Host smart-b42635b9-1963-4280-a1b7-f53ea3ca8c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105184992 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.rom_ctrl_stress_all.105184992
Directory /workspace/38.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.rom_ctrl_alert_test.1400366718
Short name T162
Test name
Test status
Simulation time 1699911026 ps
CPU time 14 seconds
Started Jan 24 02:34:10 PM PST 24
Finished Jan 24 02:34:36 PM PST 24
Peak memory 210980 kb
Host smart-e4df88f0-9000-41d0-b34f-df6374d8efe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400366718 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_alert_test.1400366718
Directory /workspace/39.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.rom_ctrl_corrupt_sig_fatal_chk.1121591982
Short name T242
Test name
Test status
Simulation time 714605549863 ps
CPU time 332.16 seconds
Started Jan 24 02:34:09 PM PST 24
Finished Jan 24 02:39:53 PM PST 24
Peak memory 233732 kb
Host smart-dcdb141b-1622-4606-91a9-0644966b2577
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121591982 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_
corrupt_sig_fatal_chk.1121591982
Directory /workspace/39.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_kmac_err_chk.44775757
Short name T160
Test name
Test status
Simulation time 6144125932 ps
CPU time 28.37 seconds
Started Jan 24 02:34:08 PM PST 24
Finished Jan 24 02:34:49 PM PST 24
Peak memory 211256 kb
Host smart-4c68e59d-5ed8-4609-b030-2573d3531d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44775757 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_kmac_err_chk.44775757
Directory /workspace/39.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_max_throughput_chk.2063928743
Short name T169
Test name
Test status
Simulation time 5318837626 ps
CPU time 13.98 seconds
Started Jan 24 02:34:07 PM PST 24
Finished Jan 24 02:34:34 PM PST 24
Peak memory 211108 kb
Host smart-d4fbafe7-d470-4e98-90c0-d85dba588f63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063928743 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_max_throughput_chk.2063928743
Directory /workspace/39.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/39.rom_ctrl_smoke.1518307047
Short name T149
Test name
Test status
Simulation time 3491327373 ps
CPU time 30.34 seconds
Started Jan 24 03:19:19 PM PST 24
Finished Jan 24 03:19:59 PM PST 24
Peak memory 213016 kb
Host smart-57b96009-5592-47a3-85de-b9523c9966f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518307047 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rom_ctrl_smoke.1518307047
Directory /workspace/39.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/39.rom_ctrl_stress_all.833643656
Short name T172
Test name
Test status
Simulation time 23841825756 ps
CPU time 65.63 seconds
Started Jan 24 03:18:54 PM PST 24
Finished Jan 24 03:20:02 PM PST 24
Peak memory 216512 kb
Host smart-fb332831-dbb7-45b4-9505-51fe3cbf3eaf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833643656 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 39.rom_ctrl_stress_all.833643656
Directory /workspace/39.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_alert_test.2279181788
Short name T133
Test name
Test status
Simulation time 379182485 ps
CPU time 4.33 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:30:53 PM PST 24
Peak memory 210576 kb
Host smart-23f3c8e3-470a-4d2a-a317-b9a51bddca0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279181788 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_alert_test.2279181788
Directory /workspace/4.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.749465768
Short name T397
Test name
Test status
Simulation time 1860483179 ps
CPU time 61.08 seconds
Started Jan 24 02:30:25 PM PST 24
Finished Jan 24 02:31:38 PM PST 24
Peak memory 212168 kb
Host smart-50279357-48ad-4261-be1a-f148a7d01ba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749465768 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_co
rrupt_sig_fatal_chk.749465768
Directory /workspace/4.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_kmac_err_chk.4150170843
Short name T278
Test name
Test status
Simulation time 2251096454 ps
CPU time 23.4 seconds
Started Jan 24 02:30:24 PM PST 24
Finished Jan 24 02:30:59 PM PST 24
Peak memory 211276 kb
Host smart-f37e76b7-3eee-456e-9fa7-4f6e1ebda2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150170843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_kmac_err_chk.4150170843
Directory /workspace/4.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_max_throughput_chk.3616581025
Short name T350
Test name
Test status
Simulation time 198483501 ps
CPU time 5.66 seconds
Started Jan 24 02:30:25 PM PST 24
Finished Jan 24 02:30:42 PM PST 24
Peak memory 211036 kb
Host smart-624452cb-ec4e-4586-b9b9-50e223018218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616581025 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_max_throughput_chk.3616581025
Directory /workspace/4.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/4.rom_ctrl_smoke.1750783205
Short name T170
Test name
Test status
Simulation time 9229506005 ps
CPU time 23.73 seconds
Started Jan 24 02:30:25 PM PST 24
Finished Jan 24 02:31:00 PM PST 24
Peak memory 213052 kb
Host smart-73ed1d0d-c0a9-4ae3-b8dc-2582bdd1edfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750783205 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_smoke.1750783205
Directory /workspace/4.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all.3386508892
Short name T315
Test name
Test status
Simulation time 2491431619 ps
CPU time 16.57 seconds
Started Jan 24 02:30:26 PM PST 24
Finished Jan 24 02:30:54 PM PST 24
Peak memory 210964 kb
Host smart-7c9b0d2d-dc74-4b99-a0c8-5bac5a9368ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386508892 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 4.rom_ctrl_stress_all.3386508892
Directory /workspace/4.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.2007770005
Short name T311
Test name
Test status
Simulation time 139469074335 ps
CPU time 1998.38 seconds
Started Jan 24 02:30:25 PM PST 24
Finished Jan 24 03:03:55 PM PST 24
Peak memory 235744 kb
Host smart-48ad4b04-fa54-46be-90ff-86c7207d37be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007770005 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rom_ctrl_stress_all_with_rand_reset.2007770005
Directory /workspace/4.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rom_ctrl_alert_test.3713597927
Short name T44
Test name
Test status
Simulation time 272807281 ps
CPU time 5.16 seconds
Started Jan 24 02:34:13 PM PST 24
Finished Jan 24 02:34:29 PM PST 24
Peak memory 211036 kb
Host smart-30e1caf6-e85e-47bd-83ee-506eab0878ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713597927 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_alert_test.3713597927
Directory /workspace/40.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.rom_ctrl_corrupt_sig_fatal_chk.1298848469
Short name T54
Test name
Test status
Simulation time 37880679803 ps
CPU time 317.41 seconds
Started Jan 24 02:34:12 PM PST 24
Finished Jan 24 02:39:42 PM PST 24
Peak memory 212288 kb
Host smart-8c702556-db96-4acc-b4eb-2db5fe68746e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298848469 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_
corrupt_sig_fatal_chk.1298848469
Directory /workspace/40.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_kmac_err_chk.483332832
Short name T23
Test name
Test status
Simulation time 170571796 ps
CPU time 9.48 seconds
Started Jan 24 02:34:13 PM PST 24
Finished Jan 24 02:34:34 PM PST 24
Peak memory 211204 kb
Host smart-983349a7-e942-4682-80ed-e21cbcac3cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483332832 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_kmac_err_chk.483332832
Directory /workspace/40.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_max_throughput_chk.1214055638
Short name T183
Test name
Test status
Simulation time 664883410 ps
CPU time 5.65 seconds
Started Jan 24 02:34:12 PM PST 24
Finished Jan 24 02:34:30 PM PST 24
Peak memory 210968 kb
Host smart-4fe1aeeb-542d-44c8-9cb0-f32b9513d8f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214055638 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_max_throughput_chk.1214055638
Directory /workspace/40.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/40.rom_ctrl_smoke.2660136930
Short name T406
Test name
Test status
Simulation time 380297581 ps
CPU time 10.49 seconds
Started Jan 24 02:34:06 PM PST 24
Finished Jan 24 02:34:30 PM PST 24
Peak memory 212820 kb
Host smart-139d3a73-2e92-48a5-b70b-c84aee307414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660136930 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_smoke.2660136930
Directory /workspace/40.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all.1395884922
Short name T353
Test name
Test status
Simulation time 11867109353 ps
CPU time 28.85 seconds
Started Jan 24 02:34:11 PM PST 24
Finished Jan 24 02:34:51 PM PST 24
Peak memory 213552 kb
Host smart-ad62dbbd-18fa-4962-bb90-2b9b0068f1ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395884922 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 40.rom_ctrl_stress_all.1395884922
Directory /workspace/40.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.rom_ctrl_stress_all_with_rand_reset.1021151105
Short name T299
Test name
Test status
Simulation time 63749678624 ps
CPU time 2487.75 seconds
Started Jan 24 02:34:08 PM PST 24
Finished Jan 24 03:15:48 PM PST 24
Peak memory 243936 kb
Host smart-4e1046bc-1dd3-4a3b-a7b8-5523aba4340a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021151105 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rom_ctrl_stress_all_with_rand_reset.1021151105
Directory /workspace/40.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rom_ctrl_alert_test.1754149467
Short name T304
Test name
Test status
Simulation time 1350822911 ps
CPU time 12.12 seconds
Started Jan 24 02:34:24 PM PST 24
Finished Jan 24 02:34:44 PM PST 24
Peak memory 210980 kb
Host smart-e98d3e15-d882-4d4f-be34-c817d3db4b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754149467 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_alert_test.1754149467
Directory /workspace/41.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.rom_ctrl_kmac_err_chk.1835690540
Short name T3
Test name
Test status
Simulation time 7601496860 ps
CPU time 21.63 seconds
Started Jan 24 02:34:24 PM PST 24
Finished Jan 24 02:34:54 PM PST 24
Peak memory 211956 kb
Host smart-b29709a9-2baa-43c4-87bf-f65c73dd4b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835690540 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_kmac_err_chk.1835690540
Directory /workspace/41.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_max_throughput_chk.2037631113
Short name T289
Test name
Test status
Simulation time 8072738072 ps
CPU time 17.23 seconds
Started Jan 24 02:34:26 PM PST 24
Finished Jan 24 02:34:51 PM PST 24
Peak memory 211104 kb
Host smart-5a780bbc-2853-4095-a22f-983a1c0e0018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037631113 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_max_throughput_chk.2037631113
Directory /workspace/41.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/41.rom_ctrl_smoke.3199154316
Short name T132
Test name
Test status
Simulation time 3492182538 ps
CPU time 20.92 seconds
Started Jan 24 02:34:08 PM PST 24
Finished Jan 24 02:34:42 PM PST 24
Peak memory 212384 kb
Host smart-2c4e40dd-1218-4438-ac1a-457842c360ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199154316 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rom_ctrl_smoke.3199154316
Directory /workspace/41.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/41.rom_ctrl_stress_all.1858941912
Short name T238
Test name
Test status
Simulation time 782377448 ps
CPU time 15.37 seconds
Started Jan 24 02:34:08 PM PST 24
Finished Jan 24 02:34:36 PM PST 24
Peak memory 213720 kb
Host smart-5fc92319-2086-4ecf-9c44-479f55ac98f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858941912 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.rom_ctrl_stress_all.1858941912
Directory /workspace/41.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_alert_test.1858876124
Short name T395
Test name
Test status
Simulation time 3573959950 ps
CPU time 9.47 seconds
Started Jan 24 02:34:28 PM PST 24
Finished Jan 24 02:34:44 PM PST 24
Peak memory 211096 kb
Host smart-3f6aacbb-7f51-4219-97b1-87c95375e020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858876124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_alert_test.1858876124
Directory /workspace/42.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.rom_ctrl_corrupt_sig_fatal_chk.1901278572
Short name T343
Test name
Test status
Simulation time 88328064176 ps
CPU time 383.27 seconds
Started Jan 24 02:34:32 PM PST 24
Finished Jan 24 02:41:01 PM PST 24
Peak memory 237620 kb
Host smart-8d0dc9f3-aa7c-4d48-83d0-cde3d84d6cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901278572 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_
corrupt_sig_fatal_chk.1901278572
Directory /workspace/42.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_kmac_err_chk.799156345
Short name T354
Test name
Test status
Simulation time 15413504591 ps
CPU time 31.72 seconds
Started Jan 24 02:34:30 PM PST 24
Finished Jan 24 02:35:08 PM PST 24
Peak memory 211112 kb
Host smart-0809c02f-8d91-4286-8c89-6bb17af1b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799156345 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_kmac_err_chk.799156345
Directory /workspace/42.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_max_throughput_chk.3489114843
Short name T298
Test name
Test status
Simulation time 8330084168 ps
CPU time 12.61 seconds
Started Jan 24 02:34:29 PM PST 24
Finished Jan 24 02:34:48 PM PST 24
Peak memory 211100 kb
Host smart-b80c9f08-cc05-4c9d-9565-105f755a869f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489114843 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_max_throughput_chk.3489114843
Directory /workspace/42.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/42.rom_ctrl_smoke.1352245006
Short name T184
Test name
Test status
Simulation time 3802038026 ps
CPU time 24.14 seconds
Started Jan 24 03:53:01 PM PST 24
Finished Jan 24 03:53:26 PM PST 24
Peak memory 213164 kb
Host smart-75254c96-e05e-4c89-8e06-f1de7fcbe0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352245006 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_smoke.1352245006
Directory /workspace/42.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all.3000698631
Short name T319
Test name
Test status
Simulation time 3717849046 ps
CPU time 36.82 seconds
Started Jan 24 02:54:18 PM PST 24
Finished Jan 24 02:55:19 PM PST 24
Peak memory 213792 kb
Host smart-bf7dd69a-d37b-4ca0-9667-8126ffa20e73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000698631 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 42.rom_ctrl_stress_all.3000698631
Directory /workspace/42.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.rom_ctrl_stress_all_with_rand_reset.3042136591
Short name T366
Test name
Test status
Simulation time 761369753909 ps
CPU time 4437.27 seconds
Started Jan 24 02:34:29 PM PST 24
Finished Jan 24 03:48:33 PM PST 24
Peak memory 253568 kb
Host smart-1dafc0ae-df1c-4a7b-aae7-c9d44064b7d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042136591 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rom_ctrl_stress_all_with_rand_reset.3042136591
Directory /workspace/42.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rom_ctrl_alert_test.3261984212
Short name T204
Test name
Test status
Simulation time 170006761 ps
CPU time 5.43 seconds
Started Jan 24 02:34:44 PM PST 24
Finished Jan 24 02:34:54 PM PST 24
Peak memory 211020 kb
Host smart-e60a3f74-3d21-4583-8bc5-5e1195fce7d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261984212 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_alert_test.3261984212
Directory /workspace/43.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.rom_ctrl_corrupt_sig_fatal_chk.1613898965
Short name T206
Test name
Test status
Simulation time 82497217820 ps
CPU time 285.93 seconds
Started Jan 24 02:34:42 PM PST 24
Finished Jan 24 02:39:33 PM PST 24
Peak memory 238672 kb
Host smart-73729bb1-de61-4462-b15c-fec512f0fd56
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613898965 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_
corrupt_sig_fatal_chk.1613898965
Directory /workspace/43.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_kmac_err_chk.2755836400
Short name T247
Test name
Test status
Simulation time 3477734311 ps
CPU time 29.3 seconds
Started Jan 24 02:34:43 PM PST 24
Finished Jan 24 02:35:17 PM PST 24
Peak memory 211508 kb
Host smart-9e9d36fb-7913-4105-ace1-1b5c496a871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755836400 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_kmac_err_chk.2755836400
Directory /workspace/43.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_max_throughput_chk.4148483794
Short name T390
Test name
Test status
Simulation time 3634621440 ps
CPU time 10.96 seconds
Started Jan 24 02:34:30 PM PST 24
Finished Jan 24 02:34:47 PM PST 24
Peak memory 211108 kb
Host smart-399a1eed-0413-493f-9349-f53559d59a42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4148483794 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_max_throughput_chk.4148483794
Directory /workspace/43.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/43.rom_ctrl_smoke.1396649277
Short name T291
Test name
Test status
Simulation time 378409351 ps
CPU time 10.48 seconds
Started Jan 24 02:34:33 PM PST 24
Finished Jan 24 02:34:49 PM PST 24
Peak memory 213028 kb
Host smart-afc068b4-2491-4327-a916-1104d2209bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396649277 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rom_ctrl_smoke.1396649277
Directory /workspace/43.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_alert_test.172125576
Short name T202
Test name
Test status
Simulation time 733150752 ps
CPU time 6.86 seconds
Started Jan 24 02:35:01 PM PST 24
Finished Jan 24 02:35:12 PM PST 24
Peak memory 210940 kb
Host smart-2252f561-5505-424a-b072-9404a66b9f54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172125576 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_alert_test.172125576
Directory /workspace/44.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.rom_ctrl_corrupt_sig_fatal_chk.2773523420
Short name T333
Test name
Test status
Simulation time 55153331743 ps
CPU time 235.47 seconds
Started Jan 24 02:34:38 PM PST 24
Finished Jan 24 02:38:37 PM PST 24
Peak memory 224460 kb
Host smart-59aeaa7a-b6e0-4ccb-997a-b6d480b1fee2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773523420 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_
corrupt_sig_fatal_chk.2773523420
Directory /workspace/44.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_kmac_err_chk.3922821803
Short name T177
Test name
Test status
Simulation time 6595734170 ps
CPU time 11.59 seconds
Started Jan 24 02:34:44 PM PST 24
Finished Jan 24 02:35:00 PM PST 24
Peak memory 212084 kb
Host smart-0488d50c-584e-47ae-b09c-f0dc690c30a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922821803 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_kmac_err_chk.3922821803
Directory /workspace/44.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_max_throughput_chk.3825223755
Short name T327
Test name
Test status
Simulation time 95818538 ps
CPU time 5.65 seconds
Started Jan 24 02:34:41 PM PST 24
Finished Jan 24 02:34:52 PM PST 24
Peak memory 211044 kb
Host smart-380671ce-16c1-49ab-a9c7-9b7e73b49e0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3825223755 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_max_throughput_chk.3825223755
Directory /workspace/44.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/44.rom_ctrl_smoke.1130511008
Short name T175
Test name
Test status
Simulation time 192933314 ps
CPU time 10.1 seconds
Started Jan 24 02:34:40 PM PST 24
Finished Jan 24 02:34:56 PM PST 24
Peak memory 212832 kb
Host smart-f1765482-d5cb-4c2a-aafc-bf2a12714d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130511008 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_smoke.1130511008
Directory /workspace/44.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all.3930520124
Short name T383
Test name
Test status
Simulation time 32730191303 ps
CPU time 35.91 seconds
Started Jan 24 02:34:43 PM PST 24
Finished Jan 24 02:35:24 PM PST 24
Peak memory 216076 kb
Host smart-5effbc84-56b4-4b7b-a56a-63472a329df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930520124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 44.rom_ctrl_stress_all.3930520124
Directory /workspace/44.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.rom_ctrl_stress_all_with_rand_reset.3379109908
Short name T12
Test name
Test status
Simulation time 42217336184 ps
CPU time 1865.26 seconds
Started Jan 24 03:07:09 PM PST 24
Finished Jan 24 03:38:38 PM PST 24
Peak memory 235676 kb
Host smart-e6a38ee1-6124-44da-aafe-de28bd7cc4a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379109908 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rom_ctrl_stress_all_with_rand_reset.3379109908
Directory /workspace/44.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rom_ctrl_alert_test.2902353019
Short name T316
Test name
Test status
Simulation time 5585020653 ps
CPU time 13.24 seconds
Started Jan 24 02:34:57 PM PST 24
Finished Jan 24 02:35:13 PM PST 24
Peak memory 211152 kb
Host smart-1f17c5a8-1718-4f26-ba7b-9956f6e880ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902353019 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_alert_test.2902353019
Directory /workspace/45.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.rom_ctrl_corrupt_sig_fatal_chk.4119357802
Short name T29
Test name
Test status
Simulation time 5514639957 ps
CPU time 105.37 seconds
Started Jan 24 02:55:48 PM PST 24
Finished Jan 24 02:57:43 PM PST 24
Peak memory 228300 kb
Host smart-28e51a36-bfdb-4d53-8609-6be07538b4a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119357802 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_
corrupt_sig_fatal_chk.4119357802
Directory /workspace/45.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_kmac_err_chk.3774420559
Short name T288
Test name
Test status
Simulation time 7042642609 ps
CPU time 29.55 seconds
Started Jan 24 02:35:00 PM PST 24
Finished Jan 24 02:35:34 PM PST 24
Peak memory 211724 kb
Host smart-060f1ab7-7c9c-4151-b33a-64eb721e5d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774420559 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_kmac_err_chk.3774420559
Directory /workspace/45.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_max_throughput_chk.396196904
Short name T348
Test name
Test status
Simulation time 1706749650 ps
CPU time 14.6 seconds
Started Jan 24 02:45:32 PM PST 24
Finished Jan 24 02:46:00 PM PST 24
Peak memory 211064 kb
Host smart-0cd9fd44-9134-4efe-8935-74693efcc7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396196904 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_max_throughput_chk.396196904
Directory /workspace/45.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/45.rom_ctrl_smoke.1349862675
Short name T151
Test name
Test status
Simulation time 51708059985 ps
CPU time 34 seconds
Started Jan 24 02:56:03 PM PST 24
Finished Jan 24 02:56:40 PM PST 24
Peak memory 215044 kb
Host smart-df6055be-00b4-4785-aa26-a752a0d74a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349862675 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_smoke.1349862675
Directory /workspace/45.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all.4096323034
Short name T303
Test name
Test status
Simulation time 3686545219 ps
CPU time 37.28 seconds
Started Jan 24 02:35:01 PM PST 24
Finished Jan 24 02:35:42 PM PST 24
Peak memory 212792 kb
Host smart-9d1291e1-3bb6-4f15-b78d-d640612b114f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096323034 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 45.rom_ctrl_stress_all.4096323034
Directory /workspace/45.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.rom_ctrl_stress_all_with_rand_reset.3914212279
Short name T167
Test name
Test status
Simulation time 66532185772 ps
CPU time 1769.37 seconds
Started Jan 24 02:35:01 PM PST 24
Finished Jan 24 03:04:35 PM PST 24
Peak memory 235732 kb
Host smart-a882d99f-e4fe-48f9-ae35-ab9ec2b0bfac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914212279 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rom_ctrl_stress_all_with_rand_reset.3914212279
Directory /workspace/45.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rom_ctrl_alert_test.1046286734
Short name T253
Test name
Test status
Simulation time 2021101083 ps
CPU time 15.38 seconds
Started Jan 24 02:35:09 PM PST 24
Finished Jan 24 02:35:29 PM PST 24
Peak memory 211000 kb
Host smart-da2dfbb0-fc37-42ec-998f-76a576a9557e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046286734 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_alert_test.1046286734
Directory /workspace/46.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.rom_ctrl_corrupt_sig_fatal_chk.2813551581
Short name T214
Test name
Test status
Simulation time 34588328583 ps
CPU time 176.42 seconds
Started Jan 24 02:35:07 PM PST 24
Finished Jan 24 02:38:08 PM PST 24
Peak memory 213320 kb
Host smart-91e0c6ba-5e09-45fe-922e-692231c96cc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813551581 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_
corrupt_sig_fatal_chk.2813551581
Directory /workspace/46.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_kmac_err_chk.1178467672
Short name T250
Test name
Test status
Simulation time 5120918882 ps
CPU time 16.94 seconds
Started Jan 24 02:35:07 PM PST 24
Finished Jan 24 02:35:29 PM PST 24
Peak memory 211712 kb
Host smart-f984046a-5c83-4d4b-8827-b7acb6db728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178467672 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_kmac_err_chk.1178467672
Directory /workspace/46.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_max_throughput_chk.4216737325
Short name T187
Test name
Test status
Simulation time 7648498207 ps
CPU time 17.48 seconds
Started Jan 24 02:35:07 PM PST 24
Finished Jan 24 02:35:30 PM PST 24
Peak memory 211108 kb
Host smart-a907c12b-1ee5-489d-bbed-3196b7c9698f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4216737325 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_max_throughput_chk.4216737325
Directory /workspace/46.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/46.rom_ctrl_smoke.175595430
Short name T279
Test name
Test status
Simulation time 9826413104 ps
CPU time 34.04 seconds
Started Jan 24 02:54:30 PM PST 24
Finished Jan 24 02:55:26 PM PST 24
Peak memory 213452 kb
Host smart-58275701-86ab-4c43-abd5-478299821931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175595430 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_smoke.175595430
Directory /workspace/46.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all.715892767
Short name T246
Test name
Test status
Simulation time 1950960220 ps
CPU time 33.06 seconds
Started Jan 24 02:59:43 PM PST 24
Finished Jan 24 03:00:42 PM PST 24
Peak memory 212108 kb
Host smart-f9f8d3e2-3f92-4062-9d13-8d85acb6985c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715892767 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.rom_ctrl_stress_all.715892767
Directory /workspace/46.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.rom_ctrl_stress_all_with_rand_reset.4177513034
Short name T105
Test name
Test status
Simulation time 55115918156 ps
CPU time 2163.58 seconds
Started Jan 24 02:35:06 PM PST 24
Finished Jan 24 03:11:16 PM PST 24
Peak memory 239736 kb
Host smart-c76a2198-c211-4bbf-941c-252f46a1961f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177513034 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rom_ctrl_stress_all_with_rand_reset.4177513034
Directory /workspace/46.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rom_ctrl_alert_test.440458365
Short name T329
Test name
Test status
Simulation time 1018465088 ps
CPU time 10.46 seconds
Started Jan 24 02:35:12 PM PST 24
Finished Jan 24 02:35:26 PM PST 24
Peak memory 211008 kb
Host smart-eea73178-c3ce-4602-bf13-741c8ac47325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440458365 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_alert_test.440458365
Directory /workspace/47.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.rom_ctrl_corrupt_sig_fatal_chk.824081168
Short name T258
Test name
Test status
Simulation time 10812007345 ps
CPU time 101.03 seconds
Started Jan 24 02:35:09 PM PST 24
Finished Jan 24 02:36:54 PM PST 24
Peak memory 240528 kb
Host smart-c0aca1a3-799f-40dc-81a5-f1d5a40c9f96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824081168 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_c
orrupt_sig_fatal_chk.824081168
Directory /workspace/47.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_kmac_err_chk.1595222007
Short name T400
Test name
Test status
Simulation time 1281551009 ps
CPU time 9.46 seconds
Started Jan 24 02:35:10 PM PST 24
Finished Jan 24 02:35:23 PM PST 24
Peak memory 211604 kb
Host smart-aa25dbc8-7328-4fcb-9664-08ce5c4ff0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595222007 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_kmac_err_chk.1595222007
Directory /workspace/47.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_max_throughput_chk.626010303
Short name T272
Test name
Test status
Simulation time 4213436213 ps
CPU time 18.56 seconds
Started Jan 24 02:46:08 PM PST 24
Finished Jan 24 02:46:32 PM PST 24
Peak memory 211148 kb
Host smart-3540e73f-32e1-45e9-a4cc-331533acae22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626010303 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_max_throughput_chk.626010303
Directory /workspace/47.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/47.rom_ctrl_smoke.1146702235
Short name T241
Test name
Test status
Simulation time 11735888244 ps
CPU time 25.77 seconds
Started Jan 24 02:35:16 PM PST 24
Finished Jan 24 02:35:53 PM PST 24
Peak memory 213708 kb
Host smart-15d737ab-d493-4403-a1bc-e97a5ea4ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146702235 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rom_ctrl_smoke.1146702235
Directory /workspace/47.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/47.rom_ctrl_stress_all.3719269097
Short name T15
Test name
Test status
Simulation time 469425110 ps
CPU time 8.98 seconds
Started Jan 24 03:54:46 PM PST 24
Finished Jan 24 03:54:57 PM PST 24
Peak memory 211024 kb
Host smart-a1cd6c80-1989-4ec2-9675-697efe61cbbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719269097 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 47.rom_ctrl_stress_all.3719269097
Directory /workspace/47.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_alert_test.881861308
Short name T188
Test name
Test status
Simulation time 2863436651 ps
CPU time 8.4 seconds
Started Jan 24 02:35:21 PM PST 24
Finished Jan 24 02:35:47 PM PST 24
Peak memory 211064 kb
Host smart-c789aa87-9e29-4acf-a795-a7e8d0899ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881861308 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_alert_test.881861308
Directory /workspace/48.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.rom_ctrl_corrupt_sig_fatal_chk.2300431499
Short name T309
Test name
Test status
Simulation time 43634663302 ps
CPU time 405.73 seconds
Started Jan 24 02:35:21 PM PST 24
Finished Jan 24 02:42:25 PM PST 24
Peak memory 237652 kb
Host smart-d34cb40a-e1c8-4090-8278-263ab8eb5e2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300431499 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_
corrupt_sig_fatal_chk.2300431499
Directory /workspace/48.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_kmac_err_chk.827442276
Short name T237
Test name
Test status
Simulation time 3618662434 ps
CPU time 20.53 seconds
Started Jan 24 02:35:23 PM PST 24
Finished Jan 24 02:36:00 PM PST 24
Peak memory 213060 kb
Host smart-cfc01693-21e8-4982-a060-6940c657fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827442276 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_kmac_err_chk.827442276
Directory /workspace/48.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_max_throughput_chk.3767330151
Short name T233
Test name
Test status
Simulation time 2309168972 ps
CPU time 16.81 seconds
Started Jan 24 02:35:17 PM PST 24
Finished Jan 24 02:35:53 PM PST 24
Peak memory 211104 kb
Host smart-8d8759e0-0610-4378-8f19-38eb52f39061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767330151 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_max_throughput_chk.3767330151
Directory /workspace/48.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/48.rom_ctrl_smoke.837118289
Short name T261
Test name
Test status
Simulation time 4513800487 ps
CPU time 18.39 seconds
Started Jan 24 02:35:16 PM PST 24
Finished Jan 24 02:35:46 PM PST 24
Peak memory 213108 kb
Host smart-021d52b7-8241-4830-b788-9c37c405442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837118289 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_smoke.837118289
Directory /workspace/48.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all.1776983890
Short name T326
Test name
Test status
Simulation time 33065717510 ps
CPU time 81.52 seconds
Started Jan 24 02:35:17 PM PST 24
Finished Jan 24 02:36:55 PM PST 24
Peak memory 217328 kb
Host smart-d9756894-e866-408c-a98f-49ab170e8f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776983890 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 48.rom_ctrl_stress_all.1776983890
Directory /workspace/48.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.rom_ctrl_stress_all_with_rand_reset.3038904652
Short name T313
Test name
Test status
Simulation time 132201533559 ps
CPU time 1577.78 seconds
Started Jan 24 02:35:24 PM PST 24
Finished Jan 24 03:01:58 PM PST 24
Peak memory 235732 kb
Host smart-df92c549-4000-4e2d-af40-6fdeb950d725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038904652 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rom_ctrl_stress_all_with_rand_reset.3038904652
Directory /workspace/48.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rom_ctrl_alert_test.735732940
Short name T264
Test name
Test status
Simulation time 1602451572 ps
CPU time 14.07 seconds
Started Jan 24 02:35:18 PM PST 24
Finished Jan 24 02:35:51 PM PST 24
Peak memory 211012 kb
Host smart-82570c8f-0c76-49c1-895e-c8c7c143fde2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735732940 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_alert_test.735732940
Directory /workspace/49.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.rom_ctrl_corrupt_sig_fatal_chk.2189606109
Short name T225
Test name
Test status
Simulation time 15798294384 ps
CPU time 141.33 seconds
Started Jan 24 02:35:23 PM PST 24
Finished Jan 24 02:38:01 PM PST 24
Peak memory 237604 kb
Host smart-f4e6dd68-cb2e-4433-b724-d4e3c8a80b02
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189606109 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_
corrupt_sig_fatal_chk.2189606109
Directory /workspace/49.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_kmac_err_chk.2098327118
Short name T139
Test name
Test status
Simulation time 2505297723 ps
CPU time 17.81 seconds
Started Jan 24 02:35:25 PM PST 24
Finished Jan 24 02:35:59 PM PST 24
Peak memory 211348 kb
Host smart-040bf21e-f605-4c31-8c72-f85ea969340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098327118 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_kmac_err_chk.2098327118
Directory /workspace/49.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_max_throughput_chk.3782566441
Short name T147
Test name
Test status
Simulation time 2363376781 ps
CPU time 7.74 seconds
Started Jan 24 02:35:18 PM PST 24
Finished Jan 24 02:35:44 PM PST 24
Peak memory 211128 kb
Host smart-0d790ca6-b0c2-4463-a99a-9ed3590d705e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782566441 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_max_throughput_chk.3782566441
Directory /workspace/49.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/49.rom_ctrl_smoke.28225263
Short name T152
Test name
Test status
Simulation time 1472129777 ps
CPU time 10.22 seconds
Started Jan 24 02:35:25 PM PST 24
Finished Jan 24 02:35:51 PM PST 24
Peak memory 213276 kb
Host smart-faecf50a-cf31-448c-bb63-041b1b1c1239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28225263 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rom_ctrl_smoke.28225263
Directory /workspace/49.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_alert_test.3747416521
Short name T384
Test name
Test status
Simulation time 1405867489 ps
CPU time 13.44 seconds
Started Jan 24 02:49:52 PM PST 24
Finished Jan 24 02:50:28 PM PST 24
Peak memory 211036 kb
Host smart-cc484579-057c-48b3-9836-2e61f171ab62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747416521 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_alert_test.3747416521
Directory /workspace/5.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.298815009
Short name T25
Test name
Test status
Simulation time 23387923652 ps
CPU time 273.27 seconds
Started Jan 24 02:30:40 PM PST 24
Finished Jan 24 02:35:23 PM PST 24
Peak memory 232872 kb
Host smart-d5423cba-dc5c-46b1-be4e-d84ed8602303
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298815009 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt
_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_co
rrupt_sig_fatal_chk.298815009
Directory /workspace/5.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_kmac_err_chk.1406225975
Short name T166
Test name
Test status
Simulation time 2423809681 ps
CPU time 14.03 seconds
Started Jan 24 02:50:26 PM PST 24
Finished Jan 24 02:50:53 PM PST 24
Peak memory 211480 kb
Host smart-f02deab8-9df3-45e4-bfab-49be1ce1dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406225975 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_kmac_err_chk.1406225975
Directory /workspace/5.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_max_throughput_chk.1591730660
Short name T178
Test name
Test status
Simulation time 1120726896 ps
CPU time 11.56 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:31:00 PM PST 24
Peak memory 211016 kb
Host smart-2d01d806-b0a3-40ed-be3a-cacf36b61dca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591730660 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_max_throughput_chk.1591730660
Directory /workspace/5.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/5.rom_ctrl_smoke.670758329
Short name T256
Test name
Test status
Simulation time 20629118846 ps
CPU time 23.02 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:31:11 PM PST 24
Peak memory 213808 kb
Host smart-322cf8f7-72dd-4535-b64c-c05dd8228325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670758329 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_smoke.670758329
Directory /workspace/5.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all.3450465057
Short name T337
Test name
Test status
Simulation time 9946547328 ps
CPU time 60.57 seconds
Started Jan 24 02:30:40 PM PST 24
Finished Jan 24 02:31:50 PM PST 24
Peak memory 213180 kb
Host smart-db3bce6d-f43e-41f7-ad37-ff54ce427200
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450465057 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 5.rom_ctrl_stress_all.3450465057
Directory /workspace/5.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.1533965142
Short name T377
Test name
Test status
Simulation time 68635538296 ps
CPU time 618.11 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:41:07 PM PST 24
Peak memory 235280 kb
Host smart-e7e5df98-e5d5-4e22-970e-f176497339ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533965142 -assert nop
ostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rom_ctrl_stress_all_with_rand_reset.1533965142
Directory /workspace/5.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.rom_ctrl_alert_test.2178215310
Short name T282
Test name
Test status
Simulation time 87481717 ps
CPU time 4.42 seconds
Started Jan 24 02:30:36 PM PST 24
Finished Jan 24 02:30:51 PM PST 24
Peak memory 210564 kb
Host smart-64db9be8-5faf-4933-b272-e8c72cda2d84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178215310 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_alert_test.2178215310
Directory /workspace/6.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.3867008058
Short name T56
Test name
Test status
Simulation time 90311974920 ps
CPU time 465.76 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:38:35 PM PST 24
Peak memory 233520 kb
Host smart-23612d81-daba-4523-ac22-530baf5026af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867008058 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_c
orrupt_sig_fatal_chk.3867008058
Directory /workspace/6.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_kmac_err_chk.418175587
Short name T314
Test name
Test status
Simulation time 602554214 ps
CPU time 13.91 seconds
Started Jan 24 02:30:40 PM PST 24
Finished Jan 24 02:31:04 PM PST 24
Peak memory 211228 kb
Host smart-b8717939-7638-486f-8d4a-ba98ad91ed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418175587 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_kmac_err_chk.418175587
Directory /workspace/6.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_max_throughput_chk.3807860949
Short name T103
Test name
Test status
Simulation time 6700176380 ps
CPU time 13.48 seconds
Started Jan 24 02:30:37 PM PST 24
Finished Jan 24 02:31:01 PM PST 24
Peak memory 211148 kb
Host smart-82dc2b2c-c56a-4bac-b763-e3bf6fb7002b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3807860949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_max_throughput_chk.3807860949
Directory /workspace/6.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/6.rom_ctrl_smoke.820850949
Short name T155
Test name
Test status
Simulation time 7613711268 ps
CPU time 20.61 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:31:09 PM PST 24
Peak memory 214224 kb
Host smart-ca4583b7-bf37-4af5-ab9e-6c06dee957f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820850949 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rom_ctrl_smoke.820850949
Directory /workspace/6.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/6.rom_ctrl_stress_all.278474508
Short name T232
Test name
Test status
Simulation time 3009021694 ps
CPU time 24.78 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:31:13 PM PST 24
Peak memory 215016 kb
Host smart-5f52dc11-21ea-4e56-b877-18753abd3e92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278474508 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +
UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.rom_ctrl_stress_all.278474508
Directory /workspace/6.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_alert_test.375811216
Short name T215
Test name
Test status
Simulation time 12523756951 ps
CPU time 17.46 seconds
Started Jan 24 02:30:37 PM PST 24
Finished Jan 24 02:31:05 PM PST 24
Peak memory 211136 kb
Host smart-7e4a2908-5f92-4e3d-b9ab-3e54466f4dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375811216 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_alert_test.375811216
Directory /workspace/7.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.2115708268
Short name T208
Test name
Test status
Simulation time 19473330696 ps
CPU time 224.98 seconds
Started Jan 24 02:30:34 PM PST 24
Finished Jan 24 02:34:30 PM PST 24
Peak memory 236616 kb
Host smart-a30ad429-46a9-4c1c-97f0-c9aae7af800a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115708268 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_c
orrupt_sig_fatal_chk.2115708268
Directory /workspace/7.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_kmac_err_chk.3433685066
Short name T369
Test name
Test status
Simulation time 664844816 ps
CPU time 9.49 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:30:58 PM PST 24
Peak memory 211328 kb
Host smart-155acc8a-84bf-4670-b478-eff829e2d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433685066 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_kmac_err_chk.3433685066
Directory /workspace/7.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_max_throughput_chk.729432963
Short name T102
Test name
Test status
Simulation time 2423526445 ps
CPU time 8.99 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:30:57 PM PST 24
Peak memory 211136 kb
Host smart-8960cc61-9c4f-46f9-9846-c198f85a07c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=729432963 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_max_throughput_chk.729432963
Directory /workspace/7.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/7.rom_ctrl_smoke.1779126225
Short name T335
Test name
Test status
Simulation time 9274977308 ps
CPU time 25.2 seconds
Started Jan 24 02:30:40 PM PST 24
Finished Jan 24 02:31:15 PM PST 24
Peak memory 213572 kb
Host smart-d04429a2-8cfe-4faf-a641-d2faa79ef14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779126225 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_smoke.1779126225
Directory /workspace/7.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all.4246023939
Short name T226
Test name
Test status
Simulation time 12352763449 ps
CPU time 65.09 seconds
Started Jan 24 02:30:37 PM PST 24
Finished Jan 24 02:31:53 PM PST 24
Peak memory 219324 kb
Host smart-45649602-a0f6-42bf-9637-c5a4c0d8716d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246023939 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 7.rom_ctrl_stress_all.4246023939
Directory /workspace/7.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.835901573
Short name T14
Test name
Test status
Simulation time 17057567840 ps
CPU time 1009.63 seconds
Started Jan 24 02:30:38 PM PST 24
Finished Jan 24 02:47:38 PM PST 24
Peak memory 229848 kb
Host smart-27495c3b-3dda-4956-bbd7-200ee9c3a5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835901573 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rom_ctrl_stress_all_with_rand_reset.835901573
Directory /workspace/7.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.rom_ctrl_alert_test.3323911233
Short name T223
Test name
Test status
Simulation time 5511652524 ps
CPU time 12.58 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:09 PM PST 24
Peak memory 211096 kb
Host smart-ebed4c82-f596-4590-891d-720cd2fbc694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323911233 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_alert_test.3323911233
Directory /workspace/8.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2651416223
Short name T321
Test name
Test status
Simulation time 84219553734 ps
CPU time 335.09 seconds
Started Jan 24 02:30:48 PM PST 24
Finished Jan 24 02:36:30 PM PST 24
Peak memory 223860 kb
Host smart-1b0be801-fae0-490d-b669-cb179c318374
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651416223 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_c
orrupt_sig_fatal_chk.2651416223
Directory /workspace/8.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_kmac_err_chk.2068273566
Short name T244
Test name
Test status
Simulation time 655364145 ps
CPU time 14.17 seconds
Started Jan 24 03:47:09 PM PST 24
Finished Jan 24 03:47:26 PM PST 24
Peak memory 211208 kb
Host smart-fee99766-b831-44f9-b1d8-a1786dc14d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068273566 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_kmac_err_chk.2068273566
Directory /workspace/8.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_max_throughput_chk.53600483
Short name T401
Test name
Test status
Simulation time 20549030193 ps
CPU time 15.29 seconds
Started Jan 24 02:30:48 PM PST 24
Finished Jan 24 02:31:10 PM PST 24
Peak memory 211152 kb
Host smart-e551ce8b-07b7-4e92-a130-abb4e7dc7f7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=53600483 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_max_throughput_chk.53600483
Directory /workspace/8.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/8.rom_ctrl_smoke.868081594
Short name T163
Test name
Test status
Simulation time 11719936899 ps
CPU time 27.5 seconds
Started Jan 24 02:30:35 PM PST 24
Finished Jan 24 02:31:13 PM PST 24
Peak memory 213492 kb
Host smart-2df65094-dc2e-4ba2-9a42-a0445d17b6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868081594 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_smoke.868081594
Directory /workspace/8.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all.4269666124
Short name T157
Test name
Test status
Simulation time 1541708146 ps
CPU time 31.96 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:29 PM PST 24
Peak memory 213400 kb
Host smart-e1b523f7-90ec-4bba-b7de-542069450dd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269666124 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 8.rom_ctrl_stress_all.4269666124
Directory /workspace/8.rom_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.122067670
Short name T173
Test name
Test status
Simulation time 177849227219 ps
CPU time 1886.5 seconds
Started Jan 24 04:18:38 PM PST 24
Finished Jan 24 04:50:07 PM PST 24
Peak memory 243112 kb
Host smart-ac651968-2d00-484d-939f-3e949dff34ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122067670 -assert nopo
stproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rom_ctrl_stress_all_with_rand_reset.122067670
Directory /workspace/8.rom_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rom_ctrl_alert_test.2277742491
Short name T318
Test name
Test status
Simulation time 8615543898 ps
CPU time 17.17 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:14 PM PST 24
Peak memory 211096 kb
Host smart-e1983710-ee42-46dc-942c-54bcf5119fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277742491 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_alert_test.2277742491
Directory /workspace/9.rom_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.1444951596
Short name T373
Test name
Test status
Simulation time 52993446717 ps
CPU time 329.39 seconds
Started Jan 24 03:03:42 PM PST 24
Finished Jan 24 03:09:33 PM PST 24
Peak memory 226596 kb
Host smart-4d65aac6-94e6-4beb-81d4-da0b76ca834e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444951596 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrup
t_sig_fatal_chk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_c
orrupt_sig_fatal_chk.1444951596
Directory /workspace/9.rom_ctrl_corrupt_sig_fatal_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_kmac_err_chk.2451476617
Short name T271
Test name
Test status
Simulation time 5146182027 ps
CPU time 26.81 seconds
Started Jan 24 02:30:50 PM PST 24
Finished Jan 24 02:31:23 PM PST 24
Peak memory 211560 kb
Host smart-484a196b-e058-4a1e-8bc0-594d23a8a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451476617 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_kmac_err_chk.2451476617
Directory /workspace/9.rom_ctrl_kmac_err_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_max_throughput_chk.2467530237
Short name T9
Test name
Test status
Simulation time 3956977890 ps
CPU time 16.32 seconds
Started Jan 24 02:30:46 PM PST 24
Finished Jan 24 02:31:10 PM PST 24
Peak memory 211092 kb
Host smart-26f7048d-1ddd-41a1-82cf-cef71374be3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467530237 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_max_throughput_chk.2467530237
Directory /workspace/9.rom_ctrl_max_throughput_chk/latest

Test location /workspace/coverage/default/9.rom_ctrl_smoke.1498742429
Short name T10
Test name
Test status
Simulation time 22677804882 ps
CPU time 31.81 seconds
Started Jan 24 03:15:34 PM PST 24
Finished Jan 24 03:16:10 PM PST 24
Peak memory 213568 kb
Host smart-3d8cdafe-c130-4fc5-a23c-45b0ad802377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498742429 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rom_ctrl_smoke.1498742429
Directory /workspace/9.rom_ctrl_smoke/latest

Test location /workspace/coverage/default/9.rom_ctrl_stress_all.3066492378
Short name T372
Test name
Test status
Simulation time 2120575524 ps
CPU time 32.56 seconds
Started Jan 24 03:54:22 PM PST 24
Finished Jan 24 03:55:01 PM PST 24
Peak memory 212708 kb
Host smart-c8ae7267-c181-4974-a4a7-612665cef0d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066492378 -assert nopostproc +UVM_TESTNAME=rom_ctrl_base_test
+UVM_TEST_SEQ=rom_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 9.rom_ctrl_stress_all.3066492378
Directory /workspace/9.rom_ctrl_stress_all/latest
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